diff options
Diffstat (limited to 'meta-multimedia/recipes-mediacentre/xbmc/xbmc/0002-Revert-fixed-ios-Add-memory-barriers-to-atomic-Add-S.patch')
| -rw-r--r-- | meta-multimedia/recipes-mediacentre/xbmc/xbmc/0002-Revert-fixed-ios-Add-memory-barriers-to-atomic-Add-S.patch | 118 |
1 files changed, 56 insertions, 62 deletions
diff --git a/meta-multimedia/recipes-mediacentre/xbmc/xbmc/0002-Revert-fixed-ios-Add-memory-barriers-to-atomic-Add-S.patch b/meta-multimedia/recipes-mediacentre/xbmc/xbmc/0002-Revert-fixed-ios-Add-memory-barriers-to-atomic-Add-S.patch index e0a4037bc5..d3ae75e1c4 100644 --- a/meta-multimedia/recipes-mediacentre/xbmc/xbmc/0002-Revert-fixed-ios-Add-memory-barriers-to-atomic-Add-S.patch +++ b/meta-multimedia/recipes-mediacentre/xbmc/xbmc/0002-Revert-fixed-ios-Add-memory-barriers-to-atomic-Add-S.patch @@ -24,74 +24,68 @@ The build (OpenEmbedded `angstrom-2010.x` for `MACHINE = "beagleboard") fails wi make[1]: *** [Atomics.o] Error 1 make[1]: Leaving directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+9a10c48710df79118e39e9b3bb0a15bf1fe694d1/git/xbmc/threads' make: *** [xbmc/threads/threads.a] Error 2 ---- - xbmc/threads/Atomics.cpp | 8 -------- - 1 files changed, 0 insertions(+), 8 deletions(-) -diff --git a/xbmc/threads/Atomics.cpp b/xbmc/threads/Atomics.cpp -index 5b09f18..0a98a7e 100644 ---- a/xbmc/threads/Atomics.cpp -+++ b/xbmc/threads/Atomics.cpp -@@ -194,14 +194,12 @@ long AtomicIncrement(volatile long* pAddr) - { +Index: git/xbmc/threads/Atomics.cpp +=================================================================== +--- git.orig/xbmc/threads/Atomics.cpp ++++ git/xbmc/threads/Atomics.cpp +@@ -168,14 +166,12 @@ long AtomicIncrement(volatile long* pAdd + #elif defined(__arm__) && !defined(__ARM_ARCH_5__) register long val; asm volatile ( -- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after - "1: \n" - "ldrex %0, [%1] \n" // (val = *pAddr) - "add %0, #1 \n" // (val += 1) - "strex r1, %0, [%1] \n" - "cmp r1, #0 \n" - "bne 1b \n" -- "dmb ish \n" // Memory barrier. - : "=&r" (val) - : "r"(pAddr) - : "r1" -@@ -273,14 +271,12 @@ long AtomicAdd(volatile long* pAddr, long amount) - { +- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after + "1: \n" + "ldrex %0, [%1] \n" // (val = *pAddr) + "add %0, #1 \n" // (val += 1) + "strex r1, %0, [%1] \n" + "cmp r1, #0 \n" + "bne 1b \n" +- "dmb ish \n" // Memory barrier. + : "=&r" (val) + : "r"(pAddr) + : "r1" +@@ -246,14 +242,12 @@ long AtomicAdd(volatile long* pAddr, lon + #elif defined(__arm__) && !defined(__ARM_ARCH_5__) register long val; asm volatile ( -- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after - "1: \n" - "ldrex %0, [%1] \n" // (val = *pAddr) - "add %0, %2 \n" // (val += amount) - "strex r1, %0, [%1] \n" - "cmp r1, #0 \n" - "bne 1b \n" -- "dmb ish \n" // Memory barrier. - : "=&r" (val) - : "r"(pAddr), "r"(amount) - : "r1" -@@ -351,14 +347,12 @@ long AtomicDecrement(volatile long* pAddr) - { +- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after + "1: \n" + "ldrex %0, [%1] \n" // (val = *pAddr) + "add %0, %2 \n" // (val += amount) + "strex r1, %0, [%1] \n" + "cmp r1, #0 \n" + "bne 1b \n" +- "dmb ish \n" // Memory barrier. + : "=&r" (val) + : "r"(pAddr), "r"(amount) + : "r1" +@@ -324,14 +318,12 @@ long AtomicDecrement(volatile long* pAdd + #elif defined(__arm__) register long val; asm volatile ( -- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after - "1: \n" - "ldrex %0, [%1] \n" // (val = *pAddr) - "sub %0, #1 \n" // (val -= 1) - "strex r1, %0, [%1] \n" - "cmp r1, #0 \n" - "bne 1b \n" -- "dmb ish \n" // Memory barrier. - : "=&r" (val) - : "r"(pAddr) - : "r1" -@@ -431,14 +425,12 @@ long AtomicSubtract(volatile long* pAddr, long amount) - { +- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after + "1: \n" + "ldrex %0, [%1] \n" // (val = *pAddr) + "sub %0, #1 \n" // (val -= 1) + "strex r1, %0, [%1] \n" + "cmp r1, #0 \n" + "bne 1b \n" +- "dmb ish \n" // Memory barrier. + : "=&r" (val) + : "r"(pAddr) + : "r1" +@@ -403,14 +395,12 @@ long AtomicSubtract(volatile long* pAddr + #elif defined(__arm__) register long val; asm volatile ( -- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after - "1: \n" - "ldrex %0, [%1] \n" // (val = *pAddr) - "sub %0, %2 \n" // (val -= amount) - "strex r1, %0, [%1] \n" - "cmp r1, #0 \n" - "bne 1b \n" -- "dmb ish \n" // Memory barrier. - : "=&r" (val) - : "r"(pAddr), "r"(amount) - : "r1" --- -1.7.2.5 - +- "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after + "1: \n" + "ldrex %0, [%1] \n" // (val = *pAddr) + "sub %0, %2 \n" // (val -= amount) + "strex r1, %0, [%1] \n" + "cmp r1, #0 \n" + "bne 1b \n" +- "dmb ish \n" // Memory barrier. + : "=&r" (val) + : "r"(pAddr), "r"(amount) + : "r1" |