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-rw-r--r--meta-oe/recipes-extended/mozjs/mozjs/0001-fix-compiling-failure-on-mips64-n32-bsp.patch79
1 files changed, 79 insertions, 0 deletions
diff --git a/meta-oe/recipes-extended/mozjs/mozjs/0001-fix-compiling-failure-on-mips64-n32-bsp.patch b/meta-oe/recipes-extended/mozjs/mozjs/0001-fix-compiling-failure-on-mips64-n32-bsp.patch
new file mode 100644
index 0000000000..bc1af3c702
--- /dev/null
+++ b/meta-oe/recipes-extended/mozjs/mozjs/0001-fix-compiling-failure-on-mips64-n32-bsp.patch
@@ -0,0 +1,79 @@
+From 5ad700c92224193bfc789f7d53af38fc6f8b8904 Mon Sep 17 00:00:00 2001
+From: Hongxu Jia <hongxu.jia@windriver.com>
+Date: Thu, 19 Jul 2018 17:31:35 +0800
+Subject: [PATCH] fix compiling failure on mips64-n32 bsp
+
+- Tweak mips64-n32 with mips32
+
+- The toolchain of mips64-n32 supports both of macro
+ `__mips64' and `__mips__', but 32bit is required here.
+
+- N32 uses 64-bit registers but restricts addresses to 32 bits.
+ https://www.linux-mips.org/pub/linux/mips/doc/ABI/MIPS-N32-ABI-Handbook.pdf
+ Table 2-1 specifies the use of registers in n32 and native 64-bit mode.
+ From the table, N32 and N64 have the same registers
+
+Upstream-Status: Inappropriate [oe specific]
+
+Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
+---
+ build/moz.configure/init.configure | 5 ++++-
+ js/src/jit/mips-shared/Architecture-mips-shared.h | 4 +++-
+ python/mozbuild/mozbuild/configure/constants.py | 2 +-
+ 3 files changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/build/moz.configure/init.configure b/build/moz.configure/init.configure
+index 6fe6591..a77b46c 100644
+--- a/build/moz.configure/init.configure
++++ b/build/moz.configure/init.configure
+@@ -357,7 +357,10 @@ def split_triplet(triplet):
+ canonical_cpu = 'mips32'
+ endianness = 'little' if 'el' in cpu else 'big'
+ elif cpu in ('mips64', 'mips64el'):
+- canonical_cpu = 'mips64'
++ if 'n32' in triplet:
++ canonical_cpu = 'mips32'
++ else:
++ canonical_cpu = 'mips64'
+ endianness = 'little' if 'el' in cpu else 'big'
+ elif cpu.startswith('aarch64'):
+ canonical_cpu = 'aarch64'
+diff --git a/js/src/jit/mips-shared/Architecture-mips-shared.h b/js/src/jit/mips-shared/Architecture-mips-shared.h
+index 7afe305..c6e29dc 100644
+--- a/js/src/jit/mips-shared/Architecture-mips-shared.h
++++ b/js/src/jit/mips-shared/Architecture-mips-shared.h
+@@ -24,6 +24,8 @@
+ #define USES_O32_ABI
+ #elif (defined(_MIPS_SIM) && (_MIPS_SIM == _ABI64)) || defined(JS_SIMULATOR_MIPS64)
+ #define USES_N64_ABI
++#elif (defined(_MIPS_SIM) && (_MIPS_SIM == _ABIN32))
++#define USES_N32_ABI
+ #else
+ #error "Unsupported ABI"
+ #endif
+@@ -91,7 +93,7 @@ class Registers
+ ta1 = t5,
+ ta2 = t6,
+ ta3 = t7,
+-#elif defined(USES_N64_ABI)
++#elif defined(USES_N64_ABI) || defined(USES_N32_ABI)
+ a4 = r8,
+ a5 = r9,
+ a6 = r10,
+diff --git a/python/mozbuild/mozbuild/configure/constants.py b/python/mozbuild/mozbuild/configure/constants.py
+index dfc7cf8..27f83ab 100644
+--- a/python/mozbuild/mozbuild/configure/constants.py
++++ b/python/mozbuild/mozbuild/configure/constants.py
+@@ -83,8 +83,8 @@ CPU_preprocessor_checks = OrderedDict((
+ ('hppa', '__hppa__'),
+ ('sparc64', '__sparc__ && __arch64__'),
+ ('sparc', '__sparc__'),
+- ('mips64', '__mips64'),
+ ('mips32', '__mips__'),
++ ('mips64', '__mips64'),
+ ))
+
+ assert sorted(CPU_preprocessor_checks.keys()) == sorted(CPU.POSSIBLE_VALUES)
+--
+2.7.4
+