357 files changed, 167729 insertions, 0 deletions

diff --git a/toolchain-layer/recipes-devtools/gcc/files/canadian-build-modules-configure.patch b/toolchain-layer/recipes-devtools/gcc/files/canadian-build-modules-configure.patch
new file mode 100644
index 0000000000..8aede105c5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/canadian-build-modules-configure.patch
@@ -0,0 +1,22 @@
+diff -urN gcc-4.2.2-orig/gcc/configure gcc-4.2.2/gcc/configure
+--- gcc-4.2.2-orig/gcc/configure	2008-08-31 23:10:56.000000000 +0200
++++ gcc-4.2.2/gcc/configure	2008-08-31 23:03:02.000000000 +0200
+@@ -12716,6 +12716,7 @@
+ 	esac
+ 	saved_CFLAGS="${CFLAGS}"
+ 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
++	CPP="${CPP_FOR_BUILD}" CPPFLAGS="${CPPFLAGS_FOR_BUILD}" \
+ 	CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
+ 		--enable-languages=${enable_languages-all} \
+ 		--target=$target_alias --host=$build_alias --build=$build_alias
+diff -urN gcc-4.2.2-orig/gcc/configure.ac gcc-4.2.2/gcc/configure.ac
+--- gcc-4.2.2-orig/gcc/configure.ac	2008-08-31 23:10:53.000000000 +0200
++++ gcc-4.2.2/gcc/configure.ac	2008-08-31 23:03:29.000000000 +0200
+@@ -1490,6 +1490,7 @@
+ 	esac
+ 	saved_CFLAGS="${CFLAGS}"
+ 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
++	CPP="${CPP_FOR_BUILD}" CPPFLAGS="${CPPFLAGS_FOR_BUILD}" \
+ 	${realsrcdir}/configure \
+ 		--enable-languages=${enable_languages-all} \
+ 		--target=$target_alias --host=$build_alias --build=$build_alias
diff --git a/toolchain-layer/recipes-devtools/gcc/files/gcc-4.3.3-fix-EXTRA_BUILD.patch b/toolchain-layer/recipes-devtools/gcc/files/gcc-4.3.3-fix-EXTRA_BUILD.patch
new file mode 100644
index 0000000000..8a2a4c4040
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/gcc-4.3.3-fix-EXTRA_BUILD.patch
@@ -0,0 +1,12 @@
+Index: gcc-4.3.3/Makefile.in
+===================================================================
+--- gcc-4.3.3.orig/Makefile.in	2010-06-16 18:04:38.379008150 +0400
++++ gcc-4.3.3/Makefile.in	2010-06-16 18:05:29.115006261 +0400
+@@ -148,6 +148,7 @@
+ # built for the build system to override those in BASE_FLAGS_TO_PASSS.
+ EXTRA_BUILD_FLAGS = \
+ 	CFLAGS="$(CFLAGS_FOR_BUILD)" \
++	LIBCFLAGS="$(CFLAGS_FOR_BUILD)" \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"
+ 
+ # This is the list of directories to built for the host system.
diff --git a/toolchain-layer/recipes-devtools/gcc/files/gcc-4.3.x-fix-EXTRA_BUILD.patch b/toolchain-layer/recipes-devtools/gcc/files/gcc-4.3.x-fix-EXTRA_BUILD.patch
new file mode 100644
index 0000000000..b3753364f8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/gcc-4.3.x-fix-EXTRA_BUILD.patch
@@ -0,0 +1,13 @@
+Index: gcc-4.3.1/Makefile.in
+===================================================================
+--- gcc-4.3.1.orig/Makefile.in	2010-07-07 13:08:44.000000000 +0200
++++ gcc-4.3.1/Makefile.in	2010-07-07 13:11:59.246625709 +0200
+@@ -149,7 +149,7 @@
+ EXTRA_BUILD_FLAGS = \
+ 	CFLAGS="$(CFLAGS_FOR_BUILD)" \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)" \
+-	LIBCFLAGS=""
++        LIBCFLAGS="$(CFLAGS_FOR_BUILD)"
+ 
+ # This is the list of directories to built for the host system.
+ SUBDIRS = @configdirs@
diff --git a/toolchain-layer/recipes-devtools/gcc/files/gcc-posix-open-fix.patch b/toolchain-layer/recipes-devtools/gcc/files/gcc-posix-open-fix.patch
new file mode 100644
index 0000000000..99f813e866
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/gcc-posix-open-fix.patch
@@ -0,0 +1,11 @@
+--- gcc-3.4.6/gcc/collect2.c	2008-10-04 18:17:17.796750393 +0400
++++ gcc-3.4.6/gcc/collect2.new	2008-10-04 18:24:10.120748711 +0400
+@@ -1534,7 +1534,7 @@ collect_execute (const char *prog, char 
+   if (redir)
+     {
+       /* Open response file.  */
+-      redir_handle = open (redir, O_WRONLY | O_TRUNC | O_CREAT);
++      redir_handle = open (redir, O_WRONLY | O_TRUNC | O_CREAT, S_IWUSR);
+ 
+       /* Duplicate the stdout and stderr file handles
+ 	 so they can be restored later.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/files/gcc4-mtune-compat.patch b/toolchain-layer/recipes-devtools/gcc/files/gcc4-mtune-compat.patch
new file mode 100644
index 0000000000..0da2811d37
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/gcc4-mtune-compat.patch
@@ -0,0 +1,14 @@
+Patch for gcc3 to support gcc4-compatible (and consistent) values for -mtune= option.
+
+--- gcc-3.4.4/gcc/config/arm/arm.c.org	2007-12-15 23:58:35.000000000 +0200
++++ gcc-3.4.4/gcc/config/arm/arm.c	2007-12-16 00:20:39.000000000 +0200
+@@ -432,7 +432,9 @@
+   {"arm10tdmi",	                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED             | FL_ARCH5 },
+   {"arm1020t",	                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED             | FL_ARCH5 },
+   {"arm926ejs",                          FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
++  {"arm926ej-s",                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
+   {"arm1026ejs",                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
++  {"arm1026ej-s",                        FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
+   {"xscale",                             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
+   {"iwmmxt",                             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
+   /* V6 Architecture Processors */
diff --git a/toolchain-layer/recipes-devtools/gcc/files/gfortran-4.3.x.patch b/toolchain-layer/recipes-devtools/gcc/files/gfortran-4.3.x.patch
new file mode 100644
index 0000000000..0c42851ce1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/gfortran-4.3.x.patch
@@ -0,0 +1,40 @@
+The patch below fixes a crash building libgfortran on arm-linux-gnueabi.
+
+This target doesn't really have a 128-bit integer type, however it does use 
+TImode to represent the return value of certain special ABI defined library 
+functions. This results in type_for_size(TImode) being called.
+
+Because TImode deosn't correspond to any gfortran integer kind 
+gfc_type_for_size returns NULL and we segfault shortly after.
+
+The patch below fixes this by making gfc_type_for_size handle TImode in the 
+same way as the C frontend.
+
+Tested on x86_64-linux and arm-linux-gnueabi.
+Applied to trunk.
+
+Paul
+
+2007-05-15  Paul Brook  <paul@codesourcery.com>
+
+	gcc/fortran/
+	* trans-types.c (gfc_type_for_size): Handle signed TImode.
+
+Index: gcc-4.2.1/gcc/fortran/trans-types.c
+===================================================================
+--- gcc-4.2.1/gcc/fortran/trans-types.c	(revision 170435)
++++ gcc-4.2.1/gcc/fortran/trans-types.c	(working copy)
+@@ -1800,6 +1800,13 @@ gfc_type_for_size (unsigned bits, int un
+ 	  if (type && bits == TYPE_PRECISION (type))
+ 	    return type;
+ 	}
++
++      /* Handle TImode as a special case because it is used by some backends
++         (eg. ARM) even though it is not available for normal use.  */
++#if HOST_BITS_PER_WIDE_INT >= 65
++      if (bits == TYPE_PRECISION (intTI_type_node))
++	return intTI_type_node;
++#endif
+     }
+   else
+     {
diff --git a/toolchain-layer/recipes-devtools/gcc/files/gfortran.patch b/toolchain-layer/recipes-devtools/gcc/files/gfortran.patch
new file mode 100644
index 0000000000..96905e5d7d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/gfortran.patch
@@ -0,0 +1,40 @@
+The patch below fixes a crash building libgfortran on arm-linux-gnueabi.
+
+This target doesn't really have a 128-bit integer type, however it does use 
+TImode to represent the return value of certain special ABI defined library 
+functions. This results in type_for_size(TImode) being called.
+
+Because TImode deosn't correspond to any gfortran integer kind 
+gfc_type_for_size returns NULL and we segfault shortly after.
+
+The patch below fixes this by making gfc_type_for_size handle TImode in the 
+same way as the C frontend.
+
+Tested on x86_64-linux and arm-linux-gnueabi.
+Applied to trunk.
+
+Paul
+
+2007-05-15  Paul Brook  <paul@codesourcery.com>
+
+	gcc/fortran/
+	* trans-types.c (gfc_type_for_size): Handle signed TImode.
+
+Index: gcc-4.2.1/gcc/fortran/trans-types.c
+===================================================================
+--- gcc-4.2.1/gcc/fortran/trans-types.c	(revision 170435)
++++ gcc-4.2.1/gcc/fortran/trans-types.c	(working copy)
+@@ -1800,6 +1800,13 @@ gfc_type_for_size (unsigned bits, int un
+ 	  if (type && bits == TYPE_PRECISION (type))
+ 	    return type;
+ 	}
++
++      /* Handle TImode as a special case because it is used by some backends
++         (eg. ARM) even though it is not available for normal use.  */
++#if HOST_BITS_PER_WIDE_INT >= 64
++      if (bits == TYPE_PRECISION (intTI_type_node))
++	return intTI_type_node;
++#endif
+     }
+   else
+     {
diff --git a/toolchain-layer/recipes-devtools/gcc/files/pr22133-mingw-path-fixup.patch b/toolchain-layer/recipes-devtools/gcc/files/pr22133-mingw-path-fixup.patch
new file mode 100644
index 0000000000..429e9ffd0c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/pr22133-mingw-path-fixup.patch
@@ -0,0 +1,29 @@
+diff -rupN gcc-4.2.orig/gcc/c-incpath.c gcc-4.2/gcc/c-incpath.c
+--- gcc-4.2.orig/gcc/c-incpath.c	2007-09-01 11:28:30.000000000 -0400
++++ gcc-4.2/gcc/c-incpath.c	2008-08-17 16:56:01.000000000 -0400
+@@ -340,13 +340,18 @@ add_path (char *path, int chain, int cxx
+   cpp_dir *p;
+ 
+ #if defined (HAVE_DOS_BASED_FILE_SYSTEM)
+-  /* Convert all backslashes to slashes.  The native CRT stat()
+-     function does not recognize a directory that ends in a backslash
+-     (unless it is a drive root dir, such "c:\").  Forward slashes,
+-     trailing or otherwise, cause no problems for stat().  */
+-  char* c;
+-  for (c = path; *c; c++)
+-    if (*c == '\\') *c = '/';
++  /* Remove unnecessary trailing slashes.  On some versions of MS
++     Windows, trailing  _forward_ slashes cause no problems for stat().
++     On newer versions, stat() does not recognise a directory that ends
++     in a '\\' or '/', unless it is a drive root dir, such as "c:/",
++     where it is obligatory.  */
++  int pathlen = strlen (path);
++  char* end = path + pathlen - 1;
++  /* Preserve the lead '/' or lead "c:/".  */
++  char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1);
++  
++  for (; end > start && IS_DIR_SEPARATOR (*end); end--)
++    *end = 0;
+ #endif
+ 
+   p = XNEW (cpp_dir);
diff --git a/toolchain-layer/recipes-devtools/gcc/files/pr33281-mingw-host-fragment.patch b/toolchain-layer/recipes-devtools/gcc/files/pr33281-mingw-host-fragment.patch
new file mode 100644
index 0000000000..e16fb4464a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/pr33281-mingw-host-fragment.patch
@@ -0,0 +1,38 @@
+---
+ config/mh-mingw |    3 +++
+ configure       |    1 +
+ configure.in    |    1 +
+ 3 files changed, 5 insertions(+)
+
+Index: gcc-4.2.3/config/mh-mingw
+===================================================================
+--- /dev/null
++++ gcc-4.2.3/config/mh-mingw
+@@ -0,0 +1,3 @@
++# Add -D__USE_MINGW_ACCESS to enable the built compiler to work on Windows
++# Vista (see PR33281 for details).
++BOOT_CFLAGS += -D__USE_MINGW_ACCESS
+Index: gcc-4.2.3/configure.in
+===================================================================
+--- gcc-4.2.3.orig/configure.in
++++ gcc-4.2.3/configure.in
+@@ -929,6 +929,7 @@ case "${host}" in
+     host_makefile_frag="config/mh-cygwin"
+     ;;
+   *-mingw32*)
++    host_makefile_frag="config/mh-mingw"
+     ;;
+   *-interix*)
+     host_makefile_frag="config/mh-interix"
+Index: gcc-4.2.3/configure
+===================================================================
+--- gcc-4.2.3.orig/configure
++++ gcc-4.2.3/configure
+@@ -1769,6 +1769,7 @@ case "${host}" in
+     host_makefile_frag="config/mh-cygwin"
+     ;;
+   *-mingw32*)
++    host_makefile_frag="config/mh-mingw"
+     ;;
+   *-interix*)
+     host_makefile_frag="config/mh-interix"
diff --git a/toolchain-layer/recipes-devtools/gcc/files/pr35916-mingw-__USE_MINGW_ACCESS-everywhere.patch b/toolchain-layer/recipes-devtools/gcc/files/pr35916-mingw-__USE_MINGW_ACCESS-everywhere.patch
new file mode 100644
index 0000000000..faf44c27f9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/files/pr35916-mingw-__USE_MINGW_ACCESS-everywhere.patch
@@ -0,0 +1,13 @@
+---
+ config/mh-mingw |    1 +
+ 1 file changed, 1 insertion(+)
+
+Index: gcc-4.2.3/config/mh-mingw
+===================================================================
+--- gcc-4.2.3.orig/config/mh-mingw
++++ gcc-4.2.3/config/mh-mingw
+@@ -1,3 +1,4 @@
+ # Add -D__USE_MINGW_ACCESS to enable the built compiler to work on Windows
+ # Vista (see PR33281 for details).
+ BOOT_CFLAGS += -D__USE_MINGW_ACCESS
++CFLAGS += -D__USE_MINGW_ACCESS
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc b/toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc
new file mode 100644
index 0000000000..b23b3224b3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc
@@ -0,0 +1,273 @@
+require recipes-devtools/gcc/gcc-common.inc
+ARM_INSTRUCTION_SET = "arm"
+
+DEPENDS =+ "mpfr gmp libmpc elfutils"
+NATIVEDEPS = "mpfr-native gmp-native gettext-native libmpc-native elfutils-native"
+
+LICENSE="GCC RUNTIME LIBRARY EXCEPTION & GPLv2 & GPLv3 & LGPLv2.1 & LGPLv3"
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
+                    file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
+                    file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
+                    file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \
+                    file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8"
+
+
+PV = "4.5"
+PR = "r47"
+
+# BINV should be incremented after updating to a revision
+# after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made
+# the value will be minor-release+1 e.g. if minor release was
+# 4.5.1 then the value below will be 2 which will mean 4.5.2
+# which will be next minor release and so on.
+
+BINV = "${PV}.4"
+SRCREV = "184907"
+BRANCH = "gcc-4_5-branch"
+PR_append = "+svnr${SRCPV}"
+
+SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
+       file://gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \
+       file://100-uclibc-conf.patch \
+       file://gcc-uclibc-locale-ctype_touplow_t.patch \
+       file://cache-amnesia.patch \
+       file://gcc-flags-for-build.patch \
+       file://libstdc++-emit-__cxa_end_cleanup-in-text.patch \
+       file://Makefile.in.patch \
+       file://gcc-armv4-pass-fix-v4bx-to-ld.patch \
+       file://sh4-multilib.patch \
+       file://arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch \
+       \
+       file://linaro/gcc-4.5-linaro-r99297.patch \
+       file://linaro/gcc-4.5-linaro-r99298.patch \
+       file://linaro/gcc-4.5-linaro-r99299.patch \
+       file://linaro/gcc-4.5-linaro-r99300.patch \
+       file://linaro/gcc-4.5-linaro-r99301.patch \
+       file://linaro/gcc-4.5-linaro-r99302.patch \
+       file://linaro/gcc-4.5-linaro-r99303.patch \
+       file://linaro/gcc-4.5-linaro-r99304.patch \
+       file://linaro/gcc-4.5-linaro-r99305.patch \
+       file://linaro/gcc-4.5-linaro-r99306.patch \
+       file://linaro/gcc-4.5-linaro-r99307.patch \
+       file://linaro/gcc-4.5-linaro-r99308.patch \
+       file://linaro/gcc-4.5-linaro-r99310.patch \
+       file://linaro/gcc-4.5-linaro-r99312.patch \
+       file://linaro/gcc-4.5-linaro-r99313.patch \
+       file://linaro/gcc-4.5-linaro-r99314.patch \
+       file://linaro/gcc-4.5-linaro-r99315.patch \
+       file://linaro/gcc-4.5-linaro-r99316.patch \
+       file://linaro/gcc-4.5-linaro-r99318.patch \
+       file://linaro/gcc-4.5-linaro-r99319.patch \
+       file://linaro/gcc-4.5-linaro-r99320.patch \
+       file://linaro/gcc-4.5-linaro-r99321.patch \
+       file://linaro/gcc-4.5-linaro-r99322.patch \
+       file://linaro/gcc-4.5-linaro-r99323.patch \
+       file://linaro/gcc-4.5-linaro-r99324.patch \
+       file://linaro/gcc-4.5-linaro-r99325.patch \
+       file://linaro/gcc-4.5-linaro-r99326.patch \
+       file://linaro/gcc-4.5-linaro-r99327.patch \
+       file://linaro/gcc-4.5-linaro-r99332.patch \
+       file://linaro/gcc-4.5-linaro-r99335.patch \
+       file://linaro/gcc-4.5-linaro-r99336.patch \
+       file://linaro/gcc-4.5-linaro-r99337.patch \
+       file://linaro/gcc-4.5-linaro-r99338.patch \
+       file://linaro/gcc-4.5-linaro-r99339.patch \
+       file://linaro/gcc-4.5-linaro-r99340.patch \
+       file://linaro/gcc-4.5-linaro-r99341.patch \
+       file://linaro/gcc-4.5-linaro-r99342.patch \
+       file://linaro/gcc-4.5-linaro-r99343.patch \
+       file://linaro/gcc-4.5-linaro-r99344.patch \
+       file://linaro/gcc-4.5-linaro-r99345.patch \
+       file://linaro/gcc-4.5-linaro-r99346.patch \
+       file://linaro/gcc-4.5-linaro-r99348.patch \
+       file://linaro/gcc-4.5-linaro-r99349.patch \
+       file://linaro/gcc-4.5-linaro-r99351.patch \
+       file://linaro/gcc-4.5-linaro-r99352.patch \
+       file://linaro/gcc-4.5-linaro-r99353.patch \
+       file://linaro/gcc-4.5-linaro-r99354.patch \
+       file://linaro/gcc-4.5-linaro-r99355.patch \
+       file://linaro/gcc-4.5-linaro-r99356.patch \
+       file://linaro/gcc-4.5-linaro-r99357.patch \
+       file://linaro/gcc-4.5-linaro-r99358.patch \
+       file://linaro/gcc-4.5-linaro-r99359.patch \
+       file://linaro/gcc-4.5-linaro-r99360.patch \
+       file://linaro/gcc-4.5-linaro-r99361.patch \
+       file://linaro/gcc-4.5-linaro-r99363.patch \
+       file://linaro/gcc-4.5-linaro-r99364.patch \
+       file://linaro/gcc-4.5-linaro-r99365.patch \
+       file://linaro/gcc-4.5-linaro-r99366.patch \
+       file://linaro/gcc-4.5-linaro-r99367.patch \
+       file://linaro/gcc-4.5-linaro-r99368.patch \
+       file://linaro/gcc-4.5-linaro-r99369.patch \
+       file://linaro/gcc-4.5-linaro-r99371.patch \
+       file://linaro/gcc-4.5-linaro-r99372.patch \
+       file://linaro/gcc-4.5-linaro-r99373.patch \
+       file://linaro/gcc-4.5-linaro-r99374.patch \
+       file://linaro/gcc-4.5-linaro-r99375.patch \
+       file://linaro/gcc-4.5-linaro-r99376.patch \
+       file://linaro/gcc-4.5-linaro-r99377.patch \
+       file://linaro/gcc-4.5-linaro-r99378.patch \
+       file://linaro/gcc-4.5-linaro-r99379.patch \
+       file://linaro/gcc-4.5-linaro-r99380.patch \
+       file://linaro/gcc-4.5-linaro-r99381.patch \
+       file://linaro/gcc-4.5-linaro-r99383.patch \
+       file://linaro/gcc-4.5-linaro-r99384.patch \
+       file://linaro/gcc-4.5-linaro-r99385.patch \
+       file://linaro/gcc-4.5-linaro-r99388.patch \
+       file://linaro/gcc-4.5-linaro-r99391.patch \
+       file://linaro/gcc-4.5-linaro-r99392.patch \
+       file://linaro/gcc-4.5-linaro-r99393.patch \
+       file://linaro/gcc-4.5-linaro-r99395.patch \
+       file://linaro/gcc-4.5-linaro-r99396.patch \
+       file://linaro/gcc-4.5-linaro-r99397.patch \
+       file://linaro/gcc-4.5-linaro-r99398.patch \
+       file://linaro/gcc-4.5-linaro-r99402.patch \
+       file://linaro/gcc-4.5-linaro-r99403.patch \
+       file://linaro/gcc-4.5-linaro-r99404.patch \
+       file://linaro/gcc-4.5-linaro-r99405.patch \
+       file://linaro/gcc-4.5-linaro-r99406.patch \
+       file://linaro/gcc-4.5-linaro-r99407.patch \
+       file://linaro/gcc-4.5-linaro-r99408.patch \
+       file://linaro/gcc-4.5-linaro-r99409.patch \
+       file://linaro/gcc-4.5-linaro-r99410.patch \
+       file://linaro/gcc-4.5-linaro-r99411.patch \
+       file://linaro/gcc-4.5-linaro-r99412.patch \
+       file://linaro/gcc-4.5-linaro-r99413.patch \
+       file://linaro/gcc-4.5-linaro-r99415.patch \
+       file://linaro/gcc-4.5-linaro-r99416.patch \
+       file://linaro/gcc-4.5-linaro-r99417.patch \
+       file://linaro/gcc-4.5-linaro-r99418.patch \
+       file://linaro/gcc-4.5-linaro-r99419.patch \
+       file://linaro/gcc-4.5-linaro-r99420.patch \
+       file://linaro/gcc-4.5-linaro-r99421.patch \
+       file://linaro/gcc-4.5-linaro-r99423.patch \
+       file://linaro/gcc-4.5-linaro-r99424.patch \
+       file://linaro/gcc-4.5-linaro-r99425.patch \
+       file://linaro/gcc-4.5-linaro-r99426.patch \
+       file://linaro/gcc-4.5-linaro-r99429.patch \
+       file://linaro/gcc-4.5-linaro-r99432.patch \
+       file://linaro/gcc-4.5-linaro-r99433.patch \
+       file://linaro/gcc-4.5-linaro-r99434.patch \
+       file://linaro/gcc-4.5-linaro-r99435.patch \
+       file://linaro/gcc-4.5-linaro-r99436.patch \
+       file://linaro/gcc-4.5-linaro-r99437.patch \
+       file://linaro/gcc-4.5-linaro-r99439.patch \
+       file://linaro/gcc-4.5-linaro-r99440.patch \
+       file://linaro/gcc-4.5-linaro-r99441.patch \
+       file://linaro/gcc-4.5-linaro-r99442.patch \
+       file://linaro/gcc-4.5-linaro-r99443.patch \
+       file://linaro/gcc-4.5-linaro-r99444.patch \
+       file://linaro/gcc-4.5-linaro-r99449.patch \
+       file://linaro/gcc-4.5-linaro-r99450.patch \
+       file://linaro/gcc-4.5-linaro-r99451.patch \
+       file://linaro/gcc-4.5-linaro-r99452.patch \
+       file://linaro/gcc-4.5-linaro-r99453.patch \
+       file://linaro/gcc-4.5-linaro-r99454.patch \
+       file://linaro/gcc-4.5-linaro-r99455.patch \
+       file://linaro/gcc-4.5-linaro-r99464.patch \
+       file://linaro/gcc-4.5-linaro-r99465.patch \
+       file://linaro/gcc-4.5-linaro-r99466.patch \
+       file://linaro/gcc-4.5-linaro-r99468.patch \
+       file://linaro/gcc-4.5-linaro-r99473.patch \
+       file://linaro/gcc-4.5-linaro-r99475.patch \
+       file://linaro/gcc-4.5-linaro-r99478.patch \
+       file://linaro/gcc-4.5-linaro-r99479.patch \
+       file://linaro/gcc-4.5-linaro-r99480.patch \
+       file://linaro/gcc-4.5-linaro-r99483.patch \
+       file://linaro/gcc-4.5-linaro-r99488.patch \
+       file://linaro/gcc-4.5-linaro-r99489.patch \
+       file://linaro/gcc-4.5-linaro-r99494.patch \
+       file://linaro/gcc-4.5-linaro-r99495.patch \
+       file://linaro/gcc-4.5-linaro-r99498.patch \
+       file://linaro/gcc-4.5-linaro-r99502.patch \
+       file://linaro/gcc-4.5-linaro-r99503.patch \
+       file://linaro/gcc-4.5-linaro-r99504.patch \
+       file://linaro/gcc-4.5-linaro-r99506.patch \
+       file://linaro/gcc-4.5-linaro-r99507.patch \
+       file://linaro/gcc-4.5-linaro-r99510.patch \
+       file://linaro/gcc-4.5-linaro-r99511.patch \
+       file://linaro/gcc-4.5-linaro-r99514.patch \
+       file://linaro/gcc-4.5-linaro-r99516.patch \
+       file://linaro/gcc-4.5-linaro-r99519.patch \
+       file://linaro/gcc-4.5-linaro-r99521.patch \
+       file://linaro/gcc-4.5-linaro-r99522.patch \
+       file://linaro/gcc-4.5-linaro-r99523.patch \
+       file://linaro/gcc-4.5-linaro-r99524.patch \
+       file://linaro/gcc-4.5-linaro-r99525.patch \
+       file://linaro/gcc-4.5-linaro-r99528.patch \
+       file://linaro/gcc-4.5-linaro-r99529.patch \
+       file://linaro/gcc-4.5-linaro-r99530.patch \
+       file://linaro/gcc-4.5-linaro-r99531.patch \
+       file://linaro/gcc-4.5-linaro-r99532.patch \
+       file://linaro/gcc-4.5-linaro-r99533.patch \
+       file://linaro/gcc-4.5-linaro-r99534.patch \
+       file://linaro/gcc-4.5-linaro-r99536.patch \
+       file://linaro/gcc-4.5-linaro-r99537.patch \
+       file://linaro/gcc-4.5-linaro-r99540.patch \
+       file://linaro/gcc-4.5-linaro-r99548.patch \
+       file://linaro/gcc-4.5-linaro-r99549.patch \
+	\
+       file://more-epilogues.patch \
+       file://gcc-scalar-widening-pr45847.patch \
+       file://gcc-arm-volatile-bitfield-fix.patch \
+       \
+       file://fedora/gcc43-c++-builtin-redecl.patch;striplevel=0 \
+       file://fedora/gcc43-ia64-libunwind.patch;striplevel=0 \
+       file://fedora/gcc43-java-nomulti.patch;striplevel=0 \
+       file://fedora/gcc43-ppc32-retaddr.patch;striplevel=0 \
+       file://fedora/gcc43-pr32139.patch;striplevel=0 \
+       file://fedora/gcc43-pr33763.patch;striplevel=0 \
+       file://fedora/gcc43-rh330771.patch;striplevel=0 \
+       file://fedora/gcc43-rh341221.patch;striplevel=0 \
+       file://fedora/gcc43-java-debug-iface-type.patch;striplevel=0 \
+       file://fedora/gcc43-i386-libgomp.patch;striplevel=0 \
+       file://fedora/gcc45-no-add-needed.patch;striplevel=0 \
+       file://optional_libstdc.patch \
+       file://64bithack.patch \
+       file://COLLECT_GCC_OPTIONS.patch \
+       file://gcc-poison-dir-extend.patch \
+       file://gcc-poison-parameters.patch \
+       file://gcc-ppc-config-fix.patch \
+       file://use-defaults.h-and-t-oe-in-B.patch \
+       file://gcc-with-linker-hash-style.patch \
+       file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \
+       \
+       file://fortran-cross-compile-hack.patch \
+       "
+
+# Language Overrides
+FORTRAN = ""
+JAVA = ""
+
+S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/${BRANCH}"
+B = "${WORKDIR}/${BRANCH}/build.${HOST_SYS}.${TARGET_SYS}"
+
+#EXTRA_OECONF_BASE = "  --enable-cheaders=c_std \
+#			--enable-libssp \
+#			--disable-bootstrap \
+#			--disable-libgomp \
+#			--disable-libmudflap"
+EXTRA_OECONF_BASE = "--enable-lto \
+                     --enable-libssp \
+                     --disable-bootstrap \
+                     --disable-libgomp \
+                     --disable-libmudflap \
+		     --with-linker-hash-style=${LINKER_HASH_STYLE} \
+		     --with-ppl=no \
+		     --with-cloog=no \
+                     --enable-cheaders=c_global "
+
+EXTRA_OECONF_INITIAL = "--disable-libmudflap \
+                        --disable-libgomp \
+                        --disable-libssp \
+                        --enable-decimal-float=no"
+
+EXTRA_OECONF_INTERMEDIATE = "--disable-libmudflap \
+                             --disable-libgomp \
+                             --disable-libssp"
+
+EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float "
+EXTRA_OECONF_append_mips64 = " --with-arch-64=mips64 --with-tune-64=mips64"
+EXTRA_OECONF_append_mips64el = " --with-arch-64=mips64 --with-tune-64=mips64"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch
new file mode 100644
index 0000000000..0b799607e8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch
@@ -0,0 +1,37 @@
+Index: gcc-4.3.1/contrib/regression/objs-gcc.sh
+===================================================================
+--- gcc-4.3.1.orig/contrib/regression/objs-gcc.sh	2007-12-24 15:18:57.000000000 -0800
++++ gcc-4.3.1/contrib/regression/objs-gcc.sh	2008-08-16 01:15:12.000000000 -0700
+@@ -105,6 +105,10 @@
+  then
+   make all-gdb all-dejagnu all-ld || exit 1
+   make install-gdb install-dejagnu install-ld || exit 1
++elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ]
++ then
++  make all-gdb all-dejagnu all-ld || exit 1
++  make install-gdb install-dejagnu install-ld || exit 1
+ elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then
+   make bootstrap || exit 1
+   make install || exit 1
+Index: gcc-4.3.1/libjava/classpath/ltconfig
+===================================================================
+--- gcc-4.3.1.orig/libjava/classpath/ltconfig	2007-06-03 16:18:43.000000000 -0700
++++ gcc-4.3.1/libjava/classpath/ltconfig	2008-08-16 01:15:12.000000000 -0700
+@@ -603,7 +603,7 @@
+ 
+ # Transform linux* to *-*-linux-gnu*, to support old configure scripts.
+ case $host_os in
+-linux-gnu*) ;;
++linux-gnu*|linux-uclibc*) ;;
+ linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
+ esac
+ 
+@@ -1251,7 +1251,7 @@
+   ;;
+ 
+ # This must be Linux ELF.
+-linux-gnu*)
++linux*)
+   version_type=linux
+   need_lib_prefix=no
+   need_version=no
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch
new file mode 100644
index 0000000000..23fce7544d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch
@@ -0,0 +1,20 @@
+--- gcc-4.1.0/libstdc++-v3/fragment.am	2005-03-21 11:40:14.000000000 -0600
++++ gcc-4.1.0-patched/libstdc++-v3/fragment.am	2005-04-25 20:14:39.856251785 -0500
+@@ -21,5 +21,5 @@
+ 	$(WARN_FLAGS) $(WERROR) -fdiagnostics-show-location=once
+ 
+ # -I/-D flags to pass when compiling.
+-AM_CPPFLAGS = $(GLIBCXX_INCLUDES)
++AM_CPPFLAGS = $(GLIBCXX_INCLUDES) -I$(toplevel_srcdir)/include
+ 
+--- gcc-4.1.0/libstdc++-v3/libmath/Makefile.am	2005-03-21 11:40:18.000000000 -0600
++++ gcc-4.1.0-patched/libstdc++-v3/libmath/Makefile.am	2005-04-25 20:14:39.682280735 -0500
+@@ -35,7 +35,7 @@
+ 
+ libmath_la_SOURCES = stubs.c
+ 
+-AM_CPPFLAGS = $(CANADIAN_INCLUDES)
++AM_CPPFLAGS = $(CANADIAN_INCLUDES) -I$(toplevel_srcdir)/include
+ 
+ # Only compiling "C" sources in this directory.
+ LIBTOOL = @LIBTOOL@ --tag CC
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch
new file mode 100644
index 0000000000..70330145ec
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch
@@ -0,0 +1,68 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+GCC has internal multilib handling code but it assumes a very specific rigid directory
+layout. The build system implementation of multilib layout is very generic and allows
+complete customisation of the library directories.
+
+This patch is a partial solution to allow any custom directories to be passed into gcc
+and handled correctly. It forces gcc to use the base_libdir (which is the current 
+directory, "."). We need to do this for each multilib that is configured as we don't
+know which compiler options may be being passed into the compiler. Since we have a compiler
+per mulitlib at this point that isn't an issue.
+
+The one problem is the target compiler is only going to work for the default multlilib at
+this point. Ideally we'd figure out which multilibs were being enabled with which paths
+and be able to patch these entries with a complete set of correct paths but this we
+don't have such code at this point. This is something the target gcc recipe should do 
+and override these platform defaults in its build config.
+
+RP 15/8/11
+
+Index: gcc-4_5-branch/gcc/config/i386/t-linux64
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/i386/t-linux64	2011-09-22 11:37:51.188913390 -0700
++++ gcc-4_5-branch/gcc/config/i386/t-linux64	2011-09-22 11:37:56.818913303 -0700
+@@ -24,8 +24,8 @@
+ # MULTILIB_OSDIRNAMES according to what is found on the target.
+ 
+ MULTILIB_OPTIONS = m64/m32
+-MULTILIB_DIRNAMES = 64 32 
+-MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)
++MULTILIB_DIRNAMES = . .
++MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
+ 
+ LIBGCC = stmp-multilib
+ INSTALL_LIBGCC = install-multilib
+Index: gcc-4_5-branch/gcc/config/mips/t-linux64
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/mips/t-linux64	2011-06-16 17:59:02.000000000 -0700
++++ gcc-4_5-branch/gcc/config/mips/t-linux64	2011-09-22 11:37:56.838913302 -0700
+@@ -17,8 +17,8 @@
+ # <http://www.gnu.org/licenses/>.
+ 
+ MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
+-MULTILIB_DIRNAMES = n32 32 64
+-MULTILIB_OSDIRNAMES = ../lib32 ../lib ../lib64
++MULTILIB_DIRNAMES = . . .
++MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
+ 
+ EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
+ 
+Index: gcc-4_5-branch/gcc/config/rs6000/t-linux64
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/t-linux64	2011-06-16 17:58:58.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/t-linux64	2011-09-22 11:37:56.838913302 -0700
+@@ -32,11 +32,11 @@ TARGET_LIBGCC2_CFLAGS += -mno-minimal-to
+ # MULTILIB_OSDIRNAMES according to what is found on the target.
+ 
+ MULTILIB_OPTIONS        = m64/m32 msoft-float
+-MULTILIB_DIRNAMES       = 64 32 nof
++MULTILIB_DIRNAMES       = . . .
+ MULTILIB_EXTRA_OPTS     = fPIC mstrict-align
+ MULTILIB_EXCEPTIONS     = m64/msoft-float
+ MULTILIB_EXCLUSIONS     = m64/!m32/msoft-float
+-MULTILIB_OSDIRNAMES	= ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof
++MULTILIB_OSDIRNAMES	= ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
+ MULTILIB_MATCHES        = $(MULTILIB_MATCHES_FLOAT)
+ 
+ softfp_wrap_start := '\#ifndef __powerpc64__'
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch
new file mode 100644
index 0000000000..d84889259d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch
@@ -0,0 +1,29 @@
+http://sourceforge.net/mailarchive/forum.php?thread_id=8959304&forum_id=5348
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24836
+
+Index: gcc-4.5.0/gcc/configure.ac
+===================================================================
+--- gcc-4.5.0.orig/gcc/configure.ac	2010-03-25 22:40:32.000000000 -0700
++++ gcc-4.5.0/gcc/configure.ac	2010-06-25 11:02:48.489057877 -0700
+@@ -2784,7 +2784,7 @@
+ 	tls_first_minor=14
+ 	tls_as_opt="-m64 -Aesame --fatal-warnings"
+ 	;;
+-  sh-*-* | sh[34]-*-*)
++  sh-*-* | sh[34]*-*-*)
+     conftest_s='
+ 	.section ".tdata","awT",@progbits
+ foo:	.long	25
+Index: gcc-4.5.0/gcc/configure
+===================================================================
+--- gcc-4.5.0.orig/gcc/configure	2010-03-25 22:40:32.000000000 -0700
++++ gcc-4.5.0/gcc/configure	2010-06-25 11:02:48.508381845 -0700
+@@ -22156,7 +22156,7 @@
+ 	tls_first_minor=14
+ 	tls_as_opt="-m64 -Aesame --fatal-warnings"
+ 	;;
+-  sh-*-* | sh[34]-*-*)
++  sh-*-* | sh[34]*-*-*)
+     conftest_s='
+ 	.section ".tdata","awT",@progbits
+ foo:	.long	25
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch
new file mode 100644
index 0000000000..77d02c3abd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch
@@ -0,0 +1,34 @@
+By Lennert Buytenhek <buytenh@wantstofly.org>
+Adds support for arm*b-linux* big-endian ARM targets
+
+See http://gcc.gnu.org/PR16350
+
+Index: gcc-4.5.0/gcc/config/arm/linux-elf.h
+===================================================================
+--- gcc-4.5.0.orig/gcc/config/arm/linux-elf.h	2009-11-05 06:47:45.000000000 -0800
++++ gcc-4.5.0/gcc/config/arm/linux-elf.h	2010-06-25 11:03:06.997132728 -0700
+@@ -51,7 +51,7 @@
+ 
+ #undef  MULTILIB_DEFAULTS
+ #define MULTILIB_DEFAULTS \
+-	{ "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" }
++	{ "marm", TARGET_ENDIAN_OPTION, "mhard-float", "mno-thumb-interwork" }
+ 
+ /* Now we define the strings used to build the spec file.  */
+ #undef  LIB_SPEC
+Index: gcc-4.5.0/gcc/config.gcc
+===================================================================
+--- gcc-4.5.0.orig/gcc/config.gcc	2010-06-25 10:40:33.321880880 -0700
++++ gcc-4.5.0/gcc/config.gcc	2010-06-25 11:03:07.013133525 -0700
+@@ -734,6 +734,11 @@
+ 	esac
+ 	tmake_file="${tmake_file} t-linux arm/t-arm"
+ 	case ${target} in
++	arm*b-*)
++		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
++		;;
++	esac
++	case ${target} in
+ 	arm*-*-linux-*eabi)
+ 	    tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
+ 	    tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch
new file mode 100644
index 0000000000..c4641dc63e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch
@@ -0,0 +1,74 @@
+Hi,
+
+The attached patch makes sure that we create smaller object code for
+simple switch statements. We just make sure to flatten the switch
+statement into an if-else chain, basically.
+
+This fixes a size-regression as compared to gcc-3.4, as can be seen
+below.
+
+2007-04-15  Bernhard Fischer  <..>
+
+	* stmt.c (expand_case): Do not create a complex binary tree when
+	optimizing for size but rather use the simple ordered list.
+	(emit_case_nodes): do not emit jumps to the default_label when
+	optimizing for size.
+
+Not regtested so far.
+Comments?
+
+Attached is the test switch.c mentioned below.
+
+$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
+gcc-$i  -DCHAIN -Os -o switch-CHAIN-$i.o -c switch.c ;done
+$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
+gcc-$i  -UCHAIN -Os -o switch-$i.o -c switch.c ;done
+
+$ size switch-*.o
+   text	   data	    bss	    dec	    hex	filename
+    169	      0	      0	    169	     a9	switch-2.95.o
+    115	      0	      0	    115	     73	switch-3.3.o
+    103	      0	      0	    103	     67	switch-3.4.o
+    124	      0	      0	    124	     7c	switch-4.0.o
+    124	      0	      0	    124	     7c	switch-4.1.o
+    124	      0	      0	    124	     7c	switch-4.2.orig-HEAD.o
+     95	      0	      0	     95	     5f	switch-4.3-HEAD.o
+    124	      0	      0	    124	     7c	switch-4.3.orig-HEAD.o
+    166	      0	      0	    166	     a6	switch-CHAIN-2.95.o
+    111	      0	      0	    111	     6f	switch-CHAIN-3.3.o
+     95	      0	      0	     95	     5f	switch-CHAIN-3.4.o
+     95	      0	      0	     95	     5f	switch-CHAIN-4.0.o
+     95	      0	      0	     95	     5f	switch-CHAIN-4.1.o
+     95	      0	      0	     95	     5f	switch-CHAIN-4.2.orig-HEAD.o
+     95	      0	      0	     95	     5f	switch-CHAIN-4.3-HEAD.o
+     95	      0	      0	     95	     5f	switch-CHAIN-4.3.orig-HEAD.o
+
+
+Content-Type: text/x-diff; charset=us-ascii
+Content-Disposition: attachment; filename="gcc-4.3.gcc-flatten-switch-stmt.00.diff"
+
+Index: gcc-4.5.0/gcc/stmt.c
+===================================================================
+--- gcc-4.5.0.orig/gcc/stmt.c	2010-02-19 01:53:51.000000000 -0800
++++ gcc-4.5.0/gcc/stmt.c	2010-06-25 11:05:31.816881094 -0700
+@@ -2440,7 +2440,11 @@
+ 	     default code is emitted.  */
+ 
+ 	  use_cost_table = estimate_case_costs (case_list);
+-	  balance_case_nodes (&case_list, NULL);
++	  /* When optimizing for size, we want a straight list to avoid
++	     jumps as much as possible. This basically creates an if-else
++	     chain.  */
++	  if (!optimize_size)
++	    balance_case_nodes (&case_list, NULL);
+ 	  emit_case_nodes (index, case_list, default_label, index_type);
+ 	  if (default_label)
+ 	    emit_jump (default_label);
+@@ -3008,6 +3012,7 @@
+ 	    {
+ 	      if (!node_has_low_bound (node, index_type))
+ 		{
++		  if (!optimize_size) /* don't jl to the .default_label. */
+ 		  emit_cmp_and_jump_insns (index,
+ 					   convert_modes
+ 					   (mode, imode,
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch
new file mode 100644
index 0000000000..076e9a614f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch
@@ -0,0 +1,23 @@
+#This patck added --sysroot into COLLECT_GCC_OPTIONS which is used to
+#invoke collect2.
+
+Index: gcc-4_5-branch/gcc/gcc.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/gcc.c
++++ gcc-4_5-branch/gcc/gcc.c
+@@ -4667,6 +4667,15 @@ set_collect_gcc_options (void)
+ 		sizeof ("COLLECT_GCC_OPTIONS=") - 1);
+ 
+   first_time = TRUE;
++#ifdef HAVE_LD_SYSROOT
++  if (target_system_root_changed && target_system_root)
++    {
++      obstack_grow (&collect_obstack, "'--sysroot=", sizeof("'--sysroot=")-1);
++      obstack_grow (&collect_obstack, target_system_root,strlen(target_system_root));
++      obstack_grow (&collect_obstack, "'", 1);
++      first_time = FALSE;
++    }
++#endif
+   for (i = 0; (int) i < n_switches; i++)
+     {
+       const char *const *args;
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch
new file mode 100644
index 0000000000..5c7b346ca5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch
@@ -0,0 +1,178 @@
+source: http://patchwork.ozlabs.org/patch/129800/
+Upstream-Status: Submitted
+
+ChangeLog
+        * Makefile.in (gcc_gxx_include_dir_add_sysroot): New.
+          (PREPROCESSOR_DEFINES): Define GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT.
+
+        * cppdefault.c (cpp_include_defaults): replace hard coded "1" with
+          GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT for "add_sysroot" field.
+
+        * configure.ac (AC_SUBST): Add gcc_gxx_include_dir_add_sysroot to
+          control whether sysroot should be prepended to gxx include dir.
+
+        * configure: Regenerate.
+
+Hi, this is a follow up for issue "http://codereview.appspot.com/4641076".
+
+The rationale for the patch copied from previous thread:
+=======================================
+The setup:
+
+Configuring a toolchain targeting x86-64 GNU Linux (Ubuntu Lucid), as a
+cross-compiler.  Using a sysroot to provide the Lucid headers+libraries,
+with the sysroot path being within the GCC install tree.  Want to use the
+Lucid system libstdc++ and headers, which means that I'm not
+building/installing libstdc++-v3.
+
+So, configuring with:
+  --with-sysroot="$SYSROOT"
+  --disable-libstdc++-v3 \
+  --with-gxx-include-dir="$SYSROOT/usr/include/c++/4.4" \
+(among other options).
+
+Hoping to support two usage models with this configuration, w.r.t. use of
+the sysroot:
+
+(1) somebody installs the sysroot in the normal location relative to the
+GCC install, and relocates the whole bundle (sysroot+GCC).  This works
+great AFAICT, GCC finds its includes (including the C++ includes) thanks
+to the add_standard_paths iprefix handling.
+
+(2) somebody installs the sysroot in a non-standard location, and uses
+--sysroot to try to access it.  This works fine for the C headers, but
+doesn't work.
+
+For the C headers, add_standard_paths prepends the sysroot location to
+the /usr/include path (since that's what's specified in cppdefault.c for
+that path).  It doesn't do the same for the C++ include path, though
+(again, as specified in cppdefault.c).
+
+add_standard_paths doesn't attempt to relocate built-in include paths that
+start with the compiled-in sysroot location (e.g., the g++ include dir, in
+this case).  This isn't surprising really: normally you either prepend the
+sysroot location or you don't (as specified by cppdefault.c); none of the
+built-in paths normally *start* with the sysroot location and need to be
+relocated.  However, in this odd-ball case of trying to use the C++ headers
+from the sysroot, one of the paths *does* need to be relocated in this way.
+===========================
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -585,6 +585,7 @@ slibdir = @slibdir@
+ build_tooldir = $(exec_prefix)/$(target_noncanonical)
+ # Directory in which the compiler finds target-independent g++ includes.
+ gcc_gxx_include_dir = @gcc_gxx_include_dir@
++gcc_gxx_include_dir_add_sysroot = @gcc_gxx_include_dir_add_sysroot@
+ # Directory to search for site-specific includes.
+ local_includedir = $(local_prefix)/include
+ includedir = $(prefix)/include
+@@ -3788,6 +3789,7 @@ PREPROCESSOR_DEFINES = \
+   -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \
+   -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
+   -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
++  -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
+   -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \
+   -DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \
+   -DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -144,6 +144,15 @@ if test x${gcc_gxx_include_dir} = x; the
+   fi
+ fi
+ 
++gcc_gxx_include_dir_add_sysroot=0
++if test "${with_sysroot+set}" = set; then :
++  gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
++  if test "${gcc_gxx_without_sysroot}"; then :
++    gcc_gxx_include_dir="${gcc_gxx_without_sysroot}"
++    gcc_gxx_include_dir_add_sysroot=1
++  fi
++fi
++
+ AC_ARG_WITH(cpp_install_dir,
+ [  --with-cpp-install-dir=DIR
+                           install the user visible C preprocessor in DIR
+@@ -4492,6 +4501,7 @@ AC_SUBST(extra_programs)
+ AC_SUBST(float_h_file)
+ AC_SUBST(gcc_config_arguments)
+ AC_SUBST(gcc_gxx_include_dir)
++AC_SUBST(gcc_gxx_include_dir_add_sysroot)
+ AC_SUBST(host_exeext)
+ AC_SUBST(host_xm_file_list)
+ AC_SUBST(host_xm_include_list)
+--- a/gcc/cppdefault.c
++++ b/gcc/cppdefault.c
+@@ -48,15 +48,18 @@ const struct default_include cpp_include
+ = {
+ #ifdef GPLUSPLUS_INCLUDE_DIR
+     /* Pick up GNU C++ generic include files.  */
+-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
++    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,
++      GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
+ #endif
+ #ifdef GPLUSPLUS_TOOL_INCLUDE_DIR
+     /* Pick up GNU C++ target-dependent include files.  */
+-    { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 },
++    { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,
++      GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },
+ #endif
+ #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR
+     /* Pick up GNU C++ backward and deprecated include files.  */
+-    { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
++    { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1,
++      GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
+ #endif
+ #ifdef LOCAL_INCLUDE_DIR
+     /* /usr/local/include comes before the fixincluded header files.  */
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -639,6 +639,7 @@ host_xm_defines
+ host_xm_include_list
+ host_xm_file_list
+ host_exeext
++gcc_gxx_include_dir_add_sysroot
+ gcc_gxx_include_dir
+ gcc_config_arguments
+ float_h_file
+@@ -3282,6 +3283,15 @@ if test x${gcc_gxx_include_dir} = x; the
+   fi
+ fi
+ 
++gcc_gxx_include_dir_add_sysroot=0
++if test "${with_sysroot+set}" = set; then :
++  gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
++  if test "${gcc_gxx_without_sysroot}"; then :
++    gcc_gxx_include_dir="${gcc_gxx_without_sysroot}"
++    gcc_gxx_include_dir_add_sysroot=1
++  fi
++fi
++
+ 
+ # Check whether --with-cpp_install_dir was given.
+ if test "${with_cpp_install_dir+set}" = set; then :
+@@ -17118,7 +17128,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 17121 "configure"
++#line 17131 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -17224,7 +17234,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 17227 "configure"
++#line 17237 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -25381,6 +25391,7 @@ fi
+ 
+ 
+ 
++
+ 
+ 
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch
new file mode 100644
index 0000000000..45df47c5bf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch
@@ -0,0 +1,30 @@
+Index: gcc-4.5/gcc/Makefile.in
+===================================================================
+--- gcc-4.5.orig/gcc/Makefile.in
++++ gcc-4.5/gcc/Makefile.in
+@@ -656,7 +656,7 @@ LIBGCC2_INCLUDES =
+ TARGET_LIBGCC2_CFLAGS =
+ 
+ # Options to use when compiling crtbegin/end.
+-CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
++CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(TARGET_INCLUDES) $(MULTILIB_CFLAGS) -g0 \
+   -finhibit-size-directive -fno-inline -fno-exceptions \
+   -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \
+   $(INHIBIT_LIBC_CFLAGS)
+@@ -1038,10 +1038,14 @@ BUILD_ERRORS = build/errors.o
+ # -I$(@D) and -I$(srcdir)/$(@D) cause the subdirectory of the file
+ # currently being compiled, in both source trees, to be examined as well.
+ # libintl.h will be found in ../intl if we are using the included libintl.
+-INCLUDES = -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \
++#
++# TARGET_INCLUDES is added to avoid that GMPINC (which points to the host
++# include dir) is used for compiling libgcc.a
++TARGET_INCLUDES = -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \
+ 	   -I$(srcdir)/../include @INCINTL@ \
+-	   $(CPPINC) $(GMPINC) $(DECNUMINC) \
++	   $(CPPINC) $(DECNUMINC) \
+ 	   $(PPLINC) $(CLOOGINC) $(LIBELFINC)
++INCLUDES = $(TARGET_INCLUDES) $(GMPINC)
+ 
+ .c.o:
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $< $(OUTPUT_OPTION)
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch
new file mode 100644
index 0000000000..39c90e7e74
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch
@@ -0,0 +1,18 @@
+Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999
+
+http://patchwork.ozlabs.org/patch/72260/ is the patch that made into
+upstream gcc
+
+diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm
+index 085e690..2e76c01 100644
+--- a/gcc/config/arm/lib1funcs.asm
++++ b/gcc/config/arm/lib1funcs.asm
+@@ -641,7 +641,7 @@ pc		.req	r15
+ 	subhs	\dividend, \dividend, \divisor, lsr #3
+ 	orrhs	\result,   \result,   \curbit,  lsr #3
+ 	cmp	\dividend, #0			@ Early termination?
+-	do_it	hs, t
++	do_it	ne, t
+ 	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+ 	movne	\divisor,  \divisor, lsr #4
+ 	bne	1b
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch
new file mode 100644
index 0000000000..7bb8887068
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch
@@ -0,0 +1,36 @@
+#! /bin/sh -e
+
+# DP: Fix armv4t build on ARM
+
+dir=
+if [ $# -eq 3 -a "$2" = '-d' ]; then
+    pdir="-d $3"
+    dir="$3/"
+elif [ $# -ne 1 ]; then
+    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+    exit 1
+fi
+case "$1" in
+    -patch)
+        patch $pdir -f --no-backup-if-mismatch -p1 < $0
+        ;;
+    -unpatch)
+        patch $pdir -f --no-backup-if-mismatch -R -p1 < $0
+        ;;
+    *)
+        echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+        exit 1
+esac
+exit 0
+
+--- src/gcc/config/arm/linux-eabi.h.orig	2007-11-24 12:37:38.000000000 +0000
++++ src/gcc/config/arm/linux-eabi.h	2007-11-24 12:39:41.000000000 +0000
+@@ -44,7 +44,7 @@
+    The ARM10TDMI core is the default for armv5t, so set
+    SUBTARGET_CPU_DEFAULT to achieve this.  */
+ #undef  SUBTARGET_CPU_DEFAULT
+-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi
++#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi
+ 
+ /* TARGET_BIG_ENDIAN_DEFAULT is set in
+    config.gcc for big endian configurations.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch
new file mode 100644
index 0000000000..b889f9b6ca
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch
@@ -0,0 +1,31 @@
+---
+ gcc/configure    |    2 +-
+ gcc/configure.ac |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: gcc-4.5+svnr155514/gcc/configure
+===================================================================
+--- gcc-4.5+svnr155514.orig/gcc/configure	2009-12-29 22:00:40.000000000 -0800
++++ gcc-4.5+svnr155514/gcc/configure	2009-12-29 23:52:43.381592113 -0800
+@@ -10467,7 +10467,7 @@ else
+ 	saved_CFLAGS="${CFLAGS}"
+ 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
+ 	LDFLAGS="${LDFLAGS_FOR_BUILD}" \
+-	${realsrcdir}/configure \
++	CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
+ 		--enable-languages=${enable_languages-all} \
+ 		--target=$target_alias --host=$build_alias --build=$build_alias
+ 	CFLAGS="${saved_CFLAGS}"
+Index: gcc-4.5+svnr155514/gcc/configure.ac
+===================================================================
+--- gcc-4.5+svnr155514.orig/gcc/configure.ac	2009-12-29 22:00:40.000000000 -0800
++++ gcc-4.5+svnr155514/gcc/configure.ac	2009-12-29 23:51:54.589091778 -0800
+@@ -1458,7 +1458,7 @@ else
+ 	saved_CFLAGS="${CFLAGS}"
+ 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
+ 	LDFLAGS="${LDFLAGS_FOR_BUILD}" \
+-	${realsrcdir}/configure \
++	CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
+ 		--enable-languages=${enable_languages-all} \
+ 		--target=$target_alias --host=$build_alias --build=$build_alias
+ 	CFLAGS="${saved_CFLAGS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch
new file mode 100644
index 0000000000..b1d5a1a3cb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch
@@ -0,0 +1,44 @@
+GCC: disable MASK_RELAX_PIC_CALLS bit
+
+The new feature added after 4.3.3
+"http://www.pubbs.net/200909/gcc/94048-patch-add-support-for-rmipsjalr.html"
+will cause cc1plus eat up all the system memory when build webkit-gtk.
+The function mips_get_pic_call_symbol keeps on recursively calling itself.
+Disable this feature to walk aside the bug.
+
+Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
+
+diff -ruN gcc-4.5.0-orig/gcc/configure gcc-4.5.0/gcc/configure
+--- gcc-4.5.0-orig/gcc/configure	2010-09-17 23:30:21.000000000 +0800
++++ gcc-4.5.0/gcc/configure	2010-09-19 18:21:28.000000000 +0800
+@@ -23945,13 +23945,6 @@
+         rm -f conftest.*
+       fi
+     fi
+-    if test $gcc_cv_as_ld_jalr_reloc = yes; then
+-      if test x$target_cpu_default = x; then
+-        target_cpu_default=MASK_RELAX_PIC_CALLS
+-      else
+-        target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS"
+-      fi
+-    fi
+     { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ld_jalr_reloc" >&5
+ $as_echo "$gcc_cv_as_ld_jalr_reloc" >&6; }
+ 
+diff -ruN gcc-4.5.0-orig/gcc/configure.ac gcc-4.5.0/gcc/configure.ac
+--- gcc-4.5.0-orig/gcc/configure.ac	2010-09-17 23:30:21.000000000 +0800
++++ gcc-4.5.0/gcc/configure.ac	2010-09-19 18:21:11.000000000 +0800
+@@ -3467,13 +3467,6 @@
+         rm -f conftest.*
+       fi
+     fi
+-    if test $gcc_cv_as_ld_jalr_reloc = yes; then
+-      if test x$target_cpu_default = x; then
+-        target_cpu_default=MASK_RELAX_PIC_CALLS
+-      else
+-        target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS"
+-      fi
+-    fi
+     AC_MSG_RESULT($gcc_cv_as_ld_jalr_reloc)
+ 
+     AC_CACHE_CHECK([linker for .eh_frame personality relaxation],
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch
new file mode 100644
index 0000000000..a149eae98e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch
@@ -0,0 +1,114 @@
+2007-10-02  Jakub Jelinek  <jakub@redhat.com>
+
+	* decl.c (duplicate_decls): When redeclaring a builtin function,
+	keep the merged decl builtin whenever types match, even if new
+	decl defines a function.
+
+	* gcc.dg/builtins-65.c: New test.
+	* g++.dg/ext/builtin10.C: New test.
+
+Index: gcc/cp/decl.c
+===================================================================
+--- gcc/cp/decl.c.orig	2010-04-01 11:48:46.000000000 -0700
++++ gcc/cp/decl.c	2010-06-25 10:10:54.749131719 -0700
+@@ -2021,23 +2021,21 @@
+ 	  DECL_ARGUMENTS (olddecl) = DECL_ARGUMENTS (newdecl);
+ 	  DECL_RESULT (olddecl) = DECL_RESULT (newdecl);
+ 	}
++      /* If redeclaring a builtin function, it stays built in.  */
++      if (types_match && DECL_BUILT_IN (olddecl))
++	{
++	  DECL_BUILT_IN_CLASS (newdecl) = DECL_BUILT_IN_CLASS (olddecl);
++	  DECL_FUNCTION_CODE (newdecl) = DECL_FUNCTION_CODE (olddecl);
++	  /* If we're keeping the built-in definition, keep the rtl,
++	     regardless of declaration matches.  */
++	  COPY_DECL_RTL (olddecl, newdecl);
++	}
+       if (new_defines_function)
+ 	/* If defining a function declared with other language
+ 	   linkage, use the previously declared language linkage.  */
+ 	SET_DECL_LANGUAGE (newdecl, DECL_LANGUAGE (olddecl));
+       else if (types_match)
+ 	{
+-	  /* If redeclaring a builtin function, and not a definition,
+-	     it stays built in.  */
+-	  if (DECL_BUILT_IN (olddecl))
+-	    {
+-	      DECL_BUILT_IN_CLASS (newdecl) = DECL_BUILT_IN_CLASS (olddecl);
+-	      DECL_FUNCTION_CODE (newdecl) = DECL_FUNCTION_CODE (olddecl);
+-	      /* If we're keeping the built-in definition, keep the rtl,
+-		 regardless of declaration matches.  */
+-	      COPY_DECL_RTL (olddecl, newdecl);
+-	    }
+-
+ 	  DECL_RESULT (newdecl) = DECL_RESULT (olddecl);
+ 	  /* Don't clear out the arguments if we're just redeclaring a
+ 	     function.  */
+Index: gcc/testsuite/gcc.dg/builtins-65.c
+===================================================================
+--- gcc/testsuite/gcc.dg/builtins-65.c.orig	2009-06-26 02:02:04.000000000 -0700
++++ gcc/testsuite/gcc.dg/builtins-65.c	2010-06-25 10:10:54.784464429 -0700
+@@ -1,3 +1,28 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef __SIZE_TYPE__ size_t;
++extern void __chk_fail (void);
++extern int snprintf (char *, size_t, const char *, ...);
++extern inline __attribute__((gnu_inline, always_inline)) int snprintf (char *a, size_t b, const char *fmt, ...)
++{
++  if (__builtin_object_size (a, 0) != -1UL && __builtin_object_size (a, 0) < b)
++    __chk_fail ();
++  return __builtin_snprintf (a, b, fmt, __builtin_va_arg_pack ());
++}
++extern int snprintf (char *, size_t, const char *, ...) __asm ("mysnprintf");
++
++char buf[10];
++
++int
++main (void)
++{
++  snprintf (buf, 10, "%d%d\n", 10, 10);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mysnprintf" } } */
++/* { dg-final { scan-assembler-not "__chk_fail" } } */
+ /* { dg-do link } */
+ /* { dg-options "-O2 -ffast-math" } */
+ /* { dg-require-effective-target c99_runtime } */
+Index: gcc/testsuite/g++.dg/ext/builtin10.C
+===================================================================
+--- gcc/testsuite/g++.dg/ext/builtin10.C.orig	2009-02-02 03:27:50.000000000 -0800
++++ gcc/testsuite/g++.dg/ext/builtin10.C	2010-06-25 10:10:54.816467202 -0700
+@@ -1,3 +1,30 @@
++// { dg-do compile }
++// { dg-options "-O2" }
++
++typedef __SIZE_TYPE__ size_t;
++extern "C" {
++extern void __chk_fail (void);
++extern int snprintf (char *, size_t, const char *, ...);
++extern inline __attribute__((gnu_inline, always_inline)) int snprintf (char *a, size_t b, const char *fmt, ...)
++{
++  if (__builtin_object_size (a, 0) != -1UL && __builtin_object_size (a, 0) < b)
++    __chk_fail ();
++  return __builtin_snprintf (a, b, fmt, __builtin_va_arg_pack ());
++}
++extern int snprintf (char *, size_t, const char *, ...) __asm ("mysnprintf");
++}
++
++char buf[10];
++
++int
++main (void)
++{
++  snprintf (buf, 10, "%d%d\n", 10, 10);
++  return 0;
++}
++
++// { dg-final { scan-assembler "mysnprintf" } }
++// { dg-final { scan-assembler-not "__chk_fail" } }
+ // { dg-do compile { target correct_iso_cpp_string_wchar_protos } }
+ // { dg-options "-O2 -fdump-tree-optimized" }
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch
new file mode 100644
index 0000000000..00d37bd7ce
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch
@@ -0,0 +1,284 @@
+2008-02-26  Jakub Jelinek  <jakub@redhat.com>
+
+	* c-ppoutput.c (scan_translation_unit): Handle CPP_PRAGMA
+	and CPP_PRAGMA_EOL.
+	* c-pragma.c (pragma_ns_name): New typedef.
+	(registered_pp_pragmas): New variable.
+	(c_pp_lookup_pragma): New function.
+	(c_register_pragma_1): If flag_preprocess_only, do nothing
+	for non-expanded pragmas, for expanded ones push pragma's
+	namespace and name into registered_pp_pragmas vector.
+	(c_invoke_pragma_handler): Register OpenMP pragmas even when
+	flag_preprocess_only, don't register GCC pch_preprocess
+	pragma if flag_preprocess_only.
+	* c-opts.c (c_common_init): Call init_pragma even if
+	flag_preprocess_only.
+	* c-pragma.c (c_pp_lookup_pragma): New prototype.
+	* config/darwin.h (DARWIN_REGISTER_TARGET_PRAGMAS): Don't call
+	cpp_register_pragma if flag_preprocess_only.
+
+	* gcc.dg/gomp/preprocess-1.c: New test.
+
+--- gcc/c-ppoutput.c.jj	2008-01-26 18:01:16.000000000 +0100
++++ gcc/c-ppoutput.c	2008-02-26 22:54:57.000000000 +0100
+@@ -1,6 +1,6 @@
+ /* Preprocess only, using cpplib.
+-   Copyright (C) 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007
+-   Free Software Foundation, Inc.
++   Copyright (C) 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
++   2008 Free Software Foundation, Inc.
+    Written by Per Bothner, 1994-95.
+ 
+    This program is free software; you can redistribute it and/or modify it
+@@ -177,7 +177,24 @@ scan_translation_unit (cpp_reader *pfile
+       avoid_paste = false;
+       print.source = NULL;
+       print.prev = token;
+-      cpp_output_token (token, print.outf);
++      if (token->type == CPP_PRAGMA)
++	{
++	  const char *space;
++	  const char *name;
++
++	  maybe_print_line (token->src_loc);
++	  fputs ("#pragma ", print.outf);
++	  c_pp_lookup_pragma (token->val.pragma, &space, &name);
++	  if (space)
++	    fprintf (print.outf, "%s %s", space, name);
++	  else
++	    fprintf (print.outf, "%s", name);
++	  print.printed = 1;
++	}
++      else if (token->type == CPP_PRAGMA_EOL)
++	maybe_print_line (token->src_loc);
++      else
++	cpp_output_token (token, print.outf);
+ 
+       if (token->type == CPP_COMMENT)
+ 	account_for_newlines (token->val.str.text, token->val.str.len);
+--- gcc/c-pragma.c.jj	2008-02-15 18:43:03.000000000 +0100
++++ gcc/c-pragma.c	2008-02-26 22:59:44.000000000 +0100
+@@ -1,6 +1,6 @@
+ /* Handle #pragma, system V.4 style.  Supports #pragma weak and #pragma pack.
+    Copyright (C) 1992, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+-   2006, 2007 Free Software Foundation, Inc.
++   2006, 2007, 2008 Free Software Foundation, Inc.
+ 
+ This file is part of GCC.
+ 
+@@ -872,6 +872,61 @@ DEF_VEC_ALLOC_O (pragma_handler, heap);
+ 
+ static VEC(pragma_handler, heap) *registered_pragmas;
+ 
++typedef struct
++{
++  const char *space;
++  const char *name;
++} pragma_ns_name;
++
++DEF_VEC_O (pragma_ns_name);
++DEF_VEC_ALLOC_O (pragma_ns_name, heap);
++
++static VEC(pragma_ns_name, heap) *registered_pp_pragmas;
++
++struct omp_pragma_def { const char *name; unsigned int id; };
++static const struct omp_pragma_def omp_pragmas[] = {
++  { "atomic", PRAGMA_OMP_ATOMIC },
++  { "barrier", PRAGMA_OMP_BARRIER },
++  { "critical", PRAGMA_OMP_CRITICAL },
++  { "flush", PRAGMA_OMP_FLUSH },
++  { "for", PRAGMA_OMP_FOR },
++  { "master", PRAGMA_OMP_MASTER },
++  { "ordered", PRAGMA_OMP_ORDERED },
++  { "parallel", PRAGMA_OMP_PARALLEL },
++  { "section", PRAGMA_OMP_SECTION },
++  { "sections", PRAGMA_OMP_SECTIONS },
++  { "single", PRAGMA_OMP_SINGLE },
++  { "threadprivate", PRAGMA_OMP_THREADPRIVATE }
++};
++
++void
++c_pp_lookup_pragma (unsigned int id, const char **space, const char **name)
++{
++  const int n_omp_pragmas = sizeof (omp_pragmas) / sizeof (*omp_pragmas);
++  int i;
++
++  for (i = 0; i < n_omp_pragmas; ++i)
++    if (omp_pragmas[i].id == id)
++      {
++	*space = "omp";
++	*name = omp_pragmas[i].name;
++	return;
++      }
++
++  if (id >= PRAGMA_FIRST_EXTERNAL
++      && (id < PRAGMA_FIRST_EXTERNAL
++	  + VEC_length (pragma_ns_name, registered_pp_pragmas)))
++    {
++      *space = VEC_index (pragma_ns_name, registered_pp_pragmas,
++			  id - PRAGMA_FIRST_EXTERNAL)->space;
++      *name = VEC_index (pragma_ns_name, registered_pp_pragmas,
++			 id - PRAGMA_FIRST_EXTERNAL)->name;
++      return;
++    }
++
++  gcc_unreachable ();
++}
++
+ /* Front-end wrappers for pragma registration to avoid dragging
+    cpplib.h in almost everywhere.  */
+ 
+@@ -881,13 +936,29 @@ c_register_pragma_1 (const char *space, 
+ {
+   unsigned id;
+ 
+-  VEC_safe_push (pragma_handler, heap, registered_pragmas, &handler);
+-  id = VEC_length (pragma_handler, registered_pragmas);
+-  id += PRAGMA_FIRST_EXTERNAL - 1;
+-
+-  /* The C++ front end allocates 6 bits in cp_token; the C front end
+-     allocates 7 bits in c_token.  At present this is sufficient.  */
+-  gcc_assert (id < 64);
++  if (flag_preprocess_only)
++    {
++      pragma_ns_name ns_name;
++
++      if (!allow_expansion)
++	return;
++
++      ns_name.space = space;
++      ns_name.name = name;
++      VEC_safe_push (pragma_ns_name, heap, registered_pp_pragmas, &ns_name);
++      id = VEC_length (pragma_ns_name, registered_pp_pragmas);
++      id += PRAGMA_FIRST_EXTERNAL - 1;
++    }
++  else
++    {
++      VEC_safe_push (pragma_handler, heap, registered_pragmas, &handler);
++      id = VEC_length (pragma_handler, registered_pragmas);
++      id += PRAGMA_FIRST_EXTERNAL - 1;
++
++      /* The C++ front end allocates 6 bits in cp_token; the C front end
++	 allocates 7 bits in c_token.  At present this is sufficient.  */
++      gcc_assert (id < 64);
++    }
+ 
+   cpp_register_deferred_pragma (parse_in, space, name, id,
+ 				allow_expansion, false);
+@@ -921,24 +992,8 @@ c_invoke_pragma_handler (unsigned int id
+ void
+ init_pragma (void)
+ {
+-  if (flag_openmp && !flag_preprocess_only)
++  if (flag_openmp)
+     {
+-      struct omp_pragma_def { const char *name; unsigned int id; };
+-      static const struct omp_pragma_def omp_pragmas[] = {
+-	{ "atomic", PRAGMA_OMP_ATOMIC },
+-	{ "barrier", PRAGMA_OMP_BARRIER },
+-	{ "critical", PRAGMA_OMP_CRITICAL },
+-	{ "flush", PRAGMA_OMP_FLUSH },
+-	{ "for", PRAGMA_OMP_FOR },
+-	{ "master", PRAGMA_OMP_MASTER },
+-	{ "ordered", PRAGMA_OMP_ORDERED },
+-	{ "parallel", PRAGMA_OMP_PARALLEL },
+-	{ "section", PRAGMA_OMP_SECTION },
+-	{ "sections", PRAGMA_OMP_SECTIONS },
+-	{ "single", PRAGMA_OMP_SINGLE },
+-	{ "threadprivate", PRAGMA_OMP_THREADPRIVATE }
+-      };
+-
+       const int n_omp_pragmas = sizeof (omp_pragmas) / sizeof (*omp_pragmas);
+       int i;
+ 
+@@ -947,8 +1002,9 @@ init_pragma (void)
+ 				      omp_pragmas[i].id, true, true);
+     }
+ 
+-  cpp_register_deferred_pragma (parse_in, "GCC", "pch_preprocess",
+-				PRAGMA_GCC_PCH_PREPROCESS, false, false);
++  if (!flag_preprocess_only)
++    cpp_register_deferred_pragma (parse_in, "GCC", "pch_preprocess",
++				  PRAGMA_GCC_PCH_PREPROCESS, false, false);
+ 
+ #ifdef HANDLE_PRAGMA_PACK
+ #ifdef HANDLE_PRAGMA_PACK_WITH_EXPANSION
+--- gcc/c-opts.c.jj	2008-02-26 22:53:23.000000000 +0100
++++ gcc/c-opts.c	2008-02-26 22:54:57.000000000 +0100
+@@ -1,5 +1,5 @@
+ /* C/ObjC/C++ command line option handling.
+-   Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
++   Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008
+    Free Software Foundation, Inc.
+    Contributed by Neil Booth.
+ 
+@@ -1239,6 +1239,9 @@ c_common_init (void)
+   if (version_flag)
+     c_common_print_pch_checksum (stderr);
+ 
++  /* Has to wait until now so that cpplib has its hash table.  */
++  init_pragma ();
++
+   if (flag_preprocess_only)
+     {
+       finish_options ();
+@@ -1246,9 +1249,6 @@ c_common_init (void)
+       return false;
+     }
+ 
+-  /* Has to wait until now so that cpplib has its hash table.  */
+-  init_pragma ();
+-
+   return true;
+ }
+ 
+--- gcc/c-pragma.h.jj	2008-01-26 18:01:16.000000000 +0100
++++ gcc/c-pragma.h	2008-02-26 22:54:57.000000000 +0100
+@@ -1,6 +1,6 @@
+ /* Pragma related interfaces.
+    Copyright (C) 1995, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+-   2007  Free Software Foundation, Inc.
++   2007, 2008  Free Software Foundation, Inc.
+ 
+ This file is part of GCC.
+ 
+@@ -124,4 +124,6 @@ extern enum cpp_ttype pragma_lex (tree *
+ extern enum cpp_ttype c_lex_with_flags (tree *, location_t *, unsigned char *,
+ 					int);
+ 
++extern void c_pp_lookup_pragma (unsigned int, const char **, const char **);
++
+ #endif /* GCC_C_PRAGMA_H */
+--- gcc/config/darwin.h.jj	2008-02-11 14:48:12.000000000 +0100
++++ gcc/config/darwin.h	2008-02-26 22:54:57.000000000 +0100
+@@ -892,8 +892,9 @@ enum machopic_addr_class {
+ 
+ #define DARWIN_REGISTER_TARGET_PRAGMAS()			\
+   do {								\
+-    cpp_register_pragma (parse_in, NULL, "mark",		\
+-			 darwin_pragma_ignore, false);		\
++    if (!flag_preprocess_only)					\
++      cpp_register_pragma (parse_in, NULL, "mark",		\
++			   darwin_pragma_ignore, false);	\
+     c_register_pragma (0, "options", darwin_pragma_options);	\
+     c_register_pragma (0, "segment", darwin_pragma_ignore);	\
+     c_register_pragma (0, "unused", darwin_pragma_unused);	\
+--- gcc/testsuite/gcc.dg/gomp/preprocess-1.c.jj	2008-02-26 22:54:57.000000000 +0100
++++ gcc/testsuite/gcc.dg/gomp/preprocess-1.c	2008-02-26 22:54:57.000000000 +0100
+@@ -0,0 +1,16 @@
++/* { dg-do preprocess } */
++
++void foo (void)
++{
++  int i1, j1, k1;
++#define p parallel
++#define P(x) private (x##1)
++#define S(x) shared (x##1)
++#define F(x) firstprivate (x##1)
++#pragma omp p P(i) \
++  S(j) \
++  F(k)
++  ;
++}
++
++/* { dg-final { scan-file preprocess-1.i "(^|\n)#pragma omp parallel private \\(i1\\) shared \\(j1\\) firstprivate \\(k1\\)($|\n)" } } */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch
new file mode 100644
index 0000000000..a588db28e8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch
@@ -0,0 +1,65 @@
+Build i386.rpm libgomp and libsupc++.a(guard.o) as i486+, pre-i486
+hardware isn't supported because NPTL doesn't support it anyway.
+
+Index: libgomp/configure.tgt
+===================================================================
+--- libgomp/configure.tgt.orig	2010-01-28 13:47:59.000000000 -0800
++++ libgomp/configure.tgt	2010-06-25 10:32:26.706135558 -0700
+@@ -48,14 +48,14 @@
+ 	;;
+ 
+     # Note that bare i386 is not included here.  We need cmpxchg.
+-    i[456]86-*-linux*)
++    i[3456]86-*-linux*)
+ 	config_path="linux/x86 linux posix"
+ 	case " ${CC} ${CFLAGS} " in
+ 	  *" -m64 "*)
+ 	    ;;
+ 	  *)
+ 	    if test -z "$with_arch"; then
+-	      XCFLAGS="${XCFLAGS} -march=i486 -mtune=${target_cpu}"
++	      XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
+ 	    fi
+ 	esac
+ 	;;
+@@ -67,7 +67,7 @@
+ 	config_path="linux/x86 linux posix"
+ 	case " ${CC} ${CFLAGS} " in
+ 	  *" -m32 "*)
+-	    XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686"
++	    XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
+ 	    ;;
+ 	esac
+ 	;;
+Index: libstdc++-v3/libsupc++/guard.cc
+===================================================================
+--- libstdc++-v3/libsupc++/guard.cc.orig	2009-11-09 14:09:30.000000000 -0800
++++ libstdc++-v3/libsupc++/guard.cc	2010-06-25 10:32:26.710135964 -0700
+@@ -30,6 +30,27 @@
+ #include <new>
+ #include <ext/atomicity.h>
+ #include <ext/concurrence.h>
++#if defined __i386__ && !defined _GLIBCXX_ATOMIC_BUILTINS
++# define _GLIBCXX_ATOMIC_BUILTINS 1
++# define __sync_val_compare_and_swap(a, b, c) \
++  ({								\
++     typedef char sltast[sizeof (*a) == sizeof (int) ? 1 : -1];	\
++     int sltas;							\
++     __asm __volatile ("lock; cmpxchgl %3, (%1)"		\
++		       : "=a" (sltas)				\
++		       : "r" (a), "0" (b), "r" (c) : "memory");	\
++     sltas;							\
++   })
++# define __sync_lock_test_and_set(a, b) \
++  ({								\
++     typedef char sltast[sizeof (*a) == sizeof (int) ? 1 : -1];	\
++     int sltas;							\
++     __asm __volatile ("xchgl (%1), %0"				\
++		       : "=r" (sltas)				\
++		       : "r" (a), "0" (b) : "memory");		\
++     sltas;							\
++   })
++#endif
+ #if defined(__GTHREADS) && defined(__GTHREAD_HAS_COND) \
+     && defined(_GLIBCXX_ATOMIC_BUILTINS_4) && defined(_GLIBCXX_HAVE_LINUX_FUTEX)
+ # include <climits>
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch
new file mode 100644
index 0000000000..cad13d1228
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch
@@ -0,0 +1,550 @@
+2004-11-27  Jakub Jelinek  <jakub@redhat.com>
+
+	* config.gcc (ia64*-*-linux*): If native and libelf is installed,
+	use ia64/t-glibc-no-libunwind instead of the other t-*unwind*
+	fragments.
+	* config/ia64/t-glibc-no-libunwind: New file.
+	* config/ia64/change-symver.c: New file.
+	* config/ia64/unwind-ia64.c: If USE_SYMVER_GLOBAL and SHARED,
+	define _Unwind_* to __symverglobal_Unwind_*.
+	(alias): Undefine.
+	(symverglobal): Define.  Use it on _Unwind_*.
+	* config/ia64/mkmap-symver-multi.awk: New file.
+	* config/ia64/libgcc-ia64-no-libunwind.ver: New file.
+
+Index: gcc/config.gcc
+===================================================================
+--- gcc/config.gcc.orig	2010-04-07 03:34:00.000000000 -0700
++++ gcc/config.gcc	2010-06-25 10:15:25.133131055 -0700
+@@ -1457,9 +1457,16 @@
+ 	;;
+ ia64*-*-linux*)
+ 	tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h ia64/sysv4.h ia64/linux.h"
+-	tmake_file="${tmake_file} ia64/t-ia64 t-libunwind ia64/t-glibc"
+-	if test x$with_system_libunwind != xyes ; then
+-		tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind"
++	tmake_file="${tmake_file} ia64/t-ia64"
++	if test x${target} = x${host} && test x${target} = x${build} \
++	   && grep gelf_getverdef /usr/include/gelf.h > /dev/null 2>&1 \
++	   && test -f /usr/lib/libelf.so; then
++		tmake_file="${tmake_file} ia64/t-glibc-no-libunwind"
++	else
++		tmake_file="${tmake_file} t-libunwind ia64/t-glibc"
++		if test x$with_system_libunwind != xyes ; then
++			tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind"
++		fi
+ 	fi
+ 	target_cpu_default="MASK_GNU_AS|MASK_GNU_LD"
+ 	extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtfastmath.o"
+Index: gcc/config/ia64/t-glibc-no-libunwind
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/config/ia64/t-glibc-no-libunwind	2010-06-25 10:14:32.521880765 -0700
+@@ -0,0 +1,30 @@
++# Don't use system libunwind library on IA-64 GLIBC based system,
++# but make _Unwind_* symbols unversioned, so that created programs
++# are usable even when libgcc_s uses libunwind.
++LIB2ADDEH += $(srcdir)/config/ia64/fde-glibc.c
++SHLIB_MAPFILES += $(srcdir)/config/ia64/libgcc-ia64-no-libunwind.ver
++SHLIB_MKMAP = $(srcdir)/config/ia64/mkmap-symver-multi.awk
++
++SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
++	-Wl,--soname=$(SHLIB_SONAME) \
++	-Wl,--version-script=$(SHLIB_MAP) \
++	-o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ $(SHLIB_OBJS) -lc && \
++	rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \
++	if [ -f $(SHLIB_DIR)/$(SHLIB_SONAME) ]; then \
++	  mv -f $(SHLIB_DIR)/$(SHLIB_SONAME) \
++		$(SHLIB_DIR)/$(SHLIB_SONAME).backup; \
++	else true; fi && \
++	gcc -O2 -o $(SHLIB_DIR)/$(SHLIB_SONAME).tweak \
++	  $$(gcc_srcdir)/config/ia64/change-symver.c -lelf && \
++	$(SHLIB_DIR)/$(SHLIB_SONAME).tweak $(SHLIB_DIR)/$(SHLIB_SONAME).tmp \
++	GCC_3.4.2 _GLOBAL_ \
++	_Unwind_GetGR _Unwind_RaiseException _Unwind_GetRegionStart _Unwind_SetIP \
++	_Unwind_GetIP _Unwind_GetLanguageSpecificData _Unwind_Resume \
++	_Unwind_DeleteException _Unwind_SetGR _Unwind_ForcedUnwind \
++	_Unwind_Backtrace _Unwind_FindEnclosingFunction _Unwind_GetCFA \
++	_Unwind_Resume_or_Rethrow _Unwind_GetBSP && \
++	rm -f $(SHLIB_DIR)/$(SHLIB_SONAME).tweak && \
++	mv $(SHLIB_DIR)/$(SHLIB_SONAME).tmp $(SHLIB_DIR)/$(SHLIB_SONAME) && \
++	$(LN_S) $(SHLIB_SONAME) $(SHLIB_DIR)/$(SHLIB_SOLINK)
++
++TARGET_LIBGCC2_CFLAGS += -DUSE_SYMVER_GLOBAL
+Index: gcc/config/ia64/change-symver.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/config/ia64/change-symver.c	2010-06-25 10:14:32.521880765 -0700
+@@ -0,0 +1,211 @@
++#define _GNU_SOURCE 1
++#define _FILE_OFFSET_BITS 64
++#include <endian.h>
++#include <errno.h>
++#include <error.h>
++#include <fcntl.h>
++#include <fnmatch.h>
++#include <gelf.h>
++#include <stdlib.h>
++#include <string.h>
++#include <unistd.h>
++
++int
++compute_veridx (const char *name, Elf *elf, Elf_Data *verd, GElf_Shdr *verd_shdr)
++{
++  if (strcmp (name, "_GLOBAL_") == 0)
++    return 1;
++
++  int cnt;
++  size_t offset = 0;
++  for (cnt = verd_shdr->sh_info; --cnt >= 0; )
++    {
++      GElf_Verdef defmem;
++      GElf_Verdef *def;
++      GElf_Verdaux auxmem;
++      GElf_Verdaux *aux;
++      unsigned int auxoffset;
++
++      /* Get the data at the next offset.  */
++      def = gelf_getverdef (verd, offset, &defmem);
++      if (def == NULL)
++	break;
++
++      auxoffset = offset + def->vd_aux;
++      aux = gelf_getverdaux (verd, auxoffset, &auxmem);
++      if (aux == NULL)
++	break;
++
++      if (strcmp (name, elf_strptr (elf, verd_shdr->sh_link,
++		  aux->vda_name)) == 0)
++	return def->vd_ndx;
++
++      /* Find the next offset.  */
++      offset += def->vd_next;
++    }
++
++  return -1;
++}
++
++int
++main (int argc, char **argv)
++{
++  if (argc < 4)
++    error (1, 0, "Usage: change_symver library from_symver to_symver symbol...\nExample: change_symver libfoo.so FOO_1.0 *global* bar baz");
++
++  const char *fname = argv[1];
++
++  /* Open the file.  */
++  int fd;
++  fd = open (fname, O_RDWR);
++  if (fd == -1)
++    error (1, errno, fname);
++
++  elf_version (EV_CURRENT);
++
++  /* Now get the ELF descriptor.  */
++  Elf *elf = elf_begin (fd, ELF_C_READ_MMAP, NULL);
++  if (elf == NULL || elf_kind (elf) != ELF_K_ELF)
++    error (1, 0, "Couldn't open %s: %s", fname, elf_errmsg (-1));
++
++  size_t shstrndx;
++  /* Get the section header string table index.  */
++  if (elf_getshstrndx (elf, &shstrndx) < 0)
++    error (1, 0, "cannot get shstrndx from %s", fname);
++
++  GElf_Ehdr ehdr_mem;
++  GElf_Ehdr *ehdr;
++
++  /* We need the ELF header in a few places.  */
++  ehdr = gelf_getehdr (elf, &ehdr_mem);
++  if (ehdr == NULL)
++    error (1, 0, "couldn't get ELF headers %s: %s", fname, elf_errmsg (-1));
++
++  Elf_Scn *scn = NULL;
++  GElf_Shdr shdr_mem, verd_shdr, ver_shdr, dynsym_shdr;
++  Elf_Data *ver = NULL, *verd = NULL, *dynsym = NULL;
++
++  while ((scn = elf_nextscn (elf, scn)) != NULL)
++    {
++      GElf_Shdr *shdr = gelf_getshdr (scn, &shdr_mem);
++
++      if (shdr == NULL)
++	error (1, 0, "couldn't get shdr from %s", fname);
++
++      if ((shdr->sh_flags & SHF_ALLOC) != 0)
++	{
++	  const char *name = elf_strptr (elf, shstrndx, shdr->sh_name);
++	  Elf_Data **p;
++
++	  if (strcmp (name, ".gnu.version") == 0)
++	    {
++	      p = &ver;
++	      ver_shdr = *shdr;
++	    }
++	  else if (strcmp (name, ".gnu.version_d") == 0)
++	    {
++	      p = &verd;
++	      verd_shdr = *shdr;
++	    }
++	  else if (strcmp (name, ".dynsym") == 0)
++	    {
++	      p = &dynsym;
++	      dynsym_shdr = *shdr;
++	    }
++	  else
++	    continue;
++
++	  if (*p != NULL)
++	    error (1, 0, "Two %s sections in %s", name, fname);
++	  *p = elf_getdata (scn, NULL);
++	  if (*p == NULL || elf_getdata (scn, *p) != NULL)
++	    error (1, 0, "No data or non-contiguous data in %s section in %s",
++		   name, fname);
++	}
++    }
++
++  if (ver == NULL || verd == NULL || dynsym == NULL)
++    error (1, 0, "Couldn't find one of the needed sections in %s", fname);
++
++  int from_idx = compute_veridx (argv[2], elf, verd, &verd_shdr);
++  if (from_idx == -1)
++    error (1, 0, "Could not find symbol version %s in %s", argv[2], fname);
++
++  int to_idx = compute_veridx (argv[3], elf, verd, &verd_shdr);
++  if (to_idx == -1)
++    error (1, 0, "Could not find symbol version %s in %s", argv[3], fname);
++
++  if (dynsym_shdr.sh_entsize != gelf_fsize (elf, ELF_T_SYM, 1, ehdr->e_version)
++      || dynsym_shdr.sh_size % dynsym_shdr.sh_entsize
++      || ver_shdr.sh_entsize != 2
++      || (ver_shdr.sh_size & 1)
++      || dynsym_shdr.sh_size / dynsym_shdr.sh_entsize != ver_shdr.sh_size / 2)
++    error (1, 0, "Unexpected sh_size or sh_entsize in %s", fname);
++
++  size_t nentries = ver_shdr.sh_size / 2;
++  size_t cnt;
++  GElf_Versym array[nentries];
++  for (cnt = 0; cnt < nentries; ++cnt)
++    {
++      GElf_Versym vsymmem;
++      GElf_Versym *vsym;
++
++      vsym = gelf_getversym (ver, cnt, &vsymmem);
++      if (vsym == NULL)
++	error (1, 0, "gelt_getversym failed in %s: %s", fname, elf_errmsg (-1));
++
++      array[cnt] = *vsym;
++      if (*vsym != from_idx)
++	continue;
++
++      GElf_Sym sym_mem;
++      GElf_Sym *sym;
++      sym = gelf_getsym (dynsym, cnt, &sym_mem);
++      if (sym == NULL)
++	error (1, 0, "gelt_getsym failed in %s: %s", fname, elf_errmsg (-1));
++
++      const char *name = elf_strptr (elf, dynsym_shdr.sh_link, sym->st_name);
++
++      int argn;
++      for (argn = 4; argn < argc; ++argn)
++	if (fnmatch (argv[argn], name, 0) == 0)
++	  {
++	    array[cnt] = to_idx;
++	    break;
++	  }
++    }
++
++  if (sizeof (array[0]) != 2)
++    abort ();
++
++#if __BYTE_ORDER == __LITTLE_ENDIAN
++  if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
++    ;
++  else if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
++#elif __BYTE_ORDER == __BIG_ENDIAN
++  if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
++    ;
++  else if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
++#else
++# error Unsupported endianity
++#endif
++    {
++      for (cnt = 0; cnt < nentries; ++cnt)
++	array[cnt] = ((array[cnt] & 0xff) << 8) | ((array[cnt] & 0xff00) >> 8);
++    }
++  else
++    error (1, 0, "Unknown EI_DATA %d in %s", ehdr->e_ident[EI_DATA], fname);
++
++  if (elf_end (elf) != 0)
++    error (1, 0, "couldn't close %s: %s", fname, elf_errmsg (-1));
++
++  if (lseek (fd, ver_shdr.sh_offset, SEEK_SET) != (off_t) ver_shdr.sh_offset)
++    error (1, 0, "failed to seek to %zd in %s", (size_t) ver_shdr.sh_offset,
++	   fname);
++
++  if (write (fd, array, 2 * nentries) != (ssize_t) (2 * nentries))
++    error (1, 0, "failed to write .gnu.version section into %s", fname);
++
++  close (fd);
++  return 0;
++}
+Index: gcc/config/ia64/unwind-ia64.c
+===================================================================
+--- gcc/config/ia64/unwind-ia64.c.orig	2009-09-07 08:41:52.000000000 -0700
++++ gcc/config/ia64/unwind-ia64.c	2010-06-25 10:14:32.521880765 -0700
+@@ -48,6 +48,51 @@
+ #define MD_UNW_COMPATIBLE_PERSONALITY_P(HEADER) 1
+ #endif
+ 
++#if defined (USE_SYMVER_GLOBAL) && defined (SHARED)
++extern _Unwind_Reason_Code __symverglobal_Unwind_Backtrace
++  (_Unwind_Trace_Fn, void *);
++extern void __symverglobal_Unwind_DeleteException
++  (struct _Unwind_Exception *);
++extern void * __symverglobal_Unwind_FindEnclosingFunction (void *);
++extern _Unwind_Reason_Code __symverglobal_Unwind_ForcedUnwind
++  (struct _Unwind_Exception *, _Unwind_Stop_Fn, void *);
++extern _Unwind_Word __symverglobal_Unwind_GetCFA
++  (struct _Unwind_Context *);
++extern _Unwind_Word __symverglobal_Unwind_GetBSP
++  (struct _Unwind_Context *);
++extern _Unwind_Word __symverglobal_Unwind_GetGR
++  (struct _Unwind_Context *, int );
++extern _Unwind_Ptr __symverglobal_Unwind_GetIP (struct _Unwind_Context *);
++extern void *__symverglobal_Unwind_GetLanguageSpecificData
++  (struct _Unwind_Context *);
++extern _Unwind_Ptr __symverglobal_Unwind_GetRegionStart
++  (struct _Unwind_Context *);
++extern _Unwind_Reason_Code __symverglobal_Unwind_RaiseException
++  (struct _Unwind_Exception *);
++extern void __symverglobal_Unwind_Resume (struct _Unwind_Exception *);
++extern _Unwind_Reason_Code __symverglobal_Unwind_Resume_or_Rethrow
++   (struct _Unwind_Exception *);
++extern void __symverglobal_Unwind_SetGR
++  (struct _Unwind_Context *, int, _Unwind_Word);
++extern void __symverglobal_Unwind_SetIP
++  (struct _Unwind_Context *, _Unwind_Ptr);
++#define _Unwind_Backtrace __symverglobal_Unwind_Backtrace
++#define _Unwind_DeleteException __symverglobal_Unwind_DeleteException
++#define _Unwind_FindEnclosingFunction __symverglobal_Unwind_FindEnclosingFunction
++#define _Unwind_ForcedUnwind __symverglobal_Unwind_ForcedUnwind
++#define _Unwind_GetBSP __symverglobal_Unwind_GetBSP
++#define _Unwind_GetCFA __symverglobal_Unwind_GetCFA
++#define _Unwind_GetGR __symverglobal_Unwind_GetGR
++#define _Unwind_GetIP __symverglobal_Unwind_GetIP
++#define _Unwind_GetLanguageSpecificData __symverglobal_Unwind_GetLanguageSpecificData
++#define _Unwind_GetRegionStart __symverglobal_Unwind_GetRegionStart
++#define _Unwind_RaiseException __symverglobal_Unwind_RaiseException
++#define _Unwind_Resume __symverglobal_Unwind_Resume
++#define _Unwind_Resume_or_Rethrow __symverglobal_Unwind_Resume_or_Rethrow
++#define _Unwind_SetGR __symverglobal_Unwind_SetGR
++#define _Unwind_SetIP __symverglobal_Unwind_SetIP
++#endif
++
+ enum unw_application_register
+ {
+   UNW_AR_BSP,
+@@ -2457,4 +2502,44 @@
+ alias (_Unwind_SetIP);
+ #endif
+ 
++#if defined (USE_SYMVER_GLOBAL) && defined (SHARED)
++#undef alias
++#define symverglobal(name, version) \
++__typeof (__symverglobal##name) __symverlocal##name		\
++  __attribute__ ((alias ("__symverglobal" #name)));		\
++__asm__ (".symver __symverglobal" #name"," #name "@@GCC_3.4.2");\
++__asm__ (".symver __symverlocal" #name"," #name "@" #version)
++
++#undef _Unwind_Backtrace
++#undef _Unwind_DeleteException
++#undef _Unwind_FindEnclosingFunction
++#undef _Unwind_ForcedUnwind
++#undef _Unwind_GetBSP
++#undef _Unwind_GetCFA
++#undef _Unwind_GetGR
++#undef _Unwind_GetIP
++#undef _Unwind_GetLanguageSpecificData
++#undef _Unwind_GetRegionStart
++#undef _Unwind_RaiseException
++#undef _Unwind_Resume
++#undef _Unwind_Resume_or_Rethrow
++#undef _Unwind_SetGR
++#undef _Unwind_SetIP
++symverglobal (_Unwind_Backtrace, GCC_3.3);
++symverglobal (_Unwind_DeleteException, GCC_3.0);
++symverglobal (_Unwind_FindEnclosingFunction, GCC_3.3);
++symverglobal (_Unwind_ForcedUnwind, GCC_3.0);
++symverglobal (_Unwind_GetBSP, GCC_3.3.2);
++symverglobal (_Unwind_GetCFA, GCC_3.3);
++symverglobal (_Unwind_GetGR, GCC_3.0);
++symverglobal (_Unwind_GetIP, GCC_3.0);
++symverglobal (_Unwind_GetLanguageSpecificData, GCC_3.0);
++symverglobal (_Unwind_GetRegionStart, GCC_3.0);
++symverglobal (_Unwind_RaiseException, GCC_3.0);
++symverglobal (_Unwind_Resume, GCC_3.0);
++symverglobal (_Unwind_Resume_or_Rethrow, GCC_3.3);
++symverglobal (_Unwind_SetGR, GCC_3.0);
++symverglobal (_Unwind_SetIP, GCC_3.0);
++#endif
++
+ #endif
+Index: gcc/config/ia64/mkmap-symver-multi.awk
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/config/ia64/mkmap-symver-multi.awk	2010-06-25 10:14:32.521880765 -0700
+@@ -0,0 +1,133 @@
++# Generate an ELF symbol version map a-la Solaris and GNU ld.
++#	Contributed by Richard Henderson <rth@cygnus.com>
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify it under
++# the terms of the GNU General Public License as published by the Free
++# Software Foundation; either version 2, or (at your option) any later
++# version.
++#
++# GCC is distributed in the hope that it will be useful, but WITHOUT
++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++# License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING.  If not, write to the Free
++# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
++# 02110-1301, USA.
++
++BEGIN {
++  state = "nm";
++  sawsymbol = 0;
++}
++
++# Remove comment and blank lines.
++/^ *#/ || /^ *$/ {
++  next;
++}
++
++# We begin with nm input.  Collect the set of symbols that are present
++# so that we can not emit them into the final version script -- Solaris
++# complains at us if we do.
++
++state == "nm" && /^%%/ {
++  state = "ver";
++  next;
++}
++
++state == "nm" && ($1 == "U" || $2 == "U") {
++  next;
++}
++
++state == "nm" && NF == 3 {
++  if ($3 ~ /^[^@]*@GCC_[0-9.]*$/) {
++    def[$3] = 1
++    tl=$3
++    sub(/^.*@/,"",tl)
++    ver[$3] = tl
++  } else {
++    sub(/@@?GCC_[0-9.]*$/,"",$3)
++    def[$3] = 1;
++  }
++  sawsymbol = 1;
++  next;
++}
++
++state == "nm" {
++  next;
++}
++
++# Now we process a simplified variant of the Solaris symbol version
++# script.  We have one symbol per line, no semicolons, simple markers
++# for beginning and ending each section, and %inherit markers for
++# describing version inheritence.  A symbol may appear in more than
++# one symbol version, and the last seen takes effect.
++
++NF == 3 && $1 == "%inherit" {
++  inherit[$2] = $3;
++  next;
++}
++
++NF == 2 && $2 == "{" {
++  libs[$1] = 1;
++  thislib = $1;
++  next;
++}
++
++$1 == "}" {
++  thislib = "";
++  next;
++}
++
++{
++  ver[$1] = thislib;
++  next;
++}
++
++END {
++  if (!sawsymbol)
++    {
++      print "No symbols seen -- broken or mis-installed nm?" | "cat 1>&2";
++      exit 1;
++    }
++  for (l in libs)
++    output(l);
++}
++
++function output(lib) {
++  if (done[lib])
++    return;
++  done[lib] = 1;
++  if (inherit[lib])
++    output(inherit[lib]);
++
++  empty=1
++  for (sym in ver)
++    if ((ver[sym] == lib) && (sym in def))
++      {
++	if (empty)
++	  {
++	    printf("%s {\n", lib);
++	    printf("  global:\n");
++	    empty = 0;
++	  }
++	symp = sym;
++	sub(/@GCC_[0-9.]*$/,"",symp);
++	printf("\t%s;\n", symp);
++	if (dotsyms)
++	  printf("\t.%s;\n", symp);
++      }
++
++  if (empty)
++    {
++      for (l in libs)
++	if (inherit[l] == lib)
++	  inherit[l] = inherit[lib];
++    }
++  else if (inherit[lib])
++    printf("} %s;\n", inherit[lib]);
++  else
++    printf ("\n  local:\n\t*;\n};\n");
++}
+Index: gcc/config/ia64/libgcc-ia64-no-libunwind.ver
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/config/ia64/libgcc-ia64-no-libunwind.ver	2010-06-25 10:14:32.525880902 -0700
+@@ -0,0 +1,17 @@
++GCC_3.4.2 {
++  _Unwind_GetGR
++  _Unwind_RaiseException
++  _Unwind_GetRegionStart
++  _Unwind_SetIP
++  _Unwind_GetIP
++  _Unwind_GetLanguageSpecificData
++  _Unwind_Resume
++  _Unwind_DeleteException
++  _Unwind_SetGR
++  _Unwind_ForcedUnwind
++  _Unwind_Backtrace
++  _Unwind_FindEnclosingFunction
++  _Unwind_GetCFA
++  _Unwind_Resume_or_Rethrow
++  _Unwind_GetBSP
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch
new file mode 100644
index 0000000000..de14a50018
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch
@@ -0,0 +1,19 @@
+2008-01-25  Jakub Jelinek  <jakub@redhat.com>
+
+	* lang.c (java_classify_record): Revert 2007-12-20 change.
+
+Index: gcc/java/lang.c
+===================================================================
+--- gcc/java/lang.c.orig	2010-01-20 00:17:00.000000000 -0800
++++ gcc/java/lang.c	2010-06-25 10:28:46.569383189 -0700
+@@ -881,9 +881,7 @@
+   if (! CLASS_P (type))
+     return RECORD_IS_STRUCT;
+ 
+-  /* ??? GDB does not support DW_TAG_interface_type as of December,
+-     2007.  Re-enable this at a later time.  */
+-  if (0 && CLASS_INTERFACE (TYPE_NAME (type)))
++  if (CLASS_INTERFACE (TYPE_NAME (type)))
+     return RECORD_IS_INTERFACE;
+ 
+   return RECORD_IS_CLASS;
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch
new file mode 100644
index 0000000000..3cb10f3c23
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch
@@ -0,0 +1,48 @@
+Index: libjava/configure.ac
+===================================================================
+--- libjava/configure.ac.orig	2010-03-21 12:41:37.000000000 -0700
++++ libjava/configure.ac	2010-06-25 10:17:47.489886278 -0700
+@@ -139,6 +139,13 @@
+ 	[allow rebuilding of .class and .h files]))
+ AM_CONDITIONAL(JAVA_MAINTAINER_MODE, test "$enable_java_maintainer_mode" = yes)
+ 
++AC_ARG_ENABLE(libjava-multilib,
++	AS_HELP_STRING([--enable-libjava-multilib], [build libjava as multilib]))
++if test "$enable_libjava_multilib" = no; then
++  multilib=no
++  ac_configure_args="$ac_configure_args --disable-multilib"
++fi
++
+ # It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX.
+ GCC_NO_EXECUTABLES
+ 
+Index: libjava/configure
+===================================================================
+--- libjava/configure.orig	2010-04-02 11:18:06.000000000 -0700
++++ libjava/configure	2010-06-25 10:17:47.516381209 -0700
+@@ -1609,6 +1609,8 @@
+                           default=yes
+   --enable-java-maintainer-mode
+                           allow rebuilding of .class and .h files
++  --enable-libjava-multilib
++                          build libjava as multilib
+   --disable-dependency-tracking  speeds up one-time build
+   --enable-dependency-tracking   do not reject slow dependency extractors
+   --enable-maintainer-mode  enable make rules and dependencies not useful
+@@ -3346,6 +3348,16 @@
+ fi
+ 
+ 
++# Check whether --enable-libjava-multilib was given.
++if test "${enable_libjava_multilib+set}" = set; then
++  enableval=$enable_libjava_multilib;
++fi
++
++if test "$enable_libjava_multilib" = no; then
++  multilib=no
++  ac_configure_args="$ac_configure_args --disable-multilib"
++fi
++
+ # It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX.
+ 
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch
new file mode 100644
index 0000000000..da85e556ec
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch
@@ -0,0 +1,2797 @@
+2008-03-28  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/linux/sparc/futex.h (atomic_write_barrier): Fix membar
+	argument.
+
+2008-03-27  Jakub Jelinek  <jakub@redhat.com>
+
+	* libgomp.h (struct gomp_team_state): Remove single_count field
+	ifndef HAVE_SYNC_BUILTINS.
+	(struct gomp_team): Likewise.  Add work_share_list_free_lock
+	ifndef HAVE_SYNC_BUILTINS.
+	* team.c (gomp_new_team): If HAVE_SYNC_BUILTINS is not defined,
+	don't initialize single_count, but instead initialize
+	work_share_list_free_lock.
+	(free_team): Destroy work_share_list_free_lock ifndef
+	HAVE_SYNC_BUILTINS.
+	(gomp_team_start): Don't initialize ts.single_count ifndef
+	HAVE_SYNC_BUILTINS.
+	* work.c (alloc_work_share, free_work_share): Use
+	work_share_list_free_lock instead of atomic chaining ifndef
+	HAVE_SYNC_BUILTINS.
+
+2008-03-26  Jakub Jelinek  <jakub@redhat.com>
+
+	* loop.c (gomp_loop_init): Fix GFS_DYNAMIC ws->mode setting.
+	* testsuite/libgomp.c/loop-4.c: New test.
+
+	* libgomp.h (struct gomp_team_state): Add single_count field.
+	(struct gomp_team): Likewise.
+	* team.c (gomp_new_team): Clear single_count.
+	(gomp_team_start): Likewise.
+	* single.c (GOMP_single_start): Rewritten if HAVE_SYNC_BUILTINS.
+
+2008-03-25  Jakub Jelinek  <jakub@redhat.com>
+
+	* team.c (gomp_thread_start): Don't clear ts.static_trip here.
+	* loop.c (gomp_loop_static_start, gomp_loop_dynamic_start): Clear
+	ts.static_trip here.
+	* work.c (gomp_work_share_start): Don't clear ts.static_trip here.
+
+2008-03-21  Jakub Jelinek  <jakub@redhat.com>
+
+	* libgomp.h: Include ptrlock.h.
+	(struct gomp_work_share): Reshuffle fields.  Add next_alloc,
+	next_ws, next_free and inline_ordered_team_ids fields, change
+	ordered_team_ids into pointer from flexible array member.
+	(struct gomp_team_state): Add last_work_share field, remove
+	work_share_generation.
+	(struct gomp_team): Remove work_share_lock, generation_mask,
+	oldest_live_gen, num_live_gen and init_work_shares fields, add
+	work work_share_list_alloc, work_share_list_free and work_share_chunk
+	fields.  Change work_shares from pointer to pointers into an array.
+	(gomp_new_team): New prototype.
+	(gomp_team_start): Change type of last argument.
+	(gomp_new_work_share): Removed.
+	(gomp_init_work_share, gomp_fini_work_share): New prototypes.
+	(gomp_work_share_init_done): New static inline.
+	* team.c (gomp_thread_start): Clear ts.last_work_share, don't clear
+	ts.work_share_generation.
+	(new_team): Removed.
+	(gomp_new_team): New function.
+	(free_team): Free gomp_work_share blocks chained through next_alloc,
+	instead of freeing work_shares and destroying work_share_lock.
+	(gomp_team_start): Change last argument from ws to team, don't create
+	new team, set ts.work_share to &team->work_shares[0] and clear
+	ts.last_work_share.  Don't clear ts.work_share_generation.
+	(gomp_team_end): Call gomp_fini_work_share.
+	* work.c (gomp_new_work_share): Removed.
+	(alloc_work_share, gomp_init_work_share, gomp_fini_work_share): New
+	functions.
+	(free_work_share): Add team argument.  Call gomp_fini_work_share
+	and then either free ws if orphaned, or put it into
+	work_share_list_free list of the current team.
+	(gomp_work_share_start, gomp_work_share_end,
+	gomp_work_share_end_nowait): Rewritten.
+	* sections.c (GOMP_sections_start): Call gomp_work_share_init_done
+	after gomp_sections_init.  If HAVE_SYNC_BUILTINS, call
+	gomp_iter_dynamic_next instead of the _locked variant and don't take
+	lock around it, otherwise acquire it before calling
+	gomp_iter_dynamic_next_locked.
+	(GOMP_sections_next): If HAVE_SYNC_BUILTINS, call
+	gomp_iter_dynamic_next instead of the _locked variant and don't take
+	lock around it.
+	(GOMP_parallel_sections_start): Call gomp_new_team instead of
+	gomp_new_work_share.  Call gomp_sections_init on &team->work_shares[0].
+	Adjust gomp_team_start caller.
+	* loop.c (gomp_loop_static_start, gomp_loop_ordered_static_start): Call
+	gomp_work_share_init_done after gomp_loop_init.  Don't unlock ws->lock.
+	(gomp_loop_dynamic_start, gomp_loop_guided_start): Call
+	gomp_work_share_init_done after gomp_loop_init.  If HAVE_SYNC_BUILTINS,
+	don't unlock ws->lock, otherwise lock it.
+	(gomp_loop_ordered_dynamic_start, gomp_loop_ordered_guided_start): Call
+	gomp_work_share_init_done after gomp_loop_init.  Lock ws->lock.
+	(gomp_parallel_loop_start): Call gomp_new_team instead of
+	gomp_new_work_share.  Call gomp_loop_init on &team->work_shares[0].
+	Adjust gomp_team_start caller.
+	* single.c (GOMP_single_start, GOMP_single_copy_start): Call
+	gomp_work_share_init_done if gomp_work_share_start returned true.
+	Don't unlock ws->lock.
+	* parallel.c (GOMP_parallel_start): Call gomp_new_team and pass that
+	as last argument to gomp_team_start.
+	* config/linux/ptrlock.c: New file.
+	* config/linux/ptrlock.h: New file.
+	* config/posix/ptrlock.c: New file.
+	* config/posix/ptrlock.h: New file.
+	* Makefile.am (libgomp_la_SOURCES): Add ptrlock.c.
+	* Makefile.in: Regenerated.
+	* testsuite/Makefile.in: Regenerated.
+
+2008-03-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* libgomp.h (gomp_active_wait_policy): Remove decl.
+	(gomp_throttled_spin_count_var, gomp_available_cpus,
+	gomp_managed_threads): New extern decls.
+	* team.c (gomp_team_start, gomp_team_end): If number of threads
+	changed, adjust atomically gomp_managed_threads.
+	* env.c (gomp_active_wait_policy, gomp_block_time_var): Remove.
+	(gomp_throttled_spin_count_var, gomp_available_cpus,
+	gomp_managed_threads): New variables.
+	(parse_millis): Removed.
+	(parse_spincount): New function.
+	(parse_wait_policy): Return -1/0/1 instead of setting
+	gomp_active_wait_policy.
+	(initialize_env): Call gomp_init_num_threads unconditionally.
+	Initialize gomp_available_cpus.  Call parse_spincount instead
+	of parse_millis, initialize gomp_{,throttled_}spin_count_var
+	depending on presence and value of OMP_WAIT_POLICY and
+	GOMP_SPINCOUNT env vars.
+	* config/linux/wait.h (do_wait): Use gomp_throttled_spin_count_var
+	instead of gomp_spin_count_var if gomp_managed_threads >
+	gomp_available_cpus.
+
+	* config/linux/wait.h: Include errno.h.
+	(FUTEX_WAIT, FUTEX_WAKE, FUTEX_PRIVATE_FLAG): Define.
+	(gomp_futex_wake, gomp_futex_wait): New extern decls.
+	* config/linux/mutex.c (gomp_futex_wake, gomp_futex_wait): New
+	variables.
+	* config/linux/powerpc/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove.
+	(sys_futex0): Return error code.
+	(futex_wake, futex_wait): If ENOSYS was returned, clear
+	FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry.
+	* config/linux/alpha/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove.
+	(futex_wake, futex_wait): If ENOSYS was returned, clear
+	FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry.
+	* config/linux/x86/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove.
+	(sys_futex0): Return error code.
+	(futex_wake, futex_wait): If ENOSYS was returned, clear
+	FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry.
+	* config/linux/s390/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove.
+	(sys_futex0): Return error code.
+	(futex_wake, futex_wait): If ENOSYS was returned, clear
+	FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry.
+	* config/linux/ia64/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove.
+	(sys_futex0): Return error code.
+	(futex_wake, futex_wait): If ENOSYS was returned, clear
+	FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry.
+	* config/linux/sparc/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove.
+	(sys_futex0): Return error code.
+	(futex_wake, futex_wait): If ENOSYS was returned, clear
+	FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry.
+
+2008-03-18  Jakub Jelinek  <jakub@redhat.com>
+
+	* libgomp.h (struct gomp_work_share): Add mode field.  Put lock and
+	next into a different cache line from most of the write-once fields.
+	* loop.c: Include limits.h.
+	(gomp_loop_init): For GFS_DYNAMIC, multiply ws->chunk_size by incr.
+	If adding ws->chunk_size nthreads + 1 times after end won't
+	overflow, set ws->mode to 1.
+	* iter.c (gomp_iter_dynamic_next_locked): Don't multiply
+	ws->chunk_size by incr.
+	(gomp_iter_dynamic_next): Likewise.  If ws->mode, use more efficient
+	code.
+	* work.c: Include stddef.h.
+	(gomp_new_work_share): Use offsetof rather than sizeof.
+
+2008-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* libgomp.h (struct gomp_team): Change ordered_release field
+	into gomp_sem_t ** from flexible array member.  Add implicit_task
+	and initial_work_shares fields.
+	(gomp_new_task): Removed.
+	(gomp_init_task): New prototype.
+	* team.c (new_team): Allocate implicit_task for each thread
+	and initial work_shares together with gomp_team allocation.
+	(free_team): Only free work_shares if it is not init_work_shares.
+	(gomp_team_start): Use gomp_init_task instead of gomp_new_task,
+	set thr->task to the corresponding implicit_task array entry.
+	* task.c (gomp_new_task): Removed.
+	(gomp_init_task): New function.
+	(gomp_end_task): Don't free the task.
+	(GOMP_task): Allocate struct gomp_task on the stack, call
+	gomp_init_task rather than gomp_new_task.
+	* work.c (gomp_work_share_start): If work_shares ==
+	init_work_shares, gomp_malloc + memcpy rather than gomp_realloc.
+
+2008-03-15  Jakub Jelinek  <jakub@redhat.com>
+	    Ulrich Drepper  <drepper@redhat.com>
+
+	* config/linux/bar.h (gomp_barrier_state_t): Rewritten.
+	(gomp_barrier_state_t): Change to unsigned int.
+	(gomp_barrier_init, gomp_barrier_reinit, gomp_barrier_destroy,
+	gomp_barrier_wait_start, gomp_barrier_last_thread): Rewritten.
+	(gomp_barrier_wait_last): Prototype rather than inline.
+	* config/linux/bar.c (gomp_barrier_wait_end): Rewritten.
+	(gomp_barrier_wait_last): New function.
+
+2008-03-15  Jakub Jelinek  <jakub@redhat.com>
+
+	* team.c (gomp_thread_start): Use gomp_barrier_wait_last instead
+	of gomp_barrier_wait.
+	* env.c (gomp_block_time_var, gomp_spin_count_var): New variables.
+	(parse_millis): New function.
+	(initialize_env): Handle GOMP_BLOCKTIME env var.
+	* libgomp.h (struct gomp_team): Move close to the end of the struct.
+	(gomp_spin_count_var): New extern var decl.
+	* work.c (gomp_work_share_end): Use gomp_barrier_state_t bstate
+	var instead of bool last, call gomp_barrier_last_thread to check
+	for last thread, pass bstate to gomp_barrier_wait_end.
+	* config/linux/wait.h: New file.
+	* config/linux/mutex.c: Include wait.h instead of libgomp.h and
+	futex.h.
+	(gomp_mutex_lock_slow): Call do_wait instead of futex_wait.
+	* config/linux/bar.c: Include wait.h instead of libgomp.h and
+	futex.h.
+	(gomp_barrier_wait_end): Change second argument to
+	gomp_barrier_state_t.  Call do_wait instead of futex_wait.
+	* config/linux/sem.c: Include wait.h instead of libgomp.h and
+	futex.h.
+	(gomp_sem_wait_slow): Call do_wait instead of futex_wait.
+	* config/linux/lock.c: Include wait.h instead of libgomp.h and
+	futex.h.
+	(gomp_set_nest_lock_25): Call do_wait instead of futex_wait.
+	* config/linux/affinity.c: Assume HAVE_SYNC_BUILTINS.
+	* config/linux/bar.h (gomp_barrier_state_t): New typedef.
+	(gomp_barrier_wait_end): Change second argument to
+	gomp_barrier_state_t.
+	(gomp_barrier_wait_start): Return gomp_barrier_state_t.
+	(gomp_barrier_last_thread, gomp_barrier_wait_last): New static
+	inlines.
+	* config/linux/powerpc/futex.h (cpu_relax, atomic_write_barrier): New
+	static inlines.
+	* config/linux/alpha/futex.h (cpu_relax, atomic_write_barrier):
+	Likewise.
+	* config/linux/x86/futex.h (cpu_relax, atomic_write_barrier):
+	Likewise.
+	* config/linux/s390/futex.h (cpu_relax, atomic_write_barrier):
+	Likewise.
+	* config/linux/ia64/futex.h (cpu_relax, atomic_write_barrier):
+	Likewise.
+	* config/linux/sparc/futex.h (cpu_relax, atomic_write_barrier):
+	Likewise.
+	* config/posix/bar.c (gomp_barrier_wait_end): Change second argument
+	to gomp_barrier_state_t.
+	* config/posix/bar.h (gomp_barrier_state_t): New typedef.
+	(gomp_barrier_wait_end): Change second argument to
+	gomp_barrier_state_t.
+	(gomp_barrier_wait_start): Return gomp_barrier_state_t.
+	(gomp_barrier_last_thread, gomp_barrier_wait_last): New static
+	inlines.
+
+--- libgomp/parallel.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/parallel.c	2008-03-26 15:32:06.000000000 +0100
+@@ -68,7 +68,7 @@ void
+ GOMP_parallel_start (void (*fn) (void *), void *data, unsigned num_threads)
+ {
+   num_threads = gomp_resolve_num_threads (num_threads);
+-  gomp_team_start (fn, data, num_threads, NULL);
++  gomp_team_start (fn, data, num_threads, gomp_new_team (num_threads));
+ }
+ 
+ void
+--- libgomp/sections.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/sections.c	2008-03-26 15:33:06.000000000 +0100
+@@ -59,14 +59,24 @@ GOMP_sections_start (unsigned count)
+   long s, e, ret;
+ 
+   if (gomp_work_share_start (false))
+-    gomp_sections_init (thr->ts.work_share, count);
++    {
++      gomp_sections_init (thr->ts.work_share, count);
++      gomp_work_share_init_done ();
++    }
+ 
++#ifdef HAVE_SYNC_BUILTINS
++  if (gomp_iter_dynamic_next (&s, &e))
++    ret = s;
++  else
++    ret = 0;
++#else
++  gomp_mutex_lock (&thr->ts.work_share->lock);
+   if (gomp_iter_dynamic_next_locked (&s, &e))
+     ret = s;
+   else
+     ret = 0;
+-
+   gomp_mutex_unlock (&thr->ts.work_share->lock);
++#endif
+ 
+   return ret;
+ }
+@@ -83,15 +93,23 @@ GOMP_sections_start (unsigned count)
+ unsigned
+ GOMP_sections_next (void)
+ {
+-  struct gomp_thread *thr = gomp_thread ();
+   long s, e, ret;
+ 
++#ifdef HAVE_SYNC_BUILTINS
++  if (gomp_iter_dynamic_next (&s, &e))
++    ret = s;
++  else
++    ret = 0;
++#else
++  struct gomp_thread *thr = gomp_thread ();
++
+   gomp_mutex_lock (&thr->ts.work_share->lock);
+   if (gomp_iter_dynamic_next_locked (&s, &e))
+     ret = s;
+   else
+     ret = 0;
+   gomp_mutex_unlock (&thr->ts.work_share->lock);
++#endif
+ 
+   return ret;
+ }
+@@ -103,15 +121,15 @@ void
+ GOMP_parallel_sections_start (void (*fn) (void *), void *data,
+ 			      unsigned num_threads, unsigned count)
+ {
+-  struct gomp_work_share *ws;
++  struct gomp_team *team;
+ 
+   num_threads = gomp_resolve_num_threads (num_threads);
+   if (gomp_dyn_var && num_threads > count)
+     num_threads = count;
+ 
+-  ws = gomp_new_work_share (false, num_threads);
+-  gomp_sections_init (ws, count);
+-  gomp_team_start (fn, data, num_threads, ws);
++  team = gomp_new_team (num_threads);
++  gomp_sections_init (&team->work_shares[0], count);
++  gomp_team_start (fn, data, num_threads, team);
+ }
+ 
+ /* The GOMP_section_end* routines are called after the thread is told
+--- libgomp/env.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/env.c	2008-03-26 16:40:26.000000000 +0100
+@@ -44,6 +44,11 @@ enum gomp_schedule_type gomp_run_sched_v
+ unsigned long gomp_run_sched_chunk = 1;
+ unsigned short *gomp_cpu_affinity;
+ size_t gomp_cpu_affinity_len;
++#ifndef HAVE_SYNC_BUILTINS
++gomp_mutex_t gomp_remaining_threads_lock;
++#endif
++unsigned long gomp_available_cpus = 1, gomp_managed_threads = 1;
++unsigned long long gomp_spin_count_var, gomp_throttled_spin_count_var;
+ 
+ /* Parse the OMP_SCHEDULE environment variable.  */
+ 
+@@ -147,6 +152,79 @@ parse_unsigned_long (const char *name, u
+   return false;
+ }
+ 
++/* Parse the GOMP_SPINCOUNT environment varible.  Return true if one was
++   present and it was successfully parsed.  */
++
++static bool
++parse_spincount (const char *name, unsigned long long *pvalue)
++{
++  char *env, *end;
++  unsigned long long value, mult = 1;
++
++  env = getenv (name);
++  if (env == NULL)
++    return false;
++
++  while (isspace ((unsigned char) *env))
++    ++env;
++  if (*env == '\0')
++    goto invalid;
++
++  if (strncasecmp (env, "infinite", 8) == 0
++      || strncasecmp (env, "infinity", 8) == 0)
++    {
++      value = ~0ULL;
++      end = env + 8;
++      goto check_tail;
++    }
++
++  errno = 0;
++  value = strtoull (env, &end, 10);
++  if (errno)
++    goto invalid;
++
++  while (isspace ((unsigned char) *end))
++    ++end;
++  if (*end != '\0')
++    {
++      switch (tolower (*end))
++	{
++	case 'k':
++	  mult = 1000LL;
++	  break;
++	case 'm':
++	  mult = 1000LL * 1000LL;
++	  break;
++	case 'g':
++	  mult = 1000LL * 1000LL * 1000LL;
++	  break;
++	case 't':
++	  mult = 1000LL * 1000LL * 1000LL * 1000LL;
++	  break;
++	default:
++	  goto invalid;
++	}
++      ++end;
++     check_tail:
++      while (isspace ((unsigned char) *end))
++	++end;
++      if (*end != '\0')
++	goto invalid;
++    }
++
++  if (value > ~0ULL / mult)
++    value = ~0ULL;
++  else
++    value *= mult;
++
++  *pvalue = value;
++  return true;
++
++ invalid:
++  gomp_error ("Invalid value for environment variable %s", name);
++  return false;
++}
++
+ /* Parse a boolean value for environment variable NAME and store the 
+    result in VALUE.  */
+ 
+@@ -281,10 +359,25 @@ initialize_env (void)
+   parse_schedule ();
+   parse_boolean ("OMP_DYNAMIC", &gomp_dyn_var);
+   parse_boolean ("OMP_NESTED", &gomp_nest_var);
++  gomp_init_num_threads ();
++  gomp_available_cpus = gomp_nthreads_var;
+   if (!parse_unsigned_long ("OMP_NUM_THREADS", &gomp_nthreads_var))
+-    gomp_init_num_threads ();
++    gomp_nthreads_var = gomp_available_cpus;
+   if (parse_affinity ())
+     gomp_init_affinity ();
++  if (!parse_spincount ("GOMP_SPINCOUNT", &gomp_spin_count_var))
++    {
++      /* Using a rough estimation of 100000 spins per msec,
++	 use 200 msec blocking.
++	 Depending on the CPU speed, this can be e.g. 5 times longer
++	 or 5 times shorter.  */
++      gomp_spin_count_var = 20000000LL;
++    }
++  /* gomp_throttled_spin_count_var is used when there are more libgomp
++     managed threads than available CPUs.  Use very short spinning.  */
++  gomp_throttled_spin_count_var = 100LL;
++  if (gomp_throttled_spin_count_var > gomp_spin_count_var)
++    gomp_throttled_spin_count_var = gomp_spin_count_var;
+ 
+   /* Not strictly environment related, but ordering constructors is tricky.  */
+   pthread_attr_init (&gomp_thread_attr);
+--- libgomp/libgomp.h.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/libgomp.h	2008-03-27 12:21:51.000000000 +0100
+@@ -50,6 +50,7 @@
+ #include "sem.h"
+ #include "mutex.h"
+ #include "bar.h"
++#include "ptrlock.h"
+ 
+ 
+ /* This structure contains the data to control one work-sharing construct,
+@@ -70,6 +71,8 @@ struct gomp_work_share
+      If this is a SECTIONS construct, this value will always be DYNAMIC.  */
+   enum gomp_schedule_type sched;
+ 
++  int mode;
++
+   /* This is the chunk_size argument to the SCHEDULE clause.  */
+   long chunk_size;
+ 
+@@ -81,17 +84,38 @@ struct gomp_work_share
+      is always 1.  */
+   long incr;
+ 
+-  /* This lock protects the update of the following members.  */
+-  gomp_mutex_t lock;
++  /* This is a circular queue that details which threads will be allowed
++     into the ordered region and in which order.  When a thread allocates
++     iterations on which it is going to work, it also registers itself at
++     the end of the array.  When a thread reaches the ordered region, it
++     checks to see if it is the one at the head of the queue.  If not, it
++     blocks on its RELEASE semaphore.  */
++  unsigned *ordered_team_ids;
+ 
+-  union {
+-    /* This is the next iteration value to be allocated.  In the case of
+-       GFS_STATIC loops, this the iteration start point and never changes.  */
+-    long next;
++  /* This is the number of threads that have registered themselves in
++     the circular queue ordered_team_ids.  */
++  unsigned ordered_num_used;
+ 
+-    /* This is the returned data structure for SINGLE COPYPRIVATE.  */
+-    void *copyprivate;
+-  };
++  /* This is the team_id of the currently acknowledged owner of the ordered
++     section, or -1u if the ordered section has not been acknowledged by
++     any thread.  This is distinguished from the thread that is *allowed*
++     to take the section next.  */
++  unsigned ordered_owner;
++
++  /* This is the index into the circular queue ordered_team_ids of the
++     current thread that's allowed into the ordered reason.  */
++  unsigned ordered_cur;
++
++  /* This is a chain of allocated gomp_work_share blocks, valid only
++     in the first gomp_work_share struct in the block.  */
++  struct gomp_work_share *next_alloc;
++
++  /* The above fields are written once during workshare initialization,
++     or related to ordered worksharing.  Make sure the following fields
++     are in a different cache line.  */
++
++  /* This lock protects the update of the following members.  */
++  gomp_mutex_t lock __attribute__((aligned (64)));
+ 
+   /* This is the count of the number of threads that have exited the work
+      share construct.  If the construct was marked nowait, they have moved on
+@@ -99,27 +123,28 @@ struct gomp_work_share
+      of the team to exit the work share construct must deallocate it.  */
+   unsigned threads_completed;
+ 
+-  /* This is the index into the circular queue ordered_team_ids of the 
+-     current thread that's allowed into the ordered reason.  */
+-  unsigned ordered_cur;
++  union {
++    /* This is the next iteration value to be allocated.  In the case of
++       GFS_STATIC loops, this the iteration start point and never changes.  */
++    long next;
+ 
+-  /* This is the number of threads that have registered themselves in
+-     the circular queue ordered_team_ids.  */
+-  unsigned ordered_num_used;
++    /* This is the returned data structure for SINGLE COPYPRIVATE.  */
++    void *copyprivate;
++  };
+ 
+-  /* This is the team_id of the currently acknoledged owner of the ordered
+-     section, or -1u if the ordered section has not been acknowledged by
+-     any thread.  This is distinguished from the thread that is *allowed*
+-     to take the section next.  */
+-  unsigned ordered_owner;
++  union {
++    /* Link to gomp_work_share struct for next work sharing construct
++       encountered after this one.  */
++    gomp_ptrlock_t next_ws;
++
++    /* gomp_work_share structs are chained in the free work share cache
++       through this.  */
++    struct gomp_work_share *next_free;
++  };
+ 
+-  /* This is a circular queue that details which threads will be allowed
+-     into the ordered region and in which order.  When a thread allocates
+-     iterations on which it is going to work, it also registers itself at
+-     the end of the array.  When a thread reaches the ordered region, it
+-     checks to see if it is the one at the head of the queue.  If not, it
+-     blocks on its RELEASE semaphore.  */
+-  unsigned ordered_team_ids[];
++  /* If only few threads are in the team, ordered_team_ids can point
++     to this array which fills the padding at the end of this struct.  */
++  unsigned inline_ordered_team_ids[0];
+ };
+ 
+ /* This structure contains all of the thread-local data associated with 
+@@ -133,21 +158,24 @@ struct gomp_team_state
+ 
+   /* This is the work share construct which this thread is currently
+      processing.  Recall that with NOWAIT, not all threads may be 
+-     processing the same construct.  This value is NULL when there
+-     is no construct being processed.  */
++     processing the same construct.  */
+   struct gomp_work_share *work_share;
+ 
++  /* This is the previous work share construct or NULL if there wasn't any.
++     When all threads are done with the current work sharing construct,
++     the previous one can be freed.  The current one can't, as its
++     next_ws field is used.  */
++  struct gomp_work_share *last_work_share;
++
+   /* This is the ID of this thread within the team.  This value is
+      guaranteed to be between 0 and N-1, where N is the number of
+      threads in the team.  */
+   unsigned team_id;
+ 
+-  /* The work share "generation" is a number that increases by one for
+-     each work share construct encountered in the dynamic flow of the
+-     program.  It is used to find the control data for the work share
+-     when encountering it for the first time.  This particular number
+-     reflects the generation of the work_share member of this struct.  */
+-  unsigned work_share_generation;
++#ifdef HAVE_SYNC_BUILTINS
++  /* Number of single stmts encountered.  */
++  unsigned long single_count;
++#endif
+ 
+   /* For GFS_RUNTIME loops that resolved to GFS_STATIC, this is the
+      trip number through the loop.  So first time a particular loop
+@@ -163,41 +191,53 @@ struct gomp_team_state
+ 
+ struct gomp_team
+ {
+-  /* This lock protects access to the following work shares data structures.  */
+-  gomp_mutex_t work_share_lock;
+-
+-  /* This is a dynamically sized array containing pointers to the control
+-     structs for all "live" work share constructs.  Here "live" means that
+-     the construct has been encountered by at least one thread, and not
+-     completed by all threads.  */
+-  struct gomp_work_share **work_shares;
+-
+-  /* The work_shares array is indexed by "generation & generation_mask".
+-     The mask will be 2**N - 1, where 2**N is the size of the array.  */
+-  unsigned generation_mask;
+-
+-  /* These two values define the bounds of the elements of the work_shares
+-     array that are currently in use.  */
+-  unsigned oldest_live_gen;
+-  unsigned num_live_gen;
+-
+   /* This is the number of threads in the current team.  */
+   unsigned nthreads;
+ 
++  /* This is number of gomp_work_share structs that have been allocated
++     as a block last time.  */
++  unsigned work_share_chunk;
++
+   /* This is the saved team state that applied to a master thread before
+      the current thread was created.  */
+   struct gomp_team_state prev_ts;
+ 
+-  /* This barrier is used for most synchronization of the team.  */
+-  gomp_barrier_t barrier;
+-
+   /* This semaphore should be used by the master thread instead of its
+      "native" semaphore in the thread structure.  Required for nested
+      parallels, as the master is a member of two teams.  */
+   gomp_sem_t master_release;
+ 
+-  /* This array contains pointers to the release semaphore of the threads
+-     in the team.  */
++  /* List of gomp_work_share structs chained through next_free fields.
++     This is populated and taken off only by the first thread in the
++     team encountering a new work sharing construct, in a critical
++     section.  */
++  struct gomp_work_share *work_share_list_alloc;
++
++  /* List of gomp_work_share structs freed by free_work_share.  New
++     entries are atomically added to the start of the list, and
++     alloc_work_share can safely only move all but the first entry
++     to work_share_list alloc, as free_work_share can happen concurrently
++     with alloc_work_share.  */
++  struct gomp_work_share *work_share_list_free;
++
++#ifdef HAVE_SYNC_BUILTINS
++  /* Number of simple single regions encountered by threads in this
++     team.  */
++  unsigned long single_count;
++#else
++  /* Mutex protecting addition of workshares to work_share_list_free.  */
++  gomp_mutex_t work_share_list_free_lock;
++#endif
++
++  /* This barrier is used for most synchronization of the team.  */
++  gomp_barrier_t barrier;
++
++  /* Initial work shares, to avoid allocating any gomp_work_share
++     structs in the common case.  */
++  struct gomp_work_share work_shares[8];
++
++  /* This is an array with pointers to the release semaphore
++     of the threads in the team.  */
+   gomp_sem_t *ordered_release[];
+ };
+ 
+@@ -242,6 +282,11 @@ extern bool gomp_dyn_var;
+ extern bool gomp_nest_var;
+ extern enum gomp_schedule_type gomp_run_sched_var;
+ extern unsigned long gomp_run_sched_chunk;
++#ifndef HAVE_SYNC_BUILTINS
++extern gomp_mutex_t gomp_remaining_threads_lock;
++#endif
++extern unsigned long long gomp_spin_count_var, gomp_throttled_spin_count_var;
++extern unsigned long gomp_available_cpus, gomp_managed_threads;
+ 
+ /* The attributes to be used during thread creation.  */
+ extern pthread_attr_t gomp_thread_attr;
+@@ -306,17 +351,27 @@ extern unsigned gomp_dynamic_max_threads
+ 
+ /* team.c */
+ 
++extern struct gomp_team *gomp_new_team (unsigned);
+ extern void gomp_team_start (void (*) (void *), void *, unsigned,
+-			     struct gomp_work_share *);
++			     struct gomp_team *);
+ extern void gomp_team_end (void);
+ 
+ /* work.c */
+ 
+-extern struct gomp_work_share * gomp_new_work_share (bool, unsigned);
++extern void gomp_init_work_share (struct gomp_work_share *, bool, unsigned);
++extern void gomp_fini_work_share (struct gomp_work_share *);
+ extern bool gomp_work_share_start (bool);
+ extern void gomp_work_share_end (void);
+ extern void gomp_work_share_end_nowait (void);
+ 
++static inline void
++gomp_work_share_init_done (void)
++{
++  struct gomp_thread *thr = gomp_thread ();
++  if (__builtin_expect (thr->ts.last_work_share != NULL, 1))
++    gomp_ptrlock_set (&thr->ts.last_work_share->next_ws, thr->ts.work_share);
++}
++
+ #ifdef HAVE_ATTRIBUTE_VISIBILITY
+ # pragma GCC visibility pop
+ #endif
+--- libgomp/iter.c.jj	2008-03-26 14:48:34.000000000 +0100
++++ libgomp/iter.c	2008-03-26 15:11:23.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -154,7 +154,7 @@ gomp_iter_dynamic_next_locked (long *pst
+   if (start == ws->end)
+     return false;
+ 
+-  chunk = ws->chunk_size * ws->incr;
++  chunk = ws->chunk_size;
+   left = ws->end - start;
+   if (ws->incr < 0)
+     {
+@@ -186,11 +186,38 @@ gomp_iter_dynamic_next (long *pstart, lo
+   struct gomp_work_share *ws = thr->ts.work_share;
+   long start, end, nend, chunk, incr;
+ 
+-  start = ws->next;
+   end = ws->end;
+   incr = ws->incr;
+-  chunk = ws->chunk_size * incr;
++  chunk = ws->chunk_size;
++
++  if (__builtin_expect (ws->mode, 1))
++    {
++      long tmp = __sync_fetch_and_add (&ws->next, chunk);
++      if (incr > 0)
++	{
++	  if (tmp >= end)
++	    return false;
++	  nend = tmp + chunk;
++	  if (nend > end)
++	    nend = end;
++	  *pstart = tmp;
++	  *pend = nend;
++	  return true;
++	}
++      else
++	{
++	  if (tmp <= end)
++	    return false;
++	  nend = tmp + chunk;
++	  if (nend < end)
++	    nend = end;
++	  *pstart = tmp;
++	  *pend = nend;
++	  return true;
++	}
++    }
+ 
++  start = ws->next;
+   while (1)
+     {
+       long left = end - start;
+--- libgomp/work.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/work.c	2008-03-27 12:21:51.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -29,39 +29,138 @@
+    of threads.  */
+ 
+ #include "libgomp.h"
++#include <stddef.h>
+ #include <stdlib.h>
+ #include <string.h>
+ 
+ 
+-/* Create a new work share structure.  */
++/* Allocate a new work share structure, preferably from current team's
++   free gomp_work_share cache.  */
+ 
+-struct gomp_work_share *
+-gomp_new_work_share (bool ordered, unsigned nthreads)
++static struct gomp_work_share *
++alloc_work_share (struct gomp_team *team)
+ {
+   struct gomp_work_share *ws;
+-  size_t size;
++  unsigned int i;
+ 
+-  size = sizeof (*ws);
+-  if (ordered)
+-    size += nthreads * sizeof (ws->ordered_team_ids[0]);
++  /* This is called in a critical section.  */
++  if (team->work_share_list_alloc != NULL)
++    {
++      ws = team->work_share_list_alloc;
++      team->work_share_list_alloc = ws->next_free;
++      return ws;
++    }
+ 
+-  ws = gomp_malloc_cleared (size);
+-  gomp_mutex_init (&ws->lock);
+-  ws->ordered_owner = -1;
++#ifdef HAVE_SYNC_BUILTINS
++  ws = team->work_share_list_free;
++  /* We need atomic read from work_share_list_free,
++     as free_work_share can be called concurrently.  */
++  __asm ("" : "+r" (ws));
++
++  if (ws && ws->next_free)
++    {
++      struct gomp_work_share *next = ws->next_free;
++      ws->next_free = NULL;
++      team->work_share_list_alloc = next->next_free;
++      return next;
++    }
++#else
++  gomp_mutex_lock (&team->work_share_list_free_lock);
++  ws = team->work_share_list_free;
++  if (ws)
++    {
++      team->work_share_list_alloc = ws->next_free;
++      team->work_share_list_free = NULL;
++      gomp_mutex_unlock (&team->work_share_list_free_lock);
++      return ws;
++    }
++  gomp_mutex_unlock (&team->work_share_list_free_lock);
++#endif
+ 
++  team->work_share_chunk *= 2;
++  ws = gomp_malloc (team->work_share_chunk * sizeof (struct gomp_work_share));
++  ws->next_alloc = team->work_shares[0].next_alloc;
++  team->work_shares[0].next_alloc = ws;
++  team->work_share_list_alloc = &ws[1];
++  for (i = 1; i < team->work_share_chunk - 1; i++)
++    ws[i].next_free = &ws[i + 1];
++  ws[i].next_free = NULL;
+   return ws;
+ }
+ 
++/* Initialize an already allocated struct gomp_work_share.
++   This shouldn't touch the next_alloc field.  */
++
++void
++gomp_init_work_share (struct gomp_work_share *ws, bool ordered,
++		      unsigned nthreads)
++{
++  gomp_mutex_init (&ws->lock);
++  if (__builtin_expect (ordered, 0))
++    {
++#define INLINE_ORDERED_TEAM_IDS_CNT \
++  ((sizeof (struct gomp_work_share) \
++    - offsetof (struct gomp_work_share, inline_ordered_team_ids)) \
++   / sizeof (((struct gomp_work_share *) 0)->inline_ordered_team_ids[0]))
++
++      if (nthreads > INLINE_ORDERED_TEAM_IDS_CNT)
++	ws->ordered_team_ids
++	  = gomp_malloc (nthreads * sizeof (*ws->ordered_team_ids));
++      else
++	ws->ordered_team_ids = ws->inline_ordered_team_ids;
++      memset (ws->ordered_team_ids, '\0',
++	      nthreads * sizeof (*ws->ordered_team_ids));
++      ws->ordered_num_used = 0;
++      ws->ordered_owner = -1;
++      ws->ordered_cur = 0;
++    }
++  else
++    ws->ordered_team_ids = NULL;
++  gomp_ptrlock_init (&ws->next_ws, NULL);
++  ws->threads_completed = 0;
++}
+ 
+-/* Free a work share structure.  */
++/* Do any needed destruction of gomp_work_share fields before it
++   is put back into free gomp_work_share cache or freed.  */
+ 
+-static void
+-free_work_share (struct gomp_work_share *ws)
++void
++gomp_fini_work_share (struct gomp_work_share *ws)
+ {
+   gomp_mutex_destroy (&ws->lock);
+-  free (ws);
++  if (ws->ordered_team_ids != ws->inline_ordered_team_ids)
++    free (ws->ordered_team_ids);
++  gomp_ptrlock_destroy (&ws->next_ws);
+ }
+ 
++/* Free a work share struct, if not orphaned, put it into current
++   team's free gomp_work_share cache.  */
++
++static inline void
++free_work_share (struct gomp_team *team, struct gomp_work_share *ws)
++{
++  gomp_fini_work_share (ws);
++  if (__builtin_expect (team == NULL, 0))
++    free (ws);
++  else
++    {
++      struct gomp_work_share *next_ws;
++#ifdef HAVE_SYNC_BUILTINS
++      do
++	{
++	  next_ws = team->work_share_list_free;
++	  ws->next_free = next_ws;
++	}
++      while (!__sync_bool_compare_and_swap (&team->work_share_list_free,
++					    next_ws, ws));
++#else
++      gomp_mutex_lock (&team->work_share_list_free_lock);
++      next_ws = team->work_share_list_free;
++      ws->next_free = next_ws;
++      team->work_share_list_free = ws;
++      gomp_mutex_unlock (&team->work_share_list_free_lock);
++#endif
++    }
++}
+ 
+ /* The current thread is ready to begin the next work sharing construct.
+    In all cases, thr->ts.work_share is updated to point to the new
+@@ -74,71 +173,34 @@ gomp_work_share_start (bool ordered)
+   struct gomp_thread *thr = gomp_thread ();
+   struct gomp_team *team = thr->ts.team;
+   struct gomp_work_share *ws;
+-  unsigned ws_index, ws_gen;
+ 
+   /* Work sharing constructs can be orphaned.  */
+   if (team == NULL)
+     {
+-      ws = gomp_new_work_share (ordered, 1);
++      ws = gomp_malloc (sizeof (*ws));
++      gomp_init_work_share (ws, ordered, 1);
+       thr->ts.work_share = ws;
+-      thr->ts.static_trip = 0;
+-      gomp_mutex_lock (&ws->lock);
+-      return true;
++      return ws;
+     }
+ 
+-  gomp_mutex_lock (&team->work_share_lock);
+-
+-  /* This thread is beginning its next generation.  */
+-  ws_gen = ++thr->ts.work_share_generation;
+-
+-  /* If this next generation is not newer than any other generation in
+-     the team, then simply reference the existing construct.  */
+-  if (ws_gen - team->oldest_live_gen < team->num_live_gen)
++  ws = thr->ts.work_share;
++  thr->ts.last_work_share = ws;
++  ws = gomp_ptrlock_get (&ws->next_ws);
++  if (ws == NULL)
+     {
+-      ws_index = ws_gen & team->generation_mask;
+-      ws = team->work_shares[ws_index];
++      /* This thread encountered a new ws first.  */
++      struct gomp_work_share *ws = alloc_work_share (team);
++      gomp_init_work_share (ws, ordered, team->nthreads);
+       thr->ts.work_share = ws;
+-      thr->ts.static_trip = 0;
+-
+-      gomp_mutex_lock (&ws->lock);
+-      gomp_mutex_unlock (&team->work_share_lock);
+-
+-      return false;
++      return true;
+     }
+-
+-  /* Resize the work shares queue if we've run out of space.  */
+-  if (team->num_live_gen++ == team->generation_mask)
++  else
+     {
+-      team->work_shares = gomp_realloc (team->work_shares,
+-					2 * team->num_live_gen
+-					* sizeof (*team->work_shares));
+-
+-      /* Unless oldest_live_gen is zero, the sequence of live elements
+-	 wraps around the end of the array.  If we do nothing, we break
+-	 lookup of the existing elements.  Fix that by unwrapping the
+-	 data from the front to the end.  */
+-      if (team->oldest_live_gen > 0)
+-	memcpy (team->work_shares + team->num_live_gen,
+-		team->work_shares,
+-		(team->oldest_live_gen & team->generation_mask)
+-		* sizeof (*team->work_shares));
+-
+-      team->generation_mask = team->generation_mask * 2 + 1;
+-    }
+-
+-  ws_index = ws_gen & team->generation_mask;
+-  ws = gomp_new_work_share (ordered, team->nthreads);
+-  thr->ts.work_share = ws;
+-  thr->ts.static_trip = 0;
+-  team->work_shares[ws_index] = ws;
+-
+-  gomp_mutex_lock (&ws->lock);
+-  gomp_mutex_unlock (&team->work_share_lock);
+-
+-  return true;
++      thr->ts.work_share = ws;
++      return false;
++    }
+ }
+ 
+-
+ /* The current thread is done with its current work sharing construct.
+    This version does imply a barrier at the end of the work-share.  */
+ 
+@@ -147,36 +209,28 @@ gomp_work_share_end (void)
+ {
+   struct gomp_thread *thr = gomp_thread ();
+   struct gomp_team *team = thr->ts.team;
+-  struct gomp_work_share *ws = thr->ts.work_share;
+-  bool last;
+-
+-  thr->ts.work_share = NULL;
++  gomp_barrier_state_t bstate;
+ 
+   /* Work sharing constructs can be orphaned.  */
+   if (team == NULL)
+     {
+-      free_work_share (ws);
++      free_work_share (NULL, thr->ts.work_share);
++      thr->ts.work_share = NULL;
+       return;
+     }
+ 
+-  last = gomp_barrier_wait_start (&team->barrier);
++  bstate = gomp_barrier_wait_start (&team->barrier);
+ 
+-  if (last)
++  if (gomp_barrier_last_thread (bstate))
+     {
+-      unsigned ws_index;
+-
+-      ws_index = thr->ts.work_share_generation & team->generation_mask;
+-      team->work_shares[ws_index] = NULL;
+-      team->oldest_live_gen++;
+-      team->num_live_gen = 0;
+-
+-      free_work_share (ws);
++      if (__builtin_expect (thr->ts.last_work_share != NULL, 1))
++	free_work_share (team, thr->ts.last_work_share);
+     }
+ 
+-  gomp_barrier_wait_end (&team->barrier, last);
++  gomp_barrier_wait_end (&team->barrier, bstate);
++  thr->ts.last_work_share = NULL;
+ }
+ 
+-
+ /* The current thread is done with its current work sharing construct.
+    This version does NOT imply a barrier at the end of the work-share.  */
+ 
+@@ -188,15 +242,17 @@ gomp_work_share_end_nowait (void)
+   struct gomp_work_share *ws = thr->ts.work_share;
+   unsigned completed;
+ 
+-  thr->ts.work_share = NULL;
+-
+   /* Work sharing constructs can be orphaned.  */
+   if (team == NULL)
+     {
+-      free_work_share (ws);
++      free_work_share (NULL, ws);
++      thr->ts.work_share = NULL;
+       return;
+     }
+ 
++  if (__builtin_expect (thr->ts.last_work_share == NULL, 0))
++    return;
++
+ #ifdef HAVE_SYNC_BUILTINS
+   completed = __sync_add_and_fetch (&ws->threads_completed, 1);
+ #else
+@@ -206,18 +262,6 @@ gomp_work_share_end_nowait (void)
+ #endif
+ 
+   if (completed == team->nthreads)
+-    {
+-      unsigned ws_index;
+-
+-      gomp_mutex_lock (&team->work_share_lock);
+-
+-      ws_index = thr->ts.work_share_generation & team->generation_mask;
+-      team->work_shares[ws_index] = NULL;
+-      team->oldest_live_gen++;
+-      team->num_live_gen--;
+-
+-      gomp_mutex_unlock (&team->work_share_lock);
+-
+-      free_work_share (ws);
+-    }
++    free_work_share (team, thr->ts.last_work_share);
++  thr->ts.last_work_share = NULL;
+ }
+--- libgomp/single.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/single.c	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -37,10 +37,24 @@
+ bool
+ GOMP_single_start (void)
+ {
++#ifdef HAVE_SYNC_BUILTINS
++  struct gomp_thread *thr = gomp_thread ();
++  struct gomp_team *team = thr->ts.team;
++  unsigned long single_count;
++
++  if (__builtin_expect (team == NULL, 0))
++    return true;
++
++  single_count = thr->ts.single_count++;
++  return __sync_bool_compare_and_swap (&team->single_count, single_count,
++				       single_count + 1L);
++#else
+   bool ret = gomp_work_share_start (false);
+-  gomp_mutex_unlock (&gomp_thread ()->ts.work_share->lock);
++  if (ret)
++    gomp_work_share_init_done ();
+   gomp_work_share_end_nowait ();
+   return ret;
++#endif
+ }
+ 
+ /* This routine is called when first encountering a SINGLE construct that
+@@ -57,10 +71,12 @@ GOMP_single_copy_start (void)
+   void *ret;
+ 
+   first = gomp_work_share_start (false);
+-  gomp_mutex_unlock (&thr->ts.work_share->lock);
+   
+   if (first)
+-    ret = NULL;
++    {
++      gomp_work_share_init_done ();
++      ret = NULL;
++    }
+   else
+     {
+       gomp_barrier_wait (&thr->ts.team->barrier);
+--- libgomp/loop.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/loop.c	2008-03-26 18:47:04.000000000 +0100
+@@ -27,8 +27,9 @@
+ 
+ /* This file handles the LOOP (FOR/DO) construct.  */
+ 
+-#include "libgomp.h"
++#include <limits.h>
+ #include <stdlib.h>
++#include "libgomp.h"
+ 
+ 
+ /* Initialize the given work share construct from the given arguments.  */
+@@ -44,6 +45,39 @@ gomp_loop_init (struct gomp_work_share *
+ 	    ? start : end;
+   ws->incr = incr;
+   ws->next = start;
++  if (sched == GFS_DYNAMIC)
++    {
++      ws->chunk_size *= incr;
++
++#ifdef HAVE_SYNC_BUILTINS
++      {
++	/* For dynamic scheduling prepare things to make each iteration
++	   faster.  */
++	struct gomp_thread *thr = gomp_thread ();
++	struct gomp_team *team = thr->ts.team;
++	long nthreads = team ? team->nthreads : 1;
++
++	if (__builtin_expect (incr > 0, 1))
++	  {
++	    /* Cheap overflow protection.  */
++	    if (__builtin_expect ((nthreads | ws->chunk_size)
++				  >= 1UL << (sizeof (long)
++					     * __CHAR_BIT__ / 2 - 1), 0))
++	      ws->mode = 0;
++	    else
++	      ws->mode = ws->end < (LONG_MAX
++				    - (nthreads + 1) * ws->chunk_size);
++	  }
++	/* Cheap overflow protection.  */
++	else if (__builtin_expect ((nthreads | -ws->chunk_size)
++				   >= 1UL << (sizeof (long)
++					      * __CHAR_BIT__ / 2 - 1), 0))
++	  ws->mode = 0;
++	else
++	  ws->mode = ws->end > (nthreads + 1) * -ws->chunk_size - LONG_MAX;
++      }
++#endif
++    }
+ }
+ 
+ /* The *_start routines are called when first encountering a loop construct
+@@ -68,10 +102,13 @@ gomp_loop_static_start (long start, long
+ {
+   struct gomp_thread *thr = gomp_thread ();
+ 
++  thr->ts.static_trip = 0;
+   if (gomp_work_share_start (false))
+-    gomp_loop_init (thr->ts.work_share, start, end, incr,
+-		    GFS_STATIC, chunk_size);
+-  gomp_mutex_unlock (&thr->ts.work_share->lock);
++    {
++      gomp_loop_init (thr->ts.work_share, start, end, incr,
++		      GFS_STATIC, chunk_size);
++      gomp_work_share_init_done ();
++    }
+ 
+   return !gomp_iter_static_next (istart, iend);
+ }
+@@ -84,13 +121,16 @@ gomp_loop_dynamic_start (long start, lon
+   bool ret;
+ 
+   if (gomp_work_share_start (false))
+-    gomp_loop_init (thr->ts.work_share, start, end, incr,
+-		    GFS_DYNAMIC, chunk_size);
++    {
++      gomp_loop_init (thr->ts.work_share, start, end, incr,
++		      GFS_DYNAMIC, chunk_size);
++      gomp_work_share_init_done ();
++    }
+ 
+ #ifdef HAVE_SYNC_BUILTINS
+-  gomp_mutex_unlock (&thr->ts.work_share->lock);
+   ret = gomp_iter_dynamic_next (istart, iend);
+ #else
++  gomp_mutex_lock (&thr->ts.work_share->lock);
+   ret = gomp_iter_dynamic_next_locked (istart, iend);
+   gomp_mutex_unlock (&thr->ts.work_share->lock);
+ #endif
+@@ -106,13 +146,16 @@ gomp_loop_guided_start (long start, long
+   bool ret;
+ 
+   if (gomp_work_share_start (false))
+-    gomp_loop_init (thr->ts.work_share, start, end, incr,
+-		    GFS_GUIDED, chunk_size);
++    {
++      gomp_loop_init (thr->ts.work_share, start, end, incr,
++		      GFS_GUIDED, chunk_size);
++      gomp_work_share_init_done ();
++    }
+ 
+ #ifdef HAVE_SYNC_BUILTINS
+-  gomp_mutex_unlock (&thr->ts.work_share->lock);
+   ret = gomp_iter_guided_next (istart, iend);
+ #else
++  gomp_mutex_lock (&thr->ts.work_share->lock);
+   ret = gomp_iter_guided_next_locked (istart, iend);
+   gomp_mutex_unlock (&thr->ts.work_share->lock);
+ #endif
+@@ -149,13 +192,14 @@ gomp_loop_ordered_static_start (long sta
+ {
+   struct gomp_thread *thr = gomp_thread ();
+ 
++  thr->ts.static_trip = 0;
+   if (gomp_work_share_start (true))
+     {
+       gomp_loop_init (thr->ts.work_share, start, end, incr,
+ 		      GFS_STATIC, chunk_size);
+       gomp_ordered_static_init ();
++      gomp_work_share_init_done ();
+     }
+-  gomp_mutex_unlock (&thr->ts.work_share->lock);
+ 
+   return !gomp_iter_static_next (istart, iend);
+ }
+@@ -168,8 +212,14 @@ gomp_loop_ordered_dynamic_start (long st
+   bool ret;
+ 
+   if (gomp_work_share_start (true))
+-    gomp_loop_init (thr->ts.work_share, start, end, incr,
+-		    GFS_DYNAMIC, chunk_size);
++    {
++      gomp_loop_init (thr->ts.work_share, start, end, incr,
++		      GFS_DYNAMIC, chunk_size);
++      gomp_mutex_lock (&thr->ts.work_share->lock);
++      gomp_work_share_init_done ();
++    }
++  else
++    gomp_mutex_lock (&thr->ts.work_share->lock);
+ 
+   ret = gomp_iter_dynamic_next_locked (istart, iend);
+   if (ret)
+@@ -187,8 +237,14 @@ gomp_loop_ordered_guided_start (long sta
+   bool ret;
+ 
+   if (gomp_work_share_start (true))
+-    gomp_loop_init (thr->ts.work_share, start, end, incr,
+-		    GFS_GUIDED, chunk_size);
++    {
++      gomp_loop_init (thr->ts.work_share, start, end, incr,
++		      GFS_GUIDED, chunk_size);
++      gomp_mutex_lock (&thr->ts.work_share->lock);
++      gomp_work_share_init_done ();
++    }
++  else
++    gomp_mutex_lock (&thr->ts.work_share->lock);
+ 
+   ret = gomp_iter_guided_next_locked (istart, iend);
+   if (ret)
+@@ -375,12 +431,12 @@ gomp_parallel_loop_start (void (*fn) (vo
+ 			  long incr, enum gomp_schedule_type sched,
+ 			  long chunk_size)
+ {
+-  struct gomp_work_share *ws;
++  struct gomp_team *team;
+ 
+   num_threads = gomp_resolve_num_threads (num_threads);
+-  ws = gomp_new_work_share (false, num_threads);
+-  gomp_loop_init (ws, start, end, incr, sched, chunk_size);
+-  gomp_team_start (fn, data, num_threads, ws);
++  team = gomp_new_team (num_threads);
++  gomp_loop_init (&team->work_shares[0], start, end, incr, sched, chunk_size);
++  gomp_team_start (fn, data, num_threads, team);
+ }
+ 
+ void
+--- libgomp/Makefile.in.jj	2008-01-10 20:53:47.000000000 +0100
++++ libgomp/Makefile.in	2008-03-26 18:51:01.000000000 +0100
+@@ -83,7 +83,7 @@ libgomp_la_LIBADD =
+ am_libgomp_la_OBJECTS = alloc.lo barrier.lo critical.lo env.lo \
+ 	error.lo iter.lo loop.lo ordered.lo parallel.lo sections.lo \
+ 	single.lo team.lo work.lo lock.lo mutex.lo proc.lo sem.lo \
+-	bar.lo time.lo fortran.lo affinity.lo
++	bar.lo ptrlock.lo time.lo fortran.lo affinity.lo
+ libgomp_la_OBJECTS = $(am_libgomp_la_OBJECTS)
+ DEFAULT_INCLUDES = -I. -I$(srcdir) -I.
+ depcomp = $(SHELL) $(top_srcdir)/../depcomp
+@@ -292,7 +292,7 @@ libgomp_version_info = -version-info $(l
+ libgomp_la_LDFLAGS = $(libgomp_version_info) $(libgomp_version_script)
+ libgomp_la_SOURCES = alloc.c barrier.c critical.c env.c error.c iter.c \
+ 	loop.c ordered.c parallel.c sections.c single.c team.c work.c \
+-	lock.c mutex.c proc.c sem.c bar.c time.c fortran.c affinity.c
++	lock.c mutex.c proc.c sem.c bar.c ptrlock.c time.c fortran.c affinity.c
+ 
+ nodist_noinst_HEADERS = libgomp_f.h
+ nodist_libsubinclude_HEADERS = omp.h
+@@ -434,6 +434,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ordered.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/parallel.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/proc.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ptrlock.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sections.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sem.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/single.Plo@am__quote@
+--- libgomp/testsuite/libgomp.c/loop-4.c.jj	2008-03-26 18:47:04.000000000 +0100
++++ libgomp/testsuite/libgomp.c/loop-4.c	2008-03-26 18:47:04.000000000 +0100
+@@ -0,0 +1,28 @@
++/* { dg-do run } */
++
++extern void abort (void);
++
++int
++main (void)
++{
++  int e = 0;
++#pragma omp parallel num_threads (4) reduction(+:e)
++  {
++    long i;
++    #pragma omp for schedule(dynamic,1)
++    for (i = __LONG_MAX__ - 30001; i <= __LONG_MAX__ - 10001; i += 10000)
++      if (i != __LONG_MAX__ - 30001
++	  && i != __LONG_MAX__ - 20001
++	  && i != __LONG_MAX__ - 10001)
++	e = 1;
++    #pragma omp for schedule(dynamic,1)
++    for (i = -__LONG_MAX__ + 30000; i >= -__LONG_MAX__ + 10000; i -= 10000)
++      if (i != -__LONG_MAX__ + 30000
++	  && i != -__LONG_MAX__ + 20000
++	  && i != -__LONG_MAX__ + 10000)
++	e = 1;
++  }
++  if (e)
++    abort ();
++  return 0;
++}
+--- libgomp/Makefile.am.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/Makefile.am	2008-03-26 15:15:19.000000000 +0100
+@@ -31,7 +31,7 @@ libgomp_la_LDFLAGS = $(libgomp_version_i
+ 
+ libgomp_la_SOURCES = alloc.c barrier.c critical.c env.c error.c iter.c \
+ 	loop.c ordered.c parallel.c sections.c single.c team.c work.c \
+-	lock.c mutex.c proc.c sem.c bar.c time.c fortran.c affinity.c
++	lock.c mutex.c proc.c sem.c bar.c ptrlock.c time.c fortran.c affinity.c
+ 
+ nodist_noinst_HEADERS = libgomp_f.h
+ nodist_libsubinclude_HEADERS = omp.h
+--- libgomp/team.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/team.c	2008-03-27 12:22:26.000000000 +0100
+@@ -94,7 +94,7 @@ gomp_thread_start (void *xdata)
+     {
+       gomp_barrier_wait (&thr->ts.team->barrier);
+       local_fn (local_data);
+-      gomp_barrier_wait (&thr->ts.team->barrier);
++      gomp_barrier_wait_last (&thr->ts.team->barrier);
+     }
+   else
+     {
+@@ -114,11 +114,10 @@ gomp_thread_start (void *xdata)
+ 	  thr->data = NULL;
+ 	  thr->ts.team = NULL;
+ 	  thr->ts.work_share = NULL;
++	  thr->ts.last_work_share = NULL;
+ 	  thr->ts.team_id = 0;
+-	  thr->ts.work_share_generation = 0;
+-	  thr->ts.static_trip = 0;
+ 
+-	  gomp_barrier_wait (&team->barrier);
++	  gomp_barrier_wait_last (&team->barrier);
+ 	  gomp_barrier_wait (&gomp_threads_dock);
+ 
+ 	  local_fn = thr->fn;
+@@ -133,21 +132,29 @@ gomp_thread_start (void *xdata)
+ 
+ /* Create a new team data structure.  */
+ 
+-static struct gomp_team *
+-new_team (unsigned nthreads, struct gomp_work_share *work_share)
++struct gomp_team *
++gomp_new_team (unsigned nthreads)
+ {
+   struct gomp_team *team;
+   size_t size;
++  int i;
+ 
+   size = sizeof (*team) + nthreads * sizeof (team->ordered_release[0]);
+   team = gomp_malloc (size);
+-  gomp_mutex_init (&team->work_share_lock);
+ 
+-  team->work_shares = gomp_malloc (4 * sizeof (struct gomp_work_share *));
+-  team->generation_mask = 3;
+-  team->oldest_live_gen = work_share == NULL;
+-  team->num_live_gen = work_share != NULL;
+-  team->work_shares[0] = work_share;
++  team->work_share_chunk = 8;
++#ifdef HAVE_SYNC_BUILTINS
++  team->single_count = 0;
++#else
++  gomp_mutex_init (&team->work_share_list_free_lock);
++#endif
++  gomp_init_work_share (&team->work_shares[0], false, nthreads);
++  team->work_shares[0].next_alloc = NULL;
++  team->work_share_list_free = NULL;
++  team->work_share_list_alloc = &team->work_shares[1];
++  for (i = 1; i < 7; i++)
++    team->work_shares[i].next_free = &team->work_shares[i + 1];
++  team->work_shares[i].next_free = NULL;
+ 
+   team->nthreads = nthreads;
+   gomp_barrier_init (&team->barrier, nthreads);
+@@ -164,10 +171,22 @@ new_team (unsigned nthreads, struct gomp
+ static void
+ free_team (struct gomp_team *team)
+ {
+-  free (team->work_shares);
+-  gomp_mutex_destroy (&team->work_share_lock);
++  if (__builtin_expect (team->work_shares[0].next_alloc != NULL, 0))
++    {
++      struct gomp_work_share *ws = team->work_shares[0].next_alloc;
++      do
++	{
++	  struct gomp_work_share *next_ws = ws->next_alloc;
++	  free (ws);
++	  ws = next_ws;
++	}
++      while (ws != NULL);
++    }
+   gomp_barrier_destroy (&team->barrier);
+   gomp_sem_destroy (&team->master_release);
++#ifndef HAVE_SYNC_BUILTINS
++  gomp_mutex_destroy (&team->work_share_list_free_lock);
++#endif
+   free (team);
+ }
+ 
+@@ -176,11 +195,10 @@ free_team (struct gomp_team *team)
+ 
+ void
+ gomp_team_start (void (*fn) (void *), void *data, unsigned nthreads,
+-		 struct gomp_work_share *work_share)
++		 struct gomp_team *team)
+ {
+   struct gomp_thread_start_data *start_data;
+   struct gomp_thread *thr, *nthr;
+-  struct gomp_team *team;
+   bool nested;
+   unsigned i, n, old_threads_used = 0;
+   pthread_attr_t thread_attr, *attr;
+@@ -188,17 +206,18 @@ gomp_team_start (void (*fn) (void *), vo
+   thr = gomp_thread ();
+   nested = thr->ts.team != NULL;
+ 
+-  team = new_team (nthreads, work_share);
+-
+   /* Always save the previous state, even if this isn't a nested team.
+      In particular, we should save any work share state from an outer
+      orphaned work share construct.  */
+   team->prev_ts = thr->ts;
+ 
+   thr->ts.team = team;
+-  thr->ts.work_share = work_share;
+   thr->ts.team_id = 0;
+-  thr->ts.work_share_generation = 0;
++  thr->ts.work_share = &team->work_shares[0];
++  thr->ts.last_work_share = NULL;
++#ifdef HAVE_SYNC_BUILTINS
++  thr->ts.single_count = 0;
++#endif
+   thr->ts.static_trip = 0;
+ 
+   if (nthreads == 1)
+@@ -241,9 +260,12 @@ gomp_team_start (void (*fn) (void *), vo
+ 	{
+ 	  nthr = gomp_threads[i];
+ 	  nthr->ts.team = team;
+-	  nthr->ts.work_share = work_share;
++	  nthr->ts.work_share = &team->work_shares[0];
++	  nthr->ts.last_work_share = NULL;
+ 	  nthr->ts.team_id = i;
+-	  nthr->ts.work_share_generation = 0;
++#ifdef HAVE_SYNC_BUILTINS
++	  nthr->ts.single_count = 0;
++#endif
+ 	  nthr->ts.static_trip = 0;
+ 	  nthr->fn = fn;
+ 	  nthr->data = data;
+@@ -266,8 +288,24 @@ gomp_team_start (void (*fn) (void *), vo
+ 	}
+     }
+ 
++  if (__builtin_expect (nthreads > old_threads_used, 0))
++    {
++      long diff = (long) nthreads - (long) old_threads_used;
++
++      if (old_threads_used == 0)
++	--diff;
++
++#ifdef HAVE_SYNC_BUILTINS
++      __sync_fetch_and_add (&gomp_managed_threads, diff);
++#else
++      gomp_mutex_lock (&gomp_remaining_threads_lock);
++      gomp_managed_threads += diff;
++      gomp_mutex_unlock (&gomp_remaining_threads_lock);
++#endif
++    }
++
+   attr = &gomp_thread_attr;
+-  if (gomp_cpu_affinity != NULL)
++  if (__builtin_expect (gomp_cpu_affinity != NULL, 0))
+     {
+       size_t stacksize;
+       pthread_attr_init (&thread_attr);
+@@ -287,9 +325,12 @@ gomp_team_start (void (*fn) (void *), vo
+       int err;
+ 
+       start_data->ts.team = team;
+-      start_data->ts.work_share = work_share;
++      start_data->ts.work_share = &team->work_shares[0];
++      start_data->ts.last_work_share = NULL;
+       start_data->ts.team_id = i;
+-      start_data->ts.work_share_generation = 0;
++#ifdef HAVE_SYNC_BUILTINS
++      start_data->ts.single_count = 0;
++#endif
+       start_data->ts.static_trip = 0;
+       start_data->fn = fn;
+       start_data->fn_data = data;
+@@ -303,7 +344,7 @@ gomp_team_start (void (*fn) (void *), vo
+ 	gomp_fatal ("Thread creation failed: %s", strerror (err));
+     }
+ 
+-  if (gomp_cpu_affinity != NULL)
++  if (__builtin_expect (gomp_cpu_affinity != NULL, 0))
+     pthread_attr_destroy (&thread_attr);
+ 
+  do_release:
+@@ -313,8 +354,20 @@ gomp_team_start (void (*fn) (void *), vo
+      that should arrive back at the end of this team.  The extra
+      threads should be exiting.  Note that we arrange for this test
+      to never be true for nested teams.  */
+-  if (nthreads < old_threads_used)
+-    gomp_barrier_reinit (&gomp_threads_dock, nthreads);
++  if (__builtin_expect (nthreads < old_threads_used, 0))
++    {
++      long diff = (long) nthreads - (long) old_threads_used;
++
++      gomp_barrier_reinit (&gomp_threads_dock, nthreads);
++
++#ifdef HAVE_SYNC_BUILTINS
++      __sync_fetch_and_add (&gomp_managed_threads, diff);
++#else
++      gomp_mutex_lock (&gomp_remaining_threads_lock);
++      gomp_managed_threads += diff;
++      gomp_mutex_unlock (&gomp_remaining_threads_lock);
++#endif
++    }
+ }
+ 
+ 
+@@ -329,8 +382,21 @@ gomp_team_end (void)
+ 
+   gomp_barrier_wait (&team->barrier);
+ 
++  gomp_fini_work_share (thr->ts.work_share);
++
+   thr->ts = team->prev_ts;
+ 
++  if (__builtin_expect (thr->ts.team != NULL, 0))
++    {
++#ifdef HAVE_SYNC_BUILTINS
++      __sync_fetch_and_add (&gomp_managed_threads, 1L - team->nthreads);
++#else
++      gomp_mutex_lock (&gomp_remaining_threads_lock);
++      gomp_managed_threads -= team->nthreads - 1L;
++      gomp_mutex_unlock (&gomp_remaining_threads_lock);
++#endif
++    }
++
+   free_team (team);
+ }
+ 
+--- libgomp/config/posix/bar.h.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/config/posix/bar.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -46,18 +46,32 @@ typedef struct
+   unsigned total;
+   unsigned arrived;
+ } gomp_barrier_t;
++typedef bool gomp_barrier_state_t;
+ 
+ extern void gomp_barrier_init (gomp_barrier_t *, unsigned);
+ extern void gomp_barrier_reinit (gomp_barrier_t *, unsigned);
+ extern void gomp_barrier_destroy (gomp_barrier_t *);
+ 
+ extern void gomp_barrier_wait (gomp_barrier_t *);
+-extern void gomp_barrier_wait_end (gomp_barrier_t *, bool);
++extern void gomp_barrier_wait_end (gomp_barrier_t *, gomp_barrier_state_t);
+ 
+-static inline bool gomp_barrier_wait_start (gomp_barrier_t *bar)
++static inline gomp_barrier_state_t
++gomp_barrier_wait_start (gomp_barrier_t *bar)
+ {
+   gomp_mutex_lock (&bar->mutex1);
+   return ++bar->arrived == bar->total;
+ }
+ 
++static inline bool
++gomp_barrier_last_thread (gomp_barrier_state_t state)
++{
++  return state;
++}
++
++static inline void
++gomp_barrier_wait_last (gomp_barrier_t *bar)
++{
++  gomp_barrier_wait (bar);
++}
++
+ #endif /* GOMP_BARRIER_H */
+--- libgomp/config/posix/ptrlock.h.jj	2008-03-26 15:11:32.000000000 +0100
++++ libgomp/config/posix/ptrlock.h	2008-03-26 15:11:32.000000000 +0100
+@@ -0,0 +1,69 @@
++/* Copyright (C) 2008 Free Software Foundation, Inc.
++   Contributed by Jakub Jelinek <jakub@redhat.com>.
++
++   This file is part of the GNU OpenMP Library (libgomp).
++
++   Libgomp is free software; you can redistribute it and/or modify it
++   under the terms of the GNU Lesser General Public License as published by
++   the Free Software Foundation; either version 2.1 of the License, or
++   (at your option) any later version.
++
++   Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
++   FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for
++   more details.
++
++   You should have received a copy of the GNU Lesser General Public License 
++   along with libgomp; see the file COPYING.LIB.  If not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++   MA 02110-1301, USA.  */
++
++/* As a special exception, if you link this library with other files, some
++   of which are compiled with GCC, to produce an executable, this library
++   does not by itself cause the resulting executable to be covered by the
++   GNU General Public License.  This exception does not however invalidate
++   any other reasons why the executable file might be covered by the GNU
++   General Public License.  */
++
++/* This is a Linux specific implementation of a mutex synchronization
++   mechanism for libgomp.  This type is private to the library.  This
++   implementation uses atomic instructions and the futex syscall.  */
++
++#ifndef GOMP_PTRLOCK_H
++#define GOMP_PTRLOCK_H 1
++
++typedef struct { void *ptr; gomp_mutex_t lock; } gomp_ptrlock_t;
++
++static inline void gomp_ptrlock_init (gomp_ptrlock_t *ptrlock, void *ptr)
++{
++  ptrlock->ptr = ptr;
++  gomp_mutex_init (&ptrlock->lock);
++}
++
++static inline void *gomp_ptrlock_get (gomp_ptrlock_t *ptrlock)
++{
++  if (ptrlock->ptr != NULL)
++    return ptrlock->ptr;
++
++  gomp_mutex_lock (&ptrlock->lock);
++  if (ptrlock->ptr != NULL)
++    {
++      gomp_mutex_unlock (&ptrlock->lock);
++      return ptrlock->ptr;
++    }
++
++  return NULL;
++}
++
++static inline void gomp_ptrlock_set (gomp_ptrlock_t *ptrlock, void *ptr)
++{
++  ptrlock->ptr = ptr;
++  gomp_mutex_unlock (&ptrlock->lock);
++}
++
++static inline void gomp_ptrlock_destroy (gomp_ptrlock_t *ptrlock)
++{
++  gomp_mutex_destroy (&ptrlock->lock);
++}
++
++#endif /* GOMP_PTRLOCK_H */
+--- libgomp/config/posix/ptrlock.c.jj	2008-03-26 15:11:32.000000000 +0100
++++ libgomp/config/posix/ptrlock.c	2008-03-26 15:11:32.000000000 +0100
+@@ -0,0 +1 @@
++/* Everything is in the header.  */
+--- libgomp/config/posix/bar.c.jj	2007-12-07 14:41:01.000000000 +0100
++++ libgomp/config/posix/bar.c	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -70,7 +70,7 @@ gomp_barrier_reinit (gomp_barrier_t *bar
+ }
+ 
+ void
+-gomp_barrier_wait_end (gomp_barrier_t *bar, bool last)
++gomp_barrier_wait_end (gomp_barrier_t *bar, gomp_barrier_state_t last)
+ {
+   unsigned int n;
+ 
+--- libgomp/config/linux/alpha/futex.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/alpha/futex.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -30,8 +30,6 @@
+ #ifndef SYS_futex
+ #define SYS_futex               394
+ #endif
+-#define FUTEX_WAIT              0
+-#define FUTEX_WAKE              1
+ 
+ 
+ static inline void
+@@ -45,7 +43,7 @@ futex_wait (int *addr, int val)
+ 
+   sc_0 = SYS_futex;
+   sc_16 = (long) addr;
+-  sc_17 = FUTEX_WAIT;
++  sc_17 = gomp_futex_wait;
+   sc_18 = val;
+   sc_19 = 0;
+   __asm volatile ("callsys"
+@@ -53,6 +51,20 @@ futex_wait (int *addr, int val)
+ 		  : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18), "1"(sc_19)
+ 		  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+ 		    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
++  if (__builtin_expect (sc_19, 0) && sc_0 == ENOSYS)
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sc_0 = SYS_futex;
++      sc_17 &= ~FUTEX_PRIVATE_FLAG;
++      sc_19 = 0;
++      __asm volatile ("callsys"
++		      : "=r" (sc_0), "=r"(sc_19)
++		      : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18),
++			"1"(sc_19)
++		      : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
++			"$22", "$23", "$24", "$25", "$27", "$28", "memory");
++    }
+ }
+ 
+ static inline void
+@@ -66,11 +78,35 @@ futex_wake (int *addr, int count)
+ 
+   sc_0 = SYS_futex;
+   sc_16 = (long) addr;
+-  sc_17 = FUTEX_WAKE;
++  sc_17 = gomp_futex_wake;
+   sc_18 = count;
+   __asm volatile ("callsys"
+ 		  : "=r" (sc_0), "=r"(sc_19)
+ 		  : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18)
+ 		  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+ 		    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
++  if (__builtin_expect (sc_19, 0) && sc_0 == ENOSYS)
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sc_0 = SYS_futex;
++      sc_17 &= ~FUTEX_PRIVATE_FLAG;
++      __asm volatile ("callsys"
++		      : "=r" (sc_0), "=r"(sc_19)
++		      : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18)
++		      : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
++			"$22", "$23", "$24", "$25", "$27", "$28", "memory");
++    }
++}
++
++static inline void
++cpu_relax (void)
++{
++  __asm volatile ("" : : : "memory");
++}
++
++static inline void
++atomic_write_barrier (void)
++{
++  __asm volatile ("wmb" : : : "memory");
+ }
+--- libgomp/config/linux/affinity.c.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/affinity.c	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2006, 2007 Free Software Foundation, Inc.
++/* Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
+    Contributed by Jakub Jelinek <jakub@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -38,9 +38,6 @@
+ #ifdef HAVE_PTHREAD_AFFINITY_NP
+ 
+ static unsigned int affinity_counter;
+-#ifndef HAVE_SYNC_BUILTINS
+-static gomp_mutex_t affinity_lock;
+-#endif
+ 
+ void
+ gomp_init_affinity (void)
+@@ -76,9 +73,6 @@ gomp_init_affinity (void)
+   CPU_SET (gomp_cpu_affinity[0], &cpuset);
+   pthread_setaffinity_np (pthread_self (), sizeof (cpuset), &cpuset);
+   affinity_counter = 1;
+-#ifndef HAVE_SYNC_BUILTINS
+-  gomp_mutex_init (&affinity_lock);
+-#endif
+ }
+ 
+ void
+@@ -87,13 +81,7 @@ gomp_init_thread_affinity (pthread_attr_
+   unsigned int cpu;
+   cpu_set_t cpuset;
+ 
+-#ifdef HAVE_SYNC_BUILTINS
+   cpu = __sync_fetch_and_add (&affinity_counter, 1);
+-#else
+-  gomp_mutex_lock (&affinity_lock);
+-  cpu = affinity_counter++;
+-  gomp_mutex_unlock (&affinity_lock);
+-#endif
+   cpu %= gomp_cpu_affinity_len;
+   CPU_ZERO (&cpuset);
+   CPU_SET (gomp_cpu_affinity[cpu], &cpuset);
+--- libgomp/config/linux/bar.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/bar.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -36,40 +36,49 @@
+ 
+ typedef struct
+ {
+-  gomp_mutex_t mutex;
+-  unsigned total;
+-  unsigned arrived;
+-  int generation;
++  /* Make sure total/generation is in a mostly read cacheline, while
++     awaited in a separate cacheline.  */
++  unsigned total __attribute__((aligned (64)));
++  unsigned generation;
++  unsigned awaited __attribute__((aligned (64)));
+ } gomp_barrier_t;
++typedef unsigned int gomp_barrier_state_t;
+ 
+ static inline void gomp_barrier_init (gomp_barrier_t *bar, unsigned count)
+ {
+-  gomp_mutex_init (&bar->mutex);
+   bar->total = count;
+-  bar->arrived = 0;
++  bar->awaited = count;
+   bar->generation = 0;
+ }
+ 
+ static inline void gomp_barrier_reinit (gomp_barrier_t *bar, unsigned count)
+ {
+-  gomp_mutex_lock (&bar->mutex);
++  __sync_fetch_and_add (&bar->awaited, count - bar->total);
+   bar->total = count;
+-  gomp_mutex_unlock (&bar->mutex);
+ }
+ 
+ static inline void gomp_barrier_destroy (gomp_barrier_t *bar)
+ {
+-  /* Before destroying, make sure all threads have left the barrier.  */
+-  gomp_mutex_lock (&bar->mutex);
+ }
+ 
+ extern void gomp_barrier_wait (gomp_barrier_t *);
+-extern void gomp_barrier_wait_end (gomp_barrier_t *, bool);
++extern void gomp_barrier_wait_last (gomp_barrier_t *);
++extern void gomp_barrier_wait_end (gomp_barrier_t *, gomp_barrier_state_t);
+ 
+-static inline bool gomp_barrier_wait_start (gomp_barrier_t *bar)
++static inline gomp_barrier_state_t
++gomp_barrier_wait_start (gomp_barrier_t *bar)
+ {
+-  gomp_mutex_lock (&bar->mutex);
+-  return ++bar->arrived == bar->total;
++  unsigned int ret = bar->generation;
++  /* Do we need any barrier here or is __sync_add_and_fetch acting
++     as the needed LoadLoad barrier already?  */
++  ret += __sync_add_and_fetch (&bar->awaited, -1) == 0;
++  return ret;
++}
++
++static inline bool
++gomp_barrier_last_thread (gomp_barrier_state_t state)
++{
++  return state & 1;
+ }
+ 
+ #endif /* GOMP_BARRIER_H */
+--- libgomp/config/linux/ptrlock.h.jj	2008-03-26 15:11:32.000000000 +0100
++++ libgomp/config/linux/ptrlock.h	2008-03-26 15:11:32.000000000 +0100
+@@ -0,0 +1,65 @@
++/* Copyright (C) 2008 Free Software Foundation, Inc.
++   Contributed by Jakub Jelinek <jakub@redhat.com>.
++
++   This file is part of the GNU OpenMP Library (libgomp).
++
++   Libgomp is free software; you can redistribute it and/or modify it
++   under the terms of the GNU Lesser General Public License as published by
++   the Free Software Foundation; either version 2.1 of the License, or
++   (at your option) any later version.
++
++   Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
++   FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for
++   more details.
++
++   You should have received a copy of the GNU Lesser General Public License 
++   along with libgomp; see the file COPYING.LIB.  If not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++   MA 02110-1301, USA.  */
++
++/* As a special exception, if you link this library with other files, some
++   of which are compiled with GCC, to produce an executable, this library
++   does not by itself cause the resulting executable to be covered by the
++   GNU General Public License.  This exception does not however invalidate
++   any other reasons why the executable file might be covered by the GNU
++   General Public License.  */
++
++/* This is a Linux specific implementation of a mutex synchronization
++   mechanism for libgomp.  This type is private to the library.  This
++   implementation uses atomic instructions and the futex syscall.  */
++
++#ifndef GOMP_PTRLOCK_H
++#define GOMP_PTRLOCK_H 1
++
++typedef void *gomp_ptrlock_t;
++
++static inline void gomp_ptrlock_init (gomp_ptrlock_t *ptrlock, void *ptr)
++{
++  *ptrlock = ptr;
++}
++
++extern void *gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock);
++static inline void *gomp_ptrlock_get (gomp_ptrlock_t *ptrlock)
++{
++  if ((uintptr_t) *ptrlock > 2)
++    return *ptrlock;
++
++  if (__sync_bool_compare_and_swap (ptrlock, NULL, (uintptr_t) 1))
++    return NULL;
++
++  return gomp_ptrlock_get_slow (ptrlock);
++}
++
++extern void gomp_ptrlock_set_slow (gomp_ptrlock_t *ptrlock, void *ptr);
++static inline void gomp_ptrlock_set (gomp_ptrlock_t *ptrlock, void *ptr)
++{
++  if (!__sync_bool_compare_and_swap (ptrlock, (uintptr_t) 1, ptr))
++    gomp_ptrlock_set_slow (ptrlock, ptr);
++}
++
++static inline void gomp_ptrlock_destroy (gomp_ptrlock_t *ptrlock)
++{
++}
++
++#endif /* GOMP_PTRLOCK_H */
+--- libgomp/config/linux/lock.c.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/lock.c	2008-03-26 15:11:32.000000000 +0100
+@@ -29,11 +29,10 @@
+    primitives.  This implementation uses atomic instructions and the futex
+    syscall.  */
+ 
+-#include "libgomp.h"
+ #include <string.h>
+ #include <unistd.h>
+ #include <sys/syscall.h>
+-#include "futex.h"
++#include "wait.h"
+ 
+ 
+ /* The internal gomp_mutex_t and the external non-recursive omp_lock_t
+@@ -137,7 +136,7 @@ omp_set_nest_lock (omp_nest_lock_t *lock
+ 	  return;
+ 	}
+ 
+-      futex_wait (&lock->owner, otid);
++      do_wait (&lock->owner, otid);
+     }
+ }
+ 
+--- libgomp/config/linux/ptrlock.c.jj	2008-03-26 15:11:32.000000000 +0100
++++ libgomp/config/linux/ptrlock.c	2008-03-26 15:11:32.000000000 +0100
+@@ -0,0 +1,70 @@
++/* Copyright (C) 2008 Free Software Foundation, Inc.
++   Contributed by Jakub Jelinek <jakub@redhat.com>.
++
++   This file is part of the GNU OpenMP Library (libgomp).
++
++   Libgomp is free software; you can redistribute it and/or modify it
++   under the terms of the GNU Lesser General Public License as published by
++   the Free Software Foundation; either version 2.1 of the License, or
++   (at your option) any later version.
++
++   Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
++   FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for
++   more details.
++
++   You should have received a copy of the GNU Lesser General Public License 
++   along with libgomp; see the file COPYING.LIB.  If not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++   MA 02110-1301, USA.  */
++
++/* As a special exception, if you link this library with other files, some
++   of which are compiled with GCC, to produce an executable, this library
++   does not by itself cause the resulting executable to be covered by the
++   GNU General Public License.  This exception does not however invalidate
++   any other reasons why the executable file might be covered by the GNU
++   General Public License.  */
++
++/* This is a Linux specific implementation of a mutex synchronization
++   mechanism for libgomp.  This type is private to the library.  This
++   implementation uses atomic instructions and the futex syscall.  */
++
++#include <endian.h>
++#include <limits.h>
++#include "wait.h"
++
++void *
++gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock)
++{
++  int *intptr;
++  __sync_bool_compare_and_swap (ptrlock, 1, 2);
++
++  /* futex works on ints, not pointers.
++     But a valid work share pointer will be at least
++     8 byte aligned, so it is safe to assume the low
++     32-bits of the pointer won't contain values 1 or 2.  */
++  __asm volatile ("" : "=r" (intptr) : "0" (ptrlock));
++#if __BYTE_ORDER == __BIG_ENDIAN
++  if (sizeof (*ptrlock) > sizeof (int))
++    intptr += (sizeof (*ptrlock) / sizeof (int)) - 1;
++#endif
++  do
++    do_wait (intptr, 2);
++  while (*intptr == 2);
++  __asm volatile ("" : : : "memory");
++  return *ptrlock;
++}
++
++void
++gomp_ptrlock_set_slow (gomp_ptrlock_t *ptrlock, void *ptr)
++{
++  int *intptr;
++
++  *ptrlock = ptr;
++  __asm volatile ("" : "=r" (intptr) : "0" (ptrlock));
++#if __BYTE_ORDER == __BIG_ENDIAN
++  if (sizeof (*ptrlock) > sizeof (int))
++    intptr += (sizeof (*ptrlock) / sizeof (int)) - 1;
++#endif
++  futex_wake (intptr, INT_MAX);
++}
+--- libgomp/config/linux/x86/futex.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/x86/futex.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -27,9 +27,6 @@
+ 
+ /* Provide target-specific access to the futex system call.  */
+ 
+-#define FUTEX_WAIT	0
+-#define FUTEX_WAKE	1
+-
+ #ifdef __LP64__
+ # ifndef SYS_futex
+ #  define SYS_futex	202
+@@ -38,14 +35,26 @@
+ static inline void
+ futex_wait (int *addr, int val)
+ {
+-  register long r10 __asm__("%r10") = 0;
++  register long r10 __asm__("%r10");
+   long res;
+ 
++  r10 = 0;
+   __asm volatile ("syscall"
+ 		  : "=a" (res)
+-		  : "0"(SYS_futex), "D" (addr), "S"(FUTEX_WAIT),
+-		    "d"(val), "r"(r10)
++		  : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wait),
++		    "d" (val), "r" (r10)
+ 		  : "r11", "rcx", "memory");
++  if (__builtin_expect (res == -ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      r10 = 0;
++      __asm volatile ("syscall"
++		      : "=a" (res)
++		      : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wait),
++			"d" (val), "r" (r10)
++		      : "r11", "rcx", "memory");
++    }
+ }
+ 
+ static inline void
+@@ -55,8 +64,19 @@ futex_wake (int *addr, int count)
+ 
+   __asm volatile ("syscall"
+ 		  : "=a" (res)
+-		  : "0"(SYS_futex), "D" (addr), "S"(FUTEX_WAKE), "d"(count)
++		  : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wake),
++		    "d" (count)
+ 		  : "r11", "rcx", "memory");
++  if (__builtin_expect (res == -ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      __asm volatile ("syscall"
++		      : "=a" (res)
++		      : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wake),
++			"d" (count)
++		      : "r11", "rcx", "memory");
++    }
+ }
+ #else
+ # ifndef SYS_futex
+@@ -65,7 +85,7 @@ futex_wake (int *addr, int count)
+ 
+ # ifdef __PIC__
+ 
+-static inline void
++static inline long
+ sys_futex0 (int *addr, int op, int val)
+ {
+   long res;
+@@ -77,11 +97,12 @@ sys_futex0 (int *addr, int op, int val)
+ 		  : "0"(SYS_futex), "r" (addr), "c"(op),
+ 		    "d"(val), "S"(0)
+ 		  : "memory");
++  return res;
+ }
+ 
+ # else
+ 
+-static inline void
++static inline long
+ sys_futex0 (int *addr, int op, int val)
+ {
+   long res;
+@@ -91,6 +112,7 @@ sys_futex0 (int *addr, int op, int val)
+ 		  : "0"(SYS_futex), "b" (addr), "c"(op),
+ 		    "d"(val), "S"(0)
+ 		  : "memory");
++  return res;
+ }
+ 
+ # endif /* __PIC__ */
+@@ -98,13 +120,37 @@ sys_futex0 (int *addr, int op, int val)
+ static inline void
+ futex_wait (int *addr, int val)
+ {
+-  sys_futex0 (addr, FUTEX_WAIT, val);
++  long res = sys_futex0 (addr, gomp_futex_wait, val);
++  if (__builtin_expect (res == -ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wait, val);
++    }
+ }
+ 
+ static inline void
+ futex_wake (int *addr, int count)
+ {
+-  sys_futex0 (addr, FUTEX_WAKE, count);
++  long res = sys_futex0 (addr, gomp_futex_wake, count);
++  if (__builtin_expect (res == -ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wake, count);
++    }
+ }
+ 
+ #endif /* __LP64__ */
++
++static inline void
++cpu_relax (void)
++{
++  __asm volatile ("rep; nop" : : : "memory");
++}
++
++static inline void
++atomic_write_barrier (void)
++{
++  __sync_synchronize ();
++}
+--- libgomp/config/linux/wait.h.jj	2008-03-26 15:11:32.000000000 +0100
++++ libgomp/config/linux/wait.h	2008-03-26 15:11:32.000000000 +0100
+@@ -0,0 +1,68 @@
++/* Copyright (C) 2008 Free Software Foundation, Inc.
++   Contributed by Jakub Jelinek <jakub@redhat.com>.
++
++   This file is part of the GNU OpenMP Library (libgomp).
++
++   Libgomp is free software; you can redistribute it and/or modify it
++   under the terms of the GNU Lesser General Public License as published by
++   the Free Software Foundation; either version 2.1 of the License, or
++   (at your option) any later version.
++
++   Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
++   FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for
++   more details.
++
++   You should have received a copy of the GNU Lesser General Public License 
++   along with libgomp; see the file COPYING.LIB.  If not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++   MA 02110-1301, USA.  */
++
++/* As a special exception, if you link this library with other files, some
++   of which are compiled with GCC, to produce an executable, this library
++   does not by itself cause the resulting executable to be covered by the
++   GNU General Public License.  This exception does not however invalidate
++   any other reasons why the executable file might be covered by the GNU
++   General Public License.  */
++
++/* This is a Linux specific implementation of a mutex synchronization
++   mechanism for libgomp.  This type is private to the library.  This
++   implementation uses atomic instructions and the futex syscall.  */
++
++#ifndef GOMP_WAIT_H
++#define GOMP_WAIT_H 1
++
++#include "libgomp.h"
++#include <errno.h>
++
++#define FUTEX_WAIT	0
++#define FUTEX_WAKE	1
++#define FUTEX_PRIVATE_FLAG	128L
++
++#ifdef HAVE_ATTRIBUTE_VISIBILITY
++# pragma GCC visibility push(hidden)
++#endif
++
++extern long int gomp_futex_wait, gomp_futex_wake;
++
++#include "futex.h"
++
++static inline void do_wait (int *addr, int val)
++{
++  unsigned long long i, count = gomp_spin_count_var;
++
++  if (__builtin_expect (gomp_managed_threads > gomp_available_cpus, 0))
++    count = gomp_throttled_spin_count_var;
++  for (i = 0; i < count; i++)
++    if (__builtin_expect (*addr != val, 0))
++      return;
++    else
++      cpu_relax ();
++  futex_wait (addr, val);
++}
++
++#ifdef HAVE_ATTRIBUTE_VISIBILITY
++# pragma GCC visibility pop
++#endif
++
++#endif /* GOMP_WAIT_H */
+--- libgomp/config/linux/sparc/futex.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/sparc/futex.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Jakub Jelinek <jakub@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -28,10 +28,8 @@
+ /* Provide target-specific access to the futex system call.  */
+ 
+ #include <sys/syscall.h>
+-#define FUTEX_WAIT	0
+-#define FUTEX_WAKE	1
+ 
+-static inline void
++static inline long
+ sys_futex0 (int *addr, int op, int val)
+ {
+   register long int g1  __asm__ ("g1");
+@@ -47,9 +45,9 @@ sys_futex0 (int *addr, int op, int val)
+   o3 = 0;
+ 
+ #ifdef __arch64__
+-# define SYSCALL_STRING "ta\t0x6d"
++# define SYSCALL_STRING "ta\t0x6d; bcs,a,pt %%xcc, 1f; sub %%g0, %%o0, %%o0; 1:"
+ #else
+-# define SYSCALL_STRING "ta\t0x10"
++# define SYSCALL_STRING "ta\t0x10; bcs,a 1f; sub %%g0, %%o0, %%o0; 1:"
+ #endif
+ 
+   __asm volatile (SYSCALL_STRING
+@@ -65,16 +63,49 @@ sys_futex0 (int *addr, int op, int val)
+ 		    "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
+ #endif
+ 		    "cc", "memory");
++  return o0;
+ }
+ 
+ static inline void
+ futex_wait (int *addr, int val)
+ {
+-  sys_futex0 (addr, FUTEX_WAIT, val);
++  long err = sys_futex0 (addr, gomp_futex_wait, val);
++  if (__builtin_expect (err == ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wait, val);
++    }
+ }
+ 
+ static inline void
+ futex_wake (int *addr, int count)
+ {
+-  sys_futex0 (addr, FUTEX_WAKE, count);
++  long err = sys_futex0 (addr, gomp_futex_wake, count);
++  if (__builtin_expect (err == ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wake, count);
++    }
++}
++
++static inline void
++cpu_relax (void)
++{
++#if defined __arch64__ || defined  __sparc_v9__
++  __asm volatile ("membar #LoadLoad" : : : "memory");
++#else
++  __asm volatile ("" : : : "memory");
++#endif
++}
++
++static inline void
++atomic_write_barrier (void)
++{
++#if defined __arch64__ || defined __sparc_v9__
++  __asm volatile ("membar #StoreStore" : : : "memory");
++#else
++  __sync_synchronize ();
++#endif
+ }
+--- libgomp/config/linux/ia64/futex.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/ia64/futex.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -29,23 +29,24 @@
+ 
+ #include <sys/syscall.h>
+ 
+-#define FUTEX_WAIT	0
+-#define FUTEX_WAKE	1
+ 
+ 
+-static inline void
+-sys_futex0(int *addr, int op, int val)
++static inline long
++sys_futex0(int *addr, long op, int val)
+ {
+   register long out0 asm ("out0") = (long) addr;
+   register long out1 asm ("out1") = op;
+   register long out2 asm ("out2") = val;
+   register long out3 asm ("out3") = 0;
++  register long r8 asm ("r8");
++  register long r10 asm ("r10");
+   register long r15 asm ("r15") = SYS_futex;
+ 
+   __asm __volatile ("break 0x100000"
+-	: "=r"(r15), "=r"(out0), "=r"(out1), "=r"(out2), "=r"(out3)
++	: "=r"(r15), "=r"(out0), "=r"(out1), "=r"(out2), "=r"(out3),
++	  "=r"(r8), "=r"(r10)
+ 	: "r"(r15), "r"(out0), "r"(out1), "r"(out2), "r"(out3)
+-        : "memory", "r8", "r10", "out4", "out5", "out6", "out7",
++	: "memory", "out4", "out5", "out6", "out7",
+ 	  /* Non-stacked integer registers, minus r8, r10, r15.  */
+ 	  "r2", "r3", "r9", "r11", "r12", "r13", "r14", "r16", "r17", "r18",
+ 	  "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27",
+@@ -56,16 +57,41 @@ sys_futex0(int *addr, int op, int val)
+ 	  "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ 	  /* Branch registers.  */
+ 	  "b6");
++  return r8 & r10;
+ }
+ 
+ static inline void
+ futex_wait (int *addr, int val)
+ {
+-  sys_futex0 (addr, FUTEX_WAIT, val);
++  long err = sys_futex0 (addr, gomp_futex_wait, val);
++  if (__builtin_expect (err == ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wait, val);
++    }
+ }
+ 
+ static inline void
+ futex_wake (int *addr, int count)
+ {
+-  sys_futex0 (addr, FUTEX_WAKE, count);
++  long err = sys_futex0 (addr, gomp_futex_wake, count);
++  if (__builtin_expect (err == ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wake, count);
++    }
++}
++
++static inline void
++cpu_relax (void)
++{
++  __asm volatile ("hint @pause" : : : "memory");
++}
++
++static inline void
++atomic_write_barrier (void)
++{
++  __sync_synchronize ();
+ }
+--- libgomp/config/linux/s390/futex.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/s390/futex.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Jakub Jelinek <jakub@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -28,10 +28,8 @@
+ /* Provide target-specific access to the futex system call.  */
+ 
+ #include <sys/syscall.h>
+-#define FUTEX_WAIT	0
+-#define FUTEX_WAKE	1
+ 
+-static inline void
++static inline long
+ sys_futex0 (int *addr, int op, int val)
+ {
+   register long int gpr2  __asm__ ("2");
+@@ -49,16 +47,41 @@ sys_futex0 (int *addr, int op, int val)
+ 		  : "i" (SYS_futex),
+ 		    "0" (gpr2), "d" (gpr3), "d" (gpr4), "d" (gpr5)
+ 		  : "memory");
++  return gpr2;
+ }
+ 
+ static inline void
+ futex_wait (int *addr, int val)
+ {
+-  sys_futex0 (addr, FUTEX_WAIT, val);
++  long err = sys_futex0 (addr, gomp_futex_wait, val);
++  if (__builtin_expect (err == -ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wait, val);
++    }
+ }
+ 
+ static inline void
+ futex_wake (int *addr, int count)
+ {
+-  sys_futex0 (addr, FUTEX_WAKE, count);
++  long err = sys_futex0 (addr, gomp_futex_wake, count);
++  if (__builtin_expect (err == -ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wake, count);
++    }
++}
++
++static inline void
++cpu_relax (void)
++{
++  __asm volatile ("" : : : "memory");
++}
++
++static inline void
++atomic_write_barrier (void)
++{
++  __sync_synchronize ();
+ }
+--- libgomp/config/linux/mutex.c.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/mutex.c	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -29,9 +29,10 @@
+    mechanism for libgomp.  This type is private to the library.  This
+    implementation uses atomic instructions and the futex syscall.  */
+ 
+-#include "libgomp.h"
+-#include "futex.h"
++#include "wait.h"
+ 
++long int gomp_futex_wake = FUTEX_WAKE | FUTEX_PRIVATE_FLAG;
++long int gomp_futex_wait = FUTEX_WAIT | FUTEX_PRIVATE_FLAG;
+ 
+ void
+ gomp_mutex_lock_slow (gomp_mutex_t *mutex)
+@@ -40,7 +41,7 @@ gomp_mutex_lock_slow (gomp_mutex_t *mute
+     {
+       int oldval = __sync_val_compare_and_swap (mutex, 1, 2);
+       if (oldval != 0)
+-        futex_wait (mutex, 2);
++	do_wait (mutex, 2);
+     }
+   while (!__sync_bool_compare_and_swap (mutex, 0, 2));
+ }
+--- libgomp/config/linux/sem.c.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/sem.c	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -29,8 +29,7 @@
+    mechanism for libgomp.  This type is private to the library.  This 
+    implementation uses atomic instructions and the futex syscall.  */
+ 
+-#include "libgomp.h"
+-#include "futex.h"
++#include "wait.h"
+ 
+ 
+ void
+@@ -44,7 +43,7 @@ gomp_sem_wait_slow (gomp_sem_t *sem)
+ 	  if (__sync_bool_compare_and_swap (sem, val, val - 1))
+ 	    return;
+ 	}
+-      futex_wait (sem, -1);
++      do_wait (sem, -1);
+     }
+ }
+ 
+--- libgomp/config/linux/powerpc/futex.h.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/powerpc/futex.h	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -28,10 +28,8 @@
+ /* Provide target-specific access to the futex system call.  */
+ 
+ #include <sys/syscall.h>
+-#define FUTEX_WAIT	0
+-#define FUTEX_WAKE	1
+ 
+-static inline void
++static inline long
+ sys_futex0 (int *addr, int op, int val)
+ {
+   register long int r0  __asm__ ("r0");
+@@ -50,21 +48,48 @@ sys_futex0 (int *addr, int op, int val)
+      doesn't.  It doesn't much matter for us.  In the interest of unity,
+      go ahead and clobber it always.  */
+ 
+-  __asm volatile ("sc"
++  __asm volatile ("sc; mfcr %0"
+ 		  : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6)
+ 		  : "r"(r0), "r"(r3), "r"(r4), "r"(r5), "r"(r6)
+ 		  : "r7", "r8", "r9", "r10", "r11", "r12",
+ 		    "cr0", "ctr", "memory");
++  if (__builtin_expect (r0 & (1 << 28), 0))
++    return r3;
++  return 0;
+ }
+ 
+ static inline void
+ futex_wait (int *addr, int val)
+ {
+-  sys_futex0 (addr, FUTEX_WAIT, val);
++  long err = sys_futex0 (addr, gomp_futex_wait, val);
++  if (__builtin_expect (err == ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wait, val);
++    }
+ }
+ 
+ static inline void
+ futex_wake (int *addr, int count)
+ {
+-  sys_futex0 (addr, FUTEX_WAKE, count);
++  long err = sys_futex0 (addr, gomp_futex_wake, count);
++  if (__builtin_expect (err == ENOSYS, 0))
++    {
++      gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG;
++      gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG;
++      sys_futex0 (addr, gomp_futex_wake, count);
++    }
++}
++
++static inline void
++cpu_relax (void)
++{
++  __asm volatile ("" : : : "memory");
++}
++
++static inline void
++atomic_write_barrier (void)
++{
++  __asm volatile ("eieio" : : : "memory");
+ }
+--- libgomp/config/linux/bar.c.jj	2007-12-07 14:41:00.000000000 +0100
++++ libgomp/config/linux/bar.c	2008-03-26 15:11:32.000000000 +0100
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2005 Free Software Foundation, Inc.
++/* Copyright (C) 2005, 2008 Free Software Foundation, Inc.
+    Contributed by Richard Henderson <rth@redhat.com>.
+ 
+    This file is part of the GNU OpenMP Library (libgomp).
+@@ -29,32 +29,29 @@
+    mechanism for libgomp.  This type is private to the library.  This 
+    implementation uses atomic instructions and the futex syscall.  */
+ 
+-#include "libgomp.h"
+-#include "futex.h"
+ #include <limits.h>
++#include "wait.h"
+ 
+ 
+ void
+-gomp_barrier_wait_end (gomp_barrier_t *bar, bool last)
++gomp_barrier_wait_end (gomp_barrier_t *bar, gomp_barrier_state_t state)
+ {
+-  if (last)
++  if (__builtin_expect ((state & 1) != 0, 0))
+     {
+-      bar->generation++;
+-      futex_wake (&bar->generation, INT_MAX);
++      /* Next time we'll be awaiting TOTAL threads again.  */
++      bar->awaited = bar->total;
++      atomic_write_barrier ();
++      bar->generation += 2;
++      futex_wake ((int *) &bar->generation, INT_MAX);
+     }
+   else
+     {
+-      unsigned int generation = bar->generation;
+-
+-      gomp_mutex_unlock (&bar->mutex);
++      unsigned int generation = state;
+ 
+       do
+-	futex_wait (&bar->generation, generation);
++	do_wait ((int *) &bar->generation, generation);
+       while (bar->generation == generation);
+     }
+-
+-  if (__sync_add_and_fetch (&bar->arrived, -1) == 0)
+-    gomp_mutex_unlock (&bar->mutex);
+ }
+ 
+ void
+@@ -62,3 +59,18 @@ gomp_barrier_wait (gomp_barrier_t *barri
+ {
+   gomp_barrier_wait_end (barrier, gomp_barrier_wait_start (barrier));
+ }
++
++/* Like gomp_barrier_wait, except that if the encountering thread
++   is not the last one to hit the barrier, it returns immediately.
++   The intended usage is that a thread which intends to gomp_barrier_destroy
++   this barrier calls gomp_barrier_wait, while all other threads
++   call gomp_barrier_wait_last.  When gomp_barrier_wait returns,
++   the barrier can be safely destroyed.  */
++
++void
++gomp_barrier_wait_last (gomp_barrier_t *barrier)
++{
++  gomp_barrier_state_t state = gomp_barrier_wait_start (barrier);
++  if (state & 1)
++    gomp_barrier_wait_end (barrier, state);
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch
new file mode 100644
index 0000000000..3de4158eb0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch
@@ -0,0 +1,90 @@
+2005-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/rs6000/rs6000.c (rs6000_return_addr): If COUNT == 0,
+	read word RETURN_ADDRESS_OFFSET bytes above arg_pointer_rtx
+	instead of doing an extran indirection from frame_pointer_rtx.
+
+	* gcc.dg/20051128-1.c: New test.
+
+Index: gcc/config/rs6000/rs6000.c
+===================================================================
+--- gcc/config/rs6000/rs6000.c.orig	2010-03-27 03:27:39.000000000 -0700
++++ gcc/config/rs6000/rs6000.c	2010-06-25 10:18:04.053381930 -0700
+@@ -17646,17 +17646,22 @@
+      don't try to be too clever here.  */
+   if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
+     {
++      rtx x;
+       cfun->machine->ra_needs_full_frame = 1;
+ 
+-      return
+-	gen_rtx_MEM
+-	  (Pmode,
+-	   memory_address
+-	   (Pmode,
+-	    plus_constant (copy_to_reg
+-			   (gen_rtx_MEM (Pmode,
+-					 memory_address (Pmode, frame))),
+-			   RETURN_ADDRESS_OFFSET)));
++      if (count == 0)
++	{
++	  gcc_assert (frame == frame_pointer_rtx);
++	  x = arg_pointer_rtx;
++	}
++      else
++	{
++	  x = memory_address (Pmode, frame);
++	  x = copy_to_reg (gen_rtx_MEM (Pmode, x));
++	}
++
++      x = plus_constant (x, RETURN_ADDRESS_OFFSET);
++      return gen_rtx_MEM (Pmode, memory_address (Pmode, x));
+     }
+ 
+   cfun->machine->ra_need_lr = 1;
+Index: gcc/testsuite/gcc.dg/20051128-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/testsuite/gcc.dg/20051128-1.c	2010-06-25 10:18:04.061382856 -0700
+@@ -0,0 +1,41 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fpic" } */
++
++extern void exit (int);
++extern void abort (void);
++
++int b;
++
++struct A
++{
++  void *pad[147];
++  void *ra, *h;
++  long o;
++};
++
++void
++__attribute__((noinline))
++foo (struct A *a, void *x)
++{
++  __builtin_memset (a, 0, sizeof (a));
++  if (!b)
++    exit (0);
++}
++
++void
++__attribute__((noinline))
++bar (void)
++{
++  struct A a;
++
++  __builtin_unwind_init ();
++  foo (&a, __builtin_return_address (0));
++}
++
++int
++main (void)
++{
++  bar ();
++  abort ();
++  return 0;
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch
new file mode 100644
index 0000000000..172bb81171
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch
@@ -0,0 +1,16 @@
+2006-08-18  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/27898
+	* gcc.dg/pr27898.c: New test.
+
+--- gcc/testsuite/gcc.dg/pr27898.c.jj	2006-08-18 09:19:33.000000000 +0200
++++ gcc/testsuite/gcc.dg/pr27898.c	2006-08-18 09:19:27.000000000 +0200
+@@ -0,0 +1,8 @@
++/* PR c/27898 */
++/* { dg-do compile } */
++/* { dg-options "--combine" } */
++/* { dg-additional-sources "pr27898.c" } */
++
++union u { struct { int i; }; };
++
++extern int foo (union u *);
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch
new file mode 100644
index 0000000000..f35696703d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch
@@ -0,0 +1,19 @@
+2007-06-01  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/32139
+	* gcc.c-torture/compile/20070531-1.c: New test.
+
+--- gcc/testsuite/gcc.c-torture/compile/20070531-1.c.jj	2007-05-31 13:47:22.000000000 +0200
++++ gcc/testsuite/gcc.c-torture/compile/20070531-1.c	2007-06-01 10:57:15.000000000 +0200
+@@ -0,0 +1,11 @@
++/* PR tree-optimization/32139 */
++int foo (void);
++int bar (void) __attribute__ ((const));
++
++int
++test (int x)
++{
++  int a = (x == 10000 ? foo : bar) ();
++  int b = (x == 10000 ? foo : bar) ();
++  return a + b;
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch
new file mode 100644
index 0000000000..68c30650ff
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch
@@ -0,0 +1,159 @@
+2007-11-06  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/33763
+	* gcc.dg/pr33763.c: New test.
+	* g++.dg/opt/inline13.C: New test.
+
+2007-11-06  Jan Hubicka  <jh@suse.cz>
+
+	PR tree-optimization/33763
+	* tree-inline.c (expand_call_inline): Silently ignore always_inline
+	attribute for redefined extern inline functions.
+
+Index: gcc/tree-inline.c
+===================================================================
+--- gcc/tree-inline.c.orig	2010-03-18 13:07:13.000000000 -0700
++++ gcc/tree-inline.c	2010-06-25 10:18:51.230139825 -0700
+@@ -3545,6 +3545,12 @@
+ 	goto egress;
+ 
+       if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (fn))
++	/* For extern inline functions that get redefined we always
++	   silently ignored alway_inline flag. Better behaviour would
++	   be to be able to keep both bodies and use extern inline body
++	   for inlining, but we can't do that because frontends overwrite
++	   the body.  */
++	  && !cg_edge->callee->local.redefined_extern_inline
+ 	  /* Avoid warnings during early inline pass. */
+ 	  && cgraph_global_info_ready)
+ 	{
+Index: gcc/testsuite/gcc.dg/pr33763.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/testsuite/gcc.dg/pr33763.c	2010-06-25 10:18:51.234141302 -0700
+@@ -0,0 +1,60 @@
++/* PR tree-optimization/33763 */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef struct
++{
++  void *a;
++  void *b;
++} T;
++extern void *foo (const char *, const char *);
++extern void *bar (void *, const char *, T);
++extern int baz (const char *, int);
++
++extern inline __attribute__ ((always_inline, gnu_inline)) int
++baz (const char *x, int y)
++{
++  return 2;
++}
++
++int
++baz (const char *x, int y)
++{
++  return 1;
++}
++
++int xa, xb;
++
++static void *
++inl (const char *x, const char *y)
++{
++  T t = { &xa, &xb };
++  int *f = (int *) __builtin_malloc (sizeof (int));
++  const char *z;
++  int o = 0;
++  void *r = 0;
++
++  for (z = y; *z; z++)
++    {
++      if (*z == 'r')
++	o |= 1;
++      if (*z == 'w')
++	o |= 2;
++    }
++  if (o == 1)
++    *f = baz (x, 0);
++  if (o == 2)
++    *f = baz (x, 1);
++  if (o == 3)
++    *f = baz (x, 2);
++
++  if (o && *f > 0)
++    r = bar (f, "w", t);
++  return r;
++}
++
++void *
++foo (const char *x, const char *y)
++{
++  return inl (x, y);
++}
+Index: gcc/testsuite/g++.dg/opt/inline13.C
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc/testsuite/g++.dg/opt/inline13.C	2010-06-25 10:18:51.261052137 -0700
+@@ -0,0 +1,60 @@
++// PR tree-optimization/33763
++// { dg-do compile }
++// { dg-options "-O2" }
++
++typedef struct
++{
++  void *a;
++  void *b;
++} T;
++extern void *foo (const char *, const char *);
++extern void *bar (void *, const char *, T);
++extern int baz (const char *, int);
++
++extern inline __attribute__ ((always_inline, gnu_inline)) int
++baz (const char *x, int y)
++{
++  return 2;
++}
++
++int
++baz (const char *x, int y)
++{
++  return 1;
++}
++
++int xa, xb;
++
++static void *
++inl (const char *x, const char *y)
++{
++  T t = { &xa, &xb };
++  int *f = (int *) __builtin_malloc (sizeof (int));
++  const char *z;
++  int o = 0;
++  void *r = 0;
++
++  for (z = y; *z; z++)
++    {
++      if (*z == 'r')
++	o |= 1;
++      if (*z == 'w')
++	o |= 2;
++    }
++  if (o == 1)
++    *f = baz (x, 0);
++  if (o == 2)
++    *f = baz (x, 1);
++  if (o == 3)
++    *f = baz (x, 2);
++
++  if (o && *f > 0)
++    r = bar (f, "w", t);
++  return r;
++}
++
++void *
++foo (const char *x, const char *y)
++{
++  return inl (x, y);
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch
new file mode 100644
index 0000000000..e96ae6f134
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch
@@ -0,0 +1,89 @@
+2008-04-01  Jakub Jelinek  <jakub@redhat.com>
+
+	PR pch/13675
+	* files.c (struct _cpp_file): Remove pch field.
+	(pch_open_file): Don't set file->pch, just file->pchname.
+	(should_stack_file): After pfile->cb.read_pch call
+	free pchname and clear pchname, don't close file->fd.
+	Test file->pchname instead of file->pch.  Don't close fd after cb.
+	(_cpp_stack_include): Test file->pchname instead of file->pch.
+
+	* c-pch.c (c_common_read_pch): On error close (fd) resp. fclose (f).
+
+--- libcpp/files.c.jj	2008-02-18 23:50:17.000000000 +0100
++++ libcpp/files.c	2008-03-31 15:59:01.000000000 +0200
+@@ -106,9 +106,6 @@ struct _cpp_file
+ 
+   /* If BUFFER above contains the true contents of the file.  */
+   bool buffer_valid;
+-
+-  /* File is a PCH (on return from find_include_file).  */
+-  bool pch;
+ };
+ 
+ /* A singly-linked list for all searches for a given file name, with
+@@ -322,9 +319,7 @@ pch_open_file (cpp_reader *pfile, _cpp_f
+ 	    }
+ 	  closedir (pchdir);
+ 	}
+-      if (valid)
+-	file->pch = true;
+-      else
++      if (!valid)
+ 	*invalid_pch = true;
+     }
+ 
+@@ -703,11 +698,12 @@ should_stack_file (cpp_reader *pfile, _c
+     return false;
+ 
+   /* Handle PCH files immediately; don't stack them.  */
+-  if (file->pch)
++  if (file->pchname)
+     {
+       pfile->cb.read_pch (pfile, file->pchname, file->fd, file->path);
+-      close (file->fd);
+       file->fd = -1;
++      free ((void *) file->pchname);
++      file->pchname = NULL;
+       return false;
+     }
+ 
+@@ -916,7 +912,7 @@ _cpp_stack_include (cpp_reader *pfile, c
+      complicates LAST_SOURCE_LINE_LOCATION.  This does not apply if we
+      found a PCH file (in which case linemap_add is not called) or we
+      were included from the command-line.  */
+-  if (! file->pch && file->err_no == 0 && type != IT_CMDLINE)
++  if (file->pchname == NULL && file->err_no == 0 && type != IT_CMDLINE)
+     pfile->line_table->highest_location--;
+ 
+   return _cpp_stack_file (pfile, file, type == IT_IMPORT);
+--- gcc/c-pch.c.jj	2008-02-18 23:46:08.000000000 +0100
++++ gcc/c-pch.c	2008-03-31 15:56:00.000000000 +0200
+@@ -372,6 +372,7 @@ c_common_read_pch (cpp_reader *pfile, co
+   if (f == NULL)
+     {
+       cpp_errno (pfile, CPP_DL_ERROR, "calling fdopen");
++      close (fd);
+       return;
+     }
+ 
+@@ -380,6 +381,7 @@ c_common_read_pch (cpp_reader *pfile, co
+   if (fread (&h, sizeof (h), 1, f) != 1)
+     {
+       cpp_errno (pfile, CPP_DL_ERROR, "reading");
++      fclose (f);
+       return;
+     }
+ 
+@@ -425,7 +427,10 @@ c_common_read_pch (cpp_reader *pfile, co
+   gt_pch_restore (f);
+ 
+   if (cpp_read_state (pfile, name, f, smd) != 0)
+-    return;
++    {
++      fclose (f);
++      return;
++    }
+ 
+   fclose (f);
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch
new file mode 100644
index 0000000000..4888ac47dd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch
@@ -0,0 +1,31 @@
+2007-10-16  Jakub Jelinek  <jakub@redhat.com>
+
+	* Makefile.am (libgcj_tools_la_LIBADD): Add.
+	* Makefile.in: Regenerated.
+
+Index: libjava/Makefile.am
+===================================================================
+--- libjava/Makefile.am.orig	2010-03-21 12:41:37.000000000 -0700
++++ libjava/Makefile.am	2010-06-25 10:22:11.394130458 -0700
+@@ -507,6 +507,8 @@
+ libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS) -findirect-dispatch \
+  -fno-bootstrap-classes -fno-indirect-classes \
+  -fsource-filename=$(here)/classpath/tools/all-classes.lst
++## See jv_convert_LDADD.
++libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la
+ libgcj_tools_la_LDFLAGS = -rpath $(toolexeclibdir) \
+  -version-info `grep -v '^\#' $(srcdir)/libtool-version` \
+  $(LIBGCJ_LD_SYMBOLIC_FUNCTIONS) $(LIBJAVA_LDFLAGS_NOUNDEF)
+Index: libjava/Makefile.in
+===================================================================
+--- libjava/Makefile.in.orig	2010-04-02 11:18:06.000000000 -0700
++++ libjava/Makefile.in	2010-06-25 10:27:41.841708512 -0700
+@@ -1190,7 +1190,7 @@
+  -version-info `grep -v '^\#' $(srcdir)/libtool-version` \
+  $(LIBGCJ_LD_SYMBOLIC_FUNCTIONS) $(LIBJAVA_LDFLAGS_NOUNDEF)
+ 
+-libgcj_tools_la_LIBADD = libgcj.la -lm
++libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la -lm
+ libgcj_tools_la_DEPENDENCIES = libgcj.la libgcj.spec $(am__append_22)
+ libgcj_tools_la_LINK = $(LIBLINK) $(libgcj_tools_la_LDFLAGS)
+ libjvm_la_SOURCES = jni-libjvm.cc
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch
new file mode 100644
index 0000000000..7e2801b99b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch
@@ -0,0 +1,32 @@
+2007-10-21  Jakub Jelinek  <jakub@redhat.com>
+
+	* doc/Makefile.am (POD2MAN): Set date from cp-tools.texinfo
+	timestamp rather than from current date.
+	* doc/Makefile.in: Regenerated.
+
+Index: libjava/classpath/doc/Makefile.am
+===================================================================
+--- libjava/classpath/doc/Makefile.am.orig	2008-10-21 10:55:01.000000000 -0700
++++ libjava/classpath/doc/Makefile.am	2010-06-25 10:28:30.237631599 -0700
+@@ -31,7 +31,7 @@
+ 	gtnameserv.1 \
+ 	gjdoc.1
+ 
+-POD2MAN = pod2man --center="GNU" --release="$(VERSION)"
++POD2MAN = pod2man --center="GNU" --release="$(VERSION)" --date="$(shell ls --time-style=+%F -l $(srcdir)/cp-tools.texinfo | awk '{print $$6}')"
+ TEXI2POD = perl $(srcdir)/texi2pod.pl
+ STAMP = echo timestamp >
+ 
+Index: libjava/classpath/doc/Makefile.in
+===================================================================
+--- libjava/classpath/doc/Makefile.in.orig	2010-04-02 11:18:06.000000000 -0700
++++ libjava/classpath/doc/Makefile.in	2010-06-25 10:28:30.245635728 -0700
+@@ -376,7 +376,7 @@
+ 	gtnameserv.1 \
+ 	gjdoc.1
+ 
+-POD2MAN = pod2man --center="GNU" --release="$(VERSION)"
++POD2MAN = pod2man --center="GNU" --release="$(VERSION)" --date="$(shell ls --time-style=+%F -l $(srcdir)/cp-tools.texinfo | awk '{print $$6}')"
+ TEXI2POD = perl $(srcdir)/texi2pod.pl
+ STAMP = echo timestamp >
+ @GENINSRC_FALSE@STAMP_GENINSRC = 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch
new file mode 100644
index 0000000000..bf03c27852
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch
@@ -0,0 +1,60 @@
+2010-02-08  Roland McGrath  <roland@redhat.com>
+
+	* config/rs6000/sysv4.h (LINK_EH_SPEC): Pass --no-add-needed to the
+	linker.
+	* config/linux.h (LINK_EH_SPEC): Likewise.
+	* config/alpha/elf.h (LINK_EH_SPEC): Likewise.
+	* config/ia64/linux.h (LINK_EH_SPEC): Likewise.
+
+Index: gcc/config/alpha/elf.h
+===================================================================
+--- gcc/config/alpha/elf.h.orig	2011-06-16 17:58:47.000000000 -0700
++++ gcc/config/alpha/elf.h	2011-09-17 11:04:57.033298875 -0700
+@@ -441,7 +441,7 @@ extern int alpha_this_gpdisp_sequence_nu
+    I imagine that other systems will catch up.  In the meantime, it
+    doesn't harm to make sure that the data exists to be used later.  */
+ #if defined(HAVE_LD_EH_FRAME_HDR)
+-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
++#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
+ #endif
+ 
+ /* A C statement (sans semicolon) to output to the stdio stream STREAM
+Index: gcc/config/ia64/linux.h
+===================================================================
+--- gcc/config/ia64/linux.h.orig	2011-09-17 11:03:19.000000000 -0700
++++ gcc/config/ia64/linux.h	2011-09-17 11:04:57.033298875 -0700
+@@ -80,7 +80,7 @@ do {						\
+    Signalize that because we have fde-glibc, we don't need all C shared libs
+    linked against -lgcc_s.  */
+ #undef LINK_EH_SPEC
+-#define LINK_EH_SPEC ""
++#define LINK_EH_SPEC "--no-add-needed "
+ 
+ #define MD_UNWIND_SUPPORT "config/ia64/linux-unwind.h"
+ 
+Index: gcc/config/linux.h
+===================================================================
+--- gcc/config/linux.h.orig	2011-09-17 11:03:38.000000000 -0700
++++ gcc/config/linux.h	2011-09-17 11:04:57.033298875 -0700
+@@ -101,7 +101,7 @@ see the files COPYING3 and COPYING.RUNTI
+     } while (0)
+ 
+ #if defined(HAVE_LD_EH_FRAME_HDR)
+-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
++#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
+ #endif
+ 
+ /* Define this so we can compile MS code for use with WINE.  */
+Index: gcc/config/rs6000/sysv4.h
+===================================================================
+--- gcc/config/rs6000/sysv4.h.orig	2011-09-17 11:03:41.000000000 -0700
++++ gcc/config/rs6000/sysv4.h	2011-09-17 11:05:58.653298861 -0700
+@@ -908,7 +908,7 @@ SVR4_ASM_SPEC \
+ 
+ #if defined(HAVE_LD_EH_FRAME_HDR)
+ # undef LINK_EH_SPEC
+-# define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
++# define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
+ #endif
+ 
+ #define CPP_OS_LINUX_SPEC "-D__unix__ -D__gnu_linux__ -D__linux__ \
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch
new file mode 100644
index 0000000000..348c77006f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch
@@ -0,0 +1,30 @@
+* Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used
+  used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross
+  directory.
+
+Index: gcc-4.5+svnr155514/libgfortran/configure
+===================================================================
+--- gcc-4.5+svnr155514.orig/libgfortran/configure	2009-12-29 22:02:01.000000000 -0800
++++ gcc-4.5+svnr155514/libgfortran/configure	2009-12-30 08:12:40.889091657 -0800
+@@ -11655,7 +11655,7 @@ CC="$lt_save_CC"
+ 
+ # We need gfortran to compile parts of the library
+ #AC_PROG_FC(gfortran)
+-FC="$GFORTRAN"
++#FC="$GFORTRAN"
+ ac_ext=${ac_fc_srcext-f}
+ ac_compile='$FC -c $FCFLAGS $ac_fcflags_srcext conftest.$ac_ext >&5'
+ ac_link='$FC -o conftest$ac_exeext $FCFLAGS $LDFLAGS $ac_fcflags_srcext conftest.$ac_ext $LIBS >&5'
+Index: gcc-4.5+svnr155514/libgfortran/configure.ac
+===================================================================
+--- gcc-4.5+svnr155514.orig/libgfortran/configure.ac	2009-12-29 22:02:01.000000000 -0800
++++ gcc-4.5+svnr155514/libgfortran/configure.ac	2009-12-30 08:12:13.453094218 -0800
+@@ -187,7 +187,7 @@ AC_SUBST(enable_static)
+ 
+ # We need gfortran to compile parts of the library
+ #AC_PROG_FC(gfortran)
+-FC="$GFORTRAN"
++#FC="$GFORTRAN"
+ AC_PROG_FC(gfortran)
+ 
+ # extra LD Flags which are required for targets
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch
new file mode 100644
index 0000000000..d1df8b2716
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch
@@ -0,0 +1,319 @@
+Adds support for Freescale Power architecture e300c2 and e300c3 cores.
+http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
+
+Leon Woestenberg <leonw@mailcan.com>
+
+---
+ gcc/config.gcc                |    2 
+ gcc/config/rs6000/e300c2c3.md |  189 ++++++++++++++++++++++++++++++++++++++++++
+ gcc/config/rs6000/rs6000.c    |   24 +++++
+ gcc/config/rs6000/rs6000.h    |    4 
+ gcc/config/rs6000/rs6000.md   |    3 
+ 5 files changed, 220 insertions(+), 2 deletions(-)
+
+Index: gcc-4.3.1/gcc/config/rs6000/e300c2c3.md
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4.3.1/gcc/config/rs6000/e300c2c3.md	2008-08-23 16:51:33.000000000 -0700
+@@ -0,0 +1,189 @@
++;; Pipeline description for Motorola PowerPC e300c3 core.
++;;   Copyright (C) 2003 Free Software Foundation, Inc.
++;;
++;; This file is part of GCC.
++
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published
++;; by the Free Software Foundation; either version 2, or (at your
++;; option) any later version.
++
++;; GCC is distributed in the hope that it will be useful, but WITHOUT
++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++;; License for more details.
++
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING.  If not, write to the
++;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
++;; MA 02111-1307, USA.
++
++(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
++(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
++
++;; We don't simulate general issue queue (GIC).  If we have SU insn
++;; and then SU1 insn, they can not be issued on the same cycle
++;; (although SU1 insn and then SU insn can be issued) because the SU
++;; insn will go to SU1 from GIC0 entry.  Fortunately, the first cycle
++;; multipass insn scheduling will find the situation and issue the SU1
++;; insn and then the SU insn.
++(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1"   "ppce300c3_most")
++
++;; We could describe completion buffers slots in combination with the
++;; retirement units and the order of completion but the result
++;; automaton would behave in the same way because we can not describe
++;; real latency time with taking in order completion into account.
++;; Actually we could define the real latency time by querying reserved
++;; automaton units but the current scheduler uses latency time before
++;; issuing insns and making any reservations.
++;;
++;; So our description is aimed to achieve a insn schedule in which the
++;; insns would not wait in the completion buffer.
++(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
++
++;; Branch unit:
++(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
++
++;; IU:
++(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
++
++;; IU: This used to describe non-pipelined division.
++(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
++
++;; SRU:
++(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
++
++;; Here we simplified LSU unit description not describing the stages.
++(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
++
++;; FPU:
++(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
++
++;; The following units are used to make automata deterministic
++(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
++(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
++(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
++(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
++
++;; The following sets to make automata deterministic when option ndfa is used.
++(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
++(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
++(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
++(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
++
++;; Some useful abbreviations.
++(define_reservation "ppce300c3_decode"
++    "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
++(define_reservation "ppce300c3_issue"
++    "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
++(define_reservation "ppce300c3_retire"
++   "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
++(define_reservation "ppce300c3_iu_stage0"
++   "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
++
++;; Compares can be executed either one of the IU or SRU
++(define_insn_reservation "ppce300c3_cmp" 1
++  (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
++        +ppce300c3_retire")
++
++;; Other one cycle IU insns
++(define_insn_reservation "ppce300c3_iu" 1
++  (and (eq_attr "type" "integer,insert_word")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
++
++;; Branch.  Actually this latency time is not used by the scheduler.
++(define_insn_reservation "ppce300c3_branch" 1
++  (and (eq_attr "type" "jmpreg,branch")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
++
++;; Multiply is non-pipelined but can be executed in any IU
++(define_insn_reservation "ppce300c3_multiply" 2
++  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
++   ppce300c3_iu_stage0+ppce300c3_retire")
++
++;; Divide.  We use the average latency time here.  We omit reserving a
++;; retire unit because of the result automata will be huge.
++(define_insn_reservation "ppce300c3_divide" 20
++  (and (eq_attr "type" "idiv")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
++   ppce300c3_mu_div*19")
++
++;; CR logical
++(define_insn_reservation "ppce300c3_cr_logical" 1
++  (and (eq_attr "type" "cr_logical,delayed_cr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Mfcr
++(define_insn_reservation "ppce300c3_mfcr" 1
++  (and (eq_attr "type" "mfcr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Mtcrf
++(define_insn_reservation "ppce300c3_mtcrf" 1
++  (and (eq_attr "type" "mtcr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Mtjmpr
++(define_insn_reservation "ppce300c3_mtjmpr" 1
++  (and (eq_attr "type" "mtjmpr,mfjmpr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Float point instructions
++(define_insn_reservation "ppce300c3_fpcompare" 3
++  (and (eq_attr "type" "fpcompare")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_fp" 3
++  (and (eq_attr "type" "fp")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_dmul" 4
++  (and (eq_attr "type" "dmul")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
++
++; Divides are not pipelined
++(define_insn_reservation "ppce300c3_sdiv" 18
++  (and (eq_attr "type" "sdiv")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
++
++(define_insn_reservation "ppce300c3_ddiv" 33
++  (and (eq_attr "type" "ddiv")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
++
++;; Loads
++(define_insn_reservation "ppce300c3_load" 2
++  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_fpload" 2
++  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
++
++;; Stores.
++(define_insn_reservation "ppce300c3_store" 2
++  (and (eq_attr "type" "store,store_ux,store_u")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_fpstore" 2
++  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+Index: gcc-4.3.1/gcc/config/rs6000/rs6000.c
+===================================================================
+--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.c	2008-08-23 16:49:39.000000000 -0700
++++ gcc-4.3.1/gcc/config/rs6000/rs6000.c	2008-08-23 16:54:25.000000000 -0700
+@@ -669,6 +669,21 @@ struct processor_costs ppc8540_cost = {
+   1,			/* prefetch streams /*/
+ };
+ 
++/* Instruction costs on E300C2 and E300C3 cores.  */
++static const
++struct processor_costs ppce300c2c3_cost = {
++  COSTS_N_INSNS (4),    /* mulsi */
++  COSTS_N_INSNS (4),    /* mulsi_const */
++  COSTS_N_INSNS (4),    /* mulsi_const9 */
++  COSTS_N_INSNS (4),    /* muldi */
++  COSTS_N_INSNS (19),   /* divsi */
++  COSTS_N_INSNS (19),   /* divdi */
++  COSTS_N_INSNS (3),    /* fp */
++  COSTS_N_INSNS (4),    /* dmul */
++  COSTS_N_INSNS (18),   /* sdiv */
++  COSTS_N_INSNS (33),   /* ddiv */
++};
++
+ /* Instruction costs on POWER4 and POWER5 processors.  */
+ static const
+ struct processor_costs power4_cost = {
+@@ -1420,6 +1435,8 @@ rs6000_override_options (const char *def
+ 	 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
+ 	 /* 8548 has a dummy entry for now.  */
+ 	 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
++	 {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
++	 {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
+ 	 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
+ 	 {"970", PROCESSOR_POWER4,
+ 	  POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
+@@ -1845,6 +1862,11 @@ rs6000_override_options (const char *def
+ 	rs6000_cost = &ppc8540_cost;
+ 	break;
+ 
++      case PROCESSOR_PPCE300C2:
++      case PROCESSOR_PPCE300C3:
++	rs6000_cost = &ppce300c2c3_cost;
++	break;
++
+       case PROCESSOR_POWER4:
+       case PROCESSOR_POWER5:
+ 	rs6000_cost = &power4_cost;
+@@ -18606,6 +18628,8 @@ rs6000_issue_rate (void)
+   case CPU_PPC7400:
+   case CPU_PPC8540:
+   case CPU_CELL:
++  case CPU_PPCE300C2:
++  case CPU_PPCE300C3:
+     return 2;
+   case CPU_RIOS2:
+   case CPU_PPC604:
+Index: gcc-4.3.1/gcc/config/rs6000/rs6000.h
+===================================================================
+--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.h	2008-01-26 09:18:35.000000000 -0800
++++ gcc-4.3.1/gcc/config/rs6000/rs6000.h	2008-08-23 16:55:30.000000000 -0700
+@@ -117,6 +117,8 @@
+ %{mcpu=G5: -mpower4 -maltivec} \
+ %{mcpu=8540: -me500} \
+ %{mcpu=8548: -me500} \
++%{mcpu=e300c2: -mppc} \
++%{mcpu=e300c3: -mppc -mpmr} \
+ %{maltivec: -maltivec} \
+ -many"
+ 
+@@ -262,6 +264,8 @@ enum processor_type
+    PROCESSOR_PPC7400,
+    PROCESSOR_PPC7450,
+    PROCESSOR_PPC8540,
++   PROCESSOR_PPCE300C2,
++   PROCESSOR_PPCE300C3,
+    PROCESSOR_POWER4,
+    PROCESSOR_POWER5,
+    PROCESSOR_POWER6,
+Index: gcc-4.3.1/gcc/config/rs6000/rs6000.md
+===================================================================
+--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.md	2008-02-13 16:14:45.000000000 -0800
++++ gcc-4.3.1/gcc/config/rs6000/rs6000.md	2008-08-23 16:57:29.000000000 -0700
+@@ -133,7 +133,7 @@
+ ;; Processor type -- this attribute must exactly match the processor_type
+ ;; enumeration in rs6000.h.
+ 
+-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
++(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell,ppce300c2,ppce300c3"
+   (const (symbol_ref "rs6000_cpu_attr")))
+ 
+ 
+@@ -166,6 +166,7 @@
+ (include "7xx.md")
+ (include "7450.md")
+ (include "8540.md")
++(include "e300c2c3.md")
+ (include "power4.md")
+ (include "power5.md")
+ (include "power6.md")
+Index: gcc-4.3.1/gcc/config.gcc
+===================================================================
+--- gcc-4.3.1.orig/gcc/config.gcc	2008-08-23 16:49:43.000000000 -0700
++++ gcc-4.3.1/gcc/config.gcc	2008-08-23 17:03:55.000000000 -0700
+@@ -3144,7 +3144,7 @@ case "${target}" in
+ 			| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
+ 			| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
+ 			| 601 | 602 | 603 | 603e | ec603e | 604 \
+-			| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
++			| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
+ 			| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
+ 				# OK
+ 				;;
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
new file mode 100644
index 0000000000..f33e6c1ea6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
@@ -0,0 +1,31 @@
+---
+ configure    |    2 +-
+ configure.ac |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: gcc-4.3.1/configure.ac
+===================================================================
+--- gcc-4.3.1.orig/configure.ac	2008-07-21 12:29:18.000000000 -0700
++++ gcc-4.3.1/configure.ac	2008-07-21 12:29:35.000000000 -0700
+@@ -2352,7 +2352,7 @@ fi
+ # for target_alias and gcc doesn't manage it consistently.
+ target_configargs="--cache-file=./config.cache ${target_configargs}"
+ 
+-FLAGS_FOR_TARGET=
++FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
+ case " $target_configdirs " in
+  *" newlib "*)
+   case " $target_configargs " in
+Index: gcc-4.3.1/configure
+===================================================================
+--- gcc-4.3.1.orig/configure	2008-07-21 12:29:48.000000000 -0700
++++ gcc-4.3.1/configure	2008-07-21 12:29:59.000000000 -0700
+@@ -5841,7 +5841,7 @@ fi
+ # for target_alias and gcc doesn't manage it consistently.
+ target_configargs="--cache-file=./config.cache ${target_configargs}"
+ 
+-FLAGS_FOR_TARGET=
++FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
+ case " $target_configdirs " in
+  *" newlib "*)
+   case " $target_configargs " in
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2 b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2
new file mode 100644
index 0000000000..d37a2c0329
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch
new file mode 100644
index 0000000000..d5a31d19d8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch
@@ -0,0 +1,103 @@
+Date: Mon, 22 Nov 2010 13:28:54 +0000
+From: Julian Brown <julian at codesourcery dot com>
+To: gcc-patches at gcc dot gnu dot org
+Cc: DJ Delorie <dj at redhat dot com>
+Subject: [PATCH] Volatile bitfields vs. inline asm memory constraints
+Message-ID: <20101122132854.0aca431a@rex.config>
+Mime-Version: 1.0
+Content-Type: multipart/mixed; boundary="MP_/ONpW806RnQ1ziaYj7_Y5E27"
+X-IsSubscribed: yes
+Mailing-List: contact gcc-patches-help at gcc dot gnu dot org; run by ezmlm
+Precedence: bulk
+List-Id: <gcc-patches.gcc.gnu.org>
+List-Archive: <http://gcc.gnu.org/ml/gcc-patches/>
+List-Post: <mailto:gcc-patches at gcc dot gnu dot org>
+List-Help: <mailto:gcc-patches-help at gcc dot gnu dot org>
+Sender: gcc-patches-owner at gcc dot gnu dot org
+Delivered-To: mailing list gcc-patches at gcc dot gnu dot org
+
+
+
+Hi,
+
+This patch fixes the issue in the (Launchpad, not GCC) bug tracker:
+
+https://bugs.launchpad.net/gcc-linaro/+bug/675347
+
+The problem was introduced by the patch from DJ to honour volatile
+bitfield types:
+
+http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01167.html
+
+but not exposed (on ARM) until the option was made the default (on the
+Linaro branch) -- it's not yet the default on mainline.
+
+The issue is as follows: after DJ's patch and with
+-fstrict-volatile-bitfields, in expr.c:expand_expr_real_1, the if
+condition with the comment "In cases where an aligned union has an
+unaligned object as a field, we might be extracting a BLKmode value
+from an integer-mode (e.g., SImode) object [...]" triggers for a normal
+(non-bitfield) volatile field of a struct/class.
+
+But, this appears to be over-eager: in the particular case mentioned
+above, when expanding a "volatile int" struct field used as a memory
+constraint for an inline asm, we end up with something which is no
+longer addressable (I think because of the actions of
+extract_bit_field). So, compilation aborts.
+
+My proposed fix is to restrict the conditional by only making it execute
+for -fstrict-volatile-bitfields only for non-naturally-aligned accesses:
+this appears to work (fixes test in question, and no regressions for
+cross to ARM Linux, gcc/g++/libstdc++, with -fstrict-volatile-bitfields
+turned on), but I don't know if there will be unintended consequences.
+DJ, does it look sane to you?
+
+Incidentally the constraints in the inline asm in the Launchpad
+testcase might be slightly dubious (attempting to force (mem (reg)) by
+using both "+m" (var) and "r" (&var) constraints), but replacing
+them with e.g.:
+
+    asm volatile("0:\n"
+                 "ldrex %[newValue], %[_q_value]\n"
+                 "sub %[newValue], %[newValue], #1\n"
+                 "strex %[result], %[newValue], %[_q_value]\n"
+                 "teq %[result], #0\n"
+                 "bne 0b\n"
+                 : [newValue] "=&r" (newValue),
+                   [result] "=&r" (result)
+                 : [_q_value] "Q" (_q_value)
+                 : "cc", "memory");
+
+still leads to a warning (not an error) with trunk and
+-fstrict-volatile-bitfields:
+
+atomic-changed.cc:24:35: warning: use of memory input without lvalue in
+asm operand 2 is deprecated [enabled by default]
+
+The warning goes away with the attached patch. So, I don't think the
+problem is purely that the original inline asm is invalid.
+
+OK to apply, or any comments?
+
+Julian
+
+ChangeLog
+
+    gcc/
+    * expr.c (expand_expr_real_1): Only use BLKmode for volatile
+    accesses which are not naturally aligned.
+
+Index: gcc-4_5-branch/gcc/expr.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expr.c	2010-12-23 00:42:11.690101002 -0800
++++ gcc-4_5-branch/gcc/expr.c	2010-12-24 15:07:39.400101000 -0800
+@@ -9029,7 +9029,8 @@
+ 		&& modifier != EXPAND_INITIALIZER)
+ 	    /* If the field is volatile, we always want an aligned
+ 	       access.  */
+-	    || (volatilep && flag_strict_volatile_bitfields > 0)
++	    || (volatilep && flag_strict_volatile_bitfields > 0
++		&& (bitpos % GET_MODE_ALIGNMENT (mode) != 0))
+ 	    /* If the field isn't aligned enough to fetch as a memref,
+ 	       fetch it as a bit field.  */
+ 	    || (mode1 != BLKmode
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch
new file mode 100644
index 0000000000..5d1a033a9b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch
@@ -0,0 +1,29 @@
+The LINK_SPEC for linux gets overwritten by linux-eabi.h which
+means the value of TARGET_FIX_V4BX_SPEC gets lost and as a result
+the option is not passed to linker when chosing march=armv4
+This patch redefines this in linux-eabi.h and reinserts it
+for eabi defaulting toolchains.
+
+We might want to send it upstream
+
+-Khem
+Index: gcc-4.5/gcc/config/arm/linux-eabi.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/linux-eabi.h
++++ gcc-4.5/gcc/config/arm/linux-eabi.h
+@@ -63,10 +63,14 @@
+ #undef  GLIBC_DYNAMIC_LINKER
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3"
+ 
++/* For armv4 we pass --fix-v4bx to linker to support EABI */
++#undef TARGET_FIX_V4BX_SPEC
++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to
+    use the GNU/Linux version, not the generic BPABI version.  */
+ #undef  LINK_SPEC
+-#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC
++#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC
+ 
+ /* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+    do not use -lfloat.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch
new file mode 100644
index 0000000000..51892855af
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch
@@ -0,0 +1,178 @@
+Index: gcc-4.5/Makefile.def
+===================================================================
+--- gcc-4.5.orig/Makefile.def
++++ gcc-4.5/Makefile.def
+@@ -240,6 +240,7 @@ flags_to_pass = { flag= AWK ; };
+ flags_to_pass = { flag= BISON ; };
+ flags_to_pass = { flag= CC_FOR_BUILD ; };
+ flags_to_pass = { flag= CFLAGS_FOR_BUILD ; };
++flags_to_pass = { flag= CPPFLAGS_FOR_BUILD ; };
+ flags_to_pass = { flag= CXX_FOR_BUILD ; };
+ flags_to_pass = { flag= EXPECT ; };
+ flags_to_pass = { flag= FLEX ; };
+Index: gcc-4.5/gcc/Makefile.in
+===================================================================
+--- gcc-4.5.orig/gcc/Makefile.in
++++ gcc-4.5/gcc/Makefile.in
+@@ -766,7 +766,7 @@ BUILD_LINKERFLAGS = $(BUILD_CFLAGS)
+ 
+ # Native linker and preprocessor flags.  For x-fragment overrides.
+ BUILD_LDFLAGS=@BUILD_LDFLAGS@
+-BUILD_CPPFLAGS=$(ALL_CPPFLAGS)
++BUILD_CPPFLAGS=$(INCLUDES) @BUILD_CPPFLAGS@ $(X_CPPFLAGS)
+ 
+ # Actual name to use when installing a native compiler.
+ GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')
+Index: gcc-4.5/gcc/configure.ac
+===================================================================
+--- gcc-4.5.orig/gcc/configure.ac
++++ gcc-4.5/gcc/configure.ac
+@@ -1798,16 +1798,18 @@ AC_SUBST(inhibit_libc)
+ # Also, we cannot run fixincludes.
+ 
+ # These are the normal (build=host) settings:
+-CC_FOR_BUILD='$(CC)'		AC_SUBST(CC_FOR_BUILD)
+-BUILD_CFLAGS='$(ALL_CFLAGS)'	AC_SUBST(BUILD_CFLAGS)
+-BUILD_LDFLAGS='$(LDFLAGS)'	AC_SUBST(BUILD_LDFLAGS)
+-STMP_FIXINC=stmp-fixinc		AC_SUBST(STMP_FIXINC)
++CC_FOR_BUILD='$(CC)'			AC_SUBST(CC_FOR_BUILD)
++BUILD_CFLAGS='$(ALL_CFLAGS)'		AC_SUBST(BUILD_CFLAGS)
++BUILD_LDFLAGS='$(LDFLAGS)'		AC_SUBST(BUILD_LDFLAGS)
++BUILD_CPPFLAGS='$(ALL_CPPFLAGS)'	AC_SUBST(BUILD_CPPFLAGS)
++STMP_FIXINC=stmp-fixinc			AC_SUBST(STMP_FIXINC)
+ 
+ # And these apply if build != host, or we are generating coverage data
+ if test x$build != x$host || test "x$coverage_flags" != x
+ then
+     BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
+     BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
++    BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)'
+ fi
+ 
+ # Expand extra_headers to include complete path.
+Index: gcc-4.5/Makefile.in
+===================================================================
+--- gcc-4.5.orig/Makefile.in
++++ gcc-4.5/Makefile.in
+@@ -333,6 +333,7 @@ AR_FOR_BUILD = @AR_FOR_BUILD@
+ AS_FOR_BUILD = @AS_FOR_BUILD@
+ CC_FOR_BUILD = @CC_FOR_BUILD@
+ CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
++CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
+ CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
+ CXX_FOR_BUILD = @CXX_FOR_BUILD@
+ DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
+@@ -662,6 +663,7 @@ BASE_FLAGS_TO_PASS = \
+ 	"BISON=$(BISON)" \
+ 	"CC_FOR_BUILD=$(CC_FOR_BUILD)" \
+ 	"CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \
++	"CPPFLAGS_FOR_BUILD=$(CPPFLAGS_FOR_BUILD)" \
+ 	"CXX_FOR_BUILD=$(CXX_FOR_BUILD)" \
+ 	"EXPECT=$(EXPECT)" \
+ 	"FLEX=$(FLEX)" \
+Index: gcc-4.5/gcc/configure
+===================================================================
+--- gcc-4.5.orig/gcc/configure
++++ gcc-4.5/gcc/configure
+@@ -707,6 +707,7 @@ SED
+ LIBTOOL
+ collect2
+ STMP_FIXINC
++BUILD_CPPFLAGS
+ BUILD_LDFLAGS
+ BUILD_CFLAGS
+ CC_FOR_BUILD
+@@ -10982,6 +10983,7 @@ fi
+ CC_FOR_BUILD='$(CC)'
+ BUILD_CFLAGS='$(ALL_CFLAGS)'
+ BUILD_LDFLAGS='$(LDFLAGS)'
++BUILD_CPPFLAGS='$(ALL_CPPFLAGS)'
+ STMP_FIXINC=stmp-fixinc
+ 
+ # And these apply if build != host, or we are generating coverage data
+@@ -10989,6 +10991,7 @@ if test x$build != x$host || test "x$cov
+ then
+     BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
+     BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
++    BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)'
+ fi
+ 
+ # Expand extra_headers to include complete path.
+@@ -17108,7 +17111,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 17111 "configure"
++#line 17114 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -17214,7 +17217,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 17217 "configure"
++#line 17220 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+Index: gcc-4.5/Makefile.tpl
+===================================================================
+--- gcc-4.5.orig/Makefile.tpl
++++ gcc-4.5/Makefile.tpl
+@@ -336,6 +336,7 @@ AR_FOR_BUILD = @AR_FOR_BUILD@
+ AS_FOR_BUILD = @AS_FOR_BUILD@
+ CC_FOR_BUILD = @CC_FOR_BUILD@
+ CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
++CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
+ CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
+ CXX_FOR_BUILD = @CXX_FOR_BUILD@
+ DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
+Index: gcc-4.5/configure
+===================================================================
+--- gcc-4.5.orig/configure
++++ gcc-4.5/configure
+@@ -651,6 +651,7 @@ GCJ_FOR_BUILD
+ DLLTOOL_FOR_BUILD
+ CXX_FOR_BUILD
+ CXXFLAGS_FOR_BUILD
++CPPFLAGS_FOR_BUILD
+ CFLAGS_FOR_BUILD
+ CC_FOR_BUILD
+ AS_FOR_BUILD
+@@ -8036,6 +8037,7 @@ esac
+ # our build compiler if desired.
+ if test x"${build}" = x"${host}" ; then
+   CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}}
++  CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}}
+   CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}}
+   LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}}
+ fi
+@@ -8101,6 +8103,7 @@ done
+ 
+ 
+ 
++
+ 
+ 
+ 
+Index: gcc-4.5/configure.ac
+===================================================================
+--- gcc-4.5.orig/configure.ac
++++ gcc-4.5/configure.ac
+@@ -3089,6 +3089,7 @@ esac
+ # our build compiler if desired.
+ if test x"${build}" = x"${host}" ; then
+   CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}}
++  CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}}
+   CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}}
+   LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}}
+ fi
+@@ -3155,6 +3156,7 @@ AC_SUBST(AR_FOR_BUILD)
+ AC_SUBST(AS_FOR_BUILD)
+ AC_SUBST(CC_FOR_BUILD)
+ AC_SUBST(CFLAGS_FOR_BUILD)
++AC_SUBST(CPPFLAGS_FOR_BUILD)
+ AC_SUBST(CXXFLAGS_FOR_BUILD)
+ AC_SUBST(CXX_FOR_BUILD)
+ AC_SUBST(DLLTOOL_FOR_BUILD)
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch
new file mode 100644
index 0000000000..84c5ef2ebd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch
@@ -0,0 +1,331 @@
+#! /bin/sh -e
+
+# DP: Retry the build on an ice, save the calling options and preprocessed
+# DP: source when the ice is reproducible.
+
+dir=
+if [ $# -eq 3 -a "$2" = '-d' ]; then
+    pdir="-d $3"
+    dir="$3/"
+elif [ $# -ne 1 ]; then
+    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+    exit 1
+fi
+case "$1" in
+    -patch)
+        patch $pdir -f --no-backup-if-mismatch -p0 < $0
+        ;;
+    -unpatch)
+        patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
+        ;;
+    *)
+        echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+        exit 1
+esac
+exit 0
+
+2004-01-23  Jakub Jelinek  <jakub@redhat.com>
+
+	* system.h (ICE_EXIT_CODE): Define.
+	* gcc.c (execute): Don't free first string early, but at the end
+	of the function.  Call retry_ice if compiler exited with
+	ICE_EXIT_CODE.
+	(retry_ice): New function.
+	* diagnostic.c (diagnostic_count_diagnostic,
+	diagnostic_action_after_output, error_recursion): Exit with
+	ICE_EXIT_CODE instead of FATAL_EXIT_CODE.
+
+--- gcc/diagnostic.c.orig	2007-09-30 10:48:13.000000000 +0000
++++ gcc/diagnostic.c	2007-09-30 10:49:57.000000000 +0000
+@@ -244,7 +244,7 @@
+       fnotice (stderr, "Please submit a full bug report,\n"
+ 	       "with preprocessed source if appropriate.\n"
+ 	       "See %s for instructions.\n", bug_report_url);
+-      exit (ICE_EXIT_CODE);
++      exit (FATAL_EXIT_CODE);
+ 
+     case DK_FATAL:
+       if (context->abort_on_error)
+--- gcc/gcc.c.orig	2007-09-30 10:48:13.000000000 +0000
++++ gcc/gcc.c	2007-09-30 10:48:39.000000000 +0000
+@@ -357,6 +357,9 @@
+ #if defined(HAVE_TARGET_OBJECT_SUFFIX) || defined(HAVE_TARGET_EXECUTABLE_SUFFIX)
+ static const char *convert_filename (const char *, int, int);
+ #endif
++#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
++static void retry_ice (const char *prog, const char **argv);
++#endif
+ 
+ static const char *getenv_spec_function (int, const char **);
+ static const char *if_exists_spec_function (int, const char **);
+@@ -2999,7 +3002,7 @@
+ 	    }
+ 	}
+ 
+-      if (string != commands[i].prog)
++      if (i && string != commands[i].prog)
+ 	free (CONST_CAST (char *, string));
+     }
+ 
+@@ -3056,6 +3059,16 @@
+ 	else if (WIFEXITED (status)
+ 		 && WEXITSTATUS (status) >= MIN_FATAL_STATUS)
+ 	  {
++#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
++	    /* For ICEs in cc1, cc1obj, cc1plus see if it is
++	       reproducible or not.  */
++	    char *p;
++	    if (WEXITSTATUS (status) == ICE_EXIT_CODE
++		&& i == 0
++		&& (p = strrchr (commands[0].argv[0], DIR_SEPARATOR))
++		&& ! strncmp (p + 1, "cc1", 3))
++	      retry_ice (commands[0].prog, commands[0].argv);
++#endif
+ 	    if (WEXITSTATUS (status) > greatest_status)
+ 	      greatest_status = WEXITSTATUS (status);
+ 	    ret_code = -1;
+@@ -3076,6 +3089,9 @@
+ 	  }
+       }
+ 
++    if (commands[0].argv[0] != commands[0].prog)
++      free ((PTR) commands[0].argv[0]);
++
+     return ret_code;
+   }
+ }
+@@ -6016,6 +6032,224 @@
+   switches[switchnum].validated = 1;
+ }
+ 
++#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
++#define RETRY_ICE_ATTEMPTS 2
++
++static void
++retry_ice (const char *prog, const char **argv)
++{
++  int nargs, out_arg = -1, quiet = 0, attempt;
++  int pid, retries, sleep_interval;
++  const char **new_argv;
++  char *temp_filenames[RETRY_ICE_ATTEMPTS * 2 + 2];
++
++  if (input_filename == NULL || ! strcmp (input_filename, "-"))
++    return;
++
++  for (nargs = 0; argv[nargs] != NULL; ++nargs)
++    /* Only retry compiler ICEs, not preprocessor ones.  */
++    if (! strcmp (argv[nargs], "-E"))
++      return;
++    else if (argv[nargs][0] == '-' && argv[nargs][1] == 'o')
++      {
++	if (out_arg == -1)
++	  out_arg = nargs;
++	else
++	  return;
++      }
++    /* If the compiler is going to output any time information,
++       it might vary between invocations.  */
++    else if (! strcmp (argv[nargs], "-quiet"))
++      quiet = 1;
++    else if (! strcmp (argv[nargs], "-ftime-report"))
++      return;
++
++  if (out_arg == -1 || !quiet)
++    return;
++
++  memset (temp_filenames, '\0', sizeof (temp_filenames));
++  new_argv = alloca ((nargs + 3) * sizeof (const char *));
++  memcpy (new_argv, argv, (nargs + 1) * sizeof (const char *));
++  new_argv[nargs++] = "-frandom-seed=0";
++  new_argv[nargs] = NULL;
++  if (new_argv[out_arg][2] == '\0')
++    new_argv[out_arg + 1] = "-";
++  else
++    new_argv[out_arg] = "-o-";
++
++  for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS + 1; ++attempt)
++    {
++      int fd = -1;
++      int status;
++
++      temp_filenames[attempt * 2] = make_temp_file (".out");
++      temp_filenames[attempt * 2 + 1] = make_temp_file (".err");
++
++      if (attempt == RETRY_ICE_ATTEMPTS)
++        {
++	  int i;
++	  int fd1, fd2;
++	  struct stat st1, st2;
++	  size_t n, len;
++	  char *buf;
++
++	  buf = xmalloc (8192);
++
++	  for (i = 0; i < 2; ++i)
++	    {
++	      fd1 = open (temp_filenames[i], O_RDONLY);
++	      fd2 = open (temp_filenames[2 + i], O_RDONLY);
++
++	      if (fd1 < 0 || fd2 < 0)
++		{
++		  i = -1;
++		  close (fd1);
++		  close (fd2);
++		  break;
++		}
++
++	      if (fstat (fd1, &st1) < 0 || fstat (fd2, &st2) < 0)
++		{
++		  i = -1;
++		  close (fd1);
++		  close (fd2);
++		  break;
++		}
++
++	      if (st1.st_size != st2.st_size)
++		{
++		  close (fd1);
++		  close (fd2);
++		  break;
++		}
++
++	      len = 0;
++	      for (n = st1.st_size; n; n -= len)
++		{
++		  len = n;
++		  if (len > 4096)
++		    len = 4096;
++
++		  if (read (fd1, buf, len) != (int) len
++		      || read (fd2, buf + 4096, len) != (int) len)
++		    {
++		      i = -1;
++		      break;
++		    }
++
++		  if (memcmp (buf, buf + 4096, len) != 0)
++		    break;
++		}
++
++	      close (fd1);
++	      close (fd2);
++
++	      if (n)
++		break;
++	    }
++
++	  free (buf);
++	  if (i == -1)
++	    break;
++
++	  if (i != 2)
++	    {
++	      notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n");
++	      break;
++	    }
++
++          fd = open (temp_filenames[attempt * 2], O_RDWR);
++	  if (fd < 0)
++	    break;
++	  write (fd, "//", 2);
++	  for (i = 0; i < nargs; i++)
++	    {
++	      write (fd, " ", 1);
++	      write (fd, new_argv[i], strlen (new_argv[i]));
++	    }
++	  write (fd, "\n", 1);
++	  new_argv[nargs] = "-E";
++	  new_argv[nargs + 1] = NULL;
++        }
++
++      /* Fork a subprocess; wait and retry if it fails.  */
++      sleep_interval = 1;
++      pid = -1;
++      for (retries = 0; retries < 4; retries++)
++	{
++	  pid = fork ();
++	  if (pid >= 0)
++	    break;
++	  sleep (sleep_interval);
++	  sleep_interval *= 2;
++	}
++
++      if (pid < 0)
++	break;
++      else if (pid == 0)
++	{
++	  if (attempt != RETRY_ICE_ATTEMPTS)
++	    fd = open (temp_filenames[attempt * 2], O_RDWR);
++	  if (fd < 0)
++	    exit (-1);
++	  if (fd != 1)
++	    {
++	      close (1);
++	      dup (fd);
++	      close (fd);
++	    }
++
++	  fd = open (temp_filenames[attempt * 2 + 1], O_RDWR);
++	  if (fd < 0)
++	    exit (-1);
++	  if (fd != 2)
++	    {
++	      close (2);
++	      dup (fd);
++	      close (fd);
++	    }
++
++	  if (prog == new_argv[0])
++	    execvp (prog, (char *const *) new_argv);
++	  else
++	    execv (new_argv[0], (char *const *) new_argv);
++	  exit (-1);
++	}
++
++      if (waitpid (pid, &status, 0) < 0)
++	break;
++
++      if (attempt < RETRY_ICE_ATTEMPTS
++	  && (! WIFEXITED (status) || WEXITSTATUS (status) != ICE_EXIT_CODE))
++	{
++	  notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n");
++	  break;
++	}
++      else if (attempt == RETRY_ICE_ATTEMPTS)
++	{
++	  close (fd);
++	  if (WIFEXITED (status)
++	      && WEXITSTATUS (status) == SUCCESS_EXIT_CODE)
++	    {
++	      notice ("Preprocessed source stored into %s file, please attach this to your bugreport.\n",
++		      temp_filenames[attempt * 2]);
++	      /* Make sure it is not deleted.  */
++	      free (temp_filenames[attempt * 2]);
++	      temp_filenames[attempt * 2] = NULL;
++	      break;
++	    }
++	}
++    }
++
++  for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS * 2 + 2; attempt++)
++    if (temp_filenames[attempt])
++      {
++	unlink (temp_filenames[attempt]);
++	free (temp_filenames[attempt]);
++      }
++}
++#endif
++
+ /* Search for a file named NAME trying various prefixes including the
+    user's -B prefix and some standard ones.
+    Return the absolute file name found.  If nothing is found, return NAME.  */
+--- gcc/Makefile.in.orig	2007-09-30 10:48:13.000000000 +0000
++++ gcc/Makefile.in	2007-09-30 10:48:39.000000000 +0000
+@@ -192,6 +192,7 @@
+ build/gengtype-lex.o-warn = -Wno-error
+ # SYSCALLS.c misses prototypes
+ SYSCALLS.c.X-warn = -Wno-strict-prototypes -Wno-error
++build/gcc.o-warn = -Wno-error
+ 
+ # All warnings have to be shut off in stage1 if the compiler used then
+ # isn't gcc; configure determines that.  WARN_CFLAGS will be either
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch
new file mode 100644
index 0000000000..862b102133
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch
@@ -0,0 +1,25 @@
+Add /sw/include and /opt/include based on the original
+zecke-no-host-includes.patch patch.  The original patch checked for
+/usr/include, /sw/include and /opt/include and then triggered a failure and
+aborted.
+
+Instead, we add the two missing items to the current scan.  If the user
+wants this to be a failure, they can add "-Werror=poison-system-directories".
+
+Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
+
+Index: gcc-4_5-branch/gcc/incpath.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/incpath.c
++++ gcc-4_5-branch/gcc/incpath.c
+@@ -365,7 +365,9 @@ merge_include_chains (const char *sysroo
+ 	  {
+ 	   if ((!strncmp (p->name, "/usr/include", 12))
+ 	       || (!strncmp (p->name, "/usr/local/include", 18))
+-	       || (!strncmp (p->name, "/usr/X11R6/include", 18)))
++	       || (!strncmp (p->name, "/usr/X11R6/include", 18))
++	       || (!strncmp (p->name, "/sw/include", 11))
++	       || (!strncmp (p->name, "/opt/include", 12)))
+ 	     warning (OPT_Wpoison_system_directories,
+ 		      "include location \"%s\" is unsafe for "
+ 		      "cross-compilation",
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch
new file mode 100644
index 0000000000..ba20e8b15e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch
@@ -0,0 +1,83 @@
+gcc: add poison parameters detection
+
+Add the logic that, if not configured with "--enable-target-optspace",
+gcc will meet error when build target app with "-Os" option.
+This could avoid potential binary crash.
+
+Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
+
+Index: gcc-4_5-branch/gcc/config.in
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config.in
++++ gcc-4_5-branch/gcc/config.in
+@@ -138,6 +138,12 @@
+ #endif
+ 
+ 
++/* Define to enable target optspace support. */
++#ifndef USED_FOR_TARGET
++#undef ENABLE_TARGET_OPTSPACE
++#endif
++
++
+ /* Define if you want all operations on RTL (the basic data structure of the
+    optimizer and back end) to be checked for dynamic type safety at runtime.
+    This is quite expensive. */
+Index: gcc-4_5-branch/gcc/configure
+===================================================================
+--- gcc-4_5-branch.orig/gcc/configure
++++ gcc-4_5-branch/gcc/configure
+@@ -915,6 +915,7 @@ enable_version_specific_runtime_libs
+ with_slibdir
+ enable_poison_system_directories
+ enable_plugin
++enable_target_optspace
+ '
+       ac_precious_vars='build_alias
+ host_alias
+@@ -25658,6 +25659,13 @@ $as_echo "#define ENABLE_PLUGIN 1" >>con
+ 
+ fi
+ 
++if test x"$enable_target_optspace" != x; then :
++
++$as_echo "#define ENABLE_TARGET_OPTSPACE 1" >>confdefs.h
++
++fi
++
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 
+Index: gcc-4_5-branch/gcc/configure.ac
+===================================================================
+--- gcc-4_5-branch.orig/gcc/configure.ac
++++ gcc-4_5-branch/gcc/configure.ac
+@@ -4659,6 +4659,11 @@ if test x"$enable_plugin" = x"yes"; then
+   AC_DEFINE(ENABLE_PLUGIN, 1, [Define to enable plugin support.])
+ fi
+ 
++AC_SUBST(enable_target_optspace)
++if test x"$enable_target_optspace" != x; then
++  AC_DEFINE(ENABLE_TARGET_OPTSPACE, 1, [Define to enable target optspace support.])
++fi
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 
+Index: gcc-4_5-branch/gcc/opts.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/opts.c
++++ gcc-4_5-branch/gcc/opts.c
+@@ -953,6 +953,11 @@ decode_options (unsigned int argc, const
+   else
+     set_param_value ("min-crossjump-insns", initial_min_crossjump_insns);
+ 
++#ifndef ENABLE_TARGET_OPTSPACE
++  if (optimize_size == 1)
++    error ("Do not use -Os option if --enable-target-optspace is not set.");
++#endif
++
+   if (first_time_p)
+     {
+       /* Initialize whether `char' is signed.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch
new file mode 100644
index 0000000000..04043ff0b7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch
@@ -0,0 +1,201 @@
+       gcc/
+       2008-07-02  Joseph Myers  <joseph@codesourcery.com>
+       * c-incpath.c: Include toplev.h.
+       (merge_include_chains): Use warning instead of cpp_error for
+       system directory poisoning diagnostic.
+       * Makefile.in (c-incpath.o): Depend on toplev.h.
+       * gcc.c (LINK_COMMAND_SPEC): Pass
+       --error-poison-system-directories if
+       -Werror=poison-system-directories.
+
+       2007-06-13  Joseph Myers  <joseph@codesourcery.com>
+       * common.opt (--Wno-poison-system-directories): New.
+       * doc/invoke.texi (-Wno-poison-system-directories): Document.
+       * c-incpath.c: Include flags.h.
+       (merge_include_chains): Check flag_poison_system_directories.
+       * gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories
+       to linker if -Wno-poison-system-directories.
+       * Makefile.in (c-incpath.o): Depend on $(FLAGS_H).
+
+       2007-03-20  Daniel Jacobowitz  <dan@codesourcery.com>
+                   Joseph Myers  <joseph@codesourcery.com>
+       * configure.ac (--enable-poison-system-directories): New option.
+       * configure, config.in: Regenerate.
+       * c-incpath.c (merge_include_chains): If
+       ENABLE_POISON_SYSTEM_DIRECTORIES defined, warn for use of
+       /usr/include, /usr/local/include or /usr/X11R6/include.
+
+Index: gcc-4.5.0/gcc/common.opt
+===================================================================
+--- gcc-4.5.0.orig/gcc/common.opt	2010-03-17 20:01:09.000000000 -0700
++++ gcc-4.5.0/gcc/common.opt	2010-06-25 11:35:39.965383734 -0700
+@@ -152,6 +152,10 @@
+ Common Var(warn_padded) Warning
+ Warn when padding is required to align structure members
+ 
++Wpoison-system-directories
++Common Var(flag_poison_system_directories) Init(1) Warning
++Warn for -I and -L options using system directories if cross compiling
++
+ Wshadow
+ Common Var(warn_shadow) Warning
+ Warn when one local variable shadows another
+Index: gcc-4.5.0/gcc/config.in
+===================================================================
+--- gcc-4.5.0.orig/gcc/config.in	2010-04-14 02:30:07.000000000 -0700
++++ gcc-4.5.0/gcc/config.in	2010-06-25 11:35:39.969383588 -0700
+@@ -132,6 +132,12 @@
+ #endif
+ 
+ 
++/* Define to warn for use of native system header directories */
++#ifndef USED_FOR_TARGET
++#undef ENABLE_POISON_SYSTEM_DIRECTORIES
++#endif
++
++
+ /* Define if you want all operations on RTL (the basic data structure of the
+    optimizer and back end) to be checked for dynamic type safety at runtime.
+    This is quite expensive. */
+Index: gcc-4.5.0/gcc/configure.ac
+===================================================================
+--- gcc-4.5.0.orig/gcc/configure.ac	2010-06-25 11:34:01.433382161 -0700
++++ gcc-4.5.0/gcc/configure.ac	2010-06-25 11:35:39.969383588 -0700
+@@ -4276,6 +4276,16 @@
+ fi)
+ AC_SUBST(slibdir)
+ 
++AC_ARG_ENABLE([poison-system-directories],
++             AS_HELP_STRING([--enable-poison-system-directories],
++                            [warn for use of native system header directories]),,
++             [enable_poison_system_directories=no])
++if test "x${enable_poison_system_directories}" = "xyes"; then
++  AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES],
++           [1],
++           [Define to warn for use of native system header directories])
++fi
++
+ # Substitute configuration variables
+ AC_SUBST(subdirs)
+ AC_SUBST(srcdir)
+Index: gcc-4.5.0/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4.5.0.orig/gcc/doc/invoke.texi	2010-04-06 07:02:22.000000000 -0700
++++ gcc-4.5.0/gcc/doc/invoke.texi	2010-06-25 11:35:39.992666345 -0700
+@@ -252,6 +252,7 @@
+ -Woverlength-strings  -Wpacked  -Wpacked-bitfield-compat  -Wpadded @gol
+ -Wparentheses  -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
+ -Wpointer-arith  -Wno-pointer-to-int-cast @gol
++-Wno-poison-system-directories @gol
+ -Wredundant-decls @gol
+ -Wreturn-type  -Wsequence-point  -Wshadow @gol
+ -Wsign-compare  -Wsign-conversion  -Wstack-protector @gol
+@@ -3603,6 +3604,14 @@
+ option will @emph{not} warn about unknown pragmas in system
+ headers---for that, @option{-Wunknown-pragmas} must also be used.
+ 
++@item -Wno-poison-system-directories
++@opindex Wno-poison-system-directories
++Do not warn for @option{-I} or @option{-L} options using system
++directories such as @file{/usr/include} when cross compiling.  This
++option is intended for use in chroot environments when such
++directories contain the correct headers and libraries for the target
++system rather than the host.
++
+ @item -Wfloat-equal
+ @opindex Wfloat-equal
+ @opindex Wno-float-equal
+Index: gcc-4.5.0/gcc/gcc.c
+===================================================================
+--- gcc-4.5.0.orig/gcc/gcc.c	2010-02-11 04:23:08.000000000 -0800
++++ gcc-4.5.0/gcc/gcc.c	2010-06-25 11:35:40.009381858 -0700
+@@ -792,6 +792,8 @@
+     %{flto} %{fwhopr} %l " LINK_PIE_SPEC \
+    "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
+     %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
++    %{Wno-poison-system-directories:--no-poison-system-directories}\
++    %{Werror=poison-system-directories:--error-poison-system-directories}\
+     %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
+     %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\
+     %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\
+Index: gcc-4.5.0/gcc/incpath.c
+===================================================================
+--- gcc-4.5.0.orig/gcc/incpath.c	2009-11-25 02:55:54.000000000 -0800
++++ gcc-4.5.0/gcc/incpath.c	2010-06-25 11:35:40.017209818 -0700
+@@ -353,6 +353,24 @@
+ 	}
+       fprintf (stderr, _("End of search list.\n"));
+     }
++
++#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES
++  if (flag_poison_system_directories)
++    {
++       struct cpp_dir *p;
++
++       for (p = heads[QUOTE]; p; p = p->next)
++         {
++          if ((!strncmp (p->name, "/usr/include", 12))
++              || (!strncmp (p->name, "/usr/local/include", 18))
++              || (!strncmp (p->name, "/usr/X11R6/include", 18)))
++            warning (OPT_Wpoison_system_directories,
++                     "include location \"%s\" is unsafe for "
++                     "cross-compilation",
++                     p->name);
++         }
++    }
++#endif
+ }
+ 
+ /* Use given -I paths for #include "..." but not #include <...>, and
+diff -ur gcc-4.5.0.orig/gcc/Makefile.in gcc-4.5.0/gcc/Makefile.in
+--- gcc-4.5.0.orig/gcc/Makefile.in	2010-09-29 17:13:49.164088845 -0500
++++ gcc-4.5.0/gcc/Makefile.in	2010-09-29 18:48:19.300178501 -0500
+@@ -1965,7 +1965,7 @@
+ 
+ incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \
+ 		intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \
+-		$(MACHMODE_H)
++		$(MACHMODE_H) $(FLAGS_H) toplev.h
+ 
+ c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \
+     $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \
+diff -ur gcc-4.5.0.orig/gcc/configure gcc-4.5.0/gcc/configure
+--- gcc-4.5.0.orig/gcc/configure	2010-09-29 14:58:31.702054881 -0500
++++ gcc-4.5.0/gcc/configure	2010-09-29 18:46:31.486068500 -0500
+@@ -913,6 +913,7 @@
+ enable_maintainer_mode
+ enable_version_specific_runtime_libs
+ with_slibdir
++enable_poison_system_directories
+ enable_plugin
+ enable_target_optspace
+ '
+@@ -1621,6 +1622,8 @@
+   --enable-version-specific-runtime-libs
+                           specify that runtime libraries should be
+                           installed in a compiler-specific directory
++  --enable-poison-system-directories
++                          warn for use of native system header directories
+   --enable-plugin         enable plugin support
+ 
+ Optional Packages:
+@@ -25339,6 +25377,19 @@
+ 
+ 
+ 
++# Check whether --enable-poison-system-directories was given.
++if test "${enable_poison_system_directories+set}" = set; then :
++  enableval=$enable_poison_system_directories;
++else
++  enable_poison_system_directories=no
++fi
++
++if test "x${enable_poison_system_directories}" = "xyes"; then
++
++$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h
++
++fi
++
+ # Substitute configuration variables
+ 
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch
new file mode 100644
index 0000000000..6ae75a012b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch
@@ -0,0 +1,221 @@
+commit de784bee66a1ec1d0dad00d9eedbe9b1667dd883
+Author: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date:   Mon Dec 20 15:29:31 2010 +0000
+
+    	* config/rs6000/freebsd.h (SVR4_ASM_SPEC): Don't define.
+    	(DBX_REGISTER_NUMBER): Define.
+    	* config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Define.
+    	* config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Define.
+    	* config/rs6000/sysv4.h (SIZE_TYPE): Define.
+    	(ASM_SPEC): Define without using SVR4_ASM_SPEC.
+    	(DBX_REGISTER_NUMBER): Undefine.
+    	* config.gcc (powerpc-*-eabispe*, powerpc-*-eabisimaltivec*,
+    	powerpc-*-eabisim*, powerpc-*-elf*, powerpc-*-eabialtivec*,
+    	powerpc-xilinx-eabi*, powerpc-*-eabi*, powerpc-*-rtems*,
+    	powerpc-*-linux* | powerpc64-*-linux*, powerpc64-*-gnu*,
+    	powerpc-*-gnu-gnualtivec*, powerpc-*-gnu*,
+    	powerpc-wrs-vxworks|powerpc-wrs-vxworksae, powerpcle-*-elf*,
+    	powerpcle-*-eabisim*, powerpcle-*-eabi*): Don't use svr4.h.
+    
+    
+    git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168085 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Index: gcc-4_5-branch/gcc/config.gcc
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config.gcc	2011-09-17 11:11:28.000000000 -0700
++++ gcc-4_5-branch/gcc/config.gcc	2011-09-17 11:16:32.543298716 -0700
+@@ -1989,48 +1989,48 @@ powerpc-*-netbsd*)
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	;;
+ powerpc-*-eabispe*)
+-	tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
++	tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-spe rs6000/t-ppccomm"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpc-*-eabisimaltivec*)
+-	tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h"
++	tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpc-*-eabisim*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpc-*-elf*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ 	;;
+ powerpc-*-eabialtivec*)
+-	tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
++	tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpc-xilinx-eabi*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm rs6000/t-xilinx"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpc-*-eabi*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpc-*-rtems*)
+-	tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
++	tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm"
+ 	;;
+@@ -2079,12 +2079,12 @@ powerpc-*-linux* | powerpc64-*-linux*)
+ 	fi
+ 	;;
+ powerpc64-*-gnu*)
+-	tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h"
++	tm_file="${tm_file} elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt rs6000/linux64.opt"
+ 	tmake_file="t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu"
+ 	;;
+ powerpc-*-gnu-gnualtivec*)
+-	tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h"
++	tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm"
+ 	if test x$enable_threads = xyes; then
+@@ -2092,7 +2092,7 @@ powerpc-*-gnu-gnualtivec*)
+ 	fi
+ 	;;
+ powerpc-*-gnu*)
+-	tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h"
++	tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	if test x$enable_threads = xyes; then
+@@ -2100,7 +2100,7 @@ powerpc-*-gnu*)
+ 	fi
+ 	;;
+ powerpc-wrs-vxworks|powerpc-wrs-vxworksae)
+-	tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h"
++	tm_file="${tm_file} elfos.h freebsd-spec.h rs6000/sysv4.h"
+ 	tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppccomm rs6000/t-vxworks"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	extra_headers=ppc-asm.h
+@@ -2126,18 +2126,18 @@ powerpc-*-lynxos*)
+ 	gas=yes
+ 	;;
+ powerpcle-*-elf*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	;;
+ powerpcle-*-eabisim*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	use_gcc_stdint=wrap
+ 	;;
+ powerpcle-*-eabi*)
+-	tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h"
++	tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h"
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	use_gcc_stdint=wrap
+Index: gcc-4_5-branch/gcc/config/rs6000/freebsd.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/freebsd.h	2011-06-16 17:58:58.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/freebsd.h	2011-09-17 11:13:13.623298761 -0700
+@@ -69,6 +69,4 @@
+ /* Override rs6000.h definition.  */
+ #undef  ASM_APP_OFF
+ #define ASM_APP_OFF "#NO_APP\n"
+-/* Define SVR4_ASM_SPEC, we use GAS by default. See svr4.h for details.  */
+-#define SVR4_ASM_SPEC \
+-  "%{v:-V} %{Wa,*:%*}"
++#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
+Index: gcc-4_5-branch/gcc/config/rs6000/lynx.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/lynx.h	2011-06-16 17:58:58.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/lynx.h	2011-09-17 11:13:13.623298761 -0700
+@@ -1,5 +1,5 @@
+ /* Definitions for Rs6000 running LynxOS.
+-   Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007
++   Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2010
+    Free Software Foundation, Inc.
+    Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com)
+    Rewritten by Adam Nemet, LynuxWorks Inc.
+@@ -105,6 +105,8 @@
+ #undef HAVE_AS_TLS
+ #define HAVE_AS_TLS 0
+ 
++#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
++
+ #ifdef CRT_BEGIN
+ /* This function is part of crtbegin*.o which is at the beginning of
+    the link and is called from .fini which is usually toward the end
+Index: gcc-4_5-branch/gcc/config/rs6000/netbsd.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/netbsd.h	2011-06-16 17:58:58.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/netbsd.h	2011-09-17 11:13:13.623298761 -0700
+@@ -1,6 +1,6 @@
+ /* Definitions of target machine for GNU compiler,
+    for PowerPC NetBSD systems.
+-   Copyright 2002, 2003, 2007, 2008 Free Software Foundation, Inc.
++   Copyright 2002, 2003, 2007, 2008, 2010 Free Software Foundation, Inc.
+    Contributed by Wasabi Systems, Inc.
+ 
+    This file is part of GCC.
+@@ -89,3 +89,5 @@
+ 
+ #undef  TARGET_VERSION
+ #define TARGET_VERSION fprintf (stderr, " (NetBSD/powerpc ELF)");
++
++#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
+Index: gcc-4_5-branch/gcc/config/rs6000/sysv4.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/sysv4.h	2011-09-17 11:11:29.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/sysv4.h	2011-09-17 11:13:13.623298761 -0700
+@@ -293,6 +293,10 @@ do {									\
+ #define	RESTORE_FP_PREFIX "_restfpr_"
+ #define RESTORE_FP_SUFFIX ""
+ 
++/* Type used for size_t, as a string used in a declaration.  */
++#undef  SIZE_TYPE
++#define SIZE_TYPE "unsigned int"
++
+ /* Type used for ptrdiff_t, as a string used in a declaration.  */
+ #define PTRDIFF_TYPE "int"
+ 
+@@ -588,9 +592,8 @@ extern int fixuplabelno;
+ /* Override svr4.h definition.  */
+ #undef	ASM_SPEC
+ #define	ASM_SPEC "%(asm_cpu) \
+-%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \
+-SVR4_ASM_SPEC \
+-"%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \
++%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \
++%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \
+ %{memb|msdata=eabi: -memb} \
+ %{mlittle|mlittle-endian:-mlittle; \
+   mbig|mbig-endian      :-mbig;    \
+@@ -1120,3 +1123,5 @@ ncrtn.o%s"
+ 
+ /* This target uses the sysv4.opt file.  */
+ #define TARGET_USES_SYSV4_OPT 1
++
++#undef DBX_REGISTER_NUMBER
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch
new file mode 100644
index 0000000000..61c883e1ff
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch
@@ -0,0 +1,117 @@
+backport http://gcc.gnu.org/viewcvs?view=revision&revision=162404
+from trunk
+
+Which fixes http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43698
+
+2010-07-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+        PR target/43698
+        * config/arm/arm.md: Split arm_rev into *arm_rev
+        and *thumb1_rev. Set *arm_rev to be predicable.
+
+2010-07-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+        PR target/43698
+        * gcc.target/arm/pr43698.c: New test.
+
+
+/scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+Usage: date [OPTION]... [+FORMAT]
+Display the current time in the given FORMAT.
+
+  -d, --date=STRING         display time described by STRING, not `now'
+  -f, --file=DATEFILE       like --date once for each line of DATEFILE
+  -R, --rfc-822             output RFC-822 compliant date string
+  -u, --utc, --universal    print or set Coordinated Universal Time
+      --help                display this help and exit
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /bin/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /bin/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /bin/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
+date is /bin/date
+date
+Khem
+Index: gcc-4.5/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.md	2010-07-20 20:31:25.000000000 -0700
++++ gcc-4.5/gcc/config/arm/arm.md	2010-07-22 14:55:54.303169081 -0700
+@@ -11197,15 +11197,21 @@
+    (set_attr "length" "4")]
+ )
+ 
+-(define_insn "arm_rev"
++(define_insn "*arm_rev"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
+-  "TARGET_EITHER && arm_arch6"
+-  "rev\t%0, %1"
+-  [(set (attr "length")
+-        (if_then_else (eq_attr "is_thumb" "yes")
+-		      (const_int 2)
+-		      (const_int 4)))]
++  "TARGET_32BIT && arm_arch6"
++  "rev%?\t%0, %1"
++  [(set_attr "predicable" "yes")
++   (set_attr "length" "4")]
++)
++
++(define_insn "*thumb1_rev"
++  [(set (match_operand:SI 0 "s_register_operand" "=l")
++	(bswap:SI (match_operand:SI 1 "s_register_operand" "l")))]
++  "TARGET_THUMB1 && arm_arch6"
++   "rev\t%0, %1"
++  [(set_attr "length" "2")]
+ )
+ 
+ (define_expand "arm_legacy_rev"
+Index: gcc-4.5/gcc/testsuite/gcc.target/arm/pr43698.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4.5/gcc/testsuite/gcc.target/arm/pr43698.c	2010-07-22 14:56:35.406670213 -0700
+@@ -0,0 +1,39 @@
++/* { dg-do run } */
++/* { dg-options "-Os -march=armv7-a" } */
++#include <stdint.h>
++#include <stdlib.h>
++
++
++char do_reverse_endian = 0;
++
++#  define bswap_32(x) \
++  ((((x) & 0xff000000) >> 24) | \
++   (((x) & 0x00ff0000) >>  8) | \
++   (((x) & 0x0000ff00) <<  8) | \
++   (((x) & 0x000000ff) << 24))
++
++#define EGET(X) \
++  (__extension__ ({ \
++      uint64_t __res; \
++      if (!do_reverse_endian) {    __res = (X); \
++      } else if (sizeof(X) == 4) { __res = bswap_32((X)); \
++      } \
++      __res; \
++    }))
++
++void __attribute__((noinline)) X(char **phdr, char **data, int *phoff)
++{
++  *phdr = *data + EGET(*phoff);
++}
++
++int main()
++{
++  char *phdr;
++  char *data = (char *)0x40164000;
++  int phoff = 0x34;
++  X(&phdr, &data, &phoff);
++  if (phdr != (char *)0x40164034)
++    abort ();
++  exit (0);
++}
++
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch
new file mode 100644
index 0000000000..cbe12303e8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch
@@ -0,0 +1,63 @@
+Hi,
+
+The attached patch fixes Bugzilla 45847
+(http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45847). When compiling
+without -mvectorize-with-neon-quad and vectorizing scalar widening
+operations that widen words to double words, there are no corresponding
+vector types for DI scalar types. For this scenario, a call to
+get_vect_type_for_scalar_type() returns NULL and an absent NULL-check
+caused this segfault. The attached patch adds this NULL-check. Also,
+this is consistent with all the other places where a NULL-check follows
+a call to get_vect_type_for_scalar_type() in tree-vect-patterns.c. 
+
+Regression tested with arm-linux-gnueabi. OK?
+
+--
+Tejas Belagod
+ARM.
+
+gcc/
+
+2010-10-05  Tejas Belagod  <tejas.belagod@arm.com>
+
+	* tree-vect-patterns.c (vect_recog_widen_mult_pattern): Add NULL
+	check for vectype_out returned by get_vectype_for_scalar_type().
+
+testsuite/
+
+2010-10-05  Tejas Belagod  <tejas.belagod@arm.com>
+
+	* gcc.dg/vect/pr45847.c: New test.
+
+Index: gcc-4.5/gcc/testsuite/gcc.dg/vect/pr45847.c
+===================================================================
+--- /dev/null
++++ gcc-4.5/gcc/testsuite/gcc.dg/vect/pr45847.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++
++
++long long foo (long long *__restrict a,  int *__restrict b, int *__restrict c )
++{
++  int i;
++  long long sum=0;
++  for (i=0;i<256;i++)
++   sum += (long long)b[i] * c[i];
++
++  return sum;
++}
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+Index: gcc-4.5/gcc/tree-vect-patterns.c
+===================================================================
+--- gcc-4.5.orig/gcc/tree-vect-patterns.c
++++ gcc-4.5/gcc/tree-vect-patterns.c
+@@ -411,6 +411,7 @@ vect_recog_widen_mult_pattern (gimple la
+   /* Check target support  */
+   vectype = get_vectype_for_scalar_type (half_type0);
+   if (!vectype
++      || !get_vectype_for_scalar_type (type)
+       || !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt, vectype,
+ 					  &dummy, &dummy, &dummy_code,
+ 					  &dummy_code, &dummy_int, &dummy_vec))
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch
new file mode 100644
index 0000000000..4f94fc9d66
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch
@@ -0,0 +1,67 @@
+Index: gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.h
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/config/locale/generic/c_locale.h	2010-06-30 22:30:53.993316002 -0700
++++ gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.h	2010-06-30 22:31:26.043316001 -0700
+@@ -41,12 +41,17 @@
+ 
+ #include <clocale>
+ #include <cstddef>
++#include <features.h>
++#include <ctype.h>
+ 
+ #define _GLIBCXX_NUM_CATEGORIES 0
+ 
+ _GLIBCXX_BEGIN_NAMESPACE(std)
+-
+-  typedef int*			__c_locale;
++#ifdef __UCLIBC__
++   typedef __ctype_touplow_t*   __c_locale;
++#else
++   typedef int*         __c_locale;
++#endif
+ 
+   // Convert numeric value of type double and long double to string and
+   // return length of string.  If vsnprintf is available use it, otherwise
+Index: gcc-4.5/libstdc++-v3/config/os/gnu-linux/ctype_base.h
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/config/os/gnu-linux/ctype_base.h	2010-06-30 22:30:54.013316002 -0700
++++ gcc-4.5/libstdc++-v3/config/os/gnu-linux/ctype_base.h	2010-06-30 22:31:26.053316001 -0700
+@@ -33,14 +33,21 @@
+  */
+ 
+ // Information as gleaned from /usr/include/ctype.h
+-  
++
++#include <features.h>
++#include <ctype.h>
++
+ _GLIBCXX_BEGIN_NAMESPACE(std)
+ 
+   /// @brief  Base class for ctype.
+   struct ctype_base
+   {
+     // Non-standard typedefs.
+-    typedef const int* 		__to_type;
++#ifdef __UCLIBC__
++    typedef const __ctype_touplow_t*   __to_type;
++#else
++    typedef const int*         __to_type;
++#endif
+ 
+     // NB: Offsets into ctype<char>::_M_table force a particular size
+     // on the mask type. Because of this, we don't use an enum.
+Index: gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.cc
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/config/locale/generic/c_locale.cc	2010-06-28 12:12:42.000000000 -0700
++++ gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.cc	2010-06-30 22:31:26.063316001 -0700
+@@ -256,5 +256,10 @@ _GLIBCXX_END_NAMESPACE
+ #ifdef _GLIBCXX_LONG_DOUBLE_COMPAT
+ #define _GLIBCXX_LDBL_COMPAT(dbl, ldbl) \
+   extern "C" void ldbl (void) __attribute__ ((alias (#dbl)))
++#ifdef __UCLIBC__
++// This is because __c_locale is of type __ctype_touplow_t* which is short on uclibc. for glibc its int*
++_GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPs, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPs);
++#else
+ _GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPi, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPi);
++#endif
+ #endif // _GLIBCXX_LONG_DOUBLE_COMPAT
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch
new file mode 100644
index 0000000000..ac4281ac28
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch
@@ -0,0 +1,212 @@
+Upstream-Status: Backport
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+
+commit 3cb9bbfa927aa187048534f9069202c017a78e38
+Author: ppluzhnikov <ppluzhnikov@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date:   Wed May 11 18:28:14 2011 +0000
+
+    2011-05-11  Satoru Takabayashi  <satorux@google.com>
+    	    Paul Pluzhnikov  <ppluzhnikov@google.com>
+    
+    	* gcc/doc/install.texi (Configuration): Document
+    	--with-linker-hash-style.
+    	* gcc/gcc.c (init_spec): Handle LINKER_HASH_STYLE.
+    	* gcc/config.in: Add LINKER_HASH_STYLE.
+    	* gcc/configure.ac: Add --with-linker-hash-style.
+    	* gcc/configure: Regenerate.
+    
+    
+    
+    git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173668 138bc75d-0d04-0410-961f-82ee72b054a4
+
+Index: gcc-4_5-branch/gcc/config.in
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config.in	2011-12-03 13:41:00.000000000 -0800
++++ gcc-4_5-branch/gcc/config.in	2011-12-03 13:44:46.287530329 -0800
+@@ -113,6 +113,12 @@
+ #endif
+ 
+ 
++/* The linker hash style */
++#ifndef USED_FOR_TARGET
++#undef LINKER_HASH_STYLE
++#endif
++
++
+ /* Define to enable LTO support. */
+ #ifndef USED_FOR_TARGET
+ #undef ENABLE_LTO
+Index: gcc-4_5-branch/gcc/configure
+===================================================================
+--- gcc-4_5-branch.orig/gcc/configure	2011-12-03 13:41:00.000000000 -0800
++++ gcc-4_5-branch/gcc/configure	2011-12-03 13:46:12.747530321 -0800
+@@ -600,6 +600,7 @@
+ 
+ ac_subst_vars='LTLIBOBJS
+ LIBOBJS
++enable_target_optspace
+ enable_plugin
+ pluginlibs
+ LIBELFINC
+@@ -915,7 +916,7 @@
+ with_slibdir
+ enable_poison_system_directories
+ enable_plugin
+-enable_target_optspace
++with_linker_hash_style
+ '
+       ac_precious_vars='build_alias
+ host_alias
+@@ -1663,6 +1664,8 @@
+                           with the compiler
+   --with-system-zlib      use installed libz
+   --with-slibdir=DIR      shared libraries in DIR [LIBDIR]
++  --with-linker-hash-style={sysv,gnu,both}
++                          specify the linker hash style
+ 
+ Some influential environment variables:
+   CC          C compiler command
+@@ -17115,7 +17118,7 @@
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 17114 "configure"
++#line 17121 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -17221,7 +17224,7 @@
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 17220 "configure"
++#line 17227 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -25659,12 +25662,42 @@
+ 
+ fi
+ 
+-if test x"$enable_target_optspace" != x; then :
++
++if test x"$enable_target_optspace" != x; then
+ 
+ $as_echo "#define ENABLE_TARGET_OPTSPACE 1" >>confdefs.h
+ 
+ fi
+ 
++# Specify what hash style to use by default.
++
++# Check whether --with-linker-hash-style was given.
++if test "${with_linker_hash_style+set}" = set; then :
++  withval=$with_linker_hash_style; case x"$withval" in
++   xsysv)
++     LINKER_HASH_STYLE=sysv
++     ;;
++   xgnu)
++     LINKER_HASH_STYLE=gnu
++     ;;
++   xboth)
++     LINKER_HASH_STYLE=both
++     ;;
++   *)
++     as_fn_error "$withval is an invalid option to --with-linker-hash-style" "$LINENO" 5
++     ;;
++ esac
++else
++  LINKER_HASH_STYLE=''
++fi
++
++if test x"${LINKER_HASH_STYLE}" != x; then
++
++cat >>confdefs.h <<_ACEOF
++#define LINKER_HASH_STYLE "$LINKER_HASH_STYLE"
++_ACEOF
++
++fi
+ 
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+Index: gcc-4_5-branch/gcc/configure.ac
+===================================================================
+--- gcc-4_5-branch.orig/gcc/configure.ac	2011-12-03 13:41:00.000000000 -0800
++++ gcc-4_5-branch/gcc/configure.ac	2011-12-03 13:41:04.499530358 -0800
+@@ -4664,6 +4664,30 @@
+   AC_DEFINE(ENABLE_TARGET_OPTSPACE, 1, [Define to enable target optspace support.])
+ fi
+ 
++# Specify what hash style to use by default.
++AC_ARG_WITH([linker-hash-style],
++[AC_HELP_STRING([--with-linker-hash-style={sysv,gnu,both}],
++                [specify the linker hash style])],
++[case x"$withval" in
++   xsysv)
++     LINKER_HASH_STYLE=sysv
++     ;;
++   xgnu)
++     LINKER_HASH_STYLE=gnu
++     ;;
++   xboth)
++     LINKER_HASH_STYLE=both
++     ;;
++   *)
++     AC_MSG_ERROR([$withval is an invalid option to --with-linker-hash-style])
++     ;;
++ esac],
++[LINKER_HASH_STYLE=''])
++if test x"${LINKER_HASH_STYLE}" != x; then
++  AC_DEFINE_UNQUOTED(LINKER_HASH_STYLE, "$LINKER_HASH_STYLE",
++                                         [The linker hash style])
++fi
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 
+Index: gcc-4_5-branch/gcc/doc/install.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/install.texi	2011-12-03 13:15:09.000000000 -0800
++++ gcc-4_5-branch/gcc/doc/install.texi	2011-12-03 13:41:04.499530358 -0800
+@@ -1630,6 +1630,11 @@
+ support @option{--build-id} option, a warning is issued and the
+ @option{--enable-linker-build-id} option is ignored.  The default is off.
+ 
++@item --with-linker-hash-style=@var{choice}
++Tells GCC to pass @option{--hash-style=@var{choice}} option to the
++linker for all final links. @var{choice} can be one of
++@samp{sysv}, @samp{gnu}, and @samp{both} where @samp{sysv} is the default.
++
+ @item --enable-gnu-unique-object
+ @itemx --disable-gnu-unique-object
+ Tells GCC to use the gnu_unique_object relocation for C++ template
+Index: gcc-4_5-branch/gcc/gcc.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/gcc.c	2011-12-03 13:41:00.000000000 -0800
++++ gcc-4_5-branch/gcc/gcc.c	2011-12-03 13:41:04.499530358 -0800
+@@ -1917,7 +1917,8 @@
+   }
+ #endif
+ 
+-#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC
++#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC || \
++    defined LINKER_HASH_STYLE
+ # ifdef LINK_BUILDID_SPEC
+   /* Prepend LINK_BUILDID_SPEC to whatever link_spec we had before.  */
+   obstack_grow (&obstack, LINK_BUILDID_SPEC, sizeof(LINK_BUILDID_SPEC) - 1);
+@@ -1926,6 +1927,16 @@
+   /* Prepend LINK_EH_SPEC to whatever link_spec we had before.  */
+   obstack_grow (&obstack, LINK_EH_SPEC, sizeof(LINK_EH_SPEC) - 1);
+ # endif
++# ifdef LINKER_HASH_STYLE
++  /* Prepend --hash-style=LINKER_HASH_STYLE to whatever link_spec we had
++     before.  */
++  {
++    static const char hash_style[] = "--hash-style=";
++    obstack_grow (&obstack, hash_style, sizeof(hash_style) - 1);
++    obstack_grow (&obstack, LINKER_HASH_STYLE, sizeof(LINKER_HASH_STYLE) - 1);
++    obstack_1grow (&obstack, ' ');
++  }
++# endif
+   obstack_grow0 (&obstack, link_spec, strlen (link_spec));
+   link_spec = XOBFINISH (&obstack, const char *);
+ #endif
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch
new file mode 100644
index 0000000000..5f134ef338
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch
@@ -0,0 +1,9 @@
+the svn patch changed the BASE-VER to 4.5.1, bring it back to 4.5.0
+- Nitin A Kamble nitin.a.kamble@intel.com
+- 2010/07/20
+
+--- gcc-4.5.0/gcc/BASE-VER	2010-07-20 00:57:37.000000000 -0700
++++ gcc-4.5.0.new/gcc/BASE-VER	2010-07-20 01:06:17.000000000 -0700
+@@ -1 +1 @@
+-4.5.1
++4.5.0
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch
new file mode 100644
index 0000000000..ada36a5914
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch
@@ -0,0 +1,40 @@
+2010-06-07  Khem Raj  <raj.khem@gmail.com>
+
+	* libsupc++/eh_arm.cc (__cxa_end_cleanup): Use .pushsection/.popsection
+	to emit inline assembly into .text section.
+
+Index: gcc-4.5/libstdc++-v3/libsupc++/eh_arm.cc
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/libsupc++/eh_arm.cc	2010-06-04 23:20:18.000000000 -0700
++++ gcc-4.5/libstdc++-v3/libsupc++/eh_arm.cc	2010-06-08 11:27:34.247541722 -0700
+@@ -157,22 +157,26 @@ __gnu_end_cleanup(void)
+ // Assembly wrapper to call __gnu_end_cleanup without clobbering r1-r3.
+ // Also push r4 to preserve stack alignment.
+ #ifdef __thumb__
+-asm (".global __cxa_end_cleanup\n"
++asm ("  .pushsection .text.__cxa_end_cleanup\n"
++"	.global __cxa_end_cleanup\n"
+ "	.type __cxa_end_cleanup, \"function\"\n"
+ "	.thumb_func\n"
+ "__cxa_end_cleanup:\n"
+ "	push\t{r1, r2, r3, r4}\n"
+ "	bl\t__gnu_end_cleanup\n"
+ "	pop\t{r1, r2, r3, r4}\n"
+-"	bl\t_Unwind_Resume @ Never returns\n");
++"	bl\t_Unwind_Resume @ Never returns\n"
++"	.popsection\n");
+ #else
+-asm (".global __cxa_end_cleanup\n"
++asm ("  .pushsection .text.__cxa_end_cleanup\n"
++"	.global __cxa_end_cleanup\n"
+ "	.type __cxa_end_cleanup, \"function\"\n"
+ "__cxa_end_cleanup:\n"
+ "	stmfd\tsp!, {r1, r2, r3, r4}\n"
+ "	bl\t__gnu_end_cleanup\n"
+ "	ldmfd\tsp!, {r1, r2, r3, r4}\n"
+-"	bl\t_Unwind_Resume @ Never returns\n");
++"	bl\t_Unwind_Resume @ Never returns\n"
++"	.popsection\n");
+ #endif
+ 
+ #endif
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch
new file mode 100644
index 0000000000..70c9e81542
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch
@@ -0,0 +1,71 @@
+#! /bin/sh -e
+
+# DP: Build and install libstdc++_pic.a library.
+
+dir=
+if [ $# -eq 3 -a "$2" = '-d' ]; then
+    pdir="-d $3"
+    dir="$3/"
+elif [ $# -ne 1 ]; then
+    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+    exit 1
+fi
+case "$1" in
+    -patch)
+        patch $pdir -f --no-backup-if-mismatch -p0 < $0
+        ;;
+    -unpatch)
+        patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
+        ;;
+    *)
+        echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+        exit 1
+esac
+exit 0
+
+diff -ur libstdc++-v3/src/Makefile.am libstdc++-v3/src/Makefile.am
+--- libstdc++-v3/src/Makefile.am~	2004-04-16 21:04:05.000000000 +0200
++++ libstdc++-v3/src/Makefile.am	2004-07-03 20:22:43.000000000 +0200
+@@ -210,6 +210,10 @@
+ 	  $(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LDFLAGS) -o $@
+ 
+ 
++install-exec-local:
++	$(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a
++	$(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
++
+ # Added bits to build debug library.
+ if GLIBCXX_BUILD_DEBUG
+ all-local: build_debug
+diff -ur libstdc++-v3/src/Makefile.in libstdc++-v3/src/Makefile.in
+--- libstdc++-v3/src/Makefile.in	2004-07-03 06:41:13.000000000 +0200
++++ libstdc++-v3/src/Makefile.in	2004-07-03 20:25:05.000000000 +0200
+@@ -611,7 +611,7 @@
+ 
+ install-data-am: install-data-local
+ 
+-install-exec-am: install-toolexeclibLTLIBRARIES
++install-exec-am: install-toolexeclibLTLIBRARIES install-exec-local
+ 
+ install-info: install-info-am
+ 
+@@ -644,6 +644,7 @@
+ 	distclean-libtool distclean-tags distdir dvi dvi-am html \
+ 	html-am info info-am install install-am install-data \
+ 	install-data-am install-data-local install-exec \
++	install-exec-local \
+ 	install-exec-am install-info install-info-am install-man \
+ 	install-strip install-toolexeclibLTLIBRARIES installcheck \
+ 	installcheck-am installdirs maintainer-clean \
+@@ -729,6 +730,11 @@
+ install_debug:
+ 	(cd ${debugdir} && $(MAKE) \
+ 	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install)
++
++install-exec-local:
++	$(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a
++	$(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
++
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
+ .NOEXPORT:
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch
new file mode 100644
index 0000000000..bff745dae0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch
@@ -0,0 +1,207 @@
+2010-06-28  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	Daniel Jacobowitz  <dan@codesourcery.com>
+	Joseph Myers  <joseph@codesourcery.com>
+
+	gcc/
+	* doc/invoke.texi (-Wno-poison-system-directories): Document.
+	* gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories
+	if -Wno-poison-system-directories and --error-poison-system-directories
+	if -Werror=poison-system-directories to linker.
+	* incpath.c: Include flags.h. Include toplev.h.
+	(merge_include_chains): If ENABLE_POISON_SYSTEM_DIRECTORIES defined
+	and flag_poison_system_directories is true, warn for use of
+	/usr/include, /usr/local/include or /usr/X11R6/include.
+	* Makefile.in (incpath.o): Depend on $(FLAGS_H) and toplev.h.
+	* common.opt (--Wno-poison-system-directories): New.
+	* configure.ac (--enable-poison-system-directories): New option.
+	* configure: Regenerate.
+	* config.in: Regenerate.
+
+Index: gcc-4.5/gcc/Makefile.in
+===================================================================
+--- gcc-4.5.orig/gcc/Makefile.in	2010-09-23 16:44:12.000000000 -0700
++++ gcc-4.5/gcc/Makefile.in	2010-09-23 16:46:33.552416860 -0700
+@@ -1969,7 +1969,7 @@ gcc.srcextra: gengtype-lex.c
+ 
+ incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \
+ 		intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \
+-		$(MACHMODE_H)
++		$(MACHMODE_H) $(FLAGS_H) toplev.h
+ 
+ c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \
+     $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \
+Index: gcc-4.5/gcc/common.opt
+===================================================================
+--- gcc-4.5.orig/gcc/common.opt	2010-07-11 16:14:47.000000000 -0700
++++ gcc-4.5/gcc/common.opt	2010-09-23 16:46:33.556418045 -0700
+@@ -152,6 +152,10 @@ Wpadded
+ Common Var(warn_padded) Warning
+ Warn when padding is required to align structure members
+ 
++Wpoison-system-directories
++Common Var(flag_poison_system_directories) Init(1)
++Warn for -I and -L options using system directories if cross compiling
++
+ Wshadow
+ Common Var(warn_shadow) Warning
+ Warn when one local variable shadows another
+Index: gcc-4.5/gcc/config.in
+===================================================================
+--- gcc-4.5.orig/gcc/config.in	2010-07-11 16:14:46.000000000 -0700
++++ gcc-4.5/gcc/config.in	2010-09-23 16:46:33.556418045 -0700
+@@ -132,6 +132,12 @@
+ #endif
+ 
+ 
++/* Define to warn for use of native system header directories */
++#ifndef USED_FOR_TARGET
++#undef ENABLE_POISON_SYSTEM_DIRECTORIES
++#endif
++
++
+ /* Define if you want all operations on RTL (the basic data structure of the
+    optimizer and back end) to be checked for dynamic type safety at runtime.
+    This is quite expensive. */
+Index: gcc-4.5/gcc/configure
+===================================================================
+--- gcc-4.5.orig/gcc/configure	2010-09-23 16:44:11.000000000 -0700
++++ gcc-4.5/gcc/configure	2010-09-23 16:46:33.572415719 -0700
+@@ -913,6 +913,7 @@ with_system_zlib
+ enable_maintainer_mode
+ enable_version_specific_runtime_libs
+ with_slibdir
++enable_poison_system_directories
+ enable_plugin
+ '
+       ac_precious_vars='build_alias
+@@ -1620,6 +1621,8 @@ Optional Features:
+   --enable-version-specific-runtime-libs
+                           specify that runtime libraries should be
+                           installed in a compiler-specific directory
++  --enable-poison-system-directories
++                          warn for use of native system header directories
+   --enable-plugin         enable plugin support
+ 
+ Optional Packages:
+@@ -25345,6 +25348,19 @@ fi
+ 
+ 
+ 
++# Check whether --enable-poison-system-directories was given.
++if test "${enable_poison_system_directories+set}" = set; then :
++  enableval=$enable_poison_system_directories;
++else
++  enable_poison_system_directories=no
++fi
++
++if test "x${enable_poison_system_directories}" = "xyes"; then
++
++$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h
++
++fi
++
+ # Substitute configuration variables
+ 
+ 
+Index: gcc-4.5/gcc/configure.ac
+===================================================================
+--- gcc-4.5.orig/gcc/configure.ac	2010-09-23 16:44:11.000000000 -0700
++++ gcc-4.5/gcc/configure.ac	2010-09-23 16:46:33.576417624 -0700
+@@ -4439,6 +4439,16 @@ else
+ fi)
+ AC_SUBST(slibdir)
+ 
++AC_ARG_ENABLE([poison-system-directories],
++	      AS_HELP_STRING([--enable-poison-system-directories],
++			     [warn for use of native system header directories]),,
++	      [enable_poison_system_directories=no])
++if test "x${enable_poison_system_directories}" = "xyes"; then
++  AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES],
++	    [1],
++	    [Define to warn for use of native system header directories])
++fi
++
+ # Substitute configuration variables
+ AC_SUBST(subdirs)
+ AC_SUBST(srcdir)
+Index: gcc-4.5/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4.5.orig/gcc/doc/invoke.texi	2010-09-23 15:33:28.000000000 -0700
++++ gcc-4.5/gcc/doc/invoke.texi	2010-09-23 16:46:33.584416934 -0700
+@@ -252,6 +252,7 @@ Objective-C and Objective-C++ Dialects}.
+ -Woverlength-strings  -Wpacked  -Wpacked-bitfield-compat  -Wpadded @gol
+ -Wparentheses  -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
+ -Wpointer-arith  -Wno-pointer-to-int-cast @gol
++-Wno-poison-system-directories @gol
+ -Wredundant-decls @gol
+ -Wreturn-type  -Wsequence-point  -Wshadow @gol
+ -Wsign-compare  -Wsign-conversion  -Wstack-protector @gol
+@@ -3603,6 +3604,14 @@ code.  However, note that using @option{
+ option will @emph{not} warn about unknown pragmas in system
+ headers---for that, @option{-Wunknown-pragmas} must also be used.
+ 
++@item -Wno-poison-system-directories
++@opindex Wno-poison-system-directories
++Do not warn for @option{-I} or @option{-L} options using system
++directories such as @file{/usr/include} when cross compiling.  This
++option is intended for use in chroot environments when such
++directories contain the correct headers and libraries for the target
++system rather than the host.
++
+ @item -Wfloat-equal
+ @opindex Wfloat-equal
+ @opindex Wno-float-equal
+Index: gcc-4.5/gcc/gcc.c
+===================================================================
+--- gcc-4.5.orig/gcc/gcc.c	2010-07-11 16:14:46.000000000 -0700
++++ gcc-4.5/gcc/gcc.c	2010-09-23 16:46:33.588417920 -0700
+@@ -792,6 +792,8 @@ proper position among the other output f
+     %{flto} %{fwhopr} %l " LINK_PIE_SPEC \
+    "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
+     %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
++    %{Wno-poison-system-directories:--no-poison-system-directories}\
++    %{Werror=poison-system-directories:--error-poison-system-directories}\
+     %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
+     %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\
+     %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\
+Index: gcc-4.5/gcc/incpath.c
+===================================================================
+--- gcc-4.5.orig/gcc/incpath.c	2010-07-11 16:14:44.000000000 -0700
++++ gcc-4.5/gcc/incpath.c	2010-09-23 16:46:33.588417920 -0700
+@@ -30,6 +30,8 @@
+ #include "intl.h"
+ #include "incpath.h"
+ #include "cppdefault.h"
++#include "flags.h"
++#include "toplev.h"
+ 
+ /* Microsoft Windows does not natively support inodes.
+    VMS has non-numeric inodes.  */
+@@ -353,6 +355,24 @@ merge_include_chains (const char *sysroo
+ 	}
+       fprintf (stderr, _("End of search list.\n"));
+     }
++
++#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES
++  if (flag_poison_system_directories)
++    {
++	struct cpp_dir *p;
++
++	for (p = heads[QUOTE]; p; p = p->next)
++	  {
++	   if ((!strncmp (p->name, "/usr/include", 12))
++	       || (!strncmp (p->name, "/usr/local/include", 18))
++	       || (!strncmp (p->name, "/usr/X11R6/include", 18)))
++	     warning (OPT_Wpoison_system_directories,
++		      "include location \"%s\" is unsafe for "
++		      "cross-compilation",
++		      p->name);
++	  }
++    }
++#endif
+ }
+ 
+ /* Use given -I paths for #include "..." but not #include <...>, and
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch
new file mode 100644
index 0000000000..541134a6bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch
@@ -0,0 +1,26654 @@
+2010-07-07 Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from mainline (originally from Sourcery G++ 4.4):
+
+	2010-05-24  Daniel Jacobowitz  <dan@codesourcery.com>
+		    Sandra Loosemore  <sandra@codesourcery.com>
+
+	gcc/
+	* config/arm/neon-testgen.ml: Use dg-add-options arm_neon.
+	* doc/sourcebuild.texi (Effective-Target Keywords): Update arm_neon_ok
+	description.  Add arm_neon_fp16_ok.
+	(Add Options): Add arm_neon and arm_neon_fp16.
+
+	gcc/testsuite/
+	* gcc.target/arm/neon/: Regenerated test cases.
+
+	* gcc.target/arm/neon/polytypes.c,
+	gcc.target/arm/neon-vmla-1.c, gcc.target/arm/neon-vmls-1.c,
+	gcc.target/arm/neon-cond-1.c, gcc.target/arm/neon/vfp-shift-a2t2.c,
+	gcc.target/arm/neon-thumb2-move.c, gcc.dg/torture/arm-fp16-ops-8.c, 
+	gcc.dg/torture/arm-fp16-ops-7.c, g++.dg/ext/arm-fp16/arm-fp16-ops-7.C,
+	g++.dg/ext/arm-fp16/arm-fp16-ops-8.C, g++.dg/abi/mangle-neon.C: Use
+	dg-add-options arm_neon.
+
+	* gcc.target/arm/fp16-compile-vcvt.c, gcc.dg/torture/arm-fp16-ops-5.c,
+	gcc.dg/torture/arm-fp16-ops-6.c, g++.dg/ext/arm-fp16/arm-fp16-ops-5.C,
+	g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Use dg-add-options arm_neon_fp16
+	and arm_neon_fp16_ok.
+
+	* gcc.dg/vect/vect.exp, g++.dg/vect/vect.exp,
+	gfortran.dg/vect/vect.exp: Use add_options_for_arm_neon.
+
+	* lib/target-supports.exp (add_options_for_arm_neon): New.
+	(check_effective_target_arm_neon_ok_nocache): New, from
+	check_effective_target_arm_neon_ok.  Check multiple possibilities.
+	(check_effective_target_arm_neon_ok): Use
+	check_effective_target_arm_neon_ok_nocache.
+	(add_options_for_arm_neon_fp16)
+	(check_effective_target_arm_neon_fp16_ok)
+	check_effective_target_arm_neon_fp16_ok_nocache): New.
+	(check_effective_target_arm_neon_hw): Use add_options_for_arm_neon.
+
+
+=== modified file 'gcc/config/arm/neon-testgen.ml'
+Index: gcc-4_5-branch/gcc/config/arm/neon-testgen.ml
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/neon-testgen.ml
++++ gcc-4_5-branch/gcc/config/arm/neon-testgen.ml
+@@ -51,8 +51,8 @@ let emit_prologue chan test_name =
+   Printf.fprintf chan "/* This file was autogenerated by neon-testgen.  */\n\n";
+   Printf.fprintf chan "/* { dg-do assemble } */\n";
+   Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n";
+-  Printf.fprintf chan
+-                 "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n";
++  Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n";
++  Printf.fprintf chan "/* { dg-add-options arm_neon } */\n";
+   Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n";
+   Printf.fprintf chan "void test_%s (void)\n{\n" test_name
+ 
+Index: gcc-4_5-branch/gcc/doc/sourcebuild.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/sourcebuild.texi
++++ gcc-4_5-branch/gcc/doc/sourcebuild.texi
+@@ -362,7 +362,7 @@ A copy of @file{texinfo.tex} known to wo
+ @end table
+ 
+ DVI-formatted manuals are generated by @samp{make dvi}, which uses
+-@command{texi2dvi} (via the Makefile macro @code{$(TEXI2DVI)}).  
++@command{texi2dvi} (via the Makefile macro @code{$(TEXI2DVI)}).
+ PDF-formatted manuals are generated by @samp{make pdf}, which uses
+ @command{texi2pdf} (via the Makefile macro @code{$(TEXI2PDF)}).  HTML
+ formatted manuals are generated by @samp{make html}.  Info
+@@ -1500,8 +1500,14 @@ ARM target supports generating NEON inst
+ Test system supports executing NEON instructions.
+ 
+ @item arm_neon_ok
+-ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp}.
+-Some multilibs may be incompatible with these options.
++@anchor{arm_neon_ok}
++ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible
++options.  Some multilibs may be incompatible with these options.
++
++@item arm_neon_fp16_ok
++@anchor{arm_neon_fp16_ok}
++ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible
++options.  Some multilibs may be incompatible with these options.
+ 
+ @item arm_thumb1_ok
+ ARM target generates Thumb-1 code for @code{-mthumb}.
+@@ -1895,6 +1901,16 @@ Only MIPS targets support this feature,
+ 
+ @item tls
+ Add the target-specific flags needed to use thread-local storage.
++
++@item arm_neon
++NEON support.  Only ARM targets support this feature, and only then
++in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target
++keyword}.
++
++@item arm_neon_fp16
++NEON and half-precision floating point support.  Only ARM targets
++support this feature, and only then in certain modes; see
++the @ref{arm_neon_ok,,arm_neon_fp16_ok effective target keyword}.
+ @end table
+ 
+ @node Require Support
+Index: gcc-4_5-branch/gcc/testsuite/g++.dg/abi/mangle-neon.C
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/abi/mangle-neon.C
++++ gcc-4_5-branch/gcc/testsuite/g++.dg/abi/mangle-neon.C
+@@ -2,7 +2,7 @@
+ 
+ // { dg-do compile }
+ // { dg-require-effective-target arm_neon_ok }
+-// { dg-options "-mfpu=neon -mfloat-abi=softfp" }
++// { dg-add-options arm_neon }
+ 
+ #include <arm_neon.h>
+ 
+Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C
++++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
++/* { dg-require-effective-target arm_neon_fp16_ok } */
++/* { dg-options "-mfp16-format=ieee" } */
++/* { dg-add-options arm_neon_fp16 } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C
++++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */
++/* { dg-require-effective-target arm_neon_fp16_ok } */
++/* { dg-options "-mfp16-format=ieee -ffast-math" } */
++/* { dg-add-options arm_neon_fp16 } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C
++++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-mfp16-format=ieee" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C
++++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-mfp16-format=ieee -ffast-math" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/g++.dg/vect/vect.exp
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/vect/vect.exp
++++ gcc-4_5-branch/gcc/testsuite/g++.dg/vect/vect.exp
+@@ -112,7 +112,7 @@ if  [istarget "powerpc-*paired*"]  {
+ } elseif [istarget "ia64-*-*"] {
+     set dg-do-what-default run
+ } elseif [is-effective-target arm_neon_ok] {
+-    lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
++    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
+     if [is-effective-target arm_neon_hw] {
+       set dg-do-what-default run
+     } else {
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
++/* { dg-require-effective-target arm_neon_fp16_ok } */
++/* { dg-options "-mfp16-format=ieee" } */
++/* { dg-add-options arm_neon_fp16 } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */
++/* { dg-require-effective-target arm_neon_fp16_ok } */
++/* { dg-options "-mfp16-format=ieee -ffast-math" } */
++/* { dg-add-options arm_neon_fp16 } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-mfp16-format=ieee" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c
+@@ -1,7 +1,8 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-mfp16-format=ieee -ffast-math" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm-fp16-ops.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/vect/vect.exp
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/vect/vect.exp
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/vect/vect.exp
+@@ -104,7 +104,7 @@ if  [istarget "powerpc-*paired*"]  {
+ } elseif [istarget "ia64-*-*"] {
+     set dg-do-what-default run
+ } elseif [is-effective-target arm_neon_ok] {
+-    lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
++    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
+     if [is-effective-target arm_neon_hw] {
+       set dg-do-what-default run
+     } else {
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
+@@ -1,6 +1,7 @@
+ /* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
++/* { dg-require-effective-target arm_neon_fp16_ok } */
++/* { dg-options "-mfp16-format=ieee" } */
++/* { dg-add-options arm_neon_fp16 } */
+ 
+ /* Test generation of VFP __fp16 instructions.  */
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-cond-1.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-cond-1.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-cond-1.c
+@@ -1,6 +1,7 @@
+ /* { dg-do run } */
+ /* { dg-require-effective-target arm_neon_hw } */
+-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
+ /* Check that the arm_final_prescan_insn ccfsm code does not try to
+  * conditionally execute NEON instructions.  */
+ #include <arm_neon.h>
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
+@@ -1,6 +1,7 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -mthumb -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */
++/* { dg-options "-O2 -mthumb -march=armv7-a" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include <arm_neon.h>
+ #include <stddef.h>
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
+@@ -1,5 +1,6 @@
+ /* { dg-require-effective-target arm_neon_hw } */
+-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
++/* { dg-options "-O2 -ftree-vectorize" } */
++/* { dg-add-options arm_neon } */
+ /* { dg-final { scan-assembler "vmla\\.f32" } } */
+ 
+ /* Verify that VMLA is used.  */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmls-1.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-vmls-1.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmls-1.c
+@@ -1,5 +1,6 @@
+ /* { dg-require-effective-target arm_neon_hw } */
+-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
++/* { dg-options "-O2 -ftree-vectorize" } */
++/* { dg-add-options arm_neon } */
+ /* { dg-final { scan-assembler "vmls\\.f32" } } */
+ 
+ /* Verify that VMLS is used.  */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/polytypes.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/polytypes.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/polytypes.c
+@@ -3,7 +3,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include <arm_neon.h>
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabals16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabals32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabals8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabas16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabas32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabas8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabau16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabau32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabau8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabds16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabds32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabds8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabss16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabss32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabss8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcges16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcges32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcges8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcles16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcles32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcles8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclss16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclss32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclss8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclts16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclts32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclts8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
+@@ -2,7 +2,8 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include <arm_neon.h>
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmins16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmins32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmins8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzips16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzips32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzips8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
+@@ -3,7 +3,8 @@
+ 
+ /* { dg-do assemble } */
+ /* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
++/* { dg-options "-save-temps -O0" } */
++/* { dg-add-options arm_neon } */
+ 
+ #include "arm_neon.h"
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gfortran.dg/vect/vect.exp
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gfortran.dg/vect/vect.exp
++++ gcc-4_5-branch/gcc/testsuite/gfortran.dg/vect/vect.exp
+@@ -105,7 +105,7 @@ if  [istarget "powerpc-*paired*"]  {
+ } elseif [istarget "ia64-*-*"] {
+     set dg-do-what-default run
+ } elseif [is-effective-target arm_neon_ok] {
+-    lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
++    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
+     if [is-effective-target arm_neon_hw] {
+       set dg-do-what-default run
+     } else {
+Index: gcc-4_5-branch/gcc/testsuite/lib/target-supports.exp
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/lib/target-supports.exp
++++ gcc-4_5-branch/gcc/testsuite/lib/target-supports.exp
+@@ -1695,19 +1695,87 @@ proc check_effective_target_arm_hard_vfp
+     }
+ }
+ 
++# Add the options needed for NEON.  We need either -mfloat-abi=softfp
++# or -mfloat-abi=hard, but if one is already specified by the
++# multilib, use it.  Similarly, if a -mfpu option already enables
++# NEON, do not add -mfpu=neon.
++
++proc add_options_for_arm_neon { flags } {
++    if { ! [check_effective_target_arm_neon_ok] } {
++	return "$flags"
++    }
++    global et_arm_neon_flags
++    return "$flags $et_arm_neon_flags"
++}
++
+ # Return 1 if this is an ARM target supporting -mfpu=neon
+-# -mfloat-abi=softfp.  Some multilibs may be incompatible with these
+-# options.
++# -mfloat-abi=softfp or equivalent options.  Some multilibs may be
++# incompatible with these options.  Also set et_arm_neon_flags to the
++# best options to add.
++
++proc check_effective_target_arm_neon_ok_nocache { } {
++    global et_arm_neon_flags
++    set et_arm_neon_flags ""
++    if { [check_effective_target_arm32] } {
++	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} {
++	    if { [check_no_compiler_messages_nocache arm_neon_ok object {
++		#include "arm_neon.h"
++		int dummy;
++	    } "$flags"] } {
++		set et_arm_neon_flags $flags
++		return 1
++	    }
++	}
++    }
++
++    return 0
++}
+ 
+ proc check_effective_target_arm_neon_ok { } {
++    return [check_cached_effective_target arm_neon_ok \
++		check_effective_target_arm_neon_ok_nocache]
++}
++
++# Add the options needed for NEON.  We need either -mfloat-abi=softfp
++# or -mfloat-abi=hard, but if one is already specified by the
++# multilib, use it.
++
++proc add_options_for_arm_neon_fp16 { flags } {
++    if { ! [check_effective_target_arm_neon_fp16_ok] } {
++	return "$flags"
++    }
++    global et_arm_neon_fp16_flags
++    return "$flags $et_arm_neon_fp16_flags"
++}
++
++# Return 1 if this is an ARM target supporting -mfpu=neon-fp16
++# -mfloat-abi=softfp or equivalent options.  Some multilibs may be
++# incompatible with these options.  Also set et_arm_neon_flags to the
++# best options to add.
++
++proc check_effective_target_arm_neon_fp16_ok_nocache { } {
++    global et_arm_neon_fp16_flags
++    set et_arm_neon_fp16_flags ""
+     if { [check_effective_target_arm32] } {
+-        return [check_no_compiler_messages arm_neon_ok object {
+-	    #include "arm_neon.h"
+-            int dummy;
+-        } "-mfpu=neon -mfloat-abi=softfp"]
+-    } else {
+-        return 0
++	# Always add -mfpu=neon-fp16, since there is no preprocessor
++	# macro for FP16 support.
++	foreach flags {"-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
++	    if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
++		#include "arm_neon.h"
++		int dummy;
++	    } "$flags"] } {
++		set et_arm_neon_fp16_flags $flags
++		return 1
++	    }
++	}
+     }
++
++    return 0
++}
++
++proc check_effective_target_arm_neon_fp16_ok { } {
++    return [check_cached_effective_target arm_neon_fp16_ok \
++		check_effective_target_arm_neon_fp16_ok_nocache]
+ }
+ 
+ # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
+@@ -1746,7 +1814,7 @@ proc check_effective_target_arm_neon_hw
+ 	       : "0" (a), "w" (b));
+ 	  return (a != 1);
+ 	}
+-    } "-mfpu=neon -mfloat-abi=softfp"]
++    } [add_options_for_arm_neon ""]]
+ }
+ 
+ # Return 1 if this is a ARM target with NEON enabled.
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch
new file mode 100644
index 0000000000..7dea4303a9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch
@@ -0,0 +1,62 @@
+2010-07-07  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	2010-03-08  Paul Brook  <paul@codesourcery.com>
+
+	gcc/
+	* doc/invoke.texi: Document ARM -mcpu=cortex-m4.
+	* config/arm/arm.c (all_architectures): Change v7e-m default to
+	cortexm4.
+	* config/arm/arm-cores.def: Add cortex-m4.
+	* config/arm/arm-tune.md: Regenerate.
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2009-11-20 17:37:30 +0000
++++ new/gcc/config/arm/arm-cores.def	2010-07-29 15:53:39 +0000
+@@ -123,6 +123,7 @@
+ ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, 9e)
++ARM_CORE("cortex-m4",	  cortexm4,	7EM,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, 9e)
+
+=== modified file 'gcc/config/arm/arm-tune.md'
+--- old/gcc/config/arm/arm-tune.md	2009-11-20 17:37:30 +0000
++++ new/gcc/config/arm/arm-tune.md	2010-07-29 15:53:39 +0000
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from arm-cores.def
+ (define_attr "tune"
+-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0"
++	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-04-02 07:32:00 +0000
++++ new/gcc/config/arm/arm.c	2010-07-29 15:53:39 +0000
+@@ -782,7 +782,7 @@
+   {"armv7-a", cortexa8,	  "7A",	 FL_CO_PROC |		  FL_FOR_ARCH7A, NULL},
+   {"armv7-r", cortexr4,	  "7R",	 FL_CO_PROC |		  FL_FOR_ARCH7R, NULL},
+   {"armv7-m", cortexm3,	  "7M",	 FL_CO_PROC |		  FL_FOR_ARCH7M, NULL},
+-  {"armv7e-m",   cortexm3, "7EM", FL_CO_PROC |		  FL_FOR_ARCH7EM, NULL},
++  {"armv7e-m", cortexm4,  "7EM", FL_CO_PROC |		  FL_FOR_ARCH7EM, NULL},
+   {"ep9312",  ep9312,     "4T",  FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
+   {"iwmmxt",  iwmmxt,     "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
+   {"iwmmxt2", iwmmxt2,     "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-07-29 14:59:35 +0000
++++ new/gcc/doc/invoke.texi	2010-07-29 15:53:39 +0000
+@@ -9826,7 +9826,7 @@
+ @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
+ @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
+ @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9},
+-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
++@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3},
+ @samp{cortex-m1},
+ @samp{cortex-m0},
+ @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch
new file mode 100644
index 0000000000..ae417a18f5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch
@@ -0,0 +1,3094 @@
+2010-07-08  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from upstream (originally from Sourcery G++ 4.4):
+
+	2010-07-02  Sandra Loosemore  <sandra@codesourcery.com>
+
+	gcc/
+	* config/arm/neon.md (vec_extractv2di): Correct error in register
+	numbering to reconcile with neon_vget_lanev2di.
+
+	2010-07-02  Sandra Loosemore  <sandra@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL
+	instead of an unspec.
+	(neon_expand_vector_init): Likewise.
+	* config/arm/neon.md (UNSPEC_VCOMBINE): Delete.
+	(UNSPEC_VDUP_LANE): Delete.
+	(UNSPEC VDUP_N): Delete.
+	(UNSPEC_VGET_HIGH): Delete.
+	(UNSPEC_VGET_LANE): Delete.
+	(UNSPEC_VGET_LOW): Delete.
+	(UNSPEC_VMVN): Delete.
+	(UNSPEC_VSET_LANE): Delete.
+	(V_double_vector_mode): New.
+	(vec_set<mode>_internal): Make code emitted match that for the
+	corresponding intrinsics.
+	(vec_setv2di_internal): Likewise.
+	(neon_vget_lanedi): Rewrite to expand into emit_move_insn.
+	(neon_vget_lanev2di): Rewrite to expand into vec_extractv2di.
+	(neon_vset_lane<mode>): Combine double and quad patterns and
+	expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE.
+	(neon_vset_lanedi): Rewrite to expand into emit_move_insn.
+	(neon_vdup_n<mode>): Rewrite RTL without unspec.
+	(neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn.
+	(neon_vdup_nv2di): Rewrite RTL without unspec and merge with
+	with neon_vdup_lanev2di, adjusting the pattern from the latter
+	to be predicable for consistency.
+	(neon_vdup_lane<mode>_internal): New.
+	(neon_vdup_lane<mode>): Turn into a define_expand and rewrite
+	to avoid using an unspec.
+	(neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec.
+	(neon_vdup_lanev2di): Turn into a define_expand.
+	(neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE.
+	(neon_vget_high<mode>): Replace with....
+	(neon_vget_highv16qi): New pattern using canonical RTL.
+	(neon_vget_highv8hi): Likewise.
+	(neon_vget_highv4si): Likewise.
+	(neon_vget_highv4sf): Likewise.
+	(neon_vget_highv2di): Likewise.
+	(neon_vget_low<mode>): Replace with....
+	(neon_vget_lowv16qi): New pattern using canonical RTL.
+	(neon_vget_lowv8hi): Likewise.
+	(neon_vget_lowv4si): Likewise.
+	(neon_vget_lowv4sf): Likewise.
+	(neon_vget_lowv2di): Likewise.
+
+	* config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress
+	test for this emitting vmov.
+	(Vset_lane): Likewise.
+	(Vdup_n): Likewise.
+	(Vmov_n): Likewise.
+
+	* doc/arm-neon-intrinsics.texi: Regenerated.
+
+	gcc/testsuite/
+	* gcc.target/arm/neon/vdup_ns64.c: Regenerated.
+	* gcc.target/arm/neon/vdup_nu64.c: Regenerated.
+	* gcc.target/arm/neon/vdupQ_ns64.c: Regenerated.
+	* gcc.target/arm/neon/vdupQ_nu64.c: Regenerated.
+	* gcc.target/arm/neon/vmov_ns64.c: Regenerated.
+	* gcc.target/arm/neon/vmov_nu64.c: Regenerated.
+	* gcc.target/arm/neon/vmovQ_ns64.c: Regenerated.
+	* gcc.target/arm/neon/vmovQ_nu64.c: Regenerated.
+	* gcc.target/arm/neon/vget_lanes64.c: Regenerated.
+	* gcc.target/arm/neon/vget_laneu64.c: Regenerated.
+	* gcc.target/arm/neon/vset_lanes64.c: Regenerated.
+	* gcc.target/arm/neon/vset_laneu64.c: Regenerated.
+	* gcc.target/arm/neon-vdup_ns64.c: New.
+	* gcc.target/arm/neon-vdup_nu64.c: New.
+	* gcc.target/arm/neon-vdupQ_ns64.c: New.
+	* gcc.target/arm/neon-vdupQ_nu64.c: New.
+	* gcc.target/arm/neon-vdupQ_lanes64.c: New.
+	* gcc.target/arm/neon-vdupQ_laneu64.c: New.
+	* gcc.target/arm/neon-vmov_ns64.c: New.
+	* gcc.target/arm/neon-vmov_nu64.c: New.
+	* gcc.target/arm/neon-vmovQ_ns64.c: New.
+	* gcc.target/arm/neon-vmovQ_nu64.c: New.
+	* gcc.target/arm/neon-vget_lanes64.c: New.
+	* gcc.target/arm/neon-vget_laneu64.c: New.
+	* gcc.target/arm/neon-vset_lanes64.c: New.
+	* gcc.target/arm/neon-vset_laneu64.c: New.
+
+	2010-07-02  Sandra Loosemore  <sandra@codesourcery.com>
+		    Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/neon.md (UNSPEC_VABA): Delete.
+	(UNSPEC_VABAL): Delete.
+	(UNSPEC_VABS): Delete.
+	(UNSPEC_VMUL_N): Delete.
+	(adddi3_neon): New.
+	(subdi3_neon): New.
+	(mul<mode>3add<mode>_neon): Make the pattern named.
+	(mul<mode>3neg<mode>add<mode>_neon): Likewise.
+	(neon_vadd<mode>): Replace with define_expand, and move the remaining
+	unspec parts...
+	(neon_vadd<mode>_unspec): ...to this.
+	(neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise.
+	(neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise.
+	(neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise.
+	(neon_vaba<mode>): Rewrite in terms of vabd.
+	(neon_vabal<mode>): Rewrite in terms of vabdl.
+	(neon_vabs<mode>): Rewrite without unspec.
+	* config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON.
+	(*arm_subdi3): Likewise.
+	* config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add
+	No_op attribute to disable assembly output checks.
+	* config/arm/arm_neon.h: Regenerated.
+	* doc/arm-neon-intrinsics.texi: Regenerated.
+
+	gcc/testsuite/
+	* gcc.target/arm/neon/vadds64.c: Regenerated.
+	* gcc.target/arm/neon/vaddu64.c: Regenerated.
+	* gcc.target/arm/neon/vsubs64.c: Regenerated.
+	* gcc.target/arm/neon/vsubu64.c: Regenerated.
+	* gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options.
+	* gcc.target/arm/neon-vmls-1.c: Likewise.
+	* gcc.target/arm/neon-vsubs64.c: New execution test.
+	* gcc.target/arm/neon-vsubu64.c: New execution test.
+	* gcc.target/arm/neon-vadds64.c: New execution test.
+	* gcc.target/arm/neon-vaddu64.c: New execution test.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-07-29 15:53:39 +0000
++++ new/gcc/config/arm/arm.c	2010-07-29 15:59:12 +0000
+@@ -8110,8 +8110,7 @@
+      load.  */
+ 
+   x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
+-  return gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
+-			 UNSPEC_VDUP_N);
++  return gen_rtx_VEC_DUPLICATE (mode, x);
+ }
+ 
+ /* Generate code to load VALS, which is a PARALLEL containing only
+@@ -8207,8 +8206,7 @@
+     {
+       x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
+       emit_insn (gen_rtx_SET (VOIDmode, target,
+-			      gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
+-					      UNSPEC_VDUP_N)));
++			      gen_rtx_VEC_DUPLICATE (mode, x)));
+       return;
+     }
+ 
+@@ -8217,7 +8215,7 @@
+   if (n_var == 1)
+     {
+       rtx copy = copy_rtx (vals);
+-      rtvec ops;
++      rtx index = GEN_INT (one_var);
+ 
+       /* Load constant part of vector, substitute neighboring value for
+ 	 varying element.  */
+@@ -8226,9 +8224,38 @@
+ 
+       /* Insert variable.  */
+       x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
+-      ops = gen_rtvec (3, x, target, GEN_INT (one_var));
+-      emit_insn (gen_rtx_SET (VOIDmode, target,
+-			      gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE)));
++      switch (mode)
++	{
++	case V8QImode:
++	  emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
++	  break;
++	case V16QImode:
++	  emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
++	  break;
++	case V4HImode:
++	  emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
++	  break;
++	case V8HImode:
++	  emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
++	  break;
++	case V2SImode:
++	  emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
++	  break;
++	case V4SImode:
++	  emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
++	  break;
++	case V2SFmode:
++	  emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
++	  break;
++	case V4SFmode:
++	  emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
++	  break;
++	case V2DImode:
++	  emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
++	  break;
++	default:
++	  gcc_unreachable ();
++	}
+       return;
+     }
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-04-02 18:54:46 +0000
++++ new/gcc/config/arm/arm.md	2010-07-29 15:59:12 +0000
+@@ -497,9 +497,10 @@
+ 	(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
+ 		 (match_operand:DI 2 "s_register_operand" "r,  0")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
+   "#"
+-  "TARGET_32BIT && reload_completed"
++  "TARGET_32BIT && reload_completed
++   && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"
+   [(parallel [(set (reg:CC_C CC_REGNUM)
+ 		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
+ 				 (match_dup 1)))
+@@ -997,7 +998,7 @@
+ 	(minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0")
+ 		  (match_operand:DI 2 "s_register_operand" "r,0,0")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_32BIT"
++  "TARGET_32BIT && !TARGET_NEON"
+   "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
+   [(set_attr "conds" "clob")
+    (set_attr "length" "8")]
+@@ -1784,6 +1785,7 @@
+ 	  [(match_operand:DI 1 "s_register_operand" "")
+ 	   (match_operand:DI 2 "s_register_operand" "")]))]
+   "TARGET_32BIT && reload_completed
++   && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
+    && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
+   [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
+    (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
+@@ -1857,11 +1859,19 @@
+   }"
+ )
+ 
+-(define_insn "anddi3"
++(define_expand "anddi3"
++  [(set (match_operand:DI         0 "s_register_operand" "")
++	(and:DI (match_operand:DI 1 "s_register_operand" "")
++		(match_operand:DI 2 "neon_inv_logic_op2" "")))]
++  "TARGET_32BIT"
++  ""
++)
++
++(define_insn "*anddi3_insn"
+   [(set (match_operand:DI         0 "s_register_operand" "=&r,&r")
+ 	(and:DI (match_operand:DI 1 "s_register_operand"  "%0,r")
+ 		(match_operand:DI 2 "s_register_operand"   "r,r")))]
+-  "TARGET_32BIT && ! TARGET_IWMMXT"
++  "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
+   "#"
+   [(set_attr "length" "8")]
+ )
+@@ -2461,7 +2471,9 @@
+ 		(match_operand:DI 2 "s_register_operand" "r,0")))]
+   "TARGET_32BIT"
+   "#"
+-  "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
++  "TARGET_32BIT && reload_completed
++   && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
++   && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
+   [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2)))
+    (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))]
+   "
+@@ -2585,11 +2597,19 @@
+   [(set_attr "conds" "set")]
+ )
+ 
+-(define_insn "iordi3"
++(define_expand "iordi3"
++  [(set (match_operand:DI         0 "s_register_operand" "")
++	(ior:DI (match_operand:DI 1 "s_register_operand" "")
++		(match_operand:DI 2 "neon_logic_op2" "")))]
++  "TARGET_32BIT"
++  ""
++)
++
++(define_insn "*iordi3_insn"
+   [(set (match_operand:DI         0 "s_register_operand" "=&r,&r")
+ 	(ior:DI (match_operand:DI 1 "s_register_operand"  "%0,r")
+ 		(match_operand:DI 2 "s_register_operand"   "r,r")))]
+-  "TARGET_32BIT && ! TARGET_IWMMXT"
++  "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
+   "#"
+   [(set_attr "length" "8")
+    (set_attr "predicable" "yes")]
+@@ -2715,11 +2735,19 @@
+   [(set_attr "conds" "set")]
+ )
+ 
+-(define_insn "xordi3"
++(define_expand "xordi3"
++  [(set (match_operand:DI         0 "s_register_operand" "")
++	(xor:DI (match_operand:DI 1 "s_register_operand" "")
++		(match_operand:DI 2 "s_register_operand" "")))]
++  "TARGET_32BIT"
++  ""
++)
++
++(define_insn "*xordi3_insn"
+   [(set (match_operand:DI         0 "s_register_operand" "=&r,&r")
+ 	(xor:DI (match_operand:DI 1 "s_register_operand"  "%0,r")
+ 		(match_operand:DI 2 "s_register_operand"   "r,r")))]
+-  "TARGET_32BIT && !TARGET_IWMMXT"
++  "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
+   "#"
+   [(set_attr "length" "8")
+    (set_attr "predicable" "yes")]
+
+=== modified file 'gcc/config/arm/arm_neon.h'
+--- old/gcc/config/arm/arm_neon.h	2009-11-03 17:58:59 +0000
++++ new/gcc/config/arm/arm_neon.h	2010-07-29 15:59:12 +0000
+@@ -414,12 +414,6 @@
+   return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vadd_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+ vadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+@@ -444,6 +438,12 @@
+   return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vadd_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ vadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+@@ -1368,12 +1368,6 @@
+   return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsub_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+ vsub_f32 (float32x2_t __a, float32x2_t __b)
+ {
+@@ -1398,6 +1392,12 @@
+   return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vsub_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ vsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+@@ -5808,12 +5808,6 @@
+   return (int32x2_t)__builtin_neon_vget_lowv4si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vget_low_s64 (int64x2_t __a)
+-{
+-  return (int64x1_t)__builtin_neon_vget_lowv2di (__a);
+-}
+-
+ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+ vget_low_f32 (float32x4_t __a)
+ {
+@@ -5838,12 +5832,6 @@
+   return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vget_low_u64 (uint64x2_t __a)
+-{
+-  return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
+-}
+-
+ __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+ vget_low_p8 (poly8x16_t __a)
+ {
+@@ -5856,6 +5844,18 @@
+   return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vget_low_s64 (int64x2_t __a)
++{
++  return (int64x1_t)__builtin_neon_vget_lowv2di (__a);
++}
++
++__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++vget_low_u64 (uint64x2_t __a)
++{
++  return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
++}
++
+ __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+ vcvt_s32_f32 (float32x2_t __a)
+ {
+@@ -10386,12 +10386,6 @@
+   return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vand_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+ vand_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+@@ -10410,6 +10404,12 @@
+   return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vand_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ vand_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+@@ -10482,12 +10482,6 @@
+   return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vorr_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+ vorr_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+@@ -10506,6 +10500,12 @@
+   return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vorr_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ vorr_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+@@ -10578,12 +10578,6 @@
+   return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-veor_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_veordi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+ veor_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+@@ -10602,6 +10596,12 @@
+   return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++veor_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_veordi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ veor_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+@@ -10674,12 +10674,6 @@
+   return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vbic_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+ vbic_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+@@ -10698,6 +10692,12 @@
+   return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vbic_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ vbic_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+@@ -10770,12 +10770,6 @@
+   return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vorn_s64 (int64x1_t __a, int64x1_t __b)
+-{
+-  return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1);
+-}
+-
+ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+ vorn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+@@ -10794,6 +10788,12 @@
+   return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
+ }
+ 
++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++vorn_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1);
++}
++
+ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+ vorn_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2009-11-11 14:23:03 +0000
++++ new/gcc/config/arm/neon.md	2010-07-29 15:59:12 +0000
+@@ -22,17 +22,12 @@
+ (define_constants
+   [(UNSPEC_ASHIFT_SIGNED	65)
+    (UNSPEC_ASHIFT_UNSIGNED	66)
+-   (UNSPEC_VABA			67)
+-   (UNSPEC_VABAL		68)
+    (UNSPEC_VABD			69)
+    (UNSPEC_VABDL		70)
+-   (UNSPEC_VABS			71)
+    (UNSPEC_VADD			72)
+    (UNSPEC_VADDHN		73)
+    (UNSPEC_VADDL		74)
+    (UNSPEC_VADDW		75)
+-   (UNSPEC_VAND			76)
+-   (UNSPEC_VBIC			77)
+    (UNSPEC_VBSL			78)
+    (UNSPEC_VCAGE		79)
+    (UNSPEC_VCAGT		80)
+@@ -40,18 +35,9 @@
+    (UNSPEC_VCGE			82)
+    (UNSPEC_VCGT			83)
+    (UNSPEC_VCLS			84)
+-   (UNSPEC_VCLZ			85)
+-   (UNSPEC_VCNT			86)
+-   (UNSPEC_VCOMBINE		87)
+    (UNSPEC_VCVT			88)
+    (UNSPEC_VCVT_N		89)
+-   (UNSPEC_VDUP_LANE		90)
+-   (UNSPEC_VDUP_N		91)
+-   (UNSPEC_VEOR			92)
+    (UNSPEC_VEXT			93)
+-   (UNSPEC_VGET_HIGH		94)
+-   (UNSPEC_VGET_LANE		95)
+-   (UNSPEC_VGET_LOW		96)
+    (UNSPEC_VHADD		97)
+    (UNSPEC_VHSUB		98)
+    (UNSPEC_VLD1			99)
+@@ -86,10 +72,6 @@
+    (UNSPEC_VMULL		128)
+    (UNSPEC_VMUL_LANE		129)
+    (UNSPEC_VMULL_LANE		130)
+-   (UNSPEC_VMUL_N		131)
+-   (UNSPEC_VMVN			132)
+-   (UNSPEC_VORN			133)
+-   (UNSPEC_VORR			134)
+    (UNSPEC_VPADAL		135)
+    (UNSPEC_VPADD		136)
+    (UNSPEC_VPADDL		137)
+@@ -125,7 +107,6 @@
+    (UNSPEC_VREV64		167)
+    (UNSPEC_VRSQRTE		168)
+    (UNSPEC_VRSQRTS		169)
+-   (UNSPEC_VSET_LANE		170)
+    (UNSPEC_VSHL			171)
+    (UNSPEC_VSHLL_N		172)
+    (UNSPEC_VSHL_N		173)
+@@ -335,6 +316,14 @@
+ 				  (V4HI "V2SI") (V8HI "V4SI")
+ 				  (V2SI "DI")   (V4SI "V2DI")])
+ 
++;; Double-sized modes with the same element size.
++;; Used for neon_vdup_lane, where the second operand is double-sized
++;; even when the first one is quad.
++(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
++                                        (V4SI "V2SI") (V4SF "V2SF")
++                                        (V8QI "V8QI") (V4HI "V4HI")
++                                        (V2SI "V2SI") (V2SF "V2SF")])
++
+ ;; Mode of result of comparison operations (and bit-select operand 1).
+ (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
+ 			        (V4HI "V4HI") (V8HI  "V8HI")
+@@ -688,7 +677,7 @@
+     elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
+   operands[2] = GEN_INT (elt);
+   
+-  return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
++  return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
+ }
+   [(set_attr "predicable" "yes")
+    (set_attr "neon_type" "neon_mcr")])
+@@ -714,7 +703,7 @@
+   operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
+   operands[2] = GEN_INT (elt);
+ 
+-  return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
++  return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
+ }
+   [(set_attr "predicable" "yes")
+    (set_attr "neon_type" "neon_mcr")]
+@@ -734,7 +723,7 @@
+ 
+   operands[0] = gen_rtx_REG (DImode, regno);
+ 
+-  return "vmov%?.64\t%P0, %Q1, %R1";
++  return "vmov%?\t%P0, %Q1, %R1";
+ }
+   [(set_attr "predicable" "yes")
+    (set_attr "neon_type" "neon_mcr_2_mcrr")]
+@@ -802,11 +791,11 @@
+           (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[1]) + INTVAL (operands[2]);
++  int regno = REGNO (operands[1]) + 2 * INTVAL (operands[2]);
+ 
+   operands[1] = gen_rtx_REG (DImode, regno);
+ 
+-  return "vmov%?.64\t%Q0, %R0, %P1";
++  return "vmov%?\t%Q0, %R0, %P1  @ v2di";
+ }
+   [(set_attr "predicable" "yes")
+    (set_attr "neon_type" "neon_int_1")]
+@@ -823,11 +812,8 @@
+ 
+ ;; Doubleword and quadword arithmetic.
+ 
+-;; NOTE: vadd/vsub and some other instructions also support 64-bit integer
+-;; element size, which we could potentially use for "long long" operations. We
+-;; don't want to do this at present though, because moving values from the
+-;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is
+-;; easy to do with ARM instructions anyway.
++;; NOTE: some other instructions also support 64-bit integer
++;; element size, which we could potentially use for "long long" operations.
+ 
+ (define_insn "*add<mode>3_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+@@ -843,6 +829,26 @@
+                     (const_string "neon_int_1")))]
+ )
+ 
++(define_insn "adddi3_neon"
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
++        (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0")
++                 (match_operand:DI 2 "s_register_operand" "w,r,0")))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_NEON"
++{
++  switch (which_alternative)
++    {
++    case 0: return "vadd.i64\t%P0, %P1, %P2";
++    case 1: return "#";
++    case 2: return "#";
++    default: gcc_unreachable ();
++    }
++}
++  [(set_attr "neon_type" "neon_int_1,*,*")
++   (set_attr "conds" "*,clob,clob")
++   (set_attr "length" "*,8,8")]
++)
++
+ (define_insn "*sub<mode>3_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+@@ -857,6 +863,27 @@
+                     (const_string "neon_int_2")))]
+ )
+ 
++(define_insn "subdi3_neon"
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
++        (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0")
++                  (match_operand:DI 2 "s_register_operand" "w,r,0,0")))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_NEON"
++{
++  switch (which_alternative)
++    {
++    case 0: return "vsub.i64\t%P0, %P1, %P2";
++    case 1: /* fall through */ 
++    case 2: /* fall through */
++    case 3: return  "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
++    default: gcc_unreachable ();
++    }
++}
++  [(set_attr "neon_type" "neon_int_2,*,*,*")
++   (set_attr "conds" "*,clob,clob,clob")
++   (set_attr "length" "*,8,8,8")]
++)
++
+ (define_insn "*mul<mode>3_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+@@ -878,7 +905,7 @@
+                                     (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
+ )
+ 
+-(define_insn "*mul<mode>3add<mode>_neon"
++(define_insn "mul<mode>3add<mode>_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
+                             (match_operand:VDQ 3 "s_register_operand" "w"))
+@@ -900,7 +927,7 @@
+                                     (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
+ )
+ 
+-(define_insn "*mul<mode>3neg<mode>add<mode>_neon"
++(define_insn "mul<mode>3neg<mode>add<mode>_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
+                    (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
+@@ -940,10 +967,9 @@
+ )
+ 
+ (define_insn "iordi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0")
+-		    (match_operand:DI 2 "neon_logic_op2" "w,Dl")]
+-                    UNSPEC_VORR))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
++        (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
++		(match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))]
+   "TARGET_NEON"
+ {
+   switch (which_alternative)
+@@ -951,10 +977,13 @@
+     case 0: return "vorr\t%P0, %P1, %P2";
+     case 1: return neon_output_logic_immediate ("vorr", &operands[2],
+ 		     DImode, 0, VALID_NEON_QREG_MODE (DImode));
++    case 2: return "#";
++    case 3: return "#";
+     default: gcc_unreachable ();
+     }
+ }
+-  [(set_attr "neon_type" "neon_int_1")]
++  [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
++   (set_attr "length" "*,*,8,8")]
+ )
+ 
+ ;; The concrete forms of the Neon immediate-logic instructions are vbic and
+@@ -980,10 +1009,9 @@
+ )
+ 
+ (define_insn "anddi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0")
+-		    (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")]
+-                    UNSPEC_VAND))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
++        (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
++		(match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))]
+   "TARGET_NEON"
+ {
+   switch (which_alternative)
+@@ -991,10 +1019,13 @@
+     case 0: return "vand\t%P0, %P1, %P2";
+     case 1: return neon_output_logic_immediate ("vand", &operands[2],
+     		     DImode, 1, VALID_NEON_QREG_MODE (DImode));
++    case 2: return "#";
++    case 3: return "#";
+     default: gcc_unreachable ();
+     }
+ }
+-  [(set_attr "neon_type" "neon_int_1")]
++  [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
++   (set_attr "length" "*,*,8,8")]
+ )
+ 
+ (define_insn "orn<mode>3_neon"
+@@ -1007,13 +1038,16 @@
+ )
+ 
+ (define_insn "orndi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
+-		    (match_operand:DI 2 "s_register_operand" "w")]
+-                    UNSPEC_VORN))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
++	(ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0")
++	         (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))]
+   "TARGET_NEON"
+-  "vorn\t%P0, %P1, %P2"
+-  [(set_attr "neon_type" "neon_int_1")]
++  "@
++   vorn\t%P0, %P1, %P2
++   #
++   #"
++  [(set_attr "neon_type" "neon_int_1,*,*")
++   (set_attr "length" "*,8,8")]
+ )
+ 
+ (define_insn "bic<mode>3_neon"
+@@ -1025,14 +1059,18 @@
+   [(set_attr "neon_type" "neon_int_1")]
+ )
+ 
++;; Compare to *anddi_notdi_di.
+ (define_insn "bicdi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
+-		     (match_operand:DI 2 "s_register_operand" "w")]
+-                    UNSPEC_VBIC))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
++        (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0"))
++		(match_operand:DI 1 "s_register_operand" "w,0,r")))]
+   "TARGET_NEON"
+-  "vbic\t%P0, %P1, %P2"
+-  [(set_attr "neon_type" "neon_int_1")]
++  "@
++   vbic\t%P0, %P1, %P2
++   #
++   #"
++  [(set_attr "neon_type" "neon_int_1,*,*")
++   (set_attr "length" "*,8,8")]
+ )
+ 
+ (define_insn "xor<mode>3"
+@@ -1045,13 +1083,16 @@
+ )
+ 
+ (define_insn "xordi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
+-		     (match_operand:DI 2 "s_register_operand" "w")]
+-                    UNSPEC_VEOR))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
++        (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r")
++	        (match_operand:DI 2 "s_register_operand" "w,r,r")))]
+   "TARGET_NEON"
+-  "veor\t%P0, %P1, %P2"
+-  [(set_attr "neon_type" "neon_int_1")]
++  "@
++   veor\t%P0, %P1, %P2
++   #
++   #"
++  [(set_attr "neon_type" "neon_int_1,*,*")
++   (set_attr "length" "*,8,8")]
+ )
+ 
+ (define_insn "one_cmpl<mode>2"
+@@ -1711,11 +1752,37 @@
+ 
+ ; good for plain vadd, vaddq.
+ 
+-(define_insn "neon_vadd<mode>"
++(define_expand "neon_vadd<mode>"
++  [(match_operand:VDQX 0 "s_register_operand" "=w")
++   (match_operand:VDQX 1 "s_register_operand" "w")
++   (match_operand:VDQX 2 "s_register_operand" "w")
++   (match_operand:SI 3 "immediate_operand" "i")]
++  "TARGET_NEON"
++{
++  if (!<Is_float_mode> || flag_unsafe_math_optimizations)
++    emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (gen_neon_vadd<mode>_unspec (operands[0], operands[1],
++					   operands[2]));
++  DONE;
++})
++
++; Note that NEON operations don't support the full IEEE 754 standard: in
++; particular, denormal values are flushed to zero.  This means that GCC cannot
++; use those instructions for autovectorization, etc. unless
++; -funsafe-math-optimizations is in effect (in which case flush-to-zero
++; behaviour is permissible).  Intrinsic operations (provided by the arm_neon.h
++; header) must work in either case: if -funsafe-math-optimizations is given,
++; intrinsics expand to "canonical" RTL where possible, otherwise intrinsics
++; expand to unspecs (which may potentially limit the extent to which they might
++; be optimized by generic code).
++
++; Used for intrinsics when flag_unsafe_math_optimizations is false.
++
++(define_insn "neon_vadd<mode>_unspec"
+   [(set (match_operand:VDQX 0 "s_register_operand" "=w")
+         (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
+-		      (match_operand:VDQX 2 "s_register_operand" "w")
+-                      (match_operand:SI 3 "immediate_operand" "i")]
++		      (match_operand:VDQX 2 "s_register_operand" "w")]
+                      UNSPEC_VADD))]
+   "TARGET_NEON"
+   "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+@@ -1788,6 +1855,8 @@
+   [(set_attr "neon_type" "neon_int_4")]
+ )
+ 
++;; We cannot replace this unspec with mul<mode>3 because of the odd 
++;; polynomial multiplication case that can specified by operand 3.
+ (define_insn "neon_vmul<mode>"
+   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+         (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
+@@ -1811,13 +1880,31 @@
+                                     (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
+ )
+ 
+-(define_insn "neon_vmla<mode>"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-		      (match_operand:VDQW 2 "s_register_operand" "w")
+-		      (match_operand:VDQW 3 "s_register_operand" "w")
+-                     (match_operand:SI 4 "immediate_operand" "i")]
+-                    UNSPEC_VMLA))]
++(define_expand "neon_vmla<mode>"
++  [(match_operand:VDQW 0 "s_register_operand" "=w")
++   (match_operand:VDQW 1 "s_register_operand" "0")
++   (match_operand:VDQW 2 "s_register_operand" "w")
++   (match_operand:VDQW 3 "s_register_operand" "w")
++   (match_operand:SI 4 "immediate_operand" "i")]
++  "TARGET_NEON"
++{
++  if (!<Is_float_mode> || flag_unsafe_math_optimizations)
++    emit_insn (gen_mul<mode>3add<mode>_neon (operands[0], operands[1],
++				             operands[2], operands[3]));
++  else
++    emit_insn (gen_neon_vmla<mode>_unspec (operands[0], operands[1],
++					   operands[2], operands[3]));
++  DONE;
++})
++
++; Used for intrinsics when flag_unsafe_math_optimizations is false.
++
++(define_insn "neon_vmla<mode>_unspec"
++  [(set (match_operand:VDQ 0 "s_register_operand" "=w")
++	(unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0")
++		     (match_operand:VDQ 2 "s_register_operand" "w")
++		     (match_operand:VDQ 3 "s_register_operand" "w")]
++		    UNSPEC_VMLA))]
+   "TARGET_NEON"
+   "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+   [(set (attr "neon_type")
+@@ -1850,13 +1937,31 @@
+                    (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
+ )
+ 
+-(define_insn "neon_vmls<mode>"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-		      (match_operand:VDQW 2 "s_register_operand" "w")
+-		      (match_operand:VDQW 3 "s_register_operand" "w")
+-                     (match_operand:SI 4 "immediate_operand" "i")]
+-                    UNSPEC_VMLS))]
++(define_expand "neon_vmls<mode>"
++  [(match_operand:VDQW 0 "s_register_operand" "=w")
++   (match_operand:VDQW 1 "s_register_operand" "0")
++   (match_operand:VDQW 2 "s_register_operand" "w")
++   (match_operand:VDQW 3 "s_register_operand" "w")
++   (match_operand:SI 4 "immediate_operand" "i")]
++  "TARGET_NEON"
++{
++  if (!<Is_float_mode> || flag_unsafe_math_optimizations)
++    emit_insn (gen_mul<mode>3neg<mode>add<mode>_neon (operands[0],
++		 operands[1], operands[2], operands[3]));
++  else
++    emit_insn (gen_neon_vmls<mode>_unspec (operands[0], operands[1],
++					   operands[2], operands[3]));
++  DONE;
++})
++
++; Used for intrinsics when flag_unsafe_math_optimizations is false.
++
++(define_insn "neon_vmls<mode>_unspec"
++  [(set (match_operand:VDQ 0 "s_register_operand" "=w")
++	(unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0")
++		     (match_operand:VDQ 2 "s_register_operand" "w")
++		     (match_operand:VDQ 3 "s_register_operand" "w")]
++		    UNSPEC_VMLS))]
+   "TARGET_NEON"
+   "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+   [(set (attr "neon_type")
+@@ -1966,11 +2071,27 @@
+                    (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
+ )
+ 
+-(define_insn "neon_vsub<mode>"
++(define_expand "neon_vsub<mode>"
++  [(match_operand:VDQX 0 "s_register_operand" "=w")
++   (match_operand:VDQX 1 "s_register_operand" "w")
++   (match_operand:VDQX 2 "s_register_operand" "w")
++   (match_operand:SI 3 "immediate_operand" "i")]
++  "TARGET_NEON"
++{
++  if (!<Is_float_mode> || flag_unsafe_math_optimizations)
++    emit_insn (gen_sub<mode>3 (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (gen_neon_vsub<mode>_unspec (operands[0], operands[1],
++					   operands[2]));
++  DONE;
++})
++
++; Used for intrinsics when flag_unsafe_math_optimizations is false.
++
++(define_insn "neon_vsub<mode>_unspec"
+   [(set (match_operand:VDQX 0 "s_register_operand" "=w")
+         (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
+-		      (match_operand:VDQX 2 "s_register_operand" "w")
+-                      (match_operand:SI 3 "immediate_operand" "i")]
++		      (match_operand:VDQX 2 "s_register_operand" "w")]
+                      UNSPEC_VSUB))]
+   "TARGET_NEON"
+   "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+@@ -2153,11 +2274,11 @@
+ 
+ (define_insn "neon_vaba<mode>"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+-        (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0")
+-		       (match_operand:VDQIW 2 "s_register_operand" "w")
+-		       (match_operand:VDQIW 3 "s_register_operand" "w")
+-                       (match_operand:SI 4 "immediate_operand" "i")]
+-		      UNSPEC_VABA))]
++        (plus:VDQIW (match_operand:VDQIW 1 "s_register_operand" "0")
++                    (unspec:VDQIW [(match_operand:VDQIW 2 "s_register_operand" "w")
++		                   (match_operand:VDQIW 3 "s_register_operand" "w")
++                                   (match_operand:SI 4 "immediate_operand" "i")]
++		                  UNSPEC_VABD)))]
+   "TARGET_NEON"
+   "vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+   [(set (attr "neon_type")
+@@ -2167,11 +2288,11 @@
+ 
+ (define_insn "neon_vabal<mode>"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+-        (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
+-		           (match_operand:VW 2 "s_register_operand" "w")
+-		           (match_operand:VW 3 "s_register_operand" "w")
+-                           (match_operand:SI 4 "immediate_operand" "i")]
+-                          UNSPEC_VABAL))]
++        (plus:<V_widen> (match_operand:<V_widen> 1 "s_register_operand" "0")
++                        (unspec:<V_widen> [(match_operand:VW 2 "s_register_operand" "w")
++                                           (match_operand:VW 3 "s_register_operand" "w")
++                                           (match_operand:SI 4 "immediate_operand" "i")]
++                          UNSPEC_VABDL)))]
+   "TARGET_NEON"
+   "vabal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
+   [(set_attr "neon_type" "neon_vaba")]
+@@ -2302,22 +2423,15 @@
+                     (const_string "neon_fp_vrecps_vrsqrts_qqq")))]
+ )
+ 
+-(define_insn "neon_vabs<mode>"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+-	(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
+-		      (match_operand:SI 2 "immediate_operand" "i")]
+-                     UNSPEC_VABS))]
++(define_expand "neon_vabs<mode>"
++  [(match_operand:VDQW 0 "s_register_operand" "")
++   (match_operand:VDQW 1 "s_register_operand" "")
++   (match_operand:SI 2 "immediate_operand" "")]
+   "TARGET_NEON"
+-  "vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
+-  [(set (attr "neon_type")
+-     (if_then_else (ior (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+-                        (ne (symbol_ref "<Is_float_mode>") (const_int 0)))
+-                   (if_then_else
+-                      (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+-                      (const_string "neon_fp_vadd_ddd_vabs_dd")
+-                      (const_string "neon_fp_vadd_qqq_vabs_qq"))
+-                   (const_string "neon_vqneg_vqabs")))]
+-)
++{
++  emit_insn (gen_abs<mode>2 (operands[0], operands[1]));
++  DONE;
++})
+ 
+ (define_insn "neon_vqabs<mode>"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+@@ -2359,26 +2473,42 @@
+   [(set_attr "neon_type" "neon_int_1")]
+ )
+ 
+-(define_insn "neon_vclz<mode>"
++(define_insn "clz<mode>2"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+-	(unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
+-		       (match_operand:SI 2 "immediate_operand" "i")]
+-		      UNSPEC_VCLZ))]
++        (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))]
+   "TARGET_NEON"
+   "vclz.<V_if_elem>\t%<V_reg>0, %<V_reg>1"
+   [(set_attr "neon_type" "neon_int_1")]
+ )
+ 
+-(define_insn "neon_vcnt<mode>"
++(define_expand "neon_vclz<mode>"
++  [(match_operand:VDQIW 0 "s_register_operand" "")
++   (match_operand:VDQIW 1 "s_register_operand" "")
++   (match_operand:SI 2 "immediate_operand" "")]
++  "TARGET_NEON"
++{
++  emit_insn (gen_clz<mode>2 (operands[0], operands[1]));
++  DONE;
++})
++
++(define_insn "popcount<mode>2"
+   [(set (match_operand:VE 0 "s_register_operand" "=w")
+-	(unspec:VE [(match_operand:VE 1 "s_register_operand" "w")
+-                    (match_operand:SI 2 "immediate_operand" "i")]
+-                   UNSPEC_VCNT))]
++        (popcount:VE (match_operand:VE 1 "s_register_operand" "w")))]
+   "TARGET_NEON"
+   "vcnt.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
+   [(set_attr "neon_type" "neon_int_1")]
+ )
+ 
++(define_expand "neon_vcnt<mode>"
++  [(match_operand:VE 0 "s_register_operand" "=w")
++   (match_operand:VE 1 "s_register_operand" "w")
++   (match_operand:SI 2 "immediate_operand" "i")]
++  "TARGET_NEON"
++{
++  emit_insn (gen_popcount<mode>2 (operands[0], operands[1]));
++  DONE;
++})
++
+ (define_insn "neon_vrecpe<mode>"
+   [(set (match_operand:V32 0 "s_register_operand" "=w")
+ 	(unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")
+@@ -2555,126 +2685,65 @@
+ ; Operand 3 (info word) is ignored because it does nothing useful with 64-bit
+ ; elements.
+ 
+-(define_insn "neon_vget_lanedi"
+-  [(set (match_operand:DI 0 "s_register_operand" "=r")
+-       (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
+-                   (match_operand:SI 2 "immediate_operand" "i")
+-                   (match_operand:SI 3 "immediate_operand" "i")]
+-                  UNSPEC_VGET_LANE))]
++(define_expand "neon_vget_lanedi"
++  [(match_operand:DI 0 "s_register_operand" "=r")
++   (match_operand:DI 1 "s_register_operand" "w")
++   (match_operand:SI 2 "immediate_operand" "i")
++   (match_operand:SI 3 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
+   neon_lane_bounds (operands[2], 0, 1);
+-  return "vmov%?\t%Q0, %R0, %P1  @ di";
+-}
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
++  emit_move_insn (operands[0], operands[1]);
++  DONE;
++})
+ 
+-(define_insn "neon_vget_lanev2di"
+-  [(set (match_operand:DI 0 "s_register_operand" "=r")
+-       (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w")
+-                   (match_operand:SI 2 "immediate_operand" "i")
+-                   (match_operand:SI 3 "immediate_operand" "i")]
+-                  UNSPEC_VGET_LANE))]
++(define_expand "neon_vget_lanev2di"
++  [(match_operand:DI 0 "s_register_operand" "=r")
++   (match_operand:V2DI 1 "s_register_operand" "w")
++   (match_operand:SI 2 "immediate_operand" "i")
++   (match_operand:SI 3 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
+-  rtx ops[2];
+-  unsigned int regno = REGNO (operands[1]);
+-  unsigned int elt = INTVAL (operands[2]);
+-
+   neon_lane_bounds (operands[2], 0, 2);
+-
+-  ops[0] = operands[0];
+-  ops[1] = gen_rtx_REG (DImode, regno + 2 * elt);
+-  output_asm_insn ("vmov%?\t%Q0, %R0, %P1  @ v2di", ops);
+-
+-  return "";
+-}
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vset_lane<mode>"
+-  [(set (match_operand:VD 0 "s_register_operand" "=w")
+-	(unspec:VD [(match_operand:<V_elem> 1 "s_register_operand" "r")
+-		    (match_operand:VD 2 "s_register_operand" "0")
+-                    (match_operand:SI 3 "immediate_operand" "i")]
+-                   UNSPEC_VSET_LANE))]
++  emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_expand "neon_vset_lane<mode>"
++  [(match_operand:VDQ 0 "s_register_operand" "=w")
++   (match_operand:<V_elem> 1 "s_register_operand" "r")
++   (match_operand:VDQ 2 "s_register_operand" "0")
++   (match_operand:SI 3 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
++  unsigned int elt = INTVAL (operands[3]);
+   neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
+-  return "vmov%?.<V_sz_elem>\t%P0[%c3], %1";
+-}
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
++
++  if (BYTES_BIG_ENDIAN)
++    {
++      unsigned int reg_nelts
++	= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
++      elt ^= reg_nelts - 1;
++    }
++
++  emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1],
++                                         GEN_INT (1 << elt), operands[2]));
++  DONE;
++})
+ 
+ ; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored.
+ 
+-(define_insn "neon_vset_lanedi"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "r")
+-		    (match_operand:DI 2 "s_register_operand" "0")
+-                    (match_operand:SI 3 "immediate_operand" "i")]
+-                   UNSPEC_VSET_LANE))]
++(define_expand "neon_vset_lanedi"
++  [(match_operand:DI 0 "s_register_operand" "=w")
++   (match_operand:DI 1 "s_register_operand" "r")
++   (match_operand:DI 2 "s_register_operand" "0")
++   (match_operand:SI 3 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
+   neon_lane_bounds (operands[3], 0, 1);
+-  return "vmov%?\t%P0, %Q1, %R1  @ di";
+-}
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vset_lane<mode>"
+-  [(set (match_operand:VQ 0 "s_register_operand" "=w")
+-	(unspec:VQ [(match_operand:<V_elem> 1 "s_register_operand" "r")
+-		    (match_operand:VQ 2 "s_register_operand" "0")
+-                    (match_operand:SI 3 "immediate_operand" "i")]
+-                   UNSPEC_VSET_LANE))]
+-  "TARGET_NEON"
+-{
+-  rtx ops[4];
+-  unsigned int regno = REGNO (operands[0]);
+-  unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2;
+-  unsigned int elt = INTVAL (operands[3]);
+-
+-  neon_lane_bounds (operands[3], 0, halfelts * 2);
+-
+-  ops[0] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
+-  ops[1] = operands[1];
+-  ops[2] = GEN_INT (elt % halfelts);
+-  output_asm_insn ("vmov%?.<V_sz_elem>\t%P0[%c2], %1", ops);
+-
+-  return "";
+-}
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vset_lanev2di"
+-  [(set (match_operand:V2DI 0 "s_register_operand" "=w")
+-	(unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")
+-		      (match_operand:V2DI 2 "s_register_operand" "0")
+-                      (match_operand:SI 3 "immediate_operand" "i")]
+-                   UNSPEC_VSET_LANE))]
+-  "TARGET_NEON"
+-{
+-  rtx ops[2];
+-  unsigned int regno = REGNO (operands[0]);
+-  unsigned int elt = INTVAL (operands[3]);
+-
+-  neon_lane_bounds (operands[3], 0, 2);
+-
+-  ops[0] = gen_rtx_REG (DImode, regno + 2 * elt);
+-  ops[1] = operands[1];
+-  output_asm_insn ("vmov%?\t%P0, %Q1, %R1  @ v2di", ops);
+-
+-  return "";
+-}
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
++  emit_move_insn (operands[0], operands[1]);
++  DONE;
++})
+ 
+ (define_expand "neon_vcreate<mode>"
+   [(match_operand:VDX 0 "s_register_operand" "")
+@@ -2688,8 +2757,7 @@
+ 
+ (define_insn "neon_vdup_n<mode>"
+   [(set (match_operand:VX 0 "s_register_operand" "=w")
+-	(unspec:VX [(match_operand:<V_elem> 1 "s_register_operand" "r")]
+-		   UNSPEC_VDUP_N))]
++        (vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))]
+   "TARGET_NEON"
+   "vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
+   ;; Assume this schedules like vmov.
+@@ -2699,8 +2767,7 @@
+ 
+ (define_insn "neon_vdup_n<mode>"
+   [(set (match_operand:V32 0 "s_register_operand" "=w,w")
+-	(unspec:V32 [(match_operand:<V_elem> 1 "s_register_operand" "r,t")]
+-		    UNSPEC_VDUP_N))]
++        (vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))]
+   "TARGET_NEON"
+   "@
+   vdup%?.<V_sz_elem>\t%<V_reg>0, %1
+@@ -2710,61 +2777,76 @@
+    (set_attr "neon_type" "neon_bp_simple")]
+ )
+ 
+-(define_insn "neon_vdup_ndi"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
+-                   UNSPEC_VDUP_N))]
++(define_expand "neon_vdup_ndi"
++  [(match_operand:DI 0 "s_register_operand" "=w")
++   (match_operand:DI 1 "s_register_operand" "r")]
+   "TARGET_NEON"
+-  "vmov%?\t%P0, %Q1, %R1"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "neon_type" "neon_bp_simple")]
++{
++  emit_move_insn (operands[0], operands[1]);
++  DONE;
++}
+ )
+ 
+ (define_insn "neon_vdup_nv2di"
+-  [(set (match_operand:V2DI 0 "s_register_operand" "=w")
+-	(unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")]
+-                     UNSPEC_VDUP_N))]
++  [(set (match_operand:V2DI 0 "s_register_operand" "=w,w")
++        (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))]
+   "TARGET_NEON"
+-  "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1"
++  "@
++  vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1
++  vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1"
+   [(set_attr "predicable" "yes")
+    (set_attr "length" "8")
+    (set_attr "neon_type" "neon_bp_simple")]
+ )
+ 
+-(define_insn "neon_vdup_lane<mode>"
+-  [(set (match_operand:VD 0 "s_register_operand" "=w")
+-	(unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
+-		    (match_operand:SI 2 "immediate_operand" "i")]
+-                   UNSPEC_VDUP_LANE))]
++(define_insn "neon_vdup_lane<mode>_internal"
++  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
++  	(vec_duplicate:VDQW 
++          (vec_select:<V_elem>
++            (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
++            (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
+   "TARGET_NEON"
+ {
+-  neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<MODE>mode));
+-  return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
++  if (BYTES_BIG_ENDIAN)
++    {
++      int elt = INTVAL (operands[2]);
++      elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt;
++      operands[2] = GEN_INT (elt);
++    }
++  if (<Is_d_reg>)
++    return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
++  else
++    return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
+ }
+   ;; Assume this schedules like vmov.
+   [(set_attr "neon_type" "neon_bp_simple")]
+ )
+ 
+-(define_insn "neon_vdup_lane<mode>"
+-  [(set (match_operand:VQ 0 "s_register_operand" "=w")
+-	(unspec:VQ [(match_operand:<V_HALF> 1 "s_register_operand" "w")
+-		    (match_operand:SI 2 "immediate_operand" "i")]
+-                   UNSPEC_VDUP_LANE))]
++(define_expand "neon_vdup_lane<mode>"
++  [(match_operand:VDQW 0 "s_register_operand" "=w")
++   (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
++   (match_operand:SI 2 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
+-  neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_HALF>mode));
+-  return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
+-}
+-  ;; Assume this schedules like vmov.
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
++  neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_double_vector_mode>mode));
++  if (BYTES_BIG_ENDIAN)
++    {
++      unsigned int elt = INTVAL (operands[2]);
++      unsigned int reg_nelts
++	= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<V_double_vector_mode>mode));
++      elt ^= reg_nelts - 1;
++      operands[2] = GEN_INT (elt);
++    }
++    emit_insn (gen_neon_vdup_lane<mode>_internal (operands[0], operands[1],
++                                                  operands[2]));
++    DONE;
++})
+ 
+ ; Scalar index is ignored, since only zero is valid here.
+ (define_expand "neon_vdup_lanedi"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
+-		    (match_operand:SI 2 "immediate_operand" "i")]
+-                   UNSPEC_VDUP_LANE))]
++  [(match_operand:DI 0 "s_register_operand" "=w")
++   (match_operand:DI 1 "s_register_operand" "w")
++   (match_operand:SI 2 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
+   neon_lane_bounds (operands[2], 0, 1);
+@@ -2772,20 +2854,17 @@
+   DONE;
+ })
+ 
+-; Likewise.
+-(define_insn "neon_vdup_lanev2di"
+-  [(set (match_operand:V2DI 0 "s_register_operand" "=w")
+-	(unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w")
+-		      (match_operand:SI 2 "immediate_operand" "i")]
+-                     UNSPEC_VDUP_LANE))]
++; Likewise for v2di, as the DImode second operand has only a single element.
++(define_expand "neon_vdup_lanev2di"
++  [(match_operand:V2DI 0 "s_register_operand" "=w")
++   (match_operand:DI 1 "s_register_operand" "w")
++   (match_operand:SI 2 "immediate_operand" "i")]
+   "TARGET_NEON"
+ {
+   neon_lane_bounds (operands[2], 0, 1);
+-  return "vmov\t%e0, %P1\;vmov\t%f0, %P1";
+-}
+-  [(set_attr "length" "8")
+-   (set_attr "neon_type" "neon_bp_simple")]
+-)
++  emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1]));
++  DONE;
++})
+ 
+ ;; In this insn, operand 1 should be low, and operand 2 the high part of the
+ ;; dest vector.
+@@ -2796,9 +2875,8 @@
+ 
+ (define_insn "neon_vcombine<mode>"
+   [(set (match_operand:<V_DOUBLE> 0 "s_register_operand" "=w")
+-	(unspec:<V_DOUBLE> [(match_operand:VDX 1 "s_register_operand" "w")
+-			    (match_operand:VDX 2 "s_register_operand" "w")]
+-                           UNSPEC_VCOMBINE))]
++        (vec_concat:<V_DOUBLE> (match_operand:VDX 1 "s_register_operand" "w")
++			       (match_operand:VDX 2 "s_register_operand" "w")))]
+   "TARGET_NEON"
+ {
+   int dest = REGNO (operands[0]);
+@@ -2838,27 +2916,171 @@
+    (set_attr "neon_type" "neon_bp_simple")]
+ )
+ 
+-(define_insn "neon_vget_high<mode>"
+-  [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
+-	(unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
+-			 UNSPEC_VGET_HIGH))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src + 2)
+-    return "vmov\t%P0, %f1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_low<mode>"
+-  [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
+-	(unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
+-			 UNSPEC_VGET_LOW))]
++(define_insn "neon_vget_highv16qi"
++  [(set (match_operand:V8QI 0 "s_register_operand" "=w")
++	(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
++                         (parallel [(const_int 8) (const_int 9)
++			            (const_int 10) (const_int 11)
++				    (const_int 12) (const_int 13)
++				    (const_int 14) (const_int 15)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src + 2)
++    return "vmov\t%P0, %f1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_highv8hi"
++  [(set (match_operand:V4HI 0 "s_register_operand" "=w")
++	(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
++	                 (parallel [(const_int 4) (const_int 5)
++			            (const_int 6) (const_int 7)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src + 2)
++    return "vmov\t%P0, %f1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_highv4si"
++  [(set (match_operand:V2SI 0 "s_register_operand" "=w")
++	(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
++	                 (parallel [(const_int 2) (const_int 3)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src + 2)
++    return "vmov\t%P0, %f1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_highv4sf"
++  [(set (match_operand:V2SF 0 "s_register_operand" "=w")
++	(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
++	                 (parallel [(const_int 2) (const_int 3)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src + 2)
++    return "vmov\t%P0, %f1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_highv2di"
++  [(set (match_operand:DI 0 "s_register_operand" "=w")
++	(vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
++	               (parallel [(const_int 1)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src + 2)
++    return "vmov\t%P0, %f1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_lowv16qi"
++  [(set (match_operand:V8QI 0 "s_register_operand" "=w")
++	(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
++                         (parallel [(const_int 0) (const_int 1)
++			            (const_int 2) (const_int 3)
++				    (const_int 4) (const_int 5)
++				    (const_int 6) (const_int 7)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src)
++    return "vmov\t%P0, %e1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_lowv8hi"
++  [(set (match_operand:V4HI 0 "s_register_operand" "=w")
++	(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
++	                 (parallel [(const_int 0) (const_int 1)
++			            (const_int 2) (const_int 3)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src)
++    return "vmov\t%P0, %e1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_lowv4si"
++  [(set (match_operand:V2SI 0 "s_register_operand" "=w")
++	(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
++	                 (parallel [(const_int 0) (const_int 1)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src)
++    return "vmov\t%P0, %e1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_lowv4sf"
++  [(set (match_operand:V2SF 0 "s_register_operand" "=w")
++	(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
++	                 (parallel [(const_int 0) (const_int 1)])))]
++  "TARGET_NEON"
++{
++  int dest = REGNO (operands[0]);
++  int src = REGNO (operands[1]);
++
++  if (dest != src)
++    return "vmov\t%P0, %e1";
++  else
++    return "";
++}
++  [(set_attr "neon_type" "neon_bp_simple")]
++)
++
++(define_insn "neon_vget_lowv2di"
++  [(set (match_operand:DI 0 "s_register_operand" "=w")
++	(vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
++	               (parallel [(const_int 0)])))]
+   "TARGET_NEON"
+ {
+   int dest = REGNO (operands[0]);
+
+=== modified file 'gcc/config/arm/neon.ml'
+--- old/gcc/config/arm/neon.ml	2010-01-19 14:21:14 +0000
++++ new/gcc/config/arm/neon.ml	2010-07-29 15:59:12 +0000
+@@ -709,7 +709,8 @@
+ let ops =
+   [
+     (* Addition.  *)
+-    Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64;
++    Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32;
++    Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64];
+     Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;
+     Vadd, [], Long, "vaddl", elts_same_2, su_8_32;
+     Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;
+@@ -758,7 +759,8 @@
+     Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];
+ 
+     (* Subtraction.  *)
+-    Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64;
++    Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
++    Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2,  [S64; U64];
+     Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;
+     Vsub, [], Long, "vsubl", elts_same_2, su_8_32;
+     Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;
+@@ -967,7 +969,8 @@
+       Use_operands [| Corereg; Dreg; Immed |],
+       "vget_lane", get_lane, pf_su_8_32;
+     Vget_lane,
+-      [InfoWord;
++      [No_op;
++       InfoWord;
+        Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
+        Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+       Use_operands [| Corereg; Dreg; Immed |],
+@@ -989,7 +992,8 @@
+                 Instruction_name ["vmov"]],
+       Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
+       set_lane, pf_su_8_32;
+-    Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
++    Vset_lane, [No_op;
++                Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
+                 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+       Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
+       set_lane_notype, [S64; U64];
+@@ -1017,7 +1021,8 @@
+       Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
+       pf_su_8_32;
+     Vdup_n,
+-      [Instruction_name ["vmov"];
++      [No_op;
++       Instruction_name ["vmov"];
+        Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+       Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
+       [S64; U64];
+@@ -1028,7 +1033,8 @@
+       Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
+       pf_su_8_32;
+     Vdup_n,
+-      [Instruction_name ["vmov"];
++      [No_op;
++       Instruction_name ["vmov"];
+        Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
+                         Use_operands [| Dreg; Corereg; Corereg |]]],
+       Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1,
+@@ -1043,7 +1049,8 @@
+       Use_operands [| Dreg; Corereg |],
+       "vmov_n", bits_1, pf_su_8_32;
+     Vmov_n,
+-      [Builtin_name "vdup_n";
++      [No_op;
++       Builtin_name "vdup_n";
+        Instruction_name ["vmov"];
+        Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+       Use_operands [| Dreg; Corereg |],
+@@ -1056,7 +1063,8 @@
+       Use_operands [| Qreg; Corereg |],
+       "vmovQ_n", bits_1, pf_su_8_32;
+     Vmov_n,
+-      [Builtin_name "vdupQ_n";
++      [No_op;
++       Builtin_name "vdupQ_n";
+        Instruction_name ["vmov"];
+        Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
+                         Use_operands [| Dreg; Corereg; Corereg |]]],
+@@ -1613,23 +1621,28 @@
+       store_3, [P16; F32; U16; U32; S16; S32];
+ 
+     (* Logical operations. And.  *)
+-    Vand, [], All (3, Dreg), "vand", notype_2, su_8_64;
++    Vand, [], All (3, Dreg), "vand", notype_2, su_8_32;
++    Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64];
+     Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64;
+ 
+     (* Or.  *)
+-    Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64;
++    Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32;
++    Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64];
+     Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64;
+ 
+     (* Eor.  *)
+-    Veor, [], All (3, Dreg), "veor", notype_2, su_8_64;
++    Veor, [], All (3, Dreg), "veor", notype_2, su_8_32;
++    Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64];
+     Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64;
+ 
+     (* Bic (And-not).  *)
+-    Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64;
++    Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_32;
++    Vbic, [No_op], All (3, Dreg), "vbic", notype_2, [S64; U64];
+     Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64;
+ 
+     (* Or-not.  *)
+-    Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64;
++    Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_32;
++    Vorn, [No_op], All (3, Dreg), "vorn", notype_2, [S64; U64];
+     Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64;
+   ]
+ 
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2009-07-15 09:12:22 +0000
++++ new/gcc/config/arm/predicates.md	2010-07-29 15:59:12 +0000
+@@ -499,13 +499,15 @@
+ (define_predicate "imm_for_neon_logic_operand"
+   (match_code "const_vector")
+ {
+-  return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL);
++  return (TARGET_NEON
++          && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
+ })
+ 
+ (define_predicate "imm_for_neon_inv_logic_operand"
+   (match_code "const_vector")
+ {
+-  return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL);
++  return (TARGET_NEON
++          && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
+ })
+ 
+ (define_predicate "neon_logic_op2"
+
+=== modified file 'gcc/doc/arm-neon-intrinsics.texi'
+--- old/gcc/doc/arm-neon-intrinsics.texi	2009-11-18 17:06:46 +0000
++++ new/gcc/doc/arm-neon-intrinsics.texi	2010-07-29 15:59:12 +0000
+@@ -43,20 +43,18 @@
+ 
+ 
+ @itemize @bullet
++@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
++@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
++@end itemize
++
++
++@itemize @bullet
+ @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
+-@end itemize
+-
+-
+-@itemize @bullet
+-@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
+-@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -1013,20 +1011,18 @@
+ 
+ 
+ @itemize @bullet
++@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
++@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
++@end itemize
++
++
++@itemize @bullet
+ @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
+-@end itemize
+-
+-
+-@itemize @bullet
+-@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
+-@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -4750,13 +4746,11 @@
+ 
+ @itemize @bullet
+ @item uint64_t vget_lane_u64 (uint64x1_t, const int)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64_t vget_lane_s64 (int64x1_t, const int)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -4886,13 +4880,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+@@ -5081,13 +5073,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vdup_n_u64 (uint64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vdup_n_s64 (int64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+@@ -5147,13 +5137,11 @@
+ 
+ @itemize @bullet
+ @item uint64x2_t vdupq_n_u64 (uint64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x2_t vdupq_n_s64 (int64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+@@ -5213,13 +5201,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vmov_n_u64 (uint64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vmov_n_s64 (int64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+@@ -5279,13 +5265,11 @@
+ 
+ @itemize @bullet
+ @item uint64x2_t vmovq_n_u64 (uint64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x2_t vmovq_n_s64 (int64_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+ @end itemize
+ 
+ 
+@@ -5572,18 +5556,6 @@
+ 
+ 
+ @itemize @bullet
+-@item uint64x1_t vget_low_u64 (uint64x2_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+-@end itemize
+-
+-
+-@itemize @bullet
+-@item int64x1_t vget_low_s64 (int64x2_t)
+-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+-@end itemize
+-
+-
+-@itemize @bullet
+ @item float32x2_t vget_low_f32 (float32x4_t)
+ @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+ @end itemize
+@@ -5601,6 +5573,16 @@
+ @end itemize
+ 
+ 
++@itemize @bullet
++@item uint64x1_t vget_low_u64 (uint64x2_t)
++@end itemize
++
++
++@itemize @bullet
++@item int64x1_t vget_low_s64 (int64x2_t)
++@end itemize
++
++
+ 
+ 
+ @subsubsection Conversions
+@@ -9727,13 +9709,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -9827,13 +9807,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -9927,13 +9905,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -10027,13 +10003,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+@@ -10127,13 +10101,11 @@
+ 
+ @itemize @bullet
+ @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+ @itemize @bullet
+ @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
+-@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+ @end itemize
+ 
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vadds64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vadds64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vadds64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vadd_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL;
++
++  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vaddu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vaddu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vaddu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vadd_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL;
++
++  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vands64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vands64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vands64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vand_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
++
++  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0xdead000000000000LL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vandu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vandu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vandu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vand_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
++
++  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vbics64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vbics64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vbics64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vbic_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL);
++
++  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0xdead000000000000LL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vbicu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vbicu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vbicu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vbic_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL);
++
++  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,22 @@
++/* Test the `vdupq_lanes64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x2_t out_int64x2_t = {0, 0};
++  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
++
++  out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0);
++  if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
++    abort();
++  if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,22 @@
++/* Test the `vdupq_laneu64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x2_t out_uint64x2_t = {0, 0};
++  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
++
++  out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0);
++  if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
++    abort();
++  if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,22 @@
++/* Test the `vdupq_ns64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x2_t out_int64x2_t = {0, 0};
++  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
++
++  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
++  if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
++    abort();
++  if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,22 @@
++/* Test the `vdupq_nu64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x2_t out_uint64x2_t = {0, 0};
++  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
++
++  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
++  if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
++    abort();
++  if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,20 @@
++/* Test the `vdup_ns64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
++
++  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
++  if ((int64_t)out_int64x1_t != arg0_int64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,20 @@
++/* Test the `vdup_nu64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
++
++  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
++  if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-veors64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-veors64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-veors64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `veor_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
++
++  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-veoru64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-veoru64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-veoru64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `veor_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
++
++  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,20 @@
++/* Test the `vget_lane_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64_t out_int64_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
++
++  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
++  if (out_int64_t != (int64_t)arg0_int64x1_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,20 @@
++/* Test the `vget_lane_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64_t out_uint64_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
++
++  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
++  if (out_uint64_t != (uint64_t)arg0_uint64x1_t)
++    abort();
++  return 0;
++}
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmla-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vmla-1.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vmla-1.c	2010-07-29 15:59:12 +0000
+@@ -1,5 +1,5 @@
+ /* { dg-require-effective-target arm_neon_hw } */
+-/* { dg-options "-O2 -ftree-vectorize" } */
++/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+ /* { dg-add-options arm_neon } */
+ /* { dg-final { scan-assembler "vmla\\.f32" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmls-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vmls-1.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vmls-1.c	2010-07-29 15:59:12 +0000
+@@ -1,5 +1,5 @@
+ /* { dg-require-effective-target arm_neon_hw } */
+-/* { dg-options "-O2 -ftree-vectorize" } */
++/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+ /* { dg-add-options arm_neon } */
+ /* { dg-final { scan-assembler "vmls\\.f32" } } */
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,22 @@
++/* Test the `vmovq_ns64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x2_t out_int64x2_t = {0, 0};
++  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
++
++  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
++  if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
++    abort();
++  if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,23 @@
++/* Test the `vmovq_nu64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x2_t out_uint64x2_t = {0, 0};
++  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
++
++  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
++  if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
++    abort();
++  if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
++    abort();
++  return 0;
++}
++
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,20 @@
++/* Test the `vmov_ns64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
++
++  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
++  if ((int64_t)out_int64x1_t != arg0_int64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,20 @@
++/* Test the `vmov_nu64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
++
++  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
++  if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vorns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vorns64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vorns64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vorn_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL);
++
++  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vornu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vornu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vornu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vorn_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL);
++
++  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vorrs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vorrs64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vorrs64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vorr_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
++
++  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vorru64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vorru64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vorru64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vorr_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
++
++  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vset_lane_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64_t arg0_int64_t = 0xf00f00f00LL;
++  int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
++
++  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
++  if ((int64_t)out_int64x1_t != arg0_int64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vset_lane_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64_t arg0_uint64_t = 0xf00f00f00LL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
++
++  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
++  if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vsubs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vsubs64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vsubs64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vsub_s64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  int64x1_t out_int64x1_t = 0;
++  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL;
++  int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL;
++
++  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
++  if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL)
++    abort();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vsubu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vsubu64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vsubu64.c	2010-07-29 15:59:12 +0000
+@@ -0,0 +1,21 @@
++/* Test the `vsub_u64' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O0" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++#include <stdlib.h>
++
++int main (void)
++{
++  uint64x1_t out_uint64x1_t = 0;
++  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL;
++  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL;
++
++  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
++  if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL)
++    abort();
++  return 0;
++}
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vadds64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vadds64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vands64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vands64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandu64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbics64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbics64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c	2010-07-29 15:59:12 +0000
+@@ -16,6 +16,4 @@
+   out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c	2010-07-29 15:59:12 +0000
+@@ -16,6 +16,4 @@
+   out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c	2010-07-29 15:59:12 +0000
+@@ -16,5 +16,4 @@
+   out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c	2010-07-29 15:59:12 +0000
+@@ -16,5 +16,4 @@
+   out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veors64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veors64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veoru64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veoru64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c	2010-07-29 15:59:12 +0000
+@@ -16,5 +16,4 @@
+   out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c	2010-07-29 15:59:12 +0000
+@@ -16,5 +16,4 @@
+   out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c	2010-07-29 15:59:12 +0000
+@@ -16,6 +16,4 @@
+   out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c	2010-07-29 15:59:12 +0000
+@@ -16,6 +16,4 @@
+   out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c	2010-07-29 15:59:12 +0000
+@@ -16,5 +16,4 @@
+   out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c	2010-07-29 15:59:12 +0000
+@@ -16,5 +16,4 @@
+   out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorns64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornu64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorru64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorru64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu64.c	2010-07-29 15:59:12 +0000
+@@ -17,5 +17,4 @@
+   out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch
new file mode 100644
index 0000000000..0943130de6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch
@@ -0,0 +1,674 @@
+	2010-07-02  Daniel Jacobowitz  <dan@codesourcery.com>
+		    Julian Brown  <julian@codesourcery.com>
+		    Sandra Loosemore <sandra@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode
+	comparisons.  Adjust to take both operands.
+	(arm_select_cc_mode): Handle DImode comparisons.
+	(arm_gen_compare_reg): Generate a scratch register for DImode
+	comparisons which require one.  Use xor for Thumb equality checks.
+	(arm_const_double_by_immediates): New.
+	(arm_print_operand): Allow 'Q' and 'R' for constants.
+	(get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode.
+	* config/arm/arm.h (CANONICALIZE_COMPARISON): Always use
+	arm_canonicalize_comparison.
+	* config/arm/arm-modes.def: Add CC_CZmode and CC_NCVmode.
+	* config/arm/arm-protos.h (arm_canonicalize_comparison): Update
+	prototype.
+	(arm_const_double_by_immediates): Declare.
+	* config/arm/constraints.md (Di): New constraint.
+	* config/arm/predicates.md (arm_immediate_di_operand)
+	(arm_di_operand, cmpdi_operand): New.
+	* config/arm/arm.md (cbranchdi4): Handle non-Cirrus also.
+	(*arm_cmpdi_insn, *arm_cmpdi_unsigned)
+	(*arm_cmpdi_zero, *thumb_cmpdi_zero): New insns.
+	(cstoredi4): Handle non-Cirrus also.
+
+	gcc/testsuite/
+	* gcc.c-torture/execute/20100416-1.c: New test case.
+
+2010-07-08  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from upstream (originally from Sourcery G++ 4.4):
+
+ 	2010-07-02  Sandra Loosemore  <sandra@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm-modes.def'
+Index: gcc-4.5.3/gcc/config/arm/arm-modes.def
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/arm-modes.def
++++ gcc-4.5.3/gcc/config/arm/arm-modes.def
+@@ -35,10 +35,16 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_form
+    CC_NOOVmode should be used with SImode integer equalities.
+    CC_Zmode should be used if only the Z flag is set correctly
+    CC_Nmode should be used if only the N (sign) flag is set correctly
++   CC_CZmode should be used if only the C and Z flags are correct
++   (used for DImode unsigned comparisons).
++   CC_NCVmode should be used if only the N, C, and V flags are correct
++   (used for DImode signed comparisons).
+    CCmode should be used otherwise.  */
+ 
+ CC_MODE (CC_NOOV);
+ CC_MODE (CC_Z);
++CC_MODE (CC_CZ);
++CC_MODE (CC_NCV);
+ CC_MODE (CC_SWP);
+ CC_MODE (CCFP);
+ CC_MODE (CCFPE);
+Index: gcc-4.5.3/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/arm-protos.h
++++ gcc-4.5.3/gcc/config/arm/arm-protos.h
+@@ -49,8 +49,7 @@ extern int arm_hard_regno_mode_ok (unsig
+ extern int const_ok_for_arm (HOST_WIDE_INT);
+ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
+ 			       HOST_WIDE_INT, rtx, rtx, int);
+-extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, enum machine_mode,
+-					     rtx *);
++extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
+ extern int legitimate_pic_operand_p (rtx);
+ extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
+ extern rtx legitimize_tls_address (rtx, rtx);
+@@ -116,6 +115,7 @@ extern void arm_reload_in_hi (rtx *);
+ extern void arm_reload_out_hi (rtx *);
+ extern int arm_const_double_inline_cost (rtx);
+ extern bool arm_const_double_by_parts (rtx);
++extern bool arm_const_double_by_immediates (rtx);
+ extern const char *fp_immediate_constant (rtx);
+ extern void arm_emit_call_insn (rtx, rtx);
+ extern const char *output_call (rtx *);
+Index: gcc-4.5.3/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/arm.c
++++ gcc-4.5.3/gcc/config/arm/arm.c
+@@ -3191,13 +3191,82 @@ arm_gen_constant (enum rtx_code code, en
+    immediate value easier to load.  */
+ 
+ enum rtx_code
+-arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
+-			     rtx * op1)
++arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
+ {
+-  unsigned HOST_WIDE_INT i = INTVAL (*op1);
+-  unsigned HOST_WIDE_INT maxval;
++  enum machine_mode mode;
++  unsigned HOST_WIDE_INT i, maxval;
++
++  mode = GET_MODE (*op0);
++  if (mode == VOIDmode)
++    mode = GET_MODE (*op1);
++
+   maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
+ 
++  /* For DImode, we have GE/LT/GEU/LTU comparisons.  In ARM mode
++     we can also use cmp/cmpeq for GTU/LEU.  GT/LE must be either
++     reversed or (for constant OP1) adjusted to GE/LT.  Similarly
++     for GTU/LEU in Thumb mode.  */
++  if (mode == DImode)
++    {
++      rtx tem;
++
++      /* To keep things simple, always use the Cirrus cfcmp64 if it is
++	 available.  */
++      if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
++	return code;
++
++      if (code == GT || code == LE
++	  || (!TARGET_ARM && (code == GTU || code == LEU)))
++	{
++	  /* Missing comparison.  First try to use an available
++	     comparison.  */
++	  if (GET_CODE (*op1) == CONST_INT)
++	    {
++	      i = INTVAL (*op1);
++	      switch (code)
++		{
++		case GT:
++		case LE:
++		  if (i != maxval
++		      && arm_const_double_by_immediates (GEN_INT (i + 1)))
++		    {
++		      *op1 = GEN_INT (i + 1);
++		      return code == GT ? GE : LT;
++		    }
++		  break;
++		case GTU:
++		case LEU:
++		  if (i != ~((unsigned HOST_WIDE_INT) 0)
++		      && arm_const_double_by_immediates (GEN_INT (i + 1)))
++		    {
++		      *op1 = GEN_INT (i + 1);
++		      return code == GTU ? GEU : LTU;
++		    }
++		  break;
++		default:
++		  gcc_unreachable ();
++		}
++	    }
++
++	  /* If that did not work, reverse the condition.  */
++	  tem = *op0;
++	  *op0 = *op1;
++	  *op1 = tem;
++	  return swap_condition (code);
++	}
++
++      return code;
++    }
++
++  /* Comparisons smaller than DImode.  Only adjust comparisons against
++     an out-of-range constant.  */
++  if (GET_CODE (*op1) != CONST_INT
++      || const_ok_for_arm (INTVAL (*op1))
++      || const_ok_for_arm (- INTVAL (*op1)))
++    return code;
++
++  i = INTVAL (*op1);
++
+   switch (code)
+     {
+     case EQ:
+@@ -9913,6 +9982,55 @@ arm_select_cc_mode (enum rtx_code op, rt
+       && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
+     return CC_Cmode;
+ 
++  if (GET_MODE (x) == DImode || GET_MODE (y) == DImode)
++    {
++      /* To keep things simple, always use the Cirrus cfcmp64 if it is
++	 available.  */
++      if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
++	return CCmode;
++
++      switch (op)
++	{
++	case EQ:
++	case NE:
++	  /* A DImode comparison against zero can be implemented by
++	     or'ing the two halves together.  */
++	  if (y == const0_rtx)
++	    return CC_Zmode;
++
++	  /* We can do an equality test in three Thumb instructions.  */
++	  if (!TARGET_ARM)
++	    return CC_Zmode;
++
++	  /* FALLTHROUGH */
++
++	case LTU:
++	case LEU:
++	case GTU:
++	case GEU:
++	  /* DImode unsigned comparisons can be implemented by cmp +
++	     cmpeq without a scratch register.  Not worth doing in
++	     Thumb-2.  */
++	  if (TARGET_ARM)
++	    return CC_CZmode;
++
++	  /* FALLTHROUGH */
++
++	case LT:
++	case LE:
++	case GT:
++	case GE:
++	  /* DImode signed and unsigned comparisons can be implemented
++	     by cmp + sbcs with a scratch register, but that does not
++	     set the Z flag - we must reverse GT/LE/GTU/LEU.  */
++	  gcc_assert (op != EQ && op != NE);
++	  return CC_NCVmode;
++
++	default:
++	  gcc_unreachable ();
++	}
++    }
++
+   return CCmode;
+ }
+ 
+@@ -9922,10 +10040,39 @@ arm_select_cc_mode (enum rtx_code op, rt
+ rtx
+ arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
+ {
+-  enum machine_mode mode = SELECT_CC_MODE (code, x, y);
+-  rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
++  enum machine_mode mode;
++  rtx cc_reg;
++  int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode;
+ 
+-  emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
++  /* We might have X as a constant, Y as a register because of the predicates
++     used for cmpdi.  If so, force X to a register here.  */
++  if (dimode_comparison && !REG_P (x))
++    x = force_reg (DImode, x);
++
++  mode = SELECT_CC_MODE (code, x, y);
++  cc_reg = gen_rtx_REG (mode, CC_REGNUM);
++
++  if (dimode_comparison
++      && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
++      && mode != CC_CZmode)
++    {
++      rtx clobber, set;
++
++      /* To compare two non-zero values for equality, XOR them and
++	 then compare against zero.  Not used for ARM mode; there
++	 CC_CZmode is cheaper.  */
++      if (mode == CC_Zmode && y != const0_rtx)
++	{
++	  x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN);
++	  y = const0_rtx;
++	}
++      /* A scratch register is required.  */
++      clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode));
++      set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y));
++      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
++    }
++  else
++    emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
+ 
+   return cc_reg;
+ }
+@@ -11254,6 +11401,34 @@ arm_const_double_by_parts (rtx val)
+   return false;
+ }
+ 
++/* Return true if it is possible to inline both the high and low parts
++   of a 64-bit constant into 32-bit data processing instructions.  */
++bool
++arm_const_double_by_immediates (rtx val)
++{
++  enum machine_mode mode = GET_MODE (val);
++  rtx part;
++
++  if (mode == VOIDmode)
++    mode = DImode;
++
++  part = gen_highpart_mode (SImode, mode, val);
++
++  gcc_assert (GET_CODE (part) == CONST_INT);
++
++  if (!const_ok_for_arm (INTVAL (part)))
++    return false;
++
++  part = gen_lowpart (SImode, val);
++
++  gcc_assert (GET_CODE (part) == CONST_INT);
++
++  if (!const_ok_for_arm (INTVAL (part)))
++    return false;
++
++  return true;
++}
++
+ /* Scan INSN and note any of its operands that need fixing.
+    If DO_PUSHES is false we do not actually push any of the fixups
+    needed.  The function returns TRUE if any fixups were needed/pushed.
+@@ -15150,8 +15325,18 @@ arm_print_operand (FILE *stream, rtx x,
+ 	 the value being loaded is big-wordian or little-wordian.  The
+ 	 order of the two register loads can matter however, if the address
+ 	 of the memory location is actually held in one of the registers
+-	 being overwritten by the load.  */
++	 being overwritten by the load.
++
++	 The 'Q' and 'R' constraints are also available for 64-bit
++	 constants.  */
+     case 'Q':
++      if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
++	{
++	  rtx part = gen_lowpart (SImode, x);
++	  fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
++	  return;
++	}
++
+       if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ 	{
+ 	  output_operand_lossage ("invalid operand for code '%c'", code);
+@@ -15162,6 +15347,18 @@ arm_print_operand (FILE *stream, rtx x,
+       return;
+ 
+     case 'R':
++      if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
++	{
++	  enum machine_mode mode = GET_MODE (x);
++	  rtx part;
++
++	  if (mode == VOIDmode)
++	    mode = DImode;
++	  part = gen_highpart_mode (SImode, mode, x);
++	  fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
++	  return;
++	}
++
+       if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ 	{
+ 	  output_operand_lossage ("invalid operand for code '%c'", code);
+@@ -15854,6 +16051,28 @@ get_arm_condition_code (rtx comparison)
+       default: gcc_unreachable ();
+       }
+ 
++    case CC_CZmode:
++      switch (comp_code)
++	{
++	case NE: return ARM_NE;
++	case EQ: return ARM_EQ;
++	case GEU: return ARM_CS;
++	case GTU: return ARM_HI;
++	case LEU: return ARM_LS;
++	case LTU: return ARM_CC;
++	default: gcc_unreachable ();
++	}
++
++    case CC_NCVmode:
++      switch (comp_code)
++	{
++	case GE: return ARM_GE;
++	case LT: return ARM_LT;
++	case GEU: return ARM_CS;
++	case LTU: return ARM_CC;
++	default: gcc_unreachable ();
++	}
++
+     case CCmode:
+       switch (comp_code)
+ 	{
+Index: gcc-4.5.3/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/arm.h
++++ gcc-4.5.3/gcc/config/arm/arm.h
+@@ -2253,19 +2253,7 @@ extern int making_const_table;
+    : reverse_condition (code))
+ 
+ #define CANONICALIZE_COMPARISON(CODE, OP0, OP1)				\
+-  do									\
+-    {									\
+-      if (GET_CODE (OP1) == CONST_INT					\
+-          && ! (const_ok_for_arm (INTVAL (OP1))				\
+-	        || (const_ok_for_arm (- INTVAL (OP1)))))		\
+-        {								\
+-          rtx const_op = OP1;						\
+-          CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0),	\
+-					      &const_op);		\
+-          OP1 = const_op;						\
+-        }								\
+-    }									\
+-  while (0)
++  (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
+ 
+ /* The arm5 clz instruction returns 32.  */
+ #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
+Index: gcc-4.5.3/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/arm.md
++++ gcc-4.5.3/gcc/config/arm/arm.md
+@@ -6718,17 +6718,45 @@
+ 				   operands[3])); DONE;"
+ )
+ 
+-;; this uses the Cirrus DI compare instruction
+ (define_expand "cbranchdi4"
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "arm_comparison_operator"
+-	       [(match_operand:DI 1 "cirrus_fp_register" "")
+-	        (match_operand:DI 2 "cirrus_fp_register" "")])
++	       [(match_operand:DI 1 "cmpdi_operand" "")
++	        (match_operand:DI 2 "cmpdi_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+ 	      (pc)))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+-  "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
+-				   operands[3])); DONE;"
++  "TARGET_32BIT"
++  "{
++     rtx swap = NULL_RTX;
++     enum rtx_code code = GET_CODE (operands[0]);
++
++     /* We should not have two constants.  */
++     gcc_assert (GET_MODE (operands[1]) == DImode
++		 || GET_MODE (operands[2]) == DImode);
++
++    /* Flip unimplemented DImode comparisons to a form that
++       arm_gen_compare_reg can handle.  */
++     switch (code)
++     {
++     case GT:
++       swap = gen_rtx_LT (VOIDmode, operands[2], operands[1]); break;
++     case LE:
++       swap = gen_rtx_GE (VOIDmode, operands[2], operands[1]); break;
++     case GTU:
++       swap = gen_rtx_LTU (VOIDmode, operands[2], operands[1]); break;
++     case LEU:
++       swap = gen_rtx_GEU (VOIDmode, operands[2], operands[1]); break;
++     default:
++       break;
++     }
++     if (swap)
++       emit_jump_insn (gen_cbranch_cc (swap, operands[2], operands[1],
++                                       operands[3]));
++     else
++       emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
++				       operands[3]));
++     DONE;
++   }"
+ )
+ 
+ (define_insn "*cbranchsi4_insn"
+@@ -7880,6 +7908,52 @@
+ 				    (const_string "alu_shift_reg")))]
+ )
+ 
++;; DImode comparisons.  The generic code generates branches that
++;; if-conversion can not reduce to a conditional compare, so we do
++;; that directly.
++
++(define_insn "*arm_cmpdi_insn"
++  [(set (reg:CC_NCV CC_REGNUM)
++	(compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
++			(match_operand:DI 1 "arm_di_operand"	   "rDi")))
++   (clobber (match_scratch:SI 2 "=r"))]
++  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++  "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
++  [(set_attr "conds" "set")
++   (set_attr "length" "8")]
++)
++
++(define_insn "*arm_cmpdi_unsigned"
++  [(set (reg:CC_CZ CC_REGNUM)
++	(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
++		       (match_operand:DI 1 "arm_di_operand"	"rDi")))]
++  "TARGET_ARM"
++  "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1"
++  [(set_attr "conds" "set")
++   (set_attr "length" "8")]
++)
++
++(define_insn "*arm_cmpdi_zero"
++  [(set (reg:CC_Z CC_REGNUM)
++	(compare:CC_Z (match_operand:DI 0 "s_register_operand" "r")
++		      (const_int 0)))
++   (clobber (match_scratch:SI 1 "=r"))]
++  "TARGET_32BIT"
++  "orr%.\\t%1, %Q0, %R0"
++  [(set_attr "conds" "set")]
++)
++
++(define_insn "*thumb_cmpdi_zero"
++  [(set (reg:CC_Z CC_REGNUM)
++	(compare:CC_Z (match_operand:DI 0 "s_register_operand" "l")
++		      (const_int 0)))
++   (clobber (match_scratch:SI 1 "=l"))]
++  "TARGET_THUMB1"
++  "orr\\t%1, %Q0, %R0"
++  [(set_attr "conds" "set")
++   (set_attr "length" "2")]
++)
++
+ ;; Cirrus SF compare instruction
+ (define_insn "*cirrus_cmpsf"
+   [(set (reg:CCFP CC_REGNUM)
+@@ -8183,17 +8257,44 @@
+ 			     operands[2], operands[3])); DONE;"
+ )
+ 
+-;; this uses the Cirrus DI compare instruction
+ (define_expand "cstoredi4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(match_operator:SI 1 "arm_comparison_operator"
+-	 [(match_operand:DI 2 "cirrus_fp_register" "")
+-	  (match_operand:DI 3 "cirrus_fp_register" "")]))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+-  "emit_insn (gen_cstore_cc (operands[0], operands[1],
+-			     operands[2], operands[3])); DONE;"
+-)
++	 [(match_operand:DI 2 "cmpdi_operand" "")
++	  (match_operand:DI 3 "cmpdi_operand" "")]))]
++  "TARGET_32BIT"
++  "{
++     rtx swap = NULL_RTX;
++     enum rtx_code code = GET_CODE (operands[1]);
+ 
++     /* We should not have two constants.  */
++     gcc_assert (GET_MODE (operands[2]) == DImode
++		 || GET_MODE (operands[3]) == DImode);
++
++    /* Flip unimplemented DImode comparisons to a form that
++       arm_gen_compare_reg can handle.  */
++     switch (code)
++     {
++     case GT:
++       swap = gen_rtx_LT (VOIDmode, operands[3], operands[2]); break;
++     case LE:
++       swap = gen_rtx_GE (VOIDmode, operands[3], operands[2]); break;
++     case GTU:
++       swap = gen_rtx_LTU (VOIDmode, operands[3], operands[2]); break;
++     case LEU:
++       swap = gen_rtx_GEU (VOIDmode, operands[3], operands[2]); break;
++     default:
++       break;
++     }
++     if (swap)
++       emit_insn (gen_cstore_cc (operands[0], swap, operands[3],
++		      	         operands[2]));
++     else
++       emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2],
++		      	         operands[3]));
++     DONE;
++   }"
++)
+ 
+ (define_expand "cstoresi_eq0_thumb1"
+   [(parallel
+Index: gcc-4.5.3/gcc/config/arm/constraints.md
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/constraints.md
++++ gcc-4.5.3/gcc/config/arm/constraints.md
+@@ -29,7 +29,7 @@
+ ;; in Thumb-1 state: I, J, K, L, M, N, O
+ 
+ ;; The following multi-letter normal constraints have been used:
+-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy
++;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
+ ;; in Thumb-1 state: Pa, Pb
+ ;; in Thumb-2 state: Ps, Pt
+ 
+@@ -191,6 +191,13 @@
+       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
+ 		   && !(optimize_size || arm_ld_sched)")))
+ 
++(define_constraint "Di"
++ "@internal
++  In ARM/Thumb-2 state a const_int or const_double where both the high
++  and low SImode words can be generated as immediates in 32-bit instructions."
++ (and (match_code "const_double,const_int")
++      (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
++
+ (define_constraint "Dn"
+  "@internal
+   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
+Index: gcc-4.5.3/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/predicates.md
++++ gcc-4.5.3/gcc/config/arm/predicates.md
+@@ -101,6 +101,12 @@
+   (and (match_code "const_int")
+        (match_test "const_ok_for_arm (INTVAL (op))")))
+ 
++;; A constant value which fits into two instructions, each taking
++;; an arithmetic constant operand for one of the words.
++(define_predicate "arm_immediate_di_operand"
++  (and (match_code "const_int,const_double")
++       (match_test "arm_const_double_by_immediates (op)")))
++
+ (define_predicate "arm_neg_immediate_operand"
+   (and (match_code "const_int")
+        (match_test "const_ok_for_arm (-INTVAL (op))")))
+@@ -130,6 +136,10 @@
+   (ior (match_operand 0 "arm_rhs_operand")
+        (match_operand 0 "arm_not_immediate_operand")))
+ 
++(define_predicate "arm_di_operand"
++  (ior (match_operand 0 "s_register_operand")
++       (match_operand 0 "arm_immediate_di_operand")))
++
+ ;; True if the operand is a memory reference which contains an
+ ;; offsettable address.
+ (define_predicate "offsettable_memory_operand"
+@@ -538,3 +548,12 @@
+   (and (match_code "const_int")
+        (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
+ 
++;; Predicates for named expanders that overlap multiple ISAs.
++
++(define_predicate "cmpdi_operand"
++  (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
++               (and (match_test "TARGET_ARM")
++                    (match_operand 0 "cirrus_fp_register"))
++               (and (match_test "TARGET_32BIT")
++                    (match_operand 0 "arm_di_operand"))))
++
+Index: gcc-4.5.3/gcc/testsuite/gcc.c-torture/execute/20100416-1.c
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/gcc/testsuite/gcc.c-torture/execute/20100416-1.c
+@@ -0,0 +1,40 @@
++void abort(void);
++
++int
++movegt(int x, int y, long long a)
++{
++  int i;
++  int ret = 0;
++  for (i = 0; i < y; i++)
++    {
++      if (a >= (long long) 0xf000000000000000LL)
++	ret = x;
++      else
++	ret = y;
++    }
++  return ret;
++}
++
++struct test
++{
++  long long val;
++  int ret;
++} tests[] = {
++  { 0xf000000000000000LL, -1 },
++  { 0xefffffffffffffffLL, 1 },
++  { 0xf000000000000001LL, -1 },
++  { 0x0000000000000000LL, -1 },
++  { 0x8000000000000000LL, 1 },
++};
++
++int
++main()
++{
++  int i;
++  for (i = 0; i < sizeof (tests) / sizeof (tests[0]); i++)
++    {
++      if (movegt (-1, 1, tests[i].val) != tests[i].ret)
++	abort ();
++    }
++  return 0;
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch
new file mode 100644
index 0000000000..635d3f8bd5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch
@@ -0,0 +1,244 @@
+2010-07-09  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from mainline (originally on Sourcery G++ 4.4):
+
+	2010-07-02  Julian Brown  <julian@codesourcery.com>
+		    Sandra Loosemore <sandra@codesourcery.com>
+
+	PR target/43703
+
+	gcc/
+	* config/arm/vec-common.md (add<mode>3, sub<mode>3, smin<mode>3)
+	(smax<mode>3): Disable for NEON float modes when
+	flag_unsafe_math_optimizations is false.
+	* config/arm/neon.md (*add<mode>3_neon, *sub<mode>3_neon)
+	(*mul<mode>3_neon)
+	(mul<mode>3add<mode>_neon, mul<mode>3neg<mode>add<mode>_neon)
+	(reduc_splus_<mode>, reduc_smin_<mode>, reduc_smax_<mode>): Disable
+	for NEON float modes when flag_unsafe_math_optimizations is false.
+	(quad_halves_<code>v4sf): Only enable if flag_unsafe_math_optimizations
+	is true.
+	* doc/invoke.texi (ARM Options): Add note about floating point
+	vectorization requiring -funsafe-math-optimizations.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect.exp: Add -ffast-math for NEON.
+	* gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON.
+
+ 2010-07-08  Sandra Loosemore  <sandra@codesourcery.com>
+ 
+ 	Backport from upstream (originally from Sourcery G++ 4.4):
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2010-07-29 15:59:12 +0000
++++ new/gcc/config/arm/neon.md	2010-07-29 17:03:20 +0000
+@@ -819,7 +819,7 @@
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+ 		  (match_operand:VDQ 2 "s_register_operand" "w")))]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+   "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+   [(set (attr "neon_type")
+       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+@@ -853,7 +853,7 @@
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+                    (match_operand:VDQ 2 "s_register_operand" "w")))]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+   "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+   [(set (attr "neon_type")
+       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+@@ -888,7 +888,7 @@
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+         (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+                   (match_operand:VDQ 2 "s_register_operand" "w")))]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+   "vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+   [(set (attr "neon_type")
+       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+@@ -910,7 +910,7 @@
+         (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
+                             (match_operand:VDQ 3 "s_register_operand" "w"))
+ 		  (match_operand:VDQ 1 "s_register_operand" "0")))]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+   "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+   [(set (attr "neon_type")
+       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+@@ -932,7 +932,7 @@
+         (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
+                    (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
+                              (match_operand:VDQ 3 "s_register_operand" "w"))))]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+   "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
+   [(set (attr "neon_type")
+       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+@@ -1361,7 +1361,7 @@
+                            (parallel [(const_int 0) (const_int 1)]))
+           (vec_select:V2SF (match_dup 1)
+                            (parallel [(const_int 2) (const_int 3)]))))]
+-  "TARGET_NEON"
++  "TARGET_NEON && flag_unsafe_math_optimizations"
+   "<VQH_mnem>.f32\t%P0, %e1, %f1"
+   [(set_attr "vqh_mnem" "<VQH_mnem>")
+    (set (attr "neon_type")
+@@ -1496,7 +1496,7 @@
+ (define_expand "reduc_splus_<mode>"
+   [(match_operand:VD 0 "s_register_operand" "")
+    (match_operand:VD 1 "s_register_operand" "")]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+ {
+   neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ 			&gen_neon_vpadd_internal<mode>);
+@@ -1506,7 +1506,7 @@
+ (define_expand "reduc_splus_<mode>"
+   [(match_operand:VQ 0 "s_register_operand" "")
+    (match_operand:VQ 1 "s_register_operand" "")]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+ {
+   rtx step1 = gen_reg_rtx (<V_HALF>mode);
+   rtx res_d = gen_reg_rtx (<V_HALF>mode);
+@@ -1541,7 +1541,7 @@
+ (define_expand "reduc_smin_<mode>"
+   [(match_operand:VD 0 "s_register_operand" "")
+    (match_operand:VD 1 "s_register_operand" "")]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+ {
+   neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ 			&gen_neon_vpsmin<mode>);
+@@ -1551,7 +1551,7 @@
+ (define_expand "reduc_smin_<mode>"
+   [(match_operand:VQ 0 "s_register_operand" "")
+    (match_operand:VQ 1 "s_register_operand" "")]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+ {
+   rtx step1 = gen_reg_rtx (<V_HALF>mode);
+   rtx res_d = gen_reg_rtx (<V_HALF>mode);
+@@ -1566,7 +1566,7 @@
+ (define_expand "reduc_smax_<mode>"
+   [(match_operand:VD 0 "s_register_operand" "")
+    (match_operand:VD 1 "s_register_operand" "")]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+ {
+   neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ 			&gen_neon_vpsmax<mode>);
+@@ -1576,7 +1576,7 @@
+ (define_expand "reduc_smax_<mode>"
+   [(match_operand:VQ 0 "s_register_operand" "")
+    (match_operand:VQ 1 "s_register_operand" "")]
+-  "TARGET_NEON"
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
+ {
+   rtx step1 = gen_reg_rtx (<V_HALF>mode);
+   rtx res_d = gen_reg_rtx (<V_HALF>mode);
+
+=== modified file 'gcc/config/arm/vec-common.md'
+--- old/gcc/config/arm/vec-common.md	2009-11-11 14:23:03 +0000
++++ new/gcc/config/arm/vec-common.md	2010-07-29 17:03:20 +0000
+@@ -57,7 +57,8 @@
+   [(set (match_operand:VALL 0 "s_register_operand" "")
+         (plus:VALL (match_operand:VALL 1 "s_register_operand" "")
+                    (match_operand:VALL 2 "s_register_operand" "")))]
+-  "TARGET_NEON
++  "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
++		    || flag_unsafe_math_optimizations))
+    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
+ {
+ })
+@@ -66,7 +67,8 @@
+   [(set (match_operand:VALL 0 "s_register_operand" "")
+         (minus:VALL (match_operand:VALL 1 "s_register_operand" "")
+                     (match_operand:VALL 2 "s_register_operand" "")))]
+-  "TARGET_NEON
++  "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
++		    || flag_unsafe_math_optimizations))
+    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
+ {
+ })
+@@ -75,7 +77,9 @@
+   [(set (match_operand:VALLW 0 "s_register_operand" "")
+         (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
+ 		    (match_operand:VALLW 2 "s_register_operand" "")))]
+-  "TARGET_NEON || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
++  "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
++		    || flag_unsafe_math_optimizations))
++   || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
+ {
+ })
+ 
+@@ -83,7 +87,8 @@
+   [(set (match_operand:VALLW 0 "s_register_operand" "")
+ 	(smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
+ 		    (match_operand:VALLW 2 "s_register_operand" "")))]
+-  "TARGET_NEON
++  "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
++		    || flag_unsafe_math_optimizations))
+    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
+ {
+ })
+@@ -101,7 +106,8 @@
+   [(set (match_operand:VALLW 0 "s_register_operand" "")
+ 	(smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
+ 		    (match_operand:VALLW 2 "s_register_operand" "")))]
+-  "TARGET_NEON
++  "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
++		    || flag_unsafe_math_optimizations))
+    || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
+ {
+ })
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-07-29 15:53:39 +0000
++++ new/gcc/doc/invoke.texi	2010-07-29 17:03:20 +0000
+@@ -9874,6 +9874,14 @@
+ If @option{-msoft-float} is specified this specifies the format of
+ floating point values.
+ 
++If the selected floating-point hardware includes the NEON extension
++(e.g. @option{-mfpu}=@samp{neon}), note that floating-point
++operations will not be used by GCC's auto-vectorization pass unless
++@option{-funsafe-math-optimizations} is also specified.  This is
++because NEON hardware does not fully implement the IEEE 754 standard for
++floating-point arithmetic (in particular denormal values are treated as
++zero), so the use of NEON instructions may lead to a loss of precision.
++
+ @item -mfp16-format=@var{name}
+ @opindex mfp16-format
+ Specify the format of the @code{__fp16} half-precision floating-point type.
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-6.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c	2010-07-29 17:03:20 +0000
+@@ -49,5 +49,6 @@
+ }
+ 
+ /* need -ffast-math to vectorizer these loops.  */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
++/* ARM NEON passes -ffast-math to these tests, so expect this to fail.  */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail arm_neon_ok } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
+--- old/gcc/testsuite/gcc.dg/vect/vect.exp	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect.exp	2010-07-29 17:03:20 +0000
+@@ -102,6 +102,10 @@
+     set dg-do-what-default run
+ } elseif [is-effective-target arm_neon_ok] {
+     eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
++    # NEON does not support denormals, so is not used for vectorization by
++    # default to avoid loss of precision.  We must pass -ffast-math to test
++    # vectorization of float operations.
++    lappend DEFAULT_VECTCFLAGS "-ffast-math"
+     if [is-effective-target arm_neon_hw] {
+       set dg-do-what-default run
+     } else {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch
new file mode 100644
index 0000000000..53d1d08d52
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch
@@ -0,0 +1,131 @@
+	Merge from Sourcery G++ 4.4:
+
+	2009-05-21  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Merge from Sourcery G++ 4.3:
+
+	2009-04-04  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Issue #5104
+	PR tree-optimization/39604
+
+	gcc/testsuite
+	* g++.dg/tree-ssa/sink-1.C: New.
+
+	gcc/
+	* tree_ssa-sink.c (sink_code_in_bb): Do not sink statements out
+	of a lexical block containing variable definitions.
+
+2010-07-09  Sandra Loosemore  <sandra@codesourcery.com>
+
+ 	Backport from mainline (originally on Sourcery G++ 4.4):
+ 
+ 	2010-07-02  Julian Brown  <julian@codesourcery.com>
+
+=== added file 'gcc/testsuite/g++.dg/tree-ssa/sink-1.C'
+--- old/gcc/testsuite/g++.dg/tree-ssa/sink-1.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/tree-ssa/sink-1.C	2010-07-30 12:14:18 +0000
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-options "-O1" } */
++
++class A {
++ public:
++  A() {}
++  virtual ~A() {}  
++  void * dostuff();
++  
++  virtual int dovirtual() = 0;
++};
++
++
++class B : public A {
++ public:
++  B() {}
++  int dovirtual() { return 0;}
++  virtual ~B() {};
++}; 
++
++class C : public B {
++ public:
++  C() {}
++  virtual ~C() {};
++};
++
++void* A::dostuff()
++{
++  return (void*)dovirtual();
++}
++
++/* tree-ssa-sink was sinking the inlined destructor for STUFF out of
++   the first inner block and into the second one, where it was ending up
++   after the inlined constructor for STUFF2.  This is bad because
++   cfgexpand aliases STUFF and STUFF2 to the same storage at -O1
++   (i.e., without -fstrict-aliasing), with the result that STUFF2's
++   vtable was getting trashed. */
++
++int main() {
++  {
++    B stuff;
++    stuff.dostuff();
++  }
++  {
++    C stuff2;
++    stuff2.dostuff();
++  }
++  return 0;
++}
++
+
+=== modified file 'gcc/tree-ssa-sink.c'
+--- old/gcc/tree-ssa-sink.c	2009-11-28 16:21:00 +0000
++++ new/gcc/tree-ssa-sink.c	2010-07-30 12:14:18 +0000
+@@ -470,6 +470,47 @@
+ 	  last = false;
+ 	  continue;
+ 	}
++
++      /* We cannot move statements that contain references to block-scope
++	 variables out of that block, as this may lead to incorrect aliasing
++	 when we lay out the stack frame in cfgexpand.c.
++	 In lieu of more sophisticated analysis, be very conservative here
++	 and prohibit moving any statement that references memory out of a
++	 block with variables.  */
++      if (gimple_references_memory_p (stmt))
++	{
++	  tree fromblock = gimple_block (stmt);
++	  while (fromblock
++		 && fromblock != current_function_decl
++		 && !BLOCK_VARS (fromblock))
++	    fromblock = BLOCK_SUPERCONTEXT (fromblock);
++	  if (fromblock && fromblock != current_function_decl)
++	    {
++	      gimple tostmt;
++	      tree toblock;
++
++	      if (gsi_end_p (togsi))
++		tostmt = gimple_seq_last_stmt (gsi_seq (togsi));
++	      else
++		tostmt = gsi_stmt (togsi);
++	      if (tostmt)
++		toblock = gimple_block (tostmt);
++	      else
++		toblock = NULL;
++	      while (toblock
++		     && toblock != current_function_decl
++		     && toblock != fromblock)
++		toblock = BLOCK_SUPERCONTEXT (toblock);
++	      if (!toblock || toblock != fromblock)
++		{
++		  if (!gsi_end_p (gsi))
++		    gsi_prev (&gsi);
++		  last = false;
++		  continue;
++		}
++	    }
++	}
++
+       if (dump_file)
+ 	{
+ 	  fprintf (dump_file, "Sinking ");
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch
new file mode 100644
index 0000000000..ab1296347b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch
@@ -0,0 +1,81 @@
+2010-07-10  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	2009-05-28  Julian Brown  <julian@codesourcery.com>
+
+	Merged from Sourcery G++ 4.3:
+
+	libgcc/
+	* config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*)
+	(arm*-*-symbianelf): Add arm/t-divmod-ef to tmake_file.
+	* Makefile.in (LIB2_DIVMOD_EXCEPTION_FLAGS): Set to previous
+	default if not set by a target-specific Makefile fragment.
+	(lib2-divmod-o, lib2-divmod-s-o): Use above.
+	* config/arm/t-divmod-ef: New.
+
+ 2010-07-09  Sandra Loosemore  <sandra@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.4:
+
+=== modified file 'libgcc/Makefile.in'
+--- old/libgcc/Makefile.in	2010-03-30 12:08:52 +0000
++++ new/libgcc/Makefile.in	2010-07-30 12:21:02 +0000
+@@ -400,18 +400,24 @@
+ endif
+ endif
+ 
++ifeq ($(LIB2_DIVMOD_EXCEPTION_FLAGS),)
++# Provide default flags for compiling divmod functions, if they haven't been
++# set already by a target-specific Makefile fragment.
++LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions -fnon-call-exceptions
++endif
++
+ # Build LIB2_DIVMOD_FUNCS.
+ lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS))
+ $(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c
+ 	$(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
+-	  -fexceptions -fnon-call-exceptions $(vis_hide)
++	  $(LIB2_DIVMOD_EXCEPTION_FLAGS) $(vis_hide)
+ libgcc-objects += $(lib2-divmod-o)
+ 
+ ifeq ($(enable_shared),yes)
+ lib2-divmod-s-o = $(patsubst %,%_s$(objext),$(LIB2_DIVMOD_FUNCS))
+ $(lib2-divmod-s-o): %_s$(objext): $(gcc_srcdir)/libgcc2.c
+ 	$(gcc_s_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
+-	  -fexceptions -fnon-call-exceptions
++	  $(LIB2_DIVMOD_EXCEPTION_FLAGS)
+ libgcc-s-objects += $(lib2-divmod-s-o)
+ endif
+ 
+
+=== modified file 'libgcc/config.host'
+--- old/libgcc/config.host	2010-04-02 02:02:18 +0000
++++ new/libgcc/config.host	2010-07-30 12:21:02 +0000
+@@ -208,12 +208,15 @@
+ arm*-*-netbsd*)
+ 	;;
+ arm*-*-linux*)			# ARM GNU/Linux with ELF
++	tmake_file="${tmake_file} arm/t-divmod-ef"
+ 	;;
+ arm*-*-uclinux*)		# ARM ucLinux
++	tmake_file="${tmake_file} arm/t-divmod-ef"
+ 	;;
+ arm*-*-ecos-elf)
+ 	;;
+ arm*-*-eabi* | arm*-*-symbianelf* )
++	tmake_file="${tmake_file} arm/t-divmod-ef"
+ 	;;
+ arm*-*-rtems*)
+ 	;;
+
+=== added directory 'libgcc/config/arm'
+=== added file 'libgcc/config/arm/t-divmod-ef'
+--- old/libgcc/config/arm/t-divmod-ef	1970-01-01 00:00:00 +0000
++++ new/libgcc/config/arm/t-divmod-ef	2010-07-30 12:21:02 +0000
+@@ -0,0 +1,4 @@
++# On ARM, specifying -fnon-call-exceptions will needlessly pull in
++# the unwinder in simple programs which use 64-bit division.  Omitting
++# the option is safe.
++LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch
new file mode 100644
index 0000000000..ed25334dfb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch
@@ -0,0 +1,52 @@
+	2009-09-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	libgcc/
+	* shared-object.mk (c_flags-$(base)$(objext)): New.
+	($(base)$(objext)): Use above.
+	($(base)_s$(objext)): Likewise.
+	* static-object.mk (c_flags-$(base)$(objext)): New.
+	($(base)$(objext)): Use above.
+	
+2010-07-10  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2009-05-28  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Merged from Sourcery G++ 4.3:
+
+=== modified file 'libgcc/shared-object.mk'
+--- old/libgcc/shared-object.mk	2008-07-03 18:22:00 +0000
++++ new/libgcc/shared-object.mk	2010-07-30 13:11:02 +0000
+@@ -8,11 +8,13 @@
+ 
+ ifeq ($(suffix $o),.c)
+ 
++c_flags-$(base)$(objext) := $(c_flags)
+ $(base)$(objext): $o
+-	$(gcc_compile) $(c_flags) -c $< $(vis_hide)
++	$(gcc_compile) $(c_flags-$@) -c $< $(vis_hide)
+ 
++c_flags-$(base)_s$(objext) := $(c_flags)
+ $(base)_s$(objext): $o
+-	$(gcc_s_compile) $(c_flags) -c $<
++	$(gcc_s_compile) $(c_flags-$@) -c $<
+ 
+ else
+ 
+
+=== modified file 'libgcc/static-object.mk'
+--- old/libgcc/static-object.mk	2007-01-04 04:22:37 +0000
++++ new/libgcc/static-object.mk	2010-07-30 13:11:02 +0000
+@@ -8,8 +8,9 @@
+ 
+ ifeq ($(suffix $o),.c)
+ 
++c_flags-$(base)$(objext) := $(c_flags)
+ $(base)$(objext): $o
+-	$(gcc_compile) $(c_flags) -c $< $(vis_hide)
++	$(gcc_compile) $(c_flags-$@) -c $< $(vis_hide)
+ 
+ else
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch
new file mode 100644
index 0000000000..423cd56528
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch
@@ -0,0 +1,1401 @@
+2010-07-10  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-05-08  Sandra Loosemore  <sandra@codesourcery.com>
+
+	PR middle-end/28685
+
+	gcc/
+	* tree-ssa-reassoc.c (eliminate_redundant_comparison): New function.
+	(optimize_ops_list): Call it.
+
+	gcc/testsuite/
+	* gcc.dg/pr28685-1.c: New file.
+
+	2010-06-08  Sandra Loosemore  <sandra@codesourcery.com>
+
+	PR tree-optimization/39874
+	PR middle-end/28685
+
+	gcc/
+	* gimple.h (maybe_fold_and_comparisons, maybe_fold_or_comparisons):
+	Declare.
+	* gimple-fold.c (canonicalize_bool, same_bool_comparison_p,
+	same_bool_result_p): New.
+	(and_var_with_comparison, and_var_with_comparison_1,
+	and_comparisons_1, and_comparisons, maybe_fold_and_comparisons): New.
+	(or_var_with_comparison, or_var_with_comparison_1,
+	or_comparisons_1, or_comparisons, maybe_fold_or_comparisons): New.
+	* tree-ssa-reassoc.c (eliminate_redundant_comparison): Use
+	maybe_fold_and_comparisons or maybe_fold_or_comparisons instead
+	of combine_comparisons.
+	* tree-ssa-ifcombine.c (ifcombine_ifandif, ifcombine_iforif): Likewise.
+
+	gcc/testsuite/
+	* gcc.dg/pr39874.c: New file.
+
+ 2010-07-10  Yao Qi  <yao@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.4:
+
+=== modified file 'gcc/gimple.h'
+--- old/gcc/gimple.h	2010-04-02 18:54:46 +0000
++++ new/gcc/gimple.h	2010-07-30 13:21:51 +0000
+@@ -4743,4 +4743,9 @@
+ 
+ extern void dump_gimple_statistics (void);
+ 
++extern tree maybe_fold_and_comparisons (enum tree_code, tree, tree, 
++					enum tree_code, tree, tree);
++extern tree maybe_fold_or_comparisons (enum tree_code, tree, tree,
++				       enum tree_code, tree, tree);
++
+ #endif  /* GCC_GIMPLE_H */
+
+=== added file 'gcc/testsuite/gcc.dg/pr28685-1.c'
+--- old/gcc/testsuite/gcc.dg/pr28685-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr28685-1.c	2010-07-30 13:21:51 +0000
+@@ -0,0 +1,50 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-optimized" }  */
++
++/* Should produce <=.  */
++int test1 (int a, int b)
++{
++  return (a < b || a == b);
++}
++
++/* Should produce <=.  */
++int test2 (int a, int b)
++{
++  int lt = a < b;
++  int eq = a == b;
++
++  return (lt || eq);
++}
++
++/* Should produce <= (just deleting redundant test).  */
++int test3 (int a, int b)
++{
++  int lt = a <= b;
++  int eq = a == b;
++
++  return (lt || eq);
++}
++
++/* Should produce <= (operands reversed to test the swap logic).  */
++int test4 (int a, int b)
++{
++  int lt = a < b;
++  int eq = b == a;
++
++  return (lt || eq);
++}
++
++/* Should produce constant 0.  */
++int test5 (int a, int b)
++{
++  int lt = a < b;
++  int eq = a == b;
++
++  return (lt && eq);
++}
++
++/* { dg-final { scan-tree-dump-times " <= " 4 "optimized" } } */
++/* { dg-final { scan-tree-dump-times "return 0" 1 "optimized" } } */
++/* { dg-final { scan-tree-dump-not " < " "optimized" } } */
++/* { dg-final { scan-tree-dump-not " == " "optimized" } } */
++/* { dg-final { cleanup-tree-dump "optimized" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/pr39874.c'
+--- old/gcc/testsuite/gcc.dg/pr39874.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr39874.c	2010-07-30 13:21:51 +0000
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-optimized" }  */
++
++extern void func();
++
++void test1(char *signature)
++{
++  char ch = signature[0];
++  if (ch == 15 || ch == 3)
++  {
++    if (ch == 15) func();
++  }
++}
++
++
++void test2(char *signature)
++{
++  char ch = signature[0];
++  if (ch == 15 || ch == 3)
++  {
++    if (ch > 14) func();
++  }
++}
++
++/* { dg-final { scan-tree-dump-times " == 15" 2 "optimized" } } */
++/* { dg-final { scan-tree-dump-not " == 3" "optimized" } } */
++/* { dg-final { cleanup-tree-dump "optimized" } } */
++
++
+
+=== modified file 'gcc/tree-ssa-ccp.c'
+--- old/gcc/tree-ssa-ccp.c	2010-04-02 15:50:04 +0000
++++ new/gcc/tree-ssa-ccp.c	2010-07-30 13:21:51 +0000
+@@ -3176,6 +3176,1056 @@
+   return changed;
+ }
+ 
++/* Canonicalize and possibly invert the boolean EXPR; return NULL_TREE 
++   if EXPR is null or we don't know how.
++   If non-null, the result always has boolean type.  */
++
++static tree
++canonicalize_bool (tree expr, bool invert)
++{
++  if (!expr)
++    return NULL_TREE;
++  else if (invert)
++    {
++      if (integer_nonzerop (expr))
++	return boolean_false_node;
++      else if (integer_zerop (expr))
++	return boolean_true_node;
++      else if (TREE_CODE (expr) == SSA_NAME)
++	return fold_build2 (EQ_EXPR, boolean_type_node, expr,
++			    build_int_cst (TREE_TYPE (expr), 0));
++      else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison)
++	return fold_build2 (invert_tree_comparison (TREE_CODE (expr), false),
++			    boolean_type_node,
++			    TREE_OPERAND (expr, 0),
++			    TREE_OPERAND (expr, 1));
++      else
++	return NULL_TREE;
++    }
++  else
++    {
++      if (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE)
++	return expr;
++      if (integer_nonzerop (expr))
++	return boolean_true_node;
++      else if (integer_zerop (expr))
++	return boolean_false_node;
++      else if (TREE_CODE (expr) == SSA_NAME)
++	return fold_build2 (NE_EXPR, boolean_type_node, expr,
++			    build_int_cst (TREE_TYPE (expr), 0));
++      else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison)
++	return fold_build2 (TREE_CODE (expr),
++			    boolean_type_node,
++			    TREE_OPERAND (expr, 0),
++			    TREE_OPERAND (expr, 1));
++      else
++	return NULL_TREE;
++    }
++}
++
++/* Check to see if a boolean expression EXPR is logically equivalent to the
++   comparison (OP1 CODE OP2).  Check for various identities involving
++   SSA_NAMEs.  */
++
++static bool
++same_bool_comparison_p (const_tree expr, enum tree_code code,
++			const_tree op1, const_tree op2)
++{
++  gimple s;
++
++  /* The obvious case.  */
++  if (TREE_CODE (expr) == code
++      && operand_equal_p (TREE_OPERAND (expr, 0), op1, 0)
++      && operand_equal_p (TREE_OPERAND (expr, 1), op2, 0))
++    return true;
++
++  /* Check for comparing (name, name != 0) and the case where expr
++     is an SSA_NAME with a definition matching the comparison.  */
++  if (TREE_CODE (expr) == SSA_NAME
++      && TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE)
++    {
++      if (operand_equal_p (expr, op1, 0))
++	return ((code == NE_EXPR && integer_zerop (op2))
++		|| (code == EQ_EXPR && integer_nonzerop (op2)));
++      s = SSA_NAME_DEF_STMT (expr);
++      if (is_gimple_assign (s)
++	  && gimple_assign_rhs_code (s) == code
++	  && operand_equal_p (gimple_assign_rhs1 (s), op1, 0)
++	  && operand_equal_p (gimple_assign_rhs2 (s), op2, 0))
++	return true;
++    }
++
++  /* If op1 is of the form (name != 0) or (name == 0), and the definition
++     of name is a comparison, recurse.  */
++  if (TREE_CODE (op1) == SSA_NAME
++      && TREE_CODE (TREE_TYPE (op1)) == BOOLEAN_TYPE)
++    {
++      s = SSA_NAME_DEF_STMT (op1);
++      if (is_gimple_assign (s)
++	  && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison)
++	{
++	  enum tree_code c = gimple_assign_rhs_code (s);
++	  if ((c == NE_EXPR && integer_zerop (op2))
++	      || (c == EQ_EXPR && integer_nonzerop (op2)))
++	    return same_bool_comparison_p (expr, c,
++					   gimple_assign_rhs1 (s),
++					   gimple_assign_rhs2 (s));
++	  if ((c == EQ_EXPR && integer_zerop (op2))
++	      || (c == NE_EXPR && integer_nonzerop (op2)))
++	    return same_bool_comparison_p (expr,
++					   invert_tree_comparison (c, false),
++					   gimple_assign_rhs1 (s),
++					   gimple_assign_rhs2 (s));
++	}
++    }
++  return false;
++}
++
++/* Check to see if two boolean expressions OP1 and OP2 are logically
++   equivalent.  */
++
++static bool
++same_bool_result_p (const_tree op1, const_tree op2)
++{
++  /* Simple cases first.  */
++  if (operand_equal_p (op1, op2, 0))
++    return true;
++
++  /* Check the cases where at least one of the operands is a comparison.
++     These are a bit smarter than operand_equal_p in that they apply some
++     identifies on SSA_NAMEs.  */
++  if (TREE_CODE_CLASS (TREE_CODE (op2)) == tcc_comparison
++      && same_bool_comparison_p (op1, TREE_CODE (op2),
++				 TREE_OPERAND (op2, 0),
++				 TREE_OPERAND (op2, 1)))
++    return true;
++  if (TREE_CODE_CLASS (TREE_CODE (op1)) == tcc_comparison
++      && same_bool_comparison_p (op2, TREE_CODE (op1),
++				 TREE_OPERAND (op1, 0),
++				 TREE_OPERAND (op1, 1)))
++    return true;
++
++  /* Default case.  */
++  return false;
++}
++
++/* Forward declarations for some mutually recursive functions.  */
++
++static tree
++and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b,
++		   enum tree_code code2, tree op2a, tree op2b);
++static tree
++and_var_with_comparison (tree var, bool invert,
++			 enum tree_code code2, tree op2a, tree op2b);
++static tree
++and_var_with_comparison_1 (gimple stmt, 
++			   enum tree_code code2, tree op2a, tree op2b);
++static tree
++or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b,
++		  enum tree_code code2, tree op2a, tree op2b);
++static tree
++or_var_with_comparison (tree var, bool invert,
++			enum tree_code code2, tree op2a, tree op2b);
++static tree
++or_var_with_comparison_1 (gimple stmt, 
++			  enum tree_code code2, tree op2a, tree op2b);
++
++/* Helper function for and_comparisons_1:  try to simplify the AND of the
++   ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B).
++   If INVERT is true, invert the value of the VAR before doing the AND.
++   Return NULL_EXPR if we can't simplify this to a single expression.  */
++
++static tree
++and_var_with_comparison (tree var, bool invert,
++			 enum tree_code code2, tree op2a, tree op2b)
++{
++  tree t;
++  gimple stmt = SSA_NAME_DEF_STMT (var);
++
++  /* We can only deal with variables whose definitions are assignments.  */
++  if (!is_gimple_assign (stmt))
++    return NULL_TREE;
++  
++  /* If we have an inverted comparison, apply DeMorgan's law and rewrite
++     !var AND (op2a code2 op2b) => !(var OR !(op2a code2 op2b))
++     Then we only have to consider the simpler non-inverted cases.  */
++  if (invert)
++    t = or_var_with_comparison_1 (stmt, 
++				  invert_tree_comparison (code2, false),
++				  op2a, op2b);
++  else
++    t = and_var_with_comparison_1 (stmt, code2, op2a, op2b);
++  return canonicalize_bool (t, invert);
++}
++
++/* Try to simplify the AND of the ssa variable defined by the assignment
++   STMT with the comparison specified by (OP2A CODE2 OP2B).
++   Return NULL_EXPR if we can't simplify this to a single expression.  */
++
++static tree
++and_var_with_comparison_1 (gimple stmt,
++			   enum tree_code code2, tree op2a, tree op2b)
++{
++  tree var = gimple_assign_lhs (stmt);
++  tree true_test_var = NULL_TREE;
++  tree false_test_var = NULL_TREE;
++  enum tree_code innercode = gimple_assign_rhs_code (stmt);
++
++  /* Check for identities like (var AND (var == 0)) => false.  */
++  if (TREE_CODE (op2a) == SSA_NAME
++      && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE)
++    {
++      if ((code2 == NE_EXPR && integer_zerop (op2b))
++	  || (code2 == EQ_EXPR && integer_nonzerop (op2b)))
++	{
++	  true_test_var = op2a;
++	  if (var == true_test_var)
++	    return var;
++	}
++      else if ((code2 == EQ_EXPR && integer_zerop (op2b))
++	       || (code2 == NE_EXPR && integer_nonzerop (op2b)))
++	{
++	  false_test_var = op2a;
++	  if (var == false_test_var)
++	    return boolean_false_node;
++	}
++    }
++
++  /* If the definition is a comparison, recurse on it.  */
++  if (TREE_CODE_CLASS (innercode) == tcc_comparison)
++    {
++      tree t = and_comparisons_1 (innercode,
++				  gimple_assign_rhs1 (stmt),
++				  gimple_assign_rhs2 (stmt),
++				  code2,
++				  op2a,
++				  op2b);
++      if (t)
++	return t;
++    }
++
++  /* If the definition is an AND or OR expression, we may be able to
++     simplify by reassociating.  */
++  if (innercode == TRUTH_AND_EXPR
++      || innercode == TRUTH_OR_EXPR
++      || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE
++	  && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR)))
++    {
++      tree inner1 = gimple_assign_rhs1 (stmt);
++      tree inner2 = gimple_assign_rhs2 (stmt);
++      gimple s;
++      tree t;
++      tree partial = NULL_TREE;
++      bool is_and = (innercode == TRUTH_AND_EXPR || innercode == BIT_AND_EXPR);
++      
++      /* Check for boolean identities that don't require recursive examination
++	 of inner1/inner2:
++	 inner1 AND (inner1 AND inner2) => inner1 AND inner2 => var
++	 inner1 AND (inner1 OR inner2) => inner1
++	 !inner1 AND (inner1 AND inner2) => false
++	 !inner1 AND (inner1 OR inner2) => !inner1 AND inner2
++         Likewise for similar cases involving inner2.  */
++      if (inner1 == true_test_var)
++	return (is_and ? var : inner1);
++      else if (inner2 == true_test_var)
++	return (is_and ? var : inner2);
++      else if (inner1 == false_test_var)
++	return (is_and
++		? boolean_false_node
++		: and_var_with_comparison (inner2, false, code2, op2a, op2b));
++      else if (inner2 == false_test_var)
++	return (is_and
++		? boolean_false_node
++		: and_var_with_comparison (inner1, false, code2, op2a, op2b));
++
++      /* Next, redistribute/reassociate the AND across the inner tests.
++	 Compute the first partial result, (inner1 AND (op2a code op2b))  */
++      if (TREE_CODE (inner1) == SSA_NAME
++	  && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1))
++	  && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison
++	  && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s),
++					      gimple_assign_rhs1 (s),
++					      gimple_assign_rhs2 (s),
++					      code2, op2a, op2b)))
++	{
++	  /* Handle the AND case, where we are reassociating:
++	     (inner1 AND inner2) AND (op2a code2 op2b)
++	     => (t AND inner2)
++	     If the partial result t is a constant, we win.  Otherwise
++	     continue on to try reassociating with the other inner test.  */
++	  if (is_and)
++	    {
++	      if (integer_onep (t))
++		return inner2;
++	      else if (integer_zerop (t))
++		return boolean_false_node;
++	    }
++
++	  /* Handle the OR case, where we are redistributing:
++	     (inner1 OR inner2) AND (op2a code2 op2b)
++	     => (t OR (inner2 AND (op2a code2 op2b)))  */
++	  else
++	    {
++	      if (integer_onep (t))
++		return boolean_true_node;
++	      else
++		/* Save partial result for later.  */
++		partial = t;
++	    }
++	}
++      
++      /* Compute the second partial result, (inner2 AND (op2a code op2b)) */
++      if (TREE_CODE (inner2) == SSA_NAME
++	  && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2))
++	  && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison
++	  && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s),
++					      gimple_assign_rhs1 (s),
++					      gimple_assign_rhs2 (s),
++					      code2, op2a, op2b)))
++	{
++	  /* Handle the AND case, where we are reassociating:
++	     (inner1 AND inner2) AND (op2a code2 op2b)
++	     => (inner1 AND t)  */
++	  if (is_and)
++	    {
++	      if (integer_onep (t))
++		return inner1;
++	      else if (integer_zerop (t))
++		return boolean_false_node;
++	    }
++
++	  /* Handle the OR case. where we are redistributing:
++	     (inner1 OR inner2) AND (op2a code2 op2b)
++	     => (t OR (inner1 AND (op2a code2 op2b)))
++	     => (t OR partial)  */
++	  else
++	    {
++	      if (integer_onep (t))
++		return boolean_true_node;
++	      else if (partial)
++		{
++		  /* We already got a simplification for the other
++		     operand to the redistributed OR expression.  The
++		     interesting case is when at least one is false.
++		     Or, if both are the same, we can apply the identity
++		     (x OR x) == x.  */
++		  if (integer_zerop (partial))
++		    return t;
++		  else if (integer_zerop (t))
++		    return partial;
++		  else if (same_bool_result_p (t, partial))
++		    return t;
++		}
++	    }
++	}
++    }
++  return NULL_TREE;
++}
++
++/* Try to simplify the AND of two comparisons defined by
++   (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively.
++   If this can be done without constructing an intermediate value,
++   return the resulting tree; otherwise NULL_TREE is returned.
++   This function is deliberately asymmetric as it recurses on SSA_DEFs
++   in the first comparison but not the second.  */
++
++static tree
++and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b,
++		   enum tree_code code2, tree op2a, tree op2b)
++{
++  /* First check for ((x CODE1 y) AND (x CODE2 y)).  */
++  if (operand_equal_p (op1a, op2a, 0)
++      && operand_equal_p (op1b, op2b, 0))
++    {
++      tree t = combine_comparisons (UNKNOWN_LOCATION,
++				    TRUTH_ANDIF_EXPR, code1, code2,
++				    boolean_type_node, op1a, op1b);
++      if (t)
++	return t;
++    }
++
++  /* Likewise the swapped case of the above.  */
++  if (operand_equal_p (op1a, op2b, 0)
++      && operand_equal_p (op1b, op2a, 0))
++    {
++      tree t = combine_comparisons (UNKNOWN_LOCATION,
++				    TRUTH_ANDIF_EXPR, code1,
++				    swap_tree_comparison (code2),
++				    boolean_type_node, op1a, op1b);
++      if (t)
++	return t;
++    }
++
++  /* If both comparisons are of the same value against constants, we might
++     be able to merge them.  */
++  if (operand_equal_p (op1a, op2a, 0)
++      && TREE_CODE (op1b) == INTEGER_CST
++      && TREE_CODE (op2b) == INTEGER_CST)
++    {
++      int cmp = tree_int_cst_compare (op1b, op2b);
++
++      /* If we have (op1a == op1b), we should either be able to
++	 return that or FALSE, depending on whether the constant op1b
++	 also satisfies the other comparison against op2b.  */
++      if (code1 == EQ_EXPR)
++	{
++	  bool done = true;
++	  bool val;
++	  switch (code2)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp < 0); break;
++	    case GT_EXPR: val = (cmp > 0); break;
++	    case LE_EXPR: val = (cmp <= 0); break;
++	    case GE_EXPR: val = (cmp >= 0); break;
++	    default: done = false;
++	    }
++	  if (done)
++	    {
++	      if (val)
++		return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	      else
++		return boolean_false_node;
++	    }
++	}
++      /* Likewise if the second comparison is an == comparison.  */
++      else if (code2 == EQ_EXPR)
++	{
++	  bool done = true;
++	  bool val;
++	  switch (code1)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp > 0); break;
++	    case GT_EXPR: val = (cmp < 0); break;
++	    case LE_EXPR: val = (cmp >= 0); break;
++	    case GE_EXPR: val = (cmp <= 0); break;
++	    default: done = false;
++	    }
++	  if (done)
++	    {
++	      if (val)
++		return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	      else
++		return boolean_false_node;
++	    }
++	}
++
++      /* Same business with inequality tests.  */
++      else if (code1 == NE_EXPR)
++	{
++	  bool val;
++	  switch (code2)
++	    {
++	    case EQ_EXPR: val = (cmp != 0); break;
++	    case NE_EXPR: val = (cmp == 0); break;
++	    case LT_EXPR: val = (cmp >= 0); break;
++	    case GT_EXPR: val = (cmp <= 0); break;
++	    case LE_EXPR: val = (cmp > 0); break;
++	    case GE_EXPR: val = (cmp < 0); break;
++	    default:
++	      val = false;
++	    }
++	  if (val)
++	    return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	}
++      else if (code2 == NE_EXPR)
++	{
++	  bool val;
++	  switch (code1)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp <= 0); break;
++	    case GT_EXPR: val = (cmp >= 0); break;
++	    case LE_EXPR: val = (cmp < 0); break;
++	    case GE_EXPR: val = (cmp > 0); break;
++	    default:
++	      val = false;
++	    }
++	  if (val)
++	    return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	}
++
++      /* Chose the more restrictive of two < or <= comparisons.  */
++      else if ((code1 == LT_EXPR || code1 == LE_EXPR)
++	       && (code2 == LT_EXPR || code2 == LE_EXPR))
++	{
++	  if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR))
++	    return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	  else
++	    return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	}
++
++      /* Likewise chose the more restrictive of two > or >= comparisons.  */
++      else if ((code1 == GT_EXPR || code1 == GE_EXPR)
++	       && (code2 == GT_EXPR || code2 == GE_EXPR))
++	{
++	  if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR))
++	    return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	  else
++	    return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	}
++
++      /* Check for singleton ranges.  */
++      else if (cmp == 0
++	       && ((code1 == LE_EXPR && code2 == GE_EXPR)
++		   || (code1 == GE_EXPR && code2 == LE_EXPR)))
++	return fold_build2 (EQ_EXPR, boolean_type_node, op1a, op2b);
++
++      /* Check for disjoint ranges. */
++      else if (cmp <= 0
++	       && (code1 == LT_EXPR || code1 == LE_EXPR)
++	       && (code2 == GT_EXPR || code2 == GE_EXPR))
++	return boolean_false_node;
++      else if (cmp >= 0
++	       && (code1 == GT_EXPR || code1 == GE_EXPR)
++	       && (code2 == LT_EXPR || code2 == LE_EXPR))
++	return boolean_false_node;
++    }
++
++  /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where
++     NAME's definition is a truth value.  See if there are any simplifications
++     that can be done against the NAME's definition.  */
++  if (TREE_CODE (op1a) == SSA_NAME
++      && (code1 == NE_EXPR || code1 == EQ_EXPR)
++      && (integer_zerop (op1b) || integer_onep (op1b)))
++    {
++      bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b))
++		     || (code1 == NE_EXPR && integer_onep (op1b)));
++      gimple stmt = SSA_NAME_DEF_STMT (op1a);
++      switch (gimple_code (stmt))
++	{
++	case GIMPLE_ASSIGN:
++	  /* Try to simplify by copy-propagating the definition.  */
++	  return and_var_with_comparison (op1a, invert, code2, op2a, op2b);
++
++	case GIMPLE_PHI:
++	  /* If every argument to the PHI produces the same result when
++	     ANDed with the second comparison, we win.
++	     Do not do this unless the type is bool since we need a bool
++	     result here anyway.  */
++	  if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE)
++	    {
++	      tree result = NULL_TREE;
++	      unsigned i;
++	      for (i = 0; i < gimple_phi_num_args (stmt); i++)
++		{
++		  tree arg = gimple_phi_arg_def (stmt, i);
++		  
++		  /* If this PHI has itself as an argument, ignore it.
++		     If all the other args produce the same result,
++		     we're still OK.  */
++		  if (arg == gimple_phi_result (stmt))
++		    continue;
++		  else if (TREE_CODE (arg) == INTEGER_CST)
++		    {
++		      if (invert ? integer_nonzerop (arg) : integer_zerop (arg))
++			{
++			  if (!result)
++			    result = boolean_false_node;
++			  else if (!integer_zerop (result))
++			    return NULL_TREE;
++			}
++		      else if (!result)
++			result = fold_build2 (code2, boolean_type_node,
++					      op2a, op2b);
++		      else if (!same_bool_comparison_p (result,
++							code2, op2a, op2b))
++			return NULL_TREE;
++		    }
++		  else if (TREE_CODE (arg) == SSA_NAME)
++		    {
++		      tree temp = and_var_with_comparison (arg, invert,
++							   code2, op2a, op2b);
++		      if (!temp)
++			return NULL_TREE;
++		      else if (!result)
++			result = temp;
++		      else if (!same_bool_result_p (result, temp))
++			return NULL_TREE;
++		    }
++		  else
++		    return NULL_TREE;
++		}
++	      return result;
++	    }
++
++	default:
++	  break;
++	}
++    }
++  return NULL_TREE;
++}
++
++/* Try to simplify the AND of two comparisons, specified by
++   (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively.
++   If this can be simplified to a single expression (without requiring
++   introducing more SSA variables to hold intermediate values),
++   return the resulting tree.  Otherwise return NULL_TREE.
++   If the result expression is non-null, it has boolean type.  */
++
++tree
++maybe_fold_and_comparisons (enum tree_code code1, tree op1a, tree op1b,
++			    enum tree_code code2, tree op2a, tree op2b)
++{
++  tree t = and_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b);
++  if (t)
++    return t;
++  else
++    return and_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b);
++}
++
++/* Helper function for or_comparisons_1:  try to simplify the OR of the
++   ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B).
++   If INVERT is true, invert the value of VAR before doing the OR.
++   Return NULL_EXPR if we can't simplify this to a single expression.  */
++
++static tree
++or_var_with_comparison (tree var, bool invert,
++			enum tree_code code2, tree op2a, tree op2b)
++{
++  tree t;
++  gimple stmt = SSA_NAME_DEF_STMT (var);
++
++  /* We can only deal with variables whose definitions are assignments.  */
++  if (!is_gimple_assign (stmt))
++    return NULL_TREE;
++  
++  /* If we have an inverted comparison, apply DeMorgan's law and rewrite
++     !var OR (op2a code2 op2b) => !(var AND !(op2a code2 op2b))
++     Then we only have to consider the simpler non-inverted cases.  */
++  if (invert)
++    t = and_var_with_comparison_1 (stmt, 
++				   invert_tree_comparison (code2, false),
++				   op2a, op2b);
++  else
++    t = or_var_with_comparison_1 (stmt, code2, op2a, op2b);
++  return canonicalize_bool (t, invert);
++}
++
++/* Try to simplify the OR of the ssa variable defined by the assignment
++   STMT with the comparison specified by (OP2A CODE2 OP2B).
++   Return NULL_EXPR if we can't simplify this to a single expression.  */
++
++static tree
++or_var_with_comparison_1 (gimple stmt,
++			  enum tree_code code2, tree op2a, tree op2b)
++{
++  tree var = gimple_assign_lhs (stmt);
++  tree true_test_var = NULL_TREE;
++  tree false_test_var = NULL_TREE;
++  enum tree_code innercode = gimple_assign_rhs_code (stmt);
++
++  /* Check for identities like (var OR (var != 0)) => true .  */
++  if (TREE_CODE (op2a) == SSA_NAME
++      && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE)
++    {
++      if ((code2 == NE_EXPR && integer_zerop (op2b))
++	  || (code2 == EQ_EXPR && integer_nonzerop (op2b)))
++	{
++	  true_test_var = op2a;
++	  if (var == true_test_var)
++	    return var;
++	}
++      else if ((code2 == EQ_EXPR && integer_zerop (op2b))
++	       || (code2 == NE_EXPR && integer_nonzerop (op2b)))
++	{
++	  false_test_var = op2a;
++	  if (var == false_test_var)
++	    return boolean_true_node;
++	}
++    }
++
++  /* If the definition is a comparison, recurse on it.  */
++  if (TREE_CODE_CLASS (innercode) == tcc_comparison)
++    {
++      tree t = or_comparisons_1 (innercode,
++				 gimple_assign_rhs1 (stmt),
++				 gimple_assign_rhs2 (stmt),
++				 code2,
++				 op2a,
++				 op2b);
++      if (t)
++	return t;
++    }
++  
++  /* If the definition is an AND or OR expression, we may be able to
++     simplify by reassociating.  */
++  if (innercode == TRUTH_AND_EXPR
++      || innercode == TRUTH_OR_EXPR
++      || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE
++	  && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR)))
++    {
++      tree inner1 = gimple_assign_rhs1 (stmt);
++      tree inner2 = gimple_assign_rhs2 (stmt);
++      gimple s;
++      tree t;
++      tree partial = NULL_TREE;
++      bool is_or = (innercode == TRUTH_OR_EXPR || innercode == BIT_IOR_EXPR);
++      
++      /* Check for boolean identities that don't require recursive examination
++	 of inner1/inner2:
++	 inner1 OR (inner1 OR inner2) => inner1 OR inner2 => var
++	 inner1 OR (inner1 AND inner2) => inner1
++	 !inner1 OR (inner1 OR inner2) => true
++	 !inner1 OR (inner1 AND inner2) => !inner1 OR inner2
++      */
++      if (inner1 == true_test_var)
++	return (is_or ? var : inner1);
++      else if (inner2 == true_test_var)
++	return (is_or ? var : inner2);
++      else if (inner1 == false_test_var)
++	return (is_or
++		? boolean_true_node
++		: or_var_with_comparison (inner2, false, code2, op2a, op2b));
++      else if (inner2 == false_test_var)
++	return (is_or
++		? boolean_true_node
++		: or_var_with_comparison (inner1, false, code2, op2a, op2b));
++      
++      /* Next, redistribute/reassociate the OR across the inner tests.
++	 Compute the first partial result, (inner1 OR (op2a code op2b))  */
++      if (TREE_CODE (inner1) == SSA_NAME
++	  && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1))
++	  && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison
++	  && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s),
++					     gimple_assign_rhs1 (s),
++					     gimple_assign_rhs2 (s),
++					     code2, op2a, op2b)))
++	{
++	  /* Handle the OR case, where we are reassociating:
++	     (inner1 OR inner2) OR (op2a code2 op2b)
++	     => (t OR inner2)
++	     If the partial result t is a constant, we win.  Otherwise
++	     continue on to try reassociating with the other inner test.  */
++	  if (innercode == TRUTH_OR_EXPR)
++	    {
++	      if (integer_onep (t))
++		return boolean_true_node;
++	      else if (integer_zerop (t))
++		return inner2;
++	    }
++	  
++	  /* Handle the AND case, where we are redistributing:
++	     (inner1 AND inner2) OR (op2a code2 op2b)
++	     => (t AND (inner2 OR (op2a code op2b)))  */
++	  else
++	    {
++	      if (integer_zerop (t))
++		return boolean_false_node;
++	      else
++		/* Save partial result for later.  */
++		partial = t;
++	    }
++	}
++      
++      /* Compute the second partial result, (inner2 OR (op2a code op2b)) */
++      if (TREE_CODE (inner2) == SSA_NAME
++	  && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2))
++	  && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison
++	  && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s),
++					     gimple_assign_rhs1 (s),
++					     gimple_assign_rhs2 (s),
++					     code2, op2a, op2b)))
++	{
++	  /* Handle the OR case, where we are reassociating:
++	     (inner1 OR inner2) OR (op2a code2 op2b)
++	     => (inner1 OR t)  */
++	  if (innercode == TRUTH_OR_EXPR)
++	    {
++	      if (integer_zerop (t))
++		return inner1;
++	      else if (integer_onep (t))
++		return boolean_true_node;
++	    }
++	  
++	  /* Handle the AND case, where we are redistributing:
++	     (inner1 AND inner2) OR (op2a code2 op2b)
++	     => (t AND (inner1 OR (op2a code2 op2b)))
++	     => (t AND partial)  */
++	  else 
++	    {
++	      if (integer_zerop (t))
++		return boolean_false_node;
++	      else if (partial)
++		{
++		  /* We already got a simplification for the other
++		     operand to the redistributed AND expression.  The
++		     interesting case is when at least one is true.
++		     Or, if both are the same, we can apply the identity
++		     (x AND x) == true.  */
++		  if (integer_onep (partial))
++		    return t;
++		  else if (integer_onep (t))
++		    return partial;
++		  else if (same_bool_result_p (t, partial))
++		    return boolean_true_node;
++		}
++	    }
++	}
++    }
++  return NULL_TREE;
++}
++
++/* Try to simplify the OR of two comparisons defined by
++   (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively.
++   If this can be done without constructing an intermediate value,
++   return the resulting tree; otherwise NULL_TREE is returned.
++   This function is deliberately asymmetric as it recurses on SSA_DEFs
++   in the first comparison but not the second.  */
++
++static tree
++or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b,
++		  enum tree_code code2, tree op2a, tree op2b)
++{
++  /* First check for ((x CODE1 y) OR (x CODE2 y)).  */
++  if (operand_equal_p (op1a, op2a, 0)
++      && operand_equal_p (op1b, op2b, 0))
++    {
++      tree t = combine_comparisons (UNKNOWN_LOCATION,
++				    TRUTH_ORIF_EXPR, code1, code2,
++				    boolean_type_node, op1a, op1b);
++      if (t)
++	return t;
++    }
++
++  /* Likewise the swapped case of the above.  */
++  if (operand_equal_p (op1a, op2b, 0)
++      && operand_equal_p (op1b, op2a, 0))
++    {
++      tree t = combine_comparisons (UNKNOWN_LOCATION,
++				    TRUTH_ORIF_EXPR, code1,
++				    swap_tree_comparison (code2),
++				    boolean_type_node, op1a, op1b);
++      if (t)
++	return t;
++    }
++
++  /* If both comparisons are of the same value against constants, we might
++     be able to merge them.  */
++  if (operand_equal_p (op1a, op2a, 0)
++      && TREE_CODE (op1b) == INTEGER_CST
++      && TREE_CODE (op2b) == INTEGER_CST)
++    {
++      int cmp = tree_int_cst_compare (op1b, op2b);
++
++      /* If we have (op1a != op1b), we should either be able to
++	 return that or TRUE, depending on whether the constant op1b
++	 also satisfies the other comparison against op2b.  */
++      if (code1 == NE_EXPR)
++	{
++	  bool done = true;
++	  bool val;
++	  switch (code2)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp < 0); break;
++	    case GT_EXPR: val = (cmp > 0); break;
++	    case LE_EXPR: val = (cmp <= 0); break;
++	    case GE_EXPR: val = (cmp >= 0); break;
++	    default: done = false;
++	    }
++	  if (done)
++	    {
++	      if (val)
++		return boolean_true_node;
++	      else
++		return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	    }
++	}
++      /* Likewise if the second comparison is a != comparison.  */
++      else if (code2 == NE_EXPR)
++	{
++	  bool done = true;
++	  bool val;
++	  switch (code1)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp > 0); break;
++	    case GT_EXPR: val = (cmp < 0); break;
++	    case LE_EXPR: val = (cmp >= 0); break;
++	    case GE_EXPR: val = (cmp <= 0); break;
++	    default: done = false;
++	    }
++	  if (done)
++	    {
++	      if (val)
++		return boolean_true_node;
++	      else
++		return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	    }
++	}
++
++      /* See if an equality test is redundant with the other comparison.  */
++      else if (code1 == EQ_EXPR)
++	{
++	  bool val;
++	  switch (code2)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp < 0); break;
++	    case GT_EXPR: val = (cmp > 0); break;
++	    case LE_EXPR: val = (cmp <= 0); break;
++	    case GE_EXPR: val = (cmp >= 0); break;
++	    default:
++	      val = false;
++	    }
++	  if (val)
++	    return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	}
++      else if (code2 == EQ_EXPR)
++	{
++	  bool val;
++	  switch (code1)
++	    {
++	    case EQ_EXPR: val = (cmp == 0); break;
++	    case NE_EXPR: val = (cmp != 0); break;
++	    case LT_EXPR: val = (cmp > 0); break;
++	    case GT_EXPR: val = (cmp < 0); break;
++	    case LE_EXPR: val = (cmp >= 0); break;
++	    case GE_EXPR: val = (cmp <= 0); break;
++	    default:
++	      val = false;
++	    }
++	  if (val)
++	    return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	}
++
++      /* Chose the less restrictive of two < or <= comparisons.  */
++      else if ((code1 == LT_EXPR || code1 == LE_EXPR)
++	       && (code2 == LT_EXPR || code2 == LE_EXPR))
++	{
++	  if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR))
++	    return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	  else
++	    return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	}
++
++      /* Likewise chose the less restrictive of two > or >= comparisons.  */
++      else if ((code1 == GT_EXPR || code1 == GE_EXPR)
++	       && (code2 == GT_EXPR || code2 == GE_EXPR))
++	{
++	  if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR))
++	    return fold_build2 (code2, boolean_type_node, op2a, op2b);
++	  else
++	    return fold_build2 (code1, boolean_type_node, op1a, op1b);
++	}
++
++      /* Check for singleton ranges.  */
++      else if (cmp == 0
++	       && ((code1 == LT_EXPR && code2 == GT_EXPR)
++		   || (code1 == GT_EXPR && code2 == LT_EXPR)))
++	return fold_build2 (NE_EXPR, boolean_type_node, op1a, op2b);
++
++      /* Check for less/greater pairs that don't restrict the range at all.  */
++      else if (cmp >= 0
++	       && (code1 == LT_EXPR || code1 == LE_EXPR)
++	       && (code2 == GT_EXPR || code2 == GE_EXPR))
++	return boolean_true_node;
++      else if (cmp <= 0
++	       && (code1 == GT_EXPR || code1 == GE_EXPR)
++	       && (code2 == LT_EXPR || code2 == LE_EXPR))
++	return boolean_true_node;
++    }
++
++  /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where
++     NAME's definition is a truth value.  See if there are any simplifications
++     that can be done against the NAME's definition.  */
++  if (TREE_CODE (op1a) == SSA_NAME
++      && (code1 == NE_EXPR || code1 == EQ_EXPR)
++      && (integer_zerop (op1b) || integer_onep (op1b)))
++    {
++      bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b))
++		     || (code1 == NE_EXPR && integer_onep (op1b)));
++      gimple stmt = SSA_NAME_DEF_STMT (op1a);
++      switch (gimple_code (stmt))
++	{
++	case GIMPLE_ASSIGN:
++	  /* Try to simplify by copy-propagating the definition.  */
++	  return or_var_with_comparison (op1a, invert, code2, op2a, op2b);
++
++	case GIMPLE_PHI:
++	  /* If every argument to the PHI produces the same result when
++	     ORed with the second comparison, we win.
++	     Do not do this unless the type is bool since we need a bool
++	     result here anyway.  */
++	  if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE)
++	    {
++	      tree result = NULL_TREE;
++	      unsigned i;
++	      for (i = 0; i < gimple_phi_num_args (stmt); i++)
++		{
++		  tree arg = gimple_phi_arg_def (stmt, i);
++		  
++		  /* If this PHI has itself as an argument, ignore it.
++		     If all the other args produce the same result,
++		     we're still OK.  */
++		  if (arg == gimple_phi_result (stmt))
++		    continue;
++		  else if (TREE_CODE (arg) == INTEGER_CST)
++		    {
++		      if (invert ? integer_zerop (arg) : integer_nonzerop (arg))
++			{
++			  if (!result)
++			    result = boolean_true_node;
++			  else if (!integer_onep (result))
++			    return NULL_TREE;
++			}
++		      else if (!result)
++			result = fold_build2 (code2, boolean_type_node,
++					      op2a, op2b);
++		      else if (!same_bool_comparison_p (result,
++							code2, op2a, op2b))
++			return NULL_TREE;
++		    }
++		  else if (TREE_CODE (arg) == SSA_NAME)
++		    {
++		      tree temp = or_var_with_comparison (arg, invert,
++							  code2, op2a, op2b);
++		      if (!temp)
++			return NULL_TREE;
++		      else if (!result)
++			result = temp;
++		      else if (!same_bool_result_p (result, temp))
++			return NULL_TREE;
++		    }
++		  else
++		    return NULL_TREE;
++		}
++	      return result;
++	    }
++
++	default:
++	  break;
++	}
++    }
++  return NULL_TREE;
++}
++
++/* Try to simplify the OR of two comparisons, specified by
++   (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively.
++   If this can be simplified to a single expression (without requiring
++   introducing more SSA variables to hold intermediate values),
++   return the resulting tree.  Otherwise return NULL_TREE.
++   If the result expression is non-null, it has boolean type.  */
++
++tree
++maybe_fold_or_comparisons (enum tree_code code1, tree op1a, tree op1b,
++			   enum tree_code code2, tree op2a, tree op2b)
++{
++  tree t = or_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b);
++  if (t)
++    return t;
++  else
++    return or_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b);
++}
++
+ /* Try to optimize out __builtin_stack_restore.  Optimize it out
+    if there is another __builtin_stack_restore in the same basic
+    block and no calls or ASM_EXPRs are in between, or if this block's
+
+=== modified file 'gcc/tree-ssa-ifcombine.c'
+--- old/gcc/tree-ssa-ifcombine.c	2009-11-25 10:55:54 +0000
++++ new/gcc/tree-ssa-ifcombine.c	2010-07-30 13:21:51 +0000
+@@ -366,21 +366,16 @@
+ 
+   /* See if we have two comparisons that we can merge into one.  */
+   else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison
+-	   && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison
+-	   && operand_equal_p (gimple_cond_lhs (inner_cond),
+-			       gimple_cond_lhs (outer_cond), 0)
+-	   && operand_equal_p (gimple_cond_rhs (inner_cond),
+-			       gimple_cond_rhs (outer_cond), 0))
++	   && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison)
+     {
+-      enum tree_code code1 = gimple_cond_code (inner_cond);
+-      enum tree_code code2 = gimple_cond_code (outer_cond);
+       tree t;
+ 
+-      if (!(t = combine_comparisons (UNKNOWN_LOCATION,
+-	      			     TRUTH_ANDIF_EXPR, code1, code2,
+-				     boolean_type_node,
+-				     gimple_cond_lhs (outer_cond),
+-				     gimple_cond_rhs (outer_cond))))
++      if (!(t = maybe_fold_and_comparisons (gimple_cond_code (inner_cond),
++					    gimple_cond_lhs (inner_cond),
++					    gimple_cond_rhs (inner_cond),
++					    gimple_cond_code (outer_cond),
++					    gimple_cond_lhs (outer_cond),
++					    gimple_cond_rhs (outer_cond))))
+ 	return false;
+       t = canonicalize_cond_expr_cond (t);
+       if (!t)
+@@ -518,22 +513,17 @@
+   /* See if we have two comparisons that we can merge into one.
+      This happens for C++ operator overloading where for example
+      GE_EXPR is implemented as GT_EXPR || EQ_EXPR.  */
+-  else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison
+-	   && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison
+-	   && operand_equal_p (gimple_cond_lhs (inner_cond),
+-			       gimple_cond_lhs (outer_cond), 0)
+-	   && operand_equal_p (gimple_cond_rhs (inner_cond),
+-			       gimple_cond_rhs (outer_cond), 0))
++    else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison
++	   && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison)
+     {
+-      enum tree_code code1 = gimple_cond_code (inner_cond);
+-      enum tree_code code2 = gimple_cond_code (outer_cond);
+       tree t;
+ 
+-      if (!(t = combine_comparisons (UNKNOWN_LOCATION,
+-	      			     TRUTH_ORIF_EXPR, code1, code2,
+-				     boolean_type_node,
+-				     gimple_cond_lhs (outer_cond),
+-				     gimple_cond_rhs (outer_cond))))
++      if (!(t = maybe_fold_or_comparisons (gimple_cond_code (inner_cond),
++					   gimple_cond_lhs (inner_cond),
++					   gimple_cond_rhs (inner_cond),
++					   gimple_cond_code (outer_cond),
++					   gimple_cond_lhs (outer_cond),
++					   gimple_cond_rhs (outer_cond))))
+ 	return false;
+       t = canonicalize_cond_expr_cond (t);
+       if (!t)
+
+=== modified file 'gcc/tree-ssa-reassoc.c'
+--- old/gcc/tree-ssa-reassoc.c	2010-01-13 15:04:38 +0000
++++ new/gcc/tree-ssa-reassoc.c	2010-07-30 13:21:51 +0000
+@@ -1159,6 +1159,117 @@
+   return changed;
+ }
+ 
++/* If OPCODE is BIT_IOR_EXPR or BIT_AND_EXPR and CURR is a comparison
++   expression, examine the other OPS to see if any of them are comparisons
++   of the same values, which we may be able to combine or eliminate.
++   For example, we can rewrite (a < b) | (a == b) as (a <= b).  */
++
++static bool
++eliminate_redundant_comparison (enum tree_code opcode,
++				VEC (operand_entry_t, heap) **ops,
++				unsigned int currindex,
++				operand_entry_t curr)
++{
++  tree op1, op2;
++  enum tree_code lcode, rcode;
++  gimple def1, def2;
++  int i;
++  operand_entry_t oe;
++
++  if (opcode != BIT_IOR_EXPR && opcode != BIT_AND_EXPR)
++    return false;
++
++  /* Check that CURR is a comparison.  */
++  if (TREE_CODE (curr->op) != SSA_NAME)
++    return false;
++  def1 = SSA_NAME_DEF_STMT (curr->op);
++  if (!is_gimple_assign (def1))
++    return false;
++  lcode = gimple_assign_rhs_code (def1);
++  if (TREE_CODE_CLASS (lcode) != tcc_comparison)
++    return false;
++  op1 = gimple_assign_rhs1 (def1);
++  op2 = gimple_assign_rhs2 (def1);
++
++  /* Now look for a similar comparison in the remaining OPS.  */
++  for (i = currindex + 1;
++       VEC_iterate (operand_entry_t, *ops, i, oe);
++       i++)
++    {
++      tree t;
++
++      if (TREE_CODE (oe->op) != SSA_NAME)
++	continue;
++      def2 = SSA_NAME_DEF_STMT (oe->op);
++      if (!is_gimple_assign (def2))
++	continue;
++      rcode = gimple_assign_rhs_code (def2);
++      if (TREE_CODE_CLASS (rcode) != tcc_comparison)
++	continue;
++
++      /* If we got here, we have a match.  See if we can combine the
++	 two comparisons.  */
++      if (opcode == BIT_IOR_EXPR)
++	t = maybe_fold_or_comparisons (lcode, op1, op2,
++				       rcode, gimple_assign_rhs1 (def2),
++				       gimple_assign_rhs2 (def2));
++      else
++	t = maybe_fold_and_comparisons (lcode, op1, op2,
++					rcode, gimple_assign_rhs1 (def2),
++					gimple_assign_rhs2 (def2));
++      if (!t)
++	continue;
++
++      /* maybe_fold_and_comparisons and maybe_fold_or_comparisons
++	 always give us a boolean_type_node value back.  If the original
++	 BIT_AND_EXPR or BIT_IOR_EXPR was of a wider integer type,
++	 we need to convert.  */
++      if (!useless_type_conversion_p (TREE_TYPE (curr->op), TREE_TYPE (t)))
++	t = fold_convert (TREE_TYPE (curr->op), t);
++
++      if (dump_file && (dump_flags & TDF_DETAILS))
++	{
++	  fprintf (dump_file, "Equivalence: ");
++	  print_generic_expr (dump_file, curr->op, 0);
++	  fprintf (dump_file, " %s ", op_symbol_code (opcode));
++	  print_generic_expr (dump_file, oe->op, 0);
++	  fprintf (dump_file, " -> ");
++	  print_generic_expr (dump_file, t, 0);
++	  fprintf (dump_file, "\n");
++	}
++
++      /* Now we can delete oe, as it has been subsumed by the new combined
++         expression t.  */
++      VEC_ordered_remove (operand_entry_t, *ops, i);
++      reassociate_stats.ops_eliminated ++;
++
++      /* If t is the same as curr->op, we're done.  Otherwise we must
++	 replace curr->op with t.  Special case is if we got a constant
++	 back, in which case we add it to the end instead of in place of
++	 the current entry.  */
++      if (TREE_CODE (t) == INTEGER_CST)
++	{
++	  VEC_ordered_remove (operand_entry_t, *ops, currindex);
++	  add_to_ops_vec (ops, t);
++	}
++      else if (!operand_equal_p (t, curr->op, 0))
++	{
++	  tree tmpvar;
++	  gimple sum;
++	  enum tree_code subcode;
++	  tree newop1;
++	  tree newop2;
++	  tmpvar = create_tmp_var (TREE_TYPE (t), NULL);
++	  add_referenced_var (tmpvar);
++	  extract_ops_from_tree (t, &subcode, &newop1, &newop2);
++	  sum = build_and_add_sum (tmpvar, newop1, newop2, subcode);
++	  curr->op = gimple_get_lhs (sum);
++	}
++      return true;
++    }
++
++  return false;
++}
+ 
+ /* Perform various identities and other optimizations on the list of
+    operand entries, stored in OPS.  The tree code for the binary
+@@ -1220,7 +1331,8 @@
+       if (eliminate_not_pairs (opcode, ops, i, oe))
+ 	return;
+       if (eliminate_duplicate_pair (opcode, ops, &done, i, oe, oelast)
+-	  || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe)))
++	  || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe))
++	  || (!done && eliminate_redundant_comparison (opcode, ops, i, oe)))
+ 	{
+ 	  if (done)
+ 	    return;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch
new file mode 100644
index 0000000000..9c936d4fad
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch
@@ -0,0 +1,138 @@
+2010-07-12  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+ 
+	2009-10-06  Paul Brook  <paul@codesourcery.com>
+	Issue #3869
+	gcc/
+	* target.h (gcc_target): Add warn_func_result.
+	* target-def.h (TARGET_WARN_FUNC_RESULT): Define and use.
+	* tree-cfg.h (execute_warn_function_return): Use
+	targetm.warn_func_result.
+	* config/arm/arm.c (TARGET_WARN_FUNC_RESULT): Define.
+	(arm_warn_func_result): New function.
+
+	gcc/testuite/
+	 * gcc.target/arm/naked-3.c: New test.
+
+ 2010-07-10  Sandra Loosemore  <sandra@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-07-29 16:58:56 +0000
++++ new/gcc/config/arm/arm.c	2010-07-30 13:58:02 +0000
+@@ -214,6 +214,7 @@
+ static int arm_issue_rate (void);
+ static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
+ static bool arm_allocate_stack_slots_for_args (void);
++static bool arm_warn_func_result (void);
+ static const char *arm_invalid_parameter_type (const_tree t);
+ static const char *arm_invalid_return_type (const_tree t);
+ static tree arm_promoted_type (const_tree t);
+@@ -378,6 +379,9 @@
+ #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
+ #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
+ 
++#undef TARGET_WARN_FUNC_RESULT
++#define TARGET_WARN_FUNC_RESULT arm_warn_func_result
++
+ #undef TARGET_DEFAULT_SHORT_ENUMS
+ #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
+ 
+@@ -2008,6 +2012,14 @@
+   return !IS_NAKED (arm_current_func_type ());
+ }
+ 
++static bool
++arm_warn_func_result (void)
++{
++  /* Naked functions are implemented entirely in assembly, including the
++     return sequence, so suppress warnings about this.  */
++  return !IS_NAKED (arm_current_func_type ());
++}
++
+ 
+ /* Output assembler code for a block containing the constant parts
+    of a trampoline, leaving space for the variable parts.
+
+=== modified file 'gcc/target-def.h'
+--- old/gcc/target-def.h	2010-03-24 20:44:48 +0000
++++ new/gcc/target-def.h	2010-07-30 13:58:02 +0000
+@@ -212,6 +212,10 @@
+ #define TARGET_EXTRA_LIVE_ON_ENTRY hook_void_bitmap
+ #endif
+ 
++#ifndef TARGET_WARN_FUNC_RESULT
++#define TARGET_WARN_FUNC_RESULT hook_bool_void_true
++#endif
++
+ #ifndef TARGET_ASM_FILE_START_APP_OFF
+ #define TARGET_ASM_FILE_START_APP_OFF false
+ #endif
+@@ -1020,6 +1024,7 @@
+   TARGET_EMUTLS,				\
+   TARGET_OPTION_HOOKS,				\
+   TARGET_EXTRA_LIVE_ON_ENTRY,			\
++  TARGET_WARN_FUNC_RESULT,			\
+   TARGET_UNWIND_TABLES_DEFAULT,			\
+   TARGET_HAVE_NAMED_SECTIONS,			\
+   TARGET_HAVE_SWITCHABLE_BSS_SECTIONS,		\
+
+=== modified file 'gcc/target.h'
+--- old/gcc/target.h	2010-03-27 10:27:39 +0000
++++ new/gcc/target.h	2010-07-30 13:58:02 +0000
+@@ -1171,6 +1171,10 @@
+      bits in the bitmap passed in. */
+   void (*live_on_entry) (bitmap);
+ 
++  /* Return false if warnings about missing return statements or suspect
++     noreturn attributes should be suppressed for the current function.  */
++  bool (*warn_func_result) (void);
++
+   /* True if unwinding tables should be generated by default.  */
+   bool unwind_tables_default;
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/naked-3.c'
+--- old/gcc/testsuite/gcc.target/arm/naked-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/naked-3.c	2010-07-30 13:58:02 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -Wall" } */
++/* Check that we do not get warnings about missing return statements
++   or bogus looking noreturn functions.  */
++int __attribute__((naked))
++foo(void)
++{
++  __asm__ volatile ("mov r0, #1\r\nbx lr\n");
++}
++
++int __attribute__((naked,noreturn))
++bar(void)
++{
++  __asm__ volatile ("frob r0\n");
++}
+
+=== modified file 'gcc/tree-cfg.c'
+--- old/gcc/tree-cfg.c	2010-03-16 12:31:38 +0000
++++ new/gcc/tree-cfg.c	2010-07-30 13:58:02 +0000
+@@ -47,6 +47,7 @@
+ #include "value-prof.h"
+ #include "pointer-set.h"
+ #include "tree-inline.h"
++#include "target.h"
+ 
+ /* This file contains functions for building the Control Flow Graph (CFG)
+    for a function tree.  */
+@@ -7092,6 +7093,9 @@
+   edge e;
+   edge_iterator ei;
+ 
++  if (!targetm.warn_func_result())
++    return 0;
++
+   /* If we have a path to EXIT, then we do return.  */
+   if (TREE_THIS_VOLATILE (cfun->decl)
+       && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch
new file mode 100644
index 0000000000..bf35a2ed4e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch
@@ -0,0 +1,112 @@
+2010-07-15  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline (originally from Sourcery G++ 4.4):
+
+	gcc/cp/
+	2010-04-07  Jie Zhang  <jie@codesourcery.com>
+
+	PR c++/42556
+	* typeck2.c (split_nonconstant_init_1): Drop empty CONSTRUCTOR
+	when all of its elements are non-constant and have been split out.
+
+	gcc/testsuite/
+	2010-04-07  Jie Zhang  <jie@codesourcery.com>
+
+	PR c++/42556
+	* g++.dg/init/pr42556.C: New test.
+
+ 2010-07-12  Yao Qi  <yao@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.4:
+
+=== modified file 'gcc/cp/typeck2.c'
+--- old/gcc/cp/typeck2.c	2010-02-23 18:32:20 +0000
++++ new/gcc/cp/typeck2.c	2010-07-30 14:05:57 +0000
+@@ -549,13 +549,15 @@
+    expression to which INIT should be assigned.  INIT is a CONSTRUCTOR.  */
+ 
+ static void
+-split_nonconstant_init_1 (tree dest, tree init)
++split_nonconstant_init_1 (tree dest, tree *initp)
+ {
+   unsigned HOST_WIDE_INT idx;
++  tree init = *initp;
+   tree field_index, value;
+   tree type = TREE_TYPE (dest);
+   tree inner_type = NULL;
+   bool array_type_p = false;
++  HOST_WIDE_INT num_type_elements, num_initialized_elements;
+ 
+   switch (TREE_CODE (type))
+     {
+@@ -567,6 +569,7 @@
+     case RECORD_TYPE:
+     case UNION_TYPE:
+     case QUAL_UNION_TYPE:
++      num_initialized_elements = 0;
+       FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx,
+ 				field_index, value)
+ 	{
+@@ -589,12 +592,13 @@
+ 		sub = build3 (COMPONENT_REF, inner_type, dest, field_index,
+ 			      NULL_TREE);
+ 
+-	      split_nonconstant_init_1 (sub, value);
++	      split_nonconstant_init_1 (sub, &value);
+ 	    }
+ 	  else if (!initializer_constant_valid_p (value, inner_type))
+ 	    {
+ 	      tree code;
+ 	      tree sub;
++	      HOST_WIDE_INT inner_elements;
+ 
+ 	      /* FIXME: Ordered removal is O(1) so the whole function is
+ 		 worst-case quadratic. This could be fixed using an aside
+@@ -617,9 +621,22 @@
+ 	      code = build2 (INIT_EXPR, inner_type, sub, value);
+ 	      code = build_stmt (input_location, EXPR_STMT, code);
+ 	      add_stmt (code);
++
++	      inner_elements = count_type_elements (inner_type, true);
++	      if (inner_elements < 0)
++		num_initialized_elements = -1;
++	      else if (num_initialized_elements >= 0)
++		num_initialized_elements += inner_elements;
+ 	      continue;
+ 	    }
+ 	}
++
++      num_type_elements = count_type_elements (type, true);
++      /* If all elements of the initializer are non-constant and
++	 have been split out, we don't need the empty CONSTRUCTOR.  */
++      if (num_type_elements > 0
++	  && num_type_elements == num_initialized_elements)
++	*initp = NULL;
+       break;
+ 
+     case VECTOR_TYPE:
+@@ -655,7 +672,7 @@
+   if (TREE_CODE (init) == CONSTRUCTOR)
+     {
+       code = push_stmt_list ();
+-      split_nonconstant_init_1 (dest, init);
++      split_nonconstant_init_1 (dest, &init);
+       code = pop_stmt_list (code);
+       DECL_INITIAL (dest) = init;
+       TREE_READONLY (dest) = 0;
+
+=== added file 'gcc/testsuite/g++.dg/init/pr42556.C'
+--- old/gcc/testsuite/g++.dg/init/pr42556.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/init/pr42556.C	2010-07-30 14:05:57 +0000
+@@ -0,0 +1,10 @@
++// { dg-do compile }
++// { dg-options "-fdump-tree-gimple" }
++
++void foo (int a, int b, int c, int d)
++{
++  int v[4] = {a, b, c, d};
++}
++
++// { dg-final { scan-tree-dump-not "v = {}"  "gimple" } }
++// { dg-final { cleanup-tree-dump "gimple" } }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch
new file mode 100644
index 0000000000..da95fba790
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch
@@ -0,0 +1,36 @@
+	Backport from mainline (originally from Sourcery G++ 4.4):
+
+	gcc/
+	2010-07-07  Jie Zhang  <jie@codesourcery.com>
+	* genautomata.c (output_automata_list_min_issue_delay_code):
+	Correctly decompress min_issue_delay.
+
+2010-07-15  Jie Zhang  <jie@codesourcery.com>
+
+ 	Issue #8980
+ 
+ 	Backport from mainline (originally from Sourcery G++ 4.4):
+
+=== modified file 'gcc/genautomata.c'
+--- old/gcc/genautomata.c	2009-11-25 10:55:54 +0000
++++ new/gcc/genautomata.c	2010-07-30 14:21:58 +0000
+@@ -7865,12 +7865,15 @@
+ 	{
+ 	  fprintf (output_file, ") / %d];\n",
+ 		   automaton->min_issue_delay_table_compression_factor);
+-	  fprintf (output_file, "      %s = (%s >> (8 - (",
++	  fprintf (output_file, "      %s = (%s >> (8 - ((",
+ 		   TEMPORARY_VARIABLE_NAME, TEMPORARY_VARIABLE_NAME);
+ 	  output_translate_vect_name (output_file, automaton);
++	  fprintf (output_file, " [%s] + ", INTERNAL_INSN_CODE_NAME);
++	  fprintf (output_file, "%s->", CHIP_PARAMETER_NAME);
++	  output_chip_member_name (output_file, automaton);
++	  fprintf (output_file, " * %d)", automaton->insn_equiv_classes_num);
+ 	  fprintf
+-	    (output_file, " [%s] %% %d + 1) * %d)) & %d;\n",
+-	     INTERNAL_INSN_CODE_NAME,
++	    (output_file, " %% %d + 1) * %d)) & %d;\n",
+ 	     automaton->min_issue_delay_table_compression_factor,
+ 	     8 / automaton->min_issue_delay_table_compression_factor,
+ 	     (1 << (8 / automaton->min_issue_delay_table_compression_factor))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch
new file mode 100644
index 0000000000..9f0c98e9c9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch
@@ -0,0 +1,714 @@
+2010-07-15  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-06-09  Sandra Loosemore  <sandra@codesourcery.com>
+
+	gcc/	
+	* tree-ssa-loop-ivopts.c (adjust_setup_cost): New function.
+	(get_computation_cost_at): Use it.
+	(determine_use_iv_cost_condition): Likewise.
+	(determine_iv_cost): Likewise.
+
+	2010-07-05  Sandra Loosemore  <sandra@codesourcery.com>
+
+	PR middle-end/42505
+
+	gcc/
+	* tree-ssa-loop-ivopts.c (determine_set_costs): Delete obsolete
+	comments about cost model.
+	(try_add_cand_for):  Add second strategy for choosing initial set
+	based on original IVs, controlled by ORIGINALP argument.
+	(get_initial_solution): Add ORIGINALP argument.
+	(find_optimal_iv_set_1): New function, split from find_optimal_iv_set.
+	(find_optimal_iv_set): Try two different strategies for choosing
+	the IV set, and return the one with lower cost.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42505.c: New test case.
+
+	2010-07-10  Sandra Loosemore  <sandra@codesourcery.com>
+
+	PR middle-end/42505
+
+	gcc/
+	* tree-inline.c (estimate_num_insns): Refactor builtin complexity
+	lookup code into....
+	* builtins.c (is_simple_builtin, is_inexpensive_builtin): ...these
+	new functions.
+	* tree.h (is_simple_builtin, is_inexpensive_builtin): Declare.
+	* cfgloopanal.c (target_clobbered_regs): Define.
+	(init_set_costs): Initialize target_clobbered_regs.
+	(estimate_reg_pressure_cost): Add call_p argument.  When true,
+	adjust the number of available registers to exclude the
+	call-clobbered registers.
+	* cfgloop.h (target_clobbered_regs): Declare.
+	(estimate_reg_pressure_cost): Adjust declaration.
+	* tree-ssa-loop-ivopts.c (struct ivopts_data): Add body_includes_call.
+	(ivopts_global_cost_for_size): Pass it to estimate_reg_pressure_cost.
+	(determine_set_costs): Dump target_clobbered_regs.
+	(loop_body_includes_call): New function.
+	(tree_ssa_iv_optimize_loop): Use it to initialize new field.
+	* loop-invariant.c (gain_for_invariant): Adjust arguments to pass
+	call_p flag through.
+	(best_gain_for_invariant): Likewise.
+	(find_invariants_to_move): Likewise.
+	(move_single_loop_invariants): Likewise, using already-computed
+	has_call field.
+
+ 2010-07-15  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Issue #8497, #8893
+
+=== modified file 'gcc/builtins.c'
+--- old/gcc/builtins.c	2010-04-13 12:47:11 +0000
++++ new/gcc/builtins.c	2010-08-02 13:51:23 +0000
+@@ -13624,3 +13624,123 @@
+       break;
+     }
+ }
++
++/* Return true if DECL is a builtin that expands to a constant or similarly
++   simple code.  */
++bool
++is_simple_builtin (tree decl)
++{
++  if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
++    switch (DECL_FUNCTION_CODE (decl))
++      {
++	/* Builtins that expand to constants.  */
++      case BUILT_IN_CONSTANT_P:
++      case BUILT_IN_EXPECT:
++      case BUILT_IN_OBJECT_SIZE:
++      case BUILT_IN_UNREACHABLE:
++	/* Simple register moves or loads from stack.  */
++      case BUILT_IN_RETURN_ADDRESS:
++      case BUILT_IN_EXTRACT_RETURN_ADDR:
++      case BUILT_IN_FROB_RETURN_ADDR:
++      case BUILT_IN_RETURN:
++      case BUILT_IN_AGGREGATE_INCOMING_ADDRESS:
++      case BUILT_IN_FRAME_ADDRESS:
++      case BUILT_IN_VA_END:
++      case BUILT_IN_STACK_SAVE:
++      case BUILT_IN_STACK_RESTORE:
++	/* Exception state returns or moves registers around.  */
++      case BUILT_IN_EH_FILTER:
++      case BUILT_IN_EH_POINTER:
++      case BUILT_IN_EH_COPY_VALUES:
++	return true;
++
++      default:
++	return false;
++      }
++
++  return false;
++}
++
++/* Return true if DECL is a builtin that is not expensive, i.e., they are
++   most probably expanded inline into reasonably simple code.  This is a
++   superset of is_simple_builtin.  */
++bool
++is_inexpensive_builtin (tree decl)
++{
++  if (!decl)
++    return false;
++  else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD)
++    return true;
++  else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
++    switch (DECL_FUNCTION_CODE (decl))
++      {
++      case BUILT_IN_ABS:
++      case BUILT_IN_ALLOCA:
++      case BUILT_IN_BSWAP32:
++      case BUILT_IN_BSWAP64:
++      case BUILT_IN_CLZ:
++      case BUILT_IN_CLZIMAX:
++      case BUILT_IN_CLZL:
++      case BUILT_IN_CLZLL:
++      case BUILT_IN_CTZ:
++      case BUILT_IN_CTZIMAX:
++      case BUILT_IN_CTZL:
++      case BUILT_IN_CTZLL:
++      case BUILT_IN_FFS:
++      case BUILT_IN_FFSIMAX:
++      case BUILT_IN_FFSL:
++      case BUILT_IN_FFSLL:
++      case BUILT_IN_IMAXABS:
++      case BUILT_IN_FINITE:
++      case BUILT_IN_FINITEF:
++      case BUILT_IN_FINITEL:
++      case BUILT_IN_FINITED32:
++      case BUILT_IN_FINITED64:
++      case BUILT_IN_FINITED128:
++      case BUILT_IN_FPCLASSIFY:
++      case BUILT_IN_ISFINITE:
++      case BUILT_IN_ISINF_SIGN:
++      case BUILT_IN_ISINF:
++      case BUILT_IN_ISINFF:
++      case BUILT_IN_ISINFL:
++      case BUILT_IN_ISINFD32:
++      case BUILT_IN_ISINFD64:
++      case BUILT_IN_ISINFD128:
++      case BUILT_IN_ISNAN:
++      case BUILT_IN_ISNANF:
++      case BUILT_IN_ISNANL:
++      case BUILT_IN_ISNAND32:
++      case BUILT_IN_ISNAND64:
++      case BUILT_IN_ISNAND128:
++      case BUILT_IN_ISNORMAL:
++      case BUILT_IN_ISGREATER:
++      case BUILT_IN_ISGREATEREQUAL:
++      case BUILT_IN_ISLESS:
++      case BUILT_IN_ISLESSEQUAL:
++      case BUILT_IN_ISLESSGREATER:
++      case BUILT_IN_ISUNORDERED:
++      case BUILT_IN_VA_ARG_PACK:
++      case BUILT_IN_VA_ARG_PACK_LEN:
++      case BUILT_IN_VA_COPY:
++      case BUILT_IN_TRAP:
++      case BUILT_IN_SAVEREGS:
++      case BUILT_IN_POPCOUNTL:
++      case BUILT_IN_POPCOUNTLL:
++      case BUILT_IN_POPCOUNTIMAX:
++      case BUILT_IN_POPCOUNT:
++      case BUILT_IN_PARITYL:
++      case BUILT_IN_PARITYLL:
++      case BUILT_IN_PARITYIMAX:
++      case BUILT_IN_PARITY:
++      case BUILT_IN_LABS:
++      case BUILT_IN_LLABS:
++      case BUILT_IN_PREFETCH:
++	return true;
++
++      default:
++	return is_simple_builtin (decl);
++      }
++
++  return false;
++}
++
+
+=== modified file 'gcc/cfgloop.h'
+--- old/gcc/cfgloop.h	2009-11-25 10:55:54 +0000
++++ new/gcc/cfgloop.h	2010-08-02 13:51:23 +0000
+@@ -622,13 +622,14 @@
+ /* The properties of the target.  */
+ 
+ extern unsigned target_avail_regs;
++extern unsigned target_clobbered_regs;
+ extern unsigned target_res_regs;
+ extern unsigned target_reg_cost [2];
+ extern unsigned target_spill_cost [2];
+ 
+ /* Register pressure estimation for induction variable optimizations & loop
+    invariant motion.  */
+-extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool);
++extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool, bool);
+ extern void init_set_costs (void);
+ 
+ /* Loop optimizer initialization.  */
+
+=== modified file 'gcc/cfgloopanal.c'
+--- old/gcc/cfgloopanal.c	2009-09-30 08:57:56 +0000
++++ new/gcc/cfgloopanal.c	2010-08-02 13:51:23 +0000
+@@ -320,6 +320,8 @@
+ /* The properties of the target.  */
+ 
+ unsigned target_avail_regs;	/* Number of available registers.  */
++unsigned target_clobbered_regs; /* Number of available registers that are
++				   call-clobbered.  */
+ unsigned target_res_regs;	/* Number of registers reserved for temporary
+ 				   expressions.  */
+ unsigned target_reg_cost[2];	/* The cost for register when there still
+@@ -342,10 +344,15 @@
+   unsigned i;
+ 
+   target_avail_regs = 0;
++  target_clobbered_regs = 0;
+   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i)
+ 	&& !fixed_regs[i])
+-      target_avail_regs++;
++      {
++	target_avail_regs++;
++	if (call_used_regs[i])
++	  target_clobbered_regs++;
++      }
+ 
+   target_res_regs = 3;
+ 
+@@ -379,20 +386,29 @@
+ 
+ /* Estimates cost of increased register pressure caused by making N_NEW new
+    registers live around the loop.  N_OLD is the number of registers live
+-   around the loop.  */
++   around the loop.  If CALL_P is true, also take into account that
++   call-used registers may be clobbered in the loop body, reducing the
++   number of available registers before we spill.  */
+ 
+ unsigned
+-estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed)
++estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
++			    bool call_p)
+ {
+   unsigned cost;
+   unsigned regs_needed = n_new + n_old;
++  unsigned available_regs = target_avail_regs;
++
++  /* If there is a call in the loop body, the call-clobbered registers
++     are not available for loop invariants.  */
++  if (call_p)
++    available_regs = available_regs - target_clobbered_regs;
+ 
+   /* If we have enough registers, we should use them and not restrict
+      the transformations unnecessarily.  */
+-  if (regs_needed + target_res_regs <= target_avail_regs)
++  if (regs_needed + target_res_regs <= available_regs)
+     return 0;
+ 
+-  if (regs_needed <= target_avail_regs)
++  if (regs_needed <= available_regs)
+     /* If we are close to running out of registers, try to preserve
+        them.  */
+     cost = target_reg_cost [speed] * n_new;
+
+=== modified file 'gcc/loop-invariant.c'
+--- old/gcc/loop-invariant.c	2010-04-02 18:54:46 +0000
++++ new/gcc/loop-invariant.c	2010-08-02 13:51:23 +0000
+@@ -1173,11 +1173,13 @@
+ /* Calculates gain for eliminating invariant INV.  REGS_USED is the number
+    of registers used in the loop, NEW_REGS is the number of new variables
+    already added due to the invariant motion.  The number of registers needed
+-   for it is stored in *REGS_NEEDED.  */
++   for it is stored in *REGS_NEEDED.  SPEED and CALL_P are flags passed
++   through to estimate_reg_pressure_cost. */
+ 
+ static int
+ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
+-		    unsigned *new_regs, unsigned regs_used, bool speed)
++		    unsigned *new_regs, unsigned regs_used,
++		    bool speed, bool call_p)
+ {
+   int comp_cost, size_cost;
+ 
+@@ -1188,9 +1190,9 @@
+   if (! flag_ira_loop_pressure)
+     {
+       size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
+-					       regs_used, speed)
++					       regs_used, speed, call_p)
+ 		   - estimate_reg_pressure_cost (new_regs[0],
+-						 regs_used, speed));
++						 regs_used, speed, call_p));
+     }
+   else
+     {
+@@ -1245,7 +1247,8 @@
+ 
+ static int
+ best_gain_for_invariant (struct invariant **best, unsigned *regs_needed,
+-			 unsigned *new_regs, unsigned regs_used, bool speed)
++			 unsigned *new_regs, unsigned regs_used,
++			 bool speed, bool call_p)
+ {
+   struct invariant *inv;
+   int i, gain = 0, again;
+@@ -1261,7 +1264,7 @@
+ 	continue;
+ 
+       again = gain_for_invariant (inv, aregs_needed, new_regs, regs_used,
+-      				  speed);
++      				  speed, call_p);
+       if (again > gain)
+ 	{
+ 	  gain = again;
+@@ -1314,7 +1317,7 @@
+ /* Determines which invariants to move.  */
+ 
+ static void
+-find_invariants_to_move (bool speed)
++find_invariants_to_move (bool speed, bool call_p)
+ {
+   int gain;
+   unsigned i, regs_used, regs_needed[N_REG_CLASSES], new_regs[N_REG_CLASSES];
+@@ -1353,7 +1356,8 @@
+ 	new_regs[ira_reg_class_cover[i]] = 0;
+     }
+   while ((gain = best_gain_for_invariant (&inv, regs_needed,
+-					  new_regs, regs_used, speed)) > 0)
++					  new_regs, regs_used,
++					  speed, call_p)) > 0)
+     {
+       set_move_mark (inv->invno, gain);
+       if (! flag_ira_loop_pressure)
+@@ -1554,7 +1558,8 @@
+   init_inv_motion_data ();
+ 
+   find_invariants (loop);
+-  find_invariants_to_move (optimize_loop_for_speed_p (loop));
++  find_invariants_to_move (optimize_loop_for_speed_p (loop),
++			   LOOP_DATA (loop)->has_call);
+   move_invariants (loop);
+ 
+   free_inv_motion_data ();
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr42505.c'
+--- old/gcc/testsuite/gcc.target/arm/pr42505.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr42505.c	2010-08-02 13:51:23 +0000
+@@ -0,0 +1,23 @@
++/* { dg-options "-mthumb -Os -march=armv5te" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */
++
++struct A {
++ int f1;
++ int f2;
++};
++
++int func(int c);
++
++/* This function should not need to spill anything to the stack.  */
++int test(struct A* src, struct A* dst, int count)
++{
++  while (count--) {
++    if (!func(src->f2)) {
++        return 0;
++      }
++      *dst++ = *src++;
++  }
++
++  return 1;
++}
+
+=== modified file 'gcc/tree-inline.c'
+--- old/gcc/tree-inline.c	2010-03-18 20:07:13 +0000
++++ new/gcc/tree-inline.c	2010-08-02 13:51:23 +0000
+@@ -3246,34 +3246,13 @@
+ 	if (POINTER_TYPE_P (funtype))
+ 	  funtype = TREE_TYPE (funtype);
+ 
+-	if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD)
++	if (is_simple_builtin (decl))
++	  return 0;
++	else if (is_inexpensive_builtin (decl))
+ 	  cost = weights->target_builtin_call_cost;
+ 	else
+ 	  cost = weights->call_cost;
+ 
+-	if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
+-	  switch (DECL_FUNCTION_CODE (decl))
+-	    {
+-	    case BUILT_IN_CONSTANT_P:
+-	      return 0;
+-	    case BUILT_IN_EXPECT:
+-	      return 0;
+-
+-	    /* Prefetch instruction is not expensive.  */
+-	    case BUILT_IN_PREFETCH:
+-	      cost = weights->target_builtin_call_cost;
+-	      break;
+-
+-	    /* Exception state returns or moves registers around.  */
+-	    case BUILT_IN_EH_FILTER:
+-	    case BUILT_IN_EH_POINTER:
+-	    case BUILT_IN_EH_COPY_VALUES:
+-	      return 0;
+-
+-	    default:
+-	      break;
+-	    }
+-
+ 	if (decl)
+ 	  funtype = TREE_TYPE (decl);
+ 
+
+=== modified file 'gcc/tree-ssa-loop-ivopts.c'
+--- old/gcc/tree-ssa-loop-ivopts.c	2010-04-01 15:18:07 +0000
++++ new/gcc/tree-ssa-loop-ivopts.c	2010-08-02 13:51:23 +0000
+@@ -257,6 +257,9 @@
+ 
+   /* Are we optimizing for speed?  */
+   bool speed;
++
++  /* Whether the loop body includes any function calls.  */
++  bool body_includes_call;
+ };
+ 
+ /* An assignment of iv candidates to uses.  */
+@@ -2926,6 +2929,20 @@
+   return get_computation_at (loop, use, cand, use->stmt);
+ }
+ 
++/* Adjust the cost COST for being in loop setup rather than loop body.
++   If we're optimizing for space, the loop setup overhead is constant;
++   if we're optimizing for speed, amortize it over the per-iteration cost.  */
++static unsigned
++adjust_setup_cost (struct ivopts_data *data, unsigned cost)
++{
++  if (cost == INFTY)
++    return cost;
++  else if (optimize_loop_for_speed_p (data->current_loop))
++    return cost / AVG_LOOP_NITER (data->current_loop);
++  else
++    return cost;
++}
++
+ /* Returns cost of addition in MODE.  */
+ 
+ static unsigned
+@@ -3838,8 +3855,8 @@
+   /* Symbol + offset should be compile-time computable so consider that they
+       are added once to the variable, if present.  */
+   if (var_present && (symbol_present || offset))
+-    cost.cost += add_cost (TYPE_MODE (ctype), speed)
+-		 / AVG_LOOP_NITER (data->current_loop);
++    cost.cost += adjust_setup_cost (data,
++				    add_cost (TYPE_MODE (ctype), speed));
+ 
+   /* Having offset does not affect runtime cost in case it is added to
+      symbol, but it increases complexity.  */
+@@ -4104,7 +4121,7 @@
+       elim_cost = force_var_cost (data, bound, &depends_on_elim);
+       /* The bound is a loop invariant, so it will be only computed
+ 	 once.  */
+-      elim_cost.cost /= AVG_LOOP_NITER (data->current_loop);
++      elim_cost.cost = adjust_setup_cost (data, elim_cost.cost);
+     }
+   else
+     elim_cost = infinite_cost;
+@@ -4351,7 +4368,7 @@
+   cost_base = force_var_cost (data, base, NULL);
+   cost_step = add_cost (TYPE_MODE (TREE_TYPE (base)), data->speed);
+ 
+-  cost = cost_step + cost_base.cost / AVG_LOOP_NITER (current_loop);
++  cost = cost_step + adjust_setup_cost (data, cost_base.cost);
+ 
+   /* Prefer the original ivs unless we may gain something by replacing it.
+      The reason is to make debugging simpler; so this is not relevant for
+@@ -4404,7 +4421,8 @@
+ {
+   /* We add size to the cost, so that we prefer eliminating ivs
+      if possible.  */
+-  return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed);
++  return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed,
++					    data->body_includes_call);
+ }
+ 
+ /* For each size of the induction variable set determine the penalty.  */
+@@ -4419,30 +4437,11 @@
+   struct loop *loop = data->current_loop;
+   bitmap_iterator bi;
+ 
+-  /* We use the following model (definitely improvable, especially the
+-     cost function -- TODO):
+-
+-     We estimate the number of registers available (using MD data), name it A.
+-
+-     We estimate the number of registers used by the loop, name it U.  This
+-     number is obtained as the number of loop phi nodes (not counting virtual
+-     registers and bivs) + the number of variables from outside of the loop.
+-
+-     We set a reserve R (free regs that are used for temporary computations,
+-     etc.).  For now the reserve is a constant 3.
+-
+-     Let I be the number of induction variables.
+-
+-     -- if U + I + R <= A, the cost is I * SMALL_COST (just not to encourage
+-	make a lot of ivs without a reason).
+-     -- if A - R < U + I <= A, the cost is I * PRES_COST
+-     -- if U + I > A, the cost is I * PRES_COST and
+-        number of uses * SPILL_COST * (U + I - A) / (U + I) is added.  */
+-
+   if (dump_file && (dump_flags & TDF_DETAILS))
+     {
+       fprintf (dump_file, "Global costs:\n");
+       fprintf (dump_file, "  target_avail_regs %d\n", target_avail_regs);
++      fprintf (dump_file, "  target_clobbered_regs %d\n", target_clobbered_regs);
+       fprintf (dump_file, "  target_reg_cost %d\n", target_reg_cost[data->speed]);
+       fprintf (dump_file, "  target_spill_cost %d\n", target_spill_cost[data->speed]);
+     }
+@@ -5062,11 +5061,13 @@
+ }
+ 
+ /* Tries to extend the sets IVS in the best possible way in order
+-   to express the USE.  */
++   to express the USE.  If ORIGINALP is true, prefer candidates from
++   the original set of IVs, otherwise favor important candidates not
++   based on any memory object.  */
+ 
+ static bool
+ try_add_cand_for (struct ivopts_data *data, struct iv_ca *ivs,
+-		  struct iv_use *use)
++		  struct iv_use *use, bool originalp)
+ {
+   comp_cost best_cost, act_cost;
+   unsigned i;
+@@ -5085,7 +5086,8 @@
+       iv_ca_set_no_cp (data, ivs, use);
+     }
+ 
+-  /* First try important candidates not based on any memory object.  Only if
++  /* If ORIGINALP is true, try to find the original IV for the use.  Otherwise
++     first try important candidates not based on any memory object.  Only if
+      this fails, try the specific ones.  Rationale -- in loops with many
+      variables the best choice often is to use just one generic biv.  If we
+      added here many ivs specific to the uses, the optimization algorithm later
+@@ -5097,7 +5099,10 @@
+     {
+       cand = iv_cand (data, i);
+ 
+-      if (cand->iv->base_object != NULL_TREE)
++      if (originalp && cand->pos !=IP_ORIGINAL)
++	continue;
++
++      if (!originalp && cand->iv->base_object != NULL_TREE)
+ 	continue;
+ 
+       if (iv_ca_cand_used_p (ivs, cand))
+@@ -5133,8 +5138,13 @@
+ 	    continue;
+ 
+ 	  /* Already tried this.  */
+-	  if (cand->important && cand->iv->base_object == NULL_TREE)
+-	    continue;
++	  if (cand->important)
++	    {
++	      if (originalp && cand->pos == IP_ORIGINAL)
++		continue;
++	      if (!originalp && cand->iv->base_object == NULL_TREE)
++		continue;
++	    }
+ 
+ 	  if (iv_ca_cand_used_p (ivs, cand))
+ 	    continue;
+@@ -5168,13 +5178,13 @@
+ /* Finds an initial assignment of candidates to uses.  */
+ 
+ static struct iv_ca *
+-get_initial_solution (struct ivopts_data *data)
++get_initial_solution (struct ivopts_data *data, bool originalp)
+ {
+   struct iv_ca *ivs = iv_ca_new (data);
+   unsigned i;
+ 
+   for (i = 0; i < n_iv_uses (data); i++)
+-    if (!try_add_cand_for (data, ivs, iv_use (data, i)))
++    if (!try_add_cand_for (data, ivs, iv_use (data, i), originalp))
+       {
+ 	iv_ca_free (&ivs);
+ 	return NULL;
+@@ -5246,14 +5256,12 @@
+    solution and remove the unused ivs while this improves the cost.  */
+ 
+ static struct iv_ca *
+-find_optimal_iv_set (struct ivopts_data *data)
++find_optimal_iv_set_1 (struct ivopts_data *data, bool originalp)
+ {
+-  unsigned i;
+   struct iv_ca *set;
+-  struct iv_use *use;
+ 
+   /* Get the initial solution.  */
+-  set = get_initial_solution (data);
++  set = get_initial_solution (data, originalp);
+   if (!set)
+     {
+       if (dump_file && (dump_flags & TDF_DETAILS))
+@@ -5276,11 +5284,46 @@
+ 	}
+     }
+ 
++  return set;
++}
++
++static struct iv_ca *
++find_optimal_iv_set (struct ivopts_data *data)
++{
++  unsigned i;
++  struct iv_ca *set, *origset;
++  struct iv_use *use;
++  comp_cost cost, origcost;
++
++  /* Determine the cost based on a strategy that starts with original IVs,
++     and try again using a strategy that prefers candidates not based
++     on any IVs.  */
++  origset = find_optimal_iv_set_1 (data, true);
++  set = find_optimal_iv_set_1 (data, false);
++
++  if (!origset && !set)
++    return NULL;
++
++  origcost = origset ? iv_ca_cost (origset) : infinite_cost;
++  cost = set ? iv_ca_cost (set) : infinite_cost;
++
+   if (dump_file && (dump_flags & TDF_DETAILS))
+     {
+-      comp_cost cost = iv_ca_cost (set);
+-      fprintf (dump_file, "Final cost %d (complexity %d)\n\n", cost.cost, cost.complexity);
+-    }
++      fprintf (dump_file, "Original cost %d (complexity %d)\n\n",
++	       origcost.cost, origcost.complexity);
++      fprintf (dump_file, "Final cost %d (complexity %d)\n\n",
++	       cost.cost, cost.complexity);
++    }
++
++  /* Choose the one with the best cost.  */
++  if (compare_costs (origcost, cost) <= 0)
++    {
++      if (set)
++	iv_ca_free (&set);
++      set = origset;
++    }
++  else if (origset)
++    iv_ca_free (&origset);
+ 
+   for (i = 0; i < n_iv_uses (data); i++)
+     {
+@@ -5768,6 +5811,25 @@
+   VEC_free (iv_cand_p, heap, data->iv_candidates);
+ }
+ 
++/* Returns true if the loop body BODY includes any function calls.  */
++
++static bool
++loop_body_includes_call (basic_block *body, unsigned num_nodes)
++{
++  gimple_stmt_iterator gsi;
++  unsigned i;
++
++  for (i = 0; i < num_nodes; i++)
++    for (gsi = gsi_start_bb (body[i]); !gsi_end_p (gsi); gsi_next (&gsi))
++      {
++	gimple stmt = gsi_stmt (gsi);
++	if (is_gimple_call (stmt)
++	    && !is_inexpensive_builtin (gimple_call_fndecl (stmt)))
++	  return true;
++      }
++  return false;
++}
++
+ /* Optimizes the LOOP.  Returns true if anything changed.  */
+ 
+ static bool
+@@ -5799,6 +5861,7 @@
+     }
+ 
+   body = get_loop_body (loop);
++  data->body_includes_call = loop_body_includes_call (body, loop->num_nodes);
+   renumber_gimple_stmt_uids_in_blocks (body, loop->num_nodes);
+   free (body);
+ 
+
+=== modified file 'gcc/tree.h'
+--- old/gcc/tree.h	2010-04-02 18:54:46 +0000
++++ new/gcc/tree.h	2010-08-02 13:51:23 +0000
+@@ -4962,6 +4962,8 @@
+ extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int,
+ 			  tree, tree);
+ extern void set_builtin_user_assembler_name (tree decl, const char *asmspec);
++extern bool is_simple_builtin (tree);
++extern bool is_inexpensive_builtin (tree);
+ 
+ /* In convert.c */
+ extern tree strip_float_extensions (tree);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch
new file mode 100644
index 0000000000..eadce6ec6c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch
@@ -0,0 +1,37 @@
+2010-07-15  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	2010-02-25  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	gcc/
+	* tree.c (initializer_zerop): Handle STRING_CST.
+
+ 2010-07-15  Sandra Loosemore  <sandra@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/tree.c'
+--- old/gcc/tree.c	2010-04-01 15:18:07 +0000
++++ new/gcc/tree.c	2010-08-02 16:32:37 +0000
+@@ -9335,6 +9335,19 @@
+ 	return true;
+       }
+ 
++    case STRING_CST:
++      {
++	int i;
++
++	/* We need to loop through all elements to handle cases like
++	   "\0" and "\0foobar".  */
++	for (i = 0; i < TREE_STRING_LENGTH (init); ++i)
++	  if (TREE_STRING_POINTER (init)[i] != '\0')
++	    return false;
++
++	return true;
++      }
++
+     default:
+       return false;
+     }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch
new file mode 100644
index 0000000000..216fcac723
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch
@@ -0,0 +1,433 @@
+2010-07-16  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #7688
+
+	Backport from mainline:
+
+	gcc/
+	2010-07-12  Jie Zhang  <jie@codesourcery.com>
+	* postreload.c (reg_symbol_ref[]): New.
+	(move2add_use_add2_insn): New.
+	(move2add_use_add3_insn): New.
+	(reload_cse_move2add): Handle SYMBOL + OFFSET case.
+	(move2add_note_store): Likewise.
+
+ 2010-07-15  Yao Qi  <yao@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.4:
+
+=== modified file 'gcc/postreload.c'
+--- old/gcc/postreload.c	2010-03-16 10:50:42 +0000
++++ new/gcc/postreload.c	2010-08-02 16:55:34 +0000
+@@ -1160,17 +1160,19 @@
+    information about register contents we have would be costly, so we
+    use move2add_last_label_luid to note where the label is and then
+    later disable any optimization that would cross it.
+-   reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
+-   reg_set_luid[n] is greater than move2add_last_label_luid.  */
++   reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
++   are only valid if reg_set_luid[n] is greater than
++   move2add_last_label_luid.  */
+ static int reg_set_luid[FIRST_PSEUDO_REGISTER];
+ 
+ /* If reg_base_reg[n] is negative, register n has been set to
+-   reg_offset[n] in mode reg_mode[n] .
++   reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
+    If reg_base_reg[n] is non-negative, register n has been set to the
+    sum of reg_offset[n] and the value of register reg_base_reg[n]
+    before reg_set_luid[n], calculated in mode reg_mode[n] .  */
+ static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
+ static int reg_base_reg[FIRST_PSEUDO_REGISTER];
++static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
+ static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
+ 
+ /* move2add_luid is linearly increased while scanning the instructions
+@@ -1190,6 +1192,151 @@
+        && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
+ 				 GET_MODE_BITSIZE (INMODE))))
+ 
++/* This function is called with INSN that sets REG to (SYM + OFF),
++   while REG is known to already have value (SYM + offset).
++   This function tries to change INSN into an add instruction
++   (set (REG) (plus (REG) (OFF - offset))) using the known value.
++   It also updates the information about REG's known value.  */
++
++static void
++move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
++{
++  rtx pat = PATTERN (insn);
++  rtx src = SET_SRC (pat);
++  int regno = REGNO (reg);
++  rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
++			      GET_MODE (reg));
++  bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
++
++  /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
++     use (set (reg) (reg)) instead.
++     We don't delete this insn, nor do we convert it into a
++     note, to avoid losing register notes or the return
++     value flag.  jump2 already knows how to get rid of
++     no-op moves.  */
++  if (new_src == const0_rtx)
++    {
++      /* If the constants are different, this is a
++	 truncation, that, if turned into (set (reg)
++	 (reg)), would be discarded.  Maybe we should
++	 try a truncMN pattern?  */
++      if (INTVAL (off) == reg_offset [regno])
++	validate_change (insn, &SET_SRC (pat), reg, 0);
++    }
++  else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
++	   && have_add2_insn (reg, new_src))
++    {
++      rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
++      validate_change (insn, &SET_SRC (pat), tem, 0);
++    }
++  else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
++    {
++      enum machine_mode narrow_mode;
++      for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
++	   narrow_mode != VOIDmode
++	     && narrow_mode != GET_MODE (reg);
++	   narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
++	{
++	  if (have_insn_for (STRICT_LOW_PART, narrow_mode)
++	      && ((reg_offset[regno]
++		   & ~GET_MODE_MASK (narrow_mode))
++		  == (INTVAL (off)
++		      & ~GET_MODE_MASK (narrow_mode))))
++	    {
++	      rtx narrow_reg = gen_rtx_REG (narrow_mode,
++					    REGNO (reg));
++	      rtx narrow_src = gen_int_mode (INTVAL (off),
++					     narrow_mode);
++	      rtx new_set =
++		gen_rtx_SET (VOIDmode,
++			     gen_rtx_STRICT_LOW_PART (VOIDmode,
++						      narrow_reg),
++			     narrow_src);
++	      if (validate_change (insn, &PATTERN (insn),
++				   new_set, 0))
++		break;
++	    }
++	}
++    }
++  reg_set_luid[regno] = move2add_luid;
++  reg_base_reg[regno] = -1;
++  reg_mode[regno] = GET_MODE (reg);
++  reg_symbol_ref[regno] = sym;
++  reg_offset[regno] = INTVAL (off);
++}
++
++
++/* This function is called with INSN that sets REG to (SYM + OFF),
++   but REG doesn't have known value (SYM + offset).  This function
++   tries to find another register which is known to already have
++   value (SYM + offset) and change INSN into an add instruction
++   (set (REG) (plus (the found register) (OFF - offset))) if such
++   a register is found.  It also updates the information about
++   REG's known value.  */
++
++static void
++move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
++{
++  rtx pat = PATTERN (insn);
++  rtx src = SET_SRC (pat);
++  int regno = REGNO (reg);
++  int min_cost = INT_MAX;
++  int min_regno;
++  bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
++  int i;
++
++  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
++    if (reg_set_luid[i] > move2add_last_label_luid
++	&& reg_mode[i] == GET_MODE (reg)
++	&& reg_base_reg[i] < 0
++	&& reg_symbol_ref[i] != NULL_RTX
++	&& rtx_equal_p (sym, reg_symbol_ref[i]))
++      {
++	rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
++				    GET_MODE (reg));
++	/* (set (reg) (plus (reg) (const_int 0))) is not canonical;
++	   use (set (reg) (reg)) instead.
++	   We don't delete this insn, nor do we convert it into a
++	   note, to avoid losing register notes or the return
++	   value flag.  jump2 already knows how to get rid of
++	   no-op moves.  */
++	if (new_src == const0_rtx)
++	  {
++	    min_cost = 0;
++	    min_regno = i;
++	    break;
++	  }
++	else
++	  {
++	    int cost = rtx_cost (new_src, PLUS, speed);
++	    if (cost < min_cost)
++	      {
++		min_cost = cost;
++		min_regno = i;
++	      }
++	  }
++      }
++
++  if (min_cost < rtx_cost (src, SET, speed))
++    {
++      rtx tem;
++
++      tem = gen_rtx_REG (GET_MODE (reg), min_regno);
++      if (i != min_regno)
++	{
++	  rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
++				      GET_MODE (reg));
++	  tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
++	}
++      validate_change (insn, &SET_SRC (pat), tem, 0);
++    }
++  reg_set_luid[regno] = move2add_luid;
++  reg_base_reg[regno] = -1;
++  reg_mode[regno] = GET_MODE (reg);
++  reg_symbol_ref[regno] = sym;
++  reg_offset[regno] = INTVAL (off);
++}
++
+ static void
+ reload_cse_move2add (rtx first)
+ {
+@@ -1197,7 +1344,13 @@
+   rtx insn;
+ 
+   for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
+-    reg_set_luid[i] = 0;
++    {
++      reg_set_luid[i] = 0;
++      reg_offset[i] = 0;
++      reg_base_reg[i] = 0;
++      reg_symbol_ref[i] = NULL_RTX;
++      reg_mode[i] = VOIDmode;
++    }
+ 
+   move2add_last_label_luid = 0;
+   move2add_luid = 2;
+@@ -1245,65 +1398,11 @@
+ 				  (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
+ 	      */
+ 
+-	      if (CONST_INT_P (src) && reg_base_reg[regno] < 0)
++	      if (CONST_INT_P (src)
++		  && reg_base_reg[regno] < 0
++		  && reg_symbol_ref[regno] == NULL_RTX)
+ 		{
+-		  rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno],
+-					      GET_MODE (reg));
+-		  bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+-
+-		  /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
+-		     use (set (reg) (reg)) instead.
+-		     We don't delete this insn, nor do we convert it into a
+-		     note, to avoid losing register notes or the return
+-		     value flag.  jump2 already knows how to get rid of
+-		     no-op moves.  */
+-		  if (new_src == const0_rtx)
+-		    {
+-		      /* If the constants are different, this is a
+-			 truncation, that, if turned into (set (reg)
+-			 (reg)), would be discarded.  Maybe we should
+-			 try a truncMN pattern?  */
+-		      if (INTVAL (src) == reg_offset [regno])
+-			validate_change (insn, &SET_SRC (pat), reg, 0);
+-		    }
+-		  else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
+-			   && have_add2_insn (reg, new_src))
+-		    {
+-		      rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
+-		      validate_change (insn, &SET_SRC (pat), tem, 0);
+-		    }
+-		  else if (GET_MODE (reg) != BImode)
+-		    {
+-		      enum machine_mode narrow_mode;
+-		      for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
+-			   narrow_mode != VOIDmode
+-			   && narrow_mode != GET_MODE (reg);
+-			   narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
+-			{
+-			  if (have_insn_for (STRICT_LOW_PART, narrow_mode)
+-			      && ((reg_offset[regno]
+-				   & ~GET_MODE_MASK (narrow_mode))
+-				  == (INTVAL (src)
+-				      & ~GET_MODE_MASK (narrow_mode))))
+-			    {
+-			      rtx narrow_reg = gen_rtx_REG (narrow_mode,
+-							    REGNO (reg));
+-			      rtx narrow_src = gen_int_mode (INTVAL (src),
+-							     narrow_mode);
+-			      rtx new_set =
+-				gen_rtx_SET (VOIDmode,
+-					     gen_rtx_STRICT_LOW_PART (VOIDmode,
+-								      narrow_reg),
+-					     narrow_src);
+-			      if (validate_change (insn, &PATTERN (insn),
+-						   new_set, 0))
+-				break;
+-			    }
+-			}
+-		    }
+-		  reg_set_luid[regno] = move2add_luid;
+-		  reg_mode[regno] = GET_MODE (reg);
+-		  reg_offset[regno] = INTVAL (src);
++		  move2add_use_add2_insn (reg, NULL_RTX, src, insn);
+ 		  continue;
+ 		}
+ 
+@@ -1373,6 +1472,51 @@
+ 		    }
+ 		}
+ 	    }
++
++	  /* Try to transform
++	     (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
++	     ...
++	     (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
++	     to
++	     (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
++	     ...
++	     (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A))))  */
++	  if ((GET_CODE (src) == SYMBOL_REF
++	       || (GET_CODE (src) == CONST
++		   && GET_CODE (XEXP (src, 0)) == PLUS
++		   && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
++		   && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
++	      && dbg_cnt (cse2_move2add))
++	    {
++	      rtx sym, off;
++
++	      if (GET_CODE (src) == SYMBOL_REF)
++		{
++		  sym = src;
++		  off = const0_rtx;
++		}
++	      else
++		{
++		  sym = XEXP (XEXP (src, 0), 0);
++		  off = XEXP (XEXP (src, 0), 1);
++		}
++
++	      /* If the reg already contains the value which is sum of
++		 sym and some constant value, we can use an add2 insn.  */
++	      if (reg_set_luid[regno] > move2add_last_label_luid
++		  && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
++		  && reg_base_reg[regno] < 0
++		  && reg_symbol_ref[regno] != NULL_RTX
++		  && rtx_equal_p (sym, reg_symbol_ref[regno]))
++		move2add_use_add2_insn (reg, sym, off, insn);
++
++	      /* Otherwise, we have to find a register whose value is sum
++		 of sym and some constant value.  */
++	      else
++		move2add_use_add3_insn (reg, sym, off, insn);
++
++	      continue;
++	    }
+ 	}
+ 
+       for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+@@ -1386,7 +1530,7 @@
+ 		reg_set_luid[regno] = 0;
+ 	    }
+ 	}
+-      note_stores (PATTERN (insn), move2add_note_store, NULL);
++      note_stores (PATTERN (insn), move2add_note_store, insn);
+ 
+       /* If INSN is a conditional branch, we try to extract an
+ 	 implicit set out of it.  */
+@@ -1408,7 +1552,7 @@
+ 	    {
+ 	      rtx implicit_set =
+ 		gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
+-	      move2add_note_store (SET_DEST (implicit_set), implicit_set, 0);
++	      move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
+ 	    }
+ 	}
+ 
+@@ -1426,13 +1570,15 @@
+     }
+ }
+ 
+-/* SET is a SET or CLOBBER that sets DST.
++/* SET is a SET or CLOBBER that sets DST.  DATA is the insn which
++   contains SET.
+    Update reg_set_luid, reg_offset and reg_base_reg accordingly.
+    Called from reload_cse_move2add via note_stores.  */
+ 
+ static void
+-move2add_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
++move2add_note_store (rtx dst, const_rtx set, void *data)
+ {
++  rtx insn = (rtx) data;
+   unsigned int regno = 0;
+   unsigned int nregs = 0;
+   unsigned int i;
+@@ -1466,6 +1612,38 @@
+     nregs = hard_regno_nregs[regno][mode];
+ 
+   if (SCALAR_INT_MODE_P (GET_MODE (dst))
++      && nregs == 1 && GET_CODE (set) == SET)
++    {
++      rtx note, sym = NULL_RTX;
++      HOST_WIDE_INT off;
++
++      note = find_reg_equal_equiv_note (insn);
++      if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
++	{
++	  sym = XEXP (note, 0);
++	  off = 0;
++	}
++      else if (note && GET_CODE (XEXP (note, 0)) == CONST
++	       && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
++	       && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
++	       && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
++	{
++	  sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
++	  off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1));
++	}
++
++      if (sym != NULL_RTX)
++	{
++	  reg_base_reg[regno] = -1;
++	  reg_symbol_ref[regno] = sym;
++	  reg_offset[regno] = off;
++	  reg_mode[regno] = mode;
++	  reg_set_luid[regno] = move2add_luid;
++	  return;
++	}
++    }
++
++  if (SCALAR_INT_MODE_P (GET_MODE (dst))
+       && nregs == 1 && GET_CODE (set) == SET
+       && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
+       && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
+@@ -1525,6 +1703,7 @@
+ 	case CONST_INT:
+ 	  /* Start tracking the register as a constant.  */
+ 	  reg_base_reg[regno] = -1;
++	  reg_symbol_ref[regno] = NULL_RTX;
+ 	  reg_offset[regno] = INTVAL (SET_SRC (set));
+ 	  /* We assign the same luid to all registers set to constants.  */
+ 	  reg_set_luid[regno] = move2add_last_label_luid + 1;
+@@ -1545,6 +1724,7 @@
+       if (reg_set_luid[base_regno] <= move2add_last_label_luid)
+ 	{
+ 	  reg_base_reg[base_regno] = base_regno;
++	  reg_symbol_ref[base_regno] = NULL_RTX;
+ 	  reg_offset[base_regno] = 0;
+ 	  reg_set_luid[base_regno] = move2add_luid;
+ 	  reg_mode[base_regno] = mode;
+@@ -1558,6 +1738,7 @@
+       /* Copy base information from our base register.  */
+       reg_set_luid[regno] = reg_set_luid[base_regno];
+       reg_base_reg[regno] = reg_base_reg[base_regno];
++      reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
+ 
+       /* Compute the sum of the offsets or constants.  */
+       reg_offset[regno] = trunc_int_for_mode (offset
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch
new file mode 100644
index 0000000000..3d5dd5f9ab
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch
@@ -0,0 +1,57 @@
+2010-08-03  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/
+	2010-07-28  Chung-Lin Tang  <cltang@codesourcery.com>
+	* config/arm/arm.c (arm_pcs_default): Remove static.	
+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_PCS or
+	__ARM_PCS_VFP to indicate soft/hard-float calling convention.
+	(arm_pcs_default): Declare.
+
+ 2010-07-16  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Issue #7688
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-02 13:42:24 +0000
++++ new/gcc/config/arm/arm.c	2010-08-03 13:55:46 +0000
+@@ -704,7 +704,7 @@
+ /* The maximum number of insns to be used when loading a constant.  */
+ static int arm_constant_limit = 3;
+ 
+-static enum arm_pcs arm_pcs_default;
++enum arm_pcs arm_pcs_default;
+ 
+ /* For an explanation of these variables, see final_prescan_insn below.  */
+ int arm_ccfsm_state;
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-07-29 16:58:56 +0000
++++ new/gcc/config/arm/arm.h	2010-08-03 10:40:56 +0000
+@@ -94,7 +94,13 @@
+ 	if (arm_arch_iwmmxt)				\
+ 	  builtin_define ("__IWMMXT__");		\
+ 	if (TARGET_AAPCS_BASED)				\
+-	  builtin_define ("__ARM_EABI__");		\
++	  {						\
++	    if (arm_pcs_default == ARM_PCS_AAPCS_VFP)	\
++	      builtin_define ("__ARM_PCS_VFP");		\
++	    else if (arm_pcs_default == ARM_PCS_AAPCS)	\
++	      builtin_define ("__ARM_PCS");		\
++	    builtin_define ("__ARM_EABI__");		\
++	  }						\
+     } while (0)
+ 
+ /* The various ARM cores.  */
+@@ -1648,6 +1654,9 @@
+   ARM_PCS_UNKNOWN
+ };
+ 
++/* Default procedure calling standard of current compilation unit. */
++extern enum arm_pcs arm_pcs_default;
++
+ /* A C type for declaring a variable that is used as the first argument of
+    `FUNCTION_ARG' and other related values.  */
+ typedef struct
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch
new file mode 100644
index 0000000000..c7f92b6fcb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch
@@ -0,0 +1,76 @@
+2010-07-20  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+	2010-06-07  Kazu Hirata  <kazu@codesourcery.com>
+
+	Issue #8535
+
+	Backport from mainline:
+	gcc/
+	2010-06-07  Kazu Hirata  <kazu@codesourcery.com>
+	PR rtl-optimization/44404
+	* auto-inc-dec.c (find_inc): Use reg_overlap_mentioned_p instead
+	of count_occurrences to see if it's safe to modify mem_insn.insn.
+
+	gcc/testsuite/
+	2010-06-07  Kazu Hirata  <kazu@codesourcery.com>
+	PR rtl-optimization/44404
+	* gcc.dg/pr44404.c: New.
+
+ 2010-08-03  Chung-Lin Tang  <cltang@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/auto-inc-dec.c'
+--- old/gcc/auto-inc-dec.c	2010-04-02 18:54:46 +0000
++++ new/gcc/auto-inc-dec.c	2010-08-05 11:30:21 +0000
+@@ -1068,7 +1068,7 @@
+       /* For the post_add to work, the result_reg of the inc must not be
+ 	 used in the mem insn since this will become the new index
+ 	 register.  */
+-      if (count_occurrences (PATTERN (mem_insn.insn), inc_insn.reg_res, 1) != 0)
++      if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn)))
+ 	{
+ 	  if (dump_file)
+ 	    fprintf (dump_file, "base reg replacement failure.\n");
+
+=== added file 'gcc/testsuite/gcc.dg/pr44404.c'
+--- old/gcc/testsuite/gcc.dg/pr44404.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr44404.c	2010-08-05 11:30:21 +0000
+@@ -0,0 +1,35 @@
++/* PR rtl-optimization/44404
++   foo() used to be miscompiled on ARM due to a bug in auto-inc-dec.c,
++   which resulted in "strb r1, [r1], #-36".  */
++
++/* { dg-do run } */
++/* { dg-options "-O2 -fno-unroll-loops" } */
++
++extern char *strcpy (char *, const char *);
++extern int strcmp (const char*, const char*);
++extern void abort (void);
++
++char buf[128];
++
++void __attribute__((noinline))
++bar (int a, const char *p)
++{
++  if (strcmp (p, "0123456789abcdefghijklmnopqrstuvwxyz") != 0)
++    abort ();
++}
++
++void __attribute__((noinline))
++foo (int a)
++{
++  if (a)
++    bar (0, buf);
++  strcpy (buf, "0123456789abcdefghijklmnopqrstuvwxyz");
++  bar (0, buf);
++}
++
++int
++main (void)
++{
++  foo (0);
++  return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch
new file mode 100644
index 0000000000..ad4943a0a9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch
@@ -0,0 +1,118 @@
+2010-07-24  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #9079
+
+	Backport from mainline:
+
+	gcc/
+	2010-07-23  Jie Zhang  <jie@codesourcery.com>
+	PR target/44290
+	* attribs.c (decl_attributes): Insert "noinline" and "noclone"
+	if "naked".
+	* tree-sra.c (ipa_sra_preliminary_function_checks): Return
+	false if ! tree_versionable_function_p.
+
+	gcc/testsuite/
+	2010-07-23  Jie Zhang  <jie@codesourcery.com>
+	PR target/44290
+	* gcc.dg/pr44290-1.c: New test.
+	* gcc.dg/pr44290-2.c: New test.
+
+ 2010-07-22  Maxim Kuvyrkov  <maxim@codesourcery.com>
+ 
+ 	Backport from FSF GCC 4.5 branch to fix PR45015:
+
+=== modified file 'gcc/attribs.c'
+--- old/gcc/attribs.c	2010-04-02 18:54:46 +0000
++++ new/gcc/attribs.c	2010-08-05 11:39:36 +0000
+@@ -278,6 +278,19 @@
+ 	TREE_VALUE (cur_attr) = chainon (opts, TREE_VALUE (cur_attr));
+     }
+ 
++  /* A "naked" function attribute implies "noinline" and "noclone" for
++     those targets that support it.  */
++  if (TREE_CODE (*node) == FUNCTION_DECL
++      && lookup_attribute_spec (get_identifier ("naked"))
++      && lookup_attribute ("naked", attributes) != NULL)
++    {
++      if (lookup_attribute ("noinline", attributes) == NULL)
++	attributes = tree_cons (get_identifier ("noinline"), NULL, attributes);
++
++      if (lookup_attribute ("noclone", attributes) == NULL)
++	attributes = tree_cons (get_identifier ("noclone"),  NULL, attributes);
++    }
++
+   targetm.insert_attributes (*node, &attributes);
+ 
+   for (a = attributes; a; a = TREE_CHAIN (a))
+
+=== added file 'gcc/testsuite/gcc.dg/pr44290-1.c'
+--- old/gcc/testsuite/gcc.dg/pr44290-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr44290-1.c	2010-08-05 11:39:36 +0000
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */
++/* { dg-options "-O2 -fdump-tree-optimized" } */
++
++static void __attribute__((naked))
++foo(void *from, void *to)
++{
++  asm volatile("dummy"::"r"(from), "r"(to));
++}
++
++unsigned int fie[2];
++
++void fum(void *to)
++{
++  foo(fie, to);
++}
++
++/* { dg-final { scan-tree-dump "foo \\\(void \\\* from, void \\\* to\\\)" "optimized" } } */
++/* { dg-final { cleanup-tree-dump "optimized" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/pr44290-2.c'
+--- old/gcc/testsuite/gcc.dg/pr44290-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr44290-2.c	2010-08-05 11:39:36 +0000
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */
++/* { dg-options "-O2 -fdump-tree-optimized" } */
++
++static unsigned long __attribute__((naked))
++foo (unsigned long base)
++{
++  asm volatile ("dummy");
++}
++unsigned long
++bar (void)
++{
++  static int start, set;
++
++  if (!set)
++    {
++      set = 1;
++      start = foo (0);
++    }
++
++  return foo (start);
++}
++
++/* { dg-final { scan-tree-dump "foo \\\(long unsigned int base\\\)" "optimized" } } */
++/* { dg-final { cleanup-tree-dump "optimized" } } */
+
+=== modified file 'gcc/tree-sra.c'
+--- old/gcc/tree-sra.c	2010-03-17 12:02:35 +0000
++++ new/gcc/tree-sra.c	2010-08-05 11:39:36 +0000
+@@ -4096,6 +4096,13 @@
+ static bool
+ ipa_sra_preliminary_function_checks (struct cgraph_node *node)
+ {
++  if (!tree_versionable_function_p (current_function_decl))
++    {
++      if (dump_file)
++	fprintf (dump_file, "Function isn't allowed to be versioned.\n");
++      return false;
++    }
++
+   if (!cgraph_node_can_be_local_p (node))
+     {
+       if (dump_file)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch
new file mode 100644
index 0000000000..a649c9542a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch
@@ -0,0 +1,197 @@
+2010-07-24  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-04-10  Wei Guozhi  <carrot@google.com>
+
+	PR target/42601
+	gcc/
+	* config/arm/arm.c (arm_pic_static_addr): New function.
+	(legitimize_pic_address): Call arm_pic_static_addr when it detects
+	a static symbol.
+	(arm_output_addr_const_extra): Output expression for new pattern.
+	* config/arm/arm.md (UNSPEC_SYMBOL_OFFSET): New unspec symbol.
+
+	2010-07-22  Sandra Loosemore  <sandra@codesourcery.com>
+
+	PR tree-optimization/39839
+	gcc/testsuite/
+	* gcc.target/arm/pr39839.c: New test case.
+
+ 2010-07-24  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Issue #9079
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-03 13:55:46 +0000
++++ new/gcc/config/arm/arm.c	2010-08-05 12:06:40 +0000
+@@ -225,6 +225,7 @@
+ static void arm_asm_trampoline_template (FILE *);
+ static void arm_trampoline_init (rtx, tree, rtx);
+ static rtx arm_trampoline_adjust_address (rtx);
++static rtx arm_pic_static_addr (rtx orig, rtx reg);
+ 
+ 
+ /* Table of machine attributes.  */
+@@ -4986,29 +4987,16 @@
+     {
+       rtx pic_ref, address;
+       rtx insn;
+-      int subregs = 0;
+-
+-      /* If this function doesn't have a pic register, create one now.  */
+-      require_pic_register ();
+ 
+       if (reg == 0)
+ 	{
+ 	  gcc_assert (can_create_pseudo_p ());
+ 	  reg = gen_reg_rtx (Pmode);
+-
+-	  subregs = 1;
++	  address = gen_reg_rtx (Pmode);
+ 	}
+-
+-      if (subregs)
+-	address = gen_reg_rtx (Pmode);
+       else
+ 	address = reg;
+ 
+-      if (TARGET_32BIT)
+-	emit_insn (gen_pic_load_addr_32bit (address, orig));
+-      else /* TARGET_THUMB1 */
+-	emit_insn (gen_pic_load_addr_thumb1 (address, orig));
+-
+       /* VxWorks does not impose a fixed gap between segments; the run-time
+ 	 gap can be different from the object-file gap.  We therefore can't
+ 	 use GOTOFF unless we are absolutely sure that the symbol is in the
+@@ -5020,16 +5008,23 @@
+ 	       SYMBOL_REF_LOCAL_P (orig)))
+ 	  && NEED_GOT_RELOC
+ 	  && !TARGET_VXWORKS_RTP)
+-	pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
++	insn = arm_pic_static_addr (orig, reg);
+       else
+ 	{
++	  /* If this function doesn't have a pic register, create one now.  */
++	  require_pic_register ();
++
++	  if (TARGET_32BIT)
++	    emit_insn (gen_pic_load_addr_32bit (address, orig));
++	  else /* TARGET_THUMB1 */
++	    emit_insn (gen_pic_load_addr_thumb1 (address, orig));
++
+ 	  pic_ref = gen_const_mem (Pmode,
+ 				   gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
+ 					         address));
++	  insn = emit_move_insn (reg, pic_ref);
+ 	}
+ 
+-      insn = emit_move_insn (reg, pic_ref);
+-
+       /* Put a REG_EQUAL note on this insn, so that it can be optimized
+ 	 by loop.  */
+       set_unique_reg_note (insn, REG_EQUAL, orig);
+@@ -5236,6 +5231,43 @@
+   emit_use (pic_reg);
+ }
+ 
++/* Generate code to load the address of a static var when flag_pic is set.  */
++static rtx
++arm_pic_static_addr (rtx orig, rtx reg)
++{
++  rtx l1, labelno, offset_rtx, insn;
++
++  gcc_assert (flag_pic);
++
++  /* We use an UNSPEC rather than a LABEL_REF because this label
++     never appears in the code stream.  */
++  labelno = GEN_INT (pic_labelno++);
++  l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
++  l1 = gen_rtx_CONST (VOIDmode, l1);
++
++  /* On the ARM the PC register contains 'dot + 8' at the time of the
++     addition, on the Thumb it is 'dot + 4'.  */
++  offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4);
++  offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx),
++                               UNSPEC_SYMBOL_OFFSET);
++  offset_rtx = gen_rtx_CONST (Pmode, offset_rtx);
++
++  if (TARGET_32BIT)
++    {
++      emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx));
++      if (TARGET_ARM)
++        insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
++      else
++        insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
++    }
++  else /* TARGET_THUMB1 */
++    {
++      emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx));
++      insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
++    }
++
++  return insn;
++}
+ 
+ /* Return nonzero if X is valid as an ARM state addressing register.  */
+ static int
+@@ -21461,6 +21493,16 @@
+       fputc (')', fp);
+       return TRUE;
+     }
++  else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET)
++    {
++      output_addr_const (fp, XVECEXP (x, 0, 0));
++      if (GOT_PCREL)
++        fputs ("+.", fp);
++      fputs ("-(", fp);
++      output_addr_const (fp, XVECEXP (x, 0, 1));
++      fputc (')', fp);
++      return TRUE;
++    }
+   else if (GET_CODE (x) == CONST_VECTOR)
+     return arm_emit_vector_const (fp, x);
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-07-30 14:17:05 +0000
++++ new/gcc/config/arm/arm.md	2010-08-05 12:06:40 +0000
+@@ -101,6 +101,8 @@
+ 			  ; a given symbolic address.
+    (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call.
+    (UNSPEC_RBIT 26)       ; rbit operation.
++   (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
++                             ; another symbolic address.
+   ]
+ )
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr39839.c'
+--- old/gcc/testsuite/gcc.target/arm/pr39839.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr39839.c	2010-08-05 12:06:40 +0000
+@@ -0,0 +1,24 @@
++/* { dg-options "-mthumb -Os -march=armv5te -mthumb-interwork -fpic" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */
++
++struct S
++{
++  int count;
++  char *addr;
++};
++
++void func(const char*, const char*, int, const char*);
++
++/* This function should not need to spill to the stack. */
++void test(struct S *p)
++{
++  int off = p->count;
++  while (p->count >= 0)
++    {
++      const char *s = "xyz";
++      if (*p->addr) s = "pqr";
++      func("abcde", p->addr + off, off, s);
++      p->count--;
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch
new file mode 100644
index 0000000000..669523218c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch
@@ -0,0 +1,138 @@
+2010-08-05  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-shift-2.c: Revert all previous changes.
+	* gcc.dg/vect/vect-shift-4.c: New file.
+
+	2010-07-20  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:	
+	2009-06-16  Daniel Jacobowitz  <dan@codesourcery.com>
+	
+	Merge from Sourcery G++ 4.3:
+	2008-12-03  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-shift-2.c, gcc.dg/vect/vect-shift-3.c: New.
+	* lib/target-supports.exp (check_effective_target_vect_shift_char): New
+	function.
+
+ 2010-07-24  Sandra Loosemore  <sandra@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c	2010-08-05 14:13:43 +0000
+@@ -0,0 +1,37 @@
++/* { dg-require-effective-target vect_shift } */
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++
++#define N 32
++
++unsigned short dst[N] __attribute__((aligned(N)));
++unsigned short src[N] __attribute__((aligned(N)));
++
++__attribute__ ((noinline))
++void array_shift(void)
++{
++  int i;
++  for (i = 0; i < N; i++)
++    dst[i] = src[i] >> 3;
++}
++
++int main()
++{
++  volatile int i;
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    src[i] = i << 3;
++
++  array_shift ();
++
++  for (i = 0; i < N; i++)
++    if (dst[i] != i)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c	2010-08-05 14:13:43 +0000
+@@ -0,0 +1,37 @@
++/* { dg-require-effective-target vect_shift_char } */
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++
++#define N 32
++
++unsigned char dst[N] __attribute__((aligned(N)));
++unsigned char src[N] __attribute__((aligned(N)));
++
++__attribute__ ((noinline))
++void array_shift(void)
++{
++  int i;
++  for (i = 0; i < N; i++)
++    dst[i] = src[i] >> 3;
++}
++
++int main()
++{
++  volatile int i;
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    src[i] = i << 3;
++
++  array_shift ();
++
++  for (i = 0; i < N; i++)
++    if (dst[i] != i)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2010-08-05 14:13:43 +0000
+@@ -2001,6 +2001,26 @@
+     return $et_vect_shift_saved
+ }
+ 
++# Return 1 if the target supports hardware vector shift operation for char.
++
++proc check_effective_target_vect_shift_char { } {
++    global et_vect_shift_char_saved
++
++    if [info exists et_vect_shift_char_saved] {
++	verbose "check_effective_target_vect_shift_char: using cached result" 2
++    } else {
++	set et_vect_shift_char_saved 0
++	if { ([istarget powerpc*-*-*]
++             && ![istarget powerpc-*-linux*paired*])
++	     || [check_effective_target_arm32] } {
++	   set et_vect_shift_char_saved 1
++	}
++    }
++
++    verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2
++    return $et_vect_shift_char_saved
++}
++
+ # Return 1 if the target supports hardware vectors of long, 0 otherwise.
+ #
+ # This can change for different subtargets so do not cache the result.
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch
new file mode 100644
index 0000000000..b122ab10f8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch
@@ -0,0 +1,28 @@
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	2007-07-05  Mark Shinwell  <shinwell@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.h (BRANCH_COST): Set to 1 when optimizing for size
+	on Thumb-2.
+
+ 2010-08-05  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	gcc/testsuite/
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-03 10:40:56 +0000
++++ new/gcc/config/arm/arm.h	2010-08-05 14:29:52 +0000
+@@ -2210,7 +2210,8 @@
+ /* Try to generate sequences that don't involve branches, we can then use
+    conditional instructions */
+ #define BRANCH_COST(speed_p, predictable_p) \
+-  (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
++  (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \
++		: (optimize > 0 ? 2 : 0))
+ 
+ /* Position Independent Code.  */
+ /* We decide which register to use based on the compilation options and
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch
new file mode 100644
index 0000000000..6962c1cecf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch
@@ -0,0 +1,53 @@
+	2007-06-06  Joseph Myers  <joseph@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.h (VALID_IWMMXT_REG_MODE): Allow SImode.
+	(ARM_LEGITIMIZE_RELOAD_ADDRESS): Reduce range allowed for SImode
+	offsets with iWMMXt.
+	* config/arm/arm.c (arm_hard_regno_mode_ok): Update for change to
+	VALID_IWMMXT_REG_MODE.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2007-07-05  Mark Shinwell  <shinwell@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-05 12:06:40 +0000
++++ new/gcc/config/arm/arm.c	2010-08-05 14:33:31 +0000
+@@ -16538,7 +16538,7 @@
+ 	return mode == SImode;
+ 
+       if (IS_IWMMXT_REGNUM (regno))
+-	return VALID_IWMMXT_REG_MODE (mode);
++	return VALID_IWMMXT_REG_MODE (mode) && mode != SImode;
+     }
+   
+   /* We allow almost any value to be stored in the general registers.
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-05 14:29:52 +0000
++++ new/gcc/config/arm/arm.h	2010-08-05 14:33:31 +0000
+@@ -1077,7 +1077,7 @@
+   (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
+ 
+ #define VALID_IWMMXT_REG_MODE(MODE) \
+- (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
++ (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode)
+ 
+ /* Modes valid for Neon D registers.  */
+ #define VALID_NEON_DREG_MODE(MODE) \
+@@ -1364,6 +1364,9 @@
+ 	  else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)		   \
+ 	    /* Need to be careful, -256 is not a valid offset.  */	   \
+ 	    low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);		   \
++	  else if (TARGET_REALLY_IWMMXT && MODE == SImode)		   \
++	    /* Need to be careful, -1024 is not a valid offset.  */	   \
++	    low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);		   \
+ 	  else if (MODE == SImode					   \
+ 		   || (MODE == SFmode && TARGET_SOFT_FLOAT)		   \
+ 		   || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch
new file mode 100644
index 0000000000..38b6fa3f0e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch
@@ -0,0 +1,688 @@
+	Vladimir Prus  <vladimir@codesourcery.com>
+	Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_override_options): Warn if mlow-irq-latency is
+	specified in Thumb mode.
+	(load_multiple_sequence): Return 0 if low irq latency is requested.
+	(store_multiple_sequence): Likewise.
+	(arm_gen_load_multiple): Load registers one-by-one if low irq latency
+	is requested.
+	(arm_gen_store_multiple): Likewise.
+	(vfp_output_fldmd): When low_irq_latency is non zero, pop each
+	register separately.
+	(vfp_emit_fstmd): When low_irq_latency is non zero, save each register
+	separately.
+	(arm_get_vfp_saved_size): Adjust saved register size calculation for
+	the above changes.
+	(print_pop_reg_by_ldr): New.
+	(arm_output_epilogue): Use print_pop_reg_by_ldr when low irq latency
+	is requested.
+	(emit_multi_reg_push): Push registers separately if low irq latency
+	is requested.
+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set __low_irq_latency__.
+	(low_irq_latency): Define.
+	(USE_RETURN_INSN): Don't use return insn when low irq latency is
+	requested.
+	* config/arm/lib1funcs.asm (do_pop, do_push): Define as variadic
+	macros. When __low_irq_latency__ is defined, push and pop registers
+	individually.
+	(div0): Use correct punctuation.
+	* config/arm/ieee754-df.S: Adjust syntax of using do_push.
+	* config/arm/ieee754-sf.S: Likewise.
+	* config/arm/bpabi.S: Likewise.
+	* config/arm/arm.opt (mlow-irq-latency): New option.
+	* config/arm/predicates.md (load_multiple_operation): Return false is
+	low irq latency is requested.
+	(store_multiple_operation): Likewise.
+	* config/arm/arm.md (movmemqi): Don't use it if low irq latency is
+	requested.
+	* doc/invoke.texi (-mlow-irq-latency): Add documentation.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2007-06-06  Joseph Myers  <joseph@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-05 14:33:31 +0000
++++ new/gcc/config/arm/arm.c	2010-08-05 15:20:54 +0000
+@@ -1884,6 +1884,13 @@
+ 
+   /* Register global variables with the garbage collector.  */
+   arm_add_gc_roots ();
++
++  if (low_irq_latency && TARGET_THUMB)
++    {
++      warning (0, 
++	       "-mlow-irq-latency has no effect when compiling for Thumb");
++      low_irq_latency = 0;
++    }
+ }
+ 
+ static void
+@@ -9053,6 +9060,9 @@
+   int base_reg = -1;
+   int i;
+ 
++  if (low_irq_latency)
++    return 0;
++
+   /* Can only handle 2, 3, or 4 insns at present,
+      though could be easily extended if required.  */
+   gcc_assert (nops >= 2 && nops <= 4);
+@@ -9282,6 +9292,9 @@
+   int base_reg = -1;
+   int i;
+ 
++  if (low_irq_latency)
++    return 0;
++
+   /* Can only handle 2, 3, or 4 insns at present, though could be easily
+      extended if required.  */
+   gcc_assert (nops >= 2 && nops <= 4);
+@@ -9489,7 +9502,7 @@
+ 
+      As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
+      for counts of 3 or 4 regs.  */
+-  if (arm_tune_xscale && count <= 2 && ! optimize_size)
++  if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
+     {
+       rtx seq;
+ 
+@@ -9552,7 +9565,7 @@
+ 
+   /* See arm_gen_load_multiple for discussion of
+      the pros/cons of ldm/stm usage for XScale.  */
+-  if (arm_tune_xscale && count <= 2 && ! optimize_size)
++  if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
+     {
+       rtx seq;
+ 
+@@ -11795,6 +11808,21 @@
+ vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
+ {
+   int i;
++  int offset;
++
++  if (low_irq_latency)
++    {
++      /* Output a sequence of FLDD instructions.  */
++      offset = 0;
++      for (i = reg; i < reg + count; ++i, offset += 8)
++	{
++	  fputc ('\t', stream);
++	  asm_fprintf (stream, "fldd\td%d, [%r,#%d]\n", i, base, offset);
++	}
++      asm_fprintf (stream, "\tadd\tsp, sp, #%d\n", count * 8);
++      return;
++    }
++
+ 
+   /* Workaround ARM10 VFPr1 bug.  */
+   if (count == 2 && !arm_arch6)
+@@ -11865,6 +11893,56 @@
+   rtx tmp, reg;
+   int i;
+ 
++  if (low_irq_latency)
++    {
++      int saved_size;
++      rtx sp_insn;
++
++      if (!count)
++	return 0;
++
++      saved_size = count * GET_MODE_SIZE (DFmode);
++
++      /* Since fstd does not have postdecrement addressing mode,
++	 we first decrement stack pointer and then use base+offset
++	 stores for VFP registers. The ARM EABI unwind information 
++	 can't easily describe base+offset loads, so we attach
++	 a note for the effects of the whole block in the first insn, 
++	 and  avoid marking the subsequent instructions 
++	 with RTX_FRAME_RELATED_P.  */
++      sp_insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
++			    GEN_INT (-saved_size));
++      sp_insn = emit_insn (sp_insn);
++      RTX_FRAME_RELATED_P (sp_insn) = 1;
++
++      dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
++      XVECEXP (dwarf, 0, 0) = 
++	gen_rtx_SET (VOIDmode, stack_pointer_rtx,
++		     plus_constant (stack_pointer_rtx, -saved_size));
++      
++      /* push double VFP registers to stack */
++      for (i = 0; i < count; ++i )
++	{
++	  rtx reg;
++	  rtx mem;
++	  rtx addr;
++	  rtx insn;
++	  reg = gen_rtx_REG (DFmode, base_reg + 2*i);
++	  addr = (i == 0) ? stack_pointer_rtx
++	    : gen_rtx_PLUS (SImode, stack_pointer_rtx,
++			    GEN_INT (i * GET_MODE_SIZE (DFmode)));
++	  mem = gen_frame_mem (DFmode, addr);
++	  insn = emit_move_insn (mem, reg);
++	  XVECEXP (dwarf, 0, i+1) = 
++	    gen_rtx_SET (VOIDmode, mem, reg);
++	}
++
++      REG_NOTES (sp_insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
++					       REG_NOTES (sp_insn));
++      
++      return saved_size;
++    }
++
+   /* Workaround ARM10 VFPr1 bug.  Data corruption can occur when exactly two
+      register pairs are stored by a store multiple insn.  We avoid this
+      by pushing an extra pair.  */
+@@ -13307,7 +13385,7 @@
+ 	      if (count > 0)
+ 		{
+ 		  /* Workaround ARM10 VFPr1 bug.  */
+-		  if (count == 2 && !arm_arch6)
++		  if (count == 2 && !arm_arch6 && !low_irq_latency)
+ 		    count++;
+ 		  saved += count * 8;
+ 		}
+@@ -13645,6 +13723,41 @@
+ 
+ }
+ 
++/* Generate to STREAM a code sequence that pops registers identified 
++   in REGS_MASK from SP. SP is incremented as the result.
++*/
++static void
++print_pop_reg_by_ldr (FILE *stream, int regs_mask, int rfe)
++{
++  int reg;
++
++  gcc_assert (! (regs_mask & (1 << SP_REGNUM)));
++  
++  for (reg = 0; reg < PC_REGNUM; ++reg)
++    if (regs_mask & (1 << reg))
++      asm_fprintf (stream, "\tldr\t%r, [%r], #4\n",
++		   reg, SP_REGNUM); 
++
++  if (regs_mask & (1 << PC_REGNUM))
++    {
++      if (rfe)
++	/* When returning from exception, we need to
++	   copy SPSR to CPSR.  There are two ways to do
++	   that: the ldm instruction with "^" suffix,
++	   and movs instruction.  The latter would
++	   require that we load from stack to some
++	   scratch register, and then move to PC.
++	   Therefore, we'd need extra instruction and
++	   have to make sure we actually have a spare
++	   register.  Using ldm with a single register
++	   is simler.  */
++	asm_fprintf (stream, "\tldm\tsp!, {pc}^\n");
++      else
++	asm_fprintf (stream, "\tldr\t%r, [%r], #4\n",
++		     PC_REGNUM, SP_REGNUM); 
++    }
++}
++
+ const char *
+ arm_output_epilogue (rtx sibling)
+ {
+@@ -14018,22 +14131,19 @@
+ 	 to load use the LDR instruction - it is faster.  For Thumb-2
+ 	 always use pop and the assembler will pick the best instruction.*/
+       if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
+-	  && !IS_INTERRUPT(func_type))
++	  && !IS_INTERRUPT (func_type))
+ 	{
+ 	  asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
+ 	}
+       else if (saved_regs_mask)
+ 	{
+-	  if (saved_regs_mask & (1 << SP_REGNUM))
+-	    /* Note - write back to the stack register is not enabled
+-	       (i.e. "ldmfd sp!...").  We know that the stack pointer is
+-	       in the list of registers and if we add writeback the
+-	       instruction becomes UNPREDICTABLE.  */
+-	    print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
+-			     rfe);
+-	  else if (TARGET_ARM)
+-	    print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
+-			     rfe);
++	  gcc_assert ( ! (saved_regs_mask & (1 << SP_REGNUM)));
++	  if (TARGET_ARM)
++	    if (low_irq_latency)
++	      print_pop_reg_by_ldr (f, saved_regs_mask, rfe);
++	    else
++	      print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
++			       rfe);
+ 	  else
+ 	    print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
+ 	}
+@@ -14154,6 +14264,32 @@
+ 
+   gcc_assert (num_regs && num_regs <= 16);
+ 
++  if (low_irq_latency)
++    {
++      rtx insn = 0;
++
++      /* Emit a series of ldr instructions rather rather than a single ldm.  */
++      /* TODO: Use ldrd where possible.  */
++      gcc_assert (! (mask & (1 << SP_REGNUM)));
++
++      for (i = LAST_ARM_REGNUM; i >= 0; --i)
++        {
++          if (mask & (1 << i))
++
++            {
++              rtx reg, where, mem;
++
++	      reg = gen_rtx_REG (SImode, i);
++	      where = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
++	      mem = gen_rtx_MEM (SImode, where);
++	      insn = emit_move_insn (mem, reg);
++	      RTX_FRAME_RELATED_P (insn) = 1;
++            }
++        }
++
++      return insn;
++    }
++
+   /* We don't record the PC in the dwarf frame information.  */
+   num_dwarf_regs = num_regs;
+   if (mask & (1 << PC_REGNUM))
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-05 14:33:31 +0000
++++ new/gcc/config/arm/arm.h	2010-08-05 15:20:54 +0000
+@@ -101,6 +101,8 @@
+ 	      builtin_define ("__ARM_PCS");		\
+ 	    builtin_define ("__ARM_EABI__");		\
+ 	  }						\
++	if (low_irq_latency)				\
++	  builtin_define ("__low_irq_latency__");	\
+     } while (0)
+ 
+ /* The various ARM cores.  */
+@@ -449,6 +451,10 @@
+ /* Nonzero if chip supports integer division instruction.  */
+ extern int arm_arch_hwdiv;
+ 
++/* Nonzero if we should minimize interrupt latency of the
++   generated code.  */
++extern int low_irq_latency;
++
+ #ifndef TARGET_DEFAULT
+ #define TARGET_DEFAULT  (MASK_APCS_FRAME)
+ #endif
+@@ -1823,9 +1829,10 @@
+ /* Determine if the epilogue should be output as RTL.
+    You should override this if you define FUNCTION_EXTRA_EPILOGUE.  */
+ /* This is disabled for Thumb-2 because it will confuse the
+-   conditional insn counter.  */
++   conditional insn counter.
++   Do not use a return insn if we're avoiding ldm/stm instructions.  */
+ #define USE_RETURN_INSN(ISCOND)				\
+-  (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
++  ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
+ 
+ /* Definitions for register eliminations.
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-05 12:06:40 +0000
++++ new/gcc/config/arm/arm.md	2010-08-05 15:20:54 +0000
+@@ -6587,7 +6587,7 @@
+    (match_operand:BLK 1 "general_operand" "")
+    (match_operand:SI 2 "const_int_operand" "")
+    (match_operand:SI 3 "const_int_operand" "")]
+-  "TARGET_EITHER"
++  "TARGET_EITHER && !low_irq_latency"
+   "
+   if (TARGET_32BIT)
+     {
+
+=== modified file 'gcc/config/arm/arm.opt'
+--- old/gcc/config/arm/arm.opt	2009-06-18 11:24:10 +0000
++++ new/gcc/config/arm/arm.opt	2010-08-05 15:20:54 +0000
+@@ -161,6 +161,10 @@
+ Target Report Mask(NEON_VECTORIZE_QUAD)
+ Use Neon quad-word (rather than double-word) registers for vectorization
+ 
++mlow-irq-latency
++Target Report Var(low_irq_latency)
++Try to reduce interrupt latency of the generated code
++
+ mword-relocations
+ Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
+ Only generate absolute relocations on word sized values.
+
+=== modified file 'gcc/config/arm/bpabi.S'
+--- old/gcc/config/arm/bpabi.S	2009-12-17 15:37:23 +0000
++++ new/gcc/config/arm/bpabi.S	2010-08-05 15:20:54 +0000
+@@ -116,16 +116,17 @@
+ 	test_div_by_zero signed
+ 
+ 	sub sp, sp, #8
+-#if defined(__thumb2__)
++/* Low latency and Thumb-2 do_push implementations can't push sp directly.  */
++#if defined(__thumb2__) || defined(__irq_low_latency__)
+ 	mov ip, sp
+-	push {ip, lr}
++	do_push (ip, lr)
+ #else
+-	do_push {sp, lr}
++	stmfd sp!, {sp, lr}
+ #endif
+ 	bl SYM(__gnu_ldivmod_helper) __PLT__
+ 	ldr lr, [sp, #4]
+ 	add sp, sp, #8
+-	do_pop {r2, r3}
++	do_pop (r2, r3)
+ 	RET
+ 	
+ #endif /* L_aeabi_ldivmod */
+@@ -136,16 +137,17 @@
+ 	test_div_by_zero unsigned
+ 
+ 	sub sp, sp, #8
+-#if defined(__thumb2__)
++/* Low latency and Thumb-2 do_push implementations can't push sp directly.  */
++#if defined(__thumb2__) || defined(__irq_low_latency__)
+ 	mov ip, sp
+-	push {ip, lr}
++	do_push (ip, lr)
+ #else
+-	do_push {sp, lr}
++	stmfd sp!, {sp, lr}
+ #endif
+ 	bl SYM(__gnu_uldivmod_helper) __PLT__
+ 	ldr lr, [sp, #4]
+ 	add sp, sp, #8
+-	do_pop {r2, r3}
++	do_pop (r2, r3)
+ 	RET
+ 	
+ #endif /* L_aeabi_divmod */
+
+=== modified file 'gcc/config/arm/ieee754-df.S'
+--- old/gcc/config/arm/ieee754-df.S	2009-06-05 12:52:36 +0000
++++ new/gcc/config/arm/ieee754-df.S	2010-08-05 15:20:54 +0000
+@@ -83,7 +83,7 @@
+ ARM_FUNC_START adddf3
+ ARM_FUNC_ALIAS aeabi_dadd adddf3
+ 
+-1:	do_push	{r4, r5, lr}
++1:	do_push	(r4, r5, lr)
+ 
+ 	@ Look for zeroes, equal values, INF, or NAN.
+ 	shift1	lsl, r4, xh, #1
+@@ -427,7 +427,7 @@
+ 	do_it	eq, t
+ 	moveq	r1, #0
+ 	RETc(eq)
+-	do_push	{r4, r5, lr}
++	do_push	(r4, r5, lr)
+ 	mov	r4, #0x400		@ initial exponent
+ 	add	r4, r4, #(52-1 - 1)
+ 	mov	r5, #0			@ sign bit is 0
+@@ -447,7 +447,7 @@
+ 	do_it	eq, t
+ 	moveq	r1, #0
+ 	RETc(eq)
+-	do_push	{r4, r5, lr}
++	do_push	(r4, r5, lr)
+ 	mov	r4, #0x400		@ initial exponent
+ 	add	r4, r4, #(52-1 - 1)
+ 	ands	r5, r0, #0x80000000	@ sign bit in r5
+@@ -481,7 +481,7 @@
+ 	RETc(eq)			@ we are done already.
+ 
+ 	@ value was denormalized.  We can normalize it now.
+-	do_push	{r4, r5, lr}
++	do_push	(r4, r5, lr)
+ 	mov	r4, #0x380		@ setup corresponding exponent
+ 	and	r5, xh, #0x80000000	@ move sign bit in r5
+ 	bic	xh, xh, #0x80000000
+@@ -508,9 +508,9 @@
+ 	@ compatibility.
+ 	adr	ip, LSYM(f0_ret)
+ 	@ Push pc as well so that RETLDM works correctly.
+-	do_push	{r4, r5, ip, lr, pc}
++	do_push	(r4, r5, ip, lr, pc)
+ #else
+-	do_push	{r4, r5, lr}
++	do_push	(r4, r5, lr)
+ #endif
+ 
+ 	mov	r5, #0
+@@ -534,9 +534,9 @@
+ 	@ compatibility.
+ 	adr	ip, LSYM(f0_ret)
+ 	@ Push pc as well so that RETLDM works correctly.
+-	do_push	{r4, r5, ip, lr, pc}
++	do_push	(r4, r5, ip, lr, pc)
+ #else
+-	do_push	{r4, r5, lr}
++	do_push	(r4, r5, lr)
+ #endif
+ 
+ 	ands	r5, ah, #0x80000000	@ sign bit in r5
+@@ -585,7 +585,7 @@
+ 	@ Legacy code expects the result to be returned in f0.  Copy it
+ 	@ there as well.
+ LSYM(f0_ret):
+-	do_push	{r0, r1}
++	do_push	(r0, r1)
+ 	ldfd	f0, [sp], #8
+ 	RETLDM
+ 
+@@ -602,7 +602,7 @@
+ 
+ ARM_FUNC_START muldf3
+ ARM_FUNC_ALIAS aeabi_dmul muldf3
+-	do_push	{r4, r5, r6, lr}
++	do_push	(r4, r5, r6, lr)
+ 
+ 	@ Mask out exponents, trap any zero/denormal/INF/NAN.
+ 	mov	ip, #0xff
+@@ -910,7 +910,7 @@
+ ARM_FUNC_START divdf3
+ ARM_FUNC_ALIAS aeabi_ddiv divdf3
+ 	
+-	do_push	{r4, r5, r6, lr}
++	do_push	(r4, r5, r6, lr)
+ 
+ 	@ Mask out exponents, trap any zero/denormal/INF/NAN.
+ 	mov	ip, #0xff
+@@ -1195,7 +1195,7 @@
+ 
+ 	@ The status-returning routines are required to preserve all
+ 	@ registers except ip, lr, and cpsr.
+-6:	do_push	{r0, lr}
++6:	do_push	(r0, lr)
+ 	ARM_CALL cmpdf2
+ 	@ Set the Z flag correctly, and the C flag unconditionally.
+ 	cmp	r0, #0
+
+=== modified file 'gcc/config/arm/ieee754-sf.S'
+--- old/gcc/config/arm/ieee754-sf.S	2009-06-05 12:52:36 +0000
++++ new/gcc/config/arm/ieee754-sf.S	2010-08-05 15:20:54 +0000
+@@ -481,7 +481,7 @@
+ 	and	r3, ip, #0x80000000
+ 
+ 	@ Well, no way to make it shorter without the umull instruction.
+-	do_push	{r3, r4, r5}
++	do_push	(r3, r4, r5)
+ 	mov	r4, r0, lsr #16
+ 	mov	r5, r1, lsr #16
+ 	bic	r0, r0, r4, lsl #16
+@@ -492,7 +492,7 @@
+ 	mla	r0, r4, r1, r0
+ 	adds	r3, r3, r0, lsl #16
+ 	adc	r1, ip, r0, lsr #16
+-	do_pop	{r0, r4, r5}
++	do_pop	(r0, r4, r5)
+ 
+ #else
+ 
+@@ -882,7 +882,7 @@
+ 
+ 	@ The status-returning routines are required to preserve all
+ 	@ registers except ip, lr, and cpsr.
+-6:	do_push	{r0, r1, r2, r3, lr}
++6:	do_push	(r0, r1, r2, r3, lr)
+ 	ARM_CALL cmpsf2
+ 	@ Set the Z flag correctly, and the C flag unconditionally.
+ 	cmp	r0, #0
+
+=== modified file 'gcc/config/arm/lib1funcs.asm'
+--- old/gcc/config/arm/lib1funcs.asm	2010-04-02 18:54:46 +0000
++++ new/gcc/config/arm/lib1funcs.asm	2010-08-05 15:20:54 +0000
+@@ -254,8 +254,8 @@
+ .macro shift1 op, arg0, arg1, arg2
+ 	\op	\arg0, \arg1, \arg2
+ .endm
+-#define do_push	push
+-#define do_pop	pop
++#define do_push(...)	push {__VA_ARGS__}
++#define do_pop(...)	pop {__VA_ARGS__}
+ #define COND(op1, op2, cond) op1 ## op2 ## cond
+ /* Perform an arithmetic operation with a variable shift operand.  This
+    requires two instructions and a scratch register on Thumb-2.  */
+@@ -269,8 +269,42 @@
+ .macro shift1 op, arg0, arg1, arg2
+ 	mov	\arg0, \arg1, \op \arg2
+ .endm
+-#define do_push	stmfd sp!,
+-#define do_pop	ldmfd sp!,
++#if defined(__low_irq_latency__)        
++#define do_push(...) \
++  _buildN1(do_push, _buildC1(__VA_ARGS__))( __VA_ARGS__)
++#define _buildN1(BASE, X)	_buildN2(BASE, X)
++#define _buildN2(BASE, X)	BASE##X
++#define _buildC1(...)		_buildC2(__VA_ARGS__,9,8,7,6,5,4,3,2,1)
++#define _buildC2(a1,a2,a3,a4,a5,a6,a7,a8,a9,c,...) c
++        
++#define do_push1(r1) str r1, [sp, #-4]!
++#define do_push2(r1, r2) str r2, [sp, #-4]! ; str r1, [sp, #-4]!
++#define do_push3(r1, r2, r3) str r3, [sp, #-4]! ; str r2, [sp, #-4]!; str r1, [sp, #-4]!
++#define do_push4(r1, r2, r3, r4) \
++        do_push3 (r2, r3, r4);\
++        do_push1 (r1)
++#define do_push5(r1, r2, r3, r4, r5) \
++        do_push4 (r2, r3, r4, r5);\
++        do_push1 (r1)
++        
++#define do_pop(...) \
++_buildN1(do_pop, _buildC1(__VA_ARGS__))( __VA_ARGS__)
++        
++#define do_pop1(r1) ldr r1, [sp], #4
++#define do_pop2(r1, r2) ldr r1, [sp], #4 ; ldr r2, [sp], #4
++#define do_pop3(r1, r2, r3) ldr r1, [sp], #4 ; str r2, [sp], #4; str r3, [sp], #4
++#define do_pop4(r1, r2, r3, r4) \
++        do_pop1 (r1);\
++        do_pup3 (r2, r3, r4)
++#define do_pop5(r1, r2, r3, r4, r5) \
++        do_pop1 (r1);\
++        do_pop4 (r2, r3, r4, r5)
++#else
++#define do_push(...)    stmfd sp!, { __VA_ARGS__}
++#define do_pop(...)     ldmfd sp!, {__VA_ARGS__}
++#endif
++
++        
+ #define COND(op1, op2, cond) op1 ## cond ## op2
+ .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp
+ 	\name \dest, \src1, \src2, \shiftop \shiftreg
+@@ -1260,7 +1294,7 @@
+ 	ARM_FUNC_START div0
+ #endif
+ 
+-	do_push	{r1, lr}
++	do_push	(r1, lr)
+ 	mov	r0, #SIGFPE
+ 	bl	SYM(raise) __PLT__
+ 	RETLDM	r1
+@@ -1277,7 +1311,7 @@
+ #if defined __ARM_EABI__ && defined __linux__
+ @ EABI GNU/Linux call to cacheflush syscall.
+ 	ARM_FUNC_START clear_cache
+-	do_push	{r7}
++	do_push	(r7)
+ #if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__)
+ 	movw	r7, #2
+ 	movt	r7, #0xf
+@@ -1287,7 +1321,7 @@
+ #endif
+ 	mov	r2, #0
+ 	swi	0
+-	do_pop	{r7}
++	do_pop	(r7)
+ 	RET
+ 	FUNC_END clear_cache
+ #else
+@@ -1490,7 +1524,7 @@
+ 	push	{r4, lr}
+ # else
+ ARM_FUNC_START clzdi2
+-	do_push	{r4, lr}
++	do_push	(r4, lr)
+ # endif
+ 	cmp	xxh, #0
+ 	bne	1f
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-07-30 14:17:05 +0000
++++ new/gcc/config/arm/predicates.md	2010-08-05 15:20:54 +0000
+@@ -328,6 +328,9 @@
+   HOST_WIDE_INT i = 1, base = 0;
+   rtx elt;
+ 
++  if (low_irq_latency)
++    return false;
++
+   if (count <= 1
+       || GET_CODE (XVECEXP (op, 0, 0)) != SET)
+     return false;
+@@ -385,6 +388,9 @@
+   HOST_WIDE_INT i = 1, base = 0;
+   rtx elt;
+ 
++  if (low_irq_latency)
++    return false;
++
+   if (count <= 1
+       || GET_CODE (XVECEXP (op, 0, 0)) != SET)
+     return false;
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-07-29 17:03:20 +0000
++++ new/gcc/doc/invoke.texi	2010-08-05 15:20:54 +0000
+@@ -469,6 +469,7 @@
+ -mtpcs-frame  -mtpcs-leaf-frame @gol
+ -mcaller-super-interworking  -mcallee-super-interworking @gol
+ -mtp=@var{name} @gol
++-mlow-irq-latency @gol
+ -mword-relocations @gol
+ -mfix-cortex-m3-ldrd}
+ 
+@@ -9489,6 +9490,12 @@
+ @code{,}, @code{!}, @code{|}, and @code{*} as needed.
+ 
+ 
++@item -mlow-irq-latency
++@opindex mlow-irq-latency
++Avoid instructions with high interrupt latency when generating
++code.  This can increase code size and reduce performance.
++The option is off by default.
++
+ @end table
+ 
+ The conditional text @code{X} in a %@{@code{S}:@code{X}@} or similar
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch
new file mode 100644
index 0000000000..40b368862d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch
@@ -0,0 +1,109 @@
+	Julian Brown  <julian@codesourcery.com>
+	Mark Shinwell  <mark@codesourcery.com>
+
+	gcc/
+	* regrename.c (addresses.h): Move include of addresses.h after
+	include of flags.h.
+	* recog.c: Likewise.
+	* regcprop.c: Likewise.
+	* config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Check against
+	LO_REGS only for Thumb-1.
+	(MODE_BASE_REG_CLASS): Restrict base registers to those which can
+	be used in short instructions when optimising for size on Thumb-2.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	Vladimir Prus  <vladimir@codesourcery.com>
+ 	Julian Brown  <julian@codesourcery.com>
+ 
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-05 15:20:54 +0000
++++ new/gcc/config/arm/arm.h	2010-08-05 15:28:47 +0000
+@@ -1254,11 +1254,14 @@
+      || reg_classes_intersect_p (VFP_REGS, (CLASS))	\
+    : 0)
+ 
+-/* We need to define this for LO_REGS on thumb.  Otherwise we can end up
+-   using r0-r4 for function arguments, r7 for the stack frame and don't
+-   have enough left over to do doubleword arithmetic.  */
++/* We need to define this for LO_REGS on Thumb-1.  Otherwise we can end up
++   using r0-r4 for function arguments, r7 for the stack frame and don't have
++   enough left over to do doubleword arithmetic.  For Thumb-2 all the
++   potentially problematic instructions accept high registers so this is not
++   necessary.  Care needs to be taken to avoid adding new Thumb-2 patterns
++   that require many low registers.  */
+ #define CLASS_LIKELY_SPILLED_P(CLASS)	\
+-    ((TARGET_THUMB && (CLASS) == LO_REGS)	\
++    ((TARGET_THUMB1 && (CLASS) == LO_REGS)	\
+      || (CLASS) == CC_REG)
+ 
+ /* The class value for index registers, and the one for base regs.  */
+@@ -1269,7 +1272,7 @@
+    when addressing quantities in QI or HI mode; if we don't know the
+    mode, then we must be conservative.  */
+ #define MODE_BASE_REG_CLASS(MODE)					\
+-    (TARGET_32BIT ? CORE_REGS :					\
++    (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS :	\
+      (((MODE) == SImode) ? BASE_REGS : LO_REGS))
+ 
+ /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
+
+=== modified file 'gcc/recog.c'
+--- old/gcc/recog.c	2010-04-02 18:54:46 +0000
++++ new/gcc/recog.c	2010-08-05 15:28:47 +0000
+@@ -31,10 +31,10 @@
+ #include "hard-reg-set.h"
+ #include "recog.h"
+ #include "regs.h"
+-#include "addresses.h"
+ #include "expr.h"
+ #include "function.h"
+ #include "flags.h"
++#include "addresses.h"
+ #include "real.h"
+ #include "toplev.h"
+ #include "basic-block.h"
+
+=== modified file 'gcc/regcprop.c'
+--- old/gcc/regcprop.c	2010-02-26 11:01:28 +0000
++++ new/gcc/regcprop.c	2010-08-05 15:28:47 +0000
+@@ -26,7 +26,6 @@
+ #include "tm_p.h"
+ #include "insn-config.h"
+ #include "regs.h"
+-#include "addresses.h"
+ #include "hard-reg-set.h"
+ #include "basic-block.h"
+ #include "reload.h"
+@@ -34,6 +33,7 @@
+ #include "function.h"
+ #include "recog.h"
+ #include "flags.h"
++#include "addresses.h"
+ #include "toplev.h"
+ #include "obstack.h"
+ #include "timevar.h"
+
+=== modified file 'gcc/regrename.c'
+--- old/gcc/regrename.c	2010-04-02 18:54:46 +0000
++++ new/gcc/regrename.c	2010-08-05 15:28:47 +0000
+@@ -26,7 +26,6 @@
+ #include "tm_p.h"
+ #include "insn-config.h"
+ #include "regs.h"
+-#include "addresses.h"
+ #include "hard-reg-set.h"
+ #include "basic-block.h"
+ #include "reload.h"
+@@ -34,6 +33,7 @@
+ #include "function.h"
+ #include "recog.h"
+ #include "flags.h"
++#include "addresses.h"
+ #include "toplev.h"
+ #include "obstack.h"
+ #include "timevar.h"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch
new file mode 100644
index 0000000000..0dbb3dbf7f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch
@@ -0,0 +1,174 @@
+	http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html
+
+	Kazu Hirata  <kazu@codesourcery.com>
+
+	gcc/testsuite/
+	* gcc.target/arm/vfp-ldmdbd.c, gcc.target/arm/vfp-ldmdbs.c,
+	gcc.target/arm/vfp-ldmiad.c, gcc.target/arm/vfp-ldmias.c,
+	gcc.target/arm/vfp-stmdbd.c, gcc.target/arm/vfp-stmdbs.c,
+	gcc.target/arm/vfp-stmiad.c, gcc.target/arm/vfp-stmias.c: New.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	Julian Brown  <julian@codesourcery.com>
+ 	Mark Shinwell  <mark@codesourcery.com>
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++extern void bar (double);
++
++void
++foo (double *p, double a, int n)
++{
++  do
++    bar (*--p + a);
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fldmdbd" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++extern void baz (float);
++
++void
++foo (float *p, float a, int n)
++{
++  do
++    bar (*--p + a);
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fldmdbs" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmiad.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++extern void bar (double);
++
++void
++foo (double *p, double a, int n)
++{
++  do
++    bar (*p++ + a);
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fldmiad" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmias.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-ldmias.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-ldmias.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++extern void baz (float);
++
++void
++foo (float *p, float a, int n)
++{
++  do
++    bar (*p++ + a);
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fldmias" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbd.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++void
++foo (double *p, double a, double b, int n)
++{
++  double c = a + b;
++  do
++    *--p = c;
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fstmdbd" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbs.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++void
++foo (float *p, float a, float b, int n)
++{
++  float c = a + b;
++  do
++    *--p = c;
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fstmdbs" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmiad.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-stmiad.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-stmiad.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++void
++foo (double *p, double a, double b, int n)
++{
++  double c = a + b;
++  do
++    *p++ = c;
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fstmiad" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmias.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-stmias.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-stmias.c	2010-08-05 15:37:24 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
++
++void
++foo (float *p, float a, float b, int n)
++{
++  float c = a + b;
++  do
++    *p++ = c;
++  while (n--);
++}
++
++/* { dg-final { scan-assembler "fstmias" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch
new file mode 100644
index 0000000000..59b598ba70
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch
@@ -0,0 +1,86 @@
+	
+	http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html
+
+	* g++.dg/other/armv7m-1.C: New.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+ 
+ 	http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html
+ 
+
+=== added file 'gcc/testsuite/g++.dg/other/armv7m-1.C'
+--- old/gcc/testsuite/g++.dg/other/armv7m-1.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/other/armv7m-1.C	2010-08-05 16:23:43 +0000
+@@ -0,0 +1,69 @@
++/* { dg-do run { target arm*-*-* } } */
++/* Test Armv7m interrupt routines.  */
++#include <stdlib.h>
++
++#ifdef __ARM_ARCH_7M__
++void __attribute__((interrupt))
++foo(void)
++{
++  long long n;
++  long p;
++  asm volatile ("" : "=r" (p) : "0" (&n));
++  if (p & 4)
++    abort ();
++  return;
++}
++
++void __attribute__((interrupt))
++bar(void)
++{
++  throw 42;
++}
++
++int main()
++{
++  int a;
++  int before;
++  int after;
++  volatile register int sp asm("sp");
++
++  asm volatile ("mov %0, sp\n"
++		"blx %2\n"
++		"mov %1, sp\n"
++		: "=&r" (before), "=r" (after) : "r" (foo)
++		: "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr");
++  if (before != after)
++    abort();
++  asm volatile ("mov %0, sp\n"
++		"sub sp, sp, #4\n"
++		"blx %2\n"
++		"add sp, sp, #4\n"
++		"mov %1, sp\n"
++		: "=&r" (before), "=r" (after) : "r" (foo)
++		: "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr");
++  if (before != after)
++    abort();
++  before = sp;
++  try
++    {
++      bar();
++    }
++  catch (int i)
++    {
++      if (i != 42)
++	abort();
++    }
++  catch (...)
++    {
++      abort();
++    }
++  if (before != sp)
++    abort();
++  exit(0);
++}
++#else
++int main()
++{
++  exit (0);
++}
++#endif
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch
new file mode 100644
index 0000000000..5d489aab69
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch
@@ -0,0 +1,132 @@
+	Backport from FSF mainline:
+
+	Mark Shinwell  <shinwell@codesourcery.com>
+	Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/thumb2.md (thumb2_movsi_insn): Split ldr and str
+	alternatives according to use of high and low regs.
+	* config/arm/vfp.md (thumb2_movsi_vfp): Likewise.
+	* config/arm/arm.h (CONDITIONAL_REGISTER_USAGE): Use high regs when
+	optimizing for size on Thumb-2.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+ 	Merge from Sourcery G++ 4.4:
+ 	
+ 	http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-05 15:28:47 +0000
++++ new/gcc/config/arm/arm.h	2010-08-05 16:34:46 +0000
+@@ -783,12 +783,11 @@
+ 	fixed_regs[regno] = call_used_regs[regno] = 1;		\
+     }								\
+ 								\
+-  if (TARGET_THUMB && optimize_size)				\
+-    {								\
+-      /* When optimizing for size, it's better not to use	\
+-	 the HI regs, because of the overhead of stacking 	\
+-	 them.  */						\
+-      /* ??? Is this still true for thumb2?  */			\
++  if (TARGET_THUMB1 && optimize_size)				\
++    {                                                           \
++      /* When optimizing for size on Thumb-1, it's better not	\
++        to use the HI regs, because of the overhead of		\
++        stacking them.  */                                      \
+       for (regno = FIRST_HI_REGNUM;				\
+ 	   regno <= LAST_HI_REGNUM; ++regno)			\
+ 	fixed_regs[regno] = call_used_regs[regno] = 1;		\
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-04-02 07:32:00 +0000
++++ new/gcc/config/arm/thumb2.md	2010-08-05 16:34:46 +0000
+@@ -223,9 +223,14 @@
+    (set_attr "neg_pool_range" "*,*,*,0,*")]
+ )
+ 
++;; We have two alternatives here for memory loads (and similarly for stores)
++;; to reflect the fact that the permissible constant pool ranges differ
++;; between ldr instructions taking low regs and ldr instructions taking high
++;; regs.  The high register alternatives are not taken into account when
++;; choosing register preferences in order to reflect their expense.
+ (define_insn "*thumb2_movsi_insn"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
+-	(match_operand:SI 1 "general_operand"	   "rk ,I,K,j,mi,rk"))]
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l, *hk,m,*m")
++	(match_operand:SI 1 "general_operand"	   "rk ,I,K,j,mi,*mi,l,*hk"))]
+   "TARGET_THUMB2 && ! TARGET_IWMMXT
+    && !(TARGET_HARD_FLOAT && TARGET_VFP)
+    && (   register_operand (operands[0], SImode)
+@@ -236,11 +241,13 @@
+    mvn%?\\t%0, #%B1
+    movw%?\\t%0, %1
+    ldr%?\\t%0, %1
++   ldr%?\\t%0, %1
++   str%?\\t%1, %0
+    str%?\\t%1, %0"
+-  [(set_attr "type" "*,*,*,*,load1,store1")
++  [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
+    (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "*,*,*,*,4096,*")
+-   (set_attr "neg_pool_range" "*,*,*,*,0,*")]
++   (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
+ )
+ 
+ (define_insn "tls_load_dot_plus_four"
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2010-07-30 14:17:05 +0000
++++ new/gcc/config/arm/vfp.md	2010-08-05 16:34:46 +0000
+@@ -86,9 +86,11 @@
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
+ )
+ 
++;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
++;; high/low register alternatives for loads and stores here.
+ (define_insn "*thumb2_movsi_vfp"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
+-      (match_operand:SI 1 "general_operand"	   "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv")
++      (match_operand:SI 1 "general_operand"	   "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))]
+   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SImode)
+        || s_register_operand (operands[1], SImode))"
+@@ -102,25 +104,27 @@
+     case 3:
+       return \"movw%?\\t%0, %1\";
+     case 4:
++    case 5:
+       return \"ldr%?\\t%0, %1\";
+-    case 5:
++    case 6:
++    case 7:
+       return \"str%?\\t%1, %0\";
+-    case 6:
++    case 8:
+       return \"fmsr%?\\t%0, %1\\t%@ int\";
+-    case 7:
++    case 9:
+       return \"fmrs%?\\t%0, %1\\t%@ int\";
+-    case 8:
++    case 10:
+       return \"fcpys%?\\t%0, %1\\t%@ int\";
+-    case 9: case 10:
++    case 11: case 12:
+       return output_move_vfp (operands);
+     default:
+       gcc_unreachable ();
+     }
+   "
+   [(set_attr "predicable" "yes")
+-   (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
+-   (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
+-   (set_attr "neg_pool_range" "*,*,*,*,   0,*,*,*,*,1008,*")]
++   (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
++   (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
++   (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
+ )
+ 
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch
new file mode 100644
index 0000000000..3e63611305
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch
@@ -0,0 +1,68 @@
+2010-08-06  Yao Qi  <yao@codesourcery.com>
+
+	LP: #612011
+	gcc/ 
+	* config/arm/arm.c (output_move_double): Fix typo generating 
+	instructions ('ldr'->'str').
+
+	gcc/testsuite/
+	* gcc.target/arm/pr45094.c: New test.
+
+ 2010-08-02  Ulrich Weigand  <uweigand@de.ibm.com>
+ 
+ 	LP: #604874
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-10 13:31:21 +0000
++++ new/gcc/config/arm/arm.c	2010-08-10 14:03:02 +0000
+@@ -12506,13 +12506,13 @@
+ 	    {
+ 	      if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
+ 		{
+-		  output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
+-		  output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
++		  output_asm_insn ("str%?\t%0, [%1, %2]!", otherops);
++		  output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
+ 		}
+ 	      else
+ 		{
+-		  output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
+-		  output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
++		  output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
++		  output_asm_insn ("str%?\t%0, [%1], %2", otherops);
+ 		}
+ 	    }
+ 	  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr45094.c'
+--- old/gcc/testsuite/gcc.target/arm/pr45094.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr45094.c	2010-08-06 05:10:03 +0000
+@@ -0,0 +1,27 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2 -mcpu=cortex-a8" } */
++/* { dg-add-options arm_neon } */
++
++#include <stdlib.h>
++
++long long buffer[32];
++
++void __attribute__((noinline)) f(long long *p, int n)
++{
++  while (--n >= 0)
++    {
++      *p = 1;
++      p += 32;
++    }
++}
++
++int main(void)
++{
++  f(buffer, 1);
++  
++  if (!buffer[0])
++    abort();
++
++  return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch
new file mode 100644
index 0000000000..f75a74091f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch
@@ -0,0 +1,138 @@
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+	
+	Mark Shinwell  <shinwell@codesourcery.com>
+
+	gcc/
+	* config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp)
+	(*arm_movdi_vfp, *thumb2_movdi_vfp, *movsf_vfp, *thumb2_movsf_vfp)
+	(*movdf_vfp, *thumb2_movdf_vfp, *movsfcc_vfp, *thumb2_movsfcc_vfp)
+	(*movdfcc_vfp, *thumb2_movdfcc_vfp): Add neon_type.
+	* config/arm/arm.md (neon_type): Update comment.
+
+ 2010-08-10  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-10 13:31:21 +0000
++++ new/gcc/config/arm/arm.md	2010-08-12 11:29:02 +0000
+@@ -255,8 +255,6 @@
+ (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
+ 
+ ;; Classification of NEON instructions for scheduling purposes.
+-;; Do not set this attribute and the "type" attribute together in
+-;; any one instruction pattern.
+ (define_attr "neon_type"
+    "neon_int_1,\
+    neon_int_2,\
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2010-08-10 13:31:21 +0000
++++ new/gcc/config/arm/vfp.md	2010-08-12 11:29:02 +0000
+@@ -82,6 +82,7 @@
+   "
+   [(set_attr "predicable" "yes")
+    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
++   (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
+    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
+ )
+@@ -123,6 +124,7 @@
+   "
+   [(set_attr "predicable" "yes")
+    (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
++   (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
+    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
+    (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
+ )
+@@ -160,6 +162,7 @@
+     }
+   "
+   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
++   (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
+    (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
+ 			       (eq_attr "alternative" "5")
+ 				(if_then_else
+@@ -198,6 +201,7 @@
+     }
+   "
+   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
++   (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
+    (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
+ 			       (eq_attr "alternative" "5")
+ 				(if_then_else
+@@ -352,6 +356,7 @@
+   [(set_attr "predicable" "yes")
+    (set_attr "type"
+      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
++   (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
+    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
+    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
+ )
+@@ -388,6 +393,7 @@
+   [(set_attr "predicable" "yes")
+    (set_attr "type"
+      "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
++   (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
+    (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
+    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
+ )
+@@ -430,6 +436,7 @@
+   "
+   [(set_attr "type"
+      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
++   (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
+    (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
+ 			       (eq_attr "alternative" "7")
+ 				(if_then_else
+@@ -474,6 +481,7 @@
+   "
+   [(set_attr "type"
+      "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
++   (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
+    (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
+ 			       (eq_attr "alternative" "7")
+ 				(if_then_else
+@@ -509,7 +517,8 @@
+    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
+    [(set_attr "conds" "use")
+     (set_attr "length" "4,4,8,4,4,8,4,4,8")
+-    (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
++    (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
++    (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
+ )
+ 
+ (define_insn "*thumb2_movsfcc_vfp"
+@@ -532,7 +541,8 @@
+    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
+    [(set_attr "conds" "use")
+     (set_attr "length" "6,6,10,6,6,10,6,6,10")
+-    (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
++    (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
++    (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
+ )
+ 
+ (define_insn "*movdfcc_vfp"
+@@ -555,7 +565,8 @@
+    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
+    [(set_attr "conds" "use")
+     (set_attr "length" "4,4,8,4,4,8,4,4,8")
+-    (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
++    (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
++    (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
+ )
+ 
+ (define_insn "*thumb2_movdfcc_vfp"
+@@ -578,7 +589,8 @@
+    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
+    [(set_attr "conds" "use")
+     (set_attr "length" "6,6,10,6,6,10,6,6,10")
+-    (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
++    (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
++    (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
+ )
+ 
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch
new file mode 100644
index 0000000000..9b56560942
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch
@@ -0,0 +1,95 @@
+	gcc/
+	* config/arm/arm.c (arm_override_options): Override alignments if
+	tuning for Cortex-A8.
+	(create_fix_barrier, arm_reorg): If aligning to jumps or loops,
+	make labels have a size.
+	* config/arm/arm.md (VUNSPEC_ALIGN16, VUNSPEC_ALIGN32): New constants.
+	(align_16, align_32): New patterns.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+ 	
+ 	Mark Shinwell  <shinwell@codesourcery.com>
+ 
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-10 14:03:02 +0000
++++ new/gcc/config/arm/arm.c	2010-08-12 11:33:54 +0000
+@@ -1449,6 +1449,16 @@
+      chosen.  */
+   gcc_assert (arm_tune != arm_none);
+ 
++  if (arm_tune == cortexa8 && optimize >= 3)
++    {
++      /* These alignments were experimentally determined to improve SPECint
++	 performance on SPECCPU 2000.  */
++      if (align_functions <= 0)
++	align_functions = 16;
++      if (align_jumps <= 0)
++	align_jumps = 16;
++    }
++
+   tune_flags = all_cores[(int)arm_tune].flags;
+ 
+   if (target_fp16_format_name)
+@@ -11263,7 +11273,10 @@
+       gcc_assert (GET_CODE (from) != BARRIER);
+ 
+       /* Count the length of this insn.  */
+-      count += get_attr_length (from);
++      if (LABEL_P (from) && (align_jumps > 0 || align_loops > 0))
++        count += MAX (align_jumps, align_loops);
++      else
++        count += get_attr_length (from);
+ 
+       /* If there is a jump table, add its length.  */
+       tmp = is_jump_table (from);
+@@ -11603,6 +11616,8 @@
+ 	      insn = table;
+ 	    }
+ 	}
++      else if (LABEL_P (insn) && (align_jumps > 0 || align_loops > 0))
++	address += MAX (align_jumps, align_loops);
+     }
+ 
+   fix = minipool_fix_head;
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-12 11:29:02 +0000
++++ new/gcc/config/arm/arm.md	2010-08-12 11:33:54 +0000
+@@ -135,6 +135,8 @@
+    (VUNSPEC_WCMP_EQ  12) ; Used by the iWMMXt WCMPEQ instructions
+    (VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions
+    (VUNSPEC_WCMP_GT  14) ; Used by the iwMMXT WCMPGT instructions
++   (VUNSPEC_ALIGN16  15) ; Used to force 16-byte alignment.
++   (VUNSPEC_ALIGN32  16) ; Used to force 32-byte alignment.
+    (VUNSPEC_EH_RETURN 20); Use to override the return address for exception
+ 			 ; handling.
+   ]
+@@ -11042,6 +11044,24 @@
+   "
+ )
+ 
++(define_insn "align_16"
++  [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN16)]
++  "TARGET_EITHER"
++  "*
++  assemble_align (128);
++  return \"\";
++  "
++)
++
++(define_insn "align_32"
++  [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN32)]
++  "TARGET_EITHER"
++  "*
++  assemble_align (256);
++  return \"\";
++  "
++)
++
+ (define_insn "consttable_end"
+   [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
+   "TARGET_EITHER"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch
new file mode 100644
index 0000000000..850acb31b0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch
@@ -0,0 +1,36 @@
+	2008-09-08  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	gcc/
+	* config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
+	for barrier handlers.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	gcc/
+ 	* config/arm/arm.c (arm_override_options): Override alignments if
+ 	tuning for Cortex-A8.
+
+=== modified file 'gcc/config/arm/unwind-arm.c'
+--- old/gcc/config/arm/unwind-arm.c	2009-10-30 14:55:10 +0000
++++ new/gcc/config/arm/unwind-arm.c	2010-08-12 12:39:35 +0000
+@@ -1196,8 +1196,6 @@
+ 		  ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
+ 
+ 		  if (data[0] & uint32_highbit)
+-		    phase2_call_unexpected_after_unwind = 1;
+-		  else
+ 		    {
+ 		      data += rtti_count + 1;
+ 		      /* Setup for entry to the handler.  */
+@@ -1207,6 +1205,8 @@
+ 		      _Unwind_SetGR (context, 0, (_uw) ucbp);
+ 		      return _URC_INSTALL_CONTEXT;
+ 		    }
++		  else
++		    phase2_call_unexpected_after_unwind = 1;
+ 		}
+ 	      if (data[0] & uint32_highbit)
+ 		data++;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch
new file mode 100644
index 0000000000..632e80caf7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch
@@ -0,0 +1,111 @@
+	2009-06-23  Kazu Hirata  <kazu@codesourcery.com>
+
+	Issue #4613
+	gcc/
+	* config/arm/arm.c (arm_rtx_costs_1): Teach that the cost of MLS
+	is the same as its underlying multiplication.
+	* config/arm/arm.md (two splitters): New.
+	* config/arm/predicates.md (binary_operator): New.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2008-09-08  Daniel Jacobowitz  <dan@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-12 11:33:54 +0000
++++ new/gcc/config/arm/arm.c	2010-08-12 13:35:39 +0000
+@@ -6604,6 +6604,19 @@
+ 	  return true;
+ 	}
+ 
++      /* MLS is just as expensive as its underlying multiplication.
++	 Exclude a shift by a constant, which is expressed as a
++	 multiplication.  */
++      if (TARGET_32BIT && arm_arch_thumb2
++	  && GET_CODE (XEXP (x, 1)) == MULT
++	  && ! (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
++		&& ((INTVAL (XEXP (XEXP (x, 1), 1)) &
++		     (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
++	{
++	  /* The cost comes from the cost of the multiply.  */
++	  return false;
++	}
++
+       /* Fall through */
+ 
+     case PLUS:
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-12 11:33:54 +0000
++++ new/gcc/config/arm/arm.md	2010-08-12 13:35:39 +0000
+@@ -1355,6 +1355,49 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
++; The combiner cannot combine the first and last insns in the
++; following sequence because of the intervening insn, so help the
++; combiner with this splitter.  The combiner does attempt to split
++; this particular combination but does not know this exact split.
++; Note that the combiner puts the constant at the outermost operation
++; as a part of canonicalization.
++;
++; mul r3, r2, r1
++; <add/sub> r3, r3, <constant>
++; add r3, r3, r4
++
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(match_operator:SI 1 "plusminus_operator"
++	 [(plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "")
++			    (match_operand:SI 3 "s_register_operand" ""))
++		   (match_operand:SI 4 "s_register_operand" ""))
++	  (match_operand:SI 5 "arm_immediate_operand" "")]))]
++  "TARGET_32BIT"
++  [(set (match_dup 0)
++	(plus:SI (mult:SI (match_dup 2) (match_dup 3))
++		 (match_dup 4)))
++   (set (match_dup 0)
++	(match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))]
++  "")
++
++; Likewise for MLS.  MLS is available only on select architectures.
++
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(match_operator:SI 1 "plusminus_operator"
++	 [(minus:SI (match_operand:SI 2 "s_register_operand" "")
++		    (mult:SI (match_operand:SI 3 "s_register_operand" "")
++			     (match_operand:SI 4 "s_register_operand" "")))
++	  (match_operand:SI 5 "arm_immediate_operand" "")]))]
++  "TARGET_32BIT && arm_arch_thumb2"
++  [(set (match_dup 0)
++	(minus:SI (match_dup 2)
++		  (mult:SI (match_dup 3) (match_dup 4))))
++   (set (match_dup 0)
++	(match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))]
++  "")
++
+ (define_insn "*mulsi3addsi_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-08-10 13:31:21 +0000
++++ new/gcc/config/arm/predicates.md	2010-08-12 13:35:39 +0000
+@@ -197,6 +197,11 @@
+   (and (match_code "plus,minus,ior,xor,and")
+        (match_test "mode == GET_MODE (op)")))
+ 
++;; True for plus/minus operators
++(define_special_predicate "plusminus_operator"
++  (and (match_code "plus,minus")
++       (match_test "mode == GET_MODE (op)")))
++
+ ;; True for logical binary operators.
+ (define_special_predicate "logical_binary_operator"
+   (and (match_code "ior,xor,and")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch
new file mode 100644
index 0000000000..f4a8e80ab7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch
@@ -0,0 +1,236 @@
+	Backport from FSF mainline:
+
+	gcc/
+	* gengtype-lex.l: Add HARD_REG_SET.
+	* expr.c (expand_expr_real_1): Record writes to hard registers.
+	* function.h (rtl_data): Add asm_clobbers.
+	* ira.c (compute_regs_asm_clobbered): Use crtl->asm_clobbers.
+	(ira_setup_eliminable_regset): Remove regs_asm_clobbered.
+	Use crtl->asm_clobbers.
+
+	gcc/testsuite/
+	* gcc.target/arm/frame-pointer-1.c: New test.
+	* gcc.target/i386/pr9771-1.c: Move code out of main to allow frame
+	pointer elimination.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+ 	Merge from Sourcery G++ 4.4:
+ 
+ 	2009-06-23  Kazu Hirata  <kazu@codesourcery.com>
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2010-05-31 14:45:06 +0000
++++ new/gcc/expr.c	2010-08-12 13:51:16 +0000
+@@ -8458,6 +8458,19 @@
+     expand_decl_rtl:
+       gcc_assert (decl_rtl);
+       decl_rtl = copy_rtx (decl_rtl);
++      /* Record writes to register variables.  */
++      if (modifier == EXPAND_WRITE && REG_P (decl_rtl)
++	  && REGNO (decl_rtl) < FIRST_PSEUDO_REGISTER)
++	{
++	    int i = REGNO (decl_rtl);
++	    int nregs = hard_regno_nregs[i][GET_MODE (decl_rtl)];
++	    while (nregs)
++	      {
++		SET_HARD_REG_BIT (crtl->asm_clobbers, i);
++		i++;
++		nregs--;
++	      }
++	}
+ 
+       /* Ensure variable marked as used even if it doesn't go through
+ 	 a parser.  If it hasn't be used yet, write out an external
+
+=== modified file 'gcc/function.h'
+--- old/gcc/function.h	2009-11-25 10:55:54 +0000
++++ new/gcc/function.h	2010-08-12 13:51:16 +0000
+@@ -25,6 +25,7 @@
+ #include "tree.h"
+ #include "hashtab.h"
+ #include "vecprim.h"
++#include "hard-reg-set.h"
+ 
+ /* Stack of pending (incomplete) sequences saved by `start_sequence'.
+    Each element describes one pending sequence.
+@@ -433,6 +434,12 @@
+      TREE_NOTHROW (current_function_decl) it is set even for overwritable
+      function where currently compiled version of it is nothrow.  */
+   bool nothrow;
++
++  /* Like regs_ever_live, but 1 if a reg is set or clobbered from an
++     asm.  Unlike regs_ever_live, elements of this array corresponding
++     to eliminable regs (like the frame pointer) are set if an asm
++     sets them.  */
++  HARD_REG_SET asm_clobbers;
+ };
+ 
+ #define return_label (crtl->x_return_label)
+
+=== modified file 'gcc/gengtype-lex.l'
+--- old/gcc/gengtype-lex.l	2009-11-21 10:24:25 +0000
++++ new/gcc/gengtype-lex.l	2010-08-12 13:51:16 +0000
+@@ -49,7 +49,7 @@
+ ID	[[:alpha:]_][[:alnum:]_]*
+ WS	[[:space:]]+
+ HWS	[ \t\r\v\f]*
+-IWORD	short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t
++IWORD	short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t|HARD_REG_SET
+ ITYPE	{IWORD}({WS}{IWORD})*
+ EOID	[^[:alnum:]_]
+ 
+
+=== modified file 'gcc/ira.c'
+--- old/gcc/ira.c	2010-03-31 01:44:10 +0000
++++ new/gcc/ira.c	2010-08-12 13:51:16 +0000
+@@ -1385,14 +1385,12 @@
+   return for_each_rtx (&insn, insn_contains_asm_1, NULL);
+ }
+ 
+-/* Set up regs_asm_clobbered.  */
++/* Add register clobbers from asm statements.  */
+ static void
+-compute_regs_asm_clobbered (char *regs_asm_clobbered)
++compute_regs_asm_clobbered (void)
+ {
+   basic_block bb;
+ 
+-  memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER);
+-
+   FOR_EACH_BB (bb)
+     {
+       rtx insn;
+@@ -1413,7 +1411,7 @@
+ 		      + hard_regno_nregs[dregno][mode] - 1;
+ 
+ 		    for (i = dregno; i <= end; ++i)
+-		      regs_asm_clobbered[i] = 1;
++		      SET_HARD_REG_BIT(crtl->asm_clobbers, i);
+ 		  }
+ 	      }
+ 	}
+@@ -1425,12 +1423,6 @@
+ void
+ ira_setup_eliminable_regset (void)
+ {
+-  /* Like regs_ever_live, but 1 if a reg is set or clobbered from an
+-     asm.  Unlike regs_ever_live, elements of this array corresponding
+-     to eliminable regs (like the frame pointer) are set if an asm
+-     sets them.  */
+-  char *regs_asm_clobbered
+-    = (char *) alloca (FIRST_PSEUDO_REGISTER * sizeof (char));
+ #ifdef ELIMINABLE_REGS
+   int i;
+   static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
+@@ -1454,7 +1446,8 @@
+   COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs);
+   CLEAR_HARD_REG_SET (eliminable_regset);
+ 
+-  compute_regs_asm_clobbered (regs_asm_clobbered);
++  compute_regs_asm_clobbered ();
++
+   /* Build the regset of all eliminable registers and show we can't
+      use those that we already know won't be eliminated.  */
+ #ifdef ELIMINABLE_REGS
+@@ -1464,7 +1457,7 @@
+ 	= (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to)
+ 	   || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp));
+ 
+-      if (! regs_asm_clobbered[eliminables[i].from])
++      if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from))
+ 	{
+ 	    SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from);
+ 
+@@ -1478,7 +1471,7 @@
+ 	df_set_regs_ever_live (eliminables[i].from, true);
+     }
+ #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
+-  if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM])
++  if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
+     {
+       SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM);
+       if (need_fp)
+@@ -1492,7 +1485,7 @@
+ #endif
+ 
+ #else
+-  if (! regs_asm_clobbered[FRAME_POINTER_REGNUM])
++  if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
+     {
+       SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM);
+       if (need_fp)
+
+=== added file 'gcc/testsuite/gcc.target/arm/frame-pointer-1.c'
+--- old/gcc/testsuite/gcc.target/arm/frame-pointer-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/frame-pointer-1.c	2010-08-12 13:51:16 +0000
+@@ -0,0 +1,42 @@
++/* Check local register variables using a register conventionally 
++   used as the frame pointer aren't clobbered under high register pressure.  */
++/* { dg-do run } */
++/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */
++
++#include <stdlib.h>
++
++int global=5;
++
++void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4)
++{
++  if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4)
++    abort();
++}
++
++int __attribute__((noinline)) test(int a, int b, int c, int d)
++{
++  register unsigned long r __asm__("r7") = 0xdeadbeef;
++  int e;
++
++  /* ABCD are live after the call which should be enough
++     to cause r7 to be used if it weren't for the register variable.  */
++  foo(a,b,c,d);
++
++  e = 0;
++  __asm__ __volatile__ ("mov %0, %2"
++			: "=r" (e)
++			: "0" (e), "r" (r));
++
++  global = a+b+c+d;
++
++  return e;
++}
++
++int main()
++{
++  if (test(1, 2, 3, 4) != 0xdeadbeef)
++    abort();
++  if (global != 10)
++    abort();
++  return 0;
++}
+
+=== modified file 'gcc/testsuite/gcc.target/i386/pr9771-1.c'
+--- old/gcc/testsuite/gcc.target/i386/pr9771-1.c	2007-08-22 08:59:14 +0000
++++ new/gcc/testsuite/gcc.target/i386/pr9771-1.c	2010-08-12 13:51:16 +0000
+@@ -28,7 +28,10 @@
+   *adr = save;
+ }
+ 
+-int main()
++/* This must not be inlined becuase main() requires the frame pointer
++   for stack alignment.  */
++void test(void) __attribute__((noinline));
++void test(void)
+ {
+   B = &x;
+ 
+@@ -42,3 +45,9 @@
+   exit(0);
+ }
+ 
++int main()
++{
++  test();
++  return 0;
++
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch
new file mode 100644
index 0000000000..31fa99a2e3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch
@@ -0,0 +1,43 @@
+	Merge from Sourcery G++ 4.4:
+	
+	2009-08-26  Kazu Hirata  <kazu@codesourcery.com>
+
+	Issue #6089
+	gcc/
+	* config/arm/arm.c (arm_rtx_costs_1): Don't special case for
+	Thumb-2 in the MINUS case.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+ 	Backport from FSF mainline:
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-12 13:35:39 +0000
++++ new/gcc/config/arm/arm.c	2010-08-12 14:08:29 +0000
+@@ -6494,23 +6494,6 @@
+       return true;
+ 
+     case MINUS:
+-      if (TARGET_THUMB2)
+-	{
+-	  if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	    {
+-	      if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
+-		*total = COSTS_N_INSNS (1);
+-	      else
+-		*total = COSTS_N_INSNS (20);
+-	    }
+-	  else
+-	    *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-	  /* Thumb2 does not have RSB, so all arguments must be
+-	     registers (subtracting a constant is canonicalized as
+-	     addition of the negated constant).  */
+-	  return false;
+-	}
+-
+       if (mode == DImode)
+ 	{
+ 	  *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch
new file mode 100644
index 0000000000..d9073123c4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch
@@ -0,0 +1,28 @@
+	2009-08-26  Julian Brown  <julian@codesourcery.com>
+
+	gcc/config/arm/
+	* uclinux-eabi.h (LINK_GCC_C_SEQUENCE_SPEC): Override definition
+	for uclinux.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+ 	
+ 	2009-08-26  Kazu Hirata  <kazu@codesourcery.com>
+ 
+
+=== modified file 'gcc/config/arm/uclinux-eabi.h'
+--- old/gcc/config/arm/uclinux-eabi.h	2009-02-20 15:20:38 +0000
++++ new/gcc/config/arm/uclinux-eabi.h	2010-08-12 15:23:21 +0000
+@@ -50,6 +50,10 @@
+ #undef ARM_DEFAULT_ABI
+ #define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX
+ 
++#undef LINK_GCC_C_SEQUENCE_SPEC
++#define LINK_GCC_C_SEQUENCE_SPEC \
++  "--start-group %G %L --end-group"
++
+ /* Clear the instruction cache from `beg' to `end'.  This makes an
+    inline system call to SYS_cacheflush.  */
+ #undef CLEAR_INSN_CACHE
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch
new file mode 100644
index 0000000000..02db2b4e7e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch
@@ -0,0 +1,76 @@
+	2010-05-25  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_tune_cortex_a5): New.
+	(arm_override_options): Set above. Set max_insns_skipped to 1 for
+	Cortex-A5.
+	* config/arm/arm.h (arm_tune_cortex_a5): Add declaration.
+	(BRANCH_COST): Set to zero for Cortex-A5 unless optimising for
+	size.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2009-08-26  Julian Brown  <julian@codesourcery.com>
+ 
+ 	gcc/config/arm/
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-12 14:08:29 +0000
++++ new/gcc/config/arm/arm.c	2010-08-12 16:18:41 +0000
+@@ -671,6 +671,9 @@
+    This typically means an ARM6 or ARM7 with MMU or MPU.  */
+ int arm_tune_wbuf = 0;
+ 
++/* Nonzero if tuning for Cortex-A5.  */
++int arm_tune_cortex_a5 = 0;
++
+ /* Nonzero if tuning for Cortex-A9.  */
+ int arm_tune_cortex_a9 = 0;
+ 
+@@ -1582,6 +1585,7 @@
+   arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
+   arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
+   arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
++  arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0;
+   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
+ 
+   /* If we are not using the default (ARM mode) section anchor offset
+@@ -1880,6 +1884,11 @@
+          that is worth skipping is shorter.  */
+       if (arm_tune_strongarm)
+         max_insns_skipped = 3;
++
++      /* Branches can be dual-issued on Cortex-A5, so conditional execution is
++	 less appealing.  */
++      if (arm_tune_cortex_a5)
++        max_insns_skipped = 1;
+     }
+ 
+   /* Hot/Cold partitioning is not currently supported, since we can't
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-05 16:34:46 +0000
++++ new/gcc/config/arm/arm.h	2010-08-12 16:18:41 +0000
+@@ -435,6 +435,9 @@
+ /* Nonzero if tuning for stores via the write buffer.  */
+ extern int arm_tune_wbuf;
+ 
++/* Nonzero if tuning for Cortex-A5.  */
++extern int arm_tune_cortex_a5;
++
+ /* Nonzero if tuning for Cortex-A9.  */
+ extern int arm_tune_cortex_a9;
+ 
+@@ -2222,7 +2225,8 @@
+ /* Try to generate sequences that don't involve branches, we can then use
+    conditional instructions */
+ #define BRANCH_COST(speed_p, predictable_p) \
+-  (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \
++  (TARGET_32BIT ? ((arm_tune_cortex_a5 && !optimize_size) ? 0 \
++		   : (TARGET_THUMB2 && optimize_size ? 1 : 4)) \
+ 		: (optimize > 0 ? 2 : 0))
+ 
+ /* Position Independent Code.  */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch
new file mode 100644
index 0000000000..86b2d81093
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch
@@ -0,0 +1,132 @@
+	Backport from FSF mainline:
+
+	gcc/
+	* config/arm/thumb2.md (*thumb2_addsi3_compare0): New.
+	(*thumb2_addsi3_compare0_scratch): New.
+	* config/arm/constraints.md (Pv): New.
+	* config/arm/arm.md (*addsi3_compare0): Remove FIXME comment. Use
+	for ARM mode only.
+	(*addsi3_compare0_scratch): Likewise.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+ 	Merge from Sourcery G++ 4.4:
+ 
+ 	2010-05-25  Julian Brown  <julian@codesourcery.com>
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-12 13:35:39 +0000
++++ new/gcc/config/arm/arm.md	2010-08-12 16:47:21 +0000
+@@ -701,7 +701,6 @@
+   ""
+ )
+ 
+-;; ??? Make Thumb-2 variants which prefer low regs
+ (define_insn "*addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+@@ -710,7 +709,7 @@
+ 	 (const_int 0)))
+    (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ 	(plus:SI (match_dup 1) (match_dup 2)))]
+-  "TARGET_32BIT"
++  "TARGET_ARM"
+   "@
+    add%.\\t%0, %1, %2
+    sub%.\\t%0, %1, #%n2"
+@@ -723,7 +722,7 @@
+ 	 (plus:SI (match_operand:SI 0 "s_register_operand" "r, r")
+ 		  (match_operand:SI 1 "arm_add_operand"    "rI,L"))
+ 	 (const_int 0)))]
+-  "TARGET_32BIT"
++  "TARGET_ARM"
+   "@
+    cmn%?\\t%0, %1
+    cmp%?\\t%0, #%n1"
+
+=== modified file 'gcc/config/arm/constraints.md'
+--- old/gcc/config/arm/constraints.md	2010-07-29 16:58:56 +0000
++++ new/gcc/config/arm/constraints.md	2010-08-12 16:47:21 +0000
+@@ -31,7 +31,7 @@
+ ;; The following multi-letter normal constraints have been used:
+ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
+ ;; in Thumb-1 state: Pa, Pb
+-;; in Thumb-2 state: Ps, Pt
++;; in Thumb-2 state: Ps, Pt, Pv
+ 
+ ;; The following memory constraints have been used:
+ ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
+@@ -158,6 +158,11 @@
+   (and (match_code "const_int")
+        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
+ 
++(define_constraint "Pv"
++  "@internal In Thumb-2 state a constant in the range -255 to 0"
++  (and (match_code "const_int")
++       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
++
+ (define_constraint "G"
+  "In ARM/Thumb-2 state a valid FPA immediate constant."
+  (and (match_code "const_double")
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-08-05 16:34:46 +0000
++++ new/gcc/config/arm/thumb2.md	2010-08-12 16:47:21 +0000
+@@ -1241,6 +1241,56 @@
+    (set_attr "length" "2")]
+ )
+ 
++(define_insn "*thumb2_addsi3_compare0"
++  [(set (reg:CC_NOOV CC_REGNUM)
++	(compare:CC_NOOV
++	  (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
++		   (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
++	  (const_int 0)))
++   (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
++	(plus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_THUMB2"
++  "*
++    HOST_WIDE_INT val;
++
++    if (GET_CODE (operands[2]) == CONST_INT)
++      val = INTVAL (operands[2]);
++    else
++      val = 0;
++
++    if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
++      return \"subs\\t%0, %1, #%n2\";
++    else
++      return \"adds\\t%0, %1, %2\";
++  "
++  [(set_attr "conds" "set")
++   (set_attr "length" "2,2,4")]
++)
++
++(define_insn "*thumb2_addsi3_compare0_scratch"
++  [(set (reg:CC_NOOV CC_REGNUM)
++	(compare:CC_NOOV
++	  (plus:SI (match_operand:SI 0 "s_register_operand" "l,  r")
++		   (match_operand:SI 1 "arm_add_operand"    "lPv,rIL"))
++	  (const_int 0)))]
++  "TARGET_THUMB2"
++  "*
++    HOST_WIDE_INT val;
++
++    if (GET_CODE (operands[1]) == CONST_INT)
++      val = INTVAL (operands[1]);
++    else
++      val = 0;
++
++    if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
++      return \"cmp\\t%0, #%n1\";
++    else
++      return \"cmn\\t%0, %1\";
++  "
++  [(set_attr "conds" "set")
++   (set_attr "length" "2,4")]
++)
++
+ ;; 16-bit encodings of "muls" and "mul<c>".  We only use these when
+ ;; optimizing for size since "muls" is slow on all known
+ ;; implementations and since "mul<c>" will be generated by
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch
new file mode 100644
index 0000000000..d03ee9406e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch
@@ -0,0 +1,30 @@
+	2010-02-03  Daniel Gutson  <dgutson@codesourcery.com>
+
+	Issue #6472
+
+	gcc/
+	* config/arm/lib1funcs.asm (__ARM_ARCH__): __ARM_ARCH_7EM__
+	added to the preprocessor condition.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Backport from FSF mainline:
+
+ 	gcc/
+ 	* config/arm/thumb2.md (*thumb2_addsi3_compare0): New.
+ 	(*thumb2_addsi3_compare0_scratch): New.
+
+=== modified file 'gcc/config/arm/lib1funcs.asm'
+--- old/gcc/config/arm/lib1funcs.asm	2010-08-05 15:20:54 +0000
++++ new/gcc/config/arm/lib1funcs.asm	2010-08-12 16:49:44 +0000
+@@ -104,7 +104,8 @@
+ #endif
+ 
+ #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
+-	|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__)
++	|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
++	|| defined(__ARM_ARCH_7EM__)
+ # define __ARM_ARCH__ 7
+ #endif
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch
new file mode 100644
index 0000000000..757e66c8b4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch
@@ -0,0 +1,30 @@
+	Merge from Sourcery G++ 4.4:
+
+	2010-02-04  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	Issue #7197 - backtrace() through throw()
+
+	libstdc++-v3/
+	* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): For
+	ARM EABI, skip handlers for _US_VIRTUAL_UNWIND_FRAME
+	| _US_FORCE_UNWIND.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+ 	Backport from FSF mainline:
+ 
+ 	2010-02-03  Daniel Gutson  <dgutson@codesourcery.com>
+
+=== modified file 'libstdc++-v3/libsupc++/eh_personality.cc'
+--- old/libstdc++-v3/libsupc++/eh_personality.cc	2010-02-17 05:43:24 +0000
++++ new/libstdc++-v3/libsupc++/eh_personality.cc	2010-08-12 16:53:10 +0000
+@@ -383,6 +383,8 @@
+   switch (state & _US_ACTION_MASK)
+     {
+     case _US_VIRTUAL_UNWIND_FRAME:
++      if (state & _US_FORCE_UNWIND)
++	CONTINUE_UNWINDING;
+       actions = _UA_SEARCH_PHASE;
+       break;
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch
new file mode 100644
index 0000000000..4807195158
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch
@@ -0,0 +1,170 @@
+	Backport from FSF mainline:
+
+	Julian Brown  <julian@codesourcery.com>
+	Mark Mitchell  <mark@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid
+	sibling calls for Thumb-1.
+	* config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2.
+	* config/arm/arm.md (*call_symbol, *call_value_symbol): Use for
+	Thumb-2.
+	(*call_insn, *call_value_insn): Don't use for Thumb-2.
+	(sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use
+	for Thumb-2.
+	(return): New expander.
+	(*arm_return): New name for ARM return insn.
+	* config/arm/thumb2.md (*thumb2_return): New insn pattern.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+ 	Merge from Sourcery G++ 4.4:
+ 
+ 	2010-02-04  Daniel Jacobowitz  <dan@codesourcery.com>
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-12 16:18:41 +0000
++++ new/gcc/config/arm/arm.c	2010-08-13 10:30:35 +0000
+@@ -4886,8 +4886,8 @@
+     return false;
+ 
+   /* Never tailcall something for which we have no decl, or if we
+-     are in Thumb mode.  */
+-  if (decl == NULL || TARGET_THUMB)
++     are generating code for Thumb-1.  */
++  if (decl == NULL || TARGET_THUMB1)
+     return false;
+ 
+   /* The PIC register is live on entry to VxWorks PLT entries, so we
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-12 16:18:41 +0000
++++ new/gcc/config/arm/arm.h	2010-08-13 10:30:35 +0000
+@@ -1833,11 +1833,8 @@
+ 
+ /* Determine if the epilogue should be output as RTL.
+    You should override this if you define FUNCTION_EXTRA_EPILOGUE.  */
+-/* This is disabled for Thumb-2 because it will confuse the
+-   conditional insn counter.
+-   Do not use a return insn if we're avoiding ldm/stm instructions.  */
+ #define USE_RETURN_INSN(ISCOND)				\
+-  ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
++  ((TARGET_32BIT && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
+ 
+ /* Definitions for register eliminations.
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-12 16:47:21 +0000
++++ new/gcc/config/arm/arm.md	2010-08-13 10:30:35 +0000
+@@ -8798,7 +8798,7 @@
+ 	 (match_operand 1 "" ""))
+    (use (match_operand 2 "" ""))
+    (clobber (reg:SI LR_REGNUM))]
+-  "TARGET_ARM
++  "TARGET_32BIT
+    && (GET_CODE (operands[0]) == SYMBOL_REF)
+    && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
+   "*
+@@ -8814,7 +8814,7 @@
+ 	(match_operand:SI 2 "" "")))
+    (use (match_operand 3 "" ""))
+    (clobber (reg:SI LR_REGNUM))]
+-  "TARGET_ARM
++  "TARGET_32BIT
+    && (GET_CODE (operands[1]) == SYMBOL_REF)
+    && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
+   "*
+@@ -8829,7 +8829,7 @@
+ 	 (match_operand:SI 1 "" ""))
+    (use (match_operand 2 "" ""))
+    (clobber (reg:SI LR_REGNUM))]
+-  "TARGET_THUMB
++  "TARGET_THUMB1
+    && GET_CODE (operands[0]) == SYMBOL_REF
+    && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
+   "bl\\t%a0"
+@@ -8843,7 +8843,7 @@
+ 	      (match_operand 2 "" "")))
+    (use (match_operand 3 "" ""))
+    (clobber (reg:SI LR_REGNUM))]
+-  "TARGET_THUMB
++  "TARGET_THUMB1
+    && GET_CODE (operands[1]) == SYMBOL_REF
+    && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
+   "bl\\t%a1"
+@@ -8857,7 +8857,7 @@
+ 		    (match_operand 1 "general_operand" ""))
+ 	      (return)
+ 	      (use (match_operand 2 "" ""))])]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "
+   {
+     if (operands[2] == NULL_RTX)
+@@ -8871,7 +8871,7 @@
+ 			 (match_operand 2 "general_operand" "")))
+ 	      (return)
+ 	      (use (match_operand 3 "" ""))])]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "
+   {
+     if (operands[3] == NULL_RTX)
+@@ -8884,7 +8884,7 @@
+ 	(match_operand 1 "" ""))
+   (return)
+   (use (match_operand 2 "" ""))]
+-  "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF"
++  "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF"
+   "*
+   return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
+   "
+@@ -8897,15 +8897,20 @@
+ 	     (match_operand 2 "" "")))
+   (return)
+   (use (match_operand 3 "" ""))]
+-  "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF"
++  "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF"
+   "*
+   return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
+   "
+   [(set_attr "type" "call")]
+ )
+ 
++(define_expand "return"
++  [(return)]
++  "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
++  "")
++
+ ;; Often the return insn will be the same as loading from memory, so set attr
+-(define_insn "return"
++(define_insn "*arm_return"
+   [(return)]
+   "TARGET_ARM && USE_RETURN_INSN (FALSE)"
+   "*
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-08-12 16:47:21 +0000
++++ new/gcc/config/arm/thumb2.md	2010-08-13 10:30:35 +0000
+@@ -1054,6 +1054,19 @@
+    (set_attr "length" "20")]
+ )
+ 
++;; Note: this is not predicable, to avoid issues with linker-generated
++;; interworking stubs.
++(define_insn "*thumb2_return"
++  [(return)]
++  "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
++  "*
++  {
++    return output_return_instruction (const_true_rtx, TRUE, FALSE);
++  }"
++  [(set_attr "type" "load1")
++   (set_attr "length" "12")]
++)
++
+ (define_insn_and_split "thumb2_eh_return"
+   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
+ 		    VUNSPEC_EH_RETURN)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch
new file mode 100644
index 0000000000..f99938a7f1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch
@@ -0,0 +1,37 @@
+	2010-02-23  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* calls.c (precompute_register_parameters): Avoid generating a
+	register move if optimizing for size.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2010-02-15  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Issue #7486
+
+=== modified file 'gcc/calls.c'
+--- old/gcc/calls.c	2010-04-02 18:54:46 +0000
++++ new/gcc/calls.c	2010-08-13 10:50:45 +0000
+@@ -703,7 +703,9 @@
+ 
+ 	   For small register classes, also do this if this call uses
+ 	   register parameters.  This is to avoid reload conflicts while
+-	   loading the parameters registers.  */
++	   loading the parameters registers.
++	   
++	   Avoid creating the extra move if optimizing for size.  */
+ 
+ 	else if ((! (REG_P (args[i].value)
+ 		     || (GET_CODE (args[i].value) == SUBREG
+@@ -711,6 +713,7 @@
+ 		 && args[i].mode != BLKmode
+ 		 && rtx_cost (args[i].value, SET, optimize_insn_for_speed_p ())
+ 		    > COSTS_N_INSNS (1)
++		 && !optimize_size
+ 		 && ((SMALL_REGISTER_CLASSES && *reg_parm_seen)
+ 		     || optimize))
+ 	  args[i].value = copy_to_mode_reg (args[i].mode, args[i].value);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch
new file mode 100644
index 0000000000..a95b649e43
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch
@@ -0,0 +1,401 @@
+	* config/arm/arm.c (thumb2_size_rtx_costs): New.
+	(arm_rtx_costs): Call above for Thumb-2.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	2010-02-23  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+ 	* calls.c (precompute_register_parameters): Avoid generating a
+ 	register move if optimizing for size.
+ 
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-13 10:43:42 +0000
++++ new/gcc/config/arm/arm.c	2010-08-13 10:55:28 +0000
+@@ -141,6 +141,7 @@
+ static bool arm_have_conditional_execution (void);
+ static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
+ static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
++static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+ static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+ static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+ static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+@@ -7316,14 +7317,372 @@
+     }
+ }
+ 
++static bool
++thumb2_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
++		     int *total)
++{
++  /* Attempt to give a lower cost to RTXs which can optimistically be
++     represented as short insns, assuming that the right conditions will hold
++     later (e.g. low registers will be chosen if a short insn requires them).
++
++     Note that we don't make wide insns cost twice as much as narrow insns,
++     because we can't prove that a particular RTX will actually use a narrow
++     insn, because not enough information is available (e.g., we don't know
++     which hard registers pseudos will be assigned).  Consider these to be
++     "expected" sizes/weightings.
++
++     (COSTS_NARROW_INSNS has the same weight as COSTS_N_INSNS.)  */
++
++#define COSTS_NARROW_INSNS(N) ((N) * 4)
++#define COSTS_WIDE_INSNS(N) ((N) * 6)
++#define THUMB2_LIBCALL_COST COSTS_WIDE_INSNS (2)
++  enum machine_mode mode = GET_MODE (x);
++
++  switch (code)
++    {
++    case MEM:
++      if (REG_P (XEXP (x, 0)))
++	{
++	  /* Hopefully this will use a narrow ldm/stm insn.  */
++	  *total = COSTS_NARROW_INSNS (1);
++	  return true;
++	}
++      else if ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
++		&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
++	       || reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0))
++	       || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0)))
++	{
++	  *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
++	  return true;
++	}
++      else if (GET_CODE (XEXP (x, 0)) == PLUS)
++	{
++	  rtx plus = XEXP (x, 0);
++
++	  if (GET_CODE (XEXP (plus, 1)) == CONST_INT)
++	    {
++	      HOST_WIDE_INT cst = INTVAL (XEXP (plus, 1));
++
++	      if (cst >= 0 && cst < 256)
++		*total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
++	      else
++		*total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
++
++	      *total += rtx_cost (XEXP (plus, 0), code, false);
++
++	      return true;
++	    }
++	}
++
++      *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
++      return false;
++
++    case DIV:
++    case MOD:
++    case UDIV:
++    case UMOD:
++      if (arm_arch_hwdiv)
++	*total = COSTS_WIDE_INSNS (1);
++      else
++	*total = THUMB2_LIBCALL_COST;
++      return false;
++
++    case ROTATE:
++      if (mode == SImode && REG_P (XEXP (x, 1)))
++	{
++	  *total = COSTS_WIDE_INSNS (1) + COSTS_NARROW_INSNS (1)
++		   + rtx_cost (XEXP (x, 0), code, false);
++	  return true;
++	}
++      /* Fall through */
++
++    case ASHIFT:
++    case LSHIFTRT:
++    case ASHIFTRT:
++      if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
++	{
++	  *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false);
++	  return true;
++	}
++      else if (mode == SImode)
++	{
++	  *total = COSTS_NARROW_INSNS (1);
++	  return false;
++	}
++
++      /* Needs a libcall.  */
++      *total = THUMB2_LIBCALL_COST;
++      return false;
++
++    case ROTATERT:
++      if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
++	{
++	  *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false);
++	  return true;
++	}
++      else if (mode == SImode)
++	{
++	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
++	    *total = COSTS_WIDE_INSNS (1) + rtx_cost (XEXP (x, 0), code, false);
++	  else
++	    *total = COSTS_NARROW_INSNS (1)
++		     + rtx_cost (XEXP (x, 0), code, false);
++	  return true;
++	}
++
++      /* Needs a libcall.  */
++      *total = THUMB2_LIBCALL_COST;
++      return false;
++
++    case MINUS:
++      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
++	  && (mode == SFmode || !TARGET_VFP_SINGLE))
++	{
++	  *total = COSTS_WIDE_INSNS (1);
++	  return false;
++	}
++
++      if (mode == SImode)
++	{
++	  enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
++	  enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
++
++	  if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
++	      || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
++	      || subcode1 == ROTATE || subcode1 == ROTATERT
++	      || subcode1 == ASHIFT || subcode1 == LSHIFTRT
++	      || subcode1 == ASHIFTRT)
++	    {
++	      /* It's just the cost of the two operands.  */
++	      *total = 0;
++	      return false;
++	    }
++
++	  if (subcode1 == CONST_INT)
++	    {
++	      HOST_WIDE_INT cst = INTVAL (XEXP (x, 1));
++
++	      if (cst >= 0 && cst < 256)
++		*total = COSTS_NARROW_INSNS (1);
++	      else
++		*total = COSTS_WIDE_INSNS (1);
++
++	      *total += rtx_cost (XEXP (x, 0), code, false);
++
++	      return true;
++	    }
++
++	  *total = COSTS_NARROW_INSNS (1);
++	  return false;
++	}
++
++      *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
++      return false;
++
++    case PLUS:
++      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
++	  && (mode == SFmode || !TARGET_VFP_SINGLE))
++	{
++	  *total = COSTS_WIDE_INSNS (1);
++	  return false;
++	}
++
++      /* Fall through */
++    case AND: case XOR: case IOR:
++      if (mode == SImode)
++	{
++	  enum rtx_code subcode = GET_CODE (XEXP (x, 0));
++
++	  if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
++	      || subcode == LSHIFTRT || subcode == ASHIFTRT
++	      || (code == AND && subcode == NOT))
++	    {
++	      /* It's just the cost of the two operands.  */
++	      *total = 0;
++	      return false;
++	    }
++
++	  if (code == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
++	    {
++	      HOST_WIDE_INT cst = INTVAL (XEXP (x, 1));
++
++	      if ((reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0))
++		   || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0)))
++		  && cst > -512 && cst < 1024)
++		/* Only approximately correct, depending on destination
++		   register.  */
++		*total = COSTS_NARROW_INSNS (1);
++	      else if (cst > -256 && cst < 256)
++		*total = COSTS_NARROW_INSNS (1);
++	      else
++		*total = COSTS_WIDE_INSNS (1);
++
++	      *total += rtx_cost (XEXP (x, 0), code, false);
++
++	      return true;
++	    }
++
++	  if (subcode == MULT
++	      && power_of_two_operand (XEXP (XEXP (x, 0), 1), mode))
++	    {
++	      *total = COSTS_WIDE_INSNS (1)
++		       + rtx_cost (XEXP (x, 1), code, false);
++	      return true;
++	    }
++	}
++
++      *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
++      return false;
++
++    case MULT:
++      if (mode == SImode && GET_CODE (XEXP (x, 1)) != CONST_INT)
++	{
++	  /* Might be using muls.  */
++	  *total = COSTS_NARROW_INSNS (1);
++	  return false;
++	}
++      *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
++      return false;
++
++    case NEG:
++      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
++	  && (mode == SFmode || !TARGET_VFP_SINGLE))
++	{
++	  *total = COSTS_WIDE_INSNS (1);
++	  return false;
++	}
++
++      /* Fall through */
++    case NOT:
++      if (mode == SImode)
++	{
++	  *total = COSTS_NARROW_INSNS (1);
++	  return false;
++	}
++      *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
++      return false;
++
++    case IF_THEN_ELSE:
++      *total = COSTS_NARROW_INSNS (1);
++      return false;
++
++    case COMPARE:
++      if (cc_register (XEXP (x, 0), VOIDmode))
++	*total = 0;
++      else
++	*total = COSTS_NARROW_INSNS (1);
++      return false;
++
++    case ABS:
++      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
++	  && (mode == SFmode || !TARGET_VFP_SINGLE))
++	*total = COSTS_WIDE_INSNS (1);
++      else
++	*total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)) * 2;
++      return false;
++
++    case SIGN_EXTEND:
++      if (GET_MODE_SIZE (mode) <= 4)
++	*total = GET_CODE (XEXP (x, 0)) == MEM ? 0 : COSTS_NARROW_INSNS (1);
++      else
++	*total = COSTS_NARROW_INSNS (1)
++		 + COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
++      return false;
++
++    case ZERO_EXTEND:
++      if (GET_MODE_SIZE (mode) > 4)
++	*total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode) - 1);
++      else if (GET_CODE (XEXP (x, 0)) == MEM)
++	*total = 0;
++      else
++	*total = COSTS_NARROW_INSNS (1);
++      return false;
++
++    case CONST_INT:
++      {
++	HOST_WIDE_INT cst = INTVAL (x);
++
++	switch (outer_code)
++	  {
++	  case PLUS:
++	    if (cst > -256 && cst < 256)
++	      *total = 0;
++	    else
++	      /* See note about optabs below.  */
++	      *total = COSTS_N_INSNS (1);
++	    return true;
++
++	  case MINUS:
++	  case COMPARE:
++	    if (cst >= 0 && cst < 256)
++	      *total = 0;
++	    else
++	      /* See note about optabs below.  */
++	      *total = COSTS_N_INSNS (1);
++	    return true;
++
++	  case ASHIFT:
++	  case ASHIFTRT:
++	  case LSHIFTRT:
++	    *total = 0;
++	    return true;
++
++	  default:
++	    /* Constants are compared explicitly against COSTS_N_INSNS (1) in
++	       optabs.c, creating an alternative, larger code sequence for more
++	       expensive constants).  So, it doesn't pay to make some constants
++	       cost more than this.  */
++	    *total = COSTS_N_INSNS (1);
++	  }
++	return true;
++      }
++
++    case CONST:
++    case LABEL_REF:
++    case SYMBOL_REF:
++      *total = COSTS_WIDE_INSNS (2);
++      return true;
++
++    case CONST_DOUBLE:
++      *total = COSTS_WIDE_INSNS (4);
++      return true;
++
++    case HIGH:
++    case LO_SUM:
++      /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
++       cost of these slightly.  */
++      *total = COSTS_WIDE_INSNS (1) + 1;
++      return true;
++
++    default:
++      if (mode != VOIDmode)
++	*total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
++      else
++	/* A guess (inherited from arm_size_rtx_costs).  */
++	*total = COSTS_WIDE_INSNS (4);
++      return false;
++    }
++
++  return true;
++#undef THUMB2_LIBCALL_COST
++#undef COSTS_WIDE_INSNS
++#undef COSTS_NARROW_INSNS
++}
++
+ /* RTX costs when optimizing for size.  */
+ static bool
+ arm_rtx_costs (rtx x, int code, int outer_code, int *total,
+ 	       bool speed)
+ {
+   if (!speed)
+-    return arm_size_rtx_costs (x, (enum rtx_code) code,
+-			       (enum rtx_code) outer_code, total);
++    {
++      if (TARGET_THUMB2)
++	return thumb2_size_rtx_costs (x, (enum rtx_code) code,
++				      (enum rtx_code) outer_code, total);
++      else
++	return arm_size_rtx_costs (x, (enum rtx_code) code,
++				   (enum rtx_code) outer_code, total);
++    }
+   else
+     return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code,
+ 					       (enum rtx_code) outer_code,
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch
new file mode 100644
index 0000000000..3f66f9d157
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch
@@ -0,0 +1,184 @@
+	Jie Zhang  <jie@codesourcery.com>
+
+	Issue #7122
+
+	gcc/
+	* config/arm/vfp.md (movdf_vfp): Add load double 0.0 case.
+	(thumb2_movdf_vfp): Likewise. Require that one of the operands be a
+	register.
+	* config/arm/constraints.md (D0): New constraint.
+	
+	gcc/testsuite/
+	* gcc.target/arm/neon-load-df0.c: New test.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2010-02-23  Julian Brown  <julian@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/constraints.md'
+--- old/gcc/config/arm/constraints.md	2010-08-12 16:47:21 +0000
++++ new/gcc/config/arm/constraints.md	2010-08-13 10:59:06 +0000
+@@ -29,7 +29,7 @@
+ ;; in Thumb-1 state: I, J, K, L, M, N, O
+ 
+ ;; The following multi-letter normal constraints have been used:
+-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
++;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy
+ ;; in Thumb-1 state: Pa, Pb
+ ;; in Thumb-2 state: Ps, Pt, Pv
+ 
+@@ -173,6 +173,13 @@
+  (and (match_code "const_double")
+       (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
+ 
++(define_constraint "D0"
++ "@internal
++  In ARM/Thumb-2 state a 0.0 floating point constant which can
++  be loaded with a Neon vmov immediate instruction."
++ (and (match_code "const_double")
++      (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
++
+ (define_constraint "Da"
+  "@internal
+   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2010-08-12 11:29:02 +0000
++++ new/gcc/config/arm/vfp.md	2010-08-13 10:59:06 +0000
+@@ -402,8 +402,8 @@
+ ;; DFmode moves
+ 
+ (define_insn "*movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,mF,r,UvF,w, w,r"))]
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w, r, m,w  ,Uv,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))]
+   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
+    && (   register_operand (operands[0], DFmode)
+        || register_operand (operands[1], DFmode))"
+@@ -418,16 +418,18 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+         return \"fconstd%?\\t%P0, #%G1\";
+-      case 3: case 4:
++      case 3:
++	return \"vmov.i32\\t%P0, #0\";
++      case 4: case 5:
+ 	return output_move_double (operands);
+-      case 5: case 6:
++      case 6: case 7:
+ 	return output_move_vfp (operands);
+-      case 7:
++      case 8:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
+ 	else
+ 	  return \"fcpyd%?\\t%P0, %P1\";
+-      case 8:
++      case 9:
+         return \"#\";
+       default:
+ 	gcc_unreachable ();
+@@ -435,10 +437,10 @@
+     }
+   "
+   [(set_attr "type"
+-     "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
+-   (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
+-   (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
+-			       (eq_attr "alternative" "7")
++     "r_2_f,f_2_r,fconstd,*,f_loadd,f_stored,load2,store2,ffarithd,*")
++   (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*")
++   (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8)
++			       (eq_attr "alternative" "8")
+ 				(if_then_else
+ 				 (eq (symbol_ref "TARGET_VFP_SINGLE")
+ 				     (const_int 1))
+@@ -446,14 +448,16 @@
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+    (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
++   (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,1008,*,1008,*,*,*")]
+ )
+ 
+ (define_insn "*thumb2_movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,mF,r,UvF,w, w,r"))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,r, m,w  ,Uv,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))]
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
++   && (   register_operand (operands[0], DFmode)
++       || register_operand (operands[1], DFmode))"
+   "*
+   {
+     switch (which_alternative)
+@@ -465,11 +469,13 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+ 	return \"fconstd%?\\t%P0, #%G1\";
+-      case 3: case 4: case 8:
++      case 3:
++	return \"vmov.i32\\t%P0, #0\";
++      case 4: case 5: case 9:
+ 	return output_move_double (operands);
+-      case 5: case 6:
++      case 6: case 7:
+ 	return output_move_vfp (operands);
+-      case 7:
++      case 8:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
+ 	else
+@@ -480,18 +486,18 @@
+     }
+   "
+   [(set_attr "type"
+-     "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
+-   (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
+-   (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
+-			       (eq_attr "alternative" "7")
++     "r_2_f,f_2_r,fconstd,*,load2,store2,f_load,f_store,ffarithd,*")
++   (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*")
++   (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8)
++			       (eq_attr "alternative" "8")
+ 				(if_then_else
+ 				 (eq (symbol_ref "TARGET_VFP_SINGLE")
+ 				     (const_int 1))
+ 				 (const_int 8)
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+-   (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
++   (set_attr "pool_range" "*,*,*,*,4096,*,1020,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,0,*,1008,*,*,*")]
+ )
+ 
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-load-df0.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-load-df0.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-load-df0.c	2010-08-13 10:59:06 +0000
+@@ -0,0 +1,14 @@
++/* Test the optimization of loading 0.0 for ARM Neon.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++double x;
++void bar ()
++{
++  x = 0.0;
++}
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[dD\]\[0-9\]+, #0\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch
new file mode 100644
index 0000000000..aa3b3eb85f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch
@@ -0,0 +1,548 @@
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+        Merge from Sourcery G++ 4.4:
+
+        Jie Zhang  <jie@codesourcery.com>
+        Issue #7122
+
+        gcc/
+	* config/arm/arm.c (arm_rtx_costs_1): Adjust cost for
+	CONST_VECTOR.
+	(arm_size_rtx_costs): Likewise.
+	(thumb2_size_rtx_costs): Likewise.
+	(neon_valid_immediate): Add a case for double 0.0.
+
+	gcc/testsuite/
+	* gcc.target/arm/neon-vdup-1.c: New test case.
+	* gcc.target/arm/neon-vdup-2.c: New test case.
+	* gcc.target/arm/neon-vdup-3.c: New test case.
+	* gcc.target/arm/neon-vdup-4.c: New test case.
+	* gcc.target/arm/neon-vdup-5.c: New test case.
+	* gcc.target/arm/neon-vdup-6.c: New test case.
+	* gcc.target/arm/neon-vdup-7.c: New test case.
+	* gcc.target/arm/neon-vdup-8.c: New test case.
+	* gcc.target/arm/neon-vdup-9.c: New test case.
+	* gcc.target/arm/neon-vdup-10.c: New test case.
+	* gcc.target/arm/neon-vdup-11.c: New test case.
+	* gcc.target/arm/neon-vdup-12.c: New test case.
+	* gcc.target/arm/neon-vdup-13.c: New test case.
+	* gcc.target/arm/neon-vdup-14.c: New test case.
+	* gcc.target/arm/neon-vdup-15.c: New test case.
+	* gcc.target/arm/neon-vdup-16.c: New test case.
+	* gcc.target/arm/neon-vdup-17.c: New test case.
+	* gcc.target/arm/neon-vdup-18.c: New test case.
+	* gcc.target/arm/neon-vdup-19.c: New test case.
+
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-13 10:55:28 +0000
++++ new/gcc/config/arm/arm.c	2010-08-13 11:02:47 +0000
+@@ -7061,6 +7061,17 @@
+ 	*total = COSTS_N_INSNS (4);
+       return true;
+ 
++    case CONST_VECTOR:
++      if (TARGET_NEON
++	  && TARGET_HARD_FLOAT
++	  && outer == SET
++	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
++	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
++	*total = COSTS_N_INSNS (1);
++      else
++	*total = COSTS_N_INSNS (4);
++      return true;
++
+     default:
+       *total = COSTS_N_INSNS (4);
+       return false;
+@@ -7301,6 +7312,17 @@
+       *total = COSTS_N_INSNS (4);
+       return true;
+ 
++    case CONST_VECTOR:
++      if (TARGET_NEON
++	  && TARGET_HARD_FLOAT
++	  && outer_code == SET
++	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
++	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
++	*total = COSTS_N_INSNS (1);
++      else
++	*total = COSTS_N_INSNS (4);
++      return true;
++
+     case HIGH:
+     case LO_SUM:
+       /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
+@@ -7647,6 +7669,17 @@
+       *total = COSTS_WIDE_INSNS (4);
+       return true;
+ 
++    case CONST_VECTOR:
++      if (TARGET_NEON
++	  && TARGET_HARD_FLOAT
++	  && outer_code == SET
++	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
++	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
++	*total = COSTS_WIDE_INSNS (1);
++      else
++	*total = COSTS_WIDE_INSNS (4);
++      return true;
++
+     case HIGH:
+     case LO_SUM:
+       /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
+@@ -8315,11 +8348,14 @@
+    vmov  i64    17    aaaaaaaa bbbbbbbb cccccccc dddddddd
+                       eeeeeeee ffffffff gggggggg hhhhhhhh
+    vmov  f32    18    aBbbbbbc defgh000 00000000 00000000
++   vmov  f32    19    00000000 00000000 00000000 00000000
+ 
+    For case 18, B = !b. Representable values are exactly those accepted by
+    vfp3_const_double_index, but are output as floating-point numbers rather
+    than indices.
+ 
++   For case 19, we will change it to vmov.i32 when assembling.
++
+    Variants 0-5 (inclusive) may also be used as immediates for the second
+    operand of VORR/VBIC instructions.
+ 
+@@ -8362,7 +8398,7 @@
+       rtx el0 = CONST_VECTOR_ELT (op, 0);
+       REAL_VALUE_TYPE r0;
+ 
+-      if (!vfp3_const_double_rtx (el0))
++      if (!vfp3_const_double_rtx (el0) && el0 != CONST0_RTX (GET_MODE (el0)))
+         return -1;
+ 
+       REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
+@@ -8384,7 +8420,10 @@
+       if (elementwidth)
+         *elementwidth = 0;
+ 
+-      return 18;
++      if (el0 == CONST0_RTX (GET_MODE (el0)))
++	return 19;
++      else
++	return 18;
+     }
+ 
+   /* Splat vector constant out into a byte vector.  */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-1.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++float32x4_t out_float32x4_t;
++void test_vdupq_nf32 (void)
++{
++  out_float32x4_t = vdupq_n_f32 (0.0);
++}
++
++/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-10.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-10.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-10.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (~0x12000000);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-11.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-11.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-11.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t out_uint16x8_t;
++void test_vdupq_nu16 (void)
++{
++  out_uint16x8_t = vdupq_n_u16 (0x12);
++}
++
++/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-12.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-12.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-12.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t out_uint16x8_t;
++void test_vdupq_nu16 (void)
++{
++  out_uint16x8_t = vdupq_n_u16 (0x1200);
++}
++
++/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-13.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-13.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-13.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t out_uint16x8_t;
++void test_vdupq_nu16 (void)
++{
++  out_uint16x8_t = vdupq_n_u16 (~0x12);
++}
++
++/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-14.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-14.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-14.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t out_uint16x8_t;
++void test_vdupq_nu16 (void)
++{
++  out_uint16x8_t = vdupq_n_u16 (~0x1200);
++}
++
++/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-15.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-15.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-15.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint8x16_t out_uint8x16_t;
++void test_vdupq_nu8 (void)
++{
++  out_uint8x16_t = vdupq_n_u8 (0x12);
++}
++
++/* { dg-final { scan-assembler "vmov\.i8\[ 	\]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-16.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-16.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (0x12ff);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-17.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-17.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-17.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (0x12ffff);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-18.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-18.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-18.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (~0x12ff);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-19.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-19.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-19.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (~0x12ffff);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-2.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-2.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++float32x4_t out_float32x4_t;
++void test_vdupq_nf32 (void)
++{
++  out_float32x4_t = vdupq_n_f32 (0.125);
++}
++
++/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-3.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-3.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (0x12);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-4.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-4.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (0x1200);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-5.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-5.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-5.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (0x120000);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-6.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-6.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-6.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (0x12000000);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-7.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-7.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-7.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (~0x12);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-8.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-8.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (~0x1200);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-9.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vdup-9.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vdup-9.c	2010-08-13 11:02:47 +0000
+@@ -0,0 +1,17 @@
++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint32x4_t out_uint32x4_t;
++void test_vdupq_nu32 (void)
++{
++  out_uint32x4_t = vdupq_n_u32 (~0x120000);
++}
++
++/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch
new file mode 100644
index 0000000000..8d48ada2fd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch
@@ -0,0 +1,118 @@
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+        Merge from Sourcery G++ 4.4:
+
+	2010-04-07  Thomas Schwinge  <thomas@codesourcery.com>
+		    Daniel Jacobowitz  <dan@codesourcery.com>
+
+	Issue #6715
+
+	PR debug/40521
+
+	gcc/
+	* dwarf2out.c (NEED_UNWIND_TABLES): Define.
+	(dwarf2out_do_frame, dwarf2out_do_cfi_asm, dwarf2out_begin_prologue)
+	(dwarf2out_frame_finish, dwarf2out_assembly_start): Use it.
+	(dwarf2out_assembly_start): Correct logic for TARGET_UNWIND_INFO.
+	* config/arm/arm.h (DWARF2_UNWIND_INFO): Remove definition.
+	* config/arm/bpabi.h (DWARF2_UNWIND_INFO): Define to zero.
+
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-08-13 10:30:35 +0000
++++ new/gcc/config/arm/arm.h	2010-08-13 11:11:15 +0000
+@@ -932,9 +932,6 @@
+ #define MUST_USE_SJLJ_EXCEPTIONS 1
+ #endif
+ 
+-/* We can generate DWARF2 Unwind info, even though we don't use it.  */
+-#define DWARF2_UNWIND_INFO 1
+-
+ /* Use r0 and r1 to pass exception handling information.  */
+ #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
+ 
+
+=== modified file 'gcc/config/arm/bpabi.h'
+--- old/gcc/config/arm/bpabi.h	2009-11-20 17:37:30 +0000
++++ new/gcc/config/arm/bpabi.h	2010-08-13 11:11:15 +0000
+@@ -26,6 +26,7 @@
+ #define TARGET_BPABI (TARGET_AAPCS_BASED)
+ 
+ /* BPABI targets use EABI frame unwinding tables.  */
++#define DWARF2_UNWIND_INFO 0
+ #define TARGET_UNWIND_INFO 1
+ 
+ /* Section 4.1 of the AAPCS requires the use of VFP format.  */
+
+=== modified file 'gcc/dwarf2out.c'
+--- old/gcc/dwarf2out.c	2010-07-01 11:31:19 +0000
++++ new/gcc/dwarf2out.c	2010-08-13 11:11:15 +0000
+@@ -124,6 +124,9 @@
+ # endif
+ #endif
+ 
++#define NEED_UNWIND_TABLES \
++  (flag_unwind_tables || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))
++
+ /* Map register numbers held in the call frame info that gcc has
+    collected using DWARF_FRAME_REGNUM to those that should be output in
+    .debug_frame and .eh_frame.  */
+@@ -147,9 +150,7 @@
+ 	  || write_symbols == VMS_AND_DWARF2_DEBUG
+ 	  || DWARF2_FRAME_INFO || saved_do_cfi_asm
+ #ifdef DWARF2_UNWIND_INFO
+-	  || (DWARF2_UNWIND_INFO
+-	      && (flag_unwind_tables
+-		  || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS)))
++	  || (DWARF2_UNWIND_INFO && NEED_UNWIND_TABLES)
+ #endif
+ 	  );
+ }
+@@ -185,7 +186,7 @@
+ #ifdef TARGET_UNWIND_INFO
+       return false;
+ #else
+-      if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions))
++      if (!NEED_UNWIND_TABLES)
+ 	return false;
+ #endif
+     }
+@@ -3906,8 +3907,7 @@
+   /* ??? current_function_func_begin_label is also used by except.c
+      for call-site information.  We must emit this label if it might
+      be used.  */
+-  if ((! flag_exceptions || USING_SJLJ_EXCEPTIONS)
+-      && ! dwarf2out_do_frame ())
++  if (! NEED_UNWIND_TABLES && ! dwarf2out_do_frame ())
+     return;
+ #else
+   if (! dwarf2out_do_frame ())
+@@ -4067,7 +4067,7 @@
+ 
+ #ifndef TARGET_UNWIND_INFO
+   /* Output another copy for the unwinder.  */
+-  if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions))
++  if (NEED_UNWIND_TABLES)
+     output_call_frame_info (1);
+ #endif
+ }
+@@ -20732,10 +20732,15 @@
+ {
+   if (HAVE_GAS_CFI_SECTIONS_DIRECTIVE && dwarf2out_do_cfi_asm ())
+     {
+-#ifndef TARGET_UNWIND_INFO
+-      if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions))
+-#endif
++#ifdef TARGET_UNWIND_INFO
++      /* We're only ever interested in .debug_frame.  */
++      fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n");
++#else
++      /* GAS defaults to emitting .eh_frame only, and .debug_frame is not
++	 wanted in case that the former one is present.  */
++      if (! NEED_UNWIND_TABLES)
+ 	fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n");
++#endif
+     }
+ }
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch
new file mode 100644
index 0000000000..239251d2b5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch
@@ -0,0 +1,298 @@
+	2010-04-08  Bernd Schmidt  <bernds@codesourcery.com>
+
+	Issue #6952
+
+	gcc/
+	* ira-costs.c (record_reg_classes): Ignore alternatives that are 
+	not enabled. 
+	* config/arm/vfp.md (arm_movdi_vfp): Enable only when not tuning
+	for Cortex-A8.
+	(arm_movdi_vfp_cortexa8): New pattern.
+	* config/arm/neon.md (adddi3_neon, subdi3_neon, anddi3_neon,
+	iordi3_neon, xordi3_neon): Add alternatives to discourage Neon
+	instructions when tuning for Cortex-A8.  Set attribute "alt_tune".
+	* config/arm/arm.md (define_attr "alt_tune", define_attr "enabled"):
+	New.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2010-04-07  Thomas Schwinge  <thomas@codesourcery.com>
+ 		    Daniel Jacobowitz  <dan@codesourcery.com>
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-13 10:30:35 +0000
++++ new/gcc/config/arm/arm.md	2010-08-13 11:40:17 +0000
+@@ -432,6 +432,20 @@
+ 	  (const_string "yes")
+ 	  (const_string "no"))))
+ 
++; Specifies which machine an alternative is tuned for.  Used to compute
++; attribute ENABLED.
++(define_attr "alt_tune" "all,onlya8,nota8" (const_string "all"))
++
++(define_attr "enabled" ""
++  (cond [(and (eq_attr "alt_tune" "onlya8")
++	      (not (eq_attr "tune" "cortexa8")))
++	 (const_int 0)
++
++	 (and (eq_attr "alt_tune" "nota8")
++	      (eq_attr "tune" "cortexa8"))
++	 (const_int 0)]
++	(const_int 1)))
++
+ (include "arm-generic.md")
+ (include "arm926ejs.md")
+ (include "arm1020e.md")
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2010-08-10 13:31:21 +0000
++++ new/gcc/config/arm/neon.md	2010-08-13 11:40:17 +0000
+@@ -827,23 +827,25 @@
+ )
+ 
+ (define_insn "adddi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
+-        (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0")
+-                 (match_operand:DI 2 "s_register_operand" "w,r,0")))
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r")
++        (plus:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0")
++                 (match_operand:DI 2 "s_register_operand" "w,w,r,0")))
+    (clobber (reg:CC CC_REGNUM))]
+   "TARGET_NEON"
+ {
+   switch (which_alternative)
+     {
+-    case 0: return "vadd.i64\t%P0, %P1, %P2";
+-    case 1: return "#";
++    case 0: /* fall through */
++    case 1: return "vadd.i64\t%P0, %P1, %P2";
+     case 2: return "#";
++    case 3: return "#";
+     default: gcc_unreachable ();
+     }
+ }
+-  [(set_attr "neon_type" "neon_int_1,*,*")
+-   (set_attr "conds" "*,clob,clob")
+-   (set_attr "length" "*,8,8")]
++  [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
++   (set_attr "conds" "*,*,clob,clob")
++   (set_attr "length" "*,*,8,8")
++   (set_attr "alt_tune" "nota8,onlya8,*,*")]
+ )
+ 
+ (define_insn "*sub<mode>3_neon"
+@@ -861,24 +863,26 @@
+ )
+ 
+ (define_insn "subdi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
+-        (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0")
+-                  (match_operand:DI 2 "s_register_operand" "w,r,0,0")))
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r,?&r")
++        (minus:DI (match_operand:DI 1 "s_register_operand" "w,w,0,r,0")
++                  (match_operand:DI 2 "s_register_operand" "w,w,r,0,0")))
+    (clobber (reg:CC CC_REGNUM))]
+   "TARGET_NEON"
+ {
+   switch (which_alternative)
+     {
+-    case 0: return "vsub.i64\t%P0, %P1, %P2";
+-    case 1: /* fall through */ 
+-    case 2: /* fall through */
+-    case 3: return  "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
++    case 0: /* fall through */
++    case 1: return "vsub.i64\t%P0, %P1, %P2";
++    case 2: /* fall through */ 
++    case 3: /* fall through */
++    case 4: return  "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
+     default: gcc_unreachable ();
+     }
+ }
+-  [(set_attr "neon_type" "neon_int_2,*,*,*")
+-   (set_attr "conds" "*,clob,clob,clob")
+-   (set_attr "length" "*,8,8,8")]
++  [(set_attr "neon_type" "neon_int_2,neon_int_2,*,*,*")
++   (set_attr "conds" "*,*,clob,clob,clob")
++   (set_attr "length" "*,*,8,8,8")
++   (set_attr "alt_tune" "nota8,onlya8,*,*,*")]
+ )
+ 
+ (define_insn "*mul<mode>3_neon"
+@@ -964,23 +968,26 @@
+ )
+ 
+ (define_insn "iordi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
+-        (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
+-		(match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r")
++        (ior:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r")
++		(match_operand:DI 2 "neon_logic_op2" "w,w,Dl,Dl,r,r")))]
+   "TARGET_NEON"
+ {
+   switch (which_alternative)
+     {
+-    case 0: return "vorr\t%P0, %P1, %P2";
+-    case 1: return neon_output_logic_immediate ("vorr", &operands[2],
++    case 0: /* fall through */
++    case 1: return "vorr\t%P0, %P1, %P2";
++    case 2: /* fall through */
++    case 3: return neon_output_logic_immediate ("vorr", &operands[2],
+ 		     DImode, 0, VALID_NEON_QREG_MODE (DImode));
+-    case 2: return "#";
+-    case 3: return "#";
++    case 4: return "#";
++    case 5: return "#";
+     default: gcc_unreachable ();
+     }
+ }
+-  [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
+-   (set_attr "length" "*,*,8,8")]
++  [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*")
++   (set_attr "length" "*,*,*,*,8,8")
++   (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")]
+ )
+ 
+ ;; The concrete forms of the Neon immediate-logic instructions are vbic and
+@@ -1006,23 +1013,26 @@
+ )
+ 
+ (define_insn "anddi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
+-        (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
+-		(match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r")
++        (and:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r")
++		(match_operand:DI 2 "neon_inv_logic_op2" "w,w,DL,DL,r,r")))]
+   "TARGET_NEON"
+ {
+   switch (which_alternative)
+     {
+-    case 0: return "vand\t%P0, %P1, %P2";
+-    case 1: return neon_output_logic_immediate ("vand", &operands[2],
++    case 0: /* fall through */
++    case 1: return "vand\t%P0, %P1, %P2";
++    case 2: /* fall through */
++    case 3: return neon_output_logic_immediate ("vand", &operands[2],
+     		     DImode, 1, VALID_NEON_QREG_MODE (DImode));
+-    case 2: return "#";
+-    case 3: return "#";
++    case 4: return "#";
++    case 5: return "#";
+     default: gcc_unreachable ();
+     }
+ }
+-  [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
+-   (set_attr "length" "*,*,8,8")]
++  [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*")
++   (set_attr "length" "*,*,*,*,8,8")
++   (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")]
+ )
+ 
+ (define_insn "orn<mode>3_neon"
+@@ -1080,16 +1090,18 @@
+ )
+ 
+ (define_insn "xordi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
+-        (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r")
+-	        (match_operand:DI 2 "s_register_operand" "w,r,r")))]
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r")
++        (xor:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,r")
++	        (match_operand:DI 2 "s_register_operand" "w,w,r,r")))]
+   "TARGET_NEON"
+   "@
+    veor\t%P0, %P1, %P2
++   veor\t%P0, %P1, %P2
+    #
+    #"
+-  [(set_attr "neon_type" "neon_int_1,*,*")
+-   (set_attr "length" "*,8,8")]
++  [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
++   (set_attr "length" "*,*,8,8")
++   (set_attr "alt_tune" "nota8,onlya8,*,*")]
+ )
+ 
+ (define_insn "one_cmpl<mode>2"
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2010-08-13 10:59:06 +0000
++++ new/gcc/config/arm/vfp.md	2010-08-13 11:40:17 +0000
+@@ -133,9 +133,51 @@
+ ;; DImode moves
+ 
+ (define_insn "*arm_movdi_vfp"
+-  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
+-	(match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
++  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,w,r,w,w, Uv")
++	(match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
++   && (   register_operand (operands[0], DImode)
++       || register_operand (operands[1], DImode))"
++  "*
++  switch (which_alternative)
++    {
++    case 0: 
++      return \"#\";
++    case 1:
++    case 2:
++      return output_move_double (operands);
++    case 3:
++      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
++    case 4:
++      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
++    case 5:
++      if (TARGET_VFP_SINGLE)
++	return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
++      else
++	return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
++    case 6: case 7:
++      return output_move_vfp (operands);
++    default:
++      gcc_unreachable ();
++    }
++  "
++  [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
++   (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
++   (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
++			       (eq_attr "alternative" "5")
++				(if_then_else
++				 (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
++				 (const_int 8)
++				 (const_int 4))]
++			      (const_int 4)))
++   (set_attr "pool_range"     "*,1020,*,*,*,*,1020,*")
++   (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
++)
++
++(define_insn "*arm_movdi_vfp_cortexa8"
++  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,!r,w,w, Uv")
++	(match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))"
+   "*
+
+=== modified file 'gcc/ira-costs.c'
+--- old/gcc/ira-costs.c	2009-11-25 10:55:54 +0000
++++ new/gcc/ira-costs.c	2010-08-13 11:40:17 +0000
+@@ -224,6 +224,14 @@
+       int alt_fail = 0;
+       int alt_cost = 0, op_cost_add;
+ 
++      if (!recog_data.alternative_enabled_p[alt])
++	{
++	  for (i = 0; i < recog_data.n_operands; i++)
++	    constraints[i] = skip_alternative (constraints[i]);
++
++	  continue;
++	}
++
+       for (i = 0; i < n_ops; i++)
+ 	{
+ 	  unsigned char c;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch
new file mode 100644
index 0000000000..743e2751c7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch
@@ -0,0 +1,384 @@
+	Richard Earnshaw  <rearnsha@arm.com>
+
+	gcc/
+	* doc/tm.texi (OVERLAPPING_REGISTER_NAMES): Document new macro.
+	* output.h (decode_reg_name_and_count): Declare.
+	* varasm.c (decode_reg_name_and_count): New function.
+	(decode_reg_name): Reimplement using decode_reg_name_and_count.
+	* reginfo.c (fix_register): Use decode_reg_name_and_count and 
+	iterate over all regs used.
+	* stmt.c (expand_asm_operands): Likewise.
+	* config/arm/aout.h (OVERLAPPING_REGISTER_NAMES): Define.
+	(ADDITIONAL_REGISTER_NAMES): Remove aliases that overlap
+	multiple machine registers.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	2010-04-08  Bernd Schmidt  <bernds@codesourcery.com>
+ 
+ 	Issue #6952
+
+=== modified file 'gcc/config/arm/aout.h'
+--- old/gcc/config/arm/aout.h	2009-06-21 19:48:15 +0000
++++ new/gcc/config/arm/aout.h	2010-08-13 11:53:46 +0000
+@@ -163,31 +163,45 @@
+   {"mvdx12", 39},				\
+   {"mvdx13", 40},				\
+   {"mvdx14", 41},				\
+-  {"mvdx15", 42},				\
+-  {"d0", 63}, {"q0", 63},			\
+-  {"d1", 65},					\
+-  {"d2", 67}, {"q1", 67},			\
+-  {"d3", 69},					\
+-  {"d4", 71}, {"q2", 71},			\
+-  {"d5", 73},					\
+-  {"d6", 75}, {"q3", 75},			\
+-  {"d7", 77},					\
+-  {"d8", 79}, {"q4", 79},			\
+-  {"d9", 81},					\
+-  {"d10", 83}, {"q5", 83},			\
+-  {"d11", 85},					\
+-  {"d12", 87}, {"q6", 87},			\
+-  {"d13", 89},					\
+-  {"d14", 91}, {"q7", 91},			\
+-  {"d15", 93},					\
+-  {"q8", 95},					\
+-  {"q9", 99},					\
+-  {"q10", 103},					\
+-  {"q11", 107},					\
+-  {"q12", 111},					\
+-  {"q13", 115},					\
+-  {"q14", 119},					\
+-  {"q15", 123}					\
++  {"mvdx15", 42}				\
++}
++#endif
++
++#ifndef OVERLAPPING_REGISTER_NAMES
++#define OVERLAPPING_REGISTER_NAMES		\
++{						\
++  {"d0", 63, 2},				\
++  {"d1", 65, 2},				\
++  {"d2", 67, 2},				\
++  {"d3", 69, 2},				\
++  {"d4", 71, 2},				\
++  {"d5", 73, 2},				\
++  {"d6", 75, 2},				\
++  {"d7", 77, 2},				\
++  {"d8", 79, 2},				\
++  {"d9", 81, 2},				\
++  {"d10", 83, 2},				\
++  {"d11", 85, 2},				\
++  {"d12", 87, 2},				\
++  {"d13", 89, 2},				\
++  {"d14", 91, 2},				\
++  {"d15", 93, 2},				\
++  {"q0", 63, 4},				\
++  {"q1", 67, 4},				\
++  {"q2", 71, 4},				\
++  {"q3", 75, 4},				\
++  {"q4", 79, 4},				\
++  {"q5", 83, 4},				\
++  {"q6", 87, 4},				\
++  {"q7", 91, 4},				\
++  {"q8", 95, 4},				\
++  {"q9", 99, 4},				\
++  {"q10", 103, 4},				\
++  {"q11", 107, 4},				\
++  {"q12", 111, 4},				\
++  {"q13", 115, 4},				\
++  {"q14", 119, 4},				\
++  {"q15", 123, 4}				\
+ }
+ #endif
+ 
+
+=== modified file 'gcc/doc/tm.texi'
+--- old/gcc/doc/tm.texi	2010-06-24 20:06:37 +0000
++++ new/gcc/doc/tm.texi	2010-08-13 11:53:46 +0000
+@@ -8339,6 +8339,22 @@
+ to registers using alternate names.
+ @end defmac
+ 
++@defmac OVERLAPPING_REGISTER_NAMES
++If defined, a C initializer for an array of structures containing a
++name, a register number and a count of the number of consecutive
++machine registers the name overlaps.  This macro defines additional
++names for hard registers, thus allowing the @code{asm} option in
++declarations to refer to registers using alternate names.  Unlike
++@code{ADDITIONAL_REGISTER_NAMES}, this macro should be used when the
++register name implies multiple underlying registers.
++
++This macro should be used when it is important that a clobber in an
++@code{asm} statement clobbers all the underlying values implied by the
++register name.  For example, on ARM, clobbering the double-precision
++VFP register ``d0'' implies clobbering both single-precision registers
++``s0'' and ``s1''.
++@end defmac
++
+ @defmac ASM_OUTPUT_OPCODE (@var{stream}, @var{ptr})
+ Define this macro if you are using an unusual assembler that
+ requires different names for the machine instructions.
+
+=== modified file 'gcc/output.h'
+--- old/gcc/output.h	2009-10-26 21:57:10 +0000
++++ new/gcc/output.h	2010-08-13 11:53:46 +0000
+@@ -173,6 +173,11 @@
+    Prefixes such as % are optional.  */
+ extern int decode_reg_name (const char *);
+ 
++/* Similar to decode_reg_name, but takes an extra parameter that is a
++   pointer to the number of (internal) registers described by the
++   external name.  */
++extern int decode_reg_name_and_count (const char *, int *);
++
+ extern void assemble_alias (tree, tree);
+ 
+ extern void default_assemble_visibility (tree, int);
+
+=== modified file 'gcc/reginfo.c'
+--- old/gcc/reginfo.c	2010-04-19 09:04:43 +0000
++++ new/gcc/reginfo.c	2010-08-13 11:53:46 +0000
+@@ -799,36 +799,41 @@
+ fix_register (const char *name, int fixed, int call_used)
+ {
+   int i;
++  int reg, nregs;
+ 
+   /* Decode the name and update the primary form of
+      the register info.  */
+ 
+-  if ((i = decode_reg_name (name)) >= 0)
++  if ((reg = decode_reg_name_and_count (name, &nregs)) >= 0)
+     {
+-      if ((i == STACK_POINTER_REGNUM
++      gcc_assert (nregs >= 1);
++      for (i = reg; i < reg + nregs; i++)
++	{
++	  if ((i == STACK_POINTER_REGNUM
+ #ifdef HARD_FRAME_POINTER_REGNUM
+-	   || i == HARD_FRAME_POINTER_REGNUM
++	       || i == HARD_FRAME_POINTER_REGNUM
+ #else
+-	   || i == FRAME_POINTER_REGNUM
++	       || i == FRAME_POINTER_REGNUM
+ #endif
+-	   )
+-	  && (fixed == 0 || call_used == 0))
+-	{
+-	  static const char * const what_option[2][2] = {
+-	    { "call-saved", "call-used" },
+-	    { "no-such-option", "fixed" }};
++	       )
++	      && (fixed == 0 || call_used == 0))
++	    {
++	      static const char * const what_option[2][2] = {
++		{ "call-saved", "call-used" },
++		{ "no-such-option", "fixed" }};
+ 
+-	  error ("can't use '%s' as a %s register", name,
+-		 what_option[fixed][call_used]);
+-	}
+-      else
+-	{
+-	  fixed_regs[i] = fixed;
+-	  call_used_regs[i] = call_used;
++	      error ("can't use '%s' as a %s register", name,
++		     what_option[fixed][call_used]);
++	    }
++	  else
++	    {
++	      fixed_regs[i] = fixed;
++	      call_used_regs[i] = call_used;
+ #ifdef CALL_REALLY_USED_REGISTERS
+-	  if (fixed == 0)
+-	    call_really_used_regs[i] = call_used;
++	      if (fixed == 0)
++		call_really_used_regs[i] = call_used;
+ #endif
++	    }
+ 	}
+     }
+   else
+
+=== modified file 'gcc/stmt.c'
+--- old/gcc/stmt.c	2010-02-19 09:53:51 +0000
++++ new/gcc/stmt.c	2010-08-13 11:53:46 +0000
+@@ -684,13 +684,14 @@
+   for (tail = clobbers; tail; tail = TREE_CHAIN (tail))
+     {
+       const char *regname;
++      int nregs;
+ 
+       if (TREE_VALUE (tail) == error_mark_node)
+ 	return;
+       regname = TREE_STRING_POINTER (TREE_VALUE (tail));
+ 
+-      i = decode_reg_name (regname);
+-      if (i >= 0 || i == -4)
++      i = decode_reg_name_and_count (regname, &nregs);
++      if (i == -4)
+ 	++nclobbers;
+       else if (i == -2)
+ 	error ("unknown register name %qs in %<asm%>", regname);
+@@ -698,14 +699,21 @@
+       /* Mark clobbered registers.  */
+       if (i >= 0)
+         {
+-	  /* Clobbering the PIC register is an error.  */
+-	  if (i == (int) PIC_OFFSET_TABLE_REGNUM)
++	  int reg;
++
++	  for (reg = i; reg < i + nregs; reg++)
+ 	    {
+-	      error ("PIC register %qs clobbered in %<asm%>", regname);
+-	      return;
++	      ++nclobbers;
++
++	      /* Clobbering the PIC register is an error.  */
++	      if (reg == (int) PIC_OFFSET_TABLE_REGNUM)
++		{
++		  error ("PIC register clobbered by %qs in %<asm%>", regname);
++		  return;
++		}
++
++	      SET_HARD_REG_BIT (clobbered_regs, reg);
+ 	    }
+-
+-	  SET_HARD_REG_BIT (clobbered_regs, i);
+ 	}
+     }
+ 
+@@ -1026,7 +1034,8 @@
+       for (tail = clobbers; tail; tail = TREE_CHAIN (tail))
+ 	{
+ 	  const char *regname = TREE_STRING_POINTER (TREE_VALUE (tail));
+-	  int j = decode_reg_name (regname);
++	  int reg, nregs;
++	  int j = decode_reg_name_and_count (regname, &nregs);
+ 	  rtx clobbered_reg;
+ 
+ 	  if (j < 0)
+@@ -1048,30 +1057,39 @@
+ 	      continue;
+ 	    }
+ 
+-	  /* Use QImode since that's guaranteed to clobber just one reg.  */
+-	  clobbered_reg = gen_rtx_REG (QImode, j);
+-
+-	  /* Do sanity check for overlap between clobbers and respectively
+-	     input and outputs that hasn't been handled.  Such overlap
+-	     should have been detected and reported above.  */
+-	  if (!clobber_conflict_found)
++	  for (reg = j; reg < j + nregs; reg++)
+ 	    {
+-	      int opno;
+-
+-	      /* We test the old body (obody) contents to avoid tripping
+-		 over the under-construction body.  */
+-	      for (opno = 0; opno < noutputs; opno++)
+-		if (reg_overlap_mentioned_p (clobbered_reg, output_rtx[opno]))
+-		  internal_error ("asm clobber conflict with output operand");
+-
+-	      for (opno = 0; opno < ninputs - ninout; opno++)
+-		if (reg_overlap_mentioned_p (clobbered_reg,
+-					     ASM_OPERANDS_INPUT (obody, opno)))
+-		  internal_error ("asm clobber conflict with input operand");
++	      /* Use QImode since that's guaranteed to clobber just
++	       * one reg.  */
++	      clobbered_reg = gen_rtx_REG (QImode, reg);
++
++	      /* Do sanity check for overlap between clobbers and
++		 respectively input and outputs that hasn't been
++		 handled.  Such overlap should have been detected and
++		 reported above.  */
++	      if (!clobber_conflict_found)
++		{
++		  int opno;
++
++		  /* We test the old body (obody) contents to avoid
++		     tripping over the under-construction body.  */
++		  for (opno = 0; opno < noutputs; opno++)
++		    if (reg_overlap_mentioned_p (clobbered_reg,
++						 output_rtx[opno]))
++		      internal_error
++			("asm clobber conflict with output operand");
++
++		  for (opno = 0; opno < ninputs - ninout; opno++)
++		    if (reg_overlap_mentioned_p (clobbered_reg,
++						 ASM_OPERANDS_INPUT (obody,
++								     opno)))
++		      internal_error
++			("asm clobber conflict with input operand");
++		}
++
++	      XVECEXP (body, 0, i++)
++		= gen_rtx_CLOBBER (VOIDmode, clobbered_reg);
+ 	    }
+-
+-	  XVECEXP (body, 0, i++)
+-	    = gen_rtx_CLOBBER (VOIDmode, clobbered_reg);
+ 	}
+ 
+       if (nlabels > 0)
+
+=== modified file 'gcc/varasm.c'
+--- old/gcc/varasm.c	2010-03-27 11:56:30 +0000
++++ new/gcc/varasm.c	2010-08-13 11:53:46 +0000
+@@ -1043,8 +1043,11 @@
+    Prefixes such as % are optional.  */
+ 
+ int
+-decode_reg_name (const char *asmspec)
++decode_reg_name_and_count (const char *asmspec, int *pnregs)
+ {
++  /* Presume just one register is clobbered.  */
++  *pnregs = 1;
++
+   if (asmspec != 0)
+     {
+       int i;
+@@ -1070,6 +1073,25 @@
+ 	    && ! strcmp (asmspec, strip_reg_name (reg_names[i])))
+ 	  return i;
+ 
++#ifdef OVERLAPPING_REGISTER_NAMES
++      {
++	static const struct
++	{
++	  const char *const name;
++	  const int number;
++	  const int nregs;
++	} table[] = OVERLAPPING_REGISTER_NAMES;
++
++	for (i = 0; i < (int) ARRAY_SIZE (table); i++)
++	  if (table[i].name[0]
++	      && ! strcmp (asmspec, table[i].name))
++	    {
++	      *pnregs = table[i].nregs;
++	      return table[i].number;
++	    }
++      }
++#endif /* OVERLAPPING_REGISTER_NAMES */
++
+ #ifdef ADDITIONAL_REGISTER_NAMES
+       {
+ 	static const struct { const char *const name; const int number; } table[]
+@@ -1093,6 +1115,14 @@
+ 
+   return -1;
+ }
++
++int
++decode_reg_name (const char *name)
++{
++  int count;
++  return decode_reg_name_and_count (name, &count);
++}
++
+ 
+ /* Return true if DECL's initializer is suitable for a BSS section.  */
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch
new file mode 100644
index 0000000000..b47c2ceb4c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch
@@ -0,0 +1,181 @@
+	2010-04-12  Andrew Stubbs  <ams@codesourcery.com>
+
+	Issue #7178
+
+	gcc/
+	* config/arm/arm.c (arm_init_libfuncs): Change __gnu_f2h_ieee to
+	__aeabi_f2h, __gnu_f2h_alternative to __aeabi_f2h_alt, __gnu_h2f_ieee
+	to __aeabi_h2f, and __gnu_h2f_alternative to __aeabi_h2f_alt.
+	* config/arm/fp16.c (__gnu_f2h_internal): Change return type to
+	unsigned int. Change 'sign' variable likewise.
+	(__gnu_h2f_internal): Set to static inline.
+	Change return type to unsigned int. Change 'sign' variable likewise.
+	(ALIAS): New define.
+	(__gnu_f2h_ieee): Change unsigned short to unsigned int.
+	(__gnu_h2f_ieee): Likewise.
+	(__gnu_f2h_alternative): Likewise.
+	(__gnu_h2f_alternative): Likewise.
+	(__aeabi_f2h, __aeabi_h2f): New aliases.
+	(__aeabi_f2h_alt, __aeabi_h2f_alt): Likewise.
+	* config/arm/sfp-machine.h (__extendhfsf2): Set to __aeabi_h2f.
+	(__truncsfhf2): Set to __aeabi_f2h.
+
+	gcc/testsuite/
+	* g++.dg/ext/arm-fp16/arm-fp16-ops-5.C: Check for __aeabi_h2f
+	and __aeabi_f2h.
+	* g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Likewise.
+	* gcc.dg/torture/arm-fp16-ops-5.c: Likewise.
+	* gcc.dg/torture/arm-fp16-ops-6.c: Likewise.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+ 	Richard Earnshaw  <rearnsha@arm.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-13 11:02:47 +0000
++++ new/gcc/config/arm/arm.c	2010-08-13 14:08:20 +0000
+@@ -1054,12 +1054,12 @@
+       /* Conversions.  */
+       set_conv_libfunc (trunc_optab, HFmode, SFmode,
+ 			(arm_fp16_format == ARM_FP16_FORMAT_IEEE
+-			 ? "__gnu_f2h_ieee"
+-			 : "__gnu_f2h_alternative"));
++			 ? "__aeabi_f2h"
++			 : "__aeabi_f2h_alt"));
+       set_conv_libfunc (sext_optab, SFmode, HFmode, 
+ 			(arm_fp16_format == ARM_FP16_FORMAT_IEEE
+-			 ? "__gnu_h2f_ieee"
+-			 : "__gnu_h2f_alternative"));
++			 ? "__aeabi_h2f"
++			 : "__aeabi_h2f_alt"));
+       
+       /* Arithmetic.  */
+       set_optab_libfunc (add_optab, HFmode, NULL);
+
+=== modified file 'gcc/config/arm/fp16.c'
+--- old/gcc/config/arm/fp16.c	2009-06-18 11:26:37 +0000
++++ new/gcc/config/arm/fp16.c	2010-08-13 14:08:20 +0000
+@@ -22,10 +22,10 @@
+    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+    <http://www.gnu.org/licenses/>.  */
+ 
+-static inline unsigned short
++static inline unsigned int
+ __gnu_f2h_internal(unsigned int a, int ieee)
+ {
+-  unsigned short sign = (a >> 16) & 0x8000;
++  unsigned int sign = (a >> 16) & 0x8000;
+   int aexp = (a >> 23) & 0xff;
+   unsigned int mantissa = a & 0x007fffff;
+   unsigned int mask;
+@@ -95,10 +95,10 @@
+   return sign | (((aexp + 14) << 10) + (mantissa >> 13));
+ }
+ 
+-unsigned int
+-__gnu_h2f_internal(unsigned short a, int ieee)
++static inline unsigned int
++__gnu_h2f_internal(unsigned int a, int ieee)
+ {
+-  unsigned int sign = (unsigned int)(a & 0x8000) << 16;
++  unsigned int sign = (a & 0x00008000) << 16;
+   int aexp = (a >> 10) & 0x1f;
+   unsigned int mantissa = a & 0x3ff;
+ 
+@@ -120,26 +120,33 @@
+   return sign | (((aexp + 0x70) << 23) + (mantissa << 13));
+ }
+ 
+-unsigned short
++#define ALIAS(src, dst) \
++  typeof (src) dst __attribute__ ((alias (#src)));
++
++unsigned int
+ __gnu_f2h_ieee(unsigned int a)
+ {
+   return __gnu_f2h_internal(a, 1);
+ }
++ALIAS (__gnu_f2h_ieee, __aeabi_f2h)
+ 
+ unsigned int
+-__gnu_h2f_ieee(unsigned short a)
++__gnu_h2f_ieee(unsigned int a)
+ {
+   return __gnu_h2f_internal(a, 1);
+ }
++ALIAS (__gnu_h2f_ieee, __aeabi_h2f)
+ 
+-unsigned short
++unsigned int
+ __gnu_f2h_alternative(unsigned int x)
+ {
+   return __gnu_f2h_internal(x, 0);
+ }
++ALIAS (__gnu_f2h_alternative, __aeabi_f2h_alt)
+ 
+ unsigned int
+-__gnu_h2f_alternative(unsigned short a)
++__gnu_h2f_alternative(unsigned int a)
+ {
+   return __gnu_h2f_internal(a, 0);
+ }
++ALIAS (__gnu_h2f_alternative, __aeabi_h2f_alt)
+
+=== modified file 'gcc/config/arm/sfp-machine.h'
+--- old/gcc/config/arm/sfp-machine.h	2009-06-18 11:26:37 +0000
++++ new/gcc/config/arm/sfp-machine.h	2010-08-13 14:08:20 +0000
+@@ -99,7 +99,7 @@
+ #define __fixdfdi	__aeabi_d2lz
+ #define __fixunsdfdi	__aeabi_d2ulz
+ #define __floatdidf	__aeabi_l2d
+-#define __extendhfsf2	__gnu_h2f_ieee
+-#define __truncsfhf2	__gnu_f2h_ieee
++#define __extendhfsf2	__aeabi_h2f
++#define __truncsfhf2	__aeabi_f2h
+ 
+ #endif /* __ARM_EABI__ */
+
+=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C'
+--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C	2010-08-13 14:08:20 +0000
+@@ -13,3 +13,5 @@
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
+
+=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C'
+--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C	2010-08-13 14:08:20 +0000
+@@ -13,3 +13,5 @@
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c'
+--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c	2010-08-13 14:08:20 +0000
+@@ -13,3 +13,5 @@
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c'
+--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c	2010-08-13 14:08:20 +0000
+@@ -13,3 +13,5 @@
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
+ /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch
new file mode 100644
index 0000000000..64efbc759e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch
@@ -0,0 +1,376 @@
+	
+	2010-04-11  Julian Brown  <julian@codesourcery.com>
+
+	Issue #7326
+
+	gcc/
+	* config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
+	* config/arm/arm.md (generic_sched): No for Cortex-A5.
+	(generic_vfp): Likewise.
+	(cortex-a5.md): Include.
+	* config/arm/cortex-a5.md: New.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+ 
+ 	2010-04-12  Andrew Stubbs  <ams@codesourcery.com>
+ 
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-13 14:08:20 +0000
++++ new/gcc/config/arm/arm.c	2010-08-13 15:15:12 +0000
+@@ -22262,6 +22262,7 @@
+     {
+     case cortexr4:
+     case cortexr4f:
++    case cortexa5:
+     case cortexa8:
+     case cortexa9:
+       return 2;
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-13 11:40:17 +0000
++++ new/gcc/config/arm/arm.md	2010-08-13 15:15:12 +0000
+@@ -419,7 +419,7 @@
+ 
+ (define_attr "generic_sched" "yes,no"
+   (const (if_then_else 
+-          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
++          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
+ 	      (eq_attr "tune_cortexr4" "yes"))
+           (const_string "no")
+           (const_string "yes"))))
+@@ -427,7 +427,7 @@
+ (define_attr "generic_vfp" "yes,no"
+   (const (if_then_else
+ 	  (and (eq_attr "fpu" "vfp")
+-	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
++	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
+ 	       (eq_attr "tune_cortexr4" "no"))
+ 	  (const_string "yes")
+ 	  (const_string "no"))))
+@@ -451,6 +451,7 @@
+ (include "arm1020e.md")
+ (include "arm1026ejs.md")
+ (include "arm1136jfs.md")
++(include "cortex-a5.md")
+ (include "cortex-a8.md")
+ (include "cortex-a9.md")
+ (include "cortex-r4.md")
+
+=== added file 'gcc/config/arm/cortex-a5.md'
+--- old/gcc/config/arm/cortex-a5.md	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/cortex-a5.md	2010-08-13 15:15:12 +0000
+@@ -0,0 +1,310 @@
++;; ARM Cortex-A5 pipeline description
++;; Copyright (C) 2010 Free Software Foundation, Inc.
++;; Contributed by CodeSourcery.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++
++(define_automaton "cortex_a5")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Functional units.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; The integer (ALU) pipeline.  There are five DPU pipeline stages. However the
++;; decode/issue stages operate the same for all instructions, so do not model
++;; them.  We only need to model the first execute stage because instructions
++;; always advance one stage per cycle in order. Only branch instructions may
++;; dual-issue, so a single unit  covers all of the LS, ALU, MAC and FPU
++;; pipelines.
++
++(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
++
++;; The branch pipeline.  Branches can dual-issue with other instructions
++;; (except when those instructions take multiple cycles to issue).
++
++(define_cpu_unit "cortex_a5_branch" "cortex_a5")
++
++;; Pseudo-unit for blocking the multiply pipeline when a double-precision
++;; multiply is in progress.
++
++(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
++
++;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
++;; of the add pipeline by fmac instructions, etc.
++
++(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
++
++;; Floating-point div/sqrt (long latency, out-of-order completion).
++
++(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; ALU instructions.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++(define_insn_reservation "cortex_a5_alu" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "alu"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_alu_shift" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "alu_shift,alu_shift_reg"))
++  "cortex_a5_ex1")
++
++;; Forwarding path for unshifted operands.
++
++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
++  "cortex_a5_alu")
++
++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
++  "cortex_a5_alu_shift"
++  "arm_no_early_alu_shift_dep")
++
++;; The multiplier pipeline can forward results from wr stage only (so I don't
++;; think there's any need to specify bypasses).
++
++(define_insn_reservation "cortex_a5_mul" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "mult"))
++  "cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Load/store instructions.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; Address-generation happens in the issue stage, which is one stage behind
++;; the ex1 stage (the first stage we care about for scheduling purposes). The
++;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
++
++;; FIXME: These might not be entirely accurate for load2, load3, load4. I think
++;; they make sense since there's a 32-bit interface between the DPU and the DCU,
++;; so we can't load more than that per cycle.  The store2, store3, store4
++;; reservations are similarly guessed.
++
++(define_insn_reservation "cortex_a5_load1" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load_byte,load1"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store1" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store1"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_load2" 3
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load2"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store2" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store2"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_load3" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store3" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_load4" 5
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store4" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Branches.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; Direct branches are the only instructions we can dual-issue (also IT and
++;; nop, but those aren't very interesting for scheduling).  (The latency here
++;; is meant to represent when the branch actually takes place, but may not be
++;; entirely correct.)
++
++(define_insn_reservation "cortex_a5_branch" 3
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "branch,call"))
++  "cortex_a5_branch")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Floating-point arithmetic.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++(define_insn_reservation "cortex_a5_fpalu" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
++			fcmps, fcmpd"))
++  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
++
++;; For fconsts and fconstd, 8-bit immediate data is passed directly from
++;; f1 to f3 (which I think reduces the latency by one cycle).
++
++(define_insn_reservation "cortex_a5_fconst" 3
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fconsts,fconstd"))
++  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
++
++;; We should try not to attempt to issue a single-precision multiplication in
++;; the middle of a double-precision multiplication operation (the usage of
++;; cortex_a5_fpmul_pipe).
++
++(define_insn_reservation "cortex_a5_fpmuls" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmuls"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe")
++
++;; For single-precision multiply-accumulate, the add (accumulate) is issued
++;; whilst the multiply is in F4.  The multiply result can then be forwarded
++;; from F5 to F1.  The issue unit is only used once (when we first start
++;; processing the instruction), but the usage of the FP add pipeline could
++;; block other instructions attempting to use it simultaneously.  We try to
++;; avoid that using cortex_a5_fpadd_pipe.
++
++(define_insn_reservation "cortex_a5_fpmacs" 8
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmacs"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
++
++;; Non-multiply instructions can issue in the middle two instructions of a
++;; double-precision multiply.  Note that it isn't entirely clear when a branch
++;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
++;; that for now though.
++
++(define_insn_reservation "cortex_a5_fpmuld" 7
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmuld"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
++   cortex_a5_ex1+cortex_a5_fpmul_pipe")
++
++(define_insn_reservation "cortex_a5_fpmacd" 11
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmacd"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
++   cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Floating-point divide/square root instructions.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
++;; includes the time taken for the special instruction used to collect the
++;; result to travel down the multiply pipeline, or not.  Assuming so.  (If
++;; that's wrong, the latency should be increased by a few cycles.)
++
++;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
++;; multiply pipeline to collect the divide/square-root result.
++
++(define_insn_reservation "cortex_a5_fdivs" 14
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fdivs"))
++  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
++
++;; ??? Similarly for fdivd.
++
++(define_insn_reservation "cortex_a5_fdivd" 29
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fdivd"))
++  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; VFP to/from core transfers.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; FP loads take data from wr/rot/f3.  Might need to define bypasses to model
++;; this?
++
++;; Core-to-VFP transfers use the multiply pipeline.
++;; Not sure about this at all... I think we need some bypasses too.
++
++(define_insn_reservation "cortex_a5_r2f" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "r_2_f"))
++  "cortex_a5_ex1")
++
++;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used
++;; for store and FP->core register transfers can forward into the F2 and F3
++;; stages."
++;; This doesn't correspond to what we have though.
++
++(define_insn_reservation "cortex_a5_f2r" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_2_r"))
++  "cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; VFP flag transfer.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU
++;; specification (from fmstat to the ex2 stage of the second instruction) is
++;; not modeled at present.
++
++(define_insn_reservation "cortex_a5_f_flags" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_flag"))
++  "cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; VFP load/store.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++(define_insn_reservation "cortex_a5_f_loads" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_loads"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f_loadd" 5
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_load,f_loadd"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f_stores" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_stores"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f_stored" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_store,f_stored"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a
++;; latency of two (6.8.3).
++
++(define_bypass 2 "cortex_a5_f_loads"
++                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
++		  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
++		  cortex_a5_f2r")
++
++(define_bypass 3 "cortex_a5_f_loadd"
++                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
++		  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
++		  cortex_a5_f2r")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch
new file mode 100644
index 0000000000..bbdd38b559
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch
@@ -0,0 +1,27 @@
+	2010-06-12  Jie Zhang  <jie@codesourcery.com>
+
+	gcc/
+	* config/arm/vfp.md (arm_movsi_vfp): Set neon_type correctly
+	for neon_ldr and neon_str instructions.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+	
+ 	2010-04-11  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Issue #7326
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2010-08-13 11:40:17 +0000
++++ new/gcc/config/arm/vfp.md	2010-08-13 15:28:31 +0000
+@@ -82,7 +82,7 @@
+   "
+   [(set_attr "predicable" "yes")
+    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+-   (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
++   (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,neon_ldr,neon_str")
+    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
+ )
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch
new file mode 100644
index 0000000000..eedcf62d1e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch
@@ -0,0 +1,38 @@
+	2010-06-14  Paul Brook  <paul@codesourcery.com>
+
+	Issue #8879
+	gcc/
+	* config/arm/arm.c (use_vfp_abi): Add sorry() for Thumb-1
+	hard-float ABI.
+
+2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+ 	
+ 	2010-06-12  Jie Zhang  <jie@codesourcery.com>
+ 
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-13 15:15:12 +0000
++++ new/gcc/config/arm/arm.c	2010-08-13 15:37:39 +0000
+@@ -3969,7 +3969,18 @@
+ use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
+ {
+   if (pcs_variant == ARM_PCS_AAPCS_VFP)
+-    return true;
++    {
++      static bool seen_thumb1_vfp = false;
++
++      if (TARGET_THUMB1 && !seen_thumb1_vfp)
++	{
++	  sorry ("Thumb-1 hard-float VFP ABI");
++	  /* sorry() is not immediately fatal, so only display this once.  */
++	  seen_thumb1_vfp = true;
++	}
++
++      return true;
++    }
+ 
+   if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
+     return false;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch
new file mode 100644
index 0000000000..92dfe00383
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch
@@ -0,0 +1,27 @@
+2010-07-28  Julian Brown  <julian@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	gcc/
+	* config/arm/thumb2.md (*thumb2_movdf_soft_insn): Fix alternatives
+	for pool ranges.
+
+ 2010-07-26  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.4:
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-08-13 10:30:35 +0000
++++ new/gcc/config/arm/thumb2.md	2010-08-13 16:00:58 +0000
+@@ -319,8 +319,8 @@
+   "
+   [(set_attr "length" "8,12,16,8,8")
+    (set_attr "type" "*,*,*,load2,store2")
+-   (set_attr "pool_range" "1020")
+-   (set_attr "neg_pool_range" "0")]
++   (set_attr "pool_range" "*,*,*,1020,*")
++   (set_attr "neg_pool_range" "*,*,*,0,*")]
+ )
+ 
+ (define_insn "*thumb2_cmpsi_shiftsi"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch
new file mode 100644
index 0000000000..a58dd24416
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch
@@ -0,0 +1,1759 @@
+2010-07-28  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	Backport code hoisting improvements from mainline:
+
+	2010-07-28  Jakub Jelinek  <jakub@redhat.com>
+	PR debug/45105
+	* gcc.dg/pr45105.c: New test.
+
+	2010-07-28  Jakub Jelinek  <jakub@redhat.com>
+	PR debug/45105
+	* gcse.c (hoist_code): Use FOR_BB_INSNS macro.
+
+	2010-07-28  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/45107
+	* gcc.dg/pr45107.c: New test.
+
+	2010-07-28  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/45107
+	* gcse.c (hash_scan_set): Use max_distance for gcse-las.
+
+	2010-07-28  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/45101
+	* gcc.dg/pr45101.c: New test.
+
+	2010-07-28  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/45101
+	* gcse.c (hash_scan_set): Fix argument ordering of insert_expr_in_table
+	for gcse-las.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/40956
+	PR target/42495
+	PR middle-end/42574
+	* gcc.target/arm/pr40956.c, gcc.target/arm/pr42495.c,
+	* gcc.target/arm/pr42574.c: Add tests.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	* config/arm/arm.c (params.h): Include.
+	(arm_override_options): Tune gcse-unrestricted-cost.
+	* config/arm/t-arm (arm.o): Define dependencies.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR target/42495
+	PR middle-end/42574
+	* basic-block.h (get_dominated_to_depth): Declare.
+	* dominance.c (get_dominated_to_depth): New function, use
+	get_all_dominated_blocks as a base.
+	(get_all_dominated_blocks): Use get_dominated_to_depth.
+	* gcse.c (occr_t, VEC (occr_t, heap)): Define.
+	(hoist_exprs): Remove.
+	(alloc_code_hoist_mem, free_code_hoist_mem): Update.
+	(compute_code_hoist_vbeinout): Add debug print outs.
+	(hoist_code): Partially rewrite, simplify.  Use get_dominated_to_depth.
+	* params.def (PARAM_MAX_HOIST_DEPTH): New parameter to avoid
+	quadratic behavior.
+	* params.h (MAX_HOIST_DEPTH): New macro.
+	* doc/invoke.texi (max-hoist-depth): Document.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/40956
+	* config/arm/arm.c (thumb1_size_rtx_costs): Fix cost of simple
+	constants.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+  	PR target/42495
+  	PR middle-end/42574
+	* config/arm/arm.c (legitimize_pic_address): Use
+	gen_calculate_pic_address pattern to emit calculation of PIC address.
+	(will_be_in_index_register): New function.
+	(arm_legitimate_address_outer_p, thumb2_legitimate_address_p,)
+	(thumb1_legitimate_address_p): Use it provided !strict_p.
+	* config/arm/arm.md (calculate_pic_address): New expand and split.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR target/42495
+	PR middle-end/42574
+	* config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants.
+	* config/arm/arm.md (define_split "J", define_split "K"): Make
+	IRA/reload friendly.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	* gcse.c (insert_insn_end_basic_block): Update signature, remove
+	unused checks.
+	(pre_edge_insert, hoist_code): Update.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR target/42495
+	PR middle-end/42574
+	* gcse.c (hoist_expr_reaches_here_p): Remove excessive check.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	* gcse.c (hoist_code): Generate new pseudo for every new set insn.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	PR rtl-optimization/40956
+	PR target/42495
+	PR middle-end/42574
+	* gcse.c (compute_code_hoist_vbeinout): Consider more expressions
+	for hoisting.
+	(hoist_code): Count occurences in current block too.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	* gcse.c (struct expr:max_distance): New field.
+	(doing_code_hoisting_p): New static variable.
+	(want_to_gcse_p): Change signature.  Allow constrained hoisting of
+	simple expressions, don't change behavior for PRE.  Set max_distance.
+	(insert_expr_in_table): Set new max_distance field.
+	(hash_scan_set): Update.
+	(hoist_expr_reaches_here_p): Stop search after max_distance
+	instructions.
+	(find_occr_in_bb): New static function.  Use it in ...
+	(hoist_code): Calculate sizes of basic block before any changes are
+	done.  Pass max_distance to hoist_expr_reaches_here_p.
+	(one_code_hoisting_pass): Set doing_code_hoisting_p.
+	* params.def (PARAM_GCSE_COST_DISTANCE_RATIO,)
+	(PARAM_GCSE_UNRESTRICTED_COST): New parameters.
+	* params.h (GCSE_COST_DISTANCE_RATIO, GCSE_UNRESTRICTED_COST): New
+	macros.
+	* doc/invoke.texi (gcse-cost-distance-ratio, gcse-unrestricted-cost):
+	Document.
+
+	2010-07-27  Jeff Law  <law@redhat.com>
+	    Maxim Kuvyrkov  <maxim@codesourcery.com>
+	* gcse.c (compute_transpout, transpout): Remove, move logic
+	to prune_expressions.
+	(compute_pre_data): Move pruning of trapping expressions ...
+	(prune_expressions): ... here.  New static function.
+	(compute_code_hoist_data): Use it.
+	(alloc_code_hoist_mem, free_code_hoist_mem, hoist_code): Update.
+
+	2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+	* dbgcnt.def (hoist_insn): New debug counter.
+	* gcse.c (hoist_code): Use it.
+
+ 2010-07-28  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Backport from FSF mainline:
+
+=== modified file 'gcc/basic-block.h'
+--- old/gcc/basic-block.h	2010-04-02 18:54:46 +0000
++++ new/gcc/basic-block.h	2010-08-16 09:41:58 +0000
+@@ -932,6 +932,8 @@
+ extern VEC (basic_block, heap) *get_dominated_by_region (enum cdi_direction,
+ 							 basic_block *,
+ 							 unsigned);
++extern VEC (basic_block, heap) *get_dominated_to_depth (enum cdi_direction,
++							basic_block, int);
+ extern VEC (basic_block, heap) *get_all_dominated_blocks (enum cdi_direction,
+ 							  basic_block);
+ extern void add_to_dominance_info (enum cdi_direction, basic_block);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-13 15:37:39 +0000
++++ new/gcc/config/arm/arm.c	2010-08-16 09:41:58 +0000
+@@ -56,6 +56,7 @@
+ #include "df.h"
+ #include "intl.h"
+ #include "libfuncs.h"
++#include "params.h"
+ 
+ /* Forward definitions of types.  */
+ typedef struct minipool_node    Mnode;
+@@ -1902,6 +1903,14 @@
+       flag_reorder_blocks = 1;
+     }
+ 
++  if (!PARAM_SET_P (PARAM_GCSE_UNRESTRICTED_COST)
++      && flag_pic)
++    /* Hoisting PIC address calculations more aggressively provides a small,
++       but measurable, size reduction for PIC code.  Therefore, we decrease
++       the bar for unrestricted expression hoisting to the cost of PIC address
++       calculation, which is 2 instructions.  */
++    set_param_value ("gcse-unrestricted-cost", 2);
++
+   /* Register global variables with the garbage collector.  */
+   arm_add_gc_roots ();
+ 
+@@ -5070,17 +5079,13 @@
+   if (GET_CODE (orig) == SYMBOL_REF
+       || GET_CODE (orig) == LABEL_REF)
+     {
+-      rtx pic_ref, address;
+       rtx insn;
+ 
+       if (reg == 0)
+ 	{
+ 	  gcc_assert (can_create_pseudo_p ());
+ 	  reg = gen_reg_rtx (Pmode);
+-	  address = gen_reg_rtx (Pmode);
+ 	}
+-      else
+-	address = reg;
+ 
+       /* VxWorks does not impose a fixed gap between segments; the run-time
+ 	 gap can be different from the object-file gap.  We therefore can't
+@@ -5096,18 +5101,21 @@
+ 	insn = arm_pic_static_addr (orig, reg);
+       else
+ 	{
++	  rtx pat;
++	  rtx mem;
++
+ 	  /* If this function doesn't have a pic register, create one now.  */
+ 	  require_pic_register ();
+ 
+-	  if (TARGET_32BIT)
+-	    emit_insn (gen_pic_load_addr_32bit (address, orig));
+-	  else /* TARGET_THUMB1 */
+-	    emit_insn (gen_pic_load_addr_thumb1 (address, orig));
+-
+-	  pic_ref = gen_const_mem (Pmode,
+-				   gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
+-					         address));
+-	  insn = emit_move_insn (reg, pic_ref);
++	  pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig);
++
++	  /* Make the MEM as close to a constant as possible.  */
++	  mem = SET_SRC (pat);
++	  gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem));
++	  MEM_READONLY_P (mem) = 1;
++	  MEM_NOTRAP_P (mem) = 1;
++
++	  insn = emit_insn (pat);
+ 	}
+ 
+       /* Put a REG_EQUAL note on this insn, so that it can be optimized
+@@ -5387,6 +5395,15 @@
+   return FALSE;
+ }
+ 
++/* Return true if X will surely end up in an index register after next
++   splitting pass.  */
++static bool
++will_be_in_index_register (const_rtx x)
++{
++  /* arm.md: calculate_pic_address will split this into a register.  */
++  return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM;
++}
++
+ /* Return nonzero if X is a valid ARM state address operand.  */
+ int
+ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
+@@ -5444,8 +5461,9 @@
+       rtx xop1 = XEXP (x, 1);
+ 
+       return ((arm_address_register_rtx_p (xop0, strict_p)
+-	       && GET_CODE(xop1) == CONST_INT
+-	       && arm_legitimate_index_p (mode, xop1, outer, strict_p))
++	       && ((GET_CODE(xop1) == CONST_INT
++		    && arm_legitimate_index_p (mode, xop1, outer, strict_p))
++		   || (!strict_p && will_be_in_index_register (xop1))))
+ 	      || (arm_address_register_rtx_p (xop1, strict_p)
+ 		  && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
+     }
+@@ -5531,7 +5549,8 @@
+       rtx xop1 = XEXP (x, 1);
+ 
+       return ((arm_address_register_rtx_p (xop0, strict_p)
+-	       && thumb2_legitimate_index_p (mode, xop1, strict_p))
++	       && (thumb2_legitimate_index_p (mode, xop1, strict_p)
++		   || (!strict_p && will_be_in_index_register (xop1))))
+ 	      || (arm_address_register_rtx_p (xop1, strict_p)
+ 		  && thumb2_legitimate_index_p (mode, xop0, strict_p)));
+     }
+@@ -5834,7 +5853,8 @@
+ 	  && XEXP (x, 0) != frame_pointer_rtx
+ 	  && XEXP (x, 1) != frame_pointer_rtx
+ 	  && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
+-	  && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
++	  && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)
++	      || (!strict_p && will_be_in_index_register (XEXP (x, 1)))))
+ 	return 1;
+ 
+       /* REG+const has 5-7 bit offset for non-SP registers.  */
+@@ -6413,12 +6433,16 @@
+ 
+     case CONST_INT:
+       if (outer == SET)
+-	{
+-	  if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
+-	    return 0;
+-	  if (thumb_shiftable_const (INTVAL (x)))
+-	    return COSTS_N_INSNS (2);
+-	  return COSTS_N_INSNS (3);
++        {
++          if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
++            return COSTS_N_INSNS (1);
++	  /* See split "TARGET_THUMB1 && satisfies_constraint_J".  */
++	  if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
++            return COSTS_N_INSNS (2);
++	  /* See split "TARGET_THUMB1 && satisfies_constraint_K".  */
++          if (thumb_shiftable_const (INTVAL (x)))
++            return COSTS_N_INSNS (2);
++          return COSTS_N_INSNS (3);
+ 	}
+       else if ((outer == PLUS || outer == COMPARE)
+ 	       && INTVAL (x) < 256 && INTVAL (x) > -256)
+@@ -7110,6 +7134,12 @@
+ 	 a single register, otherwise it costs one insn per word.  */
+       if (REG_P (XEXP (x, 0)))
+ 	*total = COSTS_N_INSNS (1);
++      else if (flag_pic
++	       && GET_CODE (XEXP (x, 0)) == PLUS
++	       && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
++	/* This will be split into two instructions.
++	   See arm.md:calculate_pic_address.  */
++	*total = COSTS_N_INSNS (2);
+       else
+ 	*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+       return true;
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-13 15:15:12 +0000
++++ new/gcc/config/arm/arm.md	2010-08-16 09:41:58 +0000
+@@ -5290,17 +5290,21 @@
+   [(set (match_operand:SI 0 "register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+   "TARGET_THUMB1 && satisfies_constraint_J (operands[1])"
+-  [(set (match_dup 0) (match_dup 1))
+-   (set (match_dup 0) (neg:SI (match_dup 0)))]
+-  "operands[1] = GEN_INT (- INTVAL (operands[1]));"
++  [(set (match_dup 2) (match_dup 1))
++   (set (match_dup 0) (neg:SI (match_dup 2)))]
++  "
++  {
++    operands[1] = GEN_INT (- INTVAL (operands[1]));
++    operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
++  }"
+ )
+ 
+ (define_split 
+   [(set (match_operand:SI 0 "register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+   "TARGET_THUMB1 && satisfies_constraint_K (operands[1])"
+-  [(set (match_dup 0) (match_dup 1))
+-   (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
++  [(set (match_dup 2) (match_dup 1))
++   (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))]
+   "
+   {
+     unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu;
+@@ -5311,12 +5315,13 @@
+       if ((val & (mask << i)) == val)
+         break;
+ 
+-    /* Shouldn't happen, but we don't want to split if the shift is zero.  */
++    /* Don't split if the shift is zero.  */
+     if (i == 0)
+       FAIL;
+ 
+     operands[1] = GEN_INT (val >> i);
+-    operands[2] = GEN_INT (i);
++    operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
++    operands[3] = GEN_INT (i);
+   }"
+ )
+ 
+@@ -5325,6 +5330,34 @@
+ ;; we use an unspec.  The offset will be loaded from a constant pool entry,
+ ;; since that is the only type of relocation we can use.
+ 
++;; Wrap calculation of the whole PIC address in a single pattern for the
++;; benefit of optimizers, particularly, PRE and HOIST.  Calculation of
++;; a PIC address involves two loads from memory, so we want to CSE it
++;; as often as possible.
++;; This pattern will be split into one of the pic_load_addr_* patterns
++;; and a move after GCSE optimizations.
++;;
++;; Note: Update arm.c: legitimize_pic_address() when changing this pattern.
++(define_expand "calculate_pic_address"
++  [(set (match_operand:SI 0 "register_operand" "")
++	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "")
++			 (unspec:SI [(match_operand:SI 2 "" "")]
++				    UNSPEC_PIC_SYM))))]
++  "flag_pic"
++)
++
++;; Split calculate_pic_address into pic_load_addr_* and a move.
++(define_split
++  [(set (match_operand:SI 0 "register_operand" "")
++	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "")
++			 (unspec:SI [(match_operand:SI 2 "" "")]
++				    UNSPEC_PIC_SYM))))]
++  "flag_pic"
++  [(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_PIC_SYM))
++   (set (match_dup 0) (mem:SI (plus:SI (match_dup 1) (match_dup 3))))]
++  "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];"
++)
++
+ ;; The rather odd constraints on the following are to force reload to leave
+ ;; the insn alone, and to force the minipool generation pass to then move
+ ;; the GOT symbol to memory.
+
+=== modified file 'gcc/config/arm/t-arm'
+--- old/gcc/config/arm/t-arm	2009-06-21 19:48:15 +0000
++++ new/gcc/config/arm/t-arm	2010-08-16 09:41:58 +0000
+@@ -45,6 +45,15 @@
+ 		$(srcdir)/config/arm/arm-cores.def > \
+ 		$(srcdir)/config/arm/arm-tune.md
+ 
++arm.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
++  $(RTL_H) $(TREE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
++  insn-config.h conditions.h output.h \
++  $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
++  $(EXPR_H) $(OPTABS_H) toplev.h $(RECOG_H) $(CGRAPH_H) \
++  $(GGC_H) except.h $(C_PRAGMA_H) $(INTEGRATE_H) $(TM_P_H) \
++  $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
++  intl.h libfuncs.h $(PARAMS_H)
++
+ arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \
+     coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H)
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+
+=== modified file 'gcc/dbgcnt.def'
+--- old/gcc/dbgcnt.def	2009-11-25 10:55:54 +0000
++++ new/gcc/dbgcnt.def	2010-08-16 09:41:58 +0000
+@@ -158,6 +158,7 @@
+ DEBUG_COUNTER (global_alloc_at_func)
+ DEBUG_COUNTER (global_alloc_at_reg)
+ DEBUG_COUNTER (hoist)
++DEBUG_COUNTER (hoist_insn)
+ DEBUG_COUNTER (ia64_sched2)
+ DEBUG_COUNTER (if_conversion)
+ DEBUG_COUNTER (if_after_combine)
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-08-05 15:20:54 +0000
++++ new/gcc/doc/invoke.texi	2010-08-16 09:41:58 +0000
+@@ -8086,6 +8086,29 @@
+ vectorization needs to be greater than the value specified by this option
+ to allow vectorization.  The default value is 0.
+ 
++@item gcse-cost-distance-ratio
++Scaling factor in calculation of maximum distance an expression
++can be moved by GCSE optimizations.  This is currently supported only in
++code hoisting pass.  The bigger the ratio, the more agressive code hoisting
++will be with simple expressions, i.e., the expressions which have cost
++less than @option{gcse-unrestricted-cost}.  Specifying 0 will disable
++hoisting of simple expressions.  The default value is 10.
++
++@item gcse-unrestricted-cost
++Cost, roughly measured as the cost of a single typical machine
++instruction, at which GCSE optimizations will not constrain
++the distance an expression can travel.  This is currently
++supported only in code hoisting pass.  The lesser the cost,
++the more aggressive code hoisting will be.  Specifying 0 will
++allow all expressions to travel unrestricted distances.
++The default value is 3.
++
++@item max-hoist-depth
++The depth of search in the dominator tree for expressions to hoist.
++This is used to avoid quadratic behavior in hoisting algorithm.
++The value of 0 will avoid limiting the search, but may slow down compilation
++of huge functions.  The default value is 30.
++
+ @item max-unrolled-insns
+ The maximum number of instructions that a loop should have if that loop
+ is unrolled, and if the loop is unrolled, it determines how many times
+
+=== modified file 'gcc/dominance.c'
+--- old/gcc/dominance.c	2010-04-02 18:54:46 +0000
++++ new/gcc/dominance.c	2010-08-16 09:41:58 +0000
+@@ -782,16 +782,20 @@
+ }
+ 
+ /* Returns the list of basic blocks including BB dominated by BB, in the
+-   direction DIR.  The vector will be sorted in preorder.  */
++   direction DIR up to DEPTH in the dominator tree.  The DEPTH of zero will
++   produce a vector containing all dominated blocks.  The vector will be sorted
++   in preorder.  */
+ 
+ VEC (basic_block, heap) *
+-get_all_dominated_blocks (enum cdi_direction dir, basic_block bb)
++get_dominated_to_depth (enum cdi_direction dir, basic_block bb, int depth)
+ {
+   VEC(basic_block, heap) *bbs = NULL;
+   unsigned i;
++  unsigned next_level_start;
+ 
+   i = 0;
+   VEC_safe_push (basic_block, heap, bbs, bb);
++  next_level_start = 1; /* = VEC_length (basic_block, bbs); */
+ 
+   do
+     {
+@@ -802,12 +806,24 @@
+ 	   son;
+ 	   son = next_dom_son (dir, son))
+ 	VEC_safe_push (basic_block, heap, bbs, son);
++
++      if (i == next_level_start && --depth)
++	next_level_start = VEC_length (basic_block, bbs);
+     }
+-  while (i < VEC_length (basic_block, bbs));
++  while (i < next_level_start);
+ 
+   return bbs;
+ }
+ 
++/* Returns the list of basic blocks including BB dominated by BB, in the
++   direction DIR.  The vector will be sorted in preorder.  */
++
++VEC (basic_block, heap) *
++get_all_dominated_blocks (enum cdi_direction dir, basic_block bb)
++{
++  return get_dominated_to_depth (dir, bb, 0);
++}
++
+ /* Redirect all edges pointing to BB to TO.  */
+ void
+ redirect_immediate_dominators (enum cdi_direction dir, basic_block bb,
+
+=== modified file 'gcc/gcse.c'
+--- old/gcc/gcse.c	2010-03-16 10:50:42 +0000
++++ new/gcc/gcse.c	2010-08-16 09:41:58 +0000
+@@ -296,6 +296,12 @@
+      The value is the newly created pseudo-reg to record a copy of the
+      expression in all the places that reach the redundant copy.  */
+   rtx reaching_reg;
++  /* Maximum distance in instructions this expression can travel.
++     We avoid moving simple expressions for more than a few instructions
++     to keep register pressure under control.
++     A value of "0" removes restrictions on how far the expression can
++     travel.  */
++  int max_distance;
+ };
+ 
+ /* Occurrence of an expression.
+@@ -317,6 +323,10 @@
+   char copied_p;
+ };
+ 
++typedef struct occr *occr_t;
++DEF_VEC_P (occr_t);
++DEF_VEC_ALLOC_P (occr_t, heap);
++
+ /* Expression and copy propagation hash tables.
+    Each hash table is an array of buckets.
+    ??? It is known that if it were an array of entries, structure elements
+@@ -419,6 +429,9 @@
+ /* Number of global copies propagated.  */
+ static int global_copy_prop_count;
+ 
++/* Doing code hoisting.  */
++static bool doing_code_hoisting_p = false;
++
+ /* For available exprs */
+ static sbitmap *ae_kill;
+ 
+@@ -432,12 +445,12 @@
+ static void hash_scan_set (rtx, rtx, struct hash_table_d *);
+ static void hash_scan_clobber (rtx, rtx, struct hash_table_d *);
+ static void hash_scan_call (rtx, rtx, struct hash_table_d *);
+-static int want_to_gcse_p (rtx);
++static int want_to_gcse_p (rtx, int *);
+ static bool gcse_constant_p (const_rtx);
+ static int oprs_unchanged_p (const_rtx, const_rtx, int);
+ static int oprs_anticipatable_p (const_rtx, const_rtx);
+ static int oprs_available_p (const_rtx, const_rtx);
+-static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int,
++static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, int,
+ 				  struct hash_table_d *);
+ static void insert_set_in_table (rtx, rtx, struct hash_table_d *);
+ static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int);
+@@ -462,7 +475,6 @@
+ static void alloc_cprop_mem (int, int);
+ static void free_cprop_mem (void);
+ static void compute_transp (const_rtx, int, sbitmap *, int);
+-static void compute_transpout (void);
+ static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *,
+ 				      struct hash_table_d *);
+ static void compute_cprop_data (void);
+@@ -486,7 +498,7 @@
+ static void compute_pre_data (void);
+ static int pre_expr_reaches_here_p (basic_block, struct expr *,
+ 				    basic_block);
+-static void insert_insn_end_basic_block (struct expr *, basic_block, int);
++static void insert_insn_end_basic_block (struct expr *, basic_block);
+ static void pre_insert_copy_insn (struct expr *, rtx);
+ static void pre_insert_copies (void);
+ static int pre_delete (void);
+@@ -497,7 +509,8 @@
+ static void free_code_hoist_mem (void);
+ static void compute_code_hoist_vbeinout (void);
+ static void compute_code_hoist_data (void);
+-static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *);
++static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *,
++				      int, int *);
+ static int hoist_code (void);
+ static int one_code_hoisting_pass (void);
+ static rtx process_insert_insn (struct expr *);
+@@ -755,7 +768,7 @@
+    GCSE.  */
+ 
+ static int
+-want_to_gcse_p (rtx x)
++want_to_gcse_p (rtx x, int *max_distance_ptr)
+ {
+ #ifdef STACK_REGS
+   /* On register stack architectures, don't GCSE constants from the
+@@ -765,18 +778,67 @@
+     x = avoid_constant_pool_reference (x);
+ #endif
+ 
++  /* GCSE'ing constants:
++
++     We do not specifically distinguish between constant and non-constant
++     expressions in PRE and Hoist.  We use rtx_cost below to limit
++     the maximum distance simple expressions can travel.
++
++     Nevertheless, constants are much easier to GCSE, and, hence,
++     it is easy to overdo the optimizations.  Usually, excessive PRE and
++     Hoisting of constant leads to increased register pressure.
++
++     RA can deal with this by rematerialing some of the constants.
++     Therefore, it is important that the back-end generates sets of constants
++     in a way that allows reload rematerialize them under high register
++     pressure, i.e., a pseudo register with REG_EQUAL to constant
++     is set only once.  Failing to do so will result in IRA/reload
++     spilling such constants under high register pressure instead of
++     rematerializing them.  */
++
+   switch (GET_CODE (x))
+     {
+     case REG:
+     case SUBREG:
+-    case CONST_INT:
+-    case CONST_DOUBLE:
+-    case CONST_FIXED:
+-    case CONST_VECTOR:
+     case CALL:
+       return 0;
+ 
++    case CONST_INT:
++    case CONST_DOUBLE:
++    case CONST_FIXED:
++    case CONST_VECTOR:
++      if (!doing_code_hoisting_p)
++	/* Do not PRE constants.  */
++	return 0;
++
++      /* FALLTHRU */
++
+     default:
++      if (doing_code_hoisting_p)
++	/* PRE doesn't implement max_distance restriction.  */
++	{
++	  int cost;
++	  int max_distance;
++
++	  gcc_assert (!optimize_function_for_speed_p (cfun)
++		      && optimize_function_for_size_p (cfun));
++	  cost = rtx_cost (x, SET, 0);
++
++	  if (cost < COSTS_N_INSNS (GCSE_UNRESTRICTED_COST))
++	    {
++	      max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10;
++	      if (max_distance == 0)
++		return 0;
++
++	      gcc_assert (max_distance > 0);
++	    }
++	  else
++	    max_distance = 0;
++
++	  if (max_distance_ptr)
++	    *max_distance_ptr = max_distance;
++	}
++
+       return can_assign_to_reg_without_clobbers_p (x);
+     }
+ }
+@@ -1090,11 +1152,14 @@
+    It is only used if X is a CONST_INT.
+ 
+    ANTIC_P is nonzero if X is an anticipatable expression.
+-   AVAIL_P is nonzero if X is an available expression.  */
++   AVAIL_P is nonzero if X is an available expression.
++
++   MAX_DISTANCE is the maximum distance in instructions this expression can
++   be moved.  */
+ 
+ static void
+ insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p,
+-		      int avail_p, struct hash_table_d *table)
++		      int avail_p, int max_distance, struct hash_table_d *table)
+ {
+   int found, do_not_record_p;
+   unsigned int hash;
+@@ -1137,7 +1202,11 @@
+       cur_expr->next_same_hash = NULL;
+       cur_expr->antic_occr = NULL;
+       cur_expr->avail_occr = NULL;
++      gcc_assert (max_distance >= 0);
++      cur_expr->max_distance = max_distance;
+     }
++  else
++    gcc_assert (cur_expr->max_distance == max_distance);
+ 
+   /* Now record the occurrence(s).  */
+   if (antic_p)
+@@ -1238,6 +1307,8 @@
+       cur_expr->next_same_hash = NULL;
+       cur_expr->antic_occr = NULL;
+       cur_expr->avail_occr = NULL;
++      /* Not used for set_p tables.  */
++      cur_expr->max_distance = 0;
+     }
+ 
+   /* Now record the occurrence.  */
+@@ -1307,6 +1378,7 @@
+     {
+       unsigned int regno = REGNO (dest);
+       rtx tmp;
++      int max_distance = 0;
+ 
+       /* See if a REG_EQUAL note shows this equivalent to a simpler expression.
+ 
+@@ -1329,7 +1401,7 @@
+ 	  && !REG_P (src)
+ 	  && (table->set_p
+ 	      ? gcse_constant_p (XEXP (note, 0))
+-	      : want_to_gcse_p (XEXP (note, 0))))
++	      : want_to_gcse_p (XEXP (note, 0), NULL)))
+ 	src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src);
+ 
+       /* Only record sets of pseudo-regs in the hash table.  */
+@@ -1344,7 +1416,7 @@
+ 	     can't do the same thing at the rtl level.  */
+ 	  && !can_throw_internal (insn)
+ 	  /* Is SET_SRC something we want to gcse?  */
+-	  && want_to_gcse_p (src)
++	  && want_to_gcse_p (src, &max_distance)
+ 	  /* Don't CSE a nop.  */
+ 	  && ! set_noop_p (pat)
+ 	  /* Don't GCSE if it has attached REG_EQUIV note.
+@@ -1368,7 +1440,8 @@
+ 	  int avail_p = (oprs_available_p (src, insn)
+ 			 && ! JUMP_P (insn));
+ 
+-	  insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table);
++	  insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p,
++				max_distance, table);
+ 	}
+ 
+       /* Record sets for constant/copy propagation.  */
+@@ -1394,6 +1467,7 @@
+   else if (flag_gcse_las && REG_P (src) && MEM_P (dest))
+       {
+         unsigned int regno = REGNO (src);
++	int max_distance = 0;
+ 
+         /* Do not do this for constant/copy propagation.  */
+         if (! table->set_p
+@@ -1405,7 +1479,7 @@
+ 	      do that easily for EH edges so disable GCSE on these for now.  */
+ 	   && !can_throw_internal (insn)
+ 	   /* Is SET_DEST something we want to gcse?  */
+-	   && want_to_gcse_p (dest)
++	   && want_to_gcse_p (dest, &max_distance)
+ 	   /* Don't CSE a nop.  */
+ 	   && ! set_noop_p (pat)
+ 	   /* Don't GCSE if it has attached REG_EQUIV note.
+@@ -1427,7 +1501,7 @@
+ 
+ 	       /* Record the memory expression (DEST) in the hash table.  */
+ 	       insert_expr_in_table (dest, GET_MODE (dest), insn,
+-				     antic_p, avail_p, table);
++				     antic_p, avail_p, max_distance, table);
+              }
+       }
+ }
+@@ -1513,8 +1587,8 @@
+     if (flat_table[i] != 0)
+       {
+ 	expr = flat_table[i];
+-	fprintf (file, "Index %d (hash value %d)\n  ",
+-		 expr->bitmap_index, hash_val[i]);
++	fprintf (file, "Index %d (hash value %d; max distance %d)\n  ",
++		 expr->bitmap_index, hash_val[i], expr->max_distance);
+ 	print_rtl (file, expr->expr);
+ 	fprintf (file, "\n");
+       }
+@@ -3168,11 +3242,6 @@
+ /* Nonzero for expressions that are transparent in the block.  */
+ static sbitmap *transp;
+ 
+-/* Nonzero for expressions that are transparent at the end of the block.
+-   This is only zero for expressions killed by abnormal critical edge
+-   created by a calls.  */
+-static sbitmap *transpout;
+-
+ /* Nonzero for expressions that are computed (available) in the block.  */
+ static sbitmap *comp;
+ 
+@@ -3236,28 +3305,105 @@
+   pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL;
+ }
+ 
+-/* Top level routine to do the dataflow analysis needed by PRE.  */
++/* Remove certain expressions from anticipatable and transparent
++   sets of basic blocks that have incoming abnormal edge.
++   For PRE remove potentially trapping expressions to avoid placing
++   them on abnormal edges.  For hoisting remove memory references that
++   can be clobbered by calls.  */
+ 
+ static void
+-compute_pre_data (void)
++prune_expressions (bool pre_p)
+ {
+-  sbitmap trapping_expr;
+-  basic_block bb;
++  sbitmap prune_exprs;
+   unsigned int ui;
+-
+-  compute_local_properties (transp, comp, antloc, &expr_hash_table);
+-  sbitmap_vector_zero (ae_kill, last_basic_block);
+-
+-  /* Collect expressions which might trap.  */
+-  trapping_expr = sbitmap_alloc (expr_hash_table.n_elems);
+-  sbitmap_zero (trapping_expr);
++  basic_block bb;
++
++  prune_exprs = sbitmap_alloc (expr_hash_table.n_elems);
++  sbitmap_zero (prune_exprs);
+   for (ui = 0; ui < expr_hash_table.size; ui++)
+     {
+       struct expr *e;
+       for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash)
+-	if (may_trap_p (e->expr))
+-	  SET_BIT (trapping_expr, e->bitmap_index);
+-    }
++	{
++	  /* Note potentially trapping expressions.  */
++	  if (may_trap_p (e->expr))
++	    {
++	      SET_BIT (prune_exprs, e->bitmap_index);
++	      continue;
++	    }
++
++	  if (!pre_p && MEM_P (e->expr))
++	    /* Note memory references that can be clobbered by a call.
++	       We do not split abnormal edges in hoisting, so would
++	       a memory reference get hoisted along an abnormal edge,
++	       it would be placed /before/ the call.  Therefore, only
++	       constant memory references can be hoisted along abnormal
++	       edges.  */
++	    {
++	      if (GET_CODE (XEXP (e->expr, 0)) == SYMBOL_REF
++		  && CONSTANT_POOL_ADDRESS_P (XEXP (e->expr, 0)))
++		continue;
++
++	      if (MEM_READONLY_P (e->expr)
++		  && !MEM_VOLATILE_P (e->expr)
++		  && MEM_NOTRAP_P (e->expr))
++		/* Constant memory reference, e.g., a PIC address.  */
++		continue;
++
++	      /* ??? Optimally, we would use interprocedural alias
++		 analysis to determine if this mem is actually killed
++		 by this call.  */
++
++	      SET_BIT (prune_exprs, e->bitmap_index);
++	    }
++	}
++    }
++
++  FOR_EACH_BB (bb)
++    {
++      edge e;
++      edge_iterator ei;
++
++      /* If the current block is the destination of an abnormal edge, we
++	 kill all trapping (for PRE) and memory (for hoist) expressions
++	 because we won't be able to properly place the instruction on
++	 the edge.  So make them neither anticipatable nor transparent.
++	 This is fairly conservative.
++
++	 ??? For hoisting it may be necessary to check for set-and-jump
++	 instructions here, not just for abnormal edges.  The general problem
++	 is that when an expression cannot not be placed right at the end of
++	 a basic block we should account for any side-effects of a subsequent
++	 jump instructions that could clobber the expression.  It would
++	 be best to implement this check along the lines of
++	 hoist_expr_reaches_here_p where the target block is already known
++	 and, hence, there's no need to conservatively prune expressions on
++	 "intermediate" set-and-jump instructions.  */
++      FOR_EACH_EDGE (e, ei, bb->preds)
++	if ((e->flags & EDGE_ABNORMAL)
++	    && (pre_p || CALL_P (BB_END (e->src))))
++	  {
++	    sbitmap_difference (antloc[bb->index],
++				antloc[bb->index], prune_exprs);
++	    sbitmap_difference (transp[bb->index],
++				transp[bb->index], prune_exprs);
++	    break;
++	  }
++    }
++
++  sbitmap_free (prune_exprs);
++}
++
++/* Top level routine to do the dataflow analysis needed by PRE.  */
++
++static void
++compute_pre_data (void)
++{
++  basic_block bb;
++
++  compute_local_properties (transp, comp, antloc, &expr_hash_table);
++  prune_expressions (true);
++  sbitmap_vector_zero (ae_kill, last_basic_block);
+ 
+   /* Compute ae_kill for each basic block using:
+ 
+@@ -3266,21 +3412,6 @@
+ 
+   FOR_EACH_BB (bb)
+     {
+-      edge e;
+-      edge_iterator ei;
+-
+-      /* If the current block is the destination of an abnormal edge, we
+-	 kill all trapping expressions because we won't be able to properly
+-	 place the instruction on the edge.  So make them neither
+-	 anticipatable nor transparent.  This is fairly conservative.  */
+-      FOR_EACH_EDGE (e, ei, bb->preds)
+-	if (e->flags & EDGE_ABNORMAL)
+-	  {
+-	    sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr);
+-	    sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr);
+-	    break;
+-	  }
+-
+       sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]);
+       sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]);
+     }
+@@ -3291,7 +3422,6 @@
+   antloc = NULL;
+   sbitmap_vector_free (ae_kill);
+   ae_kill = NULL;
+-  sbitmap_free (trapping_expr);
+ }
+ 
+ /* PRE utilities */
+@@ -3406,14 +3536,10 @@
+ 
+ /* Add EXPR to the end of basic block BB.
+ 
+-   This is used by both the PRE and code hoisting.
+-
+-   For PRE, we want to verify that the expr is either transparent
+-   or locally anticipatable in the target block.  This check makes
+-   no sense for code hoisting.  */
++   This is used by both the PRE and code hoisting.  */
+ 
+ static void
+-insert_insn_end_basic_block (struct expr *expr, basic_block bb, int pre)
++insert_insn_end_basic_block (struct expr *expr, basic_block bb)
+ {
+   rtx insn = BB_END (bb);
+   rtx new_insn;
+@@ -3440,12 +3566,6 @@
+ #ifdef HAVE_cc0
+       rtx note;
+ #endif
+-      /* It should always be the case that we can put these instructions
+-	 anywhere in the basic block with performing PRE optimizations.
+-	 Check this.  */
+-      gcc_assert (!NONJUMP_INSN_P (insn) || !pre
+-		  || TEST_BIT (antloc[bb->index], expr->bitmap_index)
+-		  || TEST_BIT (transp[bb->index], expr->bitmap_index));
+ 
+       /* If this is a jump table, then we can't insert stuff here.  Since
+ 	 we know the previous real insn must be the tablejump, we insert
+@@ -3482,15 +3602,7 @@
+       /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers,
+ 	 we search backward and place the instructions before the first
+ 	 parameter is loaded.  Do this for everyone for consistency and a
+-	 presumption that we'll get better code elsewhere as well.
+-
+-	 It should always be the case that we can put these instructions
+-	 anywhere in the basic block with performing PRE optimizations.
+-	 Check this.  */
+-
+-      gcc_assert (!pre
+-		  || TEST_BIT (antloc[bb->index], expr->bitmap_index)
+-		  || TEST_BIT (transp[bb->index], expr->bitmap_index));
++	 presumption that we'll get better code elsewhere as well.  */
+ 
+       /* Since different machines initialize their parameter registers
+ 	 in different orders, assume nothing.  Collect the set of all
+@@ -3587,7 +3699,7 @@
+ 			   now.  */
+ 
+ 			if (eg->flags & EDGE_ABNORMAL)
+-			  insert_insn_end_basic_block (index_map[j], bb, 0);
++			  insert_insn_end_basic_block (index_map[j], bb);
+ 			else
+ 			  {
+ 			    insn = process_insert_insn (index_map[j]);
+@@ -4046,61 +4158,12 @@
+     }
+ }
+ 
+-/* Compute transparent outgoing information for each block.
+-
+-   An expression is transparent to an edge unless it is killed by
+-   the edge itself.  This can only happen with abnormal control flow,
+-   when the edge is traversed through a call.  This happens with
+-   non-local labels and exceptions.
+-
+-   This would not be necessary if we split the edge.  While this is
+-   normally impossible for abnormal critical edges, with some effort
+-   it should be possible with exception handling, since we still have
+-   control over which handler should be invoked.  But due to increased
+-   EH table sizes, this may not be worthwhile.  */
+-
+-static void
+-compute_transpout (void)
+-{
+-  basic_block bb;
+-  unsigned int i;
+-  struct expr *expr;
+-
+-  sbitmap_vector_ones (transpout, last_basic_block);
+-
+-  FOR_EACH_BB (bb)
+-    {
+-      /* Note that flow inserted a nop at the end of basic blocks that
+-	 end in call instructions for reasons other than abnormal
+-	 control flow.  */
+-      if (! CALL_P (BB_END (bb)))
+-	continue;
+-
+-      for (i = 0; i < expr_hash_table.size; i++)
+-	for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash)
+-	  if (MEM_P (expr->expr))
+-	    {
+-	      if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF
+-		  && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0)))
+-		continue;
+-
+-	      /* ??? Optimally, we would use interprocedural alias
+-		 analysis to determine if this mem is actually killed
+-		 by this call.  */
+-	      RESET_BIT (transpout[bb->index], expr->bitmap_index);
+-	    }
+-    }
+-}
+-
+ /* Code Hoisting variables and subroutines.  */
+ 
+ /* Very busy expressions.  */
+ static sbitmap *hoist_vbein;
+ static sbitmap *hoist_vbeout;
+ 
+-/* Hoistable expressions.  */
+-static sbitmap *hoist_exprs;
+-
+ /* ??? We could compute post dominators and run this algorithm in
+    reverse to perform tail merging, doing so would probably be
+    more effective than the tail merging code in jump.c.
+@@ -4119,8 +4182,6 @@
+ 
+   hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs);
+   hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs);
+-  hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs);
+-  transpout = sbitmap_vector_alloc (n_blocks, n_exprs);
+ }
+ 
+ /* Free vars used for code hoisting analysis.  */
+@@ -4134,8 +4195,6 @@
+ 
+   sbitmap_vector_free (hoist_vbein);
+   sbitmap_vector_free (hoist_vbeout);
+-  sbitmap_vector_free (hoist_exprs);
+-  sbitmap_vector_free (transpout);
+ 
+   free_dominance_info (CDI_DOMINATORS);
+ }
+@@ -4166,8 +4225,15 @@
+       FOR_EACH_BB_REVERSE (bb)
+ 	{
+ 	  if (bb->next_bb != EXIT_BLOCK_PTR)
+-	    sbitmap_intersection_of_succs (hoist_vbeout[bb->index],
+-					   hoist_vbein, bb->index);
++	    {
++	      sbitmap_intersection_of_succs (hoist_vbeout[bb->index],
++					     hoist_vbein, bb->index);
++
++	      /* Include expressions in VBEout that are calculated
++		 in BB and available at its end.  */
++	      sbitmap_a_or_b (hoist_vbeout[bb->index],
++			      hoist_vbeout[bb->index], comp[bb->index]);
++	    }
+ 
+ 	  changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index],
+ 					      antloc[bb->index],
+@@ -4179,7 +4245,17 @@
+     }
+ 
+   if (dump_file)
+-    fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes);
++    {
++      fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes);
++
++      FOR_EACH_BB (bb)
++        {
++	  fprintf (dump_file, "vbein (%d): ", bb->index);
++	  dump_sbitmap_file (dump_file, hoist_vbein[bb->index]);
++	  fprintf (dump_file, "vbeout(%d): ", bb->index);
++	  dump_sbitmap_file (dump_file, hoist_vbeout[bb->index]);
++	}
++    }
+ }
+ 
+ /* Top level routine to do the dataflow analysis needed by code hoisting.  */
+@@ -4188,7 +4264,7 @@
+ compute_code_hoist_data (void)
+ {
+   compute_local_properties (transp, comp, antloc, &expr_hash_table);
+-  compute_transpout ();
++  prune_expressions (false);
+   compute_code_hoist_vbeinout ();
+   calculate_dominance_info (CDI_DOMINATORS);
+   if (dump_file)
+@@ -4197,6 +4273,8 @@
+ 
+ /* Determine if the expression identified by EXPR_INDEX would
+    reach BB unimpared if it was placed at the end of EXPR_BB.
++   Stop the search if the expression would need to be moved more
++   than DISTANCE instructions.
+ 
+    It's unclear exactly what Muchnick meant by "unimpared".  It seems
+    to me that the expression must either be computed or transparent in
+@@ -4209,12 +4287,24 @@
+    paths.  */
+ 
+ static int
+-hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited)
++hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb,
++			   char *visited, int distance, int *bb_size)
+ {
+   edge pred;
+   edge_iterator ei;
+   int visited_allocated_locally = 0;
+ 
++  /* Terminate the search if distance, for which EXPR is allowed to move,
++     is exhausted.  */
++  if (distance > 0)
++    {
++      distance -= bb_size[bb->index];
++
++      if (distance <= 0)
++	return 0;
++    }
++  else
++    gcc_assert (distance == 0);
+ 
+   if (visited == NULL)
+     {
+@@ -4233,9 +4323,6 @@
+       else if (visited[pred_bb->index])
+ 	continue;
+ 
+-      /* Does this predecessor generate this expression?  */
+-      else if (TEST_BIT (comp[pred_bb->index], expr_index))
+-	break;
+       else if (! TEST_BIT (transp[pred_bb->index], expr_index))
+ 	break;
+ 
+@@ -4243,8 +4330,8 @@
+       else
+ 	{
+ 	  visited[pred_bb->index] = 1;
+-	  if (! hoist_expr_reaches_here_p (expr_bb, expr_index,
+-					   pred_bb, visited))
++	  if (! hoist_expr_reaches_here_p (expr_bb, expr_index, pred_bb,
++					   visited, distance, bb_size))
+ 	    break;
+ 	}
+     }
+@@ -4254,20 +4341,33 @@
+   return (pred == NULL);
+ }
+ 
++/* Find occurence in BB.  */
++static struct occr *
++find_occr_in_bb (struct occr *occr, basic_block bb)
++{
++  /* Find the right occurrence of this expression.  */
++  while (occr && BLOCK_FOR_INSN (occr->insn) != bb)
++    occr = occr->next;
++
++  return occr;
++}
++
+ /* Actually perform code hoisting.  */
+ 
+ static int
+ hoist_code (void)
+ {
+   basic_block bb, dominated;
++  VEC (basic_block, heap) *dom_tree_walk;
++  unsigned int dom_tree_walk_index;
+   VEC (basic_block, heap) *domby;
+   unsigned int i,j;
+   struct expr **index_map;
+   struct expr *expr;
++  int *to_bb_head;
++  int *bb_size;
+   int changed = 0;
+ 
+-  sbitmap_vector_zero (hoist_exprs, last_basic_block);
+-
+   /* Compute a mapping from expression number (`bitmap_index') to
+      hash table entry.  */
+ 
+@@ -4276,28 +4376,98 @@
+     for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
+       index_map[expr->bitmap_index] = expr;
+ 
++  /* Calculate sizes of basic blocks and note how far
++     each instruction is from the start of its block.  We then use this
++     data to restrict distance an expression can travel.  */
++
++  to_bb_head = XCNEWVEC (int, get_max_uid ());
++  bb_size = XCNEWVEC (int, last_basic_block);
++
++  FOR_EACH_BB (bb)
++    {
++      rtx insn;
++      int to_head;
++
++      to_head = 0;
++      FOR_BB_INSNS (bb, insn)
++	{
++	  /* Don't count debug instructions to avoid them affecting
++	     decision choices.  */
++	  if (NONDEBUG_INSN_P (insn))
++	    to_bb_head[INSN_UID (insn)] = to_head++;
++	}
++
++      bb_size[bb->index] = to_head;
++    }
++
++  gcc_assert (EDGE_COUNT (ENTRY_BLOCK_PTR->succs) == 1
++	      && (EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest
++		  == ENTRY_BLOCK_PTR->next_bb));
++
++  dom_tree_walk = get_all_dominated_blocks (CDI_DOMINATORS,
++					    ENTRY_BLOCK_PTR->next_bb);
++
+   /* Walk over each basic block looking for potentially hoistable
+      expressions, nothing gets hoisted from the entry block.  */
+-  FOR_EACH_BB (bb)
++  for (dom_tree_walk_index = 0;
++       VEC_iterate (basic_block, dom_tree_walk, dom_tree_walk_index, bb);
++       dom_tree_walk_index++)
+     {
+-      int found = 0;
+-      int insn_inserted_p;
+-
+-      domby = get_dominated_by (CDI_DOMINATORS, bb);
++      domby = get_dominated_to_depth (CDI_DOMINATORS, bb, MAX_HOIST_DEPTH);
++
++      if (VEC_length (basic_block, domby) == 0)
++	continue;
++
+       /* Examine each expression that is very busy at the exit of this
+ 	 block.  These are the potentially hoistable expressions.  */
+       for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++)
+ 	{
+-	  int hoistable = 0;
+-
+-	  if (TEST_BIT (hoist_vbeout[bb->index], i)
+-	      && TEST_BIT (transpout[bb->index], i))
++	  if (TEST_BIT (hoist_vbeout[bb->index], i))
+ 	    {
++	      /* Current expression.  */
++	      struct expr *expr = index_map[i];
++	      /* Number of occurences of EXPR that can be hoisted to BB.  */
++	      int hoistable = 0;
++	      /* Basic blocks that have occurences reachable from BB.  */
++	      bitmap_head _from_bbs, *from_bbs = &_from_bbs;
++	      /* Occurences reachable from BB.  */
++	      VEC (occr_t, heap) *occrs_to_hoist = NULL;
++	      /* We want to insert the expression into BB only once, so
++		 note when we've inserted it.  */
++	      int insn_inserted_p;
++	      occr_t occr;
++
++	      bitmap_initialize (from_bbs, 0);
++
++	      /* If an expression is computed in BB and is available at end of
++		 BB, hoist all occurences dominated by BB to BB.  */
++	      if (TEST_BIT (comp[bb->index], i))
++		{
++		  occr = find_occr_in_bb (expr->antic_occr, bb);
++
++		  if (occr)
++		    {
++		      /* An occurence might've been already deleted
++			 while processing a dominator of BB.  */
++		      if (occr->deleted_p)
++			gcc_assert (MAX_HOIST_DEPTH > 1);
++		      else
++			{
++			  gcc_assert (NONDEBUG_INSN_P (occr->insn));
++			  hoistable++;
++			}
++		    }
++		  else
++		    hoistable++;
++		}
++
+ 	      /* We've found a potentially hoistable expression, now
+ 		 we look at every block BB dominates to see if it
+ 		 computes the expression.  */
+ 	      for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++)
+ 		{
++		  int max_distance;
++
+ 		  /* Ignore self dominance.  */
+ 		  if (bb == dominated)
+ 		    continue;
+@@ -4307,17 +4477,43 @@
+ 		  if (!TEST_BIT (antloc[dominated->index], i))
+ 		    continue;
+ 
++		  occr = find_occr_in_bb (expr->antic_occr, dominated);
++		  gcc_assert (occr);
++
++		  /* An occurence might've been already deleted
++		     while processing a dominator of BB.  */
++		  if (occr->deleted_p)
++		    {
++		      gcc_assert (MAX_HOIST_DEPTH > 1);
++		      continue;
++		    }
++		  gcc_assert (NONDEBUG_INSN_P (occr->insn));
++
++		  max_distance = expr->max_distance;
++		  if (max_distance > 0)
++		    /* Adjust MAX_DISTANCE to account for the fact that
++		       OCCR won't have to travel all of DOMINATED, but
++		       only part of it.  */
++		    max_distance += (bb_size[dominated->index]
++				     - to_bb_head[INSN_UID (occr->insn)]);
++
+ 		  /* Note if the expression would reach the dominated block
+ 		     unimpared if it was placed at the end of BB.
+ 
+ 		     Keep track of how many times this expression is hoistable
+ 		     from a dominated block into BB.  */
+-		  if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
+-		    hoistable++;
++		  if (hoist_expr_reaches_here_p (bb, i, dominated, NULL,
++						 max_distance, bb_size))
++		    {
++		      hoistable++;
++		      VEC_safe_push (occr_t, heap,
++				     occrs_to_hoist, occr);
++		      bitmap_set_bit (from_bbs, dominated->index);
++		    }
+ 		}
+ 
+ 	      /* If we found more than one hoistable occurrence of this
+-		 expression, then note it in the bitmap of expressions to
++		 expression, then note it in the vector of expressions to
+ 		 hoist.  It makes no sense to hoist things which are computed
+ 		 in only one BB, and doing so tends to pessimize register
+ 		 allocation.  One could increase this value to try harder
+@@ -4326,91 +4522,80 @@
+ 		 the vast majority of hoistable expressions are only movable
+ 		 from two successors, so raising this threshold is likely
+ 		 to nullify any benefit we get from code hoisting.  */
+-	      if (hoistable > 1)
+-		{
+-		  SET_BIT (hoist_exprs[bb->index], i);
+-		  found = 1;
+-		}
+-	    }
+-	}
+-      /* If we found nothing to hoist, then quit now.  */
+-      if (! found)
+-        {
+-	  VEC_free (basic_block, heap, domby);
+-	  continue;
+-	}
+-
+-      /* Loop over all the hoistable expressions.  */
+-      for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++)
+-	{
+-	  /* We want to insert the expression into BB only once, so
+-	     note when we've inserted it.  */
+-	  insn_inserted_p = 0;
+-
+-	  /* These tests should be the same as the tests above.  */
+-	  if (TEST_BIT (hoist_exprs[bb->index], i))
+-	    {
+-	      /* We've found a potentially hoistable expression, now
+-		 we look at every block BB dominates to see if it
+-		 computes the expression.  */
+-	      for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++)
+-		{
+-		  /* Ignore self dominance.  */
+-		  if (bb == dominated)
+-		    continue;
+-
+-		  /* We've found a dominated block, now see if it computes
+-		     the busy expression and whether or not moving that
+-		     expression to the "beginning" of that block is safe.  */
+-		  if (!TEST_BIT (antloc[dominated->index], i))
+-		    continue;
+-
+-		  /* The expression is computed in the dominated block and
+-		     it would be safe to compute it at the start of the
+-		     dominated block.  Now we have to determine if the
+-		     expression would reach the dominated block if it was
+-		     placed at the end of BB.  */
+-		  if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
+-		    {
+-		      struct expr *expr = index_map[i];
+-		      struct occr *occr = expr->antic_occr;
+-		      rtx insn;
+-		      rtx set;
+-
+-		      /* Find the right occurrence of this expression.  */
+-		      while (BLOCK_FOR_INSN (occr->insn) != dominated && occr)
+-			occr = occr->next;
+-
+-		      gcc_assert (occr);
+-		      insn = occr->insn;
+-		      set = single_set (insn);
+-		      gcc_assert (set);
+-
+-		      /* Create a pseudo-reg to store the result of reaching
+-			 expressions into.  Get the mode for the new pseudo
+-			 from the mode of the original destination pseudo.  */
+-		      if (expr->reaching_reg == NULL)
+-			expr->reaching_reg
+-			  = gen_reg_rtx_and_attrs (SET_DEST (set));
+-
+-		      gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
+-		      delete_insn (insn);
+-		      occr->deleted_p = 1;
+-		      changed = 1;
+-		      gcse_subst_count++;
+-
+-		      if (!insn_inserted_p)
+-			{
+-			  insert_insn_end_basic_block (index_map[i], bb, 0);
+-			  insn_inserted_p = 1;
+-			}
+-		    }
+-		}
++	      if (hoistable > 1 && dbg_cnt (hoist_insn))
++		{
++		  /* If (hoistable != VEC_length), then there is
++		     an occurence of EXPR in BB itself.  Don't waste
++		     time looking for LCA in this case.  */
++		  if ((unsigned) hoistable
++		      == VEC_length (occr_t, occrs_to_hoist))
++		    {
++		      basic_block lca;
++
++		      lca = nearest_common_dominator_for_set (CDI_DOMINATORS,
++							      from_bbs);
++		      if (lca != bb)
++			/* Punt, it's better to hoist these occurences to
++			   LCA.  */
++			VEC_free (occr_t, heap, occrs_to_hoist);
++		    }
++		}
++	      else
++		/* Punt, no point hoisting a single occurence.  */
++		VEC_free (occr_t, heap, occrs_to_hoist);
++
++	      insn_inserted_p = 0;
++
++	      /* Walk through occurences of I'th expressions we want
++		 to hoist to BB and make the transformations.  */
++	      for (j = 0;
++		   VEC_iterate (occr_t, occrs_to_hoist, j, occr);
++		   j++)
++		{
++		  rtx insn;
++		  rtx set;
++
++		  gcc_assert (!occr->deleted_p);
++
++		  insn = occr->insn;
++		  set = single_set (insn);
++		  gcc_assert (set);
++
++		  /* Create a pseudo-reg to store the result of reaching
++		     expressions into.  Get the mode for the new pseudo
++		     from the mode of the original destination pseudo.
++
++		     It is important to use new pseudos whenever we
++		     emit a set.  This will allow reload to use
++		     rematerialization for such registers.  */
++		  if (!insn_inserted_p)
++		    expr->reaching_reg
++		      = gen_reg_rtx_and_attrs (SET_DEST (set));
++
++		  gcse_emit_move_after (expr->reaching_reg, SET_DEST (set),
++					insn);
++		  delete_insn (insn);
++		  occr->deleted_p = 1;
++		  changed = 1;
++		  gcse_subst_count++;
++
++		  if (!insn_inserted_p)
++		    {
++		      insert_insn_end_basic_block (expr, bb);
++		      insn_inserted_p = 1;
++		    }
++		}
++
++	      VEC_free (occr_t, heap, occrs_to_hoist);
++	      bitmap_clear (from_bbs);
+ 	    }
+ 	}
+       VEC_free (basic_block, heap, domby);
+     }
+ 
++  VEC_free (basic_block, heap, dom_tree_walk);
++  free (bb_size);
++  free (to_bb_head);
+   free (index_map);
+ 
+   return changed;
+@@ -4433,6 +4618,8 @@
+       || is_too_expensive (_("GCSE disabled")))
+     return 0;
+ 
++  doing_code_hoisting_p = true;
++
+   /* We need alias.  */
+   init_alias_analysis ();
+ 
+@@ -4468,6 +4655,8 @@
+ 	       gcse_subst_count, gcse_create_count);
+     }
+ 
++  doing_code_hoisting_p = false;
++
+   return changed;
+ }
+ 
+
+=== modified file 'gcc/params.def'
+--- old/gcc/params.def	2010-04-02 18:54:46 +0000
++++ new/gcc/params.def	2010-08-16 09:41:58 +0000
+@@ -219,6 +219,29 @@
+ 	"gcse-after-reload-critical-fraction",
+ 	"The threshold ratio of critical edges execution count that permit performing redundancy elimination after reload",
+         10, 0, 0)
++
++/* GCSE will use GCSE_COST_DISTANCE_RATION as a scaling factor
++   to calculate maximum distance for which an expression is allowed to move
++   from its rtx_cost.  */
++DEFPARAM(PARAM_GCSE_COST_DISTANCE_RATIO,
++	 "gcse-cost-distance-ratio",
++	 "Scaling factor in calculation of maximum distance an expression can be moved by GCSE optimizations",
++	 10, 0, 0)
++/* GCSE won't restrict distance for which an expression with rtx_cost greater
++   than COSTS_N_INSN(GCSE_UNRESTRICTED_COST) is allowed to move.  */
++DEFPARAM(PARAM_GCSE_UNRESTRICTED_COST,
++	 "gcse-unrestricted-cost",
++	 "Cost at which GCSE optimizations will not constraint the distance an expression can travel",
++	 3, 0, 0)
++
++/* How deep from a given basic block the dominator tree should be searched
++   for expressions to hoist to the block.  The value of 0 will avoid limiting
++   the search.  */
++DEFPARAM(PARAM_MAX_HOIST_DEPTH,
++	 "max-hoist-depth",
++	 "Maximum depth of search in the dominator tree for expressions to hoist",
++	 30, 0, 0)
++
+ /* This parameter limits the number of insns in a loop that will be unrolled,
+    and by how much the loop is unrolled.
+ 
+
+=== modified file 'gcc/params.h'
+--- old/gcc/params.h	2009-12-01 19:12:29 +0000
++++ new/gcc/params.h	2010-08-16 09:41:58 +0000
+@@ -125,6 +125,12 @@
+   PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_PARTIAL_FRACTION)
+ #define GCSE_AFTER_RELOAD_CRITICAL_FRACTION \
+   PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_CRITICAL_FRACTION)
++#define GCSE_COST_DISTANCE_RATIO \
++  PARAM_VALUE (PARAM_GCSE_COST_DISTANCE_RATIO)
++#define GCSE_UNRESTRICTED_COST \
++  PARAM_VALUE (PARAM_GCSE_UNRESTRICTED_COST)
++#define MAX_HOIST_DEPTH \
++  PARAM_VALUE (PARAM_MAX_HOIST_DEPTH)
+ #define MAX_UNROLLED_INSNS \
+   PARAM_VALUE (PARAM_MAX_UNROLLED_INSNS)
+ #define MAX_SMS_LOOP_NUMBER \
+
+=== added file 'gcc/testsuite/gcc.dg/pr45101.c'
+--- old/gcc/testsuite/gcc.dg/pr45101.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr45101.c	2010-08-16 09:41:58 +0000
+@@ -0,0 +1,15 @@
++/* PR rtl-optimization/45101 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -fgcse -fgcse-las" } */
++
++struct
++{
++  int i;
++} *s;
++
++extern void bar (void);
++
++void foo ()
++{
++  !s ? s->i++ : bar ();
++}
+
+=== added file 'gcc/testsuite/gcc.dg/pr45105.c'
+--- old/gcc/testsuite/gcc.dg/pr45105.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr45105.c	2010-08-16 09:41:58 +0000
+@@ -0,0 +1,27 @@
++/* PR debug/45105 */
++/* { dg-do compile } */
++/* { dg-options "-Os -fcompare-debug" } */
++
++extern int *baz (int *, int *);
++
++void
++bar (int *p1, int *p2)
++{
++  int n = *baz (0, 0);
++  p1[n] = p2[n];
++}
++
++void
++foo (int *p, int l)
++{
++  int a1[32];
++  int a2[32];
++  baz (a1, a2);
++  while (l)
++    {
++      if (l & 1)
++	p = baz (a2, p);
++      l--;
++      bar (a1, a2);
++    }
++}
+
+=== added file 'gcc/testsuite/gcc.dg/pr45107.c'
+--- old/gcc/testsuite/gcc.dg/pr45107.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr45107.c	2010-08-16 09:41:58 +0000
+@@ -0,0 +1,13 @@
++/* PR rtl-optimization/45107 */
++/* { dg-do compile } */
++/* { dg-options "-Os -fgcse-las" } */
++
++extern void bar(int *);
++
++int foo (int *p)
++{
++    int i = *p;
++    if (i != 1)
++      bar(&i);
++    *p = i;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr40956.c'
+--- old/gcc/testsuite/gcc.target/arm/pr40956.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr40956.c	2010-08-16 09:41:58 +0000
+@@ -0,0 +1,14 @@
++/* { dg-options "-mthumb -Os -fpic -march=armv5te" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-require-effective-target fpic } */
++/* Make sure the constant "0" is loaded into register only once.  */
++/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */
++
++int foo(int p, int* q)
++{
++  if (p!=9)
++    *q = 0;
++  else
++    *(q+1) = 0;
++  return 3;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr42495.c'
+--- old/gcc/testsuite/gcc.target/arm/pr42495.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr42495.c	2010-08-16 09:41:58 +0000
+@@ -0,0 +1,31 @@
++/* { dg-options "-mthumb -Os -fpic -march=armv5te -fdump-rtl-hoist" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-require-effective-target fpic } */
++/* Make sure all calculations of gObj's address get hoisted to one location.  */
++/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */
++
++struct st_a {
++   int data;
++};
++
++struct st_b {
++   struct st_a *p_a;
++    struct st_b *next;
++};
++
++extern struct st_b gObj;
++extern void foo(int, struct st_b*);
++
++int goo(struct st_b * obj) {
++   struct st_a *pa;
++   if (gObj.p_a->data != 0) {
++     foo(gObj.p_a->data, obj);
++   }
++   pa = obj->p_a;
++   if (pa == 0) {
++     return 0;
++   } else if (pa == gObj.p_a) {
++     return 0;
++   }
++   return pa->data;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr42574.c'
+--- old/gcc/testsuite/gcc.target/arm/pr42574.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr42574.c	2010-08-16 09:41:58 +0000
+@@ -0,0 +1,24 @@
++/* { dg-options "-mthumb -Os -fpic -march=armv5te" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-require-effective-target fpic } */
++/* Make sure the address of glob.c is calculated only once and using
++   a logical shift for the offset (200<<1).  */
++/* { dg-final { scan-assembler-times "lsl" 1 } } */
++
++struct A {
++ char a[400];
++ float* c;
++};
++struct A glob;
++void func();
++void func1(float*);
++int func2(float*, int*);
++void func3(float*);
++
++void test(int *p) {
++ func1(glob.c);
++ if (func2(glob.c, p)) {
++   func();
++ }
++ func3(glob.c);
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch
new file mode 100644
index 0000000000..db9e63917d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch
@@ -0,0 +1,17586 @@
+2010-08-04  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/neon-testgen.ml (regexps): Allow any characters
+	in comments after assembly instructions.
+
+	gcc/testsuite/
+	* gcc.target/arm/neon/vfp-shift-a2t2.c: Allow any characters in
+	comments after assembly instructions.
+	* gcc.target/arm/neon/v*.c: Regenerate.
+
+ 2010-07-28  Maxim Kuvyrkov  <maxim@codesourcery.com>
+ 
+ 	Backport code hoisting improvements from mainline:
+
+=== modified file 'gcc/config/arm/neon-testgen.ml'
+--- old/gcc/config/arm/neon-testgen.ml	2010-07-29 15:38:15 +0000
++++ new/gcc/config/arm/neon-testgen.ml	2010-08-20 13:27:11 +0000
+@@ -257,7 +257,7 @@
+      intrinsic expands to.  Watch out for any writeback character and
+      comments after the instruction.  *)
+   let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^
+-			  "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n")
++			  "!?\\(\\[ \t\\]+@.*\\)?\\n")
+                          (analyze_all_shapes features shape analyze_shape)
+   in
+     (* Emit file and function prologues.  *)
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshls64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabals16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabals16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabals32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabals32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabals8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabals8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabals8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabalu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabalu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabalu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabalu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabas16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabas16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabas32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabas32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabas8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabas8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabas8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabau16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabau16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabau32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabau32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabau8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabau8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabau8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabds16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabds16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabds32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabds32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabds8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabds8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabds8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabdu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabdu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabsf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabsf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabsf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabss16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabss16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabss32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabss32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vabss8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vabss8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vabss8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vadds16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vadds16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vadds32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vadds32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vadds8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vadds8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddws16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddws32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddws8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddws8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vands16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vands16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vands32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vands32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vands8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vands8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vandu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vandu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbics16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbics16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbics32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbics32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbics8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbics8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbicu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbicu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslp16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslp8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbsls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbsls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbsls64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls64.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbsls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbsls8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu64.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vbslu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vbslu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcageQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcagef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcagef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcalef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcalef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcalef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vceqs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vceqs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcequ16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcequ32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcequ8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcequ8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcges16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcges16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcges32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcges32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcges8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcges8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcges8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgts16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgts32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgts8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgts8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcles16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcles16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcles32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcles32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcles8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcles8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcles8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcleu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcleu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclss16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclss16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclss32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclss32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclss8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclss8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclss8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclts16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclts16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclts32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclts32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclts8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclts8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclts8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcltu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcltu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vclzu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vclzu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcntp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcntp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcnts8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcnts8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcnts8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcntu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcntu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcntu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veorQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veorQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veors16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veors16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veors32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veors32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veors8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veors8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veoru16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veoru16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veoru32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veoru32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/veoru8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/veoru8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vexts16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vexts16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vexts32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vexts32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vexts64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vexts64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vexts8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vexts8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vexts8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vextu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vextu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vextu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c	2010-08-20 13:27:11 +0000
+@@ -22,7 +22,7 @@
+     return vshll_n_u32(a, 32);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhadds16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhadds32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhadds8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhadds8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x4_t = vld1q_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x8_t = vld1q_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x16_t = vld1q_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x8_t = vld1q_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x4_t = vld1q_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x2_t = vld1q_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x16_t = vld1q_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x8_t = vld1q_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x4_t = vld1q_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x2_t = vld1q_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x16_t = vld1q_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x4_t = vld1q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x8_t = vld1q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x16_t = vld1q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x8_t = vld1q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x4_t = vld1q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x2_t = vld1q_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x16_t = vld1q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x8_t = vld1q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x4_t = vld1q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x2_t = vld1q_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x16_t = vld1q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2_t = vld1_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4_t = vld1_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8_t = vld1_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4_t = vld1_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2_t = vld1_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1_t = vld1_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8_t = vld1_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4_t = vld1_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2_t = vld1_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1_t = vld1_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8_t = vld1_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2_t = vld1_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4_t = vld1_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8_t = vld1_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4_t = vld1_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2_t = vld1_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1_t = vld1_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8_t = vld1_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4_t = vld1_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2_t = vld1_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1_t = vld1_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8_t = vld1_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_float32x4x2_t = vld2q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_poly16x8x2_t = vld2q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_poly8x16x2_t = vld2q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int16x8x2_t = vld2q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int32x4x2_t = vld2q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int8x16x2_t = vld2q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint16x8x2_t = vld2q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint32x4x2_t = vld2q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint8x16x2_t = vld2q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x2_t = vld2_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x2_t = vld2_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x2_t = vld2_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x2_t = vld2_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x2_t = vld2_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x2_t = vld2_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x2_t = vld2_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x2_t = vld2_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x2_t = vld2_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x2_t = vld2_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x2_t = vld2_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x2_t = vld2_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x2_t = vld2_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x2_t = vld2_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x2_t = vld2_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x2_t = vld2_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x2_t = vld2_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x2_t = vld2_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x2_t = vld2_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x2_t = vld2_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x2_t = vld2_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x2_t = vld2_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_float32x4x3_t = vld3q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_poly16x8x3_t = vld3q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_poly8x16x3_t = vld3q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int16x8x3_t = vld3q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int32x4x3_t = vld3q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int8x16x3_t = vld3q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint16x8x3_t = vld3q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint32x4x3_t = vld3q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint8x16x3_t = vld3q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x3_t = vld3_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x3_t = vld3_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x3_t = vld3_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x3_t = vld3_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x3_t = vld3_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x3_t = vld3_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x3_t = vld3_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x3_t = vld3_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x3_t = vld3_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x3_t = vld3_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x3_t = vld3_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x3_t = vld3_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x3_t = vld3_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x3_t = vld3_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x3_t = vld3_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x3_t = vld3_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x3_t = vld3_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x3_t = vld3_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x3_t = vld3_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x3_t = vld3_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x3_t = vld3_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x3_t = vld3_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_float32x4x4_t = vld4q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_poly16x8x4_t = vld4q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_poly8x16x4_t = vld4q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int16x8x4_t = vld4q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int32x4x4_t = vld4q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_int8x16x4_t = vld4q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint16x8x4_t = vld4q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint32x4x4_t = vld4q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c	2010-08-20 13:27:11 +0000
+@@ -15,6 +15,6 @@
+   out_uint8x16x4_t = vld4q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x4_t = vld4_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x4_t = vld4_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x4_t = vld4_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x4_t = vld4_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x4_t = vld4_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x4_t = vld4_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x4_t = vld4_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x4_t = vld4_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x4_t = vld4_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x4_t = vld4_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x4_t = vld4_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x4_t = vld4_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x4_t = vld4_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x4_t = vld4_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x4_t = vld4_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x4_t = vld4_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x4_t = vld4_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x4_t = vld4_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x4_t = vld4_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x4_t = vld4_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x4_t = vld4_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c	2010-08-20 13:27:11 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x4_t = vld4_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmins16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmins16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmins32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmins32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmins8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmins8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmins8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vminu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vminu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vminu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlals16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlals32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlals8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlals8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlas16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlas32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlas8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlas8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlau16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlau32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlau8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlau8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlss16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlss32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlss8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlss8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovls8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmullp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmullp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmullu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmullu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmullu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmullu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmuls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmuls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmuls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmuls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmulu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmulu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vnegs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vnegs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vornu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vornu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorrs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorrs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorru16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorru16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorru32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorru32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vorru8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vorru8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadals16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadals32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadals8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadals8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadds16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadds32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpadds8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpadds8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpminf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpminf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmins16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmins32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpmins8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpmins8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpminu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpminu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vpminu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vpminu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqabss16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqabss32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqabss8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqabss8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqadds16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqadds32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqadds64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqadds8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqadds8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshls64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshls64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshls64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshlu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshlu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c	2010-08-20 13:27:11 +0000
+@@ -16,6 +16,6 @@
+   vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c	2010-08-20 13:27:11 +0000
+@@ -16,5 +16,5 @@
+   vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubls16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubls32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubls8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubls8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsublu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsublu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsublu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsublu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubws16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubws32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubws8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubws8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c	2010-08-20 13:27:11 +0000
+@@ -18,5 +18,5 @@
+   out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrns16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrns32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrns8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrns8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtsts16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtsts32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtsts8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtsts8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vtstu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vtstu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzps16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzps32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzps8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzps8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipf32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipf32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipp16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipp16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipp8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipp8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzips16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzips16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzips32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzips32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzips8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzips8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzips8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipu16.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu16.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipu32.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu32.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vzipu8.c	2010-07-29 15:38:15 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vzipu8.c	2010-08-20 13:27:11 +0000
+@@ -17,5 +17,5 @@
+   out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch
new file mode 100644
index 0000000000..7003cf8376
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch
@@ -0,0 +1,95 @@
+2010-08-05  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #7257
+
+	Backport from mainline:
+
+	gcc/
+	2010-08-05  Jie Zhang  <jie@codesourcery.com>
+	PR tree-optimization/45144
+	* tree-sra.c (type_consists_of_records_p): Return false
+	if the record contains bit-field.
+
+	gcc/testsuite/
+	2010-08-05  Jie Zhang  <jie@codesourcery.com>
+	PR tree-optimization/45144
+	* gcc.dg/tree-ssa/pr45144.c: New test.
+
+ 2010-08-04  Mark Mitchell  <mark@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== added file 'gcc/testsuite/gcc.dg/tree-ssa/pr45144.c'
+--- old/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c	2010-08-20 16:04:44 +0000
+@@ -0,0 +1,46 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-optimized" } */
++
++void baz (unsigned);
++
++extern unsigned buf[];
++
++struct A
++{
++  unsigned a1:10;
++  unsigned a2:3;
++  unsigned:19;
++};
++
++union TMP
++{
++  struct A a;
++  unsigned int b;
++};
++
++static unsigned
++foo (struct A *p)
++{
++  union TMP t;
++  struct A x;
++  
++  x = *p;
++  t.a = x;
++  return t.b;
++}
++
++void
++bar (unsigned orig, unsigned *new)
++{
++  struct A a;
++  union TMP s;
++
++  s.b = orig;
++  a = s.a;
++  if (a.a1)
++    baz (a.a2);
++  *new = foo (&a);
++}
++
++/* { dg-final { scan-tree-dump "x = a;" "optimized"} } */
++/* { dg-final { cleanup-tree-dump "optimized" } } */
+
+=== modified file 'gcc/tree-sra.c'
+--- old/gcc/tree-sra.c	2010-08-10 13:31:21 +0000
++++ new/gcc/tree-sra.c	2010-08-20 16:04:44 +0000
+@@ -805,7 +805,7 @@
+ /* Return true iff TYPE is a RECORD_TYPE with fields that are either of gimple
+    register types or (recursively) records with only these two kinds of fields.
+    It also returns false if any of these records has a zero-size field as its
+-   last field.  */
++   last field or has a bit-field.  */
+ 
+ static bool
+ type_consists_of_records_p (tree type)
+@@ -821,6 +821,9 @@
+       {
+ 	tree ft = TREE_TYPE (fld);
+ 
++	if (DECL_BIT_FIELD (fld))
++	  return false;
++
+ 	if (!is_gimple_reg_type (ft)
+ 	    && !type_consists_of_records_p (ft))
+ 	  return false;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch
new file mode 100644
index 0000000000..8ae781ecab
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch
@@ -0,0 +1,511 @@
+2010-08-05  Julian Brown  <julian@codesourcery.com>
+
+	Backport from mainline (candidate patch):
+
+	gcc/
+	* expr.c (expand_assignment): Add assertion to prevent emitting null
+	rtx for movmisalign pattern.
+	(expand_expr_real_1): Likewise.
+	* config/arm/arm.c (arm_builtin_support_vector_misalignment): New.
+	(TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): New. Use above.
+	(arm_vector_alignment_reachable): New.
+	(TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE): New. Use above.
+	(neon_vector_mem_operand): Disallow PRE_DEC for misaligned loads.
+	(arm_print_operand): Include alignment qualifier in %A.
+	* config/arm/neon.md (UNSPEC_MISALIGNED_ACCESS): New constant.
+	(movmisalign<mode>): New expander.
+	(movmisalign<mode>_neon_store, movmisalign<mode>_neon_load): New
+	insn patterns.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-42.c: Use vect_element_align instead of
+	vect_hw_misalign.
+	* gcc.dg/vect/vect-60.c: Likewise.
+	* gcc.dg/vect/vect-56.c: Likewise.
+	* gcc.dg/vect/vect-93.c: Likewise.
+	* gcc.dg/vect/no-scevccp-outer-8.c: Likewise.
+	* gcc.dg/vect/vect-95.c: Likewise.
+	* gcc.dg/vect/vect-96.c: Likewise.
+	* gcc.dg/vect/vect-outer-5.c: Use quad-word vectors when available.
+	* gcc.dg/vect/slp-25.c: Likewise.
+	* gcc.dg/vect/slp-3.c: Likewise.
+	* gcc.dg/vect/vect-multitypes-1.c: Likewise.
+	* gcc.dg/vect/no-vfa-pr29145.c: Likewise.
+	* gcc.dg/vect/vect-multitypes-4.c: Likewise. Use vect_element_align.
+	* gcc.dg/vect/vect-109.c: Likewise.
+	* gcc.dg/vect/vect-peel-1.c: Likewise.
+	* gcc.dg/vect/vect-peel-2.c: Likewise.
+	* lib/target-supports.exp
+	(check_effective_target_arm_vect_no_misalign): New.
+	(check_effective_target_vect_no_align): Use above.
+	(check_effective_target_vect_element_align): New.
+	(add_options_for_quad_vectors): New.
+
+ 2010-08-05  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Issue #7257
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-16 09:41:58 +0000
++++ new/gcc/config/arm/arm.c	2010-08-20 16:21:01 +0000
+@@ -228,6 +228,11 @@
+ static void arm_trampoline_init (rtx, tree, rtx);
+ static rtx arm_trampoline_adjust_address (rtx);
+ static rtx arm_pic_static_addr (rtx orig, rtx reg);
++static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
++static bool arm_builtin_support_vector_misalignment (enum machine_mode mode,
++						     const_tree type,
++						     int misalignment,
++						     bool is_packed);
+ 
+ 
+ /* Table of machine attributes.  */
+@@ -514,6 +519,14 @@
+ #undef TARGET_CAN_ELIMINATE
+ #define TARGET_CAN_ELIMINATE arm_can_eliminate
+ 
++#undef TARGET_VECTOR_ALIGNMENT_REACHABLE
++#define TARGET_VECTOR_ALIGNMENT_REACHABLE \
++  arm_vector_alignment_reachable
++
++#undef TARGET_SUPPORT_VECTOR_MISALIGNMENT
++#define TARGET_SUPPORT_VECTOR_MISALIGNMENT \
++  arm_builtin_support_vector_misalignment
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ /* Obstack for minipool constant handling.  */
+@@ -9084,7 +9097,8 @@
+     return arm_address_register_rtx_p (ind, 0);
+ 
+   /* Allow post-increment with Neon registers.  */
+-  if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC))
++  if ((type != 1 && GET_CODE (ind) == POST_INC)
++      || (type == 0 && GET_CODE (ind) == PRE_DEC))
+     return arm_address_register_rtx_p (XEXP (ind, 0), 0);
+ 
+   /* FIXME: vld1 allows register post-modify.  */
+@@ -16365,6 +16379,8 @@
+       {
+ 	rtx addr;
+ 	bool postinc = FALSE;
++	unsigned align, modesize, align_bits;
++
+ 	gcc_assert (GET_CODE (x) == MEM);
+ 	addr = XEXP (x, 0);
+ 	if (GET_CODE (addr) == POST_INC)
+@@ -16372,7 +16388,29 @@
+ 	    postinc = 1;
+ 	    addr = XEXP (addr, 0);
+ 	  }
+-	asm_fprintf (stream, "[%r]", REGNO (addr));
++	asm_fprintf (stream, "[%r", REGNO (addr));
++
++	/* We know the alignment of this access, so we can emit a hint in the
++	   instruction (for some alignments) as an aid to the memory subsystem
++	   of the target.  */
++	align = MEM_ALIGN (x) >> 3;
++	modesize = GET_MODE_SIZE (GET_MODE (x));
++	
++	/* Only certain alignment specifiers are supported by the hardware.  */
++	if (modesize == 16 && (align % 32) == 0)
++	  align_bits = 256;
++	else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
++	  align_bits = 128;
++	else if ((align % 8) == 0)
++	  align_bits = 64;
++	else
++	  align_bits = 0;
++	
++	if (align_bits != 0)
++	  asm_fprintf (stream, ", :%d", align_bits);
++
++	asm_fprintf (stream, "]");
++
+ 	if (postinc)
+ 	  fputs("!", stream);
+       }
+@@ -22450,4 +22488,43 @@
+   return !TARGET_THUMB1;
+ }
+ 
++static bool
++arm_vector_alignment_reachable (const_tree type, bool is_packed)
++{
++  /* Vectors which aren't in packed structures will not be less aligned than
++     the natural alignment of their element type, so this is safe.  */
++  if (TARGET_NEON && !BYTES_BIG_ENDIAN)
++    return !is_packed;
++
++  return default_builtin_vector_alignment_reachable (type, is_packed);
++}
++
++static bool
++arm_builtin_support_vector_misalignment (enum machine_mode mode,
++					 const_tree type, int misalignment,
++					 bool is_packed)
++{
++  if (TARGET_NEON && !BYTES_BIG_ENDIAN)
++    {
++      HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type);
++
++      if (is_packed)
++        return align == 1;
++
++      /* If the misalignment is unknown, we should be able to handle the access
++	 so long as it is not to a member of a packed data structure.  */
++      if (misalignment == -1)
++        return true;
++
++      /* Return true if the misalignment is a multiple of the natural alignment
++         of the vector's element type.  This is probably always going to be
++	 true in practice, since we've already established that this isn't a
++	 packed access.  */
++      return ((misalignment % align) == 0);
++    }
++  
++  return default_builtin_support_vector_misalignment (mode, type, misalignment,
++						      is_packed);
++}
++
+ #include "gt-arm.h"
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2010-08-13 11:40:17 +0000
++++ new/gcc/config/arm/neon.md	2010-08-20 16:21:01 +0000
+@@ -140,7 +140,8 @@
+    (UNSPEC_VUZP1		201)
+    (UNSPEC_VUZP2		202)
+    (UNSPEC_VZIP1		203)
+-   (UNSPEC_VZIP2		204)])
++   (UNSPEC_VZIP2		204)
++   (UNSPEC_MISALIGNED_ACCESS	205)])
+ 
+ ;; Double-width vector modes.
+ (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
+@@ -660,6 +661,52 @@
+   neon_disambiguate_copy (operands, dest, src, 4);
+ })
+ 
++(define_expand "movmisalign<mode>"
++  [(set (match_operand:VDQX 0 "nonimmediate_operand"	      "")
++	(unspec:VDQX [(match_operand:VDQX 1 "general_operand" "")]
++		     UNSPEC_MISALIGNED_ACCESS))]
++  "TARGET_NEON && !BYTES_BIG_ENDIAN"
++{
++  /* This pattern is not permitted to fail during expansion: if both arguments
++     are non-registers (e.g. memory := constant, which can be created by the
++     auto-vectorizer), force operand 1 into a register.  */
++  if (!s_register_operand (operands[0], <MODE>mode)
++      && !s_register_operand (operands[1], <MODE>mode))
++    operands[1] = force_reg (<MODE>mode, operands[1]);
++})
++
++(define_insn "*movmisalign<mode>_neon_store"
++  [(set (match_operand:VDX 0 "memory_operand"		       "=Um")
++	(unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")]
++		    UNSPEC_MISALIGNED_ACCESS))]
++  "TARGET_NEON && !BYTES_BIG_ENDIAN"
++  "vst1.<V_sz_elem>\t{%P1}, %A0"
++  [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
++
++(define_insn "*movmisalign<mode>_neon_load"
++  [(set (match_operand:VDX 0 "s_register_operand"	   "=w")
++	(unspec:VDX [(match_operand:VDX 1 "memory_operand" " Um")]
++		    UNSPEC_MISALIGNED_ACCESS))]
++  "TARGET_NEON && !BYTES_BIG_ENDIAN"
++  "vld1.<V_sz_elem>\t{%P0}, %A1"
++  [(set_attr "neon_type" "neon_vld1_1_2_regs")])
++
++(define_insn "*movmisalign<mode>_neon_store"
++  [(set (match_operand:VQX 0 "memory_operand"		       "=Um")
++	(unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")]
++		    UNSPEC_MISALIGNED_ACCESS))]
++  "TARGET_NEON && !BYTES_BIG_ENDIAN"
++  "vst1.<V_sz_elem>\t{%q1}, %A0"
++  [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
++
++(define_insn "*movmisalign<mode>_neon_load"
++  [(set (match_operand:VQX 0 "s_register_operand"	   "=w")
++	(unspec:VQX [(match_operand:VQX 1 "memory_operand" " Um")]
++		    UNSPEC_MISALIGNED_ACCESS))]
++  "TARGET_NEON && !BYTES_BIG_ENDIAN"
++  "vld1.<V_sz_elem>\t{%q0}, %A1"
++  [(set_attr "neon_type" "neon_vld1_1_2_regs")])
++
+ (define_insn "vec_set<mode>_internal"
+   [(set (match_operand:VD 0 "s_register_operand" "=w")
+         (vec_merge:VD
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2010-08-12 13:51:16 +0000
++++ new/gcc/expr.c	2010-08-20 16:21:01 +0000
+@@ -4362,7 +4362,10 @@
+            && op_mode1 != VOIDmode)
+          reg = copy_to_mode_reg (op_mode1, reg);
+ 
+-      insn = GEN_FCN (icode) (mem, reg);
++       insn = GEN_FCN (icode) (mem, reg);
++       /* The movmisalign<mode> pattern cannot fail, else the assignment would
++          silently be omitted.  */
++       gcc_assert (insn != NULL_RTX);
+        emit_insn (insn);
+        return;
+      }
+@@ -8742,6 +8745,7 @@
+ 
+ 	    /* Nor can the insn generator.  */
+ 	    insn = GEN_FCN (icode) (reg, temp);
++	    gcc_assert (insn != NULL_RTX);
+ 	    emit_insn (insn);
+ 
+ 	    return reg;
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c	2009-06-05 14:28:50 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c	2010-08-20 16:21:01 +0000
+@@ -46,5 +46,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_hw_misalign } } } } } */
++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_element_align } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c	2008-08-18 19:36:03 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-25.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-25.c	2009-10-27 11:46:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-25.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-3.c	2009-05-12 13:05:28 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-3.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include <stdio.h>
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-109.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-109.c	2010-07-10 20:38:32 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-109.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+@@ -72,8 +73,8 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_hw_misalign } } } */
+-/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_hw_misalign } } } */
+-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_hw_misalign } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_element_align } } } */
++/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_element_align } } } */
++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_element_align } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-42.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-42.c	2009-11-04 10:22:22 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-42.c	2010-08-20 16:21:01 +0000
+@@ -64,7 +64,7 @@
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+ /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 3 "vect" { target vect_no_align } } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_hw_misalign } } } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_element_align } } } } } */
+ /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */
+ /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-95.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-95.c	2009-10-27 11:46:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-95.c	2010-08-20 16:21:01 +0000
+@@ -56,14 +56,14 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_hw_misalign} } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_element_align} } } } */
+ 
+ /* For targets that support unaligned loads we version for the two unaligned 
+    stores and generate misaligned accesses for the loads. For targets that 
+    don't support unaligned loads we version for all four accesses.  */
+ 
+-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign} } } }  */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align} } } }  */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
+ /*  { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target vect_no_align } } } */
+ /*  { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 4 "vect" { target vect_no_align } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-96.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-96.c	2009-10-27 11:46:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-96.c	2010-08-20 16:21:01 +0000
+@@ -45,5 +45,5 @@
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+ /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { target { {! vect_no_align} && vector_alignment_reachable } } } } */
+ /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align } || {! vector_alignment_reachable} } } } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_hw_misalign} } } } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_element_align} } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c	2009-10-27 11:46:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+@@ -78,11 +79,11 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
+ /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c	2009-10-27 11:46:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+@@ -85,11 +86,11 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign}  } } } */
+-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align}  } } } */
++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
+ /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 8 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */
++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_element_align } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c	2010-08-20 16:21:01 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options quad_vectors } */
+ 
+ #include <stdio.h>
+ #include <stdarg.h>
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2010-08-10 13:31:21 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2010-08-20 16:21:01 +0000
+@@ -1642,6 +1642,18 @@
+     }]
+ }
+ 
++# Return 1 if this is an ARM target that only supports aligned vector accesses
++proc check_effective_target_arm_vect_no_misalign { } {
++    return [check_no_compiler_messages arm_vect_no_misalign assembly {
++	#if !defined(__arm__) \
++	    || (defined(__ARMEL__) \
++	        && (!defined(__thumb__) || defined(__thumb2__)))
++	#error FOO
++	#endif
++    }]
++}
++
++
+ # Return 1 if this is an ARM target supporting -mfpu=vfp
+ # -mfloat-abi=softfp.  Some multilibs may be incompatible with these
+ # options.
+@@ -2547,7 +2559,7 @@
+ 	if { [istarget mipsisa64*-*-*]
+ 	     || [istarget sparc*-*-*]
+ 	     || [istarget ia64-*-*]
+-	     || [check_effective_target_arm32] } { 
++	     || [check_effective_target_arm_vect_no_misalign] } { 
+ 	    set et_vect_no_align_saved 1
+ 	}
+     }
+@@ -2682,6 +2694,25 @@
+     return $et_vector_alignment_reachable_for_64bit_saved
+ }
+ 
++# Return 1 if the target only requires element alignment for vector accesses
++
++proc check_effective_target_vect_element_align { } {
++    global et_vect_element_align
++
++    if [info exists et_vect_element_align] {
++	verbose "check_effective_target_vect_element_align: using cached result" 2
++    } else {
++	set et_vect_element_align 0
++	if { [istarget arm*-*-*]
++	     || [check_effective_target_vect_hw_misalign] } {
++	   set et_vect_element_align 1
++	}
++    }
++
++    verbose "check_effective_target_vect_element_align: returning $et_vect_element_align" 2
++    return $et_vect_element_align
++}
++
+ # Return 1 if the target supports vector conditional operations, 0 otherwise.
+ 
+ proc check_effective_target_vect_condition { } {
+@@ -3239,6 +3270,16 @@
+     return $flags
+ }
+ 
++# Add to FLAGS the flags needed to enable 128-bit vectors.
++
++proc add_options_for_quad_vectors { flags } {
++    if [is-effective-target arm_neon_ok] {
++	return "$flags -mvectorize-with-neon-quad"
++    }
++
++    return $flags
++}
++
+ # Return 1 if the target provides a full C99 runtime.
+ 
+ proc check_effective_target_c99_runtime { } {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch
new file mode 100644
index 0000000000..36a942118a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch
@@ -0,0 +1,38 @@
+2010-08-12  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/testsuite/
+	2010-08-12  Jie Zhang  <jie@codesourcery.com>
+	* gcc.dg/graphite/interchange-9.c (M): Define to be 111.
+	(N): Likewise.
+	(main): Adjust accordingly.
+
+ 2010-08-05  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Backport from mainline (candidate patch):
+
+=== modified file 'gcc/testsuite/gcc.dg/graphite/interchange-9.c'
+--- old/gcc/testsuite/gcc.dg/graphite/interchange-9.c	2010-02-07 19:49:26 +0000
++++ new/gcc/testsuite/gcc.dg/graphite/interchange-9.c	2010-08-20 16:32:45 +0000
+@@ -5,8 +5,8 @@
+ #include <stdio.h>
+ #endif
+ 
+-#define N 1111
+-#define M 1111
++#define N 111
++#define M 111
+ 
+ static int __attribute__((noinline))
+ foo (int *x)
+@@ -38,7 +38,7 @@
+   fprintf (stderr, "res = %d \n", res);
+ #endif
+ 
+-  if (res != 2468642)
++  if (res != 24642)
+     abort ();
+ 
+   return 0;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch
new file mode 100644
index 0000000000..0998c812e8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch
@@ -0,0 +1,26 @@
+2010-08-13  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/
+	2010-08-13  Jie Zhang  <jie@codesourcery.com>
+	* config/arm/arm.md (cstoredf4): Only valid when
+	!TARGET_VFP_SINGLE.
+
+ 2010-08-12  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-16 09:41:58 +0000
++++ new/gcc/config/arm/arm.md	2010-08-20 16:41:37 +0000
+@@ -8344,7 +8344,7 @@
+ 	(match_operator:SI 1 "arm_comparison_operator"
+ 	 [(match_operand:DF 2 "s_register_operand" "")
+ 	  (match_operand:DF 3 "arm_float_compare_operand" "")]))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+   "emit_insn (gen_cstore_cc (operands[0], operands[1],
+ 			     operands[2], operands[3])); DONE;"
+ )
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch
new file mode 100644
index 0000000000..2d572b1bb0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch
@@ -0,0 +1,49 @@
+2010-08-18  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/testsuite/
+	2010-08-18  Jie Zhang  <jie@codesourcery.com>
+	* gcc.dg/builtin-apply2.c (STACK_ARGUMENTS_SIZE): Define to
+	20 if __ARM_PCS is defined otherwise 64.
+	(bar): Use STACK_ARGUMENTS_SIZE for the third argument
+	instead of hard coded 64.
+
+ 2010-08-13  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/testsuite/gcc.dg/builtin-apply2.c'
+--- old/gcc/testsuite/gcc.dg/builtin-apply2.c	2009-08-06 13:27:45 +0000
++++ new/gcc/testsuite/gcc.dg/builtin-apply2.c	2010-08-23 13:59:02 +0000
+@@ -8,10 +8,19 @@
+ /* Verify that __builtin_apply behaves correctly on targets
+    with pre-pushed arguments (e.g. SPARC).  */
+ 
+-   
++
+ 
+ #define INTEGER_ARG  5
+ 
++#ifdef __ARM_PCS
++/* For Base AAPCS, NAME is passed in r0.  D is passed in r2 and r3.
++   E, F and G are passed on stack.  So the size of the stack argument
++   data is 20.  */
++#define STACK_ARGUMENTS_SIZE  20
++#else
++#define STACK_ARGUMENTS_SIZE  64
++#endif
++
+ extern void abort(void);
+ 
+ void foo(char *name, double d, double e, double f, int g)
+@@ -22,7 +31,7 @@
+ 
+ void bar(char *name, ...)
+ {
+-  __builtin_apply(foo, __builtin_apply_args(), 64);
++  __builtin_apply(foo, __builtin_apply_args(), STACK_ARGUMENTS_SIZE);
+ }
+ 
+ int main(void)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
new file mode 100644
index 0000000000..0705e4183f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
@@ -0,0 +1,342 @@
+2010-08-18  Julian Brown  <julian@codesourcery.com>
+
+	Issue #9222
+
+	gcc/
+	* config/arm/neon.md (UNSPEC_VCLE, UNSPEC_VCLT): New constants for
+	unspecs.
+	(vcond<mode>, vcondu<mode>): New expanders.
+	(neon_vceq<mode>, neon_vcge<mode>, neon_vcgt<mode>): Support
+	comparisons with zero.
+	(neon_vcle<mode>, neon_vclt<mode>): New patterns.
+	* config/arm/constraints.md (Dz): New constraint.
+
+ 2010-08-18  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/config/arm/constraints.md'
+Index: gcc-4.5/gcc/config/arm/constraints.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/constraints.md
++++ gcc-4.5/gcc/config/arm/constraints.md
+@@ -29,7 +29,7 @@
+ ;; in Thumb-1 state: I, J, K, L, M, N, O
+ 
+ ;; The following multi-letter normal constraints have been used:
+-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
++;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
+ ;; in Thumb-1 state: Pa, Pb
+ ;; in Thumb-2 state: Ps, Pt, Pv
+ 
+@@ -173,6 +173,12 @@
+  (and (match_code "const_double")
+       (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
+ 
++(define_constraint "Dz"
++ "@internal
++  In ARM/Thumb-2 state a vector of constant zeros."
++ (and (match_code "const_vector")
++      (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
++
+ (define_constraint "Da"
+  "@internal
+   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
+Index: gcc-4.5/gcc/config/arm/neon.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/neon.md
++++ gcc-4.5/gcc/config/arm/neon.md
+@@ -141,7 +141,9 @@
+    (UNSPEC_VUZP2		202)
+    (UNSPEC_VZIP1		203)
+    (UNSPEC_VZIP2		204)
+-   (UNSPEC_MISALIGNED_ACCESS	205)])
++   (UNSPEC_MISALIGNED_ACCESS	205)
++   (UNSPEC_VCLE			206)
++   (UNSPEC_VCLT			207)])
+ 
+ ;; Double-width vector modes.
+ (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
+@@ -1804,6 +1806,169 @@
+   [(set_attr "neon_type" "neon_int_5")]
+ )
+ 
++;; Conditional instructions.  These are comparisons with conditional moves for
++;; vectors.  They perform the assignment:
++;;   
++;;     Vop0 = (Vop4 <op3> Vop5) ? Vop1 : Vop2;
++;;
++;; where op3 is <, <=, ==, !=, >= or >.  Operations are performed
++;; element-wise.
++
++(define_expand "vcond<mode>"
++  [(set (match_operand:VDQW 0 "s_register_operand" "")
++	(if_then_else:VDQW
++	  (match_operator 3 "arm_comparison_operator"
++	    [(match_operand:VDQW 4 "s_register_operand" "")
++	     (match_operand:VDQW 5 "nonmemory_operand" "")])
++	  (match_operand:VDQW 1 "s_register_operand" "")
++	  (match_operand:VDQW 2 "s_register_operand" "")))]
++  "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
++{
++  rtx mask;
++  int inverse = 0, immediate_zero = 0;
++  /* See the description of "magic" bits in the 'T' case of
++     arm_print_operand.  */
++  HOST_WIDE_INT magic_word = (<MODE>mode == V2SFmode || <MODE>mode == V4SFmode)
++			     ? 3 : 1;
++  rtx magic_rtx = GEN_INT (magic_word);
++  
++  mask = gen_reg_rtx (<V_cmp_result>mode);
++  
++  if (operands[5] == CONST0_RTX (<MODE>mode))
++    immediate_zero = 1;
++  else if (!REG_P (operands[5]))
++    operands[5] = force_reg (<MODE>mode, operands[5]);
++  
++  switch (GET_CODE (operands[3]))
++    {
++    case GE:
++      emit_insn (gen_neon_vcge<mode> (mask, operands[4], operands[5],
++				      magic_rtx));
++      break;
++    
++    case GT:
++      emit_insn (gen_neon_vcgt<mode> (mask, operands[4], operands[5],
++				      magic_rtx));
++      break;
++    
++    case EQ:
++      emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
++				      magic_rtx));
++      break;
++    
++    case LE:
++      if (immediate_zero)
++	emit_insn (gen_neon_vcle<mode> (mask, operands[4], operands[5],
++					magic_rtx));
++      else
++	emit_insn (gen_neon_vcge<mode> (mask, operands[5], operands[4],
++					magic_rtx));
++      break;
++    
++    case LT:
++      if (immediate_zero)
++	emit_insn (gen_neon_vclt<mode> (mask, operands[4], operands[5],
++					magic_rtx));
++      else
++	emit_insn (gen_neon_vcgt<mode> (mask, operands[5], operands[4],
++					magic_rtx));
++      break;
++    
++    case NE:
++      emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
++				      magic_rtx));
++      inverse = 1;
++      break;
++    
++    default:
++      gcc_unreachable ();
++    }
++  
++  if (inverse)
++    emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[2],
++				    operands[1]));
++  else
++    emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[1],
++				    operands[2]));
++
++  DONE;
++})
++
++(define_expand "vcondu<mode>"
++  [(set (match_operand:VDQIW 0 "s_register_operand" "")
++	(if_then_else:VDQIW
++	  (match_operator 3 "arm_comparison_operator"
++	    [(match_operand:VDQIW 4 "s_register_operand" "")
++	     (match_operand:VDQIW 5 "s_register_operand" "")])
++	  (match_operand:VDQIW 1 "s_register_operand" "")
++	  (match_operand:VDQIW 2 "s_register_operand" "")))]
++  "TARGET_NEON"
++{
++  rtx mask;
++  int inverse = 0, immediate_zero = 0;
++  
++  mask = gen_reg_rtx (<V_cmp_result>mode);
++  
++  if (operands[5] == CONST0_RTX (<MODE>mode))
++    immediate_zero = 1;
++  else if (!REG_P (operands[5]))
++    operands[5] = force_reg (<MODE>mode, operands[5]);
++  
++  switch (GET_CODE (operands[3]))
++    {
++    case GEU:
++      emit_insn (gen_neon_vcge<mode> (mask, operands[4], operands[5],
++				      const0_rtx));
++      break;
++    
++    case GTU:
++      emit_insn (gen_neon_vcgt<mode> (mask, operands[4], operands[5],
++				      const0_rtx));
++      break;
++    
++    case EQ:
++      emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
++				      const0_rtx));
++      break;
++    
++    case LEU:
++      if (immediate_zero)
++	emit_insn (gen_neon_vcle<mode> (mask, operands[4], operands[5],
++					const0_rtx));
++      else
++	emit_insn (gen_neon_vcge<mode> (mask, operands[5], operands[4],
++					const0_rtx));
++      break;
++    
++    case LTU:
++      if (immediate_zero)
++        emit_insn (gen_neon_vclt<mode> (mask, operands[4], operands[5],
++					const0_rtx));
++      else
++	emit_insn (gen_neon_vcgt<mode> (mask, operands[5], operands[4],
++					const0_rtx));
++      break;
++    
++    case NE:
++      emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
++				      const0_rtx));
++      inverse = 1;
++      break;
++    
++    default:
++      gcc_unreachable ();
++    }
++  
++  if (inverse)
++    emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[2],
++				    operands[1]));
++  else
++    emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[1],
++				    operands[2]));
++
++  DONE;
++})
++
+ ;; Patterns for builtins.
+ 
+ ; good for plain vadd, vaddq.
+@@ -2215,13 +2380,16 @@
+ )
+ 
+ (define_insn "neon_vceq<mode>"
+-  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
+-        (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
+-		                (match_operand:VDQW 2 "s_register_operand" "w")
+-                                (match_operand:SI 3 "immediate_operand" "i")]
+-                               UNSPEC_VCEQ))]
++  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++        (unspec:<V_cmp_result>
++	  [(match_operand:VDQW 1 "s_register_operand" "w,w")
++	   (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
++	   (match_operand:SI 3 "immediate_operand" "i,i")]
++          UNSPEC_VCEQ))]
+   "TARGET_NEON"
+-  "vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  "@
++  vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
++  vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, #0"
+   [(set (attr "neon_type")
+       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+                     (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+@@ -2231,13 +2399,16 @@
+ )
+ 
+ (define_insn "neon_vcge<mode>"
+-  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
+-        (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
+-		                (match_operand:VDQW 2 "s_register_operand" "w")
+-                                (match_operand:SI 3 "immediate_operand" "i")]
+-                               UNSPEC_VCGE))]
++  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++        (unspec:<V_cmp_result>
++	  [(match_operand:VDQW 1 "s_register_operand" "w,w")
++	   (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
++	   (match_operand:SI 3 "immediate_operand" "i,i")]
++          UNSPEC_VCGE))]
+   "TARGET_NEON"
+-  "vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  "@
++  vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
++  vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
+   [(set (attr "neon_type")
+      (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+                    (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+@@ -2247,13 +2418,16 @@
+ )
+ 
+ (define_insn "neon_vcgt<mode>"
+-  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
+-        (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
+-		                (match_operand:VDQW 2 "s_register_operand" "w")
+-                                (match_operand:SI 3 "immediate_operand" "i")]
+-                               UNSPEC_VCGT))]
++  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++        (unspec:<V_cmp_result>
++	  [(match_operand:VDQW 1 "s_register_operand" "w,w")
++	   (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
++           (match_operand:SI 3 "immediate_operand" "i,i")]
++          UNSPEC_VCGT))]
+   "TARGET_NEON"
+-  "vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  "@
++  vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
++  vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
+   [(set (attr "neon_type")
+      (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+                    (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+@@ -2262,6 +2436,43 @@
+                    (const_string "neon_int_5")))]
+ )
+ 
++;; VCLE and VCLT only support comparisons with immediate zero (register
++;; variants are VCGE and VCGT with operands reversed).
++
++(define_insn "neon_vcle<mode>"
++  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
++        (unspec:<V_cmp_result>
++	  [(match_operand:VDQW 1 "s_register_operand" "w")
++	   (match_operand:VDQW 2 "nonmemory_operand" "Dz")
++	   (match_operand:SI 3 "immediate_operand" "i")]
++          UNSPEC_VCLE))]
++  "TARGET_NEON"
++  "vcle.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
++  [(set (attr "neon_type")
++      (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
++                    (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++                                  (const_string "neon_fp_vadd_ddd_vabs_dd")
++                                  (const_string "neon_fp_vadd_qqq_vabs_qq"))
++                    (const_string "neon_int_5")))]
++)
++
++(define_insn "neon_vclt<mode>"
++  [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
++        (unspec:<V_cmp_result>
++	  [(match_operand:VDQW 1 "s_register_operand" "w")
++	   (match_operand:VDQW 2 "nonmemory_operand" "Dz")
++	   (match_operand:SI 3 "immediate_operand" "i")]
++          UNSPEC_VCLT))]
++  "TARGET_NEON"
++  "vclt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
++  [(set (attr "neon_type")
++      (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
++                    (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++                                  (const_string "neon_fp_vadd_ddd_vabs_dd")
++                                  (const_string "neon_fp_vadd_qqq_vabs_qq"))
++                    (const_string "neon_int_5")))]
++)
++
+ (define_insn "neon_vcage<mode>"
+   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
+         (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch
new file mode 100644
index 0000000000..9bbc020629
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch
@@ -0,0 +1,53 @@
+2010-08-20  Jie Zhang  <jie@codesourcery.com>
+
+	Merged from Sourcery G++ 4.4:
+
+	gcc/
+	2009-05-29  Julian Brown  <julian@codesourcery.com>
+	Merged from Sourcery G++ 4.3:
+	* config/arm/arm.md (movsi): Don't split symbol refs here.
+	(define_split): New.
+
+ 2010-08-18  Julian Brown  <julian@codesourcery.com>
+ 
+ 	Issue #9222
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-20 16:41:37 +0000
++++ new/gcc/config/arm/arm.md	2010-08-23 14:39:12 +0000
+@@ -5150,14 +5150,6 @@
+ 			       optimize && can_create_pseudo_p ());
+           DONE;
+         }
+-
+-      if (TARGET_USE_MOVT && !target_word_relocations
+-	  && GET_CODE (operands[1]) == SYMBOL_REF
+-	  && !flag_pic && !arm_tls_referenced_p (operands[1]))
+-	{
+-	  arm_emit_movpair (operands[0], operands[1]);
+-	  DONE;
+-	}
+     }
+   else /* TARGET_THUMB1...  */
+     {
+@@ -5265,6 +5257,19 @@
+   "
+ )
+ 
++(define_split
++  [(set (match_operand:SI 0 "arm_general_register_operand" "")
++	(match_operand:SI 1 "general_operand" ""))]
++  "TARGET_32BIT
++   && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
++   && !flag_pic && !target_word_relocations
++   && !arm_tls_referenced_p (operands[1])"
++  [(clobber (const_int 0))]
++{
++  arm_emit_movpair (operands[0], operands[1]);
++  DONE;
++})
++
+ (define_insn "*thumb1_movsi_insn"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk")
+ 	(match_operand:SI 1 "general_operand"      "l, I,J,K,>,l,mi,l,*lhk"))]
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch
new file mode 100644
index 0000000000..be102160c5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch
@@ -0,0 +1,663 @@
+2010-08-24  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2010-08-07  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/arm/cortex-a9.md: Rewrite VFP Pipeline description.
+	* config/arm/arm.c (arm_xscale_tune): Initialize sched_adjust_cost.
+	 (arm_fastmul_tune,arm_slowmul_tune, arm_9e_tune): Likewise.
+	 (arm_adjust_cost): Split into xscale_sched_adjust_cost and a
+	 generic part.
+	 (cortex_a9_sched_adjust_cost): New function.
+	 (xscale_sched_adjust_cost): New function.
+	* config/arm/arm-protos.h (struct tune_params): New field
+	sched_adjust_cost.
+	* config/arm/arm-cores.def: Adjust costs for cortex-a9.
+
+	2010-04-17  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-protos.h (tune_params): New structure.
+	* arm.c (current_tune): New variable.
+	(arm_constant_limit): Delete.
+	(struct processors): Add pointer to the tune parameters.
+	(arm_slowmul_tune): New tuning option.
+	(arm_fastmul_tune, arm_xscale_tune, arm_9e_tune): Likewise.
+	(all_cores): Adjust to pick up the tuning model.
+	(arm_constant_limit): New function.
+	(arm_override_options): Select the appropriate tuning model.  Delete
+	initialization of arm_const_limit.
+	(arm_split_constant): Use the new constant-limit model.
+	(arm_rtx_costs): Pick up the current tuning model.
+	* arm.md (is_strongarm, is_xscale): Delete.
+	* arm-generic.md (load_ldsched_x, load_ldsched): Test explicitly
+	for Xscale variant architectures.
+	(mult_ldsched_strongarm, mult_ldsched): Similarly for StrongARM.
+
+ 2010-08-23  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from FSF:
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2010-07-29 15:53:39 +0000
++++ new/gcc/config/arm/arm-cores.def	2010-08-24 13:15:54 +0000
+@@ -120,7 +120,7 @@
+ ARM_CORE("arm1156t2f-s",  arm1156t2fs,  6T2,				 FL_LDSCHED | FL_VFPV2, 9e)
+ ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, 9e)
++ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
+ ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, 9e)
+ ARM_CORE("cortex-m4",	  cortexm4,	7EM,				 FL_LDSCHED, 9e)
+
+=== modified file 'gcc/config/arm/arm-generic.md'
+--- old/gcc/config/arm/arm-generic.md	2007-08-02 09:49:31 +0000
++++ new/gcc/config/arm/arm-generic.md	2010-08-24 13:15:54 +0000
+@@ -104,14 +104,14 @@
+   (and (eq_attr "generic_sched" "yes")
+        (and (eq_attr "ldsched" "yes") 
+ 	    (and (eq_attr "type" "load_byte,load1")
+-	         (eq_attr "is_xscale" "yes"))))
++	         (eq_attr "tune" "xscale,iwmmxt,iwmmxt2"))))
+   "core")
+ 
+ (define_insn_reservation "load_ldsched" 2
+   (and (eq_attr "generic_sched" "yes")
+        (and (eq_attr "ldsched" "yes") 
+ 	    (and (eq_attr "type" "load_byte,load1")
+-	         (eq_attr "is_xscale" "no"))))
++	         (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2"))))
+   "core")
+ 
+ (define_insn_reservation "load_or_store" 2
+@@ -128,14 +128,16 @@
+ (define_insn_reservation "mult_ldsched_strongarm" 3
+   (and (eq_attr "generic_sched" "yes")
+        (and (eq_attr "ldsched" "yes") 
+-	    (and (eq_attr "is_strongarm" "yes")
++	    (and (eq_attr "tune"
++		  "strongarm,strongarm110,strongarm1100,strongarm1110")
+ 	         (eq_attr "type" "mult"))))
+   "core*2")
+ 
+ (define_insn_reservation "mult_ldsched" 4
+   (and (eq_attr "generic_sched" "yes")
+        (and (eq_attr "ldsched" "yes") 
+-	    (and (eq_attr "is_strongarm" "no")
++	    (and (eq_attr "tune"
++		  "!strongarm,strongarm110,strongarm1100,strongarm1110")
+ 	         (eq_attr "type" "mult"))))
+   "core*4")
+ 
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2010-08-10 13:31:21 +0000
++++ new/gcc/config/arm/arm-protos.h	2010-08-24 13:15:54 +0000
+@@ -214,4 +214,17 @@
+ 
+ extern void arm_order_regs_for_local_alloc (void);
+ 
++#ifdef RTX_CODE
++/* This needs to be here because we need RTX_CODE and similar.  */
++
++struct tune_params
++{
++  bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
++  bool (*sched_adjust_cost) (rtx, rtx, rtx, int *);
++  int constant_limit;
++};
++
++extern const struct tune_params *current_tune;
++#endif /* RTX_CODE */
++
+ #endif /* ! GCC_ARM_PROTOS_H */
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-20 16:21:01 +0000
++++ new/gcc/config/arm/arm.c	2010-08-24 13:15:54 +0000
+@@ -228,6 +228,8 @@
+ static void arm_trampoline_init (rtx, tree, rtx);
+ static rtx arm_trampoline_adjust_address (rtx);
+ static rtx arm_pic_static_addr (rtx orig, rtx reg);
++static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
++static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
+ static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
+ static bool arm_builtin_support_vector_misalignment (enum machine_mode mode,
+ 						     const_tree type,
+@@ -545,6 +547,9 @@
+ /* The processor for which instructions should be scheduled.  */
+ enum processor_type arm_tune = arm_none;
+ 
++/* The current tuning set.  */
++const struct tune_params *current_tune;
++
+ /* The default processor used if not overridden by commandline.  */
+ static enum processor_type arm_default_cpu = arm_none;
+ 
+@@ -720,9 +725,6 @@
+    the next function.  */
+ static int after_arm_reorg = 0;
+ 
+-/* The maximum number of insns to be used when loading a constant.  */
+-static int arm_constant_limit = 3;
+-
+ enum arm_pcs arm_pcs_default;
+ 
+ /* For an explanation of these variables, see final_prescan_insn below.  */
+@@ -761,8 +763,44 @@
+   enum processor_type core;
+   const char *arch;
+   const unsigned long flags;
+-  bool (* rtx_costs) (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-};
++  const struct tune_params *const tune;
++};
++
++const struct tune_params arm_slowmul_tune =
++{
++  arm_slowmul_rtx_costs,
++  NULL,
++  3
++};
++
++const struct tune_params arm_fastmul_tune =
++{
++  arm_fastmul_rtx_costs,
++  NULL,
++  1
++};
++
++const struct tune_params arm_xscale_tune =
++{
++  arm_xscale_rtx_costs,
++  xscale_sched_adjust_cost,
++  2
++};
++
++const struct tune_params arm_9e_tune =
++{
++  arm_9e_rtx_costs,
++  NULL,
++  1
++};
++
++const struct tune_params arm_cortex_a9_tune =
++{
++  arm_9e_rtx_costs,
++  cortex_a9_sched_adjust_cost,
++  1
++};
++
+ 
+ /* Not all of these give usefully different compilation alternatives,
+    but there is no simple way of generalizing them.  */
+@@ -770,7 +808,7 @@
+ {
+   /* ARM Cores */
+ #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
+-  {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
++  {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
+ #include "arm-cores.def"
+ #undef ARM_CORE
+   {NULL, arm_none, NULL, 0, NULL}
+@@ -779,7 +817,7 @@
+ static const struct processors all_architectures[] =
+ {
+   /* ARM Architectures */
+-  /* We don't specify rtx_costs here as it will be figured out
++  /* We don't specify tuning costs here as it will be figured out
+      from the core.  */
+ 
+   {"armv2",   arm2,       "2",   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
+@@ -928,6 +966,13 @@
+   TLS_LE32
+ };
+ 
++/* The maximum number of insns to be used when loading a constant.  */
++inline static int
++arm_constant_limit (bool size_p)
++{
++  return size_p ? 1 : current_tune->constant_limit;
++}
++
+ /* Emit an insn that's a simple single-set.  Both the operands must be known
+    to be valid.  */
+ inline static rtx
+@@ -1478,6 +1523,7 @@
+     }
+ 
+   tune_flags = all_cores[(int)arm_tune].flags;
++  current_tune = all_cores[(int)arm_tune].tune;
+ 
+   if (target_fp16_format_name)
+     {
+@@ -1875,26 +1921,12 @@
+ 
+   if (optimize_size)
+     {
+-      arm_constant_limit = 1;
+-
+       /* If optimizing for size, bump the number of instructions that we
+          are prepared to conditionally execute (even on a StrongARM).  */
+       max_insns_skipped = 6;
+     }
+   else
+     {
+-      /* For processors with load scheduling, it never costs more than
+-         2 cycles to load a constant, and the load scheduler may well
+-	 reduce that to 1.  */
+-      if (arm_ld_sched)
+-        arm_constant_limit = 1;
+-
+-      /* On XScale the longer latency of a load makes it more difficult
+-         to achieve a good schedule, so it's faster to synthesize
+-	 constants that can be done in two insns.  */
+-      if (arm_tune_xscale)
+-        arm_constant_limit = 2;
+-
+       /* StrongARM has early execution of branches, so a sequence
+          that is worth skipping is shorter.  */
+       if (arm_tune_strongarm)
+@@ -2423,7 +2455,8 @@
+ 	  && !cond
+ 	  && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
+ 				1, 0)
+-	      > arm_constant_limit + (code != SET)))
++	      > (arm_constant_limit (optimize_function_for_size_p (cfun))
++		 + (code != SET))))
+ 	{
+ 	  if (code == SET)
+ 	    {
+@@ -7771,9 +7804,9 @@
+ 				   (enum rtx_code) outer_code, total);
+     }
+   else
+-    return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code,
+-					       (enum rtx_code) outer_code,
+-					       total, speed);
++    return current_tune->rtx_costs (x, (enum rtx_code) code,
++				    (enum rtx_code) outer_code,
++				    total, speed);
+ }
+ 
+ /* RTX costs for cores with a slow MUL implementation.  Thumb-2 is not
+@@ -7918,7 +7951,8 @@
+    so it can be ignored.  */
+ 
+ static bool
+-arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, int *total, bool speed)
++arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
++		      int *total, bool speed)
+ {
+   enum machine_mode mode = GET_MODE (x);
+ 
+@@ -8119,15 +8153,15 @@
+   return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
+ }
+ 
+-static int
+-arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
++/* Adjust cost hook for XScale.  */
++static bool
++xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
+ {
+   rtx i_pat, d_pat;
+ 
+   /* Some true dependencies can have a higher cost depending
+      on precisely how certain input operands are used.  */
+-  if (arm_tune_xscale
+-      && REG_NOTE_KIND (link) == 0
++  if (REG_NOTE_KIND (link) == 0
+       && recog_memoized (insn) >= 0
+       && recog_memoized (dep) >= 0)
+     {
+@@ -8161,10 +8195,106 @@
+ 
+ 	      if (reg_overlap_mentioned_p (recog_data.operand[opno],
+ 					   shifted_operand))
+-		return 2;
++		{
++		  *cost = 2;
++		  return false;
++		}
+ 	    }
+ 	}
+     }
++  return true;
++}
++
++/* Adjust cost hook for Cortex A9.  */
++static bool
++cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
++{
++  switch (REG_NOTE_KIND (link))
++    {
++    case REG_DEP_ANTI:
++      *cost = 0;
++      return false;
++
++    case REG_DEP_TRUE:
++    case REG_DEP_OUTPUT:
++	if (recog_memoized (insn) >= 0
++	    && recog_memoized (dep) >= 0)
++	  {
++	    if (GET_CODE (PATTERN (insn)) == SET)
++	      {
++		if (GET_MODE_CLASS 
++		    (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT
++		  || GET_MODE_CLASS 
++		    (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
++		  {
++		    enum attr_type attr_type_insn = get_attr_type (insn);
++		    enum attr_type attr_type_dep = get_attr_type (dep);
++
++		    /* By default all dependencies of the form
++		       s0 = s0 <op> s1
++		       s0 = s0 <op> s2
++		       have an extra latency of 1 cycle because
++		       of the input and output dependency in this
++		       case. However this gets modeled as an true
++		       dependency and hence all these checks.  */
++		    if (REG_P (SET_DEST (PATTERN (insn)))
++			&& REG_P (SET_DEST (PATTERN (dep)))
++			&& reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)),
++						    SET_DEST (PATTERN (dep))))
++		      {
++			/* FMACS is a special case where the dependant
++			   instruction can be issued 3 cycles before
++			   the normal latency in case of an output 
++			   dependency.  */
++			if ((attr_type_insn == TYPE_FMACS
++			     || attr_type_insn == TYPE_FMACD)
++			    && (attr_type_dep == TYPE_FMACS
++				|| attr_type_dep == TYPE_FMACD))
++			  {
++			    if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
++			      *cost = insn_default_latency (dep) - 3;
++			    else
++			      *cost = insn_default_latency (dep);
++			    return false;
++			  }
++			else
++			  {
++			    if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
++			      *cost = insn_default_latency (dep) + 1;
++			    else
++			      *cost = insn_default_latency (dep);
++			  }
++			return false;
++		      }
++		  }
++	      }
++	  }
++	break;
++
++    default:
++      gcc_unreachable ();
++    }
++
++  return true;
++}
++
++/* This function implements the target macro TARGET_SCHED_ADJUST_COST.
++   It corrects the value of COST based on the relationship between
++   INSN and DEP through the dependence LINK.  It returns the new
++   value. There is a per-core adjust_cost hook to adjust scheduler costs
++   and the per-core hook can choose to completely override the generic 
++   adjust_cost function. Only put bits of code into arm_adjust_cost that 
++   are common across all cores.  */
++static int
++arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
++{
++  rtx i_pat, d_pat;
++
++  if (current_tune->sched_adjust_cost != NULL)
++    {
++      if (!current_tune->sched_adjust_cost (insn, link, dep, &cost))
++	return cost;
++    }
+ 
+   /* XXX This is not strictly true for the FPA.  */
+   if (REG_NOTE_KIND (link) == REG_DEP_ANTI
+@@ -8187,7 +8317,8 @@
+ 	 constant pool are cached, and that others will miss.  This is a
+ 	 hack.  */
+ 
+-      if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
++      if ((GET_CODE (src_mem) == SYMBOL_REF 
++	   && CONSTANT_POOL_ADDRESS_P (src_mem))
+ 	  || reg_mentioned_p (stack_pointer_rtx, src_mem)
+ 	  || reg_mentioned_p (frame_pointer_rtx, src_mem)
+ 	  || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-23 14:39:12 +0000
++++ new/gcc/config/arm/arm.md	2010-08-24 13:15:54 +0000
+@@ -150,13 +150,6 @@
+ ; patterns that share the same RTL in both ARM and Thumb code.
+ (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))
+ 
+-; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
+-; scheduling decisions for the load unit and the multiplier.
+-(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm")))
+-
+-; IS_XSCALE is set to 'yes' when compiling for XScale.
+-(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
+-
+ ;; Operand number of an input operand that is shifted.  Zero if the
+ ;; given instruction does not shift one of its input operands.
+ (define_attr "shift" "" (const_int 0))
+
+=== modified file 'gcc/config/arm/cortex-a9.md'
+--- old/gcc/config/arm/cortex-a9.md	2009-10-31 16:40:03 +0000
++++ new/gcc/config/arm/cortex-a9.md	2010-08-24 13:15:54 +0000
+@@ -2,8 +2,10 @@
+ ;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+ ;; Originally written by CodeSourcery for VFP.
+ ;;
+-;; Integer core pipeline description contributed by ARM Ltd.
+-;;
++;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
++;; Integer Pipeline description contributed by ARM Ltd.
++;; VFP Pipeline description rewritten and contributed by ARM Ltd.
++
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify it
+@@ -22,28 +24,27 @@
+ 
+ (define_automaton "cortex_a9")
+ 
+-;; The Cortex-A9 integer core is modelled as a dual issue pipeline that has
++;; The Cortex-A9 core is modelled as a dual issue pipeline that has
+ ;; the following components.
+ ;; 1. 1 Load Store Pipeline.
+ ;; 2. P0 / main pipeline for data processing instructions.
+ ;; 3. P1 / Dual pipeline for Data processing instructions.
+ ;; 4. MAC pipeline for multiply as well as multiply
+ ;;    and accumulate instructions.
+-;; 5. 1 VFP / Neon pipeline.
+-;; The Load/Store and VFP/Neon pipeline are multiplexed.
++;; 5. 1 VFP and an optional Neon unit.
++;; The Load/Store, VFP and Neon issue pipeline are multiplexed.
+ ;; The P0 / main pipeline and M1 stage of the MAC pipeline are
+ ;;   multiplexed.
+ ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are
+ ;;   multiplexed.
+-;; There are only 4 register read ports and hence at any point of
++;; There are only 4 integer register read ports and hence at any point of
+ ;; time we can't have issue down the E1 and the E2 ports unless
+ ;; of course there are bypass paths that get exercised.
+ ;; Both P0 and P1 have 2 stages E1 and E2.
+ ;; Data processing instructions issue to E1 or E2 depending on
+ ;; whether they have an early shift or not.
+ 
+-
+-(define_cpu_unit "cortex_a9_vfp, cortex_a9_ls" "cortex_a9")
++(define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9")
+ (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9")
+ (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9")
+ (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9")
+@@ -71,11 +72,7 @@
+ 
+ ;; Issue at the same time along the load store pipeline and
+ ;; the VFP / Neon pipeline is not possible.
+-;; FIXME:: At some point we need to model the issue
+-;; of the load store and the vfp being shared rather than anything else.
+-
+-(exclusion_set "cortex_a9_ls" "cortex_a9_vfp")
+-
++(exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon")
+ 
+ ;; Default data processing instruction without any shift
+ ;; The only exception to this is the mov instruction
+@@ -101,18 +98,13 @@
+ 
+ (define_insn_reservation "cortex_a9_load1_2" 4
+   (and (eq_attr "tune" "cortexa9")
+-       (eq_attr "type" "load1, load2, load_byte"))
++       (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd"))
+   "cortex_a9_ls")
+ 
+ ;; Loads multiples and store multiples can't be issued for 2 cycles in a
+ ;; row. The description below assumes that addresses are 64 bit aligned.
+ ;; If not, there is an extra cycle latency which is not modelled.
+ 
+-;; FIXME:: This bit might need to be reworked when we get to
+-;; tuning for the VFP because strictly speaking the ldm
+-;; is sent to the LSU unit as is and there is only an
+-;; issue restriction between the LSU and the VFP/ Neon unit.
+-
+ (define_insn_reservation "cortex_a9_load3_4" 5
+   (and (eq_attr "tune" "cortexa9")
+        (eq_attr "type" "load3, load4"))
+@@ -120,12 +112,13 @@
+ 
+ (define_insn_reservation "cortex_a9_store1_2" 0
+   (and (eq_attr "tune" "cortexa9")
+-       (eq_attr "type" "store1, store2"))
++       (eq_attr "type" "store1, store2, f_stores, f_stored"))
+   "cortex_a9_ls")
+ 
+ ;; Almost all our store multiples use an auto-increment
+ ;; form. Don't issue back to back load and store multiples
+ ;; because the load store unit will stall.
++
+ (define_insn_reservation "cortex_a9_store3_4" 0
+   (and (eq_attr "tune" "cortexa9")
+        (eq_attr "type" "store3, store4"))
+@@ -193,47 +186,79 @@
+ (define_insn_reservation "cortex_a9_call"  0
+   (and (eq_attr "tune" "cortexa9")
+        (eq_attr "type" "call"))
+-  "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + cortex_a9_vfp")
++  "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon")
+ 
+ 
+ ;; Pipelining for VFP instructions.
+-
+-(define_insn_reservation "cortex_a9_ffarith" 1
++;; Issue happens either along load store unit or the VFP / Neon unit.
++;; Pipeline   Instruction Classification.
++;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
++;; FP_ADD   - fadds, faddd, fcmps (1)
++;; FPMUL   - fmul{s,d}, fmac{s,d}
++;; FPDIV - fdiv{s,d}
++(define_cpu_unit "ca9fps" "cortex_a9")
++(define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9")
++(define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9")
++(define_cpu_unit "ca9fp_ds1" "cortex_a9")
++
++
++;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
++(define_insn_reservation "cortex_a9_fps" 2
+  (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd,fconsts,fconstd"))
+- "cortex_a9_vfp")
++      (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag"))
++ "ca9_issue_vfp_neon + ca9fps")
++
++(define_bypass 1
++  "cortex_a9_fps"
++  "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply")
++
++;; Scheduling on the FP_ADD pipeline.
++(define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
+ 
+ (define_insn_reservation "cortex_a9_fadd" 4
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fadds,faddd,f_cvt"))
+- "cortex_a9_vfp")
+-
+-(define_insn_reservation "cortex_a9_fmuls" 5
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fmuls"))
+- "cortex_a9_vfp")
+-
+-(define_insn_reservation "cortex_a9_fmuld" 6
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fmuld"))
+- "cortex_a9_vfp*2")
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fadds, faddd, f_cvt"))
++  "ca9fp_add")
++
++(define_insn_reservation "cortex_a9_fcmp" 1
++  (and (eq_attr "tune" "cortexa9")
++      (eq_attr "type" "fcmps, fcmpd"))
++ "ca9_issue_vfp_neon + ca9fp_add1")
++
++;; Scheduling for the Multiply and MAC instructions.
++(define_reservation "ca9fmuls"
++  "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
++
++(define_reservation "ca9fmuld"
++  "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
++
++(define_insn_reservation "cortex_a9_fmuls" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fmuls"))
++  "ca9fmuls")
++
++(define_insn_reservation "cortex_a9_fmuld" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fmuld"))
++  "ca9fmuld")
+ 
+ (define_insn_reservation "cortex_a9_fmacs" 8
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fmacs"))
+- "cortex_a9_vfp")
+-
+-(define_insn_reservation "cortex_a9_fmacd" 8
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fmacd"))
+- "cortex_a9_vfp*2")
+-
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fmacs"))
++  "ca9fmuls, ca9fp_add")
++
++(define_insn_reservation "cortex_a9_fmacd" 9
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fmacd"))
++  "ca9fmuld, ca9fp_add")
++
++;; Division pipeline description.
+ (define_insn_reservation "cortex_a9_fdivs" 15
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fdivs"))
+- "cortex_a9_vfp*10")
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fdivs"))
++  "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14")
+ 
+ (define_insn_reservation "cortex_a9_fdivd" 25
+- (and (eq_attr "tune" "cortexa9")
+-      (eq_attr "type" "fdivd"))
+- "cortex_a9_vfp*20")
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "type" "fdivd"))
++  "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch
new file mode 100644
index 0000000000..03b478b798
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch
@@ -0,0 +1,380 @@
+2010-08-25  Andrew Stubbs  <ams@codesourcery.com>
+
+	Revert:
+
+	2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+	
+	2010-04-11  Julian Brown  <julian@codesourcery.com>
+
+	Issue #7326
+
+	gcc/
+	* config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
+	* config/arm/arm.md (generic_sched): No for Cortex-A5.
+	(generic_vfp): Likewise.
+	(cortex-a5.md): Include.
+	* config/arm/cortex-a5.md: New.
+
+ 2010-08-24  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from FSF:
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-24 13:15:54 +0000
++++ new/gcc/config/arm/arm.c	2010-08-25 16:20:13 +0000
+@@ -22472,7 +22472,6 @@
+     {
+     case cortexr4:
+     case cortexr4f:
+-    case cortexa5:
+     case cortexa8:
+     case cortexa9:
+       return 2;
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-24 13:15:54 +0000
++++ new/gcc/config/arm/arm.md	2010-08-25 16:20:13 +0000
+@@ -412,7 +412,7 @@
+ 
+ (define_attr "generic_sched" "yes,no"
+   (const (if_then_else 
+-          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
++          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
+ 	      (eq_attr "tune_cortexr4" "yes"))
+           (const_string "no")
+           (const_string "yes"))))
+@@ -420,7 +420,7 @@
+ (define_attr "generic_vfp" "yes,no"
+   (const (if_then_else
+ 	  (and (eq_attr "fpu" "vfp")
+-	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
++	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
+ 	       (eq_attr "tune_cortexr4" "no"))
+ 	  (const_string "yes")
+ 	  (const_string "no"))))
+@@ -444,7 +444,6 @@
+ (include "arm1020e.md")
+ (include "arm1026ejs.md")
+ (include "arm1136jfs.md")
+-(include "cortex-a5.md")
+ (include "cortex-a8.md")
+ (include "cortex-a9.md")
+ (include "cortex-r4.md")
+
+=== removed file 'gcc/config/arm/cortex-a5.md'
+--- old/gcc/config/arm/cortex-a5.md	2010-08-13 15:15:12 +0000
++++ new/gcc/config/arm/cortex-a5.md	1970-01-01 00:00:00 +0000
+@@ -1,310 +0,0 @@
+-;; ARM Cortex-A5 pipeline description
+-;; Copyright (C) 2010 Free Software Foundation, Inc.
+-;; Contributed by CodeSourcery.
+-;;
+-;; This file is part of GCC.
+-;;
+-;; GCC is free software; you can redistribute it and/or modify it
+-;; under the terms of the GNU General Public License as published by
+-;; the Free Software Foundation; either version 3, or (at your option)
+-;; any later version.
+-;;
+-;; GCC is distributed in the hope that it will be useful, but
+-;; WITHOUT ANY WARRANTY; without even the implied warranty of
+-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-;; General Public License for more details.
+-;;
+-;; You should have received a copy of the GNU General Public License
+-;; along with GCC; see the file COPYING3.  If not see
+-;; <http://www.gnu.org/licenses/>.
+-
+-(define_automaton "cortex_a5")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; Functional units.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-;; The integer (ALU) pipeline.  There are five DPU pipeline stages. However the
+-;; decode/issue stages operate the same for all instructions, so do not model
+-;; them.  We only need to model the first execute stage because instructions
+-;; always advance one stage per cycle in order. Only branch instructions may
+-;; dual-issue, so a single unit  covers all of the LS, ALU, MAC and FPU
+-;; pipelines.
+-
+-(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
+-
+-;; The branch pipeline.  Branches can dual-issue with other instructions
+-;; (except when those instructions take multiple cycles to issue).
+-
+-(define_cpu_unit "cortex_a5_branch" "cortex_a5")
+-
+-;; Pseudo-unit for blocking the multiply pipeline when a double-precision
+-;; multiply is in progress.
+-
+-(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
+-
+-;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
+-;; of the add pipeline by fmac instructions, etc.
+-
+-(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
+-
+-;; Floating-point div/sqrt (long latency, out-of-order completion).
+-
+-(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; ALU instructions.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-(define_insn_reservation "cortex_a5_alu" 2
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "alu"))
+-  "cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_alu_shift" 2
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+-  "cortex_a5_ex1")
+-
+-;; Forwarding path for unshifted operands.
+-
+-(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
+-  "cortex_a5_alu")
+-
+-(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
+-  "cortex_a5_alu_shift"
+-  "arm_no_early_alu_shift_dep")
+-
+-;; The multiplier pipeline can forward results from wr stage only (so I don't
+-;; think there's any need to specify bypasses).
+-
+-(define_insn_reservation "cortex_a5_mul" 2
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "mult"))
+-  "cortex_a5_ex1")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; Load/store instructions.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-;; Address-generation happens in the issue stage, which is one stage behind
+-;; the ex1 stage (the first stage we care about for scheduling purposes). The
+-;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
+-
+-;; FIXME: These might not be entirely accurate for load2, load3, load4. I think
+-;; they make sense since there's a 32-bit interface between the DPU and the DCU,
+-;; so we can't load more than that per cycle.  The store2, store3, store4
+-;; reservations are similarly guessed.
+-
+-(define_insn_reservation "cortex_a5_load1" 2
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "load_byte,load1"))
+-  "cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_store1" 0
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "store1"))
+-  "cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_load2" 3
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "load2"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_store2" 0
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "store2"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_load3" 4
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "load3"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+-   cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_store3" 0
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "store3"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+-   cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_load4" 5
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "load3"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+-   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_store4" 0
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "store3"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+-   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; Branches.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-;; Direct branches are the only instructions we can dual-issue (also IT and
+-;; nop, but those aren't very interesting for scheduling).  (The latency here
+-;; is meant to represent when the branch actually takes place, but may not be
+-;; entirely correct.)
+-
+-(define_insn_reservation "cortex_a5_branch" 3
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "branch,call"))
+-  "cortex_a5_branch")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; Floating-point arithmetic.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-(define_insn_reservation "cortex_a5_fpalu" 4
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
+-			fcmps, fcmpd"))
+-  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
+-
+-;; For fconsts and fconstd, 8-bit immediate data is passed directly from
+-;; f1 to f3 (which I think reduces the latency by one cycle).
+-
+-(define_insn_reservation "cortex_a5_fconst" 3
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fconsts,fconstd"))
+-  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
+-
+-;; We should try not to attempt to issue a single-precision multiplication in
+-;; the middle of a double-precision multiplication operation (the usage of
+-;; cortex_a5_fpmul_pipe).
+-
+-(define_insn_reservation "cortex_a5_fpmuls" 4
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fmuls"))
+-  "cortex_a5_ex1+cortex_a5_fpmul_pipe")
+-
+-;; For single-precision multiply-accumulate, the add (accumulate) is issued
+-;; whilst the multiply is in F4.  The multiply result can then be forwarded
+-;; from F5 to F1.  The issue unit is only used once (when we first start
+-;; processing the instruction), but the usage of the FP add pipeline could
+-;; block other instructions attempting to use it simultaneously.  We try to
+-;; avoid that using cortex_a5_fpadd_pipe.
+-
+-(define_insn_reservation "cortex_a5_fpmacs" 8
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fmacs"))
+-  "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
+-
+-;; Non-multiply instructions can issue in the middle two instructions of a
+-;; double-precision multiply.  Note that it isn't entirely clear when a branch
+-;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
+-;; that for now though.
+-
+-(define_insn_reservation "cortex_a5_fpmuld" 7
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fmuld"))
+-  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
+-   cortex_a5_ex1+cortex_a5_fpmul_pipe")
+-
+-(define_insn_reservation "cortex_a5_fpmacd" 11
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fmacd"))
+-  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
+-   cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; Floating-point divide/square root instructions.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
+-;; includes the time taken for the special instruction used to collect the
+-;; result to travel down the multiply pipeline, or not.  Assuming so.  (If
+-;; that's wrong, the latency should be increased by a few cycles.)
+-
+-;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
+-;; multiply pipeline to collect the divide/square-root result.
+-
+-(define_insn_reservation "cortex_a5_fdivs" 14
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fdivs"))
+-  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
+-
+-;; ??? Similarly for fdivd.
+-
+-(define_insn_reservation "cortex_a5_fdivd" 29
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "fdivd"))
+-  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; VFP to/from core transfers.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-;; FP loads take data from wr/rot/f3.  Might need to define bypasses to model
+-;; this?
+-
+-;; Core-to-VFP transfers use the multiply pipeline.
+-;; Not sure about this at all... I think we need some bypasses too.
+-
+-(define_insn_reservation "cortex_a5_r2f" 4
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "r_2_f"))
+-  "cortex_a5_ex1")
+-
+-;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used
+-;; for store and FP->core register transfers can forward into the F2 and F3
+-;; stages."
+-;; This doesn't correspond to what we have though.
+-
+-(define_insn_reservation "cortex_a5_f2r" 2
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "f_2_r"))
+-  "cortex_a5_ex1")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; VFP flag transfer.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU
+-;; specification (from fmstat to the ex2 stage of the second instruction) is
+-;; not modeled at present.
+-
+-(define_insn_reservation "cortex_a5_f_flags" 4
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "f_flag"))
+-  "cortex_a5_ex1")
+-
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-;; VFP load/store.
+-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+-
+-(define_insn_reservation "cortex_a5_f_loads" 4
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "f_loads"))
+-  "cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_f_loadd" 5
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "f_load,f_loadd"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_f_stores" 0
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "f_stores"))
+-  "cortex_a5_ex1")
+-
+-(define_insn_reservation "cortex_a5_f_stored" 0
+-  (and (eq_attr "tune" "cortexa5")
+-       (eq_attr "type" "f_store,f_stored"))
+-  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+-
+-;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a
+-;; latency of two (6.8.3).
+-
+-(define_bypass 2 "cortex_a5_f_loads"
+-                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
+-		  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
+-		  cortex_a5_f2r")
+-
+-(define_bypass 3 "cortex_a5_f_loadd"
+-                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
+-		  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
+-		  cortex_a5_f2r")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch
new file mode 100644
index 0000000000..60608e4813
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch
@@ -0,0 +1,360 @@
+	Backport from FSF:
+
+	2010-08-25  Julian Brown  <julian@codesourcery.com>
+
+	* config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
+	* config/arm/arm.md (generic_sched): No for Cortex-A5.
+	(generic_vfp): Likewise.
+	(cortex-a5.md): Include.
+	* config/arm/cortex-a5.md: New.
+
+2010-08-25  Andrew Stubbs  <ams@codesourcery.com>
+
+ 	Revert:
+ 
+ 	2010-07-26  Julian Brown  <julian@codesourcery.com>
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-25 16:20:13 +0000
++++ new/gcc/config/arm/arm.c	2010-08-25 16:22:17 +0000
+@@ -22472,6 +22472,7 @@
+     {
+     case cortexr4:
+     case cortexr4f:
++    case cortexa5:
+     case cortexa8:
+     case cortexa9:
+       return 2;
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-25 16:20:13 +0000
++++ new/gcc/config/arm/arm.md	2010-08-25 16:22:17 +0000
+@@ -412,7 +412,7 @@
+ 
+ (define_attr "generic_sched" "yes,no"
+   (const (if_then_else 
+-          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
++          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
+ 	      (eq_attr "tune_cortexr4" "yes"))
+           (const_string "no")
+           (const_string "yes"))))
+@@ -420,7 +420,7 @@
+ (define_attr "generic_vfp" "yes,no"
+   (const (if_then_else
+ 	  (and (eq_attr "fpu" "vfp")
+-	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
++	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
+ 	       (eq_attr "tune_cortexr4" "no"))
+ 	  (const_string "yes")
+ 	  (const_string "no"))))
+@@ -444,6 +444,7 @@
+ (include "arm1020e.md")
+ (include "arm1026ejs.md")
+ (include "arm1136jfs.md")
++(include "cortex-a5.md")
+ (include "cortex-a8.md")
+ (include "cortex-a9.md")
+ (include "cortex-r4.md")
+
+=== added file 'gcc/config/arm/cortex-a5.md'
+--- old/gcc/config/arm/cortex-a5.md	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/cortex-a5.md	2010-08-25 16:22:17 +0000
+@@ -0,0 +1,297 @@
++;; ARM Cortex-A5 pipeline description
++;; Copyright (C) 2010 Free Software Foundation, Inc.
++;; Contributed by CodeSourcery.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++
++(define_automaton "cortex_a5")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Functional units.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; The integer (ALU) pipeline.  There are five DPU pipeline
++;; stages. However the decode/issue stages operate the same for all
++;; instructions, so do not model them.  We only need to model the
++;; first execute stage because instructions always advance one stage
++;; per cycle in order.  Only branch instructions may dual-issue, so a
++;; single unit covers all of the LS, ALU, MAC and FPU pipelines.
++
++(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
++
++;; The branch pipeline.  Branches can dual-issue with other instructions
++;; (except when those instructions take multiple cycles to issue).
++
++(define_cpu_unit "cortex_a5_branch" "cortex_a5")
++
++;; Pseudo-unit for blocking the multiply pipeline when a double-precision
++;; multiply is in progress.
++
++(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
++
++;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
++;; of the add pipeline by fmac instructions, etc.
++
++(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
++
++;; Floating-point div/sqrt (long latency, out-of-order completion).
++
++(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; ALU instructions.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++(define_insn_reservation "cortex_a5_alu" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "alu"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_alu_shift" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "alu_shift,alu_shift_reg"))
++  "cortex_a5_ex1")
++
++;; Forwarding path for unshifted operands.
++
++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
++  "cortex_a5_alu")
++
++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
++  "cortex_a5_alu_shift"
++  "arm_no_early_alu_shift_dep")
++
++;; The multiplier pipeline can forward results from wr stage only so 
++;; there's no need to specify bypasses).
++
++(define_insn_reservation "cortex_a5_mul" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "mult"))
++  "cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Load/store instructions.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; Address-generation happens in the issue stage, which is one stage behind
++;; the ex1 stage (the first stage we care about for scheduling purposes). The
++;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
++
++(define_insn_reservation "cortex_a5_load1" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load_byte,load1"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store1" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store1"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_load2" 3
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load2"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store2" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store2"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_load3" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store3" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_load4" 5
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "load3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_store4" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "store3"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
++   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Branches.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; Direct branches are the only instructions we can dual-issue (also IT and
++;; nop, but those aren't very interesting for scheduling).  (The latency here
++;; is meant to represent when the branch actually takes place, but may not be
++;; entirely correct.)
++
++(define_insn_reservation "cortex_a5_branch" 3
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "branch,call"))
++  "cortex_a5_branch")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Floating-point arithmetic.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++(define_insn_reservation "cortex_a5_fpalu" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
++			fcmps, fcmpd"))
++  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
++
++;; For fconsts and fconstd, 8-bit immediate data is passed directly from
++;; f1 to f3 (which I think reduces the latency by one cycle).
++
++(define_insn_reservation "cortex_a5_fconst" 3
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fconsts,fconstd"))
++  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
++
++;; We should try not to attempt to issue a single-precision multiplication in
++;; the middle of a double-precision multiplication operation (the usage of
++;; cortex_a5_fpmul_pipe).
++
++(define_insn_reservation "cortex_a5_fpmuls" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmuls"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe")
++
++;; For single-precision multiply-accumulate, the add (accumulate) is issued
++;; whilst the multiply is in F4.  The multiply result can then be forwarded
++;; from F5 to F1.  The issue unit is only used once (when we first start
++;; processing the instruction), but the usage of the FP add pipeline could
++;; block other instructions attempting to use it simultaneously.  We try to
++;; avoid that using cortex_a5_fpadd_pipe.
++
++(define_insn_reservation "cortex_a5_fpmacs" 8
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmacs"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
++
++;; Non-multiply instructions can issue in the middle two instructions of a
++;; double-precision multiply.  Note that it isn't entirely clear when a branch
++;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
++;; that for now though.
++
++(define_insn_reservation "cortex_a5_fpmuld" 7
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmuld"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
++   cortex_a5_ex1+cortex_a5_fpmul_pipe")
++
++(define_insn_reservation "cortex_a5_fpmacd" 11
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fmacd"))
++  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
++   cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; Floating-point divide/square root instructions.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
++;; includes the time taken for the special instruction used to collect the
++;; result to travel down the multiply pipeline, or not.  Assuming so.  (If
++;; that's wrong, the latency should be increased by a few cycles.)
++
++;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
++;; multiply pipeline to collect the divide/square-root result.
++
++(define_insn_reservation "cortex_a5_fdivs" 14
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fdivs"))
++  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
++
++;; ??? Similarly for fdivd.
++
++(define_insn_reservation "cortex_a5_fdivd" 29
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "fdivd"))
++  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; VFP to/from core transfers.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; FP loads take data from wr/rot/f3.
++
++;; Core-to-VFP transfers use the multiply pipeline.
++
++(define_insn_reservation "cortex_a5_r2f" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "r_2_f"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f2r" 2
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_2_r"))
++  "cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; VFP flag transfer.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++;; ??? The flag forwarding from fmstat to the ex2 stage of the second
++;; instruction is not modeled at present.
++
++(define_insn_reservation "cortex_a5_f_flags" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_flag"))
++  "cortex_a5_ex1")
++
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++;; VFP load/store.
++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
++
++(define_insn_reservation "cortex_a5_f_loads" 4
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_loads"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f_loadd" 5
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_load,f_loadd"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f_stores" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_stores"))
++  "cortex_a5_ex1")
++
++(define_insn_reservation "cortex_a5_f_stored" 0
++  (and (eq_attr "tune" "cortexa5")
++       (eq_attr "type" "f_store,f_stored"))
++  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
++
++;; Load-to-use for floating-point values has a penalty of one cycle,
++;; i.e. a latency of two.
++
++(define_bypass 2 "cortex_a5_f_loads"
++                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
++		  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
++		  cortex_a5_f2r")
++
++(define_bypass 3 "cortex_a5_f_loadd"
++                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
++		  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
++		  cortex_a5_f2r")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch
new file mode 100644
index 0000000000..dfe193ff28
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch
@@ -0,0 +1,72 @@
+2010-08-26  Andrew Stubbs  <ams@codesourcery.com>
+
+	Merge from Ubuntu GCC:
+
+	GCC bugzilla PR objc/41848.
+
+	gcc/
+	* objc/lang-specs.h: Work around ObjC and -fsection-anchors.
+
+	gcc/testsuite/
+	* objc/execute/forward-1.x: Update for ARM.
+
+ 2010-08-25  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from FSF:
+
+=== modified file 'gcc/objc/lang-specs.h'
+--- old/gcc/objc/lang-specs.h	2007-08-02 09:37:36 +0000
++++ new/gcc/objc/lang-specs.h	2010-08-26 14:02:04 +0000
+@@ -26,29 +26,33 @@
+   {"@objective-c",
+      "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\
+           %(cpp_options) %(cpp_debug_options)}\
++        %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \
+       %{!E:%{!M:%{!MM:\
+ 	%{traditional|ftraditional|traditional-cpp:\
+ %eGNU Objective C no longer supports traditional compilation}\
+ 	%{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\
+-	    cc1obj -fpreprocessed %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\
++           cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\
+ 	%{!save-temps:%{!no-integrated-cpp:\
+-	    cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\
++	    cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\
+         %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {".mi", "@objc-cpp-output", 0, 0, 0},
+   {"@objc-cpp-output",
+-     "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
+-			     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
++     "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++			     %{!fsyntax-only:%(invoke_as)}}}}   \
++    %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} ", 0, 0, 0},
+   {"@objective-c-header",
+      "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\
+           %(cpp_options) %(cpp_debug_options)}\
++        %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \
+       %{!E:%{!M:%{!MM:\
+ 	%{traditional|ftraditional|traditional-cpp:\
+ %eGNU Objective C no longer supports traditional compilation}\
+ 	%{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\
+-	    cc1obj -fpreprocessed %b.mi %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++	    cc1obj -fpreprocessed %b.mi %(cc1_options) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\
+                         -o %g.s %{!o*:--output-pch=%i.gch}\
+                         %W{o*:--output-pch=%*}%V}\
++        %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \
+ 	%{!save-temps:%{!no-integrated-cpp:\
+-	    cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++	    cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
+                         -o %g.s %{!o*:--output-pch=%i.gch}\
+                         %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0},
+
+=== modified file 'gcc/testsuite/objc/execute/forward-1.x'
+--- old/gcc/testsuite/objc/execute/forward-1.x	2010-03-25 22:25:05 +0000
++++ new/gcc/testsuite/objc/execute/forward-1.x	2010-08-26 14:02:04 +0000
+@@ -4,6 +4,7 @@
+ 
+ if { ([istarget x86_64-*-linux*] && [check_effective_target_lp64] )
+      || [istarget powerpc*-*-linux*]
++     || [istarget arm*]
+      || [istarget powerpc*-*-aix*]
+      || [istarget s390*-*-*-linux*]
+      || [istarget sh4-*-linux*]
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch
new file mode 100644
index 0000000000..fac64b9642
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch
@@ -0,0 +1,146 @@
+2010-08-26  Maciej Rozycki  <macro@codesourcery.com>
+
+	Merge from Sourcery G++ 4.4:
+
+	2009-02-17  Andrew Jenner  <andrew@codesourcery.com>
+	            Maciej Rozycki  <macro@codesourcery.com>
+
+	gcc/
+	* unwind.inc (_Unwind_RaiseException): Use return value of
+	uw_init_context.
+	* unwind-dw2.c (uw_init_context): Make macro an expression instead of
+	a statement.
+	(uw_init_context_1): Add return value.
+	* unwind-sjlj.c (uw_init_context): Add return value.
+
+ 2010-08-26  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Merge from Ubuntu GCC:
+
+=== modified file 'gcc/unwind-dw2.c'
+--- old/gcc/unwind-dw2.c	2010-04-27 08:41:30 +0000
++++ new/gcc/unwind-dw2.c	2010-08-26 15:38:19 +0000
+@@ -1414,16 +1414,12 @@
+ /* Fill in CONTEXT for top-of-stack.  The only valid registers at this
+    level will be the return address and the CFA.  */
+ 
+-#define uw_init_context(CONTEXT)					   \
+-  do									   \
+-    {									   \
+-      /* Do any necessary initialization to access arbitrary stack frames. \
+-	 On the SPARC, this means flushing the register windows.  */	   \
+-      __builtin_unwind_init ();						   \
+-      uw_init_context_1 (CONTEXT, __builtin_dwarf_cfa (),		   \
+-			 __builtin_return_address (0));			   \
+-    }									   \
+-  while (0)
++#define uw_init_context(CONTEXT)					\
++  /* Do any necessary initialization to access arbitrary stack frames.	\
++     On the SPARC, this means flushing the register windows.  */	\
++  (__builtin_unwind_init (),						\
++   uw_init_context_1 ((CONTEXT), __builtin_dwarf_cfa (),		\
++		      __builtin_return_address (0)))
+ 
+ static inline void
+ init_dwarf_reg_size_table (void)
+@@ -1431,7 +1427,7 @@
+   __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
+ }
+ 
+-static void __attribute__((noinline))
++static _Unwind_Reason_Code __attribute__((noinline))
+ uw_init_context_1 (struct _Unwind_Context *context,
+ 		   void *outer_cfa, void *outer_ra)
+ {
+@@ -1445,7 +1441,8 @@
+   context->flags = EXTENDED_CONTEXT_BIT;
+ 
+   code = uw_frame_state_for (context, &fs);
+-  gcc_assert (code == _URC_NO_REASON);
++  if (code != _URC_NO_REASON)
++    return code;
+ 
+ #if __GTHREADS
+   {
+@@ -1471,6 +1468,8 @@
+      initialization context, then we can't see it in the given
+      call frame data.  So have the initialization context tell us.  */
+   context->ra = __builtin_extract_return_addr (outer_ra);
++
++  return _URC_NO_REASON;
+ }
+ 
+ static void _Unwind_DebugHook (void *, void *)
+
+=== modified file 'gcc/unwind-sjlj.c'
+--- old/gcc/unwind-sjlj.c	2009-04-09 14:00:19 +0000
++++ new/gcc/unwind-sjlj.c	2010-08-26 15:38:19 +0000
+@@ -292,10 +292,11 @@
+   uw_update_context (context, fs);
+ }
+ 
+-static inline void
++static inline _Unwind_Reason_Code
+ uw_init_context (struct _Unwind_Context *context)
+ {
+   context->fc = _Unwind_SjLj_GetContext ();
++  return _URC_NO_REASON;
+ }
+ 
+ static void __attribute__((noreturn))
+
+=== modified file 'gcc/unwind.inc'
+--- old/gcc/unwind.inc	2009-04-09 14:00:19 +0000
++++ new/gcc/unwind.inc	2010-08-26 15:38:19 +0000
+@@ -85,7 +85,8 @@
+   _Unwind_Reason_Code code;
+ 
+   /* Set up this_context to describe the current stack frame.  */
+-  uw_init_context (&this_context);
++  code = uw_init_context (&this_context);
++  gcc_assert (code == _URC_NO_REASON);
+   cur_context = this_context;
+ 
+   /* Phase 1: Search.  Unwind the stack, calling the personality routine
+@@ -198,7 +199,8 @@
+   struct _Unwind_Context this_context, cur_context;
+   _Unwind_Reason_Code code;
+ 
+-  uw_init_context (&this_context);
++  code = uw_init_context (&this_context);
++  gcc_assert (code == _URC_NO_REASON);
+   cur_context = this_context;
+ 
+   exc->private_1 = (_Unwind_Ptr) stop;
+@@ -221,7 +223,8 @@
+   struct _Unwind_Context this_context, cur_context;
+   _Unwind_Reason_Code code;
+ 
+-  uw_init_context (&this_context);
++  code = uw_init_context (&this_context);
++  gcc_assert (code == _URC_NO_REASON);
+   cur_context = this_context;
+ 
+   /* Choose between continuing to process _Unwind_RaiseException
+@@ -251,7 +254,8 @@
+   if (exc->private_1 == 0)
+     return _Unwind_RaiseException (exc);
+ 
+-  uw_init_context (&this_context);
++  code = uw_init_context (&this_context);
++  gcc_assert (code == _URC_NO_REASON);
+   cur_context = this_context;
+ 
+   code = _Unwind_ForcedUnwind_Phase2 (exc, &cur_context);
+@@ -280,7 +284,9 @@
+   struct _Unwind_Context context;
+   _Unwind_Reason_Code code;
+ 
+-  uw_init_context (&context);
++  code = uw_init_context (&context);
++  if (code != _URC_NO_REASON)
++    return _URC_FATAL_PHASE1_ERROR;
+ 
+   while (1)
+     {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch
new file mode 100644
index 0000000000..5e402a753e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch
@@ -0,0 +1,35 @@
+2010-08-26  Paul Brook  <paul@codesourcery.com>
+
+	Merge from Sourcery G++ 4.3/4.4:
+	2007-03-30  Paul Brook  <paul@codesourcery.com>
+	gcc/
+	* calls.c (store_one_arg): Check alignment of mode used for save.
+
+ 2010-08-26  Maciej Rozycki  <macro@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.4:
+
+=== modified file 'gcc/calls.c'
+--- old/gcc/calls.c	2010-08-13 10:50:45 +0000
++++ new/gcc/calls.c	2010-08-26 15:44:20 +0000
+@@ -4048,8 +4048,17 @@
+ 	      /* We need to make a save area.  */
+ 	      unsigned int size = arg->locate.size.constant * BITS_PER_UNIT;
+ 	      enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1);
+-	      rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0));
+-	      rtx stack_area = gen_rtx_MEM (save_mode, adr);
++	      rtx adr;
++	      rtx stack_area;
++
++	      /* We can only use save_mode if the arg is sufficiently
++	         aligned.  */
++	      if (STRICT_ALIGNMENT
++		  && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary)
++		save_mode = BLKmode;
++
++	      adr = memory_address (save_mode, XEXP (arg->stack_slot, 0));
++	      stack_area = gen_rtx_MEM (save_mode, adr);
+ 
+ 	      if (save_mode == BLKmode)
+ 		{
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch
new file mode 100644
index 0000000000..d51f0874e3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch
@@ -0,0 +1,28 @@
+	Issue #1510
+	2007-04-27  Paul Brook  <paul@codesourcery.com>
+	gcc/
+	* cse.c (cse_process_notes): Make sure PLUS are canonical.
+
+2010-08-26  Paul Brook  <paul@codesourcery.com>
+
+	Merge from Sourcery G++ 4.3/4.4:
+ 	2007-03-30  Paul Brook  <paul@codesourcery.com>
+ 	gcc/
+ 	* calls.c (store_one_arg): Check alignment of mode used for save.
+
+=== modified file 'gcc/cse.c'
+--- old/gcc/cse.c	2010-01-12 20:25:10 +0000
++++ new/gcc/cse.c	2010-08-26 15:53:20 +0000
+@@ -6061,6 +6061,11 @@
+       validate_change (object, &XEXP (x, i),
+ 		       cse_process_notes (XEXP (x, i), object, changed), 0);
+ 
++  /* Rebuild a PLUS expression in canonical form if the first operand
++     ends up as a constant.  */
++  if (code == PLUS && GET_CODE (XEXP (x, 0)) == CONST_INT)
++    return plus_constant (XEXP(x, 1), INTVAL (XEXP (x, 0)));
++
+   return x;
+ }
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch
new file mode 100644
index 0000000000..aacf19b7c9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch
@@ -0,0 +1,159 @@
+2010-08-27  Paul Brook  <paul@codesourcery.com>
+
+	gcc/
+	* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si,
+	thumb2_notsi_shiftsi, thumb2_notsi_shiftsi_compare0,
+	thumb2_not_shiftsi_compare0_scratch, thumb2_cmpsi_shiftsi,
+	thumb2_cmpsi_shiftsi_swp, thumb2_cmpsi_neg_shiftsi,
+	thumb2_arith_shiftsi, thumb2_arith_shiftsi_compare0,
+	thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi,
+	thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch):
+	Use const_shift_count predicate for "M" constraints.
+	* config/arm/predicates.md (const_shift_operand): Remove.
+	(const_shift_count): New.
+
+	gcc/testsuite/
+	* gcc.dg/long-long-shift-1.c: New test.
+
+ 2010-08-26  Paul Brook  <paul@codesourcery.com>
+ 
+ 	Merge from Sourcery G++ 4.3/4.4:
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-08-12 13:35:39 +0000
++++ new/gcc/config/arm/predicates.md	2010-08-31 09:40:16 +0000
+@@ -318,10 +318,9 @@
+        (and (match_code "reg,subreg,mem")
+ 	    (match_operand 0 "nonimmediate_soft_df_operand"))))
+ 
+-(define_predicate "const_shift_operand"
++(define_predicate "const_shift_count"
+   (and (match_code "const_int")
+-       (ior (match_operand 0 "power_of_two_operand")
+-	    (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
++       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32")))
+ 
+ 
+ (define_special_predicate "load_multiple_operation"
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-08-13 16:00:58 +0000
++++ new/gcc/config/arm/thumb2.md	2010-08-31 09:40:16 +0000
+@@ -55,7 +55,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(and:SI (not:SI (match_operator:SI 4 "shift_operator"
+ 			 [(match_operand:SI 2 "s_register_operand" "r")
+-			  (match_operand:SI 3 "const_int_operand" "M")]))
++			  (match_operand:SI 3 "const_shift_count" "M")]))
+ 		(match_operand:SI 1 "s_register_operand" "r")))]
+   "TARGET_THUMB2"
+   "bic%?\\t%0, %1, %2%S4"
+@@ -124,7 +124,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(not:SI (match_operator:SI 3 "shift_operator"
+ 		 [(match_operand:SI 1 "s_register_operand" "r")
+-		  (match_operand:SI 2 "const_int_operand"  "M")])))]
++		  (match_operand:SI 2 "const_shift_count"  "M")])))]
+   "TARGET_THUMB2"
+   "mvn%?\\t%0, %1%S3"
+   [(set_attr "predicable" "yes")
+@@ -136,7 +136,7 @@
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
+ 			  [(match_operand:SI 1 "s_register_operand" "r")
+-			   (match_operand:SI 2 "const_int_operand"  "M")]))
++			   (match_operand:SI 2 "const_shift_count"  "M")]))
+ 			 (const_int 0)))
+    (set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
+@@ -151,7 +151,7 @@
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
+ 			  [(match_operand:SI 1 "s_register_operand" "r")
+-			   (match_operand:SI 2 "const_int_operand"  "M")]))
++			   (match_operand:SI 2 "const_shift_count"  "M")]))
+ 			 (const_int 0)))
+    (clobber (match_scratch:SI 0 "=r"))]
+   "TARGET_THUMB2"
+@@ -328,7 +328,7 @@
+ 	(compare:CC (match_operand:SI   0 "s_register_operand" "r")
+ 		    (match_operator:SI  3 "shift_operator"
+ 		     [(match_operand:SI 1 "s_register_operand" "r")
+-		      (match_operand:SI 2 "const_int_operand"  "M")])))]
++		      (match_operand:SI 2 "const_shift_count"  "M")])))]
+   "TARGET_THUMB2"
+   "cmp%?\\t%0, %1%S3"
+   [(set_attr "conds" "set")
+@@ -340,7 +340,7 @@
+   [(set (reg:CC_SWP CC_REGNUM)
+ 	(compare:CC_SWP (match_operator:SI 3 "shift_operator"
+ 			 [(match_operand:SI 1 "s_register_operand" "r")
+-			  (match_operand:SI 2 "const_int_operand" "M")])
++			  (match_operand:SI 2 "const_shift_count" "M")])
+ 			(match_operand:SI 0 "s_register_operand" "r")))]
+   "TARGET_THUMB2"
+   "cmp%?\\t%0, %1%S3"
+@@ -354,7 +354,7 @@
+ 	(compare:CC (match_operand:SI 0 "s_register_operand" "r")
+ 		    (neg:SI (match_operator:SI 3 "shift_operator"
+ 			     [(match_operand:SI 1 "s_register_operand" "r")
+-			      (match_operand:SI 2 "const_int_operand" "M")]))))]
++			      (match_operand:SI 2 "const_shift_count" "M")]))))]
+   "TARGET_THUMB2"
+   "cmn%?\\t%0, %1%S3"
+   [(set_attr "conds" "set")
+@@ -466,7 +466,7 @@
+         (match_operator:SI 1 "shiftable_operator"
+           [(match_operator:SI 3 "shift_operator"
+              [(match_operand:SI 4 "s_register_operand" "r")
+-              (match_operand:SI 5 "const_int_operand" "M")])
++              (match_operand:SI 5 "const_shift_count" "M")])
+            (match_operand:SI 2 "s_register_operand" "r")]))]
+   "TARGET_THUMB2"
+   "%i1%?\\t%0, %2, %4%S3"
+@@ -499,7 +499,7 @@
+         (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
+ 		          [(match_operator:SI 3 "shift_operator"
+ 		            [(match_operand:SI 4 "s_register_operand" "r")
+-		             (match_operand:SI 5 "const_int_operand" "M")])
++		             (match_operand:SI 5 "const_shift_count" "M")])
+ 		           (match_operand:SI 2 "s_register_operand" "r")])
+ 			 (const_int 0)))
+    (set (match_operand:SI 0 "s_register_operand" "=r")
+@@ -517,7 +517,7 @@
+         (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
+ 		          [(match_operator:SI 3 "shift_operator"
+ 		            [(match_operand:SI 4 "s_register_operand" "r")
+-		             (match_operand:SI 5 "const_int_operand" "M")])
++		             (match_operand:SI 5 "const_shift_count" "M")])
+ 		           (match_operand:SI 2 "s_register_operand" "r")])
+ 			 (const_int 0)))
+    (clobber (match_scratch:SI 0 "=r"))]
+@@ -533,7 +533,7 @@
+ 	(minus:SI (match_operand:SI 1 "s_register_operand" "r")
+ 		  (match_operator:SI 2 "shift_operator"
+ 		   [(match_operand:SI 3 "s_register_operand" "r")
+-		    (match_operand:SI 4 "const_int_operand" "M")])))]
++		    (match_operand:SI 4 "const_shift_count" "M")])))]
+   "TARGET_THUMB2"
+   "sub%?\\t%0, %1, %3%S2"
+   [(set_attr "predicable" "yes")
+@@ -547,7 +547,7 @@
+ 	 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
+ 		   (match_operator:SI 2 "shift_operator"
+ 		    [(match_operand:SI 3 "s_register_operand" "r")
+-		     (match_operand:SI 4 "const_int_operand" "M")]))
++		     (match_operand:SI 4 "const_shift_count" "M")]))
+ 	 (const_int 0)))
+    (set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
+@@ -565,7 +565,7 @@
+ 	 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
+ 		   (match_operator:SI 2 "shift_operator"
+ 		    [(match_operand:SI 3 "s_register_operand" "r")
+-		     (match_operand:SI 4 "const_int_operand" "M")]))
++		     (match_operand:SI 4 "const_shift_count" "M")]))
+ 	 (const_int 0)))
+    (clobber (match_scratch:SI 0 "=r"))]
+   "TARGET_THUMB2"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch
new file mode 100644
index 0000000000..e1e89bf8af
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch
@@ -0,0 +1,2011 @@
+2010-08-29  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-04-16  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/41514
+	gcc/
+	* config/arm/arm.md (cbranchsi4_insn): Renamed from "*cbranchsi4_insn".
+	If the previous insn is a cbranchsi4_insn with the same arguments,
+	omit the compare instruction.
+
+	gcc/testsuite/
+	* gcc.target/arm/thumb-comparisons.c: New test.
+
+	gcc/
+	* config/arm/arm.md (addsi3_cbranch): If destination is a high
+	register, inputs must be low registers and we need a low register
+	scratch.  Handle alternative 2 like alternative 3.
+
+	PR target/40603
+	gcc/
+	* config/arm/arm.md (cbranchqi4): New pattern.
+	* config/arm/predicates.md (const0_operand,
+	cbranchqi4_comparison_operator): New predicates.
+
+	gcc/testsuite/
+	* gcc.target/arm/thumb-cbranchqi.c: New test.
+
+	2010-04-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/40657
+	gcc/
+	* config/arm/arm.c (thumb1_extra_regs_pushed): New function.
+	(thumb1_expand_prologue, thumb1_output_function_prologue): Call it
+	here to determine which regs to push and how much stack to reserve.
+
+	gcc/testsuite/
+	* gcc.target/arm/thumb-stackframe.c: New test.
+
+	2010-07-02  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/42835
+	gcc/
+	* config/arm/arm-modes.def (CC_NOTB): New mode.
+	* config/arm/arm.c (get_arm_condition_code): Handle it.
+	* config/arm/thumb2.md (thumb2_compare_scc): Delete pattern.
+	* config/arm/arm.md (subsi3_compare0_c): New pattern.
+	(compare_scc): Now a define_and_split.  Add a number of extra
+	splitters before it.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42835.c: New test.
+
+	PR target/42172
+	gcc/
+	* config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND
+	and ZERO_EXTEND.
+	(arm_rtx_costs_1): Likewise.
+	(arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes.
+	* config/arm/arm.md (is_arch6): New attribute.
+	(zero_extendhisi2, zero_extendqisi2, extendhisi2,
+	extendqisi2): Tighten the code somewhat, avoiding invalid
+	RTL to occur in the expander patterns.
+	(thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6.
+	(thumb1_zero_extendhisi2_v6): Delete.
+	(thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6.
+	(thumb1_extendhisi2_v6): Delete.
+	(thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6.
+	(thumb1_extendqisi2_v6): Delete.
+	(zero_extendhisi2 for register input splitter): New.
+	(zero_extendqisi2 for register input splitter): New.
+	(thumb1_extendhisi2 for register input splitter): New.
+	(extendhisi2 for register input splitter): New.
+	(extendqisi2 for register input splitter): New.
+	(TARGET_THUMB1 extendqisi2 for memory input splitter): New.
+	(arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1,
+	and add support for a register alternative requiring a split.
+	(thumb1_zero_extendqisi2): Likewise.
+	(arm_zero_extendqisi2): Likewise.
+	(arm_extendhisi2): Likewise.
+	(arm_extendqisi2): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42172-1.c: New test.
+
+	2010-07-05  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case.
+	* arm-modes.def (CC_NOTB): Don't define.
+	* config/arm/arm.md (arm_adddi3): Generate canonical RTL.
+	(adddi_sesidi_di, adddi_zesidi_di): Likewise.
+	(LTUGEU): New code_iterator.
+	(cnb, optab): New corresponding code_attrs.
+	(addsi3_carryin_<optab>): Renamed from addsi3_carryin.  Change pattern
+	to canonical form.  Operands 1 and 2 are commutative.  Parametrize
+	using LTUGEU.
+	(addsi3_carryin_shift_<optab>): Likewise.
+	(addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2.
+	Operands 1 and 2 are commutative.  Parametrize using LTUGEU.
+	(addsi3_carryin_alt1, addsi3_carryin_alt3): Remove.
+	(subsi3_compare): Renamed from subsi3_compare0_c.  Change CC_NOTB to
+	CC.
+	(arm_subsi3_insn): Allow constants for operand 0.
+	(compare_scc peephole for eq case): New.
+	(compare_scc splitters): Change CC_NOTB to CC.
+
+	2010-07-09  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/40657
+	gcc/
+	* config/arm/arm.c (thumb1_extra_regs_pushed): New arg FOR_PROLOGUE.
+	All callers changed.
+	Handle the case when we're called for the epilogue.
+	(thumb_unexpanded_epilogue): Use it.
+	(thumb1_expand_epilogue): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr40657-1.c: New test.
+	* gcc.target/arm/pr40657-2.c: New test.
+	* gcc.c-torture/execute/pr40657.c: New test.
+
+	gcc/
+	* config/arm/arm.md (addsi3_cbranch): Switch alternatives 0 and 1.
+
+	* config/arm/arm.md (Thumb-1 ldrsb peephole): New.
+
+	* config/arm/arm.md (cbranchqi4): Fix array size.
+	(addsi3_cbranch): Also andle alternative 2 like alternative 3 when
+	calculating length.
+
+ 2010-08-27  Paul Brook  <paul@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm-modes.def'
+--- old/gcc/config/arm/arm-modes.def	2010-07-29 16:58:56 +0000
++++ new/gcc/config/arm/arm-modes.def	2010-08-31 10:00:27 +0000
+@@ -34,6 +34,8 @@
+    CCFPmode should be used with floating equalities.
+    CC_NOOVmode should be used with SImode integer equalities.
+    CC_Zmode should be used if only the Z flag is set correctly
++   CC_Cmode should be used if only the C flag is set correctly, after an
++     addition.
+    CC_Nmode should be used if only the N (sign) flag is set correctly
+    CC_CZmode should be used if only the C and Z flags are correct
+    (used for DImode unsigned comparisons).
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-08-25 16:22:17 +0000
++++ new/gcc/config/arm/arm.c	2010-08-31 10:00:27 +0000
+@@ -6443,6 +6443,7 @@
+ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+ {
+   enum machine_mode mode = GET_MODE (x);
++  int total;
+ 
+   switch (code)
+     {
+@@ -6545,24 +6546,20 @@
+ 	return 14;
+       return 2;
+ 
++    case SIGN_EXTEND:
+     case ZERO_EXTEND:
+-      /* XXX still guessing.  */
+-      switch (GET_MODE (XEXP (x, 0)))
+-	{
+-	case QImode:
+-	  return (1 + (mode == DImode ? 4 : 0)
+-		  + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
+-
+-	case HImode:
+-	  return (4 + (mode == DImode ? 4 : 0)
+-		  + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
+-
+-	case SImode:
+-	  return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
+-
+-	default:
+-	  return 99;
+-	}
++      total = mode == DImode ? COSTS_N_INSNS (1) : 0;
++      total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code);
++
++      if (mode == SImode)
++	return total;
++
++      if (arm_arch6)
++	return total + COSTS_N_INSNS (1);
++
++      /* Assume a two-shift sequence.  Increase the cost slightly so
++	 we prefer actual shifts over an extend operation.  */
++      return total + 1 + COSTS_N_INSNS (2);
+ 
+     default:
+       return 99;
+@@ -7046,44 +7043,39 @@
+       return false;
+ 
+     case SIGN_EXTEND:
+-      if (GET_MODE_CLASS (mode) == MODE_INT)
+-	{
+-	  *total = 0;
+-	  if (mode == DImode)
+-	    *total += COSTS_N_INSNS (1);
+-
+-	  if (GET_MODE (XEXP (x, 0)) != SImode)
+-	    {
+-	      if (arm_arch6)
+-		{
+-		  if (GET_CODE (XEXP (x, 0)) != MEM)
+-		    *total += COSTS_N_INSNS (1);
+-		}
+-	      else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM)
+-		*total += COSTS_N_INSNS (2);
+-	    }
+-
+-	  return false;
+-	}
+-
+-      /* Fall through */
+     case ZERO_EXTEND:
+       *total = 0;
+       if (GET_MODE_CLASS (mode) == MODE_INT)
+ 	{
++	  rtx op = XEXP (x, 0);
++	  enum machine_mode opmode = GET_MODE (op);
++
+ 	  if (mode == DImode)
+ 	    *total += COSTS_N_INSNS (1);
+ 
+-	  if (GET_MODE (XEXP (x, 0)) != SImode)
++	  if (opmode != SImode)
+ 	    {
+-	      if (arm_arch6)
++	      if (MEM_P (op))
+ 		{
+-		  if (GET_CODE (XEXP (x, 0)) != MEM)
+-		    *total += COSTS_N_INSNS (1);
++		  /* If !arm_arch4, we use one of the extendhisi2_mem
++		     or movhi_bytes patterns for HImode.  For a QImode
++		     sign extension, we first zero-extend from memory
++		     and then perform a shift sequence.  */
++		  if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND))
++		    *total += COSTS_N_INSNS (2);
+ 		}
+-	      else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM)
+-		*total += COSTS_N_INSNS (GET_MODE (XEXP (x, 0)) == QImode ?
+-					 1 : 2);
++	      else if (arm_arch6)
++		*total += COSTS_N_INSNS (1);
++
++	      /* We don't have the necessary insn, so we need to perform some
++		 other operation.  */
++	      else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode)
++		/* An and with constant 255.  */
++		*total += COSTS_N_INSNS (1);
++	      else
++		/* A shift sequence.  Increase costs slightly to avoid
++		   combining two shifts into an extend operation.  */
++		*total += COSTS_N_INSNS (2) + 1;
+ 	    }
+ 
+ 	  return false;
+@@ -7333,41 +7325,8 @@
+       return false;
+ 
+     case SIGN_EXTEND:
+-      *total = 0;
+-      if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
+-	{
+-	  if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
+-	    *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
+-	}
+-      if (mode == DImode)
+-	*total += COSTS_N_INSNS (1);
+-      return false;
+-
+     case ZERO_EXTEND:
+-      *total = 0;
+-      if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
+-	{
+-	  switch (GET_MODE (XEXP (x, 0)))
+-	    {
+-	    case QImode:
+-	      *total += COSTS_N_INSNS (1);
+-	      break;
+-
+-	    case HImode:
+-	      *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
+-
+-	    case SImode:
+-	      break;
+-
+-	    default:
+-	      *total += COSTS_N_INSNS (2);
+-	    }
+-	}
+-
+-      if (mode == DImode)
+-	*total += COSTS_N_INSNS (1);
+-
+-      return false;
++      return arm_rtx_costs_1 (x, outer_code, total, 0);
+ 
+     case CONST_INT:
+       if (const_ok_for_arm (INTVAL (x)))
+@@ -16898,11 +16857,11 @@
+ 
+     case CC_Cmode:
+       switch (comp_code)
+-      {
+-      case LTU: return ARM_CS;
+-      case GEU: return ARM_CC;
+-      default: gcc_unreachable ();
+-      }
++	{
++	case LTU: return ARM_CS;
++	case GEU: return ARM_CC;
++	default: gcc_unreachable ();
++	}
+ 
+     case CC_CZmode:
+       switch (comp_code)
+@@ -20127,6 +20086,81 @@
+ #endif
+ }
+ 
++/* Given the stack offsets and register mask in OFFSETS, decide how
++   many additional registers to push instead of subtracting a constant
++   from SP.  For epilogues the principle is the same except we use pop.
++   FOR_PROLOGUE indicates which we're generating.  */
++static int
++thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue)
++{
++  HOST_WIDE_INT amount;
++  unsigned long live_regs_mask = offsets->saved_regs_mask;
++  /* Extract a mask of the ones we can give to the Thumb's push/pop
++     instruction.  */
++  unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff);
++  /* Then count how many other high registers will need to be pushed.  */
++  unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
++  int n_free, reg_base;
++
++  if (!for_prologue && frame_pointer_needed)
++    amount = offsets->locals_base - offsets->saved_regs;
++  else
++    amount = offsets->outgoing_args - offsets->saved_regs;
++
++  /* If the stack frame size is 512 exactly, we can save one load
++     instruction, which should make this a win even when optimizing
++     for speed.  */
++  if (!optimize_size && amount != 512)
++    return 0;
++
++  /* Can't do this if there are high registers to push.  */
++  if (high_regs_pushed != 0)
++    return 0;
++
++  /* Shouldn't do it in the prologue if no registers would normally
++     be pushed at all.  In the epilogue, also allow it if we'll have
++     a pop insn for the PC.  */
++  if  (l_mask == 0
++       && (for_prologue
++	   || TARGET_BACKTRACE
++	   || (live_regs_mask & 1 << LR_REGNUM) == 0
++	   || TARGET_INTERWORK
++	   || crtl->args.pretend_args_size != 0))
++    return 0;
++
++  /* Don't do this if thumb_expand_prologue wants to emit instructions
++     between the push and the stack frame allocation.  */
++  if (for_prologue
++      && ((flag_pic && arm_pic_register != INVALID_REGNUM)
++	  || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)))
++    return 0;
++
++  reg_base = 0;
++  n_free = 0;
++  if (!for_prologue)
++    {
++      reg_base = arm_size_return_regs () / UNITS_PER_WORD;
++      live_regs_mask >>= reg_base;
++    }
++
++  while (reg_base + n_free < 8 && !(live_regs_mask & 1)
++	 && (for_prologue || call_used_regs[reg_base + n_free]))
++    {
++      live_regs_mask >>= 1;
++      n_free++;
++    }
++
++  if (n_free == 0)
++    return 0;
++  gcc_assert (amount / 4 * 4 == amount);
++
++  if (amount >= 512 && (amount - n_free * 4) < 512)
++    return (amount - 508) / 4;
++  if (amount <= n_free * 4)
++    return amount / 4;
++  return 0;
++}
++
+ /* The bits which aren't usefully expanded as rtl.  */
+ const char *
+ thumb_unexpanded_epilogue (void)
+@@ -20135,6 +20169,7 @@
+   int regno;
+   unsigned long live_regs_mask = 0;
+   int high_regs_pushed = 0;
++  int extra_pop;
+   int had_to_push_lr;
+   int size;
+ 
+@@ -20154,6 +20189,13 @@
+      the register is used to hold a return value.  */
+   size = arm_size_return_regs ();
+ 
++  extra_pop = thumb1_extra_regs_pushed (offsets, false);
++  if (extra_pop > 0)
++    {
++      unsigned long extra_mask = (1 << extra_pop) - 1;
++      live_regs_mask |= extra_mask << (size / UNITS_PER_WORD);
++    }
++
+   /* The prolog may have pushed some high registers to use as
+      work registers.  e.g. the testsuite file:
+      gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
+@@ -20237,7 +20279,9 @@
+ 		       live_regs_mask);
+ 
+       /* We have either just popped the return address into the
+-	 PC or it is was kept in LR for the entire function.  */
++	 PC or it is was kept in LR for the entire function.
++	 Note that thumb_pushpop has already called thumb_exit if the
++	 PC was in the list.  */
+       if (!had_to_push_lr)
+ 	thumb_exit (asm_out_file, LR_REGNUM);
+     }
+@@ -20419,6 +20463,7 @@
+ 		    stack_pointer_rtx);
+ 
+   amount = offsets->outgoing_args - offsets->saved_regs;
++  amount -= 4 * thumb1_extra_regs_pushed (offsets, true);
+   if (amount)
+     {
+       if (amount < 512)
+@@ -20503,6 +20548,7 @@
+       emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
+       amount = offsets->locals_base - offsets->saved_regs;
+     }
++  amount -= 4 * thumb1_extra_regs_pushed (offsets, false);
+ 
+   gcc_assert (amount >= 0);
+   if (amount)
+@@ -20723,7 +20769,11 @@
+      register.  */
+   else if ((l_mask & 0xff) != 0
+ 	   || (high_regs_pushed == 0 && l_mask))
+-    thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
++    {
++      unsigned long mask = l_mask;
++      mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1;
++      thumb_pushpop (f, mask, 1, &cfa_offset, mask);
++    }
+ 
+   if (high_regs_pushed)
+     {
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-08-25 16:22:17 +0000
++++ new/gcc/config/arm/arm.md	2010-08-31 10:00:27 +0000
+@@ -150,6 +150,9 @@
+ ; patterns that share the same RTL in both ARM and Thumb code.
+ (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))
+ 
++; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6.
++(define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6")))
++
+ ;; Operand number of an input operand that is shifted.  Zero if the
+ ;; given instruction does not shift one of its input operands.
+ (define_attr "shift" "" (const_int 0))
+@@ -515,8 +518,8 @@
+ 		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
+ 				 (match_dup 1)))
+ 	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+-   (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-			       (plus:SI (match_dup 4) (match_dup 5))))]
++   (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
++			       (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+   "
+   {
+     operands[3] = gen_highpart (SImode, operands[0]);
+@@ -543,10 +546,10 @@
+ 		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
+ 				 (match_dup 1)))
+ 	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+-   (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-			       (plus:SI (ashiftrt:SI (match_dup 2)
++   (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)
+ 						     (const_int 31))
+-					(match_dup 4))))]
++					(match_dup 4))
++			       (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+   "
+   {
+     operands[3] = gen_highpart (SImode, operands[0]);
+@@ -572,8 +575,8 @@
+ 		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
+ 				 (match_dup 1)))
+ 	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+-   (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-			       (plus:SI (match_dup 4) (const_int 0))))]
++   (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))
++			       (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+   "
+   {
+     operands[3] = gen_highpart (SImode, operands[0]);
+@@ -861,24 +864,38 @@
+   [(set_attr "conds" "set")]
+ )
+ 
+-(define_insn "*addsi3_carryin"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-		 (plus:SI (match_operand:SI 1 "s_register_operand" "r")
+-			  (match_operand:SI 2 "arm_rhs_operand" "rI"))))]
+-  "TARGET_32BIT"
+-  "adc%?\\t%0, %1, %2"
+-  [(set_attr "conds" "use")]
+-)
+-
+-(define_insn "*addsi3_carryin_shift"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-		 (plus:SI
+-		   (match_operator:SI 2 "shift_operator"
+-		      [(match_operand:SI 3 "s_register_operand" "r")
+-		       (match_operand:SI 4 "reg_or_int_operand" "rM")])
+-		    (match_operand:SI 1 "s_register_operand" "r"))))]
++(define_code_iterator LTUGEU [ltu geu])
++(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
++(define_code_attr optab [(ltu "ltu") (geu "geu")])
++
++(define_insn "*addsi3_carryin_<optab>"
++  [(set (match_operand:SI 0 "s_register_operand" "=r")
++	(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
++			  (match_operand:SI 2 "arm_rhs_operand" "rI"))
++		 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
++  "TARGET_32BIT"
++  "adc%?\\t%0, %1, %2"
++  [(set_attr "conds" "use")]
++)
++
++(define_insn "*addsi3_carryin_alt2_<optab>"
++  [(set (match_operand:SI 0 "s_register_operand" "=r")
++	(plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
++			  (match_operand:SI 1 "s_register_operand" "%r"))
++		 (match_operand:SI 2 "arm_rhs_operand" "rI")))]
++  "TARGET_32BIT"
++  "adc%?\\t%0, %1, %2"
++  [(set_attr "conds" "use")]
++)
++
++(define_insn "*addsi3_carryin_shift_<optab>"
++  [(set (match_operand:SI 0 "s_register_operand" "=r")
++	(plus:SI (plus:SI
++		  (match_operator:SI 2 "shift_operator"
++		    [(match_operand:SI 3 "s_register_operand" "r")
++		     (match_operand:SI 4 "reg_or_int_operand" "rM")])
++		  (match_operand:SI 1 "s_register_operand" "r"))
++		 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
+   "TARGET_32BIT"
+   "adc%?\\t%0, %1, %3%S2"
+   [(set_attr "conds" "use")
+@@ -887,36 +904,6 @@
+ 		      (const_string "alu_shift_reg")))]
+ )
+ 
+-(define_insn "*addsi3_carryin_alt1"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
+-			  (match_operand:SI 2 "arm_rhs_operand" "rI"))
+-		 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+-  "TARGET_32BIT"
+-  "adc%?\\t%0, %1, %2"
+-  [(set_attr "conds" "use")]
+-)
+-
+-(define_insn "*addsi3_carryin_alt2"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-			  (match_operand:SI 1 "s_register_operand" "r"))
+-		 (match_operand:SI 2 "arm_rhs_operand" "rI")))]
+-  "TARGET_32BIT"
+-  "adc%?\\t%0, %1, %2"
+-  [(set_attr "conds" "use")]
+-)
+-
+-(define_insn "*addsi3_carryin_alt3"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
+-			  (match_operand:SI 2 "arm_rhs_operand" "rI"))
+-		 (match_operand:SI 1 "s_register_operand" "r")))]
+-  "TARGET_32BIT"
+-  "adc%?\\t%0, %1, %2"
+-  [(set_attr "conds" "use")]
+-)
+-
+ (define_expand "incscc"
+   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
+@@ -1116,24 +1103,27 @@
+ 
+ ; ??? Check Thumb-2 split length
+ (define_insn_and_split "*arm_subsi3_insn"
+-  [(set (match_operand:SI           0 "s_register_operand" "=r,rk,r")
+-	(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n")
+-		  (match_operand:SI 2 "s_register_operand" "r, r, r")))]
++  [(set (match_operand:SI           0 "s_register_operand" "=r,r,rk,r,r")
++	(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r")
++		  (match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))]
+   "TARGET_32BIT"
+   "@
+    rsb%?\\t%0, %2, %1
+    sub%?\\t%0, %1, %2
++   sub%?\\t%0, %1, %2
++   #
+    #"
+-  "TARGET_32BIT
+-   && GET_CODE (operands[1]) == CONST_INT
+-   && !const_ok_for_arm (INTVAL (operands[1]))"
++  "&& ((GET_CODE (operands[1]) == CONST_INT
++       	&& !const_ok_for_arm (INTVAL (operands[1])))
++       || (GET_CODE (operands[2]) == CONST_INT
++	   && !const_ok_for_arm (INTVAL (operands[2]))))"
+   [(clobber (const_int 0))]
+   "
+   arm_split_constant (MINUS, SImode, curr_insn,
+                       INTVAL (operands[1]), operands[0], operands[2], 0);
+   DONE;
+   "
+-  [(set_attr "length" "4,4,16")
++  [(set_attr "length" "4,4,4,16,16")
+    (set_attr "predicable" "yes")]
+ )
+ 
+@@ -1165,6 +1155,19 @@
+   [(set_attr "conds" "set")]
+ )
+ 
++(define_insn "*subsi3_compare"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I")
++		    (match_operand:SI 2 "arm_rhs_operand" "rI,r")))
++   (set (match_operand:SI 0 "s_register_operand" "=r,r")
++	(minus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "@
++   sub%.\\t%0, %1, %2
++   rsb%.\\t%0, %2, %1"
++  [(set_attr "conds" "set")]
++)
++
+ (define_expand "decscc"
+   [(set (match_operand:SI            0 "s_register_operand" "=r,r")
+         (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
+@@ -4050,93 +4053,46 @@
+ )
+ 
+ (define_expand "zero_extendhisi2"
+-  [(set (match_dup 2)
+-	(ashift:SI (match_operand:HI 1 "nonimmediate_operand" "")
+-		   (const_int 16)))
+-   (set (match_operand:SI 0 "s_register_operand" "")
+-	(lshiftrt:SI (match_dup 2) (const_int 16)))]
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+   "TARGET_EITHER"
+-  "
+-  {
+-    if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM)
+-      {
+-	emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+-				gen_rtx_ZERO_EXTEND (SImode, operands[1])));
+-	DONE;
+-      }
+-
+-    if (TARGET_ARM && GET_CODE (operands[1]) == MEM)
+-      {
+-	emit_insn (gen_movhi_bytes (operands[0], operands[1]));
+-	DONE;
+-      }
+-
+-    if (!s_register_operand (operands[1], HImode))
+-      operands[1] = copy_to_mode_reg (HImode, operands[1]);
+-
+-    if (arm_arch6)
+-      {
+-	emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+-				gen_rtx_ZERO_EXTEND (SImode, operands[1])));
+-	DONE;
+-      }
+-
+-    operands[1] = gen_lowpart (SImode, operands[1]);
+-    operands[2] = gen_reg_rtx (SImode);
+-  }"
+-)
++{
++  if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1]))
++    {
++      emit_insn (gen_movhi_bytes (operands[0], operands[1]));
++      DONE;
++    }
++  if (!arm_arch6 && !MEM_P (operands[1]))
++    {
++      rtx t = gen_lowpart (SImode, operands[1]);
++      rtx tmp = gen_reg_rtx (SImode);
++      emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
++      emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (16)));
++      DONE;
++    }
++})
++
++(define_split
++  [(set (match_operand:SI 0 "register_operand" "")
++	(zero_extend:SI (match_operand:HI 1 "register_operand" "l,m")))]
++  "!TARGET_THUMB2 && !arm_arch6"
++  [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
++   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
++{
++  operands[2] = gen_lowpart (SImode, operands[1]);
++})
+ 
+ (define_insn "*thumb1_zero_extendhisi2"
+-  [(set (match_operand:SI 0 "register_operand" "=l")
+-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+-  "TARGET_THUMB1 && !arm_arch6"
+-  "*
+-  rtx mem = XEXP (operands[1], 0);
+-
+-  if (GET_CODE (mem) == CONST)
+-    mem = XEXP (mem, 0);
+-    
+-  if (GET_CODE (mem) == LABEL_REF)
+-    return \"ldr\\t%0, %1\";
+-    
+-  if (GET_CODE (mem) == PLUS)
+-    {
+-      rtx a = XEXP (mem, 0);
+-      rtx b = XEXP (mem, 1);
+-
+-      /* This can happen due to bugs in reload.  */
+-      if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
+-        {
+-          rtx ops[2];
+-          ops[0] = operands[0];
+-          ops[1] = a;
+-      
+-          output_asm_insn (\"mov	%0, %1\", ops);
+-
+-          XEXP (mem, 0) = operands[0];
+-       }
+-
+-      else if (   GET_CODE (a) == LABEL_REF
+-	       && GET_CODE (b) == CONST_INT)
+-        return \"ldr\\t%0, %1\";
+-    }
+-    
+-  return \"ldrh\\t%0, %1\";
+-  "
+-  [(set_attr "length" "4")
+-   (set_attr "type" "load_byte")
+-   (set_attr "pool_range" "60")]
+-)
+-
+-(define_insn "*thumb1_zero_extendhisi2_v6"
+   [(set (match_operand:SI 0 "register_operand" "=l,l")
+ 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))]
+-  "TARGET_THUMB1 && arm_arch6"
++  "TARGET_THUMB1"
+   "*
+   rtx mem;
+ 
+-  if (which_alternative == 0)
++  if (which_alternative == 0 && arm_arch6)
+     return \"uxth\\t%0, %1\";
++  if (which_alternative == 0)
++    return \"#\";
+ 
+   mem = XEXP (operands[1], 0);
+ 
+@@ -4170,20 +4126,25 @@
+     
+   return \"ldrh\\t%0, %1\";
+   "
+-  [(set_attr "length" "2,4")
++  [(set_attr_alternative "length"
++			 [(if_then_else (eq_attr "is_arch6" "yes")
++				       (const_int 2) (const_int 4))
++			 (const_int 4)])
+    (set_attr "type" "alu_shift,load_byte")
+    (set_attr "pool_range" "*,60")]
+ )
+ 
+ (define_insn "*arm_zero_extendhisi2"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
++	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+   "TARGET_ARM && arm_arch4 && !arm_arch6"
+-  "ldr%(h%)\\t%0, %1"
+-  [(set_attr "type" "load_byte")
++  "@
++   #
++   ldr%(h%)\\t%0, %1"
++  [(set_attr "type" "alu_shift,load_byte")
+    (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "256")
+-   (set_attr "neg_pool_range" "244")]
++   (set_attr "pool_range" "*,256")
++   (set_attr "neg_pool_range" "*,244")]
+ )
+ 
+ (define_insn "*arm_zero_extendhisi2_v6"
+@@ -4213,50 +4174,49 @@
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
+   "TARGET_EITHER"
+-  "
+-  if (!arm_arch6 && GET_CODE (operands[1]) != MEM)
+-    {
+-      if (TARGET_ARM)
+-        {
+-          emit_insn (gen_andsi3 (operands[0],
+-				 gen_lowpart (SImode, operands[1]),
+-			         GEN_INT (255)));
+-        }
+-      else /* TARGET_THUMB */
+-        {
+-          rtx temp = gen_reg_rtx (SImode);
+-	  rtx ops[3];
+-	  
+-          operands[1] = copy_to_mode_reg (QImode, operands[1]);
+-          operands[1] = gen_lowpart (SImode, operands[1]);
+-
+-	  ops[0] = temp;
+-	  ops[1] = operands[1];
+-	  ops[2] = GEN_INT (24);
+-
+-	  emit_insn (gen_rtx_SET (VOIDmode, ops[0],
+-				  gen_rtx_ASHIFT (SImode, ops[1], ops[2])));
+-	  
+-          ops[0] = operands[0];
+-	  ops[1] = temp;
+-	  ops[2] = GEN_INT (24);
+-
+-	  emit_insn (gen_rtx_SET (VOIDmode, ops[0],
+-				  gen_rtx_LSHIFTRT (SImode, ops[1], ops[2])));
+-	}
+-      DONE;
+-    }
+-  "
+-)
++{
++  if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM)
++    {
++      emit_insn (gen_andsi3 (operands[0],
++			     gen_lowpart (SImode, operands[1]),
++					  GEN_INT (255)));
++      DONE;
++    }
++  if (!arm_arch6 && !MEM_P (operands[1]))
++    {
++      rtx t = gen_lowpart (SImode, operands[1]);
++      rtx tmp = gen_reg_rtx (SImode);
++      emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24)));
++      emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (24)));
++      DONE;
++    }
++})
++
++(define_split
++  [(set (match_operand:SI 0 "register_operand" "")
++	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
++  "!arm_arch6"
++  [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
++   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
++{
++  operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
++  if (TARGET_ARM)
++    {
++      emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255)));
++      DONE;
++    }
++})
+ 
+ (define_insn "*thumb1_zero_extendqisi2"
+-  [(set (match_operand:SI 0 "register_operand" "=l")
+-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
++  [(set (match_operand:SI 0 "register_operand" "=l,l")
++	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))]
+   "TARGET_THUMB1 && !arm_arch6"
+-  "ldrb\\t%0, %1"
+-  [(set_attr "length" "2")
+-   (set_attr "type" "load_byte")
+-   (set_attr "pool_range" "32")]
++  "@
++   #
++   ldrb\\t%0, %1"
++  [(set_attr "length" "4,2")
++   (set_attr "type" "alu_shift,load_byte")
++   (set_attr "pool_range" "*,32")]
+ )
+ 
+ (define_insn "*thumb1_zero_extendqisi2_v6"
+@@ -4272,14 +4232,17 @@
+ )
+ 
+ (define_insn "*arm_zero_extendqisi2"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
++	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+   "TARGET_ARM && !arm_arch6"
+-  "ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
+-  [(set_attr "type" "load_byte")
++  "@
++   #
++   ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
++  [(set_attr "length" "8,4")
++   (set_attr "type" "alu_shift,load_byte")
+    (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "4096")
+-   (set_attr "neg_pool_range" "4084")]
++   (set_attr "pool_range" "*,4096")
++   (set_attr "neg_pool_range" "*,4084")]
+ )
+ 
+ (define_insn "*arm_zero_extendqisi2_v6"
+@@ -4358,108 +4321,42 @@
+ )
+ 
+ (define_expand "extendhisi2"
+-  [(set (match_dup 2)
+-	(ashift:SI (match_operand:HI 1 "nonimmediate_operand" "")
+-		   (const_int 16)))
+-   (set (match_operand:SI 0 "s_register_operand" "")
+-	(ashiftrt:SI (match_dup 2)
+-		     (const_int 16)))]
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+   "TARGET_EITHER"
+-  "
+-  {
+-    if (GET_CODE (operands[1]) == MEM)
+-      {
+-	if (TARGET_THUMB1)
+-	  {
+-	    emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
+-	    DONE;
+-          }
+-	else if (arm_arch4)
+-	  {
+-	    emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+-		       gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+-	    DONE;
+-	  }
+-      }
+-
+-    if (TARGET_ARM && GET_CODE (operands[1]) == MEM)
+-      {
+-        emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
+-        DONE;
+-      }
+-
+-    if (!s_register_operand (operands[1], HImode))
+-      operands[1] = copy_to_mode_reg (HImode, operands[1]);
+-
+-    if (arm_arch6)
+-      {
+-	if (TARGET_THUMB1)
+-	  emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
+-	else
+-	  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+-		     gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+-
+-	DONE;
+-      }
+-
+-    operands[1] = gen_lowpart (SImode, operands[1]);
+-    operands[2] = gen_reg_rtx (SImode);
+-  }"
+-)
+-
+-(define_insn "thumb1_extendhisi2"
+-  [(set (match_operand:SI 0 "register_operand" "=l")
+-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
+-   (clobber (match_scratch:SI 2 "=&l"))]
+-  "TARGET_THUMB1 && !arm_arch6"
+-  "*
+-  {
+-    rtx ops[4];
+-    rtx mem = XEXP (operands[1], 0);
+-
+-    /* This code used to try to use 'V', and fix the address only if it was
+-       offsettable, but this fails for e.g. REG+48 because 48 is outside the
+-       range of QImode offsets, and offsettable_address_p does a QImode
+-       address check.  */
+-       
+-    if (GET_CODE (mem) == CONST)
+-      mem = XEXP (mem, 0);
+-    
+-    if (GET_CODE (mem) == LABEL_REF)
+-      return \"ldr\\t%0, %1\";
+-    
+-    if (GET_CODE (mem) == PLUS)
+-      {
+-        rtx a = XEXP (mem, 0);
+-        rtx b = XEXP (mem, 1);
+-
+-        if (GET_CODE (a) == LABEL_REF
+-	    && GET_CODE (b) == CONST_INT)
+-          return \"ldr\\t%0, %1\";
+-
+-        if (GET_CODE (b) == REG)
+-          return \"ldrsh\\t%0, %1\";
+-	  
+-        ops[1] = a;
+-        ops[2] = b;
+-      }
+-    else
+-      {
+-        ops[1] = mem;
+-        ops[2] = const0_rtx;
+-      }
+-
+-    gcc_assert (GET_CODE (ops[1]) == REG);
+-
+-    ops[0] = operands[0];
+-    ops[3] = operands[2];
+-    output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops);
+-    return \"\";
+-  }"
+-  [(set_attr "length" "4")
+-   (set_attr "type" "load_byte")
+-   (set_attr "pool_range" "1020")]
+-)
++{
++  if (TARGET_THUMB1)
++    {
++      emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1]));
++      DONE;
++    }
++  if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4)
++    {
++      emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
++      DONE;
++    }
++
++  if (!arm_arch6 && !MEM_P (operands[1]))
++    {
++      rtx t = gen_lowpart (SImode, operands[1]);
++      rtx tmp = gen_reg_rtx (SImode);
++      emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16)));
++      emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16)));
++      DONE;
++    }
++})
++
++(define_split
++  [(parallel
++    [(set (match_operand:SI 0 "register_operand" "")
++	  (sign_extend:SI (match_operand:HI 1 "register_operand" "")))
++     (clobber (match_scratch:SI 2 ""))])]
++  "!arm_arch6"
++  [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
++   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
++{
++  operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
++})
+ 
+ ;; We used to have an early-clobber on the scratch register here.
+ ;; However, there's a bug somewhere in reload which means that this
+@@ -4468,16 +4365,18 @@
+ ;; we try to verify the operands.  Fortunately, we don't really need
+ ;; the early-clobber: we can always use operand 0 if operand 2
+ ;; overlaps the address.
+-(define_insn "*thumb1_extendhisi2_insn_v6"
++(define_insn "thumb1_extendhisi2"
+   [(set (match_operand:SI 0 "register_operand" "=l,l")
+ 	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))
+    (clobber (match_scratch:SI 2 "=X,l"))]
+-  "TARGET_THUMB1 && arm_arch6"
++  "TARGET_THUMB1"
+   "*
+   {
+     rtx ops[4];
+     rtx mem;
+ 
++    if (which_alternative == 0 && !arm_arch6)
++      return \"#\";
+     if (which_alternative == 0)
+       return \"sxth\\t%0, %1\";
+ 
+@@ -4525,7 +4424,10 @@
+     output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops);
+     return \"\";
+   }"
+-  [(set_attr "length" "2,4")
++  [(set_attr_alternative "length"
++			 [(if_then_else (eq_attr "is_arch6" "yes")
++					(const_int 2) (const_int 4))
++			  (const_int 4)])
+    (set_attr "type" "alu_shift,load_byte")
+    (set_attr "pool_range" "*,1020")]
+ )
+@@ -4566,15 +4468,28 @@
+   }"
+ )
+ 
++(define_split
++  [(set (match_operand:SI 0 "register_operand" "")
++	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
++  "!arm_arch6"
++  [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
++   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
++{
++  operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
++})
++
+ (define_insn "*arm_extendhisi2"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
++	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+   "TARGET_ARM && arm_arch4 && !arm_arch6"
+-  "ldr%(sh%)\\t%0, %1"
+-  [(set_attr "type" "load_byte")
++  "@
++   #
++   ldr%(sh%)\\t%0, %1"
++  [(set_attr "length" "8,4")
++   (set_attr "type" "alu_shift,load_byte")
+    (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "256")
+-   (set_attr "neg_pool_range" "244")]
++   (set_attr "pool_range" "*,256")
++   (set_attr "neg_pool_range" "*,244")]
+ )
+ 
+ ;; ??? Check Thumb-2 pool range
+@@ -4636,46 +4551,45 @@
+ )
+ 
+ (define_expand "extendqisi2"
+-  [(set (match_dup 2)
+-	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
+-		   (const_int 24)))
+-   (set (match_operand:SI 0 "s_register_operand" "")
+-	(ashiftrt:SI (match_dup 2)
+-		     (const_int 24)))]
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))]
+   "TARGET_EITHER"
+-  "
+-  {
+-    if ((TARGET_THUMB || arm_arch4) && GET_CODE (operands[1]) == MEM)
+-      {
+-        emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+-			        gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+-        DONE;
+-      }
+-
+-    if (!s_register_operand (operands[1], QImode))
+-      operands[1] = copy_to_mode_reg (QImode, operands[1]);
+-
+-    if (arm_arch6)
+-      {
+-        emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+-			        gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+-        DONE;
+-      }
+-
+-    operands[1] = gen_lowpart (SImode, operands[1]);
+-    operands[2] = gen_reg_rtx (SImode);
+-  }"
+-)
++{
++  if (!arm_arch4 && MEM_P (operands[1]))
++    operands[1] = copy_to_mode_reg (QImode, operands[1]);
++
++  if (!arm_arch6 && !MEM_P (operands[1]))
++    {
++      rtx t = gen_lowpart (SImode, operands[1]);
++      rtx tmp = gen_reg_rtx (SImode);
++      emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24)));
++      emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (24)));
++      DONE;
++    }
++})
++
++(define_split
++  [(set (match_operand:SI 0 "register_operand" "")
++	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
++  "!arm_arch6"
++  [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
++   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
++{
++  operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
++})
+ 
+ (define_insn "*arm_extendqisi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
++	(sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
+   "TARGET_ARM && arm_arch4 && !arm_arch6"
+-  "ldr%(sb%)\\t%0, %1"
+-  [(set_attr "type" "load_byte")
++  "@
++   #
++   ldr%(sb%)\\t%0, %1"
++  [(set_attr "length" "8,4")
++   (set_attr "type" "alu_shift,load_byte")
+    (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "256")
+-   (set_attr "neg_pool_range" "244")]
++   (set_attr "pool_range" "*,256")
++   (set_attr "neg_pool_range" "*,244")]
+ )
+ 
+ (define_insn "*arm_extendqisi_v6"
+@@ -4703,162 +4617,103 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
+-(define_insn "*thumb1_extendqisi2"
+-  [(set (match_operand:SI 0 "register_operand" "=l,l")
+-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))]
+-  "TARGET_THUMB1 && !arm_arch6"
+-  "*
+-  {
+-    rtx ops[3];
+-    rtx mem = XEXP (operands[1], 0);
+-    
+-    if (GET_CODE (mem) == CONST)
+-      mem = XEXP (mem, 0);
+-    
+-    if (GET_CODE (mem) == LABEL_REF)
+-      return \"ldr\\t%0, %1\";
+-
+-    if (GET_CODE (mem) == PLUS
+-        && GET_CODE (XEXP (mem, 0)) == LABEL_REF)
+-      return \"ldr\\t%0, %1\";
+-      
+-    if (which_alternative == 0)
+-      return \"ldrsb\\t%0, %1\";
+-      
+-    ops[0] = operands[0];
+-    
+-    if (GET_CODE (mem) == PLUS)
+-      {
+-        rtx a = XEXP (mem, 0);
+-	rtx b = XEXP (mem, 1);
+-	
+-        ops[1] = a;
+-        ops[2] = b;
+-
+-        if (GET_CODE (a) == REG)
+-	  {
+-	    if (GET_CODE (b) == REG)
+-              output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops);
+-            else if (REGNO (a) == REGNO (ops[0]))
+-	      {
+-                output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops);
+-		output_asm_insn (\"lsl\\t%0, %0, #24\", ops);
+-		output_asm_insn (\"asr\\t%0, %0, #24\", ops);
+-	      }
+-	    else
+-              output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
+-	  }
+-	else
+-          {
+-	    gcc_assert (GET_CODE (b) == REG);
+-            if (REGNO (b) == REGNO (ops[0]))
+-	      {
+-                output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops);
+-		output_asm_insn (\"lsl\\t%0, %0, #24\", ops);
+-		output_asm_insn (\"asr\\t%0, %0, #24\", ops);
+-	      }
+-	    else
+-              output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
+-          }
+-      }
+-    else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem))
+-      {
+-        output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops);
+-	output_asm_insn (\"lsl\\t%0, %0, #24\", ops);
+-	output_asm_insn (\"asr\\t%0, %0, #24\", ops);
+-      }
+-    else
+-      {
+-        ops[1] = mem;
+-        ops[2] = const0_rtx;
+-	
+-        output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
+-      }
+-    return \"\";
+-  }"
+-  [(set_attr "length" "2,6")
+-   (set_attr "type" "load_byte,load_byte")
+-   (set_attr "pool_range" "32,32")]
+-)
+-
+-(define_insn "*thumb1_extendqisi2_v6"
++(define_split
++  [(set (match_operand:SI 0 "register_operand" "")
++	(sign_extend:SI (match_operand:QI 1 "memory_operand" "")))]
++  "TARGET_THUMB1 && reload_completed"
++  [(set (match_dup 0) (match_dup 2))
++   (set (match_dup 0) (sign_extend:SI (match_dup 3)))]
++{
++  rtx addr = XEXP (operands[1], 0);
++
++  if (GET_CODE (addr) == CONST)
++    addr = XEXP (addr, 0);
++
++  if (GET_CODE (addr) == PLUS
++      && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1)))
++    /* No split necessary.  */
++    FAIL;
++
++  if (GET_CODE (addr) == PLUS
++      && !REG_P (XEXP (addr, 0)) && !REG_P (XEXP (addr, 1)))
++    FAIL;
++
++  if (reg_overlap_mentioned_p (operands[0], addr))
++    {
++      rtx t = gen_lowpart (QImode, operands[0]);
++      emit_move_insn (t, operands[1]);
++      emit_insn (gen_thumb1_extendqisi2 (operands[0], t));
++      DONE;
++    }
++
++  if (REG_P (addr))
++    {
++      addr = gen_rtx_PLUS (Pmode, addr, operands[0]);
++      operands[2] = const0_rtx;
++    }
++  else if (GET_CODE (addr) != PLUS)
++    FAIL;
++  else if (REG_P (XEXP (addr, 0)))
++    {
++      operands[2] = XEXP (addr, 1);
++      addr = gen_rtx_PLUS (Pmode, XEXP (addr, 0), operands[0]);
++    }
++  else
++    {
++      operands[2] = XEXP (addr, 0);
++      addr = gen_rtx_PLUS (Pmode, XEXP (addr, 1), operands[0]);
++    }
++
++  operands[3] = change_address (operands[1], QImode, addr);
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "register_operand" "")
++	(plus:SI (match_dup 0) (match_operand 1 "const_int_operand")))
++   (set (match_operand:SI 2 "register_operand" "") (const_int 0))
++   (set (match_operand:SI 3 "register_operand" "")
++	(sign_extend:SI (match_operand:QI 4 "memory_operand" "")))]
++  "TARGET_THUMB1
++   && GET_CODE (XEXP (operands[4], 0)) == PLUS
++   && rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0))
++   && rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1))
++   && (peep2_reg_dead_p (3, operands[0])
++       || rtx_equal_p (operands[0], operands[3]))
++   && (peep2_reg_dead_p (3, operands[2])
++       || rtx_equal_p (operands[2], operands[3]))"
++  [(set (match_dup 2) (match_dup 1))
++   (set (match_dup 3) (sign_extend:SI (match_dup 4)))]
++{
++  rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
++  operands[4] = change_address (operands[4], QImode, addr);
++})
++
++(define_insn "thumb1_extendqisi2"
+   [(set (match_operand:SI 0 "register_operand" "=l,l,l")
+ 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))]
+-  "TARGET_THUMB1 && arm_arch6"
+-  "*
+-  {
+-    rtx ops[3];
+-    rtx mem;
+-
+-    if (which_alternative == 0)
+-      return \"sxtb\\t%0, %1\";
+-
+-    mem = XEXP (operands[1], 0);
+-    
+-    if (GET_CODE (mem) == CONST)
+-      mem = XEXP (mem, 0);
+-    
+-    if (GET_CODE (mem) == LABEL_REF)
+-      return \"ldr\\t%0, %1\";
+-
+-    if (GET_CODE (mem) == PLUS
+-        && GET_CODE (XEXP (mem, 0)) == LABEL_REF)
+-      return \"ldr\\t%0, %1\";
+-      
+-    if (which_alternative == 0)
+-      return \"ldrsb\\t%0, %1\";
+-      
+-    ops[0] = operands[0];
+-    
+-    if (GET_CODE (mem) == PLUS)
+-      {
+-        rtx a = XEXP (mem, 0);
+-	rtx b = XEXP (mem, 1);
+-	
+-        ops[1] = a;
+-        ops[2] = b;
+-
+-        if (GET_CODE (a) == REG)
+-	  {
+-	    if (GET_CODE (b) == REG)
+-              output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops);
+-            else if (REGNO (a) == REGNO (ops[0]))
+-	      {
+-                output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops);
+-		output_asm_insn (\"sxtb\\t%0, %0\", ops);
+-	      }
+-	    else
+-              output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
+-	  }
+-	else
+-          {
+-	    gcc_assert (GET_CODE (b) == REG);
+-            if (REGNO (b) == REGNO (ops[0]))
+-	      {
+-                output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops);
+-		output_asm_insn (\"sxtb\\t%0, %0\", ops);
+-	      }
+-	    else
+-              output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
+-          }
+-      }
+-    else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem))
+-      {
+-        output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops);
+-	output_asm_insn (\"sxtb\\t%0, %0\", ops);
+-      }
+-    else
+-      {
+-        ops[1] = mem;
+-        ops[2] = const0_rtx;
+-	
+-        output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
+-      }
+-    return \"\";
+-  }"
+-  [(set_attr "length" "2,2,4")
+-   (set_attr "type" "alu_shift,load_byte,load_byte")
+-   (set_attr "pool_range" "*,32,32")]
++  "TARGET_THUMB1"
++{
++  rtx addr;
++
++  if (which_alternative == 0 && arm_arch6)
++    return "sxtb\\t%0, %1";
++  if (which_alternative == 0)
++    return "#";
++
++  addr = XEXP (operands[1], 0);
++  if (GET_CODE (addr) == PLUS
++      && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1)))
++    return "ldrsb\\t%0, %1";
++      
++  return "#";
++}
++  [(set_attr_alternative "length"
++			 [(if_then_else (eq_attr "is_arch6" "yes")
++					(const_int 2) (const_int 4))
++			  (const_int 2)
++			  (if_then_else (eq_attr "is_arch6" "yes")
++					(const_int 4) (const_int 6))])
++   (set_attr "type" "alu_shift,load_byte,load_byte")]
+ )
+ 
+ (define_expand "extendsfdf2"
+@@ -6784,6 +6639,30 @@
+     operands[2] = force_reg (SImode, operands[2]);
+   ")
+ 
++;; A pattern to recognize a special situation and optimize for it.
++;; On the thumb, zero-extension from memory is preferrable to sign-extension
++;; due to the available addressing modes.  Hence, convert a signed comparison
++;; with zero into an unsigned comparison with 127 if possible.
++(define_expand "cbranchqi4"
++  [(set (pc) (if_then_else
++	      (match_operator 0 "lt_ge_comparison_operator"
++	       [(match_operand:QI 1 "memory_operand" "")
++	        (match_operand:QI 2 "const0_operand" "")])
++	      (label_ref (match_operand 3 "" ""))
++	      (pc)))]
++  "TARGET_THUMB1"
++{
++  rtx xops[4];
++  xops[1] = gen_reg_rtx (SImode);
++  emit_insn (gen_zero_extendqisi2 (xops[1], operands[1]));
++  xops[2] = GEN_INT (127);
++  xops[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]) == GE ? LEU : GTU,
++			    VOIDmode, xops[1], xops[2]);
++  xops[3] = operands[3];
++  emit_insn (gen_cbranchsi4 (xops[0], xops[1], xops[2], xops[3]));
++  DONE;
++})
++
+ (define_expand "cbranchsf4"
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "arm_comparison_operator"
+@@ -6849,7 +6728,7 @@
+    }"
+ )
+ 
+-(define_insn "*cbranchsi4_insn"
++(define_insn "cbranchsi4_insn"
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "arm_comparison_operator"
+ 	       [(match_operand:SI 1 "s_register_operand" "l,*h")
+@@ -6858,7 +6737,20 @@
+ 	      (pc)))]
+   "TARGET_THUMB1"
+   "*
+-  output_asm_insn (\"cmp\\t%1, %2\", operands);
++  rtx t = prev_nonnote_insn (insn);
++  if (t != NULL_RTX
++      && INSN_P (t)
++      && INSN_CODE (t) == CODE_FOR_cbranchsi4_insn)
++    {
++      t = XEXP (SET_SRC (PATTERN (t)), 0);
++      if (!rtx_equal_p (XEXP (t, 0), operands[1])
++	  || !rtx_equal_p (XEXP (t, 1), operands[2]))
++	t = NULL_RTX;
++    }
++  else
++    t = NULL_RTX;
++  if (t == NULL_RTX)
++    output_asm_insn (\"cmp\\t%1, %2\", operands);
+ 
+   switch (get_attr_length (insn))
+     {
+@@ -7674,15 +7566,15 @@
+ 	(if_then_else
+ 	 (match_operator 4 "arm_comparison_operator"
+ 	  [(plus:SI
+-	    (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1")
+-	    (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ"))
++	    (match_operand:SI 2 "s_register_operand" "%0,l,*l,1,1,1")
++	    (match_operand:SI 3 "reg_or_int_operand" "IJ,lL,*l,lIJ,lIJ,lIJ"))
+ 	   (const_int 0)])
+ 	 (label_ref (match_operand 5 "" ""))
+ 	 (pc)))
+    (set
+     (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m")
+     (plus:SI (match_dup 2) (match_dup 3)))
+-   (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))]
++   (clobber (match_scratch:SI 1 "=X,X,l,l,&l,&l"))]
+   "TARGET_THUMB1
+    && (GET_CODE (operands[4]) == EQ
+        || GET_CODE (operands[4]) == NE
+@@ -7692,8 +7584,7 @@
+    {
+      rtx cond[3];
+ 
+-     
+-     cond[0] = (which_alternative < 3) ? operands[0] : operands[1];
++     cond[0] = (which_alternative < 2) ? operands[0] : operands[1];
+      cond[1] = operands[2];
+      cond[2] = operands[3];
+ 
+@@ -7702,13 +7593,13 @@
+      else
+        output_asm_insn (\"add\\t%0, %1, %2\", cond);
+ 
+-     if (which_alternative >= 3
++     if (which_alternative >= 2
+ 	 && which_alternative < 4)
+        output_asm_insn (\"mov\\t%0, %1\", operands);
+      else if (which_alternative >= 4)
+        output_asm_insn (\"str\\t%1, %0\", operands);
+ 
+-     switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0))
++     switch (get_attr_length (insn) - ((which_alternative >= 2) ? 2 : 0))
+        {
+ 	 case 4:
+ 	   return \"b%d4\\t%l5\";
+@@ -7722,7 +7613,7 @@
+   [(set (attr "far_jump")
+         (if_then_else
+ 	    (ior (and (lt (symbol_ref ("which_alternative"))
+-	                  (const_int 3))
++	                  (const_int 2))
+ 		      (eq_attr "length" "8"))
+ 		 (eq_attr "length" "10"))
+ 	    (const_string "yes")
+@@ -7730,7 +7621,7 @@
+    (set (attr "length")
+      (if_then_else
+        (lt (symbol_ref ("which_alternative"))
+-		       (const_int 3))
++		       (const_int 2))
+        (if_then_else
+ 	 (and (ge (minus (match_dup 5) (pc)) (const_int -250))
+ 	      (le (minus (match_dup 5) (pc)) (const_int 256)))
+@@ -9483,41 +9374,117 @@
+    (set_attr "length" "4,8")]
+ )
+ 
+-(define_insn "*compare_scc"
++; A series of splitters for the compare_scc pattern below.  Note that
++; order is important.
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(lt:SI (match_operand:SI 1 "s_register_operand" "")
++	       (const_int 0)))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_32BIT && reload_completed"
++  [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 31)))])
++
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(ge:SI (match_operand:SI 1 "s_register_operand" "")
++	       (const_int 0)))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_32BIT && reload_completed"
++  [(set (match_dup 0) (not:SI (match_dup 1)))
++   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))])
++
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(eq:SI (match_operand:SI 1 "s_register_operand" "")
++	       (const_int 0)))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_32BIT && reload_completed"
++  [(parallel
++    [(set (reg:CC CC_REGNUM)
++	  (compare:CC (const_int 1) (match_dup 1)))
++     (set (match_dup 0)
++	  (minus:SI (const_int 1) (match_dup 1)))])
++   (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0))
++	      (set (match_dup 0) (const_int 0)))])
++
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(ne:SI (match_operand:SI 1 "s_register_operand" "")
++	       (match_operand:SI 2 "const_int_operand" "")))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_32BIT && reload_completed"
++  [(parallel
++    [(set (reg:CC CC_REGNUM)
++	  (compare:CC (match_dup 1) (match_dup 2)))
++     (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))])
++   (cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0))
++	      (set (match_dup 0) (const_int 1)))]
++{
++  operands[3] = GEN_INT (-INTVAL (operands[2]));
++})
++
++(define_split
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(ne:SI (match_operand:SI 1 "s_register_operand" "")
++	       (match_operand:SI 2 "arm_add_operand" "")))
++   (clobber (reg:CC CC_REGNUM))]
++  "TARGET_32BIT && reload_completed"
++  [(parallel
++    [(set (reg:CC_NOOV CC_REGNUM)
++	  (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2))
++			   (const_int 0)))
++     (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
++   (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0))
++	      (set (match_dup 0) (const_int 1)))])
++
++(define_insn_and_split "*compare_scc"
+   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ 	(match_operator:SI 1 "arm_comparison_operator"
+ 	 [(match_operand:SI 2 "s_register_operand" "r,r")
+ 	  (match_operand:SI 3 "arm_add_operand" "rI,L")]))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM"
+-  "*
+-    if (operands[3] == const0_rtx)
+-      {
+-	if (GET_CODE (operands[1]) == LT)
+-	  return \"mov\\t%0, %2, lsr #31\";
+-
+-	if (GET_CODE (operands[1]) == GE)
+-	  return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\";
+-
+-	if (GET_CODE (operands[1]) == EQ)
+-	  return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\";
+-      }
+-
+-    if (GET_CODE (operands[1]) == NE)
+-      {
+-        if (which_alternative == 1)
+-	  return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\";
+-        return \"subs\\t%0, %2, %3\;movne\\t%0, #1\";
+-      }
+-    if (which_alternative == 1)
+-      output_asm_insn (\"cmn\\t%2, #%n3\", operands);
+-    else
+-      output_asm_insn (\"cmp\\t%2, %3\", operands);
+-    return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
+-  "
+-  [(set_attr "conds" "clob")
+-   (set_attr "length" "12")]
+-)
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 3)))
++   (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))
++   (cond_exec (match_dup 5) (set (match_dup 0) (const_int 1)))]
++{
++  rtx tmp1;
++  enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]),
++					   operands[2], operands[3]);
++  enum rtx_code rc = GET_CODE (operands[1]);
++
++  tmp1 = gen_rtx_REG (mode, CC_REGNUM);
++
++  operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
++  if (mode == CCFPmode || mode == CCFPEmode)
++    rc = reverse_condition_maybe_unordered (rc);
++  else
++    rc = reverse_condition (rc);
++  operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
++})
++
++;; Attempt to improve the sequence generated by the compare_scc splitters
++;; not to use conditional execution.
++(define_peephole2
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC (match_operand:SI 1 "register_operand" "")
++		    (match_operand:SI 2 "arm_rhs_operand" "")))
++   (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
++	      (set (match_operand:SI 0 "register_operand" "") (const_int 0)))
++   (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
++	      (set (match_dup 0) (const_int 1)))
++   (match_scratch:SI 3 "r")]
++  "TARGET_32BIT"
++  [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
++   (parallel
++    [(set (reg:CC CC_REGNUM)
++	  (compare:CC (const_int 0) (match_dup 3)))
++     (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
++   (set (match_dup 0)
++	(plus:SI (plus:SI (match_dup 0) (match_dup 3))
++		 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))])
+ 
+ (define_insn "*cond_move"
+   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-08-31 09:40:16 +0000
++++ new/gcc/config/arm/predicates.md	2010-08-31 10:00:27 +0000
+@@ -115,6 +115,10 @@
+   (and (match_code "const_int")
+        (match_test "const_ok_for_arm (~INTVAL (op))")))
+ 
++(define_predicate "const0_operand"
++  (and (match_code "const_int")
++       (match_test "INTVAL (op) == 0")))
++
+ ;; Something valid on the RHS of an ARM data-processing instruction
+ (define_predicate "arm_rhs_operand"
+   (ior (match_operand 0 "s_register_operand")
+@@ -233,6 +237,9 @@
+ 			 && (TARGET_FPA || TARGET_VFP)")
+             (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
+ 
++(define_special_predicate "lt_ge_comparison_operator"
++  (match_code "lt,ge"))
++
+ (define_special_predicate "minmax_operator"
+   (and (match_code "smin,smax,umin,umax")
+        (match_test "mode == GET_MODE (op)")))
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-08-31 09:40:16 +0000
++++ new/gcc/config/arm/thumb2.md	2010-08-31 10:00:27 +0000
+@@ -599,42 +599,6 @@
+    (set_attr "length" "6,10")]
+ )
+ 
+-(define_insn "*thumb2_compare_scc"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+-	(match_operator:SI 1 "arm_comparison_operator"
+-	 [(match_operand:SI 2 "s_register_operand" "r,r")
+-	  (match_operand:SI 3 "arm_add_operand" "rI,L")]))
+-   (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_THUMB2"
+-  "*
+-    if (operands[3] == const0_rtx)
+-      {
+-	if (GET_CODE (operands[1]) == LT)
+-	  return \"lsr\\t%0, %2, #31\";
+-
+-	if (GET_CODE (operands[1]) == GE)
+-	  return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
+-
+-	if (GET_CODE (operands[1]) == EQ)
+-	  return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
+-      }
+-
+-    if (GET_CODE (operands[1]) == NE)
+-      {
+-        if (which_alternative == 1)
+-	  return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
+-        return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
+-      }
+-    if (which_alternative == 1)
+-      output_asm_insn (\"cmn\\t%2, #%n3\", operands);
+-    else
+-      output_asm_insn (\"cmp\\t%2, %3\", operands);
+-    return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
+-  "
+-  [(set_attr "conds" "clob")
+-   (set_attr "length" "14")]
+-)
+-
+ (define_insn "*thumb2_cond_move"
+   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
+ 	(if_then_else:SI (match_operator 3 "equality_operator"
+
+=== added file 'gcc/testsuite/gcc.c-torture/execute/pr40657.c'
+--- old/gcc/testsuite/gcc.c-torture/execute/pr40657.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/execute/pr40657.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,23 @@
++/* Verify that that Thumb-1 epilogue size optimization does not clobber the
++   return value.  */
++
++long long v = 0x123456789abc;
++
++__attribute__((noinline)) void bar (int *x)
++{
++  asm volatile ("" : "=m" (x) ::);
++}
++
++__attribute__((noinline)) long long foo()
++{
++  int x;
++  bar(&x);
++  return v;
++}
++
++int main ()
++{
++  if (foo () != v)
++    abort ();
++  exit (0);
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr40657-1.c'
+--- old/gcc/testsuite/gcc.target/arm/pr40657-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr40657-1.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,13 @@
++/* { dg-options "-Os -march=armv5te -mthumb" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-final { scan-assembler "pop.*r1.*pc" } } */
++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */
++/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */
++
++extern void bar(int*);
++int foo()
++{
++  int x;
++  bar(&x);
++  return x;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr40657-2.c'
+--- old/gcc/testsuite/gcc.target/arm/pr40657-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr40657-2.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,20 @@
++/* { dg-options "-Os -march=armv4t -mthumb" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */
++/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */
++
++/* Here, we test that if there's a pop of r[4567] in the epilogue,
++   add sp,sp,#12 is removed and replaced by three additional pops
++   of lower-numbered regs.  */
++
++extern void bar(int*);
++
++int t1, t2, t3, t4, t5;
++int foo()
++{
++  int i,j,k,x = 0;
++  for (i = 0; i < t1; i++)
++    for (j = 0; j < t2; j++)
++	  bar(&x);
++  return x;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr42172-1.c'
+--- old/gcc/testsuite/gcc.target/arm/pr42172-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr42172-1.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,19 @@
++/* { dg-options "-O2" }  */
++
++struct A {
++  unsigned int f1 : 3;
++  unsigned int f2 : 3;
++  unsigned int f3 : 1;
++  unsigned int f4 : 1;
++
++};
++
++void init_A (struct A *this)
++{
++  this->f1 = 0;
++  this->f2 = 1;
++  this->f3 = 0;
++  this->f4 = 0;
++}
++
++/* { dg-final { scan-assembler-times "ldr" 1 } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr42835.c'
+--- old/gcc/testsuite/gcc.target/arm/pr42835.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr42835.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-mthumb -Os" }  */
++/* { dg-require-effective-target arm_thumb2_ok } */
++
++int foo(int *p, int i)
++{
++  return( (i < 0 && *p == 1)
++	  || (i > 0 && *p == 2) );
++}
++
++/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */
++/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-mthumb -Os" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++
++int ldrb(unsigned char* p)
++{
++  if (p[8] <= 0x7F)
++    return 2;
++  else
++    return 5;
++}
++
++
++/* { dg-final { scan-assembler "127" } } */
++/* { dg-final { scan-assembler "bhi" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb-comparisons.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb-comparisons.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb-comparisons.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-mthumb -Os" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++
++int foo(char ch)
++{
++  switch (ch) {
++    case '-':
++    case '?':
++    case '/':
++    case 99:
++        return 1;
++    default:
++        return 0;
++  }
++}
++
++/* { dg-final { scan-assembler-times "cmp\[\\t \]*r.,\[\\t \]*#63" 1 } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb-stackframe.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb-stackframe.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb-stackframe.c	2010-08-31 10:00:27 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-mthumb -Os" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++
++extern void bar(int*);
++int foo()
++{
++  int x;
++  bar(&x);
++  return x;
++}
++
++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch
new file mode 100644
index 0000000000..b7b6d88a04
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch
@@ -0,0 +1,2985 @@
+2010-08-31  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-04-14  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/21803
+	gcc/
+	* ifcvt.c (cond_exec_process_if_block): Look for identical sequences
+	at the start and end of the then/else blocks, and omit them from the
+	conversion.
+	* cfgcleanup.c (flow_find_cross_jump): No longer static.  Remove MODE
+	argument; all callers changed.  Pass zero to old_insns_match_p instead.
+	(flow_find_head_matching_sequence): New function.
+	(old_insns_match_p): Check REG_EH_REGION notes for calls.
+	* basic-block.h (flow_find_cross_jump,
+	flow_find_head_matching_sequence): Declare functions.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42496.c: New test.
+
+	2010-04-22  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR middle-end/29274
+	gcc/
+	* tree-pass.h (pass_optimize_widening_mul): Declare.
+	* tree-ssa-math-opts.c (execute_optimize_widening_mul,
+	gate_optimize_widening_mul): New static functions.
+	(pass_optimize_widening_mul): New.
+	* expr.c (expand_expr_real_2) <case WIDEN_MULT_EXPR>: New case.
+	<case MULT_EXPR>: Remove support for widening multiplies.
+	* tree.def (WIDEN_MULT_EXPR): Tweak comment.
+	* cfgexpand.c (expand_debug_expr) <case WIDEN_MULT_EXPR>: Use
+	simplify_gen_unary rather than directly building extensions.
+	* tree-cfg.c (verify_gimple_assign_binary): Add tests for
+	WIDEN_MULT_EXPR.
+	* expmed.c (expand_widening_mult): New function.
+	* passes.c (init_optimization_passes): Add pass_optimize_widening_mul.
+	* optabs.h (expand_widening_mult): Declare.
+
+	gcc/testsuite/
+	* gcc.target/i386/wmul-1.c: New test.
+	* gcc.target/i386/wmul-2.c: New test.
+	* gcc.target/bfin/wmul-1.c: New test.
+	* gcc.target/bfin/wmul-2.c: New test.	
+	* gcc.target/arm/wmul-1.c: New test.
+	* gcc.target/arm/wmul-2.c: New test.
+
+	2010-04-24  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR tree-optimization/41442
+	gcc/
+	* fold-const.c (merge_truthop_with_opposite_arm): New function.
+	(fold_binary_loc): Call it.
+
+	gcc/testsuite/
+	* gcc.target/i386/pr41442.c: New test.
+
+	2010-04-29  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/42895
+	gcc/
+	* doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from
+	ORDER_REGS_FOR_LOCAL_ALLOC.  All instances of this macro changed.
+	(HONOR_REG_ALLOC_ORDER): Describe new macro.
+	* ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined.
+	* ira-color.c (assign_hard_reg): Take prologue/epilogue costs into
+	account only if HONOR_REG_ALLOC_ORDER is not defined.
+	* config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define.
+	* system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison.
+
+	2010-05-04  Mikael Pettersson  <mikpe@it.uu.se>
+
+	PR bootstrap/43964
+	gcc/
+	* ira-color.c (assign_hard_reg): Declare rclass and add_cost
+	only if HONOR_REG_ALLOC_ORDER is not defined.
+
+	2010-06-04  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR rtl-optimization/39871
+	PR rtl-optimization/40615
+	PR rtl-optimization/42500
+	PR rtl-optimization/42502
+	gcc/
+	* ira.c (init_reg_equiv_memory_loc: New function.
+	(ira): Call it twice.
+	* reload.h (calculate_elim_costs_all_insns): Declare.
+	* ira-costs.c: Include "reload.h".
+	(regno_equiv_gains): New static variable.
+	(init_costs): Allocate it.
+	(finish_costs): Free it.
+	(ira_costs): Call calculate_elim_costs_all_insns.
+	(find_costs_and_classes): Take estimated elimination costs
+	into account.
+	(ira_adjust_equiv_reg_cost): New function.
+	* ira.h (ira_adjust_equiv_reg_cost): Declare it.
+	* reload1.c (init_eliminable_invariants, free_reg_equiv,
+	elimination_costs_in_insn, note_reg_elim_costly): New static functions.
+	(elim_bb): New static variable.
+	(reload): Move code out of here into init_eliminable_invariants and
+	free_reg_equiv.  Call them.
+	(calculate_elim_costs_all_insns): New function.
+	(eliminate_regs_1): Declare.  Add extra arg FOR_COSTS;
+	all callers changed.  If FOR_COSTS is true, don't call alter_reg,
+	but call note_reg_elim_costly if we turned a valid memory address
+	into an invalid one.
+	* Makefile.in (ira-costs.o): Depend on reload.h.
+
+	gcc/testsuite/
+	* gcc.target/arm/eliminate.c: New test.
+
+	2010-06-09  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (thumb2_reorg): New function.
+	(arm_reorg): Call it.
+	* config/arm/thumb2.md (define_peephole2 for flag clobbering
+	arithmetic operations): Delete.
+
+	2010-06-12  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (thumb2_reorg): Fix errors in previous change.
+
+	2010-06-17  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR rtl-optimization/39871
+	gcc/
+	* reload1.c (init_eliminable_invariants): For flag_pic, disable
+	equivalences only for constants that aren't LEGITIMATE_PIC_OPERAND_P.
+	(function_invariant_p): Rule out a plus of frame or arg pointer with
+	a SYMBOL_REF.
+	* ira.c (find_reg_equiv_invariant_const): Likewise.
+
+	2010-06-18  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/40900
+	gcc/
+	* expr.c (expand_expr_real_1) <SSA_NAME>: Fix long line.  Save the
+	original expression for later reuse.
+	<expand_decl_rtl>: Use promote_function_mode to compute the signedness
+	of the promoted RTL for a SSA_NAME on the LHS of a call statement.
+
+	2010-06-18  Bernd Schmidt  <bernds@codesourcery.com>
+	gcc/testsuite/
+	* gcc.target/arm/pr40900.c: New test.
+
+	2010-06-30  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR tree-optimization/39799
+	gcc/
+	* tree-inline.c (remap_ssa_name): Initialize variable only if
+	SSA_NAME_OCCURS_IN_ABNORMAL_PHI.
+	* tree-ssa.c (warn_uninit): Avoid emitting an unnecessary message.
+
+	gcc/testsuite/
+	* c-c++-common/uninit-17.c: New test.
+
+	2010-07-25  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR target/44484
+	gcc/
+	* config/sparc/predicates.md (memory_reg_operand): Delete.
+	* config/sparc/sync.md (sync_compare_and_swap): Minor tweaks.
+	(*sync_compare_and_swap): Encode the address form in the pattern.
+	(*sync_compare_and_swapdi_v8plus): Likewise.
+
+ 2010-08-29  Chung-Lin Tang  <cltang@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/Makefile.in'
+Index: gcc-4_5-branch/gcc/Makefile.in
+===================================================================
+--- gcc-4_5-branch.orig/gcc/Makefile.in	2012-03-06 12:11:29.000000000 -0800
++++ gcc-4_5-branch/gcc/Makefile.in	2012-03-06 12:14:01.024439210 -0800
+@@ -3197,7 +3197,7 @@
+ ira-costs.o: ira-costs.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
+    hard-reg-set.h $(RTL_H) $(EXPR_H) $(TM_P_H) $(FLAGS_H) $(BASIC_BLOCK_H) \
+    $(REGS_H) addresses.h insn-config.h $(RECOG_H) $(TOPLEV_H) $(TARGET_H) \
+-   $(PARAMS_H) $(IRA_INT_H)
++   $(PARAMS_H) $(IRA_INT_H) reload.h
+ ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
+    $(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \
+    insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \
+Index: gcc-4_5-branch/gcc/basic-block.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/basic-block.h	2012-03-06 12:11:33.000000000 -0800
++++ gcc-4_5-branch/gcc/basic-block.h	2012-03-06 12:14:01.024439210 -0800
+@@ -894,6 +894,10 @@
+ 
+ /* In cfgcleanup.c.  */
+ extern bool cleanup_cfg (int);
++extern int flow_find_cross_jump (basic_block, basic_block, rtx *, rtx *);
++extern int flow_find_head_matching_sequence (basic_block, basic_block,
++					     rtx *, rtx *, int);
++
+ extern bool delete_unreachable_blocks (void);
+ 
+ extern bool mark_dfs_back_edges (void);
+Index: gcc-4_5-branch/gcc/cfgcleanup.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/cfgcleanup.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/cfgcleanup.c	2012-03-06 12:14:01.028439167 -0800
+@@ -68,7 +68,6 @@
+ static bool try_crossjump_to_edge (int, edge, edge);
+ static bool try_crossjump_bb (int, basic_block);
+ static bool outgoing_edges_match (int, basic_block, basic_block);
+-static int flow_find_cross_jump (int, basic_block, basic_block, rtx *, rtx *);
+ static bool old_insns_match_p (int, rtx, rtx);
+ 
+ static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block);
+@@ -977,13 +976,27 @@
+      be filled that clobbers a parameter expected by the subroutine.
+ 
+      ??? We take the simple route for now and assume that if they're
+-     equal, they were constructed identically.  */
++     equal, they were constructed identically.
+ 
+-  if (CALL_P (i1)
+-      && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1),
++     Also check for identical exception regions.  */
++
++  if (CALL_P (i1))
++    {
++      /* Ensure the same EH region.  */
++      rtx n1 = find_reg_note (i1, REG_EH_REGION, 0);
++      rtx n2 = find_reg_note (i2, REG_EH_REGION, 0);
++
++      if (!n1 && n2)
++	return false;
++
++      if (n1 && (!n2 || XEXP (n1, 0) != XEXP (n2, 0)))
++	return false;
++
++      if (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1),
+ 			CALL_INSN_FUNCTION_USAGE (i2))
+-	  || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2)))
+-    return false;
++	  || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2))
++	return false;
++    }
+ 
+ #ifdef STACK_REGS
+   /* If cross_jump_death_matters is not 0, the insn's mode
+@@ -1022,6 +1035,29 @@
+   return false;
+ }
+ 
++/* When comparing insns I1 and I2 in flow_find_cross_jump or
++   flow_find_head_matching_sequence, ensure the notes match.  */
++
++static void
++merge_notes (rtx i1, rtx i2)
++{
++  /* If the merged insns have different REG_EQUAL notes, then
++     remove them.  */
++  rtx equiv1 = find_reg_equal_equiv_note (i1);
++  rtx equiv2 = find_reg_equal_equiv_note (i2);
++
++  if (equiv1 && !equiv2)
++    remove_note (i1, equiv1);
++  else if (!equiv1 && equiv2)
++    remove_note (i2, equiv2);
++  else if (equiv1 && equiv2
++	   && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0)))
++    {
++      remove_note (i1, equiv1);
++      remove_note (i2, equiv2);
++    }
++}
++
+ /* Look through the insns at the end of BB1 and BB2 and find the longest
+    sequence that are equivalent.  Store the first insns for that sequence
+    in *F1 and *F2 and return the sequence length.
+@@ -1029,9 +1065,8 @@
+    To simplify callers of this function, if the blocks match exactly,
+    store the head of the blocks in *F1 and *F2.  */
+ 
+-static int
+-flow_find_cross_jump (int mode ATTRIBUTE_UNUSED, basic_block bb1,
+-		      basic_block bb2, rtx *f1, rtx *f2)
++int
++flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2)
+ {
+   rtx i1, i2, last1, last2, afterlast1, afterlast2;
+   int ninsns = 0;
+@@ -1071,7 +1106,7 @@
+       if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2))
+ 	break;
+ 
+-      if (!old_insns_match_p (mode, i1, i2))
++      if (!old_insns_match_p (0, i1, i2))
+ 	break;
+ 
+       merge_memattrs (i1, i2);
+@@ -1079,21 +1114,7 @@
+       /* Don't begin a cross-jump with a NOTE insn.  */
+       if (INSN_P (i1))
+ 	{
+-	  /* If the merged insns have different REG_EQUAL notes, then
+-	     remove them.  */
+-	  rtx equiv1 = find_reg_equal_equiv_note (i1);
+-	  rtx equiv2 = find_reg_equal_equiv_note (i2);
+-
+-	  if (equiv1 && !equiv2)
+-	    remove_note (i1, equiv1);
+-	  else if (!equiv1 && equiv2)
+-	    remove_note (i2, equiv2);
+-	  else if (equiv1 && equiv2
+-		   && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0)))
+-	    {
+-	      remove_note (i1, equiv1);
+-	      remove_note (i2, equiv2);
+-	    }
++	  merge_notes (i1, i2);
+ 
+ 	  afterlast1 = last1, afterlast2 = last2;
+ 	  last1 = i1, last2 = i2;
+@@ -1135,6 +1156,97 @@
+   return ninsns;
+ }
+ 
++/* Like flow_find_cross_jump, except start looking for a matching sequence from
++   the head of the two blocks.  Do not include jumps at the end.
++   If STOP_AFTER is nonzero, stop after finding that many matching
++   instructions.  */
++
++int
++flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1,
++				  rtx *f2, int stop_after)
++{
++  rtx i1, i2, last1, last2, beforelast1, beforelast2;
++  int ninsns = 0;
++  edge e;
++  edge_iterator ei;
++  int nehedges1 = 0, nehedges2 = 0;
++
++  FOR_EACH_EDGE (e, ei, bb1->succs)
++    if (e->flags & EDGE_EH)
++      nehedges1++;
++  FOR_EACH_EDGE (e, ei, bb2->succs)
++    if (e->flags & EDGE_EH)
++      nehedges2++;
++
++  i1 = BB_HEAD (bb1);
++  i2 = BB_HEAD (bb2);
++  last1 = beforelast1 = last2 = beforelast2 = NULL_RTX;
++
++  while (true)
++    {
++
++      /* Ignore notes.  */
++      while (!NONDEBUG_INSN_P (i1) && i1 != BB_END (bb1))
++	i1 = NEXT_INSN (i1);
++
++      while (!NONDEBUG_INSN_P (i2) && i2 != BB_END (bb2))
++	i2 = NEXT_INSN (i2);
++
++      if (NOTE_P (i1) || NOTE_P (i2)
++	  || JUMP_P (i1) || JUMP_P (i2))
++	break;
++
++      /* A sanity check to make sure we're not merging insns with different
++	 effects on EH.  If only one of them ends a basic block, it shouldn't
++	 have an EH edge; if both end a basic block, there should be the same
++	 number of EH edges.  */
++      if ((i1 == BB_END (bb1) && i2 != BB_END (bb2)
++	   && nehedges1 > 0)
++	  || (i2 == BB_END (bb2) && i1 != BB_END (bb1)
++	      && nehedges2 > 0)
++	  || (i1 == BB_END (bb1) && i2 == BB_END (bb2)
++	      && nehedges1 != nehedges2))
++	break;
++
++      if (!old_insns_match_p (0, i1, i2))
++	break;
++
++      merge_memattrs (i1, i2);
++
++      /* Don't begin a cross-jump with a NOTE insn.  */
++      if (INSN_P (i1))
++	{
++	  merge_notes (i1, i2);
++
++	  beforelast1 = last1, beforelast2 = last2;
++	  last1 = i1, last2 = i2;
++	  ninsns++;
++	}
++
++      if (i1 == BB_END (bb1) || i2 == BB_END (bb2)
++	  || (stop_after > 0 && ninsns == stop_after))
++	break;
++
++      i1 = NEXT_INSN (i1);
++      i2 = NEXT_INSN (i2);
++    }
++
++#ifdef HAVE_cc0
++  /* Don't allow a compare to be shared by cross-jumping unless the insn
++     after the compare is also shared.  */
++  if (ninsns && reg_mentioned_p (cc0_rtx, last1) && sets_cc0_p (last1))
++    last1 = beforelast1, last2 = beforelast2, ninsns--;
++#endif
++
++  if (ninsns)
++    {
++      *f1 = last1;
++      *f2 = last2;
++    }
++
++  return ninsns;
++}
++
+ /* Return true iff outgoing edges of BB1 and BB2 match, together with
+    the branch instruction.  This means that if we commonize the control
+    flow before end of the basic block, the semantic remains unchanged.
+@@ -1503,7 +1615,7 @@
+     return false;
+ 
+   /* ... and part the second.  */
+-  nmatch = flow_find_cross_jump (mode, src1, src2, &newpos1, &newpos2);
++  nmatch = flow_find_cross_jump (src1, src2, &newpos1, &newpos2);
+ 
+   /* Don't proceed with the crossjump unless we found a sufficient number
+      of matching instructions or the 'from' block was totally matched
+Index: gcc-4_5-branch/gcc/cfgexpand.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/cfgexpand.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/cfgexpand.c	2012-03-06 12:14:01.028439167 -0800
+@@ -3033,14 +3033,15 @@
+       if (SCALAR_INT_MODE_P (GET_MODE (op0))
+ 	  && SCALAR_INT_MODE_P (mode))
+ 	{
++	  enum machine_mode inner_mode = GET_MODE (op0);
+ 	  if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0))))
+-	    op0 = gen_rtx_ZERO_EXTEND (mode, op0);
++	    op0 = simplify_gen_unary (ZERO_EXTEND, mode, op0, inner_mode);
+ 	  else
+-	    op0 = gen_rtx_SIGN_EXTEND (mode, op0);
++	    op0 = simplify_gen_unary (SIGN_EXTEND, mode, op0, inner_mode);
+ 	  if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 1))))
+-	    op1 = gen_rtx_ZERO_EXTEND (mode, op1);
++	    op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode);
+ 	  else
+-	    op1 = gen_rtx_SIGN_EXTEND (mode, op1);
++	    op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode);
+ 	  return gen_rtx_MULT (mode, op0, op1);
+ 	}
+       return NULL;
+Index: gcc-4_5-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.c	2012-03-06 12:11:35.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm.c	2012-03-06 12:14:01.032439183 -0800
+@@ -8096,8 +8096,6 @@
+ static bool
+ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
+ {
+-  rtx i_pat, d_pat;
+-
+   /* Some true dependencies can have a higher cost depending
+      on precisely how certain input operands are used.  */
+   if (REG_NOTE_KIND (link) == 0
+@@ -12146,6 +12144,60 @@
+   return result;
+ }
+ 
++/* Convert instructions to their cc-clobbering variant if possible, since
++   that allows us to use smaller encodings.  */
++
++static void
++thumb2_reorg (void)
++{
++  basic_block bb;
++  regset_head live;
++
++  INIT_REG_SET (&live);
++
++  /* We are freeing block_for_insn in the toplev to keep compatibility
++     with old MDEP_REORGS that are not CFG based.  Recompute it now.  */
++  compute_bb_for_insn ();
++  df_analyze ();
++
++  FOR_EACH_BB (bb)
++    {
++      rtx insn;
++      COPY_REG_SET (&live, DF_LR_OUT (bb));
++      df_simulate_initialize_backwards (bb, &live);
++      FOR_BB_INSNS_REVERSE (bb, insn)
++	{
++	  if (NONJUMP_INSN_P (insn)
++	      && !REGNO_REG_SET_P (&live, CC_REGNUM))
++	    {
++	      rtx pat = PATTERN (insn);
++	      if (GET_CODE (pat) == SET
++		  && low_register_operand (XEXP (pat, 0), SImode)
++		  && thumb_16bit_operator (XEXP (pat, 1), SImode)
++		  && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode)
++		  && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode))
++		{
++		  rtx dst = XEXP (pat, 0);
++		  rtx src = XEXP (pat, 1);
++		  rtx op0 = XEXP (src, 0);
++		  if (rtx_equal_p (dst, op0)
++		      || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
++		    {
++		      rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
++		      rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
++		      rtvec vec = gen_rtvec (2, pat, clobber);
++		      PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
++		      INSN_CODE (insn) = -1;
++		    }
++		}
++	    }
++	  if (NONDEBUG_INSN_P (insn))
++	    df_simulate_one_insn_backwards (bb, insn, &live);
++	}
++    }
++  CLEAR_REG_SET (&live);
++}
++
+ /* Gcc puts the pool in the wrong place for ARM, since we can only
+    load addresses a limited distance around the pc.  We do some
+    special munging to move the constant pool values to the correct
+@@ -12157,6 +12209,9 @@
+   HOST_WIDE_INT address = 0;
+   Mfix * fix;
+ 
++  if (TARGET_THUMB2)
++    thumb2_reorg ();
++  
+   minipool_fix_head = minipool_fix_tail = NULL;
+ 
+   /* The first insn must always be a note, or the code below won't
+Index: gcc-4_5-branch/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.h	2012-03-06 12:11:33.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm.h	2012-03-06 12:14:01.032439183 -0800
+@@ -1133,7 +1133,11 @@
+ }
+ 
+ /* Use different register alloc ordering for Thumb.  */
+-#define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
++
++/* Tell IRA to use the order we define rather than messing it up with its
++   own cost calculations.  */
++#define HONOR_REG_ALLOC_ORDER
+ 
+ /* Interrupt functions can only use registers that have already been
+    saved by the prologue, even if they would normally be
+Index: gcc-4_5-branch/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.md	2012-03-06 12:11:35.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm.md	2012-03-06 12:14:01.036439231 -0800
+@@ -4074,7 +4074,7 @@
+ 
+ (define_split
+   [(set (match_operand:SI 0 "register_operand" "")
+-	(zero_extend:SI (match_operand:HI 1 "register_operand" "l,m")))]
++	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
+   "!TARGET_THUMB2 && !arm_arch6"
+   [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
+    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
+Index: gcc-4_5-branch/gcc/config/arm/thumb2.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/thumb2.md	2012-03-06 12:11:35.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/thumb2.md	2012-03-06 12:14:01.036439231 -0800
+@@ -1046,29 +1046,6 @@
+   }"
+ )
+ 
+-;; Peepholes and insns for 16-bit flag clobbering instructions.
+-;; The conditional forms of these instructions do not clobber CC.
+-;; However by the time peepholes are run it is probably too late to do
+-;; anything useful with this information.
+-(define_peephole2
+-  [(set (match_operand:SI          0 "low_register_operand" "")
+-        (match_operator:SI 3 "thumb_16bit_operator"
+-	 [(match_operand:SI 1  "low_register_operand" "")
+-	  (match_operand:SI 2 "low_register_operand" "")]))]
+-  "TARGET_THUMB2
+-   && (rtx_equal_p(operands[0], operands[1])
+-       || GET_CODE(operands[3]) == PLUS
+-       || GET_CODE(operands[3]) == MINUS)
+-   && peep2_regno_dead_p(0, CC_REGNUM)"
+-  [(parallel
+-    [(set (match_dup 0)
+-	  (match_op_dup 3
+-	   [(match_dup 1)
+-	    (match_dup 2)]))
+-     (clobber (reg:CC CC_REGNUM))])]
+-  ""
+-)
+-
+ (define_insn "*thumb2_alusi3_short"
+   [(set (match_operand:SI          0 "s_register_operand" "=l")
+         (match_operator:SI 3 "thumb_16bit_operator"
+Index: gcc-4_5-branch/gcc/config/avr/avr.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/avr/avr.h	2012-03-06 11:53:21.000000000 -0800
++++ gcc-4_5-branch/gcc/config/avr/avr.h	2012-03-06 12:14:01.036439231 -0800
+@@ -232,7 +232,7 @@
+     32,33,34,35					\
+     }
+ 
+-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
+ 
+ 
+ #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+Index: gcc-4_5-branch/gcc/config/i386/i386.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/i386/i386.h	2012-03-06 11:53:19.000000000 -0800
++++ gcc-4_5-branch/gcc/config/i386/i386.h	2012-03-06 12:14:01.036439231 -0800
+@@ -955,7 +955,7 @@
+    registers listed in CALL_USED_REGISTERS, keeping the others
+    available for storage of persistent values.
+ 
+-   The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
++   The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
+    so this is just empty initializer for array.  */
+ 
+ #define REG_ALLOC_ORDER 					\
+@@ -964,11 +964,11 @@
+    33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,  \
+    48, 49, 50, 51, 52 }
+ 
+-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
++/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
+    to be rearranged based on a particular function.  When using sse math,
+    we want to allocate SSE before x87 registers and vice versa.  */
+ 
+-#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
+ 
+ 
+ #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
+Index: gcc-4_5-branch/gcc/config/mips/mips.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/mips/mips.h	2012-03-06 11:53:28.000000000 -0800
++++ gcc-4_5-branch/gcc/config/mips/mips.h	2012-03-06 12:14:01.040439261 -0800
+@@ -2059,12 +2059,12 @@
+   182,183,184,185,186,187						\
+ }
+ 
+-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
++/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
+    to be rearranged based on a particular function.  On the mips16, we
+    want to allocate $24 (T_REG) before other registers for
+    instructions for which it is possible.  */
+ 
+-#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
+ 
+ /* True if VALUE is an unsigned 6-bit number.  */
+ 
+Index: gcc-4_5-branch/gcc/config/picochip/picochip.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/picochip/picochip.h	2012-03-06 11:53:26.000000000 -0800
++++ gcc-4_5-branch/gcc/config/picochip/picochip.h	2012-03-06 12:14:01.040439261 -0800
+@@ -261,7 +261,7 @@
+ /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
+    It would be desirable to change it for leaf functions so we can put
+    r12 at the end of this list.*/
+-#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc ()
+ 
+ /* How Values Fit in Registers  */
+ 
+Index: gcc-4_5-branch/gcc/config/sparc/predicates.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/sparc/predicates.md	2012-03-06 11:53:17.000000000 -0800
++++ gcc-4_5-branch/gcc/config/sparc/predicates.md	2012-03-06 12:14:01.040439261 -0800
+@@ -1,5 +1,5 @@
+ ;; Predicate definitions for SPARC.
+-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
++;; Copyright (C) 2005, 2007, 2008, 2010 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+@@ -473,9 +473,3 @@
+ ;; and (xor ... (not ...)) to (not (xor ...)).  */
+ (define_predicate "cc_arith_not_operator"
+   (match_code "and,ior"))
+-
+-;; Return true if OP is memory operand with just [%reg] addressing mode.
+-(define_predicate "memory_reg_operand"
+-  (and (match_code "mem")
+-       (and (match_operand 0 "memory_operand")
+-	    (match_test "REG_P (XEXP (op, 0))"))))
+Index: gcc-4_5-branch/gcc/config/sparc/sparc.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/sparc/sparc.h	2012-03-06 11:53:17.000000000 -0800
++++ gcc-4_5-branch/gcc/config/sparc/sparc.h	2012-03-06 12:14:01.040439261 -0800
+@@ -1188,7 +1188,7 @@
+   96, 97, 98, 99,			/* %fcc0-3 */	\
+   100, 0, 14, 30, 31, 101}		/* %icc, %g0, %o6, %i6, %i7, %sfp */
+ 
+-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
+ 
+ extern char sparc_leaf_regs[];
+ #define LEAF_REGISTERS sparc_leaf_regs
+Index: gcc-4_5-branch/gcc/config/sparc/sync.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/sparc/sync.md	2012-03-06 11:53:17.000000000 -0800
++++ gcc-4_5-branch/gcc/config/sparc/sync.md	2012-03-06 12:14:01.040439261 -0800
+@@ -1,5 +1,5 @@
+ ;; GCC machine description for SPARC synchronization instructions.
+-;; Copyright (C) 2005, 2007, 2009
++;; Copyright (C) 2005, 2007, 2009, 2010
+ ;; Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+@@ -62,7 +62,7 @@
+ 
+ (define_expand "sync_compare_and_swap<mode>"
+   [(parallel
+-     [(set (match_operand:I48MODE 0 "register_operand" "=r")
++     [(set (match_operand:I48MODE 0 "register_operand" "")
+ 	   (match_operand:I48MODE 1 "memory_operand" ""))
+       (set (match_dup 1)
+ 	   (unspec_volatile:I48MODE
+@@ -71,7 +71,7 @@
+ 	     UNSPECV_CAS))])]
+   "TARGET_V9"
+ {
+-  if (! REG_P (XEXP (operands[1], 0)))
++  if (!REG_P (XEXP (operands[1], 0)))
+     {
+       rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
+       operands[1] = replace_equiv_address (operands[1], addr);
+@@ -81,20 +81,20 @@
+ 
+ (define_insn "*sync_compare_and_swap<mode>"
+   [(set (match_operand:I48MODE 0 "register_operand" "=r")
+-	(match_operand:I48MODE 1 "memory_reg_operand" "+m"))
+-   (set (match_dup 1)
++	(mem:I48MODE (match_operand 1 "register_operand" "r")))
++   (set (mem:I48MODE (match_dup 1))
+ 	(unspec_volatile:I48MODE
+ 	  [(match_operand:I48MODE 2 "register_operand" "r")
+ 	   (match_operand:I48MODE 3 "register_operand" "0")]
+ 	  UNSPECV_CAS))]
+   "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
+-  "cas<modesuffix>\t%1, %2, %0"
++  "cas<modesuffix>\t[%1], %2, %0"
+   [(set_attr "type" "multi")])
+ 
+ (define_insn "*sync_compare_and_swapdi_v8plus"
+   [(set (match_operand:DI 0 "register_operand" "=h")
+-	(match_operand:DI 1 "memory_reg_operand" "+m"))
+-   (set (match_dup 1)
++	(mem:DI (match_operand 1 "register_operand" "r")))
++   (set (mem:DI (match_dup 1))
+ 	(unspec_volatile:DI
+ 	  [(match_operand:DI 2 "register_operand" "h")
+ 	   (match_operand:DI 3 "register_operand" "0")]
+@@ -109,7 +109,7 @@
+     output_asm_insn ("srl\t%L2, 0, %L2", operands);
+   output_asm_insn ("sllx\t%H2, 32, %H3", operands);
+   output_asm_insn ("or\t%L2, %H3, %H3", operands);
+-  output_asm_insn ("casx\t%1, %H3, %L3", operands);
++  output_asm_insn ("casx\t[%1], %H3, %L3", operands);
+   return "srlx\t%L3, 32, %H3";
+ }
+   [(set_attr "type" "multi")
+Index: gcc-4_5-branch/gcc/config/xtensa/xtensa.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/xtensa/xtensa.h	2012-03-06 11:53:21.000000000 -0800
++++ gcc-4_5-branch/gcc/config/xtensa/xtensa.h	2012-03-06 12:14:01.040439261 -0800
+@@ -286,7 +286,7 @@
+    incoming argument in a2 is live throughout the function and
+    local-alloc decides to use a2, then the incoming argument must
+    either be spilled or copied to another register.  To get around
+-   this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
++   this, we define ADJUST_REG_ALLOC_ORDER to redefine
+    reg_alloc_order for leaf functions such that lowest numbered
+    registers are used first with the exception that the incoming
+    argument registers are not used until after other register choices
+@@ -300,7 +300,7 @@
+   35, \
+ }
+ 
+-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
+ 
+ /* For Xtensa, the only point of this is to prevent GCC from otherwise
+    giving preference to call-used registers.  To minimize window
+Index: gcc-4_5-branch/gcc/doc/tm.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/tm.texi	2012-03-06 12:11:33.000000000 -0800
++++ gcc-4_5-branch/gcc/doc/tm.texi	2012-03-06 12:14:01.044439265 -0800
+@@ -2093,7 +2093,7 @@
+ the highest numbered allocable register first.
+ @end defmac
+ 
+-@defmac ORDER_REGS_FOR_LOCAL_ALLOC
++@defmac ADJUST_REG_ALLOC_ORDER
+ A C statement (sans semicolon) to choose the order in which to allocate
+ hard registers for pseudo-registers local to a basic block.
+ 
+@@ -2107,6 +2107,15 @@
+ On most machines, it is not necessary to define this macro.
+ @end defmac
+ 
++@defmac HONOR_REG_ALLOC_ORDER
++Normally, IRA tries to estimate the costs for saving a register in the
++prologue and restoring it in the epilogue.  This discourages it from
++using call-saved registers.  If a machine wants to ensure that IRA
++allocates registers in the order given by REG_ALLOC_ORDER even if some
++call-saved registers appear earlier than call-used ones, this macro
++should be defined.
++@end defmac
++
+ @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno})
+ In some case register allocation order is not enough for the
+ Integrated Register Allocator (@acronym{IRA}) to generate a good code.
+Index: gcc-4_5-branch/gcc/expmed.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expmed.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/expmed.c	2012-03-06 12:14:01.044439265 -0800
+@@ -3255,6 +3255,55 @@
+   gcc_assert (op0);
+   return op0;
+ }
++
++/* Perform a widening multiplication and return an rtx for the result.
++   MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
++   TARGET is a suggestion for where to store the result (an rtx).
++   THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
++   or smul_widen_optab.
++
++   We check specially for a constant integer as OP1, comparing the
++   cost of a widening multiply against the cost of a sequence of shifts
++   and adds.  */
++
++rtx
++expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
++		      int unsignedp, optab this_optab)
++{
++  bool speed = optimize_insn_for_speed_p ();
++
++  if (CONST_INT_P (op1)
++      && (INTVAL (op1) >= 0
++	  || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT))
++    {
++      HOST_WIDE_INT coeff = INTVAL (op1);
++      int max_cost;
++      enum mult_variant variant;
++      struct algorithm algorithm;
++
++      /* Special case powers of two.  */
++      if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
++	{
++	  op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
++	  return expand_shift (LSHIFT_EXPR, mode, op0,
++			       build_int_cst (NULL_TREE, floor_log2 (coeff)),
++			       target, unsignedp);
++	}
++
++      /* Exclude cost of op0 from max_cost to match the cost
++	 calculation of the synth_mult.  */
++      max_cost = mul_widen_cost[speed][mode];
++      if (choose_mult_variant (mode, coeff, &algorithm, &variant,
++			       max_cost))
++	{
++	  op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
++	  return expand_mult_const (mode, op0, coeff, target,
++				    &algorithm, variant);
++	}
++    }
++  return expand_binop (mode, this_optab, op0, op1, target,
++		       unsignedp, OPTAB_LIB_WIDEN);
++}
+ 
+ /* Return the smallest n such that 2**n >= X.  */
+ 
+Index: gcc-4_5-branch/gcc/expr.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expr.c	2012-03-06 12:11:34.000000000 -0800
++++ gcc-4_5-branch/gcc/expr.c	2012-03-06 12:46:21.548533151 -0800
+@@ -7345,7 +7345,6 @@
+   optab this_optab;
+   rtx subtarget, original_target;
+   int ignore;
+-  tree subexp0, subexp1;
+   bool reduce_bit_field;
+   gimple subexp0_def, subexp1_def;
+   tree top0, top1;
+@@ -7800,13 +7799,7 @@
+ 
+       goto binop2;
+ 
+-    case MULT_EXPR:
+-      /* If this is a fixed-point operation, then we cannot use the code
+-	 below because "expand_mult" doesn't support sat/no-sat fixed-point
+-         multiplications.   */
+-      if (ALL_FIXED_POINT_MODE_P (mode))
+-	goto binop;
+-
++    case WIDEN_MULT_EXPR:
+       /* If first operand is constant, swap them.
+ 	 Thus the following special case checks need only
+ 	 check the second operand.  */
+@@ -7817,96 +7810,35 @@
+ 	  treeop1 = t1;
+ 	}
+ 
+-      /* Attempt to return something suitable for generating an
+-	 indexed address, for machines that support that.  */
+-
+-      if (modifier == EXPAND_SUM && mode == ptr_mode
+-	  && host_integerp (treeop1, 0))
+-	{
+-	  tree exp1 = treeop1;
+-
+-	  op0 = expand_expr (treeop0, subtarget, VOIDmode,
+-			     EXPAND_SUM);
+-
+-	  if (!REG_P (op0))
+-	    op0 = force_operand (op0, NULL_RTX);
+-	  if (!REG_P (op0))
+-	    op0 = copy_to_mode_reg (mode, op0);
+-
+-	  return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0,
+-			       gen_int_mode (tree_low_cst (exp1, 0),
+-					     TYPE_MODE (TREE_TYPE (exp1)))));
+-	}
+-
+-      if (modifier == EXPAND_STACK_PARM)
+-	target = 0;
+-
+-      /* Check for multiplying things that have been extended
+-	 from a narrower type.  If this machine supports multiplying
+-	 in that narrower type with a result in the desired type,
+-	 do it that way, and avoid the explicit type-conversion.  */
+-
+-      subexp0 = treeop0;
+-      subexp1 = treeop1;
+-      subexp0_def = get_def_for_expr (subexp0, NOP_EXPR);
+-      subexp1_def = get_def_for_expr (subexp1, NOP_EXPR);
+-      top0 = top1 = NULL_TREE;
+-
+       /* First, check if we have a multiplication of one signed and one
+ 	 unsigned operand.  */
+-      if (subexp0_def
+-	  && (top0 = gimple_assign_rhs1 (subexp0_def))
+-	  && subexp1_def
+-	  && (top1 = gimple_assign_rhs1 (subexp1_def))
+-	  && TREE_CODE (type) == INTEGER_TYPE
+-	  && (TYPE_PRECISION (TREE_TYPE (top0))
+-	      < TYPE_PRECISION (TREE_TYPE (subexp0)))
+-	  && (TYPE_PRECISION (TREE_TYPE (top0))
+-	      == TYPE_PRECISION (TREE_TYPE (top1)))
+-	  && (TYPE_UNSIGNED (TREE_TYPE (top0))
+-	      != TYPE_UNSIGNED (TREE_TYPE (top1))))
++      if (TREE_CODE (treeop1) != INTEGER_CST
++	  && (TYPE_UNSIGNED (TREE_TYPE (treeop0))
++	      != TYPE_UNSIGNED (TREE_TYPE (treeop1))))
+ 	{
+-	  enum machine_mode innermode
+-	    = TYPE_MODE (TREE_TYPE (top0));
++	  enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0));
+ 	  this_optab = usmul_widen_optab;
+-	  if (mode == GET_MODE_WIDER_MODE (innermode))
++	  if (mode == GET_MODE_2XWIDER_MODE (innermode))
+ 	    {
+ 	      if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
+ 		{
+-		  if (TYPE_UNSIGNED (TREE_TYPE (top0)))
+-		    expand_operands (top0, top1, NULL_RTX, &op0, &op1,
++		  if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
++		    expand_operands (treeop0, treeop1, subtarget, &op0, &op1,
+ 				     EXPAND_NORMAL);
+ 		  else
+-		    expand_operands (top0, top1, NULL_RTX, &op1, &op0,
++		    expand_operands (treeop0, treeop1, subtarget, &op1, &op0,
+ 				     EXPAND_NORMAL);
+-
+ 		  goto binop3;
+ 		}
+ 	    }
+ 	}
+-      /* Check for a multiplication with matching signedness.  If
+-	 valid, TOP0 and TOP1 were set in the previous if
+-	 condition.  */
+-      else if (top0
+-	  && TREE_CODE (type) == INTEGER_TYPE
+-	  && (TYPE_PRECISION (TREE_TYPE (top0))
+-	      < TYPE_PRECISION (TREE_TYPE (subexp0)))
+-	  && ((TREE_CODE (subexp1) == INTEGER_CST
+-	       && int_fits_type_p (subexp1, TREE_TYPE (top0))
+-	       /* Don't use a widening multiply if a shift will do.  */
+-	       && ((GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (subexp1)))
+-		    > HOST_BITS_PER_WIDE_INT)
+-		   || exact_log2 (TREE_INT_CST_LOW (subexp1)) < 0))
+-	      ||
+-	      (top1
+-	       && (TYPE_PRECISION (TREE_TYPE (top1))
+-		   == TYPE_PRECISION (TREE_TYPE (top0))
+-	       /* If both operands are extended, they must either both
+-		  be zero-extended or both be sign-extended.  */
+-	       && (TYPE_UNSIGNED (TREE_TYPE (top1))
+-		   == TYPE_UNSIGNED (TREE_TYPE (top0)))))))
++      /* Check for a multiplication with matching signedness.  */
++      else if ((TREE_CODE (treeop1) == INTEGER_CST
++		&& int_fits_type_p (treeop1, TREE_TYPE (treeop0)))
++	       || (TYPE_UNSIGNED (TREE_TYPE (treeop1))
++		   == TYPE_UNSIGNED (TREE_TYPE (treeop0))))
+ 	{
+-	  tree op0type = TREE_TYPE (top0);
++	  tree op0type = TREE_TYPE (treeop0);
+ 	  enum machine_mode innermode = TYPE_MODE (op0type);
+ 	  bool zextend_p = TYPE_UNSIGNED (op0type);
+ 	  optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
+@@ -7916,24 +7848,22 @@
+ 	    {
+ 	      if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
+ 		{
+-		  if (TREE_CODE (subexp1) == INTEGER_CST)
+-		    expand_operands (top0, subexp1, NULL_RTX, &op0, &op1,
+-				     EXPAND_NORMAL);
+-		  else
+-		    expand_operands (top0, top1, NULL_RTX, &op0, &op1,
+-				     EXPAND_NORMAL);
+-		  goto binop3;
++		  expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
++				   EXPAND_NORMAL);
++		  temp = expand_widening_mult (mode, op0, op1, target,
++					       unsignedp, this_optab);
++		  return REDUCE_BIT_FIELD (temp);
+ 		}
+-	      else if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing
+-		       && innermode == word_mode)
++	      if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing
++		  && innermode == word_mode)
+ 		{
+ 		  rtx htem, hipart;
+-		  op0 = expand_normal (top0);
+-		  if (TREE_CODE (subexp1) == INTEGER_CST)
++		  op0 = expand_normal (treeop0);
++		  if (TREE_CODE (treeop1) == INTEGER_CST)
+ 		    op1 = convert_modes (innermode, mode,
+-					 expand_normal (subexp1), unsignedp);
++					 expand_normal (treeop1), unsignedp);
+ 		  else
+-		    op1 = expand_normal (top1);
++		    op1 = expand_normal (treeop1);
+ 		  temp = expand_binop (mode, other_optab, op0, op1, target,
+ 				       unsignedp, OPTAB_LIB_WIDEN);
+ 		  hipart = gen_highpart (innermode, temp);
+@@ -7946,7 +7876,53 @@
+ 		}
+ 	    }
+ 	}
+-      expand_operands (subexp0, subexp1, subtarget, &op0, &op1, EXPAND_NORMAL);
++      treeop0 = fold_build1 (CONVERT_EXPR, type, treeop0);
++      treeop1 = fold_build1 (CONVERT_EXPR, type, treeop1);
++      expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL);
++      return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp));
++
++    case MULT_EXPR:
++      /* If this is a fixed-point operation, then we cannot use the code
++	 below because "expand_mult" doesn't support sat/no-sat fixed-point
++         multiplications.   */
++      if (ALL_FIXED_POINT_MODE_P (mode))
++	goto binop;
++
++      /* If first operand is constant, swap them.
++	 Thus the following special case checks need only
++	 check the second operand.  */
++      if (TREE_CODE (treeop0) == INTEGER_CST)
++	{
++	  tree t1 = treeop0;
++	  treeop0 = treeop1;
++	  treeop1 = t1;
++	}
++
++      /* Attempt to return something suitable for generating an
++	 indexed address, for machines that support that.  */
++
++      if (modifier == EXPAND_SUM && mode == ptr_mode
++	  && host_integerp (treeop1, 0))
++	{
++	  tree exp1 = treeop1;
++
++	  op0 = expand_expr (treeop0, subtarget, VOIDmode,
++			     EXPAND_SUM);
++
++	  if (!REG_P (op0))
++	    op0 = force_operand (op0, NULL_RTX);
++	  if (!REG_P (op0))
++	    op0 = copy_to_mode_reg (mode, op0);
++
++	  return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0,
++			       gen_int_mode (tree_low_cst (exp1, 0),
++					     TYPE_MODE (TREE_TYPE (exp1)))));
++	}
++
++      if (modifier == EXPAND_STACK_PARM)
++	target = 0;
++
++      expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL);
+       return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp));
+ 
+     case TRUNC_DIV_EXPR:
+@@ -8435,6 +8411,8 @@
+   location_t loc = EXPR_LOCATION (exp);
+   struct separate_ops ops;
+   tree treeop0, treeop1, treeop2;
++  tree ssa_name = NULL_TREE;
++  gimple g;
+ 
+   type = TREE_TYPE (exp);
+   mode = TYPE_MODE (type);
+@@ -8547,15 +8525,17 @@
+ 	 base variable.  This unnecessarily allocates a pseudo, see how we can
+ 	 reuse it, if partition base vars have it set already.  */
+       if (!currently_expanding_to_rtl)
+-	return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, NULL);
+-      {
+-	gimple g = get_gimple_for_ssa_name (exp);
+-	if (g)
+-	  return expand_expr_real (gimple_assign_rhs_to_tree (g), target,
+-				   tmode, modifier, NULL);
+-      }
+-      decl_rtl = get_rtx_for_ssa_name (exp);
+-      exp = SSA_NAME_VAR (exp);
++	return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier,
++				   NULL);
++
++      g = get_gimple_for_ssa_name (exp);
++      if (g)
++	return expand_expr_real (gimple_assign_rhs_to_tree (g), target, tmode,
++				 modifier, NULL);
++
++      ssa_name = exp;
++      decl_rtl = get_rtx_for_ssa_name (ssa_name);
++      exp = SSA_NAME_VAR (ssa_name);
+       goto expand_decl_rtl;
+ 
+     case PARM_DECL:
+@@ -8669,7 +8649,15 @@
+ 
+ 	  /* Get the signedness used for this variable.  Ensure we get the
+ 	     same mode we got when the variable was declared.  */
+-	  pmode = promote_decl_mode (exp, &unsignedp);
++	  if (code == SSA_NAME
++	      && (g = SSA_NAME_DEF_STMT (ssa_name))
++	      && gimple_code (g) == GIMPLE_CALL)
++	    pmode = promote_function_mode (type, mode, &unsignedp,
++					   TREE_TYPE
++					   (TREE_TYPE (gimple_call_fn (g))),
++					   2);
++	  else
++	    pmode = promote_decl_mode (exp, &unsignedp);
+ 	  gcc_assert (GET_MODE (decl_rtl) == pmode);
+ 
+ 	  temp = gen_lowpart_SUBREG (mode, decl_rtl);
+Index: gcc-4_5-branch/gcc/fold-const.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/fold-const.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/fold-const.c	2012-03-06 12:14:01.052439240 -0800
+@@ -5749,6 +5749,76 @@
+ 		       const_binop (BIT_XOR_EXPR, c, temp, 0));
+ }
+ 
++/* For an expression that has the form
++     (A && B) || ~B
++   or
++     (A || B) && ~B,
++   we can drop one of the inner expressions and simplify to
++     A || ~B
++   or
++     A && ~B
++   LOC is the location of the resulting expression.  OP is the inner 
++   logical operation; the left-hand side in the examples above, while CMPOP
++   is the right-hand side.  RHS_ONLY is used to prevent us from accidentally
++   removing a condition that guards another, as in
++     (A != NULL && A->...) || A == NULL
++   which we must not transform.  If RHS_ONLY is true, only eliminate the
++   right-most operand of the inner logical operation.  */
++
++static tree
++merge_truthop_with_opposite_arm (location_t loc, tree op, tree cmpop,
++				 bool rhs_only)
++{
++  tree type = TREE_TYPE (cmpop);
++  enum tree_code code = TREE_CODE (cmpop);
++  enum tree_code truthop_code = TREE_CODE (op);
++  tree lhs = TREE_OPERAND (op, 0);
++  tree rhs = TREE_OPERAND (op, 1);
++  tree orig_lhs = lhs, orig_rhs = rhs;
++  enum tree_code rhs_code = TREE_CODE (rhs);
++  enum tree_code lhs_code = TREE_CODE (lhs);
++  enum tree_code inv_code;
++
++  if (TREE_SIDE_EFFECTS (op) || TREE_SIDE_EFFECTS (cmpop))
++    return NULL_TREE;
++
++  if (TREE_CODE_CLASS (code) != tcc_comparison)
++    return NULL_TREE;
++
++  if (rhs_code == truthop_code)
++    {
++      tree newrhs = merge_truthop_with_opposite_arm (loc, rhs, cmpop, rhs_only);
++      if (newrhs != NULL_TREE)
++	{
++	  rhs = newrhs;
++	  rhs_code = TREE_CODE (rhs);
++	}
++    }
++  if (lhs_code == truthop_code && !rhs_only)
++    {
++      tree newlhs = merge_truthop_with_opposite_arm (loc, lhs, cmpop, false);
++      if (newlhs != NULL_TREE)
++	{
++	  lhs = newlhs;
++	  lhs_code = TREE_CODE (lhs);
++	}
++    }
++
++  inv_code = invert_tree_comparison (code, HONOR_NANS (TYPE_MODE (type)));
++  if (inv_code == rhs_code
++      && operand_equal_p (TREE_OPERAND (rhs, 0), TREE_OPERAND (cmpop, 0), 0)
++      && operand_equal_p (TREE_OPERAND (rhs, 1), TREE_OPERAND (cmpop, 1), 0))
++    return lhs;
++  if (!rhs_only && inv_code == lhs_code
++      && operand_equal_p (TREE_OPERAND (lhs, 0), TREE_OPERAND (cmpop, 0), 0)
++      && operand_equal_p (TREE_OPERAND (lhs, 1), TREE_OPERAND (cmpop, 1), 0))
++    return rhs;
++  if (rhs != orig_rhs || lhs != orig_lhs)
++    return fold_build2_loc (loc, truthop_code, TREE_TYPE (cmpop),
++			    lhs, rhs);
++  return NULL_TREE;
++}
++
+ /* Find ways of folding logical expressions of LHS and RHS:
+    Try to merge two comparisons to the same innermost item.
+    Look for range tests like "ch >= '0' && ch <= '9'".
+@@ -12553,6 +12623,22 @@
+       if (0 != (tem = fold_range_test (loc, code, type, op0, op1)))
+ 	return tem;
+ 
++      if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg0) == TRUTH_ORIF_EXPR)
++	  || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg0) == TRUTH_ANDIF_EXPR))
++	{
++	  tem = merge_truthop_with_opposite_arm (loc, arg0, arg1, true);
++	  if (tem)
++	    return fold_build2_loc (loc, code, type, tem, arg1);
++	}
++
++      if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg1) == TRUTH_ORIF_EXPR)
++	  || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg1) == TRUTH_ANDIF_EXPR))
++	{
++	  tem = merge_truthop_with_opposite_arm (loc, arg1, arg0, false);
++	  if (tem)
++	    return fold_build2_loc (loc, code, type, arg0, tem);
++	}
++
+       /* Check for the possibility of merging component references.  If our
+ 	 lhs is another similar operation, try to merge its rhs with our
+ 	 rhs.  Then try to merge our lhs and rhs.  */
+Index: gcc-4_5-branch/gcc/ifcvt.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/ifcvt.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/ifcvt.c	2012-03-06 12:14:01.052439240 -0800
+@@ -385,7 +385,11 @@
+   rtx false_expr;		/* test for then block insns */
+   rtx true_prob_val;		/* probability of else block */
+   rtx false_prob_val;		/* probability of then block */
+-  int n_insns;
++  rtx then_last_head = NULL_RTX;	/* Last match at the head of THEN */
++  rtx else_last_head = NULL_RTX;	/* Last match at the head of ELSE */
++  rtx then_first_tail = NULL_RTX;	/* First match at the tail of THEN */
++  rtx else_first_tail = NULL_RTX;	/* First match at the tail of ELSE */
++  int then_n_insns, else_n_insns, n_insns;
+   enum rtx_code false_code;
+ 
+   /* If test is comprised of && or || elements, and we've failed at handling
+@@ -418,15 +422,78 @@
+      number of insns and see if it is small enough to convert.  */
+   then_start = first_active_insn (then_bb);
+   then_end = last_active_insn (then_bb, TRUE);
+-  n_insns = ce_info->num_then_insns = count_bb_insns (then_bb);
++  then_n_insns = ce_info->num_then_insns = count_bb_insns (then_bb);
++  n_insns = then_n_insns;
+   max = MAX_CONDITIONAL_EXECUTE;
+ 
+   if (else_bb)
+     {
++      int n_matching;
++
+       max *= 2;
+       else_start = first_active_insn (else_bb);
+       else_end = last_active_insn (else_bb, TRUE);
+-      n_insns += ce_info->num_else_insns = count_bb_insns (else_bb);
++      else_n_insns = ce_info->num_else_insns = count_bb_insns (else_bb);
++      n_insns += else_n_insns;
++
++      /* Look for matching sequences at the head and tail of the two blocks,
++	 and limit the range of insns to be converted if possible.  */
++      n_matching = flow_find_cross_jump (then_bb, else_bb,
++					 &then_first_tail, &else_first_tail);
++      if (then_first_tail == BB_HEAD (then_bb))
++	then_start = then_end = NULL_RTX;
++      if (else_first_tail == BB_HEAD (else_bb))
++	else_start = else_end = NULL_RTX;
++
++      if (n_matching > 0)
++	{
++	  if (then_end)
++	    then_end = prev_active_insn (then_first_tail);
++	  if (else_end)
++	    else_end = prev_active_insn (else_first_tail);
++	  n_insns -= 2 * n_matching;
++	}
++
++      if (then_start && else_start)
++	{
++	  int longest_match = MIN (then_n_insns - n_matching,
++				   else_n_insns - n_matching);
++	  n_matching
++	    = flow_find_head_matching_sequence (then_bb, else_bb,
++						&then_last_head,
++						&else_last_head,
++						longest_match);
++
++	  if (n_matching > 0)
++	    {
++	      rtx insn;
++
++	      /* We won't pass the insns in the head sequence to
++		 cond_exec_process_insns, so we need to test them here
++		 to make sure that they don't clobber the condition.  */
++	      for (insn = BB_HEAD (then_bb);
++		   insn != NEXT_INSN (then_last_head);
++		   insn = NEXT_INSN (insn))
++		if (!LABEL_P (insn) && !NOTE_P (insn)
++		    && !DEBUG_INSN_P (insn)
++		    && modified_in_p (test_expr, insn))
++		  return FALSE;
++	    }
++
++	  if (then_last_head == then_end)
++	    then_start = then_end = NULL_RTX;
++	  if (else_last_head == else_end)
++	    else_start = else_end = NULL_RTX;
++
++	  if (n_matching > 0)
++	    {
++	      if (then_start)
++		then_start = next_active_insn (then_last_head);
++	      if (else_start)
++		else_start = next_active_insn (else_last_head);
++	      n_insns -= 2 * n_matching;
++	    }
++	}
+     }
+ 
+   if (n_insns > max)
+@@ -570,7 +637,21 @@
+     fprintf (dump_file, "%d insn%s converted to conditional execution.\n",
+ 	     n_insns, (n_insns == 1) ? " was" : "s were");
+ 
+-  /* Merge the blocks!  */
++  /* Merge the blocks!  If we had matching sequences, make sure to delete one
++     copy at the appropriate location first: delete the copy in the THEN branch
++     for a tail sequence so that the remaining one is executed last for both
++     branches, and delete the copy in the ELSE branch for a head sequence so
++     that the remaining one is executed first for both branches.  */
++  if (then_first_tail)
++    {
++      rtx from = then_first_tail;
++      if (!INSN_P (from))
++	from = next_active_insn (from);
++      delete_insn_chain (from, BB_END (then_bb), false);
++    }
++  if (else_last_head)
++    delete_insn_chain (first_active_insn (else_bb), else_last_head, false);
++
+   merge_if_block (ce_info);
+   cond_exec_changed_p = TRUE;
+   return TRUE;
+Index: gcc-4_5-branch/gcc/ira-color.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/ira-color.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/ira-color.c	2012-03-06 12:14:01.056439222 -0800
+@@ -447,14 +447,18 @@
+ {
+   HARD_REG_SET conflicting_regs;
+   int i, j, k, hard_regno, best_hard_regno, class_size;
+-  int cost, mem_cost, min_cost, full_cost, min_full_cost, add_cost;
++  int cost, mem_cost, min_cost, full_cost, min_full_cost;
+   int *a_costs;
+   int *conflict_costs;
+-  enum reg_class cover_class, rclass, conflict_cover_class;
++  enum reg_class cover_class, conflict_cover_class;
+   enum machine_mode mode;
+   ira_allocno_t a, conflict_allocno;
+   ira_allocno_conflict_iterator aci;
+   static int costs[FIRST_PSEUDO_REGISTER], full_costs[FIRST_PSEUDO_REGISTER];
++#ifndef HONOR_REG_ALLOC_ORDER
++  enum reg_class rclass;
++  int add_cost;
++#endif
+ #ifdef STACK_REGS
+   bool no_stack_reg_p;
+ #endif
+@@ -592,6 +596,7 @@
+ 	continue;
+       cost = costs[i];
+       full_cost = full_costs[i];
++#ifndef HONOR_REG_ALLOC_ORDER
+       if (! allocated_hardreg_p[hard_regno]
+ 	  && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set))
+ 	/* We need to save/restore the hard register in
+@@ -604,6 +609,7 @@
+ 	  cost += add_cost;
+ 	  full_cost += add_cost;
+ 	}
++#endif
+       if (min_cost > cost)
+ 	min_cost = cost;
+       if (min_full_cost > full_cost)
+Index: gcc-4_5-branch/gcc/ira-costs.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/ira-costs.c	2012-03-06 12:11:33.000000000 -0800
++++ gcc-4_5-branch/gcc/ira-costs.c	2012-03-06 12:14:01.056439222 -0800
+@@ -33,6 +33,7 @@
+ #include "addresses.h"
+ #include "insn-config.h"
+ #include "recog.h"
++#include "reload.h"
+ #include "toplev.h"
+ #include "target.h"
+ #include "params.h"
+@@ -123,6 +124,10 @@
+ /* Record cover register class of each allocno with the same regno.  */
+ static enum reg_class *regno_cover_class;
+ 
++/* Record cost gains for not allocating a register with an invariant
++   equivalence.  */
++static int *regno_equiv_gains;
++
+ /* Execution frequency of the current insn.  */
+ static int frequency;
+ 
+@@ -1263,6 +1268,7 @@
+ #ifdef FORBIDDEN_INC_DEC_CLASSES
+ 	  int inc_dec_p = false;
+ #endif
++	  int equiv_savings = regno_equiv_gains[i];
+ 
+ 	  if (! allocno_p)
+ 	    {
+@@ -1311,6 +1317,15 @@
+ #endif
+ 		}
+ 	    }
++	  if (equiv_savings < 0)
++	    temp_costs->mem_cost = -equiv_savings;
++	  else if (equiv_savings > 0)
++	    {
++	      temp_costs->mem_cost = 0;
++	      for (k = 0; k < cost_classes_num; k++)
++		temp_costs->cost[k] += equiv_savings;
++	    }
++
+ 	  best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
+ 	  best = ALL_REGS;
+ 	  alt_class = NO_REGS;
+@@ -1680,6 +1695,8 @@
+   regno_cover_class
+     = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
+ 				       * max_reg_num ());
++  regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ());
++  memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ());
+ }
+ 
+ /* Common finalization function for ira_costs and
+@@ -1687,6 +1704,7 @@
+ static void
+ finish_costs (void)
+ {
++  ira_free (regno_equiv_gains);
+   ira_free (regno_cover_class);
+   ira_free (pref_buffer);
+   ira_free (costs);
+@@ -1702,6 +1720,7 @@
+   init_costs ();
+   total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size
+ 						       * ira_allocnos_num);
++  calculate_elim_costs_all_insns ();
+   find_costs_and_classes (ira_dump_file);
+   setup_allocno_cover_class_and_costs ();
+   finish_costs ();
+@@ -1775,3 +1794,16 @@
+ 	ALLOCNO_COVER_CLASS_COST (a) = min_cost;
+     }
+ }
++
++/* Add COST to the estimated gain for eliminating REGNO with its
++   equivalence.  If COST is zero, record that no such elimination is
++   possible.  */
++
++void
++ira_adjust_equiv_reg_cost (unsigned regno, int cost)
++{
++  if (cost == 0)
++    regno_equiv_gains[regno] = 0;
++  else
++    regno_equiv_gains[regno] += cost;
++}
+Index: gcc-4_5-branch/gcc/ira.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/ira.c	2012-03-06 12:11:32.000000000 -0800
++++ gcc-4_5-branch/gcc/ira.c	2012-03-06 12:14:01.056439222 -0800
+@@ -431,9 +431,6 @@
+   HARD_REG_SET processed_hard_reg_set;
+ 
+   ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
+-  /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually
+-     putting hard callee-used hard registers first).  But our
+-     heuristics work better.  */
+   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+     {
+       COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+@@ -490,6 +487,9 @@
+ static void
+ setup_alloc_regs (bool use_hard_frame_p)
+ {
++#ifdef ADJUST_REG_ALLOC_ORDER
++  ADJUST_REG_ALLOC_ORDER;
++#endif
+   COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set);
+   if (! use_hard_frame_p)
+     SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);
+@@ -1533,12 +1533,8 @@
+ 
+ 	  x = XEXP (note, 0);
+ 
+-	  if (! function_invariant_p (x)
+-	      || ! flag_pic
+-	      /* A function invariant is often CONSTANT_P but may
+-		 include a register.  We promise to only pass CONSTANT_P
+-		 objects to LEGITIMATE_PIC_OPERAND_P.  */
+-	      || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x)))
++	  if (! CONSTANT_P (x)
++	      || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
+ 	    {
+ 	      /* It can happen that a REG_EQUIV note contains a MEM
+ 		 that is not a legitimate memory operand.  As later
+@@ -3096,8 +3092,19 @@
+   if (dump_file)
+     print_insn_chains (dump_file);
+ }
+-
+ 
++/* Allocate memory for reg_equiv_memory_loc.  */
++static void
++init_reg_equiv_memory_loc (void)
++{
++  max_regno = max_reg_num ();
++
++  /* And the reg_equiv_memory_loc array.  */
++  VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno);
++  memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0,
++	  sizeof (rtx) * max_regno);
++  reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec);
++}
+ 
+ /* All natural loops.  */
+ struct loops ira_loops;
+@@ -3202,6 +3209,8 @@
+   record_loop_exits ();
+   current_loops = &ira_loops;
+ 
++  init_reg_equiv_memory_loc ();
++
+   if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
+     fprintf (ira_dump_file, "Building IRA IR\n");
+   loops_p = ira_build (optimize
+@@ -3265,13 +3274,8 @@
+ #endif
+ 
+   delete_trivially_dead_insns (get_insns (), max_reg_num ());
+-  max_regno = max_reg_num ();
+ 
+-  /* And the reg_equiv_memory_loc array.  */
+-  VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno);
+-  memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0,
+-	  sizeof (rtx) * max_regno);
+-  reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec);
++  init_reg_equiv_memory_loc ();
+ 
+   if (max_regno != max_regno_before_ira)
+     {
+Index: gcc-4_5-branch/gcc/ira.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/ira.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/ira.h	2012-03-06 12:14:01.056439222 -0800
+@@ -87,3 +87,4 @@
+ extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
+ extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx);
+ 
++extern void ira_adjust_equiv_reg_cost (unsigned, int);
+Index: gcc-4_5-branch/gcc/optabs.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/optabs.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/optabs.h	2012-03-06 12:14:01.056439222 -0800
+@@ -771,6 +771,9 @@
+ /* Generate code for float to integral conversion.  */
+ extern bool expand_sfix_optab (rtx, rtx, convert_optab);
+ 
++/* Generate code for a widening multiply.  */
++extern rtx expand_widening_mult (enum machine_mode, rtx, rtx, rtx, int, optab);
++
+ /* Return tree if target supports vector operations for COND_EXPR.  */
+ bool expand_vec_cond_expr_p (tree, enum machine_mode);
+ 
+Index: gcc-4_5-branch/gcc/passes.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/passes.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/passes.c	2012-03-06 12:14:01.056439222 -0800
+@@ -944,6 +944,7 @@
+       NEXT_PASS (pass_forwprop);
+       NEXT_PASS (pass_phiopt);
+       NEXT_PASS (pass_fold_builtins);
++      NEXT_PASS (pass_optimize_widening_mul);
+       NEXT_PASS (pass_tail_calls);
+       NEXT_PASS (pass_rename_ssa_copies);
+       NEXT_PASS (pass_uncprop);
+Index: gcc-4_5-branch/gcc/reload.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/reload.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/reload.h	2012-03-06 12:14:01.056439222 -0800
+@@ -347,6 +347,10 @@
+ extern rtx eliminate_regs (rtx, enum machine_mode, rtx);
+ extern bool elimination_target_reg_p (rtx);
+ 
++/* Called from the register allocator to estimate costs of eliminating
++   invariant registers.  */
++extern void calculate_elim_costs_all_insns (void);
++
+ /* Deallocate the reload register used by reload number R.  */
+ extern void deallocate_reload_reg (int r);
+ 
+Index: gcc-4_5-branch/gcc/reload1.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/reload1.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/reload1.c	2012-03-06 12:14:01.060439213 -0800
+@@ -413,6 +413,7 @@
+ static void set_label_offsets (rtx, rtx, int);
+ static void check_eliminable_occurrences (rtx);
+ static void elimination_effects (rtx, enum machine_mode);
++static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
+ static int eliminate_regs_in_insn (rtx, int);
+ static void update_eliminable_offsets (void);
+ static void mark_not_eliminable (rtx, const_rtx, void *);
+@@ -420,8 +421,11 @@
+ static bool verify_initial_elim_offsets (void);
+ static void set_initial_label_offsets (void);
+ static void set_offsets_for_label (rtx);
++static void init_eliminable_invariants (rtx, bool);
+ static void init_elim_table (void);
++static void free_reg_equiv (void);
+ static void update_eliminables (HARD_REG_SET *);
++static void elimination_costs_in_insn (rtx);
+ static void spill_hard_reg (unsigned int, int);
+ static int finish_spills (int);
+ static void scan_paradoxical_subregs (rtx);
+@@ -697,6 +701,9 @@
+ 
+ /* Global variables used by reload and its subroutines.  */
+ 
++/* The current basic block while in calculate_elim_costs_all_insns.  */
++static basic_block elim_bb;
++
+ /* Set during calculate_needs if an insn needs register elimination.  */
+ static int something_needs_elimination;
+ /* Set during calculate_needs if an insn needs an operand changed.  */
+@@ -775,22 +782,6 @@
+       if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
+ 	df_set_regs_ever_live (i, true);
+ 
+-  /* Find all the pseudo registers that didn't get hard regs
+-     but do have known equivalent constants or memory slots.
+-     These include parameters (known equivalent to parameter slots)
+-     and cse'd or loop-moved constant memory addresses.
+-
+-     Record constant equivalents in reg_equiv_constant
+-     so they will be substituted by find_reloads.
+-     Record memory equivalents in reg_mem_equiv so they can
+-     be substituted eventually by altering the REG-rtx's.  */
+-
+-  reg_equiv_constant = XCNEWVEC (rtx, max_regno);
+-  reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
+-  reg_equiv_mem = XCNEWVEC (rtx, max_regno);
+-  reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
+-  reg_equiv_address = XCNEWVEC (rtx, max_regno);
+-  reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
+   reg_old_renumber = XCNEWVEC (short, max_regno);
+   memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
+   pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
+@@ -798,115 +789,9 @@
+ 
+   CLEAR_HARD_REG_SET (bad_spill_regs_global);
+ 
+-  /* Look for REG_EQUIV notes; record what each pseudo is equivalent
+-     to.  Also find all paradoxical subregs and find largest such for
+-     each pseudo.  */
+-
+-  num_eliminable_invariants = 0;
+-  for (insn = first; insn; insn = NEXT_INSN (insn))
+-    {
+-      rtx set = single_set (insn);
+-
+-      /* We may introduce USEs that we want to remove at the end, so
+-	 we'll mark them with QImode.  Make sure there are no
+-	 previously-marked insns left by say regmove.  */
+-      if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
+-	  && GET_MODE (insn) != VOIDmode)
+-	PUT_MODE (insn, VOIDmode);
+-
+-      if (NONDEBUG_INSN_P (insn))
+-	scan_paradoxical_subregs (PATTERN (insn));
+-
+-      if (set != 0 && REG_P (SET_DEST (set)))
+-	{
+-	  rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
+-	  rtx x;
+-
+-	  if (! note)
+-	    continue;
+-
+-	  i = REGNO (SET_DEST (set));
+-	  x = XEXP (note, 0);
+-
+-	  if (i <= LAST_VIRTUAL_REGISTER)
+-	    continue;
+-
+-	  if (! function_invariant_p (x)
+-	      || ! flag_pic
+-	      /* A function invariant is often CONSTANT_P but may
+-		 include a register.  We promise to only pass
+-		 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P.  */
+-	      || (CONSTANT_P (x)
+-		  && LEGITIMATE_PIC_OPERAND_P (x)))
+-	    {
+-	      /* It can happen that a REG_EQUIV note contains a MEM
+-		 that is not a legitimate memory operand.  As later
+-		 stages of reload assume that all addresses found
+-		 in the reg_equiv_* arrays were originally legitimate,
+-		 we ignore such REG_EQUIV notes.  */
+-	      if (memory_operand (x, VOIDmode))
+-		{
+-		  /* Always unshare the equivalence, so we can
+-		     substitute into this insn without touching the
+-		       equivalence.  */
+-		  reg_equiv_memory_loc[i] = copy_rtx (x);
+-		}
+-	      else if (function_invariant_p (x))
+-		{
+-		  if (GET_CODE (x) == PLUS)
+-		    {
+-		      /* This is PLUS of frame pointer and a constant,
+-			 and might be shared.  Unshare it.  */
+-		      reg_equiv_invariant[i] = copy_rtx (x);
+-		      num_eliminable_invariants++;
+-		    }
+-		  else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
+-		    {
+-		      reg_equiv_invariant[i] = x;
+-		      num_eliminable_invariants++;
+-		    }
+-		  else if (LEGITIMATE_CONSTANT_P (x))
+-		    reg_equiv_constant[i] = x;
+-		  else
+-		    {
+-		      reg_equiv_memory_loc[i]
+-			= force_const_mem (GET_MODE (SET_DEST (set)), x);
+-		      if (! reg_equiv_memory_loc[i])
+-			reg_equiv_init[i] = NULL_RTX;
+-		    }
+-		}
+-	      else
+-		{
+-		  reg_equiv_init[i] = NULL_RTX;
+-		  continue;
+-		}
+-	    }
+-	  else
+-	    reg_equiv_init[i] = NULL_RTX;
+-	}
+-    }
+-
+-  if (dump_file)
+-    for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
+-      if (reg_equiv_init[i])
+-	{
+-	  fprintf (dump_file, "init_insns for %u: ", i);
+-	  print_inline_rtx (dump_file, reg_equiv_init[i], 20);
+-	  fprintf (dump_file, "\n");
+-	}
+-
++  init_eliminable_invariants (first, true);
+   init_elim_table ();
+ 
+-  first_label_num = get_first_label_num ();
+-  num_labels = max_label_num () - first_label_num;
+-
+-  /* Allocate the tables used to store offset information at labels.  */
+-  /* We used to use alloca here, but the size of what it would try to
+-     allocate would occasionally cause it to exceed the stack limit and
+-     cause a core dump.  */
+-  offsets_known_at = XNEWVEC (char, num_labels);
+-  offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
+-
+   /* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
+      stack slots to the pseudos that lack hard regs or equivalents.
+      Do not touch virtual registers.  */
+@@ -1410,31 +1295,11 @@
+ 	}
+     }
+ 
+-  /* Indicate that we no longer have known memory locations or constants.  */
+-  if (reg_equiv_constant)
+-    free (reg_equiv_constant);
+-  if (reg_equiv_invariant)
+-    free (reg_equiv_invariant);
+-  reg_equiv_constant = 0;
+-  reg_equiv_invariant = 0;
+-  VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
+-  reg_equiv_memory_loc = 0;
+-
+   free (temp_pseudo_reg_arr);
+ 
+-  if (offsets_known_at)
+-    free (offsets_known_at);
+-  if (offsets_at)
+-    free (offsets_at);
+-
+-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+-    if (reg_equiv_alt_mem_list[i])
+-      free_EXPR_LIST_list (&reg_equiv_alt_mem_list[i]);
+-  free (reg_equiv_alt_mem_list);
+-
+-  free (reg_equiv_mem);
++  /* Indicate that we no longer have known memory locations or constants.  */
++  free_reg_equiv ();
+   reg_equiv_init = 0;
+-  free (reg_equiv_address);
+   free (reg_max_ref_width);
+   free (reg_old_renumber);
+   free (pseudo_previous_regs);
+@@ -1727,6 +1592,100 @@
+   *pprev_reload = 0;
+ }
+ 
++/* This function is called from the register allocator to set up estimates
++   for the cost of eliminating pseudos which have REG_EQUIV equivalences to
++   an invariant.  The structure is similar to calculate_needs_all_insns.  */
++
++void
++calculate_elim_costs_all_insns (void)
++{
++  int *reg_equiv_init_cost;
++  basic_block bb;
++  int i;
++
++  reg_equiv_init_cost = XCNEWVEC (int, max_regno);
++  init_elim_table ();
++  init_eliminable_invariants (get_insns (), false);
++
++  set_initial_elim_offsets ();
++  set_initial_label_offsets ();
++
++  FOR_EACH_BB (bb)
++    {
++      rtx insn;
++      elim_bb = bb;
++
++      FOR_BB_INSNS (bb, insn)
++	{
++	  /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
++	     include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
++	     what effects this has on the known offsets at labels.  */
++
++	  if (LABEL_P (insn) || JUMP_P (insn)
++	      || (INSN_P (insn) && REG_NOTES (insn) != 0))
++	    set_label_offsets (insn, insn, 0);
++
++	  if (INSN_P (insn))
++	    {
++	      rtx set = single_set (insn);
++
++	      /* Skip insns that only set an equivalence.  */
++	      if (set && REG_P (SET_DEST (set))
++		  && reg_renumber[REGNO (SET_DEST (set))] < 0
++		  && (reg_equiv_constant[REGNO (SET_DEST (set))]
++		      || (reg_equiv_invariant[REGNO (SET_DEST (set))])))
++		{
++		  unsigned regno = REGNO (SET_DEST (set));
++		  rtx init = reg_equiv_init[regno];
++		  if (init)
++		    {
++		      rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
++						false, true);
++		      int cost = rtx_cost (t, SET,
++					   optimize_bb_for_speed_p (bb));
++		      int freq = REG_FREQ_FROM_BB (bb);
++
++		      reg_equiv_init_cost[regno] = cost * freq;
++		      continue;
++		    }
++		}
++	      /* If needed, eliminate any eliminable registers.  */
++	      if (num_eliminable || num_eliminable_invariants)
++		elimination_costs_in_insn (insn);
++
++	      if (num_eliminable)
++		update_eliminable_offsets ();
++	    }
++	}
++    }
++  for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
++    {
++      if (reg_equiv_invariant[i])
++	{
++	  if (reg_equiv_init[i])
++	    {
++	      int cost = reg_equiv_init_cost[i];
++	      if (dump_file)
++		fprintf (dump_file,
++			 "Reg %d has equivalence, initial gains %d\n", i, cost);
++	      if (cost != 0)
++		ira_adjust_equiv_reg_cost (i, cost);
++	    }
++	  else
++	    {
++	      if (dump_file)
++		fprintf (dump_file,
++			 "Reg %d had equivalence, but can't be eliminated\n",
++			 i);
++	      ira_adjust_equiv_reg_cost (i, 0);
++	    }
++	}
++    }
++
++  free_reg_equiv ();
++  free (reg_equiv_init_cost);
++}
++
+ /* Comparison function for qsort to decide which of two reloads
+    should be handled first.  *P1 and *P2 are the reload numbers.  */
+ 
+@@ -2513,6 +2472,36 @@
+     }
+ }
+ 
++/* Called through for_each_rtx, this function examines every reg that occurs
++   in PX and adjusts the costs for its elimination which are gathered by IRA.
++   DATA is the insn in which PX occurs.  We do not recurse into MEM
++   expressions.  */
++
++static int
++note_reg_elim_costly (rtx *px, void *data)
++{
++  rtx insn = (rtx)data;
++  rtx x = *px;
++
++  if (MEM_P (x))
++    return -1;
++
++  if (REG_P (x)
++      && REGNO (x) >= FIRST_PSEUDO_REGISTER
++      && reg_equiv_init[REGNO (x)]
++      && reg_equiv_invariant[REGNO (x)])
++    {
++      rtx t = reg_equiv_invariant[REGNO (x)];
++      rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
++      int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
++      int freq = REG_FREQ_FROM_BB (elim_bb);
++
++      if (cost != 0)
++	ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
++    }
++  return 0;
++}
++
+ /* Scan X and replace any eliminable registers (such as fp) with a
+    replacement (such as sp), plus an offset.
+ 
+@@ -2532,6 +2521,9 @@
+    This means, do not set ref_outside_mem even if the reference
+    is outside of MEMs.
+ 
++   If FOR_COSTS is true, we are being called before reload in order to
++   estimate the costs of keeping registers with an equivalence unallocated.
++
+    REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
+    replacements done assuming all offsets are at their initial values.  If
+    they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
+@@ -2540,7 +2532,7 @@
+ 
+ static rtx
+ eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
+-		  bool may_use_invariant)
++		  bool may_use_invariant, bool for_costs)
+ {
+   enum rtx_code code = GET_CODE (x);
+   struct elim_table *ep;
+@@ -2588,11 +2580,12 @@
+ 	{
+ 	  if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
+ 	    return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
+-			             mem_mode, insn, true);
++			             mem_mode, insn, true, for_costs);
+ 	  /* There exists at least one use of REGNO that cannot be
+ 	     eliminated.  Prevent the defining insn from being deleted.  */
+ 	  reg_equiv_init[regno] = NULL_RTX;
+-	  alter_reg (regno, -1, true);
++	  if (!for_costs)
++	    alter_reg (regno, -1, true);
+ 	}
+       return x;
+ 
+@@ -2653,8 +2646,10 @@
+ 	 operand of a load-address insn.  */
+ 
+       {
+-	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
+-	rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
++	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
++				     for_costs);
++	rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
++				     for_costs);
+ 
+ 	if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
+ 	  {
+@@ -2728,9 +2723,11 @@
+     case GE:       case GT:       case GEU:    case GTU:
+     case LE:       case LT:       case LEU:    case LTU:
+       {
+-	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
++	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
++				     for_costs);
+ 	rtx new1 = XEXP (x, 1)
+-		   ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
++	  ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
++			      for_costs) : 0;
+ 
+ 	if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
+ 	  return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
+@@ -2741,7 +2738,8 @@
+       /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
+       if (XEXP (x, 0))
+ 	{
+-	  new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
++	  new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
++				      for_costs);
+ 	  if (new_rtx != XEXP (x, 0))
+ 	    {
+ 	      /* If this is a REG_DEAD note, it is not valid anymore.
+@@ -2749,7 +2747,8 @@
+ 		 REG_DEAD note for the stack or frame pointer.  */
+ 	      if (REG_NOTE_KIND (x) == REG_DEAD)
+ 		return (XEXP (x, 1)
+-			? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
++			? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
++					    for_costs)
+ 			: NULL_RTX);
+ 
+ 	      x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
+@@ -2764,7 +2763,8 @@
+ 	 strictly needed, but it simplifies the code.  */
+       if (XEXP (x, 1))
+ 	{
+-	  new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
++	  new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
++				      for_costs);
+ 	  if (new_rtx != XEXP (x, 1))
+ 	    return
+ 	      gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
+@@ -2790,7 +2790,7 @@
+ 	  && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
+ 	{
+ 	  rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
+-				      insn, true);
++					  insn, true, for_costs);
+ 
+ 	  if (new_rtx != XEXP (XEXP (x, 1), 1))
+ 	    return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
+@@ -2813,7 +2813,8 @@
+     case POPCOUNT:
+     case PARITY:
+     case BSWAP:
+-      new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
++      new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
++				  for_costs);
+       if (new_rtx != XEXP (x, 0))
+ 	return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
+       return x;
+@@ -2834,7 +2835,8 @@
+ 	  new_rtx = SUBREG_REG (x);
+ 	}
+       else
+-	new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
++	new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false,
++				    for_costs);
+ 
+       if (new_rtx != SUBREG_REG (x))
+ 	{
+@@ -2868,14 +2870,20 @@
+       /* Our only special processing is to pass the mode of the MEM to our
+ 	 recursive call and copy the flags.  While we are here, handle this
+ 	 case more efficiently.  */
+-      return
+-	replace_equiv_address_nv (x,
+-				  eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
+-						    insn, true));
++
++      new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
++				  for_costs);
++      if (for_costs
++	  && memory_address_p (GET_MODE (x), XEXP (x, 0))
++	  && !memory_address_p (GET_MODE (x), new_rtx))
++	for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
++
++      return replace_equiv_address_nv (x, new_rtx);
+ 
+     case USE:
+       /* Handle insn_list USE that a call to a pure function may generate.  */
+-      new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
++      new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
++				  for_costs);
+       if (new_rtx != XEXP (x, 0))
+ 	return gen_rtx_USE (GET_MODE (x), new_rtx);
+       return x;
+@@ -2899,7 +2907,8 @@
+     {
+       if (*fmt == 'e')
+ 	{
+-	  new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
++	  new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
++				      for_costs);
+ 	  if (new_rtx != XEXP (x, i) && ! copied)
+ 	    {
+ 	      x = shallow_copy_rtx (x);
+@@ -2912,7 +2921,8 @@
+ 	  int copied_vec = 0;
+ 	  for (j = 0; j < XVECLEN (x, i); j++)
+ 	    {
+-	      new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
++	      new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
++					  for_costs);
+ 	      if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
+ 		{
+ 		  rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
+@@ -2936,7 +2946,7 @@
+ rtx
+ eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
+ {
+-  return eliminate_regs_1 (x, mem_mode, insn, false);
++  return eliminate_regs_1 (x, mem_mode, insn, false, false);
+ }
+ 
+ /* Scan rtx X for modifications of elimination target registers.  Update
+@@ -3454,7 +3464,8 @@
+ 	  /* Companion to the above plus substitution, we can allow
+ 	     invariants as the source of a plain move.  */
+ 	  is_set_src = false;
+-	  if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
++	  if (old_set
++	      && recog_data.operand_loc[i] == &SET_SRC (old_set))
+ 	    is_set_src = true;
+ 	  in_plus = false;
+ 	  if (plus_src
+@@ -3465,7 +3476,7 @@
+ 	  substed_operand[i]
+ 	    = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
+ 			        replace ? insn : NULL_RTX,
+-				is_set_src || in_plus);
++				is_set_src || in_plus, false);
+ 	  if (substed_operand[i] != orig_operand[i])
+ 	    val = 1;
+ 	  /* Terminate the search in check_eliminable_occurrences at
+@@ -3593,11 +3604,167 @@
+      the pre-passes.  */
+   if (val && REG_NOTES (insn) != 0)
+     REG_NOTES (insn)
+-      = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
++      = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
++			  false);
+ 
+   return val;
+ }
+ 
++/* Like eliminate_regs_in_insn, but only estimate costs for the use of the
++   register allocator.  INSN is the instruction we need to examine, we perform
++   eliminations in its operands and record cases where eliminating a reg with
++   an invariant equivalence would add extra cost.  */
++
++static void
++elimination_costs_in_insn (rtx insn)
++{
++  int icode = recog_memoized (insn);
++  rtx old_body = PATTERN (insn);
++  int insn_is_asm = asm_noperands (old_body) >= 0;
++  rtx old_set = single_set (insn);
++  int i;
++  rtx orig_operand[MAX_RECOG_OPERANDS];
++  rtx orig_dup[MAX_RECOG_OPERANDS];
++  struct elim_table *ep;
++  rtx plus_src, plus_cst_src;
++  bool sets_reg_p;
++
++  if (! insn_is_asm && icode < 0)
++    {
++      gcc_assert (GET_CODE (PATTERN (insn)) == USE
++		  || GET_CODE (PATTERN (insn)) == CLOBBER
++		  || GET_CODE (PATTERN (insn)) == ADDR_VEC
++		  || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
++		  || GET_CODE (PATTERN (insn)) == ASM_INPUT
++		  || DEBUG_INSN_P (insn));
++      return;
++    }
++
++  if (old_set != 0 && REG_P (SET_DEST (old_set))
++      && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
++    {
++      /* Check for setting an eliminable register.  */
++      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
++	if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
++	  return;
++    }
++
++  /* We allow one special case which happens to work on all machines we
++     currently support: a single set with the source or a REG_EQUAL
++     note being a PLUS of an eliminable register and a constant.  */
++  plus_src = plus_cst_src = 0;
++  sets_reg_p = false;
++  if (old_set && REG_P (SET_DEST (old_set)))
++    {
++      sets_reg_p = true;
++      if (GET_CODE (SET_SRC (old_set)) == PLUS)
++	plus_src = SET_SRC (old_set);
++      /* First see if the source is of the form (plus (...) CST).  */
++      if (plus_src
++	  && CONST_INT_P (XEXP (plus_src, 1)))
++	plus_cst_src = plus_src;
++      else if (REG_P (SET_SRC (old_set))
++	       || plus_src)
++	{
++	  /* Otherwise, see if we have a REG_EQUAL note of the form
++	     (plus (...) CST).  */
++	  rtx links;
++	  for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
++	    {
++	      if ((REG_NOTE_KIND (links) == REG_EQUAL
++		   || REG_NOTE_KIND (links) == REG_EQUIV)
++		  && GET_CODE (XEXP (links, 0)) == PLUS
++		  && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
++		{
++		  plus_cst_src = XEXP (links, 0);
++		  break;
++		}
++	    }
++	}
++    }
++
++  /* Determine the effects of this insn on elimination offsets.  */
++  elimination_effects (old_body, VOIDmode);
++
++  /* Eliminate all eliminable registers occurring in operands that
++     can be handled by reload.  */
++  extract_insn (insn);
++  for (i = 0; i < recog_data.n_dups; i++)
++    orig_dup[i] = *recog_data.dup_loc[i];
++
++  for (i = 0; i < recog_data.n_operands; i++)
++    {
++      orig_operand[i] = recog_data.operand[i];
++
++      /* For an asm statement, every operand is eliminable.  */
++      if (insn_is_asm || insn_data[icode].operand[i].eliminable)
++	{
++	  bool is_set_src, in_plus;
++
++	  /* Check for setting a register that we know about.  */
++	  if (recog_data.operand_type[i] != OP_IN
++	      && REG_P (orig_operand[i]))
++	    {
++	      /* If we are assigning to a register that can be eliminated, it
++		 must be as part of a PARALLEL, since the code above handles
++		 single SETs.  We must indicate that we can no longer
++		 eliminate this reg.  */
++	      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
++		   ep++)
++		if (ep->from_rtx == orig_operand[i])
++		  ep->can_eliminate = 0;
++	    }
++
++	  /* Companion to the above plus substitution, we can allow
++	     invariants as the source of a plain move.  */
++	  is_set_src = false;
++	  if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
++	    is_set_src = true;
++	  if (is_set_src && !sets_reg_p)
++	    note_reg_elim_costly (&SET_SRC (old_set), insn);
++	  in_plus = false;
++	  if (plus_src && sets_reg_p
++	      && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
++		  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
++	    in_plus = true;
++
++	  eliminate_regs_1 (recog_data.operand[i], VOIDmode,
++			    NULL_RTX,
++			    is_set_src || in_plus, true);
++	  /* Terminate the search in check_eliminable_occurrences at
++	     this point.  */
++	  *recog_data.operand_loc[i] = 0;
++	}
++    }
++
++  for (i = 0; i < recog_data.n_dups; i++)
++    *recog_data.dup_loc[i]
++      = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
++
++  /* If any eliminable remain, they aren't eliminable anymore.  */
++  check_eliminable_occurrences (old_body);
++
++  /* Restore the old body.  */
++  for (i = 0; i < recog_data.n_operands; i++)
++    *recog_data.operand_loc[i] = orig_operand[i];
++  for (i = 0; i < recog_data.n_dups; i++)
++    *recog_data.dup_loc[i] = orig_dup[i];
++
++  /* Update all elimination pairs to reflect the status after the current
++     insn.  The changes we make were determined by the earlier call to
++     elimination_effects.  */
++
++  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
++    {
++      if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
++	ep->can_eliminate = 0;
++
++      ep->ref_outside_mem = 0;
++    }
++
++  return;
++}
++
+ /* Loop through all elimination pairs.
+    Recalculate the number not at initial offset.
+ 
+@@ -3907,6 +4074,168 @@
+       ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
+     }
+ }
++
++/* Find all the pseudo registers that didn't get hard regs
++   but do have known equivalent constants or memory slots.
++   These include parameters (known equivalent to parameter slots)
++   and cse'd or loop-moved constant memory addresses.
++
++   Record constant equivalents in reg_equiv_constant
++   so they will be substituted by find_reloads.
++   Record memory equivalents in reg_mem_equiv so they can
++   be substituted eventually by altering the REG-rtx's.  */
++
++static void
++init_eliminable_invariants (rtx first, bool do_subregs)
++{
++  int i;
++  rtx insn;
++
++  reg_equiv_constant = XCNEWVEC (rtx, max_regno);
++  reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
++  reg_equiv_mem = XCNEWVEC (rtx, max_regno);
++  reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
++  reg_equiv_address = XCNEWVEC (rtx, max_regno);
++  if (do_subregs)
++    reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
++  else
++    reg_max_ref_width = NULL;
++
++  num_eliminable_invariants = 0;
++
++  first_label_num = get_first_label_num ();
++  num_labels = max_label_num () - first_label_num;
++
++  /* Allocate the tables used to store offset information at labels.  */
++  offsets_known_at = XNEWVEC (char, num_labels);
++  offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
++
++/* Look for REG_EQUIV notes; record what each pseudo is equivalent
++   to.  If DO_SUBREGS is true, also find all paradoxical subregs and
++   find largest such for each pseudo.  FIRST is the head of the insn
++   list.  */
++
++  for (insn = first; insn; insn = NEXT_INSN (insn))
++    {
++      rtx set = single_set (insn);
++
++      /* We may introduce USEs that we want to remove at the end, so
++	 we'll mark them with QImode.  Make sure there are no
++	 previously-marked insns left by say regmove.  */
++      if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
++	  && GET_MODE (insn) != VOIDmode)
++	PUT_MODE (insn, VOIDmode);
++
++      if (do_subregs && NONDEBUG_INSN_P (insn))
++	scan_paradoxical_subregs (PATTERN (insn));
++
++      if (set != 0 && REG_P (SET_DEST (set)))
++	{
++	  rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
++	  rtx x;
++
++	  if (! note)
++	    continue;
++
++	  i = REGNO (SET_DEST (set));
++	  x = XEXP (note, 0);
++
++	  if (i <= LAST_VIRTUAL_REGISTER)
++	    continue;
++
++	  /* If flag_pic and we have constant, verify it's legitimate.  */
++	  if (!CONSTANT_P (x)
++	      || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
++	    {
++	      /* It can happen that a REG_EQUIV note contains a MEM
++		 that is not a legitimate memory operand.  As later
++		 stages of reload assume that all addresses found
++		 in the reg_equiv_* arrays were originally legitimate,
++		 we ignore such REG_EQUIV notes.  */
++	      if (memory_operand (x, VOIDmode))
++		{
++		  /* Always unshare the equivalence, so we can
++		     substitute into this insn without touching the
++		       equivalence.  */
++		  reg_equiv_memory_loc[i] = copy_rtx (x);
++		}
++	      else if (function_invariant_p (x))
++		{
++		  if (GET_CODE (x) == PLUS)
++		    {
++		      /* This is PLUS of frame pointer and a constant,
++			 and might be shared.  Unshare it.  */
++		      reg_equiv_invariant[i] = copy_rtx (x);
++		      num_eliminable_invariants++;
++		    }
++		  else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
++		    {
++		      reg_equiv_invariant[i] = x;
++		      num_eliminable_invariants++;
++		    }
++		  else if (LEGITIMATE_CONSTANT_P (x))
++		    reg_equiv_constant[i] = x;
++		  else
++		    {
++		      reg_equiv_memory_loc[i]
++			= force_const_mem (GET_MODE (SET_DEST (set)), x);
++		      if (! reg_equiv_memory_loc[i])
++			reg_equiv_init[i] = NULL_RTX;
++		    }
++		}
++	      else
++		{
++		  reg_equiv_init[i] = NULL_RTX;
++		  continue;
++		}
++	    }
++	  else
++	    reg_equiv_init[i] = NULL_RTX;
++	}
++    }
++
++  if (dump_file)
++    for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
++      if (reg_equiv_init[i])
++	{
++	  fprintf (dump_file, "init_insns for %u: ", i);
++	  print_inline_rtx (dump_file, reg_equiv_init[i], 20);
++	  fprintf (dump_file, "\n");
++	}
++}
++
++/* Indicate that we no longer have known memory locations or constants.
++   Free all data involved in tracking these.  */
++
++static void
++free_reg_equiv (void)
++{
++  int i;
++
++  if (reg_equiv_constant)
++    free (reg_equiv_constant);
++  if (reg_equiv_invariant)
++    free (reg_equiv_invariant);
++  reg_equiv_constant = 0;
++  reg_equiv_invariant = 0;
++  VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
++  reg_equiv_memory_loc = 0;
++
++  if (offsets_known_at)
++    free (offsets_known_at);
++  if (offsets_at)
++    free (offsets_at);
++  offsets_at = 0;
++  offsets_known_at = 0;
++
++  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
++    if (reg_equiv_alt_mem_list[i])
++      free_EXPR_LIST_list (&reg_equiv_alt_mem_list[i]);
++  free (reg_equiv_alt_mem_list);
++
++  free (reg_equiv_mem);
++  free (reg_equiv_address);
++}
+ 
+ /* Kick all pseudos out of hard register REGNO.
+ 
+@@ -5664,7 +5993,7 @@
+     return 1;
+   if (GET_CODE (x) == PLUS
+       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
+-      && CONSTANT_P (XEXP (x, 1)))
++      && GET_CODE (XEXP (x, 1)) == CONST_INT)
+     return 1;
+   return 0;
+ }
+Index: gcc-4_5-branch/gcc/system.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/system.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/system.h	2012-03-06 12:14:01.060439213 -0800
+@@ -761,7 +761,8 @@
+ 	TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION	   \
+ 	SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON	   \
+ 	ASM_OUTPUT_SHARED_LOCAL ASM_MAKE_LABEL_LINKONCE			   \
+-	STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD
++	STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD		   \
++	ORDER_REGS_FOR_LOCAL_ALLOC
+ 
+ /* Hooks that are no longer used.  */
+  #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE	\
+Index: gcc-4_5-branch/gcc/testsuite/c-c++-common/uninit-17.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/c-c++-common/uninit-17.c	2012-03-06 12:14:01.060439213 -0800
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -Wuninitialized" } */
++
++inline int foo(int x)
++{
++  return x;
++}
++static void bar(int a, int *ptr)
++{
++  do
++  {
++    int b; /* { dg-warning "is used uninitialized" } */
++    if (b < 40) {
++      ptr[0] = b;
++    }
++    b += 1;
++    ptr++;
++  }
++  while (--a != 0);
++}
++void foobar(int a, int *ptr)
++{
++  bar(foo(a), ptr);
++}
++
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/eliminate.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/eliminate.c	2012-03-06 12:14:01.060439213 -0800
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++
++struct X
++{
++  int c;
++};
++
++extern void bar(struct X *);
++
++void foo ()
++{
++  struct X x;
++  bar (&x);
++  bar (&x);
++  bar (&x);
++}
++
++/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr40900.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr40900.c	2012-03-06 12:14:01.060439213 -0800
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-optimize-sibling-calls" }  */
++
++extern short shortv2();
++short shortv1()
++{
++  return shortv2();
++}
++
++/* { dg-final { scan-assembler-not "lsl" } } */
++/* { dg-final { scan-assembler-not "asr" } } */
++/* { dg-final { scan-assembler-not "sxth" } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr42496.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr42496.c	2012-03-06 12:14:01.060439213 -0800
+@@ -0,0 +1,16 @@
++/* { dg-options "-O2" }  */
++
++void foo(int i)
++{
++    extern int j;
++
++    if (i) {
++         j = 10;
++    }
++    else {
++          j = 20;
++    }
++}
++
++/* { dg-final { scan-assembler-not "strne" } } */
++/* { dg-final { scan-assembler-not "streq" } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c	2012-03-06 12:14:01.060439213 -0800
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */
++
++int mac(const short *a, const short *b, int sqr, int *sum)
++{
++  int i;
++  int dotp = *sum;
++
++  for (i = 0; i < 150; i++) {
++    dotp += b[i] * a[i];
++    sqr += b[i] * b[i];
++  }
++
++  *sum = dotp;
++  return sqr;
++}
++
++/* { dg-final { scan-assembler-times "smulbb" 2 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-2.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-2.c	2012-03-06 12:14:01.064439219 -0800
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */
++
++void vec_mpy(int y[], const short x[], short scaler)
++{
++ int i;
++
++ for (i = 0; i < 150; i++)
++   y[i] += ((scaler * x[i]) >> 31);
++}
++
++/* { dg-final { scan-assembler-times "smulbb" 1 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-1.c	2012-03-06 12:14:01.064439219 -0800
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int mac(const short *a, const short *b, int sqr, int *sum)
++{
++  int i;
++  int dotp = *sum;
++
++  for (i = 0; i < 150; i++) {
++    dotp += b[i] * a[i];
++    sqr += b[i] * b[i];
++  }
++
++  *sum = dotp;
++  return sqr;
++}
++
++/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-2.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-2.c	2012-03-06 12:14:01.064439219 -0800
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++void vec_mpy(int y[], const short x[], short scaler)
++{
++ int i;
++
++ for (i = 0; i < 150; i++)
++   y[i] += ((scaler * x[i]) >> 31);
++}
++
++/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr41442.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr41442.c	2012-03-06 12:14:01.064439219 -0800
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef struct LINK link;
++struct LINK
++{
++    link* next;
++};
++
++int haha(link* p1, link* p2)
++{
++  if ((p1->next && !p2->next) || p2->next)
++    return 0;
++
++  return 1;
++}
++
++/* { dg-final { scan-assembler-times "test|cmp" 2 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-1.c	2012-03-06 12:14:01.064439219 -0800
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++long long mac(const int *a, const int *b, long long sqr, long long *sum)
++{
++  int i;
++  long long dotp = *sum;
++
++  for (i = 0; i < 150; i++) {
++    dotp += (long long)b[i] * a[i];
++    sqr += (long long)b[i] * b[i];
++  }
++
++  *sum = dotp;
++  return sqr;
++}
++
++/* { dg-final { scan-assembler-times "imull" 2 } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-2.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-2.c	2012-03-06 12:14:01.064439219 -0800
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++void vec_mpy(int y[], const int x[], int scaler)
++{
++ int i;
++
++ for (i = 0; i < 150; i++)
++   y[i] += (((long long)scaler * x[i]) >> 31);
++}
++
++/* { dg-final { scan-assembler-times "imull" 1 } } */
+Index: gcc-4_5-branch/gcc/tree-cfg.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-cfg.c	2012-03-06 12:11:30.000000000 -0800
++++ gcc-4_5-branch/gcc/tree-cfg.c	2012-03-06 12:14:01.064439219 -0800
+@@ -3429,8 +3429,13 @@
+ 	 connected to the operand types.  */
+       return verify_gimple_comparison (lhs_type, rhs1, rhs2);
+ 
+-    case WIDEN_SUM_EXPR:
+     case WIDEN_MULT_EXPR:
++      if (TREE_CODE (lhs_type) != INTEGER_TYPE)
++	return true;
++      return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type))
++	      || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)));
++
++    case WIDEN_SUM_EXPR:
+     case VEC_WIDEN_MULT_HI_EXPR:
+     case VEC_WIDEN_MULT_LO_EXPR:
+     case VEC_PACK_TRUNC_EXPR:
+Index: gcc-4_5-branch/gcc/tree-inline.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-inline.c	2012-03-06 12:11:30.000000000 -0800
++++ gcc-4_5-branch/gcc/tree-inline.c	2012-03-06 12:14:01.064439219 -0800
+@@ -229,6 +229,7 @@
+ 	     regions of the CFG, but this is expensive to test.  */
+ 	  if (id->entry_bb
+ 	      && is_gimple_reg (SSA_NAME_VAR (name))
++	      && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (name)
+ 	      && TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL
+ 	      && (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest
+ 		  || EDGE_COUNT (id->entry_bb->preds) != 1))
+Index: gcc-4_5-branch/gcc/tree-pass.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-pass.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/tree-pass.h	2012-03-06 12:14:01.068439233 -0800
+@@ -407,6 +407,7 @@
+ extern struct gimple_opt_pass pass_cse_reciprocals;
+ extern struct gimple_opt_pass pass_cse_sincos;
+ extern struct gimple_opt_pass pass_optimize_bswap;
++extern struct gimple_opt_pass pass_optimize_widening_mul;
+ extern struct gimple_opt_pass pass_warn_function_return;
+ extern struct gimple_opt_pass pass_warn_function_noreturn;
+ extern struct gimple_opt_pass pass_cselim;
+Index: gcc-4_5-branch/gcc/tree-ssa-math-opts.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-math-opts.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/tree-ssa-math-opts.c	2012-03-06 12:14:01.068439233 -0800
+@@ -1269,3 +1269,137 @@
+   0                                     /* todo_flags_finish */
+  }
+ };
++
++/* Find integer multiplications where the operands are extended from
++   smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR
++   where appropriate.  */
++
++static unsigned int
++execute_optimize_widening_mul (void)
++{
++  bool changed = false;
++  basic_block bb;
++
++  FOR_EACH_BB (bb)
++    {
++      gimple_stmt_iterator gsi;
++
++      for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi))
++        {
++	  gimple stmt = gsi_stmt (gsi);
++	  gimple rhs1_stmt = NULL, rhs2_stmt = NULL;
++	  tree type, type1 = NULL, type2 = NULL;
++	  tree rhs1, rhs2, rhs1_convop = NULL, rhs2_convop = NULL;
++	  enum tree_code rhs1_code, rhs2_code;
++
++	  if (!is_gimple_assign (stmt)
++	      || gimple_assign_rhs_code (stmt) != MULT_EXPR)
++	    continue;
++
++	  type = TREE_TYPE (gimple_assign_lhs (stmt));
++
++	  if (TREE_CODE (type) != INTEGER_TYPE)
++	    continue;
++
++	  rhs1 = gimple_assign_rhs1 (stmt);
++	  rhs2 = gimple_assign_rhs2 (stmt);
++
++	  if (TREE_CODE (rhs1) == SSA_NAME)
++	    {
++	      rhs1_stmt = SSA_NAME_DEF_STMT (rhs1);
++	      if (!is_gimple_assign (rhs1_stmt))
++		continue;
++	      rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
++	      if (!CONVERT_EXPR_CODE_P (rhs1_code))
++		continue;
++	      rhs1_convop = gimple_assign_rhs1 (rhs1_stmt);
++	      type1 = TREE_TYPE (rhs1_convop);
++	      if (TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type))
++		continue;
++	    }
++	  else if (TREE_CODE (rhs1) != INTEGER_CST)
++	    continue;
++
++	  if (TREE_CODE (rhs2) == SSA_NAME)
++	    {
++	      rhs2_stmt = SSA_NAME_DEF_STMT (rhs2);
++	      if (!is_gimple_assign (rhs2_stmt))
++		continue;
++	      rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
++	      if (!CONVERT_EXPR_CODE_P (rhs2_code))
++		continue;
++	      rhs2_convop = gimple_assign_rhs1 (rhs2_stmt);
++	      type2 = TREE_TYPE (rhs2_convop);
++	      if (TYPE_PRECISION (type2) * 2 != TYPE_PRECISION (type))
++		continue;
++	    }
++	  else if (TREE_CODE (rhs2) != INTEGER_CST)
++	    continue;
++
++	  if (rhs1_stmt == NULL && rhs2_stmt == NULL)
++	    continue;
++
++	  /* Verify that the machine can perform a widening multiply in this
++	     mode/signedness combination, otherwise this transformation is
++	     likely to pessimize code.  */
++	  if ((rhs1_stmt == NULL || TYPE_UNSIGNED (type1))
++	      && (rhs2_stmt == NULL || TYPE_UNSIGNED (type2))
++	      && (optab_handler (umul_widen_optab, TYPE_MODE (type))
++		  ->insn_code == CODE_FOR_nothing))
++	    continue;
++	  else if ((rhs1_stmt == NULL || !TYPE_UNSIGNED (type1))
++		   && (rhs2_stmt == NULL || !TYPE_UNSIGNED (type2))
++		   && (optab_handler (smul_widen_optab, TYPE_MODE (type))
++		       ->insn_code == CODE_FOR_nothing))
++	    continue;
++	  else if (rhs1_stmt != NULL && rhs2_stmt != 0
++		   && (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2))
++		   && (optab_handler (usmul_widen_optab, TYPE_MODE (type))
++		       ->insn_code == CODE_FOR_nothing))
++	    continue;
++
++	  if ((rhs1_stmt == NULL && !int_fits_type_p (rhs1, type2))
++	      || (rhs2_stmt == NULL && !int_fits_type_p (rhs2, type1)))
++	    continue;
++
++	  if (rhs1_stmt == NULL)
++	    gimple_assign_set_rhs1 (stmt, fold_convert (type2, rhs1));
++	  else
++	    gimple_assign_set_rhs1 (stmt, rhs1_convop);
++	  if (rhs2_stmt == NULL)
++	    gimple_assign_set_rhs2 (stmt, fold_convert (type1, rhs2));
++	  else
++	    gimple_assign_set_rhs2 (stmt, rhs2_convop);
++	  gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR);
++	  update_stmt (stmt);
++	  changed = true;
++	}
++    }
++  return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa
++	  | TODO_verify_stmts : 0);
++}
++
++static bool
++gate_optimize_widening_mul (void)
++{
++  return flag_expensive_optimizations && optimize;
++}
++
++struct gimple_opt_pass pass_optimize_widening_mul =
++{
++ {
++  GIMPLE_PASS,
++  "widening_mul",			/* name */
++  gate_optimize_widening_mul,		/* gate */
++  execute_optimize_widening_mul,	/* execute */
++  NULL,					/* sub */
++  NULL,					/* next */
++  0,					/* static_pass_number */
++  TV_NONE,				/* tv_id */
++  PROP_ssa,				/* properties_required */
++  0,					/* properties_provided */
++  0,					/* properties_destroyed */
++  0,					/* todo_flags_start */
++  0                                     /* todo_flags_finish */
++ }
++};
+Index: gcc-4_5-branch/gcc/tree-ssa.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/tree-ssa.c	2012-03-06 12:14:01.068439233 -0800
+@@ -1671,6 +1671,8 @@
+     {
+       TREE_NO_WARNING (var) = 1;
+ 
++      if (location == DECL_SOURCE_LOCATION (var))
++	return;
+       if (xloc.file != floc.file
+ 	  || xloc.line < floc.line
+ 	  || xloc.line > LOCATION_LINE (cfun->function_end_locus))
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch
new file mode 100644
index 0000000000..c504f44fbe
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch
@@ -0,0 +1,512 @@
+2010-09-06  Mark Mitchell  <mark@codesourcery.com>
+
+	Issue #9022
+
+	Backport from mainline:
+	2010-09-05  Mark Mitchell  <mark@codesourcery.com>
+	* doc/invoke.texi: Document -Wdouble-promotion.
+	* c-typeck.c (convert_arguments): Check for implicit conversions
+	from float to double.
+	(do_warn_double_promotion): New function.
+	(build_conditional_expr): Use it.
+	(build_binary_op): Likewise.
+	* c.opt (Wdouble-promotion): New.
+	2010-09-05  Mark Mitchell  <mark@codesourcery.com>
+	* gcc.dg/Wdouble-promotion.c: New.
+	2010-09-06  Mark Mitchell  <mark@codesourcery.com>
+	gcc/
+	* c-common.h (do_warn_double_promotion): Declare.
+	* c-common.c (do_warn_double_promotion): Define.
+	* c-typeck.c (do_warn_double_promotion): Remove.
+	* doc/invoke.texi (-Wdouble-promotion): Note available for C++ and
+	Objective-C++ too.
+	gcc/cp/
+	* typeck.c (cp_build_binary_op): Call do_warn_double_promotion.
+	* call.c (build_conditional_expr): Likewise.
+	(convert_arg_to_ellipsis): Likewise.
+	gcc/testsuite/
+	* g++.dg/warn/Wdouble-promotion.C: New.
+
+ 2010-08-31  Chung-Lin Tang  <cltang@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/c-common.c'
+--- old/gcc/c-common.c	2010-06-25 09:35:40 +0000
++++ new/gcc/c-common.c	2010-09-07 15:47:57 +0000
+@@ -9172,6 +9172,40 @@
+     }
+ }
+ 
++/* RESULT_TYPE is the result of converting TYPE1 and TYPE2 to a common
++   type via c_common_type.  If -Wdouble-promotion is in use, and the
++   conditions for warning have been met, issue a warning.  GMSGID is
++   the warning message.  It must have two %T specifiers for the type
++   that was converted (generally "float") and the type to which it was
++   converted (generally "double), respectively.  LOC is the location
++   to which the awrning should refer.  */
++
++void
++do_warn_double_promotion (tree result_type, tree type1, tree type2,
++			 const char *gmsgid, location_t loc)
++{
++  tree source_type;
++
++  if (!warn_double_promotion)
++    return;
++  /* If the conversion will not occur at run-time, there is no need to
++     warn about it.  */
++  if (c_inhibit_evaluation_warnings)
++    return;
++  if (TYPE_MAIN_VARIANT (result_type) != double_type_node
++      && TYPE_MAIN_VARIANT (result_type) != complex_double_type_node)
++    return;
++  if (TYPE_MAIN_VARIANT (type1) == float_type_node
++      || TYPE_MAIN_VARIANT (type1) == complex_float_type_node)
++    source_type = type1;
++  else if (TYPE_MAIN_VARIANT (type2) == float_type_node
++	   || TYPE_MAIN_VARIANT (type2) == complex_float_type_node)
++    source_type = type2;
++  else
++    return;
++  warning_at (loc, OPT_Wdouble_promotion, gmsgid, source_type, result_type);
++}
++
+ /* Setup a TYPE_DECL node as a typedef representation.
+ 
+    X is a TYPE_DECL for a typedef statement.  Create a brand new
+
+=== modified file 'gcc/c-common.h'
+--- old/gcc/c-common.h	2009-12-17 03:22:22 +0000
++++ new/gcc/c-common.h	2010-09-07 15:47:57 +0000
+@@ -1056,6 +1056,8 @@
+ 				   tree op0, tree op1,
+ 				   tree result_type,
+ 				   enum tree_code resultcode);
++extern void do_warn_double_promotion (tree, tree, tree, const char *, 
++				      location_t);
+ extern void set_underlying_type (tree x);
+ extern bool is_typedef_decl (tree x);
+ extern VEC(tree,gc) *make_tree_vector (void);
+
+=== modified file 'gcc/c-typeck.c'
+--- old/gcc/c-typeck.c	2010-04-02 18:54:46 +0000
++++ new/gcc/c-typeck.c	2010-09-07 15:47:57 +0000
+@@ -3012,8 +3012,15 @@
+ 	  if (type_generic)
+ 	    parmval = val;
+ 	  else
+-	    /* Convert `float' to `double'.  */
+-	    parmval = convert (double_type_node, val);
++	    {
++	      /* Convert `float' to `double'.  */
++	      if (warn_double_promotion && !c_inhibit_evaluation_warnings)
++		warning (OPT_Wdouble_promotion,
++			 "implicit conversion from %qT to %qT when passing "
++			 "argument to function",
++			 valtype, double_type_node);
++	      parmval = convert (double_type_node, val);
++	    }
+ 	}
+       else if (excess_precision && !type_generic)
+ 	/* A "double" argument with excess precision being passed
+@@ -4036,6 +4043,10 @@
+ 	       || code2 == COMPLEX_TYPE))
+     {
+       result_type = c_common_type (type1, type2);
++      do_warn_double_promotion (result_type, type1, type2,
++				"implicit conversion from %qT to %qT to "
++				"match other result of conditional",
++				colon_loc);
+ 
+       /* If -Wsign-compare, warn here if type1 and type2 have
+ 	 different signedness.  We'll promote the signed to unsigned
+@@ -9607,6 +9618,11 @@
+       if (shorten || common || short_compare)
+ 	{
+ 	  result_type = c_common_type (type0, type1);
++	  do_warn_double_promotion (result_type, type0, type1,
++				    "implicit conversion from %qT to %qT "
++				    "to match other operand of binary "
++				    "expression",
++				    location);
+ 	  if (result_type == error_mark_node)
+ 	    return error_mark_node;
+ 	}
+
+=== modified file 'gcc/c.opt'
+--- old/gcc/c.opt	2010-04-02 18:54:46 +0000
++++ new/gcc/c.opt	2010-09-07 15:47:57 +0000
+@@ -265,6 +265,10 @@
+ Wimplicit
+ C ObjC C++ ObjC++ Warning
+ 
++Wdouble-promotion
++C ObjC C++ ObjC++ Var(warn_double_promotion) Warning
++Warn about implicit conversions from \"float\" to \"double\"
++
+ Wimplicit-function-declaration
+ C ObjC Var(warn_implicit_function_declaration) Init(-1) Warning
+ Warn about implicit function declarations
+
+=== modified file 'gcc/cp/call.c'
+--- old/gcc/cp/call.c	2010-07-08 13:08:36 +0000
++++ new/gcc/cp/call.c	2010-09-07 15:47:57 +0000
+@@ -3946,6 +3946,10 @@
+       /* In this case, there is always a common type.  */
+       result_type = type_after_usual_arithmetic_conversions (arg2_type,
+ 							     arg3_type);
++      do_warn_double_promotion (result_type, arg2_type, arg3_type,
++				"implicit conversion from %qT to %qT to "
++				"match other result of conditional",
++				input_location);
+ 
+       if (TREE_CODE (arg2_type) == ENUMERAL_TYPE
+ 	  && TREE_CODE (arg3_type) == ENUMERAL_TYPE)
+@@ -5179,11 +5183,14 @@
+ tree
+ convert_arg_to_ellipsis (tree arg)
+ {
++  tree arg_type;
++
+   /* [expr.call]
+ 
+      The lvalue-to-rvalue, array-to-pointer, and function-to-pointer
+      standard conversions are performed.  */
+   arg = decay_conversion (arg);
++  arg_type = TREE_TYPE (arg);
+   /* [expr.call]
+ 
+      If the argument has integral or enumeration type that is subject
+@@ -5191,19 +5198,27 @@
+      type that is subject to the floating point promotion
+      (_conv.fpprom_), the value of the argument is converted to the
+      promoted type before the call.  */
+-  if (TREE_CODE (TREE_TYPE (arg)) == REAL_TYPE
+-      && (TYPE_PRECISION (TREE_TYPE (arg))
++  if (TREE_CODE (arg_type) == REAL_TYPE
++      && (TYPE_PRECISION (arg_type)
+ 	  < TYPE_PRECISION (double_type_node))
+-      && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (arg))))
+-    arg = convert_to_real (double_type_node, arg);
+-  else if (INTEGRAL_OR_ENUMERATION_TYPE_P (TREE_TYPE (arg)))
++      && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (arg_type)))
++    {
++      if (warn_double_promotion && !c_inhibit_evaluation_warnings)
++	warning (OPT_Wdouble_promotion,
++		 "implicit conversion from %qT to %qT when passing "
++		 "argument to function",
++		 arg_type, double_type_node);
++      arg = convert_to_real (double_type_node, arg);
++    }
++  else if (INTEGRAL_OR_ENUMERATION_TYPE_P (arg_type))
+     arg = perform_integral_promotions (arg);
+ 
+   arg = require_complete_type (arg);
++  arg_type = TREE_TYPE (arg);
+ 
+   if (arg != error_mark_node
+-      && (type_has_nontrivial_copy_init (TREE_TYPE (arg))
+-	  || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (arg))))
++      && (type_has_nontrivial_copy_init (arg_type)
++	  || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (arg_type)))
+     {
+       /* [expr.call] 5.2.2/7:
+ 	 Passing a potentially-evaluated argument of class type (Clause 9)
+@@ -5218,7 +5233,7 @@
+ 	 it is not potentially-evaluated.  */
+       if (cp_unevaluated_operand == 0)
+ 	error ("cannot pass objects of non-trivially-copyable "
+-	       "type %q#T through %<...%>", TREE_TYPE (arg));
++	       "type %q#T through %<...%>", arg_type);
+     }
+ 
+   return arg;
+
+=== modified file 'gcc/cp/typeck.c'
+--- old/gcc/cp/typeck.c	2010-06-30 21:06:28 +0000
++++ new/gcc/cp/typeck.c	2010-09-07 15:47:57 +0000
+@@ -260,6 +260,7 @@
+   enum tree_code code2 = TREE_CODE (t2);
+   tree attributes;
+ 
++
+   /* In what follows, we slightly generalize the rules given in [expr] so
+      as to deal with `long long' and `complex'.  First, merge the
+      attributes.  */
+@@ -4226,7 +4227,14 @@
+   if (!result_type
+       && arithmetic_types_p
+       && (shorten || common || short_compare))
+-    result_type = cp_common_type (type0, type1);
++    {
++      result_type = cp_common_type (type0, type1);
++      do_warn_double_promotion (result_type, type0, type1,
++				"implicit conversion from %qT to %qT "
++				"to match other operand of binary "
++				"expression",
++				location);
++    }
+ 
+   if (!result_type)
+     {
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-08-16 09:41:58 +0000
++++ new/gcc/doc/invoke.texi	2010-09-07 15:47:57 +0000
+@@ -234,8 +234,8 @@
+ -Wchar-subscripts -Wclobbered  -Wcomment @gol
+ -Wconversion  -Wcoverage-mismatch  -Wno-deprecated  @gol
+ -Wno-deprecated-declarations -Wdisabled-optimization  @gol
+--Wno-div-by-zero -Wempty-body  -Wenum-compare -Wno-endif-labels @gol
+--Werror  -Werror=* @gol
++-Wno-div-by-zero -Wdouble-promotion -Wempty-body  -Wenum-compare @gol
++-Wno-endif-labels -Werror  -Werror=* @gol
+ -Wfatal-errors  -Wfloat-equal  -Wformat  -Wformat=2 @gol
+ -Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol
+ -Wformat-security  -Wformat-y2k @gol
+@@ -2976,6 +2976,30 @@
+ comment, or whenever a Backslash-Newline appears in a @samp{//} comment.
+ This warning is enabled by @option{-Wall}.
+ 
++@item -Wdouble-promotion @r{(C, C++, Objective-C and Objective-C++ only)}
++@opindex Wdouble-promotion
++@opindex Wno-double-promotion
++Give a warning when a value of type @code{float} is implicitly
++promoted to @code{double}.  CPUs with a 32-bit ``single-precision''
++floating-point unit implement @code{float} in hardware, but emulate
++@code{double} in software.  On such a machine, doing computations
++using @code{double} values is much more expensive because of the
++overhead required for software emulation.  
++
++It is easy to accidentally do computations with @code{double} because
++floating-point literals are implicitly of type @code{double}.  For
++example, in:
++@smallexample
++@group
++float area(float radius)
++@{
++   return 3.14159 * radius * radius;        
++@}
++@end group
++@end smallexample
++the compiler will perform the entire computation with @code{double}
++because the floating-point literal is a @code{double}.
++
+ @item -Wformat
+ @opindex Wformat
+ @opindex Wno-format
+
+=== added file 'gcc/testsuite/g++.dg/warn/Wdouble-promotion.C'
+--- old/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C	2010-09-07 15:47:57 +0000
+@@ -0,0 +1,99 @@
++/* { dg-do compile } */
++/* { dg-options "-Wdouble-promotion" } */
++
++#include <stddef.h>
++
++/* Some targets do not provide <complex.h> so we define I ourselves.  */
++#define I 1.0iF
++#define ID ((_Complex double)I)
++
++float f;
++double d;
++int i;
++long double ld;
++_Complex float cf;
++_Complex double cd;
++_Complex long double cld;
++size_t s;
++
++extern void varargs_fn (int, ...);
++extern void double_fn (double);
++extern float float_fn (void);
++
++void 
++usual_arithmetic_conversions(void) 
++{
++  float local_f;
++  _Complex float local_cf;
++
++  /* Values of type "float" are implicitly converted to "double" or
++     "long double" due to use in arithmetic with "double" or "long
++     double" operands.  */
++  local_f = f + 1.0;         /* { dg-warning "implicit" } */
++  local_f = f - d;           /* { dg-warning "implicit" } */
++  local_f = 1.0f * 1.0;      /* { dg-warning "implicit" } */
++  local_f = 1.0f / d;        /* { dg-warning "implicit" } */
++
++  local_cf = cf + 1.0;       /* { dg-warning "implicit" } */
++  local_cf = cf - d;         /* { dg-warning "implicit" } */
++  local_cf = cf + 1.0 * ID;  /* { dg-warning "implicit" } */
++  local_cf = cf - cd;        /* { dg-warning "implicit" } */
++  
++  local_f = i ? f : d;       /* { dg-warning "implicit" } */
++  i = f == d;                /* { dg-warning "implicit" } */
++  i = d != f;                /* { dg-warning "implicit" } */
++}
++
++void 
++default_argument_promotion (void) 
++{
++  /* Because "f" is part of the variable argument list, it is promoted
++     to "double".  */
++  varargs_fn (1, f);   /* { dg-warning "implicit" } */
++}
++
++/* There is no warning when an explicit cast is used to perform the
++   conversion.  */
++
++void
++casts (void) 
++{
++  float local_f;
++  _Complex float local_cf;
++
++  local_f = (double)f + 1.0;                 /* { dg-bogus "implicit" } */
++  local_f = (double)f - d;                   /* { dg-bogus "implicit" } */
++  local_f = (double)1.0f + 1.0;              /* { dg-bogus "implicit" } */
++  local_f = (double)1.0f - d;                /* { dg-bogus "implicit" } */
++
++  local_cf = (_Complex double)cf + 1.0;      /* { dg-bogus "implicit" } */
++  local_cf = (_Complex double)cf - d;        /* { dg-bogus "implicit" } */
++  local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */
++  local_cf = (_Complex double)cf - cd;       /* { dg-bogus "implicit" } */
++
++  local_f = i ? (double)f : d;               /* { dg-bogus "implicit" } */
++  i = (double)f == d;                        /* { dg-bogus "implicit" } */
++  i = d != (double)f;                        /* { dg-bogus "implicit" } */
++}
++
++/* There is no warning on conversions that occur in assignment (and
++   assignment-like) contexts.  */
++
++void 
++assignments (void)
++{
++  d = f;           /* { dg-bogus "implicit" } */
++  double_fn (f);   /* { dg-bogus "implicit" } */
++  d = float_fn (); /* { dg-bogus "implicit" } */
++}
++
++/* There is no warning in non-evaluated contexts.  */
++
++void
++non_evaluated (void)
++{
++  s = sizeof (f + 1.0);             /* { dg-bogus "implicit" } */
++  s = __alignof__ (f + 1.0);        /* { dg-bogus "implicit" } */
++  d = (__typeof__(f + 1.0))f;       /* { dg-bogus "implicit" } */
++  s = sizeof (i ? f : d);           /* { dg-bogus "implicit" } */
++}
+
+=== added file 'gcc/testsuite/gcc.dg/Wdouble-promotion.c'
+--- old/gcc/testsuite/gcc.dg/Wdouble-promotion.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/Wdouble-promotion.c	2010-09-07 15:47:57 +0000
+@@ -0,0 +1,104 @@
++/* { dg-do compile } */
++/* { dg-options "-Wdouble-promotion" } */
++
++#include <stddef.h>
++
++/* Some targets do not provide <complex.h> so we define I ourselves.  */
++#define I 1.0iF
++#define ID ((_Complex double)I)
++
++float f;
++double d;
++int i;
++long double ld;
++_Complex float cf;
++_Complex double cd;
++_Complex long double cld;
++size_t s;
++
++extern void unprototyped_fn ();
++extern void varargs_fn (int, ...);
++extern void double_fn (double);
++extern float float_fn (void);
++
++void 
++usual_arithmetic_conversions(void) 
++{
++  float local_f;
++  _Complex float local_cf;
++
++  /* Values of type "float" are implicitly converted to "double" or
++     "long double" due to use in arithmetic with "double" or "long
++     double" operands.  */
++  local_f = f + 1.0;         /* { dg-warning "implicit" } */
++  local_f = f - d;           /* { dg-warning "implicit" } */
++  local_f = 1.0f * 1.0;      /* { dg-warning "implicit" } */
++  local_f = 1.0f / d;        /* { dg-warning "implicit" } */
++
++  local_cf = cf + 1.0;       /* { dg-warning "implicit" } */
++  local_cf = cf - d;         /* { dg-warning "implicit" } */
++  local_cf = cf + 1.0 * ID;  /* { dg-warning "implicit" } */
++  local_cf = cf - cd;        /* { dg-warning "implicit" } */
++  
++  local_f = i ? f : d;       /* { dg-warning "implicit" } */
++  i = f == d;                /* { dg-warning "implicit" } */
++  i = d != f;                /* { dg-warning "implicit" } */
++}
++
++void 
++default_argument_promotion (void) 
++{
++  /* Because there is no prototype, "f" is promoted to "double".  */
++  unprototyped_fn (f); /* { dg-warning "implicit" } */
++  undeclared_fn (f);   /* { dg-warning "implicit" } */
++  /* Because "f" is part of the variable argument list, it is promoted
++     to "double".  */
++  varargs_fn (1, f);   /* { dg-warning "implicit" } */
++}
++
++/* There is no warning when an explicit cast is used to perform the
++   conversion.  */
++
++void
++casts (void) 
++{
++  float local_f;
++  _Complex float local_cf;
++
++  local_f = (double)f + 1.0;                 /* { dg-bogus "implicit" } */
++  local_f = (double)f - d;                   /* { dg-bogus "implicit" } */
++  local_f = (double)1.0f + 1.0;              /* { dg-bogus "implicit" } */
++  local_f = (double)1.0f - d;                /* { dg-bogus "implicit" } */
++
++  local_cf = (_Complex double)cf + 1.0;      /* { dg-bogus "implicit" } */
++  local_cf = (_Complex double)cf - d;        /* { dg-bogus "implicit" } */
++  local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */
++  local_cf = (_Complex double)cf - cd;       /* { dg-bogus "implicit" } */
++
++  local_f = i ? (double)f : d;               /* { dg-bogus "implicit" } */
++  i = (double)f == d;                        /* { dg-bogus "implicit" } */
++  i = d != (double)f;                        /* { dg-bogus "implicit" } */
++}
++
++/* There is no warning on conversions that occur in assignment (and
++   assignment-like) contexts.  */
++
++void 
++assignments (void)
++{
++  d = f;           /* { dg-bogus "implicit" } */
++  double_fn (f);   /* { dg-bogus "implicit" } */
++  d = float_fn (); /* { dg-bogus "implicit" } */
++}
++
++/* There is no warning in non-evaluated contexts.  */
++
++void
++non_evaluated (void)
++{
++  s = sizeof (f + 1.0);             /* { dg-bogus "implicit" } */
++  s = __alignof__ (f + 1.0);        /* { dg-bogus "implicit" } */
++  d = (__typeof__(f + 1.0))f;       /* { dg-bogus "implicit" } */
++  s = sizeof (i ? f : d);           /* { dg-bogus "implicit" } */
++  s = sizeof (unprototyped_fn (f)); /* { dg-bogus "implicit" } */
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch
new file mode 100644
index 0000000000..82a9e93e43
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch
@@ -0,0 +1,369 @@
+2010-09-09  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-08-25  Tejas Belagod  <tejas.belagod@arm.com>
+	* config/arm/iterators.md (VU, SE, V_widen_l): New.
+	(V_unpack, US): New.
+	* config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for
+	vmovl.
+	(vec_unpack<US>_lo_<mode>): Likewise.
+	(neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl.
+	(neon_vec_unpack<US>_lo_<mode>): Likewise.
+	(vec_widen_<US>mult_lo_<mode>): Expansion for vmull.
+	(vec_widen_<US>mult_hi_<mode>): Likewise.
+	(neon_vec_<US>mult_lo_<mode>"): Instruction pattern for vmull.
+	(neon_vec_<US>mult_hi_<mode>"): Likewise.
+	(neon_unpack<US>_<mode>): Widening move intermediate step for
+	vectorizing without -mvectorize-with-neon-quad.
+	(neon_vec_<US>mult_<mode>): Widening multiply intermediate step
+	for vectorizing without -mvectorize-with-neon-quad.
+	* config/arm/predicates.md (vect_par_constant_high): Check for
+	high-half lanes of a vector.
+	(vect_par_constant_low): Check for low-half lanes of a vector.
+
+	2010-08-25  Tejas Belagod  <tejas.belagod@arm.com>
+	* lib/target-supports.exp (check_effective_target_vect_unpack):
+	Set vect_unpack supported flag to true for neon.
+
+ 2010-09-07  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from gcc-patches:
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-09-01 13:29:58 +0000
++++ new/gcc/config/arm/arm.md	2010-09-09 14:11:34 +0000
+@@ -868,6 +868,9 @@
+ (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
+ (define_code_attr optab [(ltu "ltu") (geu "geu")])
+ 
++;; Assembler mnemonics for signedness of widening operations.
++(define_code_attr US [(sign_extend "s") (zero_extend "u")])
++
+ (define_insn "*addsi3_carryin_<optab>"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2010-08-23 14:29:45 +0000
++++ new/gcc/config/arm/neon.md	2010-09-09 14:11:34 +0000
+@@ -235,6 +235,9 @@
+ ;; Modes with 32-bit elements only.
+ (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
+ 
++;; Modes with 8-bit, 16-bit and 32-bit elements.
++(define_mode_iterator VU [V16QI V8HI V4SI])
++ 
+ ;; (Opposite) mode to convert to/from for above conversions.
+ (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
+ 			   (V4SI "V4SF") (V4SF "V4SI")])
+@@ -388,6 +391,9 @@
+ ;; Same, without unsigned variants (for use with *SFmode pattern).
+ (define_code_iterator vqhs_ops [plus smin smax])
+ 
++;; A list of widening operators
++(define_code_iterator SE [sign_extend zero_extend])
++
+ ;; Assembler mnemonics for above codes.
+ (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
+ 			    (umin "vmin") (umax "vmax")])
+@@ -443,6 +449,12 @@
+                                  (V2SF "2") (V4SF "4")
+                                  (DI "1")   (V2DI "2")])
+ 
++;; Same as V_widen, but lower-case.
++(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
++
++;; Widen. Result is half the number of elements, but widened to double-width.
++(define_mode_attr V_unpack   [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
++
+ (define_insn "*neon_mov<mode>"
+   [(set (match_operand:VD 0 "nonimmediate_operand"
+ 	  "=w,Uv,w, w,  ?r,?w,?r,?r, ?Us")
+@@ -5540,3 +5552,205 @@
+   emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
+   DONE;
+ })
++
++(define_insn "neon_vec_unpack<US>_lo_<mode>"
++  [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
++        (SE:<V_unpack> (vec_select:<V_HALF>
++			  (match_operand:VU 1 "register_operand" "w")
++			  (match_operand:VU 2 "vect_par_constant_low" ""))))]
++  "TARGET_NEON"
++  "vmovl.<US><V_sz_elem> %q0, %e1"
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_insn "neon_vec_unpack<US>_hi_<mode>"
++  [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
++        (SE:<V_unpack> (vec_select:<V_HALF>
++			  (match_operand:VU 1 "register_operand" "w")
++			  (match_operand:VU 2 "vect_par_constant_high" ""))))]
++  "TARGET_NEON"
++  "vmovl.<US><V_sz_elem> %q0, %f1"
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_expand "vec_unpack<US>_hi_<mode>"
++  [(match_operand:<V_unpack> 0 "register_operand" "")
++   (SE:<V_unpack> (match_operand:VU 1 "register_operand"))]
++ "TARGET_NEON"
++  {
++   rtvec v = rtvec_alloc (<V_mode_nunits>/2)  ;
++   rtx t1;
++   int i;
++   for (i = 0; i < (<V_mode_nunits>/2); i++)
++     RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
++  
++   t1 = gen_rtx_PARALLEL (<MODE>mode, v);
++   emit_insn (gen_neon_vec_unpack<US>_hi_<mode> (operands[0], 
++                                                 operands[1], 
++					         t1));
++   DONE;
++  }
++)
++
++(define_expand "vec_unpack<US>_lo_<mode>"
++  [(match_operand:<V_unpack> 0 "register_operand" "")
++   (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))]
++ "TARGET_NEON"
++  {
++   rtvec v = rtvec_alloc (<V_mode_nunits>/2)  ;
++   rtx t1;
++   int i;
++   for (i = 0; i < (<V_mode_nunits>/2) ; i++)
++     RTVEC_ELT (v, i) = GEN_INT (i);
++   t1 = gen_rtx_PARALLEL (<MODE>mode, v);
++   emit_insn (gen_neon_vec_unpack<US>_lo_<mode> (operands[0], 
++                                                 operands[1], 
++				   	         t1));
++   DONE;
++  }
++)
++
++(define_insn "neon_vec_<US>mult_lo_<mode>"
++ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
++       (mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
++			   (match_operand:VU 1 "register_operand" "w") 
++                           (match_operand:VU 2 "vect_par_constant_low" "")))
++ 		        (SE:<V_unpack> (vec_select:<V_HALF>
++                           (match_operand:VU 3 "register_operand" "w") 
++                           (match_dup 2)))))]
++  "TARGET_NEON"
++  "vmull.<US><V_sz_elem> %q0, %e1, %e3"
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_expand "vec_widen_<US>mult_lo_<mode>"
++  [(match_operand:<V_unpack> 0 "register_operand" "")
++   (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
++   (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))]
++ "TARGET_NEON"
++ {
++   rtvec v = rtvec_alloc (<V_mode_nunits>/2)  ;
++   rtx t1;
++   int i;
++   for (i = 0; i < (<V_mode_nunits>/2) ; i++)
++     RTVEC_ELT (v, i) = GEN_INT (i);
++   t1 = gen_rtx_PARALLEL (<MODE>mode, v);
++
++   emit_insn (gen_neon_vec_<US>mult_lo_<mode> (operands[0],
++ 					       operands[1],
++					       t1,
++					       operands[2]));
++   DONE;
++ }
++)
++
++(define_insn "neon_vec_<US>mult_hi_<mode>"
++ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
++      (mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
++			    (match_operand:VU 1 "register_operand" "w") 
++			    (match_operand:VU 2 "vect_par_constant_high" "")))
++		       (SE:<V_unpack> (vec_select:<V_HALF>
++			    (match_operand:VU 3 "register_operand" "w") 
++			    (match_dup 2)))))]
++  "TARGET_NEON"
++  "vmull.<US><V_sz_elem> %q0, %f1, %f3"
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_expand "vec_widen_<US>mult_hi_<mode>"
++  [(match_operand:<V_unpack> 0 "register_operand" "")
++   (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
++   (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))]
++ "TARGET_NEON"
++ {
++   rtvec v = rtvec_alloc (<V_mode_nunits>/2)  ;
++   rtx t1;
++   int i;
++   for (i = 0; i < (<V_mode_nunits>/2) ; i++)
++     RTVEC_ELT (v, i) = GEN_INT (<V_mode_nunits>/2 + i);
++   t1 = gen_rtx_PARALLEL (<MODE>mode, v);
++
++   emit_insn (gen_neon_vec_<US>mult_hi_<mode> (operands[0],
++ 					       operands[1],
++					       t1,
++					       operands[2]));
++   DONE;
++
++ }
++)
++
++;; Vectorize for non-neon-quad case
++(define_insn "neon_unpack<US>_<mode>"
++ [(set (match_operand:<V_widen> 0 "register_operand" "=w")
++       (SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))]
++ "TARGET_NEON"
++ "vmovl.<US><V_sz_elem> %q0, %1"
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_expand "vec_unpack<US>_lo_<mode>"
++ [(match_operand:<V_double_width> 0 "register_operand" "")
++  (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))]
++ "TARGET_NEON"
++{
++  rtx tmpreg = gen_reg_rtx (<V_widen>mode);
++  emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1]));
++  emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
++
++  DONE;
++}
++)
++
++(define_expand "vec_unpack<US>_hi_<mode>"
++ [(match_operand:<V_double_width> 0 "register_operand" "")
++  (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))]
++ "TARGET_NEON"
++{
++  rtx tmpreg = gen_reg_rtx (<V_widen>mode);
++  emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1]));
++  emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
++
++  DONE;
++}
++)
++
++(define_insn "neon_vec_<US>mult_<mode>"
++ [(set (match_operand:<V_widen> 0 "register_operand" "=w")
++       (mult:<V_widen> (SE:<V_widen> 
++		 	   (match_operand:VDI 1 "register_operand" "w"))
++ 		       (SE:<V_widen> 
++			   (match_operand:VDI 2 "register_operand" "w"))))]
++  "TARGET_NEON"
++  "vmull.<US><V_sz_elem> %q0, %1, %2"
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_expand "vec_widen_<US>mult_hi_<mode>"
++  [(match_operand:<V_double_width> 0 "register_operand" "")
++   (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
++   (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))]
++ "TARGET_NEON"
++ {
++   rtx tmpreg = gen_reg_rtx (<V_widen>mode);
++   emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2]));
++   emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
++ 					    
++   DONE;
++
++ }
++)
++
++(define_expand "vec_widen_<US>mult_lo_<mode>"
++  [(match_operand:<V_double_width> 0 "register_operand" "")
++   (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
++   (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))]
++ "TARGET_NEON"
++ {
++   rtx tmpreg = gen_reg_rtx (<V_widen>mode);
++   emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2]));
++   emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
++ 					    
++   DONE;
++
++ }
++)
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-08-31 10:00:27 +0000
++++ new/gcc/config/arm/predicates.md	2010-09-09 14:11:34 +0000
+@@ -573,3 +573,61 @@
+ 		(and (match_test "TARGET_32BIT")
+ 		     (match_operand 0 "arm_di_operand"))))
+ 
++;; Predicates for parallel expanders based on mode.
++(define_special_predicate "vect_par_constant_high" 
++  (match_code "parallel")
++{
++  HOST_WIDE_INT count = XVECLEN (op, 0);
++  int i;
++  int base = GET_MODE_NUNITS (mode);
++
++  if ((count < 1)
++      || (count != base/2))
++    return false;
++    
++  if (!VECTOR_MODE_P (mode))
++    return false;
++
++  for (i = 0; i < count; i++)
++   {
++     rtx elt = XVECEXP (op, 0, i);
++     int val;
++
++     if (GET_CODE (elt) != CONST_INT)
++       return false;
++
++     val = INTVAL (elt);
++     if (val != (base/2) + i)
++       return false;
++   }
++  return true; 
++})
++
++(define_special_predicate "vect_par_constant_low"
++  (match_code "parallel")
++{
++  HOST_WIDE_INT count = XVECLEN (op, 0);
++  int i;
++  int base = GET_MODE_NUNITS (mode);
++
++  if ((count < 1)
++      || (count != base/2))
++    return false;
++    
++  if (!VECTOR_MODE_P (mode))
++    return false;
++
++  for (i = 0; i < count; i++)
++   {
++     rtx elt = XVECEXP (op, 0, i);
++     int val;
++
++     if (GET_CODE (elt) != CONST_INT)
++       return false;
++
++     val = INTVAL (elt);
++     if (val != i)
++       return false;
++   } 
++  return true; 
++})
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2010-08-24 13:00:03 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2010-09-09 14:11:34 +0000
+@@ -2519,7 +2519,8 @@
+         if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
+              || [istarget i?86-*-*]
+              || [istarget x86_64-*-*] 
+-             || [istarget spu-*-*] } {
++             || [istarget spu-*-*]
++             || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
+             set et_vect_unpack_saved 1
+         }
+     }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch
new file mode 100644
index 0000000000..89c04a8949
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch
@@ -0,0 +1,1202 @@
+	2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	* config/arm/arm-protos.h (arm_expand_sync): New.
+	(arm_output_memory_barrier, arm_output_sync_insn): New.
+	(arm_sync_loop_insns): New.
+	* config/arm/arm.c (FL_ARCH7): New.
+	(FL_FOR_ARCH7): Include FL_ARCH7.
+	(arm_arch7): New.
+	(arm_print_operand): Support %C markup.
+	(arm_legitimize_sync_memory): New.
+	(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
+	(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
+	(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
+	(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
+	(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
+	(arm_process_output_sync_insn, arm_output_sync_insn): New.
+	(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
+	* config/arm/arm.h (struct arm_sync_generator): New.
+	(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
+	(TARGET_HAVE_MEMORY_BARRIER): New.
+	(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
+	* config/arm/arm.md: Include sync.md.
+	(UNSPEC_MEMORY_BARRIER): New.
+	(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
+	(VUNSPEC_SYNC_OP):New.
+	(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
+	(sync_result, sync_memory, sync_required_value): New attributes.
+	(sync_new_value, sync_t1, sync_t2): Likewise.
+	(sync_release_barrier, sync_op): Likewise.
+	(length): Add logic to length attribute defintion to call
+	arm_sync_loop_insns when appropriate.
+	* config/arm/sync.md: New file.
+
+2010-09-09  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+
+ 	2010-08-25  Tejas Belagod  <tejas.belagod@arm.com>
+ 	* config/arm/iterators.md (VU, SE, V_widen_l): New.
+ 	(V_unpack, US): New.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2010-08-24 13:15:54 +0000
++++ new/gcc/config/arm/arm-protos.h	2010-09-09 15:03:00 +0000
+@@ -148,6 +148,11 @@
+ extern void arm_set_return_address (rtx, rtx);
+ extern int arm_eliminable_register (rtx);
+ extern const char *arm_output_shift(rtx *, int);
++extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *,
++ 			     rtx, rtx, rtx, rtx);
++extern const char *arm_output_memory_barrier (rtx *);
++extern const char *arm_output_sync_insn (rtx, rtx *);
++extern unsigned int arm_sync_loop_insns (rtx , rtx *);
+ 
+ extern bool arm_output_addr_const_extra (FILE *, rtx);
+ 
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-09-01 13:29:58 +0000
++++ new/gcc/config/arm/arm.c	2010-09-09 15:03:00 +0000
+@@ -605,6 +605,7 @@
+ #define FL_NEON       (1 << 20)       /* Neon instructions.  */
+ #define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
+ 					 architecture.  */
++#define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
+ 
+ #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+ 
+@@ -625,7 +626,7 @@
+ #define FL_FOR_ARCH6ZK	FL_FOR_ARCH6K
+ #define FL_FOR_ARCH6T2	(FL_FOR_ARCH6 | FL_THUMB2)
+ #define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
+-#define FL_FOR_ARCH7	(FL_FOR_ARCH6T2 &~ FL_NOTM)
++#define FL_FOR_ARCH7	((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
+ #define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+ #define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_DIV)
+ #define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_DIV)
+@@ -663,6 +664,9 @@
+ /* Nonzero if this chip supports the ARM 6K extensions.  */
+ int arm_arch6k = 0;
+ 
++/* Nonzero if this chip supports the ARM 7 extensions.  */
++int arm_arch7 = 0;
++
+ /* Nonzero if instructions not present in the 'M' profile can be used.  */
+ int arm_arch_notm = 0;
+ 
+@@ -1634,6 +1638,7 @@
+   arm_arch6 = (insn_flags & FL_ARCH6) != 0;
+   arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
+   arm_arch_notm = (insn_flags & FL_NOTM) != 0;
++  arm_arch7 = (insn_flags & FL_ARCH7) != 0;
+   arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
+   arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
+   arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
+@@ -16561,6 +16566,17 @@
+       }
+       return;
+ 
++    case 'C':
++      {
++	rtx addr;
++
++	gcc_assert (GET_CODE (x) == MEM);
++	addr = XEXP (x, 0);
++	gcc_assert (GET_CODE (addr) == REG);
++	asm_fprintf (stream, "[%r]", REGNO (addr));
++      }
++      return;
++
+     /* Translate an S register number into a D register number and element index.  */
+     case 'y':
+       {
+@@ -22763,4 +22779,372 @@
+ 						      is_packed);
+ }
+ 
++/* Legitimize a memory reference for sync primitive implemented using
++   ldrex / strex.  We currently force the form of the reference to be
++   indirect without offset.  We do not yet support the indirect offset
++   addressing supported by some ARM targets for these
++   instructions.  */
++static rtx
++arm_legitimize_sync_memory (rtx memory)
++{
++  rtx addr = force_reg (Pmode, XEXP (memory, 0));
++  rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr);
++
++  set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER);
++  MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory);
++  return legitimate_memory;
++}
++
++/* An instruction emitter. */
++typedef void (* emit_f) (int label, const char *, rtx *);
++
++/* An instruction emitter that emits via the conventional
++   output_asm_insn.  */
++static void
++arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands)
++{
++  output_asm_insn (pattern, operands);
++}
++
++/* Count the number of emitted synchronization instructions.  */
++static unsigned arm_insn_count;
++
++/* An emitter that counts emitted instructions but does not actually
++   emit instruction into the the instruction stream.  */
++static void
++arm_count (int label,
++	   const char *pattern ATTRIBUTE_UNUSED,
++	   rtx *operands ATTRIBUTE_UNUSED)
++{
++  if (! label)
++    ++ arm_insn_count;
++}
++
++/* Construct a pattern using conventional output formatting and feed
++   it to output_asm_insn.  Provides a mechanism to construct the
++   output pattern on the fly.  Note the hard limit on the pattern
++   buffer size.  */
++static void
++arm_output_asm_insn (emit_f emit, int label, rtx *operands,
++		     const char *pattern, ...)
++{
++  va_list ap;
++  char buffer[256];
++
++  va_start (ap, pattern);
++  vsprintf (buffer, pattern, ap);
++  va_end (ap);
++  emit (label, buffer, operands);
++}
++
++/* Emit the memory barrier instruction, if any, provided by this
++   target to a specified emitter.  */
++static void
++arm_process_output_memory_barrier (emit_f emit, rtx *operands)
++{
++  if (TARGET_HAVE_DMB)
++    {
++      /* Note we issue a system level barrier. We should consider
++         issuing a inner shareabilty zone barrier here instead, ie.
++         "DMB ISH".  */
++      emit (0, "dmb\tsy", operands);
++      return;
++    }
++
++  if (TARGET_HAVE_DMB_MCR)
++    {
++      emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands);
++      return;
++    }
++
++  gcc_unreachable ();
++}
++
++/* Emit the memory barrier instruction, if any, provided by this
++   target.  */
++const char *
++arm_output_memory_barrier (rtx *operands)
++{
++  arm_process_output_memory_barrier (arm_emit, operands);
++  return "";
++}
++
++/* Helper to figure out the instruction suffix required on ldrex/strex
++   for operations on an object of the specified mode.  */
++static const char *
++arm_ldrex_suffix (enum machine_mode mode)
++{
++  switch (mode)
++    {
++    case QImode: return "b";
++    case HImode: return "h";
++    case SImode: return "";
++    case DImode: return "d";
++    default:
++      gcc_unreachable ();
++    }
++  return "";
++}
++
++/* Emit an ldrex{b,h,d, } instruction appropriate for the specified
++   mode.  */
++static void
++arm_output_ldrex (emit_f emit,
++		  enum machine_mode mode,
++		  rtx target,
++		  rtx memory)
++{
++  const char *suffix = arm_ldrex_suffix (mode);
++  rtx operands[2];
++
++  operands[0] = target;
++  operands[1] = memory;
++  arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
++}
++
++/* Emit a strex{b,h,d, } instruction appropriate for the specified
++   mode.  */
++static void
++arm_output_strex (emit_f emit,
++		  enum machine_mode mode,
++		  const char *cc,
++		  rtx result,
++		  rtx value,
++		  rtx memory)
++{
++  const char *suffix = arm_ldrex_suffix (mode);
++  rtx operands[3];
++
++  operands[0] = result;
++  operands[1] = value;
++  operands[2] = memory;
++  arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix,
++		       cc);
++}
++
++/* Helper to emit a two operand instruction.  */
++static void
++arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s)
++{
++  rtx operands[2];
++
++  operands[0] = d;
++  operands[1] = s;
++  arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic);
++}
++
++/* Helper to emit a three operand instruction.  */
++static void
++arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b)
++{
++  rtx operands[3];
++
++  operands[0] = d;
++  operands[1] = a;
++  operands[2] = b;
++  arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic);
++}
++
++/* Emit a load store exclusive synchronization loop.
++
++   do
++     old_value = [mem]
++     if old_value != required_value
++       break;
++     t1 = sync_op (old_value, new_value)
++     [mem] = t1, t2 = [0|1]
++   while ! t2
++
++   Note:
++     t1 == t2 is not permitted
++     t1 == old_value is permitted
++
++   required_value:
++
++   RTX register or const_int representing the required old_value for
++   the modify to continue, if NULL no comparsion is performed.  */
++static void
++arm_output_sync_loop (emit_f emit,
++		      enum machine_mode mode,
++		      rtx old_value,
++		      rtx memory,
++		      rtx required_value,
++		      rtx new_value,
++		      rtx t1,
++		      rtx t2,
++		      enum attr_sync_op sync_op,
++		      int early_barrier_required)
++{
++  rtx operands[1];
++
++  gcc_assert (t1 != t2);
++
++  if (early_barrier_required)
++    arm_process_output_memory_barrier (emit, NULL);
++
++  arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX);
++
++  arm_output_ldrex (emit, mode, old_value, memory);
++
++  if (required_value)
++    {
++      rtx operands[2];
++
++      operands[0] = old_value;
++      operands[1] = required_value;
++      arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1");
++      arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX);
++    }
++
++  switch (sync_op)
++    {
++    case SYNC_OP_ADD:
++      arm_output_op3 (emit, "add", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_SUB:
++      arm_output_op3 (emit, "sub", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_IOR:
++      arm_output_op3 (emit, "orr", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_XOR:
++      arm_output_op3 (emit, "eor", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_AND:
++      arm_output_op3 (emit,"and", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_NAND:
++      arm_output_op3 (emit, "and", t1, old_value, new_value);
++      arm_output_op2 (emit, "mvn", t1, t1);
++      break;
++
++    case SYNC_OP_NONE:
++      t1 = new_value;
++      break;
++    }
++
++  arm_output_strex (emit, mode, "", t2, t1, memory);
++  operands[0] = t2;
++  arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
++  arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX);
++
++  arm_process_output_memory_barrier (emit, NULL);
++  arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
++}
++
++static rtx
++arm_get_sync_operand (rtx *operands, int index, rtx default_value)
++{
++  if (index > 0)
++    default_value = operands[index - 1];
++
++  return default_value;
++}
++
++#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \
++  arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT);
++
++/* Extract the operands for a synchroniztion instruction from the
++   instructions attributes and emit the instruction.  */
++static void
++arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands)
++{
++  rtx result, memory, required_value, new_value, t1, t2;
++  int early_barrier;
++  enum machine_mode mode;
++  enum attr_sync_op sync_op;
++
++  result = FETCH_SYNC_OPERAND(result, 0);
++  memory = FETCH_SYNC_OPERAND(memory, 0);
++  required_value = FETCH_SYNC_OPERAND(required_value, 0);
++  new_value = FETCH_SYNC_OPERAND(new_value, 0);
++  t1 = FETCH_SYNC_OPERAND(t1, 0);
++  t2 = FETCH_SYNC_OPERAND(t2, 0);
++  early_barrier =
++    get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES;
++  sync_op = get_attr_sync_op (insn);
++  mode = GET_MODE (memory);
++
++  arm_output_sync_loop (emit, mode, result, memory, required_value,
++			new_value, t1, t2, sync_op, early_barrier);
++}
++
++/* Emit a synchronization instruction loop.  */
++const char *
++arm_output_sync_insn (rtx insn, rtx *operands)
++{
++  arm_process_output_sync_insn (arm_emit, insn, operands);
++  return "";
++}
++
++/* Count the number of machine instruction that will be emitted for a
++   synchronization instruction.  Note that the emitter used does not
++   emit instructions, it just counts instructions being carefull not
++   to count labels.  */
++unsigned int
++arm_sync_loop_insns (rtx insn, rtx *operands)
++{
++  arm_insn_count = 0;
++  arm_process_output_sync_insn (arm_count, insn, operands);
++  return arm_insn_count;
++}
++
++/* Helper to call a target sync instruction generator, dealing with
++   the variation in operands required by the different generators.  */
++static rtx
++arm_call_generator (struct arm_sync_generator *generator, rtx old_value,
++  		    rtx memory, rtx required_value, rtx new_value)
++{
++  switch (generator->op)
++    {
++    case arm_sync_generator_omn:
++      gcc_assert (! required_value);
++      return generator->u.omn (old_value, memory, new_value);
++
++    case arm_sync_generator_omrn:
++      gcc_assert (required_value);
++      return generator->u.omrn (old_value, memory, required_value, new_value);
++    }
++
++  return NULL;
++}
++
++/* Expand a synchronization loop. The synchronization loop is expanded
++   as an opaque block of instructions in order to ensure that we do
++   not subsequently get extraneous memory accesses inserted within the
++   critical region. The exclusive access property of ldrex/strex is
++   only guaranteed in there are no intervening memory accesses. */
++void
++arm_expand_sync (enum machine_mode mode,
++		 struct arm_sync_generator *generator,
++		 rtx target, rtx memory, rtx required_value, rtx new_value)
++{
++  if (target == NULL)
++    target = gen_reg_rtx (mode);
++
++  memory = arm_legitimize_sync_memory (memory);
++  if (mode != SImode)
++    {
++      rtx load_temp = gen_reg_rtx (SImode);
++
++      if (required_value)
++	required_value = convert_modes (SImode, mode, required_value, true);
++
++      new_value = convert_modes (SImode, mode, new_value, true);
++      emit_insn (arm_call_generator (generator, load_temp, memory,
++				     required_value, new_value));
++      emit_move_insn (target, gen_lowpart (mode, load_temp));
++    }
++  else
++    {
++      emit_insn (arm_call_generator (generator, target, memory, required_value,
++				     new_value));
++    }
++}
++
+ #include "gt-arm.h"
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-09-01 13:29:58 +0000
++++ new/gcc/config/arm/arm.h	2010-09-09 15:03:00 +0000
+@@ -128,6 +128,24 @@
+ /* The processor for which instructions should be scheduled.  */
+ extern enum processor_type arm_tune;
+ 
++enum arm_sync_generator_tag
++  {
++    arm_sync_generator_omn,
++    arm_sync_generator_omrn
++  };
++
++/* Wrapper to pass around a polymorphic pointer to a sync instruction
++   generator and.  */
++struct arm_sync_generator
++{
++  enum arm_sync_generator_tag op;
++  union
++  {
++    rtx (* omn) (rtx, rtx, rtx);
++    rtx (* omrn) (rtx, rtx, rtx, rtx);
++  } u;
++};
++
+ typedef enum arm_cond_code
+ {
+   ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
+@@ -272,6 +290,20 @@
+    for Thumb-2.  */
+ #define TARGET_UNIFIED_ASM TARGET_THUMB2
+ 
++/* Nonzero if this chip provides the DMB instruction.  */
++#define TARGET_HAVE_DMB		(arm_arch7)
++
++/* Nonzero if this chip implements a memory barrier via CP15.  */
++#define TARGET_HAVE_DMB_MCR	(arm_arch6k && ! TARGET_HAVE_DMB)
++
++/* Nonzero if this chip implements a memory barrier instruction.  */
++#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
++
++/* Nonzero if this chip supports ldrex and strex */
++#define TARGET_HAVE_LDREX	((arm_arch6 && TARGET_ARM) || arm_arch7)
++
++/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}.  */
++#define TARGET_HAVE_LDREXBHD	((arm_arch6k && TARGET_ARM) || arm_arch7)
+ 
+ /* True iff the full BPABI is being used.  If TARGET_BPABI is true,
+    then TARGET_AAPCS_BASED must be true -- but the converse does not
+@@ -405,6 +437,12 @@
+ /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
+ extern int arm_arch6;
+ 
++/* Nonzero if this chip supports the ARM Architecture 6k extensions.  */
++extern int arm_arch6k;
++
++/* Nonzero if this chip supports the ARM Architecture 7 extensions.  */
++extern int arm_arch7;
++
+ /* Nonzero if instructions not present in the 'M' profile can be used.  */
+ extern int arm_arch_notm;
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-09-09 14:11:34 +0000
++++ new/gcc/config/arm/arm.md	2010-09-09 15:03:00 +0000
+@@ -103,6 +103,7 @@
+    (UNSPEC_RBIT 26)       ; rbit operation.
+    (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
+                              ; another symbolic address.
++   (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
+   ]
+ )
+ 
+@@ -139,6 +140,11 @@
+    (VUNSPEC_ALIGN32  16) ; Used to force 32-byte alignment.
+    (VUNSPEC_EH_RETURN 20); Use to override the return address for exception
+ 			 ; handling.
++   (VUNSPEC_SYNC_COMPARE_AND_SWAP 21)	; Represent an atomic compare swap.
++   (VUNSPEC_SYNC_LOCK             22)	; Represent a sync_lock_test_and_set.
++   (VUNSPEC_SYNC_OP               23)	; Represent a sync_<op>
++   (VUNSPEC_SYNC_NEW_OP           24)	; Represent a sync_new_<op>
++   (VUNSPEC_SYNC_OLD_OP           25)	; Represent a sync_old_<op>
+   ]
+ )
+ 
+@@ -163,8 +169,21 @@
+ (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
+   (const (symbol_ref "arm_fpu_attr")))
+ 
++(define_attr "sync_result"          "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_memory"          "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_required_value"  "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_new_value"       "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_t1"              "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_t2"              "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_release_barrier" "yes,no"           (const_string "yes"))
++(define_attr "sync_op"              "none,add,sub,ior,xor,and,nand"
++                                    (const_string "none"))
++
+ ; LENGTH of an instruction (in bytes)
+-(define_attr "length" "" (const_int 4))
++(define_attr "length" ""
++  (cond [(not (eq_attr "sync_memory" "none"))
++ 	   (symbol_ref "arm_sync_loop_insns (insn, operands) * 4")
++	] (const_int 4)))
+ 
+ ; POOL_RANGE is how far away from a constant pool entry that this insn
+ ; can be placed.  If the distance is zero, then this insn will never
+@@ -11530,4 +11549,5 @@
+ (include "thumb2.md")
+ ;; Neon patterns
+ (include "neon.md")
+-
++;; Synchronization Primitives
++(include "sync.md")
+
+=== added file 'gcc/config/arm/sync.md'
+--- old/gcc/config/arm/sync.md	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/sync.md	2010-09-09 15:03:00 +0000
+@@ -0,0 +1,594 @@
++;; Machine description for ARM processor synchronization primitives.
++;; Copyright (C) 2010 Free Software Foundation, Inc.
++;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com)
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.  */
++
++;; ARMV6 introduced ldrex and strex instruction. These instruction
++;; access SI width data. In order to implement synchronization
++;; primitives for the narrower QI and HI modes we insert appropriate
++;; AND/OR sequences into the synchronization loop to mask out the
++;; relevant component of an SI access.
++
++(define_expand "memory_barrier"
++  [(set (match_dup 0)
++	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
++  "TARGET_HAVE_MEMORY_BARRIER"
++{
++  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
++  MEM_VOLATILE_P (operands[0]) = 1;
++})
++
++(define_expand "sync_compare_and_swapsi"
++  [(set (match_operand:SI 0 "s_register_operand")
++        (unspec_volatile:SI [(match_operand:SI 1 "memory_operand")
++			     (match_operand:SI 2 "s_register_operand")
++			     (match_operand:SI 3 "s_register_operand")]
++			     VUNSPEC_SYNC_COMPARE_AND_SWAP))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omrn;
++    generator.u.omrn = gen_arm_sync_compare_and_swapsi;
++    arm_expand_sync (SImode, &generator, operands[0], operands[1], operands[2],
++                     operands[3]);
++    DONE;
++  })
++
++(define_mode_iterator NARROW [QI HI])
++
++(define_expand "sync_compare_and_swap<mode>"
++  [(set (match_operand:NARROW 0 "s_register_operand")
++        (unspec_volatile:NARROW [(match_operand:NARROW 1 "memory_operand")
++			     (match_operand:NARROW 2 "s_register_operand")
++			     (match_operand:NARROW 3 "s_register_operand")]
++			     VUNSPEC_SYNC_COMPARE_AND_SWAP))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omrn;
++    generator.u.omrn = gen_arm_sync_compare_and_swap<mode>;
++    arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
++                     operands[2], operands[3]);
++    DONE;
++  })
++
++(define_expand "sync_lock_test_and_setsi"
++  [(match_operand:SI 0 "s_register_operand")
++   (match_operand:SI 1 "memory_operand")
++   (match_operand:SI 2 "s_register_operand")]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_lock_test_and_setsi;
++    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
++                     operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_lock_test_and_set<mode>"
++  [(match_operand:NARROW 0 "s_register_operand")
++   (match_operand:NARROW 1 "memory_operand")
++   (match_operand:NARROW 2 "s_register_operand")]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_lock_test_and_set<mode>;
++    arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], NULL,
++                     operands[2]);
++    DONE;
++  })
++
++(define_code_iterator syncop [plus minus ior xor and])
++
++(define_code_attr sync_optab [(ior "ior")
++			      (xor "xor")
++			      (and "and")
++			      (plus "add")
++			      (minus "sub")])
++
++(define_expand "sync_<sync_optab>si"
++  [(match_operand:SI 0 "memory_operand")
++   (match_operand:SI 1 "s_register_operand")
++   (syncop:SI (match_dup 0) (match_dup 1))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_<sync_optab>si;
++    arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]);
++    DONE;
++  })
++
++(define_expand "sync_nandsi"
++  [(match_operand:SI 0 "memory_operand")
++   (match_operand:SI 1 "s_register_operand")
++   (not:SI (and:SI (match_dup 0) (match_dup 1)))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_nandsi;
++    arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]);
++    DONE;
++  })
++
++(define_expand "sync_<sync_optab><mode>"
++  [(match_operand:NARROW 0 "memory_operand")
++   (match_operand:NARROW 1 "s_register_operand")
++   (syncop:NARROW (match_dup 0) (match_dup 1))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_<sync_optab><mode>;
++    arm_expand_sync (<MODE>mode, &generator, NULL, operands[0], NULL,
++    		     operands[1]);
++    DONE;
++  })
++
++(define_expand "sync_nand<mode>"
++  [(match_operand:NARROW 0 "memory_operand")
++   (match_operand:NARROW 1 "s_register_operand")
++   (not:NARROW (and:NARROW (match_dup 0) (match_dup 1)))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_nand<mode>;
++    arm_expand_sync (<MODE>mode, &generator, NULL, operands[0], NULL,
++                     operands[1]);
++    DONE;
++  })
++
++(define_expand "sync_new_<sync_optab>si"
++  [(match_operand:SI 0 "s_register_operand")
++   (match_operand:SI 1 "memory_operand")
++   (match_operand:SI 2 "s_register_operand")
++   (syncop:SI (match_dup 1) (match_dup 2))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_<sync_optab>si;
++    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
++                     operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_new_nandsi"
++  [(match_operand:SI 0 "s_register_operand")
++   (match_operand:SI 1 "memory_operand")
++   (match_operand:SI 2 "s_register_operand")
++   (not:SI (and:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_nandsi;
++    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
++    		     operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_new_<sync_optab><mode>"
++  [(match_operand:NARROW 0 "s_register_operand")
++   (match_operand:NARROW 1 "memory_operand")
++   (match_operand:NARROW 2 "s_register_operand")
++   (syncop:NARROW (match_dup 1) (match_dup 2))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_<sync_optab><mode>;
++    arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
++    		     NULL, operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_new_nand<mode>"
++  [(match_operand:NARROW 0 "s_register_operand")
++   (match_operand:NARROW 1 "memory_operand")
++   (match_operand:NARROW 2 "s_register_operand")
++   (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_new_nand<mode>;
++    arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
++    		     NULL, operands[2]);
++    DONE;
++  });
++
++(define_expand "sync_old_<sync_optab>si"
++  [(match_operand:SI 0 "s_register_operand")
++   (match_operand:SI 1 "memory_operand")
++   (match_operand:SI 2 "s_register_operand")
++   (syncop:SI (match_dup 1) (match_dup 2))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_old_<sync_optab>si;
++    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
++                     operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_old_nandsi"
++  [(match_operand:SI 0 "s_register_operand")
++   (match_operand:SI 1 "memory_operand")
++   (match_operand:SI 2 "s_register_operand")
++   (not:SI (and:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_old_nandsi;
++    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
++                     operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_old_<sync_optab><mode>"
++  [(match_operand:NARROW 0 "s_register_operand")
++   (match_operand:NARROW 1 "memory_operand")
++   (match_operand:NARROW 2 "s_register_operand")
++   (syncop:NARROW (match_dup 1) (match_dup 2))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_old_<sync_optab><mode>;
++    arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
++    		     NULL, operands[2]);
++    DONE;
++  })
++
++(define_expand "sync_old_nand<mode>"
++  [(match_operand:NARROW 0 "s_register_operand")
++   (match_operand:NARROW 1 "memory_operand")
++   (match_operand:NARROW 2 "s_register_operand")
++   (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    struct arm_sync_generator generator;
++    generator.op = arm_sync_generator_omn;
++    generator.u.omn = gen_arm_sync_old_nand<mode>;
++    arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
++                     NULL, operands[2]);
++    DONE;
++  })
++
++(define_insn "arm_sync_compare_and_swapsi"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI
++	  [(match_operand:SI 1 "memory_operand" "+m")
++   	   (match_operand:SI 2 "s_register_operand" "r")
++	   (match_operand:SI 3 "s_register_operand" "r")]
++	  VUNSPEC_SYNC_COMPARE_AND_SWAP))
++   (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)]
++                                          VUNSPEC_SYNC_COMPARE_AND_SWAP))
++   (clobber:SI (match_scratch:SI 4 "=&r"))
++   (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
++                                                VUNSPEC_SYNC_COMPARE_AND_SWAP))
++   ]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_required_value"  "2")
++   (set_attr "sync_new_value"       "3")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "4")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_compare_and_swap<mode>"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (zero_extend:SI
++	  (unspec_volatile:NARROW
++	    [(match_operand:NARROW 1 "memory_operand" "+m")
++   	     (match_operand:SI 2 "s_register_operand" "r")
++	     (match_operand:SI 3 "s_register_operand" "r")]
++	    VUNSPEC_SYNC_COMPARE_AND_SWAP)))
++   (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)]
++                                          VUNSPEC_SYNC_COMPARE_AND_SWAP))
++   (clobber:SI (match_scratch:SI 4 "=&r"))
++   (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
++                                                VUNSPEC_SYNC_COMPARE_AND_SWAP))
++   ]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_required_value"  "2")
++   (set_attr "sync_new_value"       "3")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "4")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_lock_test_and_setsi"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (match_operand:SI 1 "memory_operand" "+m"))
++   (set (match_dup 1)
++        (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")]
++	                    VUNSPEC_SYNC_LOCK))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_release_barrier" "no")
++   (set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_lock_test_and_set<mode>"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m")))
++   (set (match_dup 1)
++        (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")]
++	                        VUNSPEC_SYNC_LOCK))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_release_barrier" "no")
++   (set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_new_<sync_optab>si"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(syncop:SI
++                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 2 "s_register_operand" "r"))
++	                    ]
++	                    VUNSPEC_SYNC_NEW_OP))
++   (set (match_dup 1)
++        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_NEW_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "sync_op"              "<sync_optab>")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_new_nandsi"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(not:SI (and:SI
++                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 2 "s_register_operand" "r")))
++	                    ]
++	                    VUNSPEC_SYNC_NEW_OP))
++   (set (match_dup 1)
++        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_NEW_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "sync_op"              "nand")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_new_<sync_optab><mode>"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(syncop:SI
++                               (zero_extend:SI
++			         (match_operand:NARROW 1 "memory_operand" "+m"))
++                               (match_operand:SI 2 "s_register_operand" "r"))
++	                    ]
++	                    VUNSPEC_SYNC_NEW_OP))
++   (set (match_dup 1)
++        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++	                        VUNSPEC_SYNC_NEW_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "sync_op"              "<sync_optab>")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_new_nand<mode>"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI
++	  [(not:SI
++	     (and:SI
++               (zero_extend:SI	  
++	         (match_operand:NARROW 1 "memory_operand" "+m"))
++               (match_operand:SI 2 "s_register_operand" "r")))
++	  ] VUNSPEC_SYNC_NEW_OP))
++   (set (match_dup 1)
++        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++	                        VUNSPEC_SYNC_NEW_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "sync_op"              "nand")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_old_<sync_optab>si"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(syncop:SI
++                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 2 "s_register_operand" "r"))
++	                    ]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (set (match_dup 1)
++        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))
++   (clobber (match_scratch:SI 4 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "3")
++   (set_attr "sync_t2"              "4")
++   (set_attr "sync_op"              "<sync_optab>")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_old_nandsi"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(not:SI (and:SI
++                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 2 "s_register_operand" "r")))
++	                    ]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (set (match_dup 1)
++        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))
++   (clobber (match_scratch:SI 4 "=&r"))]
++  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "3")
++   (set_attr "sync_t2"              "4")
++   (set_attr "sync_op"              "nand")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_old_<sync_optab><mode>"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(syncop:SI
++                               (zero_extend:SI
++			         (match_operand:NARROW 1 "memory_operand" "+m"))
++                               (match_operand:SI 2 "s_register_operand" "r"))
++	                    ]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (set (match_dup 1)
++        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))
++   (clobber (match_scratch:SI 4 "=&r"))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "3")
++   (set_attr "sync_t2"              "4")
++   (set_attr "sync_op"              "<sync_optab>")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_old_nand<mode>"
++  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SI [(not:SI (and:SI
++                               (zero_extend:SI
++			         (match_operand:NARROW 1 "memory_operand" "+m"))
++                               (match_operand:SI 2 "s_register_operand" "r")))
++	                    ]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (set (match_dup 1)
++        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))
++   (clobber (match_scratch:SI 4 "=&r"))]
++  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "3")
++   (set_attr "sync_t2"              "4")
++   (set_attr "sync_op"              "nand")
++   (set_attr "conds" "nocond")
++   (set_attr "predicable" "no")])
++
++(define_insn "*memory_barrier"
++  [(set (match_operand:BLK 0 "" "")
++	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
++  "TARGET_HAVE_MEMORY_BARRIER"
++  {
++    return arm_output_memory_barrier (operands);
++  }
++  [(set_attr "length" "4")
++   (set_attr "conds" "unconditional")
++   (set_attr "predicable" "no")])
++
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch
new file mode 100644
index 0000000000..d10cf34654
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch
@@ -0,0 +1,151 @@
+	2010-09-02  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	* config/arm/predicates.md (arm_sync_memory_operand): New.
+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate
+	to arm_sync_memory_operand and constraint to Q.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_lock_test_and_setsi): Likewise.
+	(arm_sync_lock_test_and_set<mode>): Likewise.
+	(arm_sync_new_<sync_optab>si): Likewise.
+	(arm_sync_new_nandsi): Likewise.
+	(arm_sync_new_<sync_optab><mode>): Likewise.
+	(arm_sync_new_nand<mode>): Likewise.
+	(arm_sync_old_<sync_optab>si): Likewise.
+	(arm_sync_old_nandsi): Likewise.
+	(arm_sync_old_<sync_optab><mode>): Likewise.
+	(arm_sync_old_nand<mode>): Likewise.
+
+2010-09-09  Andrew Stubbs  <ams@codesourcery.com>
+
+ 	Backport from mainline:
+ 
+ 	2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-09-09 14:11:34 +0000
++++ new/gcc/config/arm/predicates.md	2010-09-09 15:18:16 +0000
+@@ -573,6 +573,11 @@
+ 		(and (match_test "TARGET_32BIT")
+ 		     (match_operand 0 "arm_di_operand"))))
+ 
++;; True if the operand is memory reference suitable for a ldrex/strex.
++(define_predicate "arm_sync_memory_operand"
++  (and (match_operand 0 "memory_operand")
++       (match_code "reg" "0")))
++
+ ;; Predicates for parallel expanders based on mode.
+ (define_special_predicate "vect_par_constant_high" 
+   (match_code "parallel")
+
+=== modified file 'gcc/config/arm/sync.md'
+--- old/gcc/config/arm/sync.md	2010-09-09 15:03:00 +0000
++++ new/gcc/config/arm/sync.md	2010-09-09 15:18:16 +0000
+@@ -280,7 +280,7 @@
+ (define_insn "arm_sync_compare_and_swapsi"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI
+-	  [(match_operand:SI 1 "memory_operand" "+m")
++	  [(match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+    	   (match_operand:SI 2 "s_register_operand" "r")
+ 	   (match_operand:SI 3 "s_register_operand" "r")]
+ 	  VUNSPEC_SYNC_COMPARE_AND_SWAP))
+@@ -307,7 +307,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (zero_extend:SI
+ 	  (unspec_volatile:NARROW
+-	    [(match_operand:NARROW 1 "memory_operand" "+m")
++	    [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")
+    	     (match_operand:SI 2 "s_register_operand" "r")
+ 	     (match_operand:SI 3 "s_register_operand" "r")]
+ 	    VUNSPEC_SYNC_COMPARE_AND_SWAP)))
+@@ -332,7 +332,7 @@
+ 
+ (define_insn "arm_sync_lock_test_and_setsi"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (match_operand:SI 1 "memory_operand" "+m"))
++        (match_operand:SI 1 "arm_sync_memory_operand" "+Q"))
+    (set (match_dup 1)
+         (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")]
+ 	                    VUNSPEC_SYNC_LOCK))
+@@ -353,7 +353,7 @@
+ 
+ (define_insn "arm_sync_lock_test_and_set<mode>"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m")))
++        (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")))
+    (set (match_dup 1)
+         (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")]
+ 	                        VUNSPEC_SYNC_LOCK))
+@@ -375,7 +375,7 @@
+ (define_insn "arm_sync_new_<sync_optab>si"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(syncop:SI
+-                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+                                (match_operand:SI 2 "s_register_operand" "r"))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_NEW_OP))
+@@ -400,7 +400,7 @@
+ (define_insn "arm_sync_new_nandsi"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(not:SI (and:SI
+-                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+                                (match_operand:SI 2 "s_register_operand" "r")))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_NEW_OP))
+@@ -426,7 +426,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(syncop:SI
+                                (zero_extend:SI
+-			         (match_operand:NARROW 1 "memory_operand" "+m"))
++			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+                                (match_operand:SI 2 "s_register_operand" "r"))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_NEW_OP))
+@@ -454,7 +454,7 @@
+ 	  [(not:SI
+ 	     (and:SI
+                (zero_extend:SI	  
+-	         (match_operand:NARROW 1 "memory_operand" "+m"))
++	         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+                (match_operand:SI 2 "s_register_operand" "r")))
+ 	  ] VUNSPEC_SYNC_NEW_OP))
+    (set (match_dup 1)
+@@ -478,7 +478,7 @@
+ (define_insn "arm_sync_old_<sync_optab>si"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(syncop:SI
+-                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+                                (match_operand:SI 2 "s_register_operand" "r"))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_OLD_OP))
+@@ -504,7 +504,7 @@
+ (define_insn "arm_sync_old_nandsi"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(not:SI (and:SI
+-                               (match_operand:SI 1 "memory_operand" "+m")
++                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+                                (match_operand:SI 2 "s_register_operand" "r")))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_OLD_OP))
+@@ -531,7 +531,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(syncop:SI
+                                (zero_extend:SI
+-			         (match_operand:NARROW 1 "memory_operand" "+m"))
++			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+                                (match_operand:SI 2 "s_register_operand" "r"))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_OLD_OP))
+@@ -558,7 +558,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(not:SI (and:SI
+                                (zero_extend:SI
+-			         (match_operand:NARROW 1 "memory_operand" "+m"))
++			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+                                (match_operand:SI 2 "s_register_operand" "r")))
+ 	                    ]
+ 	                    VUNSPEC_SYNC_OLD_OP))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch
new file mode 100644
index 0000000000..f603fcadba
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch
@@ -0,0 +1,191 @@
+2010-09-13  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2010-09-13  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	* config/arm/arm.md: (define_attr "conds"): Update comment.
+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change 
+	  conds attribute to clob.
+	  (arm_sync_compare_and_swapsi): Likewise.
+	  (arm_sync_compare_and_swap<mode>): Likewise.
+	  (arm_sync_lock_test_and_setsi): Likewise.
+	  (arm_sync_lock_test_and_set<mode>): Likewise.
+	  (arm_sync_new_<sync_optab>si): Likewise.
+	  (arm_sync_new_nandsi): Likewise.
+	  (arm_sync_new_<sync_optab><mode>): Likewise.
+	  (arm_sync_new_nand<mode>): Likewise.
+	  (arm_sync_old_<sync_optab>si): Likewise.
+	  (arm_sync_old_nandsi): Likewise.
+	  (arm_sync_old_<sync_optab><mode>): Likewise.
+	  (arm_sync_old_nand<mode>): Likewise.
+
+	2010-09-13  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	* gcc.target/arm/sync-1.c: New.
+
+ 2010-09-10  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-09-09 15:03:00 +0000
++++ new/gcc/config/arm/arm.md	2010-09-13 15:39:11 +0000
+@@ -352,10 +352,11 @@
+ ; CLOB means that the condition codes are altered in an undefined manner, if
+ ;   they are altered at all
+ ;
+-; UNCONDITIONAL means the instions can not be conditionally executed.
++; UNCONDITIONAL means the instruction can not be conditionally executed and
++;   that the instruction does not use or alter the condition codes.
+ ;
+-; NOCOND means that the condition codes are neither altered nor affect the
+-;   output of this insn
++; NOCOND means that the instruction does not use or alter the condition
++;   codes but can be converted into a conditionally exectuted instruction.
+ 
+ (define_attr "conds" "use,set,clob,unconditional,nocond"
+ 	(if_then_else (eq_attr "type" "call")
+
+=== modified file 'gcc/config/arm/sync.md'
+--- old/gcc/config/arm/sync.md	2010-09-09 15:18:16 +0000
++++ new/gcc/config/arm/sync.md	2010-09-13 15:39:11 +0000
+@@ -300,7 +300,7 @@
+    (set_attr "sync_new_value"       "3")
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "4")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_compare_and_swap<mode>"
+@@ -327,7 +327,7 @@
+    (set_attr "sync_new_value"       "3")
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "4")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_lock_test_and_setsi"
+@@ -348,7 +348,7 @@
+    (set_attr "sync_new_value"       "2")
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "3")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_lock_test_and_set<mode>"
+@@ -369,7 +369,7 @@
+    (set_attr "sync_new_value"       "2")
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "3")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_new_<sync_optab>si"
+@@ -394,7 +394,7 @@
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "3")
+    (set_attr "sync_op"              "<sync_optab>")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_new_nandsi"
+@@ -419,7 +419,7 @@
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "3")
+    (set_attr "sync_op"              "nand")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_new_<sync_optab><mode>"
+@@ -445,7 +445,7 @@
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "3")
+    (set_attr "sync_op"              "<sync_optab>")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_new_nand<mode>"
+@@ -472,7 +472,7 @@
+    (set_attr "sync_t1"              "0")
+    (set_attr "sync_t2"              "3")
+    (set_attr "sync_op"              "nand")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_old_<sync_optab>si"
+@@ -498,7 +498,7 @@
+    (set_attr "sync_t1"              "3")
+    (set_attr "sync_t2"              "4")
+    (set_attr "sync_op"              "<sync_optab>")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_old_nandsi"
+@@ -524,7 +524,7 @@
+    (set_attr "sync_t1"              "3")
+    (set_attr "sync_t2"              "4")
+    (set_attr "sync_op"              "nand")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" 		    "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_old_<sync_optab><mode>"
+@@ -551,7 +551,7 @@
+    (set_attr "sync_t1"              "3")
+    (set_attr "sync_t2"              "4")
+    (set_attr "sync_op"              "<sync_optab>")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds" 		    "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_old_nand<mode>"
+@@ -578,7 +578,7 @@
+    (set_attr "sync_t1"              "3")
+    (set_attr "sync_t2"              "4")
+    (set_attr "sync_op"              "nand")
+-   (set_attr "conds" "nocond")
++   (set_attr "conds"                "clob")
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "*memory_barrier"
+
+=== added file 'gcc/testsuite/gcc.target/arm/sync-1.c'
+--- old/gcc/testsuite/gcc.target/arm/sync-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/sync-1.c	2010-09-13 15:39:11 +0000
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++volatile int mem;
++
++int
++bar (int x, int y)
++{
++  if (x)
++    __sync_fetch_and_add(&mem, y);
++  return 0;
++}
++
++extern void abort (void);
++
++int
++main (int argc, char *argv[])
++{
++  mem = 0;
++  bar (0, 1);
++  bar (1, 1);
++  if (mem != 1)
++    abort ();
++  return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch
new file mode 100644
index 0000000000..31122e34be
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch
@@ -0,0 +1,43 @@
+2010-09-08  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	* gcc/emit-rtl.c (set_mem_attributes_minus_bitpos): Set MEM_READONLY_P
+	for static const strings.
+	* gcc/testsuite/gcc.dg/memcpy-3.c: New test.
+
+ 2010-09-13  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/emit-rtl.c'
+--- old/gcc/emit-rtl.c	2009-11-27 12:00:28 +0000
++++ new/gcc/emit-rtl.c	2010-09-15 16:40:06 +0000
+@@ -1648,6 +1648,11 @@
+ 	  MEM_READONLY_P (ref) = 1;
+ 	}
+ 
++      /* Mark static const strings readonly as well.  */
++      if (base && TREE_CODE (base) == STRING_CST && TREE_READONLY (base)
++	  && TREE_STATIC (base))
++	MEM_READONLY_P (ref) = 1;
++
+       /* If this expression uses it's parent's alias set, mark it such
+ 	 that we won't change it.  */
+       if (component_uses_parent_alias_set (t))
+
+=== added file 'gcc/testsuite/gcc.dg/memcpy-3.c'
+--- old/gcc/testsuite/gcc.dg/memcpy-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/memcpy-3.c	2010-09-15 16:40:06 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-expand" } */
++
++void
++f1 (char *p)
++{
++  __builtin_memcpy (p, "123", 3);
++}
++
++/* { dg-final { scan-rtl-dump-times "mem/s/u:" 3 "expand" { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "expand" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch
new file mode 100644
index 0000000000..9a9d5940c8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch
@@ -0,0 +1,33 @@
+2010-09-10  Nathan Froyd  <froydnj@codesourcery.com>
+
+	Issue #9120
+
+	* release-notes-csl.xml (Compiler optimization improvements): New
+	bullet.
+
+	gcc/
+	* gimple.c (is_gimple_min_invariant): Check for constant INDIRECT_REFs.
+
+ 2010-09-08  Tom de Vries  <tom@codesourcery.com>
+ 
+ 	gcc/
+
+=== modified file 'gcc/gimple.c'
+--- old/gcc/gimple.c	2010-06-22 17:23:11 +0000
++++ new/gcc/gimple.c	2010-09-15 16:47:52 +0000
+@@ -2591,7 +2591,13 @@
+ 
+   op = strip_invariant_refs (TREE_OPERAND (t, 0));
+ 
+-  return op && (CONSTANT_CLASS_P (op) || decl_address_invariant_p (op));
++  if (!op)
++    return false;
++
++  if (TREE_CODE (op) == INDIRECT_REF)
++    return CONSTANT_CLASS_P (TREE_OPERAND (op, 0));
++  else
++    return CONSTANT_CLASS_P (op) || decl_address_invariant_p (op);
+ }
+ 
+ /* Return true if T is a gimple invariant address at IPA level
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch
new file mode 100644
index 0000000000..d8df57a448
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch
@@ -0,0 +1,45 @@
+2010-09-13  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-09-12  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.md (arm_ashldi3_1bit, arm_ashrdi3_1bit,
+	arm_lshrdi3_1bit): Put earlyclobber on the right alternative.
+
+ 2010-09-10  Nathan Froyd  <froydnj@codesourcery.com>
+ 
+ 	Issue #9120
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-09-13 15:39:11 +0000
++++ new/gcc/config/arm/arm.md	2010-09-15 16:55:55 +0000
+@@ -3295,7 +3295,7 @@
+ )
+ 
+ (define_insn "arm_ashldi3_1bit"
+-  [(set (match_operand:DI            0 "s_register_operand" "=&r,r")
++  [(set (match_operand:DI            0 "s_register_operand" "=r,&r")
+         (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r")
+                    (const_int 1)))
+    (clobber (reg:CC CC_REGNUM))]
+@@ -3354,7 +3354,7 @@
+ )
+ 
+ (define_insn "arm_ashrdi3_1bit"
+-  [(set (match_operand:DI              0 "s_register_operand" "=&r,r")
++  [(set (match_operand:DI              0 "s_register_operand" "=r,&r")
+         (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
+                      (const_int 1)))
+    (clobber (reg:CC CC_REGNUM))]
+@@ -3410,7 +3410,7 @@
+ )
+ 
+ (define_insn "arm_lshrdi3_1bit"
+-  [(set (match_operand:DI              0 "s_register_operand" "=&r,r")
++  [(set (match_operand:DI              0 "s_register_operand" "=r,&r")
+         (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
+                      (const_int 1)))
+    (clobber (reg:CC CC_REGNUM))]
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch
new file mode 100644
index 0000000000..809a20aae0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch
@@ -0,0 +1,26 @@
+2010-09-15  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/
+	2010-09-15  Jie Zhang  <jie@codesourcery.com>
+	* config/arm/vfp.md (cmpsf_trap_vfp): Change type from
+	fcmpd to fcmps.
+
+ 2010-09-13  Chung-Lin Tang  <cltang@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2010-08-13 15:28:31 +0000
++++ new/gcc/config/arm/vfp.md	2010-09-16 08:57:30 +0000
+@@ -1159,7 +1159,7 @@
+    fcmpes%?\\t%0, %1
+    fcmpezs%?\\t%0"
+   [(set_attr "predicable" "yes")
+-   (set_attr "type" "fcmpd")]
++   (set_attr "type" "fcmps")]
+ )
+ 
+ (define_insn "*cmpdf_vfp"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch
new file mode 100644
index 0000000000..b7eaa685ae
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch
@@ -0,0 +1,1721 @@
+2010-09-15  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Issue #9441
+
+	Backport from mainline:
+
+	2010-06-25  Bernd Schmidt  <bernds@codesourcery.com>
+
+	With large parts from Jim Wilson:
+	PR target/43902
+
+	gcc/
+	* tree-pretty-print.c (dump_generic_node, op_code_prio): Add
+	WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR.
+	* optabs.c (optab_for_tree_code): Likewise.
+	(expand_widen_pattern_expr): Likewise.
+	* tree-ssa-math-opts.c (convert_mult_to_widen): New function, broken
+	out of execute_optimize_widening_mul.
+	(convert_plusminus_to_widen): New function.
+	(execute_optimize_widening_mul): Use the two new functions.
+	* expr.c (expand_expr_real_2): Add support for GIMPLE_TERNARY_RHS.
+	Remove code to generate widening multiply-accumulate.  Add support
+	for WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR.
+	* gimple-pretty-print.c (dump_ternary_rhs): New function.
+	(dump_gimple_assign): Call it when appropriate.
+	* tree.def (WIDEN_MULT_PLUS_EXPR, WIDEN_MULT_MINUS_EXPR): New codes.
+	* cfgexpand.c (gimple_assign_rhs_to_tree): Likewise.
+	(expand_gimple_stmt_1): Likewise.
+	(expand_debug_expr): Support WIDEN_MULT_PLUS_EXPR and
+	WIDEN_MULT_MINUS_EXPR.
+	* tree-ssa-operands.c (get_expr_operands): Likewise.
+	* tree-inline.c (estimate_operator_cost): Likewise.
+	* gimple.c (extract_ops_from_tree_1): Renamed from
+	extract_ops_from_tree.  Add new arg for a third operand; fill it.
+	(gimple_build_assign_stat): Support operations with three operands.
+	(gimple_build_assign_with_ops_stat): Likewise.
+	(gimple_assign_set_rhs_from_tree): Likewise.
+	(gimple_assign_set_rhs_with_ops_1): Renamed from
+	gimple_assign_set_rhs_with_ops.  Add new arg for a third operand.
+	(get_gimple_rhs_num_ops): Support GIMPLE_TERNARY_RHS.
+	(get_gimple_rhs_num_ops): Handle WIDEN_MULT_PLUS_EXPR and
+	WIDEN_MULT_MINUS_EXPR.
+	* gimple.h (enum gimple_rhs_class): Add GIMPLE_TERNARY_RHS.
+	(extract_ops_from_tree_1): Adjust declaration.
+	(gimple_assign_set_rhs_with_ops_1): Likewise.
+	(gimple_build_assign_with_ops): Pass NULL for last operand.
+	(gimple_build_assign_with_ops3): New macro.
+	(gimple_assign_rhs3, gimple_assign_rhs3_ptr, gimple_assign_set_rhs3,
+	gimple_assign_set_rhs_with_ops, extract_ops_from_tree): New inline
+	functions.
+	* tree-cfg.c (verify_gimple_assign_ternary): New static function.
+	(verify_gimple_assign): Call it.
+	* doc/gimple.texi (Manipulating operands): Document GIMPLE_TERNARY_RHS.
+	(Tuple specific accessors, subsection GIMPLE_ASSIGN): Document new
+	functions for dealing with three-operand statements.
+	* tree.c (commutative_ternary_tree_code): New function.
+	* tree.h (commutative_ternary_tree_code): Declare it.
+	* tree-vrp.c (gimple_assign_nonnegative_warnv_p): Return false for
+	ternary statements.
+	(gimple_assign_nonzero_warnv_p): Likewise.
+	* tree-ssa-sccvn.c (stmt_has_constants): Handle GIMPLE_TERNARY_RHS.
+	* tree-ssa-ccp.c (get_rhs_assign_op_for_ccp): New static function.
+	(ccp_fold): Use it.  Handle GIMPLE_TERNARY_RHS.
+	* tree-ssa-dom.c (enum expr_kind): Add EXPR_TERNARY.
+	(struct hashtable_expr): New member ternary in the union.
+	(initialize_hash_element): Handle GIMPLE_TERNARY_RHS.
+	(hashable_expr_equal_p): Fix indentation.  Handle EXPR_TERNARY.
+	(iterative_hash_hashable_expr): Likewise.
+	(print_expr_hash_elt): Handle EXPR_TERNARY.
+	* gimple-fold.c (fold_gimple_assign): Handle GIMPLE_TERNARY_RHS.
+	* tree-ssa-threadedge.c (fold_assignment_stmt): Remove useless break
+	statements.  Handle GIMPLE_TERNARY_RHS.
+
+	From Jim Wilson:
+	gcc/testsuite/
+	* gcc.target/mips/madd-9.c: New test.
+
+	2010-06-29  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/43902
+	gcc/
+	* config/arm/arm.md (maddsidi4, umaddsidi4): New expanders.
+	(maddhisi4): Renamed from mulhisi3addsi.  Operands renumbered.
+	(maddhidi4): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-1.c: Test for smlabb instead of smulbb.
+	* gcc.target/arm/wmul-3.c: New test.
+	* gcc.target/arm/wmul-4.c: New test.
+
+	2010-07-22  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (is_widening_mult_rhs_p): New function.
+	(is_widening_mult_p): Likewise.
+	(convert_to_widen): Use them.
+	(convert_plusminus_to_widen): Likewise.  Handle fixed-point types as
+	well as integer ones.
+
+	2010-07-31  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (convert_plusminus_to_widen): Fix type
+	used in the call to optab_for_tree_code.  Fix the second
+	is_widening_mult_p call.  Check that both unwidened operands
+	have the same sign.
+
+ 2010-09-15  Jie Zhang  <jie@codesourcery.com>
+ 
+ 	Backport from mainline:
+
+=== modified file 'gcc/cfgexpand.c'
+Index: gcc-4_5-branch/gcc/cfgexpand.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/cfgexpand.c	2011-07-22 16:59:23.000000000 -0700
++++ gcc-4_5-branch/gcc/cfgexpand.c	2011-07-22 16:59:28.581747691 -0700
+@@ -64,7 +64,13 @@
+ 
+   grhs_class = get_gimple_rhs_class (gimple_expr_code (stmt));
+ 
+-  if (grhs_class == GIMPLE_BINARY_RHS)
++  if (grhs_class == GIMPLE_TERNARY_RHS)
++    t = build3 (gimple_assign_rhs_code (stmt),
++		TREE_TYPE (gimple_assign_lhs (stmt)),
++		gimple_assign_rhs1 (stmt),
++		gimple_assign_rhs2 (stmt),
++		gimple_assign_rhs3 (stmt));
++  else if (grhs_class == GIMPLE_BINARY_RHS)
+     t = build2 (gimple_assign_rhs_code (stmt),
+ 		TREE_TYPE (gimple_assign_lhs (stmt)),
+ 		gimple_assign_rhs1 (stmt),
+@@ -1893,6 +1899,9 @@
+ 	    ops.type = TREE_TYPE (lhs);
+ 	    switch (get_gimple_rhs_class (gimple_expr_code (stmt)))
+ 	      {
++		case GIMPLE_TERNARY_RHS:
++		  ops.op2 = gimple_assign_rhs3 (stmt);
++		  /* Fallthru */
+ 		case GIMPLE_BINARY_RHS:
+ 		  ops.op1 = gimple_assign_rhs2 (stmt);
+ 		  /* Fallthru */
+@@ -2243,6 +2252,8 @@
+ 	{
+ 	case COND_EXPR:
+ 	case DOT_PROD_EXPR:
++	case WIDEN_MULT_PLUS_EXPR:
++	case WIDEN_MULT_MINUS_EXPR:
+ 	  goto ternary;
+ 
+ 	case TRUTH_ANDIF_EXPR:
+@@ -3030,6 +3041,8 @@
+       return NULL;
+ 
+     case WIDEN_MULT_EXPR:
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
+       if (SCALAR_INT_MODE_P (GET_MODE (op0))
+ 	  && SCALAR_INT_MODE_P (mode))
+ 	{
+@@ -3042,7 +3055,13 @@
+ 	    op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode);
+ 	  else
+ 	    op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode);
+-	  return gen_rtx_MULT (mode, op0, op1);
++	  op0 = gen_rtx_MULT (mode, op0, op1);
++	  if (TREE_CODE (exp) == WIDEN_MULT_EXPR)
++	    return op0;
++	  else if (TREE_CODE (exp) == WIDEN_MULT_PLUS_EXPR)
++	    return gen_rtx_PLUS (mode, op0, op2);
++	  else
++	    return gen_rtx_MINUS (mode, op2, op0);
+ 	}
+       return NULL;
+ 
+Index: gcc-4_5-branch/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.md	2011-07-22 16:59:25.000000000 -0700
++++ gcc-4_5-branch/gcc/config/arm/arm.md	2011-07-22 16:59:28.581747691 -0700
+@@ -1507,7 +1507,15 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
+-;; Unnamed template to match long long multiply-accumulate (smlal)
++(define_expand "maddsidi4"
++  [(set (match_operand:DI 0 "s_register_operand" "")
++	(plus:DI
++	 (mult:DI
++	  (sign_extend:DI (match_operand:SI 1 "s_register_operand" ""))
++	  (sign_extend:DI (match_operand:SI 2 "s_register_operand" "")))
++	 (match_operand:DI 3 "s_register_operand" "")))]
++  "TARGET_32BIT && arm_arch3m"
++  "")
+ 
+ (define_insn "*mulsidi3adddi"
+   [(set (match_operand:DI 0 "s_register_operand" "=&r")
+@@ -1603,7 +1611,15 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
+-;; Unnamed template to match long long unsigned multiply-accumulate (umlal)
++(define_expand "umaddsidi4"
++  [(set (match_operand:DI 0 "s_register_operand" "")
++	(plus:DI
++	 (mult:DI
++	  (zero_extend:DI (match_operand:SI 1 "s_register_operand" ""))
++	  (zero_extend:DI (match_operand:SI 2 "s_register_operand" "")))
++	 (match_operand:DI 3 "s_register_operand" "")))]
++  "TARGET_32BIT && arm_arch3m"
++  "")
+ 
+ (define_insn "*umulsidi3adddi"
+   [(set (match_operand:DI 0 "s_register_operand" "=&r")
+@@ -1771,29 +1787,29 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
+-(define_insn "*mulhisi3addsi"
++(define_insn "maddhisi4"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (match_operand:SI 1 "s_register_operand" "r")
++	(plus:SI (match_operand:SI 3 "s_register_operand" "r")
+ 		 (mult:SI (sign_extend:SI
+-			   (match_operand:HI 2 "s_register_operand" "%r"))
++			   (match_operand:HI 1 "s_register_operand" "%r"))
+ 			  (sign_extend:SI
+-			   (match_operand:HI 3 "s_register_operand" "r")))))]
++			   (match_operand:HI 2 "s_register_operand" "r")))))]
+   "TARGET_DSP_MULTIPLY"
+-  "smlabb%?\\t%0, %2, %3, %1"
++  "smlabb%?\\t%0, %1, %2, %3"
+   [(set_attr "insn" "smlaxy")
+    (set_attr "predicable" "yes")]
+ )
+ 
+-(define_insn "*mulhidi3adddi"
++(define_insn "*maddhidi4"
+   [(set (match_operand:DI 0 "s_register_operand" "=r")
+ 	(plus:DI
+-	  (match_operand:DI 1 "s_register_operand" "0")
++	  (match_operand:DI 3 "s_register_operand" "0")
+ 	  (mult:DI (sign_extend:DI
+-	 	    (match_operand:HI 2 "s_register_operand" "%r"))
++	 	    (match_operand:HI 1 "s_register_operand" "%r"))
+ 		   (sign_extend:DI
+-		    (match_operand:HI 3 "s_register_operand" "r")))))]
++		    (match_operand:HI 2 "s_register_operand" "r")))))]
+   "TARGET_DSP_MULTIPLY"
+-  "smlalbb%?\\t%Q0, %R0, %2, %3"
++  "smlalbb%?\\t%Q0, %R0, %1, %2"
+   [(set_attr "insn" "smlalxy")
+    (set_attr "predicable" "yes")])
+ 
+Index: gcc-4_5-branch/gcc/doc/gimple.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/gimple.texi	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/doc/gimple.texi	2011-07-22 16:59:28.581747691 -0700
+@@ -554,6 +554,9 @@
+ @item @code{GIMPLE_INVALID_RHS}
+ The tree cannot be used as a GIMPLE operand.
+ 
++@item @code{GIMPLE_TERNARY_RHS}
++The tree is a valid GIMPLE ternary operation.
++
+ @item @code{GIMPLE_BINARY_RHS}
+ The tree is a valid GIMPLE binary operation.
+ 
+@@ -575,10 +578,11 @@
+ expressions should be flattened into the operand vector.
+ @end itemize
+ 
+-For tree nodes in the categories @code{GIMPLE_BINARY_RHS} and
+-@code{GIMPLE_UNARY_RHS}, they cannot be stored inside tuples directly.
+-They first need to be flattened and separated into individual
+-components.  For instance, given the GENERIC expression
++For tree nodes in the categories @code{GIMPLE_TERNARY_RHS},
++@code{GIMPLE_BINARY_RHS} and @code{GIMPLE_UNARY_RHS}, they cannot be
++stored inside tuples directly.  They first need to be flattened and
++separated into individual components.  For instance, given the GENERIC
++expression
+ 
+ @smallexample
+ a = b + c
+@@ -1082,7 +1086,16 @@
+ Return the address of the second operand on the @code{RHS} of assignment
+ statement @code{G}.
+ @end deftypefn
++
++@deftypefn {GIMPLE function} tree gimple_assign_rhs3 (gimple g)
++Return the third operand on the @code{RHS} of assignment statement @code{G}.
++@end deftypefn
+  
++@deftypefn {GIMPLE function} tree *gimple_assign_rhs3_ptr (gimple g)
++Return the address of the third operand on the @code{RHS} of assignment
++statement @code{G}.
++@end deftypefn
++
+ @deftypefn {GIMPLE function} void gimple_assign_set_lhs (gimple g, tree lhs)
+ Set @code{LHS} to be the @code{LHS} operand of assignment statement @code{G}.
+ @end deftypefn
+@@ -1092,17 +1105,13 @@
+ statement @code{G}.
+ @end deftypefn
+  
+-@deftypefn {GIMPLE function} tree gimple_assign_rhs2 (gimple g)
+-Return the second operand on the @code{RHS} of assignment statement @code{G}.
+-@end deftypefn
+- 
+-@deftypefn {GIMPLE function} tree *gimple_assign_rhs2_ptr (gimple g)
+-Return a pointer to the second operand on the @code{RHS} of assignment
++@deftypefn {GIMPLE function} void gimple_assign_set_rhs2 (gimple g, tree rhs)
++Set @code{RHS} to be the second operand on the @code{RHS} of assignment
+ statement @code{G}.
+ @end deftypefn
+  
+-@deftypefn {GIMPLE function} void gimple_assign_set_rhs2 (gimple g, tree rhs)
+-Set @code{RHS} to be the second operand on the @code{RHS} of assignment
++@deftypefn {GIMPLE function} void gimple_assign_set_rhs3 (gimple g, tree rhs)
++Set @code{RHS} to be the third operand on the @code{RHS} of assignment
+ statement @code{G}.
+ @end deftypefn
+  
+Index: gcc-4_5-branch/gcc/expr.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expr.c	2011-07-22 16:59:23.000000000 -0700
++++ gcc-4_5-branch/gcc/expr.c	2011-07-22 16:59:28.591747691 -0700
+@@ -7228,8 +7228,6 @@
+   rtx subtarget, original_target;
+   int ignore;
+   bool reduce_bit_field;
+-  gimple subexp0_def, subexp1_def;
+-  tree top0, top1;
+   location_t loc = ops->location;
+   tree treeop0, treeop1;
+ #define REDUCE_BIT_FIELD(expr)	(reduce_bit_field			  \
+@@ -7249,7 +7247,8 @@
+      exactly those that are valid in gimple expressions that aren't
+      GIMPLE_SINGLE_RHS (or invalid).  */
+   gcc_assert (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS
+-	      || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS);
++	      || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS
++	      || get_gimple_rhs_class (code) == GIMPLE_TERNARY_RHS);
+ 
+   ignore = (target == const0_rtx
+ 	    || ((CONVERT_EXPR_CODE_P (code)
+@@ -7424,58 +7423,6 @@
+ 				    fold_convert_loc (loc, ssizetype,
+ 						      treeop1));
+     case PLUS_EXPR:
+-
+-      /* Check if this is a case for multiplication and addition.  */
+-      if ((TREE_CODE (type) == INTEGER_TYPE
+-	   || TREE_CODE (type) == FIXED_POINT_TYPE)
+-	  && (subexp0_def = get_def_for_expr (treeop0,
+-					      MULT_EXPR)))
+-	{
+-	  tree subsubexp0, subsubexp1;
+-	  gimple subsubexp0_def, subsubexp1_def;
+-	  enum tree_code this_code;
+-
+-	  this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR
+-						       : FIXED_CONVERT_EXPR;
+-	  subsubexp0 = gimple_assign_rhs1 (subexp0_def);
+-	  subsubexp0_def = get_def_for_expr (subsubexp0, this_code);
+-	  subsubexp1 = gimple_assign_rhs2 (subexp0_def);
+-	  subsubexp1_def = get_def_for_expr (subsubexp1, this_code);
+-	  if (subsubexp0_def && subsubexp1_def
+-	      && (top0 = gimple_assign_rhs1 (subsubexp0_def))
+-	      && (top1 = gimple_assign_rhs1 (subsubexp1_def))
+-	      && (TYPE_PRECISION (TREE_TYPE (top0))
+-		  < TYPE_PRECISION (TREE_TYPE (subsubexp0)))
+-	      && (TYPE_PRECISION (TREE_TYPE (top0))
+-		  == TYPE_PRECISION (TREE_TYPE (top1)))
+-	      && (TYPE_UNSIGNED (TREE_TYPE (top0))
+-		  == TYPE_UNSIGNED (TREE_TYPE (top1))))
+-	    {
+-	      tree op0type = TREE_TYPE (top0);
+-	      enum machine_mode innermode = TYPE_MODE (op0type);
+-	      bool zextend_p = TYPE_UNSIGNED (op0type);
+-	      bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0));
+-	      if (sat_p == 0)
+-		this_optab = zextend_p ? umadd_widen_optab : smadd_widen_optab;
+-	      else
+-		this_optab = zextend_p ? usmadd_widen_optab
+-				       : ssmadd_widen_optab;
+-	      if (mode == GET_MODE_2XWIDER_MODE (innermode)
+-		  && (optab_handler (this_optab, mode)->insn_code
+-		      != CODE_FOR_nothing))
+-		{
+-		  expand_operands (top0, top1, NULL_RTX, &op0, &op1,
+-				   EXPAND_NORMAL);
+-		  op2 = expand_expr (treeop1, subtarget,
+-				     VOIDmode, EXPAND_NORMAL);
+-		  temp = expand_ternary_op (mode, this_optab, op0, op1, op2,
+-					    target, unsignedp);
+-		  gcc_assert (temp);
+-		  return REDUCE_BIT_FIELD (temp);
+-		}
+-	    }
+-	}
+-
+       /* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and
+ 	 something else, make sure we add the register to the constant and
+ 	 then to the other thing.  This case can occur during strength
+@@ -7590,57 +7537,6 @@
+       return REDUCE_BIT_FIELD (simplify_gen_binary (PLUS, mode, op0, op1));
+ 
+     case MINUS_EXPR:
+-      /* Check if this is a case for multiplication and subtraction.  */
+-      if ((TREE_CODE (type) == INTEGER_TYPE
+-	   || TREE_CODE (type) == FIXED_POINT_TYPE)
+-	  && (subexp1_def = get_def_for_expr (treeop1,
+-					      MULT_EXPR)))
+-	{
+-	  tree subsubexp0, subsubexp1;
+-	  gimple subsubexp0_def, subsubexp1_def;
+-	  enum tree_code this_code;
+-
+-	  this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR
+-						       : FIXED_CONVERT_EXPR;
+-	  subsubexp0 = gimple_assign_rhs1 (subexp1_def);
+-	  subsubexp0_def = get_def_for_expr (subsubexp0, this_code);
+-	  subsubexp1 = gimple_assign_rhs2 (subexp1_def);
+-	  subsubexp1_def = get_def_for_expr (subsubexp1, this_code);
+-	  if (subsubexp0_def && subsubexp1_def
+-	      && (top0 = gimple_assign_rhs1 (subsubexp0_def))
+-	      && (top1 = gimple_assign_rhs1 (subsubexp1_def))
+-	      && (TYPE_PRECISION (TREE_TYPE (top0))
+-		  < TYPE_PRECISION (TREE_TYPE (subsubexp0)))
+-	      && (TYPE_PRECISION (TREE_TYPE (top0))
+-		  == TYPE_PRECISION (TREE_TYPE (top1)))
+-	      && (TYPE_UNSIGNED (TREE_TYPE (top0))
+-		  == TYPE_UNSIGNED (TREE_TYPE (top1))))
+-	    {
+-	      tree op0type = TREE_TYPE (top0);
+-	      enum machine_mode innermode = TYPE_MODE (op0type);
+-	      bool zextend_p = TYPE_UNSIGNED (op0type);
+-	      bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0));
+-	      if (sat_p == 0)
+-		this_optab = zextend_p ? umsub_widen_optab : smsub_widen_optab;
+-	      else
+-		this_optab = zextend_p ? usmsub_widen_optab
+-				       : ssmsub_widen_optab;
+-	      if (mode == GET_MODE_2XWIDER_MODE (innermode)
+-		  && (optab_handler (this_optab, mode)->insn_code
+-		      != CODE_FOR_nothing))
+-		{
+-		  expand_operands (top0, top1, NULL_RTX, &op0, &op1,
+-				   EXPAND_NORMAL);
+-		  op2 = expand_expr (treeop0, subtarget,
+-				     VOIDmode, EXPAND_NORMAL);
+-		  temp = expand_ternary_op (mode, this_optab, op0, op1, op2,
+-					    target, unsignedp);
+-		  gcc_assert (temp);
+-		  return REDUCE_BIT_FIELD (temp);
+-		}
+-	    }
+-	}
+-
+       /* For initializers, we are allowed to return a MINUS of two
+ 	 symbolic constants.  Here we handle all cases when both operands
+ 	 are constant.  */
+@@ -7681,6 +7577,14 @@
+ 
+       goto binop2;
+ 
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
++      expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL);
++      op2 = expand_normal (ops->op2);
++      target = expand_widen_pattern_expr (ops, op0, op1, op2,
++					  target, unsignedp);
++      return target;
++
+     case WIDEN_MULT_EXPR:
+       /* If first operand is constant, swap them.
+ 	 Thus the following special case checks need only
+Index: gcc-4_5-branch/gcc/gimple-pretty-print.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/gimple-pretty-print.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/gimple-pretty-print.c	2011-07-22 16:59:28.591747691 -0700
+@@ -376,6 +376,34 @@
+     }
+ }
+ 
++/* Helper for dump_gimple_assign.  Print the ternary RHS of the
++   assignment GS.  BUFFER, SPC and FLAGS are as in dump_gimple_stmt.  */
++
++static void
++dump_ternary_rhs (pretty_printer *buffer, gimple gs, int spc, int flags)
++{
++  const char *p;
++  enum tree_code code = gimple_assign_rhs_code (gs);
++  switch (code)
++    {
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
++      for (p = tree_code_name [(int) code]; *p; p++)
++	pp_character (buffer, TOUPPER (*p));
++      pp_string (buffer, " <");
++      dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false);
++      pp_character (buffer, '>');
++      break;
++
++    default:
++      gcc_unreachable ();
++    }
++}
++
+ 
+ /* Dump the gimple assignment GS.  BUFFER, SPC and FLAGS are as in
+    dump_gimple_stmt.  */
+@@ -418,6 +446,8 @@
+         dump_unary_rhs (buffer, gs, spc, flags);
+       else if (gimple_num_ops (gs) == 3)
+         dump_binary_rhs (buffer, gs, spc, flags);
++      else if (gimple_num_ops (gs) == 4)
++        dump_ternary_rhs (buffer, gs, spc, flags);
+       else
+         gcc_unreachable ();
+       if (!(flags & TDF_RHS_ONLY))
+Index: gcc-4_5-branch/gcc/gimple.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/gimple.c	2011-07-22 16:59:25.000000000 -0700
++++ gcc-4_5-branch/gcc/gimple.c	2011-07-22 16:59:28.591747691 -0700
+@@ -289,31 +289,40 @@
+ 
+ 
+ /* Extract the operands and code for expression EXPR into *SUBCODE_P,
+-   *OP1_P and *OP2_P respectively.  */
++   *OP1_P, *OP2_P and *OP3_P respectively.  */
+ 
+ void
+-extract_ops_from_tree (tree expr, enum tree_code *subcode_p, tree *op1_p,
+-		       tree *op2_p)
++extract_ops_from_tree_1 (tree expr, enum tree_code *subcode_p, tree *op1_p,
++			 tree *op2_p, tree *op3_p)
+ {
+   enum gimple_rhs_class grhs_class;
+ 
+   *subcode_p = TREE_CODE (expr);
+   grhs_class = get_gimple_rhs_class (*subcode_p);
+ 
+-  if (grhs_class == GIMPLE_BINARY_RHS)
++  if (grhs_class == GIMPLE_TERNARY_RHS)
+     {
+       *op1_p = TREE_OPERAND (expr, 0);
+       *op2_p = TREE_OPERAND (expr, 1);
++      *op3_p = TREE_OPERAND (expr, 2);
++    }
++  else if (grhs_class == GIMPLE_BINARY_RHS)
++    {
++      *op1_p = TREE_OPERAND (expr, 0);
++      *op2_p = TREE_OPERAND (expr, 1);
++      *op3_p = NULL_TREE;
+     }
+   else if (grhs_class == GIMPLE_UNARY_RHS)
+     {
+       *op1_p = TREE_OPERAND (expr, 0);
+       *op2_p = NULL_TREE;
++      *op3_p = NULL_TREE;
+     }
+   else if (grhs_class == GIMPLE_SINGLE_RHS)
+     {
+       *op1_p = expr;
+       *op2_p = NULL_TREE;
++      *op3_p = NULL_TREE;
+     }
+   else
+     gcc_unreachable ();
+@@ -329,10 +338,10 @@
+ gimple_build_assign_stat (tree lhs, tree rhs MEM_STAT_DECL)
+ {
+   enum tree_code subcode;
+-  tree op1, op2;
++  tree op1, op2, op3;
+ 
+-  extract_ops_from_tree (rhs, &subcode, &op1, &op2);
+-  return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2
++  extract_ops_from_tree_1 (rhs, &subcode, &op1, &op2, &op3);
++  return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2, op3
+   					    PASS_MEM_STAT);
+ }
+ 
+@@ -343,7 +352,7 @@
+ 
+ gimple
+ gimple_build_assign_with_ops_stat (enum tree_code subcode, tree lhs, tree op1,
+-                                   tree op2 MEM_STAT_DECL)
++                                   tree op2, tree op3 MEM_STAT_DECL)
+ {
+   unsigned num_ops;
+   gimple p;
+@@ -362,6 +371,12 @@
+       gimple_assign_set_rhs2 (p, op2);
+     }
+ 
++  if (op3)
++    {
++      gcc_assert (num_ops > 3);
++      gimple_assign_set_rhs3 (p, op3);
++    }
++
+   return p;
+ }
+ 
+@@ -1860,22 +1875,22 @@
+ gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *gsi, tree expr)
+ {
+   enum tree_code subcode;
+-  tree op1, op2;
++  tree op1, op2, op3;
+ 
+-  extract_ops_from_tree (expr, &subcode, &op1, &op2);
+-  gimple_assign_set_rhs_with_ops (gsi, subcode, op1, op2);
++  extract_ops_from_tree_1 (expr, &subcode, &op1, &op2, &op3);
++  gimple_assign_set_rhs_with_ops_1 (gsi, subcode, op1, op2, op3);
+ }
+ 
+ 
+ /* Set the RHS of assignment statement pointed-to by GSI to CODE with
+-   operands OP1 and OP2.
++   operands OP1, OP2 and OP3.
+ 
+    NOTE: The statement pointed-to by GSI may be reallocated if it
+    did not have enough operand slots.  */
+ 
+ void
+-gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code,
+-				tree op1, tree op2)
++gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *gsi, enum tree_code code,
++				  tree op1, tree op2, tree op3)
+ {
+   unsigned new_rhs_ops = get_gimple_rhs_num_ops (code);
+   gimple stmt = gsi_stmt (*gsi);
+@@ -1899,6 +1914,8 @@
+   gimple_assign_set_rhs1 (stmt, op1);
+   if (new_rhs_ops > 1)
+     gimple_assign_set_rhs2 (stmt, op2);
++  if (new_rhs_ops > 2)
++    gimple_assign_set_rhs3 (stmt, op3);
+ }
+ 
+ 
+@@ -2378,6 +2395,8 @@
+     return 1;
+   else if (rhs_class == GIMPLE_BINARY_RHS)
+     return 2;
++  else if (rhs_class == GIMPLE_TERNARY_RHS)
++    return 3;
+   else
+     gcc_unreachable ();
+ }
+@@ -2394,6 +2413,8 @@
+       || (SYM) == TRUTH_OR_EXPR						    \
+       || (SYM) == TRUTH_XOR_EXPR) ? GIMPLE_BINARY_RHS			    \
+    : (SYM) == TRUTH_NOT_EXPR ? GIMPLE_UNARY_RHS				    \
++   : ((SYM) == WIDEN_MULT_PLUS_EXPR					    \
++      || (SYM) == WIDEN_MULT_MINUS_EXPR) ? GIMPLE_TERNARY_RHS		    \
+    : ((SYM) == COND_EXPR						    \
+       || (SYM) == CONSTRUCTOR						    \
+       || (SYM) == OBJ_TYPE_REF						    \
+Index: gcc-4_5-branch/gcc/gimple.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/gimple.h	2011-07-22 16:59:12.000000000 -0700
++++ gcc-4_5-branch/gcc/gimple.h	2011-07-22 16:59:28.591747691 -0700
+@@ -80,6 +80,7 @@
+ enum gimple_rhs_class
+ {
+   GIMPLE_INVALID_RHS,	/* The expression cannot be used on the RHS.  */
++  GIMPLE_TERNARY_RHS,	/* The expression is a ternary operation.  */
+   GIMPLE_BINARY_RHS,	/* The expression is a binary operation.  */
+   GIMPLE_UNARY_RHS,	/* The expression is a unary operation.  */
+   GIMPLE_SINGLE_RHS	/* The expression is a single object (an SSA
+@@ -786,12 +787,14 @@
+ gimple gimple_build_assign_stat (tree, tree MEM_STAT_DECL);
+ #define gimple_build_assign(l,r) gimple_build_assign_stat (l, r MEM_STAT_INFO)
+ 
+-void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *);
++void extract_ops_from_tree_1 (tree, enum tree_code *, tree *, tree *, tree *);
+ 
+ gimple gimple_build_assign_with_ops_stat (enum tree_code, tree, tree,
+-					  tree MEM_STAT_DECL);
+-#define gimple_build_assign_with_ops(c,o1,o2,o3) \
+-  gimple_build_assign_with_ops_stat (c, o1, o2, o3 MEM_STAT_INFO)
++					  tree, tree MEM_STAT_DECL);
++#define gimple_build_assign_with_ops(c,o1,o2,o3)			\
++  gimple_build_assign_with_ops_stat (c, o1, o2, o3, NULL_TREE MEM_STAT_INFO)
++#define gimple_build_assign_with_ops3(c,o1,o2,o3,o4)			\
++  gimple_build_assign_with_ops_stat (c, o1, o2, o3, o4 MEM_STAT_INFO)
+ 
+ gimple gimple_build_debug_bind_stat (tree, tree, gimple MEM_STAT_DECL);
+ #define gimple_build_debug_bind(var,val,stmt)			\
+@@ -850,8 +853,8 @@
+ bool gimple_assign_unary_nop_p (gimple);
+ void gimple_set_bb (gimple, struct basic_block_def *);
+ void gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *, tree);
+-void gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *, enum tree_code,
+-				     tree, tree);
++void gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *, enum tree_code,
++				       tree, tree, tree);
+ tree gimple_get_lhs (const_gimple);
+ void gimple_set_lhs (gimple, tree);
+ void gimple_replace_lhs (gimple, tree);
+@@ -1793,6 +1796,63 @@
+   gimple_set_op (gs, 2, rhs);
+ }
+ 
++/* Return the third operand on the RHS of assignment statement GS.
++   If GS does not have two operands, NULL is returned instead.  */
++
++static inline tree
++gimple_assign_rhs3 (const_gimple gs)
++{
++  GIMPLE_CHECK (gs, GIMPLE_ASSIGN);
++
++  if (gimple_num_ops (gs) >= 4)
++    return gimple_op (gs, 3);
++  else
++    return NULL_TREE;
++}
++
++/* Return a pointer to the third operand on the RHS of assignment
++   statement GS.  */
++
++static inline tree *
++gimple_assign_rhs3_ptr (const_gimple gs)
++{
++  GIMPLE_CHECK (gs, GIMPLE_ASSIGN);
++  return gimple_op_ptr (gs, 3);
++}
++
++
++/* Set RHS to be the third operand on the RHS of assignment statement GS.  */
++
++static inline void
++gimple_assign_set_rhs3 (gimple gs, tree rhs)
++{
++  GIMPLE_CHECK (gs, GIMPLE_ASSIGN);
++
++  gimple_set_op (gs, 3, rhs);
++}
++
++/* A wrapper around gimple_assign_set_rhs_with_ops_1, for callers which expect
++   to see only a maximum of two operands.  */
++
++static inline void
++gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code,
++				tree op1, tree op2)
++{
++  gimple_assign_set_rhs_with_ops_1 (gsi, code, op1, op2, NULL);
++}
++
++/* A wrapper around extract_ops_from_tree_1, for callers which expect
++   to see only a maximum of two operands.  */
++
++static inline void
++extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0,
++		       tree *op1)
++{
++  tree op2;
++  extract_ops_from_tree_1 (expr, code, op0, op1, &op2);
++  gcc_assert (op2 == NULL_TREE);
++}
++
+ /* Returns true if GS is a nontemporal move.  */
+ 
+ static inline bool
+Index: gcc-4_5-branch/gcc/optabs.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/optabs.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/optabs.c	2011-07-22 16:59:28.601747691 -0700
+@@ -408,6 +408,20 @@
+     case DOT_PROD_EXPR:
+       return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab;
+ 
++    case WIDEN_MULT_PLUS_EXPR:
++      return (TYPE_UNSIGNED (type)
++	      ? (TYPE_SATURATING (type)
++		 ? usmadd_widen_optab : umadd_widen_optab)
++	      : (TYPE_SATURATING (type)
++		 ? ssmadd_widen_optab : smadd_widen_optab));
++
++    case WIDEN_MULT_MINUS_EXPR:
++      return (TYPE_UNSIGNED (type)
++	      ? (TYPE_SATURATING (type)
++		 ? usmsub_widen_optab : umsub_widen_optab)
++	      : (TYPE_SATURATING (type)
++		 ? ssmsub_widen_optab : smsub_widen_optab));
++
+     case REDUC_MAX_EXPR:
+       return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab;
+ 
+@@ -547,7 +561,12 @@
+   tmode0 = TYPE_MODE (TREE_TYPE (oprnd0));
+   widen_pattern_optab =
+     optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default);
+-  icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code;
++  if (ops->code == WIDEN_MULT_PLUS_EXPR
++      || ops->code == WIDEN_MULT_MINUS_EXPR)
++    icode = (int) optab_handler (widen_pattern_optab,
++				 TYPE_MODE (TREE_TYPE (ops->op2)))->insn_code;
++  else
++    icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code;
+   gcc_assert (icode != CODE_FOR_nothing);
+   xmode0 = insn_data[icode].operand[1].mode;
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/wmul-1.c	2011-07-22 16:59:24.000000000 -0700
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c	2011-07-22 16:59:28.601747691 -0700
+@@ -15,4 +15,4 @@
+   return sqr;
+ }
+ 
+-/* { dg-final { scan-assembler-times "smulbb" 2 } } */
++/* { dg-final { scan-assembler-times "smlabb" 2 } } */
+Index: gcc-4_5-branch/gcc/tree-cfg.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-cfg.c	2011-07-22 16:59:24.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-cfg.c	2011-07-22 16:59:28.601747691 -0700
+@@ -3484,6 +3484,65 @@
+   return false;
+ }
+ 
++/* Verify a gimple assignment statement STMT with a ternary rhs.
++   Returns true if anything is wrong.  */
++
++static bool
++verify_gimple_assign_ternary (gimple stmt)
++{
++  enum tree_code rhs_code = gimple_assign_rhs_code (stmt);
++  tree lhs = gimple_assign_lhs (stmt);
++  tree lhs_type = TREE_TYPE (lhs);
++  tree rhs1 = gimple_assign_rhs1 (stmt);
++  tree rhs1_type = TREE_TYPE (rhs1);
++  tree rhs2 = gimple_assign_rhs2 (stmt);
++  tree rhs2_type = TREE_TYPE (rhs2);
++  tree rhs3 = gimple_assign_rhs3 (stmt);
++  tree rhs3_type = TREE_TYPE (rhs3);
++
++  if (!is_gimple_reg (lhs)
++      && !(optimize == 0
++	   && TREE_CODE (lhs_type) == COMPLEX_TYPE))
++    {
++      error ("non-register as LHS of ternary operation");
++      return true;
++    }
++
++  if (!is_gimple_val (rhs1)
++      || !is_gimple_val (rhs2)
++      || !is_gimple_val (rhs3))
++    {
++      error ("invalid operands in ternary operation");
++      return true;
++    }
++
++  /* First handle operations that involve different types.  */
++  switch (rhs_code)
++    {
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
++      if ((!INTEGRAL_TYPE_P (rhs1_type)
++	   && !FIXED_POINT_TYPE_P (rhs1_type))
++	  || !useless_type_conversion_p (rhs1_type, rhs2_type)
++	  || !useless_type_conversion_p (lhs_type, rhs3_type)
++	  || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)
++	  || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))
++	{
++	  error ("type mismatch in widening multiply-accumulate expression");
++	  debug_generic_expr (lhs_type);
++	  debug_generic_expr (rhs1_type);
++	  debug_generic_expr (rhs2_type);
++	  debug_generic_expr (rhs3_type);
++	  return true;
++	}
++      break;
++
++    default:
++      gcc_unreachable ();
++    }
++  return false;
++}
++
+ /* Verify a gimple assignment statement STMT with a single rhs.
+    Returns true if anything is wrong.  */
+ 
+@@ -3616,6 +3675,9 @@
+     case GIMPLE_BINARY_RHS:
+       return verify_gimple_assign_binary (stmt);
+ 
++    case GIMPLE_TERNARY_RHS:
++      return verify_gimple_assign_ternary (stmt);
++
+     default:
+       gcc_unreachable ();
+     }
+Index: gcc-4_5-branch/gcc/tree-inline.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-inline.c	2011-07-22 16:59:24.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-inline.c	2011-07-22 16:59:28.601747691 -0700
+@@ -3207,6 +3207,8 @@
+     case WIDEN_SUM_EXPR:
+     case WIDEN_MULT_EXPR:
+     case DOT_PROD_EXPR:
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
+ 
+     case VEC_WIDEN_MULT_HI_EXPR:
+     case VEC_WIDEN_MULT_LO_EXPR:
+Index: gcc-4_5-branch/gcc/tree-pretty-print.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-pretty-print.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-pretty-print.c	2011-07-22 16:59:28.611747691 -0700
+@@ -1939,6 +1939,26 @@
+       pp_string (buffer, " > ");
+       break;
+ 
++    case WIDEN_MULT_PLUS_EXPR:
++      pp_string (buffer, " WIDEN_MULT_PLUS_EXPR < ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false);
++      pp_string (buffer, " > ");
++      break;
++
++    case WIDEN_MULT_MINUS_EXPR:
++      pp_string (buffer, " WIDEN_MULT_MINUS_EXPR < ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false);
++      pp_string (buffer, " > ");
++      break;
++
+     case OMP_PARALLEL:
+       pp_string (buffer, "#pragma omp parallel");
+       dump_omp_clauses (buffer, OMP_PARALLEL_CLAUSES (node), spc, flags);
+@@ -2432,6 +2452,8 @@
+     case VEC_WIDEN_MULT_LO_EXPR:
+     case WIDEN_MULT_EXPR:
+     case DOT_PROD_EXPR:
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
+     case MULT_EXPR:
+     case TRUNC_DIV_EXPR:
+     case CEIL_DIV_EXPR:
+Index: gcc-4_5-branch/gcc/tree-ssa-ccp.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-ccp.c	2011-07-22 16:59:12.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-ssa-ccp.c	2011-07-22 16:59:28.611747691 -0700
+@@ -915,6 +915,23 @@
+ 					TREE_TYPE (TREE_OPERAND (addr, 0))));
+ }
+ 
++/* Get operand number OPNR from the rhs of STMT.  Before returning it,
++   simplify it to a constant if possible.  */
++
++static tree
++get_rhs_assign_op_for_ccp (gimple stmt, int opnr)
++{
++  tree op = gimple_op (stmt, opnr);
++  
++  if (TREE_CODE (op) == SSA_NAME)
++    {
++      prop_value_t *val = get_value (op);
++      if (val->lattice_val == CONSTANT)
++	op = get_value (op)->value;
++    }
++  return op;
++}
++
+ /* CCP specific front-end to the non-destructive constant folding
+    routines.
+ 
+@@ -1037,15 +1054,7 @@
+                  Note that we know the single operand must be a constant,
+                  so this should almost always return a simplified RHS.  */
+               tree lhs = gimple_assign_lhs (stmt);
+-              tree op0 = gimple_assign_rhs1 (stmt);
+-
+-              /* Simplify the operand down to a constant.  */
+-              if (TREE_CODE (op0) == SSA_NAME)
+-                {
+-                  prop_value_t *val = get_value (op0);
+-                  if (val->lattice_val == CONSTANT)
+-                    op0 = get_value (op0)->value;
+-                }
++              tree op0 = get_rhs_assign_op_for_ccp (stmt, 1);
+ 
+ 	      /* Conversions are useless for CCP purposes if they are
+ 		 value-preserving.  Thus the restrictions that
+@@ -1082,23 +1091,8 @@
+           case GIMPLE_BINARY_RHS:
+             {
+               /* Handle binary operators that can appear in GIMPLE form.  */
+-              tree op0 = gimple_assign_rhs1 (stmt);
+-              tree op1 = gimple_assign_rhs2 (stmt);
+-
+-              /* Simplify the operands down to constants when appropriate.  */
+-              if (TREE_CODE (op0) == SSA_NAME)
+-                {
+-                  prop_value_t *val = get_value (op0);
+-                  if (val->lattice_val == CONSTANT)
+-                    op0 = val->value;
+-                }
+-
+-              if (TREE_CODE (op1) == SSA_NAME)
+-                {
+-                  prop_value_t *val = get_value (op1);
+-                  if (val->lattice_val == CONSTANT)
+-                    op1 = val->value;
+-                }
++              tree op0 = get_rhs_assign_op_for_ccp (stmt, 1);
++              tree op1 = get_rhs_assign_op_for_ccp (stmt, 2);
+ 
+ 	      /* Fold &foo + CST into an invariant reference if possible.  */
+ 	      if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR
+@@ -1115,6 +1109,17 @@
+ 				  gimple_expr_type (stmt), op0, op1);
+             }
+ 
++          case GIMPLE_TERNARY_RHS:
++            {
++              /* Handle binary operators that can appear in GIMPLE form.  */
++              tree op0 = get_rhs_assign_op_for_ccp (stmt, 1);
++              tree op1 = get_rhs_assign_op_for_ccp (stmt, 2);
++              tree op2 = get_rhs_assign_op_for_ccp (stmt, 3);
++
++              return fold_ternary_loc (loc, subcode,
++				       gimple_expr_type (stmt), op0, op1, op2);
++            }
++
+           default:
+             gcc_unreachable ();
+           }
+@@ -2959,6 +2964,33 @@
+         }
+       break;
+ 
++    case GIMPLE_TERNARY_RHS:
++      result = fold_ternary_loc (loc, subcode,
++				 TREE_TYPE (gimple_assign_lhs (stmt)),
++				 gimple_assign_rhs1 (stmt),
++				 gimple_assign_rhs2 (stmt),
++				 gimple_assign_rhs3 (stmt));
++
++      if (result)
++        {
++          STRIP_USELESS_TYPE_CONVERSION (result);
++          if (valid_gimple_rhs_p (result))
++	    return result;
++
++	  /* Fold might have produced non-GIMPLE, so if we trust it blindly
++	     we lose canonicalization opportunities.  Do not go again
++	     through fold here though, or the same non-GIMPLE will be
++	     produced.  */
++          if (commutative_ternary_tree_code (subcode)
++              && tree_swap_operands_p (gimple_assign_rhs1 (stmt),
++                                       gimple_assign_rhs2 (stmt), false))
++            return build3 (subcode, TREE_TYPE (gimple_assign_lhs (stmt)),
++			   gimple_assign_rhs2 (stmt),
++			   gimple_assign_rhs1 (stmt),
++			   gimple_assign_rhs3 (stmt));
++        }
++      break;
++
+     case GIMPLE_INVALID_RHS:
+       gcc_unreachable ();
+     }
+Index: gcc-4_5-branch/gcc/tree-ssa-dom.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-dom.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-ssa-dom.c	2011-07-22 17:23:51.501747355 -0700
+@@ -54,6 +54,7 @@
+   EXPR_SINGLE,
+   EXPR_UNARY,
+   EXPR_BINARY,
++  EXPR_TERNARY,
+   EXPR_CALL
+ };
+ 
+@@ -64,7 +65,8 @@
+   union {
+     struct { tree rhs; } single;
+     struct { enum tree_code op;  tree opnd; } unary;
+-    struct { enum tree_code op;  tree opnd0; tree opnd1; } binary;
++    struct { enum tree_code op;  tree opnd0, opnd1; } binary;
++    struct { enum tree_code op;  tree opnd0, opnd1, opnd2; } ternary;
+     struct { tree fn; bool pure; size_t nargs; tree *args; } call;
+   } ops;
+ };
+@@ -229,6 +231,14 @@
+           expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt);
+           expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt);
+           break;
++        case GIMPLE_TERNARY_RHS:
++          expr->kind = EXPR_TERNARY;
++          expr->type = TREE_TYPE (gimple_assign_lhs (stmt));
++          expr->ops.ternary.op = subcode;
++          expr->ops.ternary.opnd0 = gimple_assign_rhs1 (stmt);
++          expr->ops.ternary.opnd1 = gimple_assign_rhs2 (stmt);
++          expr->ops.ternary.opnd2 = gimple_assign_rhs3 (stmt);
++          break;
+         default:
+           gcc_unreachable ();
+         }
+@@ -373,23 +383,40 @@
+                               expr1->ops.unary.opnd, 0);
+ 
+     case EXPR_BINARY:
+-      {
+-        if (expr0->ops.binary.op != expr1->ops.binary.op)
+-          return false;
++      if (expr0->ops.binary.op != expr1->ops.binary.op)
++	return false;
+ 
+-        if (operand_equal_p (expr0->ops.binary.opnd0,
+-                             expr1->ops.binary.opnd0, 0)
+-            && operand_equal_p (expr0->ops.binary.opnd1,
+-                                expr1->ops.binary.opnd1, 0))
+-          return true;
+-
+-        /* For commutative ops, allow the other order.  */
+-        return (commutative_tree_code (expr0->ops.binary.op)
+-                && operand_equal_p (expr0->ops.binary.opnd0,
+-                                    expr1->ops.binary.opnd1, 0)
+-                && operand_equal_p (expr0->ops.binary.opnd1,
+-                                    expr1->ops.binary.opnd0, 0));
+-      }
++      if (operand_equal_p (expr0->ops.binary.opnd0,
++			   expr1->ops.binary.opnd0, 0)
++	  && operand_equal_p (expr0->ops.binary.opnd1,
++			      expr1->ops.binary.opnd1, 0))
++	return true;
++
++      /* For commutative ops, allow the other order.  */
++      return (commutative_tree_code (expr0->ops.binary.op)
++	      && operand_equal_p (expr0->ops.binary.opnd0,
++				  expr1->ops.binary.opnd1, 0)
++	      && operand_equal_p (expr0->ops.binary.opnd1,
++				  expr1->ops.binary.opnd0, 0));
++
++    case EXPR_TERNARY:
++      if (expr0->ops.ternary.op != expr1->ops.ternary.op
++	  || !operand_equal_p (expr0->ops.ternary.opnd2,
++			       expr1->ops.ternary.opnd2, 0))
++	return false;
++
++      if (operand_equal_p (expr0->ops.ternary.opnd0,
++			   expr1->ops.ternary.opnd0, 0)
++	  && operand_equal_p (expr0->ops.ternary.opnd1,
++			      expr1->ops.ternary.opnd1, 0))
++	return true;
++
++      /* For commutative ops, allow the other order.  */
++      return (commutative_ternary_tree_code (expr0->ops.ternary.op)
++	      && operand_equal_p (expr0->ops.ternary.opnd0,
++				  expr1->ops.ternary.opnd1, 0)
++	      && operand_equal_p (expr0->ops.ternary.opnd1,
++				  expr1->ops.ternary.opnd0, 0));
+ 
+     case EXPR_CALL:
+       {
+@@ -452,8 +479,8 @@
+     case EXPR_BINARY:
+       val = iterative_hash_object (expr->ops.binary.op, val);
+       if (commutative_tree_code (expr->ops.binary.op))
+-          val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0,
+-                                                  expr->ops.binary.opnd1, val);
++	val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0,
++						expr->ops.binary.opnd1, val);
+       else
+         {
+           val = iterative_hash_expr (expr->ops.binary.opnd0, val);
+@@ -461,6 +488,19 @@
+         }
+       break;
+ 
++    case EXPR_TERNARY:
++      val = iterative_hash_object (expr->ops.ternary.op, val);
++      if (commutative_ternary_tree_code (expr->ops.ternary.op))
++	val = iterative_hash_exprs_commutative (expr->ops.ternary.opnd0,
++						expr->ops.ternary.opnd1, val);
++      else
++        {
++          val = iterative_hash_expr (expr->ops.ternary.opnd0, val);
++          val = iterative_hash_expr (expr->ops.ternary.opnd1, val);
++        }
++      val = iterative_hash_expr (expr->ops.ternary.opnd2, val);
++      break;
++
+     case EXPR_CALL:
+       {
+         size_t i;
+@@ -513,6 +553,16 @@
+         print_generic_expr (stream, element->expr.ops.binary.opnd1, 0);
+         break;
+ 
++      case EXPR_TERNARY:
++        fprintf (stream, " %s <", tree_code_name[element->expr.ops.ternary.op]);
++        print_generic_expr (stream, element->expr.ops.ternary.opnd0, 0);
++	fputs (", ", stream);
++        print_generic_expr (stream, element->expr.ops.ternary.opnd1, 0);
++	fputs (", ", stream);
++        print_generic_expr (stream, element->expr.ops.ternary.opnd2, 0);
++	fputs (">", stream);
++        break;
++
+       case EXPR_CALL:
+         {
+           size_t i;
+Index: gcc-4_5-branch/gcc/tree-ssa-math-opts.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-math-opts.c	2011-07-22 16:59:24.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-ssa-math-opts.c	2011-07-22 16:59:28.611747691 -0700
+@@ -1270,6 +1270,235 @@
+  }
+ };
+ 
++/* Return true if RHS is a suitable operand for a widening multiplication.
++   There are two cases:
++
++     - RHS makes some value twice as wide.  Store that value in *NEW_RHS_OUT
++       if so, and store its type in *TYPE_OUT.
++
++     - RHS is an integer constant.  Store that value in *NEW_RHS_OUT if so,
++       but leave *TYPE_OUT untouched.  */
++
++static bool
++is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out)
++{
++  gimple stmt;
++  tree type, type1, rhs1;
++  enum tree_code rhs_code;
++
++  if (TREE_CODE (rhs) == SSA_NAME)
++    {
++      type = TREE_TYPE (rhs);
++      stmt = SSA_NAME_DEF_STMT (rhs);
++      if (!is_gimple_assign (stmt))
++	return false;
++
++      rhs_code = gimple_assign_rhs_code (stmt);
++      if (TREE_CODE (type) == INTEGER_TYPE
++	  ? !CONVERT_EXPR_CODE_P (rhs_code)
++	  : rhs_code != FIXED_CONVERT_EXPR)
++	return false;
++
++      rhs1 = gimple_assign_rhs1 (stmt);
++      type1 = TREE_TYPE (rhs1);
++      if (TREE_CODE (type1) != TREE_CODE (type)
++	  || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type))
++	return false;
++
++      *new_rhs_out = rhs1;
++      *type_out = type1;
++      return true;
++    }
++
++  if (TREE_CODE (rhs) == INTEGER_CST)
++    {
++      *new_rhs_out = rhs;
++      *type_out = NULL;
++      return true;
++    }
++
++  return false;
++}
++
++/* Return true if STMT performs a widening multiplication.  If so,
++   store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT
++   respectively.  Also fill *RHS1_OUT and *RHS2_OUT such that converting
++   those operands to types *TYPE1_OUT and *TYPE2_OUT would give the
++   operands of the multiplication.  */
++
++static bool
++is_widening_mult_p (gimple stmt,
++		    tree *type1_out, tree *rhs1_out,
++		    tree *type2_out, tree *rhs2_out)
++{
++  tree type;
++
++  type = TREE_TYPE (gimple_assign_lhs (stmt));
++  if (TREE_CODE (type) != INTEGER_TYPE
++      && TREE_CODE (type) != FIXED_POINT_TYPE)
++    return false;
++
++  if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out))
++    return false;
++
++  if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out))
++    return false;
++
++  if (*type1_out == NULL)
++    {
++      if (*type2_out == NULL || !int_fits_type_p (*rhs1_out, *type2_out))
++	return false;
++      *type1_out = *type2_out;
++    }
++
++  if (*type2_out == NULL)
++    {
++      if (!int_fits_type_p (*rhs2_out, *type1_out))
++	return false;
++      *type2_out = *type1_out;
++    }
++
++  return true;
++}
++
++/* Process a single gimple statement STMT, which has a MULT_EXPR as
++   its rhs, and try to convert it into a WIDEN_MULT_EXPR.  The return
++   value is true iff we converted the statement.  */
++
++static bool
++convert_mult_to_widen (gimple stmt)
++{
++  tree lhs, rhs1, rhs2, type, type1, type2;
++  enum insn_code handler;
++
++  lhs = gimple_assign_lhs (stmt);
++  type = TREE_TYPE (lhs);
++  if (TREE_CODE (type) != INTEGER_TYPE)
++    return false;
++
++  if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
++    return false;
++
++  if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2))
++    handler = optab_handler (umul_widen_optab, TYPE_MODE (type))->insn_code;
++  else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2))
++    handler = optab_handler (smul_widen_optab, TYPE_MODE (type))->insn_code;
++  else
++    handler = optab_handler (usmul_widen_optab, TYPE_MODE (type))->insn_code;
++
++  if (handler == CODE_FOR_nothing)
++    return false;
++
++  gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1));
++  gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2));
++  gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR);
++  update_stmt (stmt);
++  return true;
++}
++
++/* Process a single gimple statement STMT, which is found at the
++   iterator GSI and has a either a PLUS_EXPR or a MINUS_EXPR as its
++   rhs (given by CODE), and try to convert it into a
++   WIDEN_MULT_PLUS_EXPR or a WIDEN_MULT_MINUS_EXPR.  The return value
++   is true iff we converted the statement.  */
++
++static bool
++convert_plusminus_to_widen (gimple_stmt_iterator *gsi, gimple stmt,
++			    enum tree_code code)
++{
++  gimple rhs1_stmt = NULL, rhs2_stmt = NULL;
++  tree type, type1, type2;
++  tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs;
++  enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK;
++  optab this_optab;
++  enum tree_code wmult_code;
++
++  lhs = gimple_assign_lhs (stmt);
++  type = TREE_TYPE (lhs);
++  if (TREE_CODE (type) != INTEGER_TYPE
++      && TREE_CODE (type) != FIXED_POINT_TYPE)
++    return false;
++
++  if (code == MINUS_EXPR)
++    wmult_code = WIDEN_MULT_MINUS_EXPR;
++  else
++    wmult_code = WIDEN_MULT_PLUS_EXPR;
++
++  rhs1 = gimple_assign_rhs1 (stmt);
++  rhs2 = gimple_assign_rhs2 (stmt);
++
++  if (TREE_CODE (rhs1) == SSA_NAME)
++    {
++      rhs1_stmt = SSA_NAME_DEF_STMT (rhs1);
++      if (is_gimple_assign (rhs1_stmt))
++	rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
++    }
++  else
++    return false;
++
++  if (TREE_CODE (rhs2) == SSA_NAME)
++    {
++      rhs2_stmt = SSA_NAME_DEF_STMT (rhs2);
++      if (is_gimple_assign (rhs2_stmt))
++	rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
++    }
++  else
++    return false;
++
++  if (code == PLUS_EXPR && rhs1_code == MULT_EXPR)
++    {
++      if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
++			       &type2, &mult_rhs2))
++	return false;
++      add_rhs = rhs2;
++    }
++  else if (rhs2_code == MULT_EXPR)
++    {
++      if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
++			       &type2, &mult_rhs2))
++	return false;
++      add_rhs = rhs1;
++    }
++  else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR)
++    {
++      mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt);
++      mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt);
++      type1 = TREE_TYPE (mult_rhs1);
++      type2 = TREE_TYPE (mult_rhs2);
++      add_rhs = rhs2;
++    }
++  else if (rhs2_code == WIDEN_MULT_EXPR)
++    {
++      mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt);
++      mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt);
++      type1 = TREE_TYPE (mult_rhs1);
++      type2 = TREE_TYPE (mult_rhs2);
++      add_rhs = rhs1;
++    }
++  else
++    return false;
++
++  if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2))
++    return false;
++
++  /* Verify that the machine can perform a widening multiply
++     accumulate in this mode/signedness combination, otherwise
++     this transformation is likely to pessimize code.  */
++  this_optab = optab_for_tree_code (wmult_code, type1, optab_default);
++  if (optab_handler (this_optab, TYPE_MODE (type))->insn_code
++      == CODE_FOR_nothing)
++    return false;
++
++  /* ??? May need some type verification here?  */
++
++  gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code,
++				    fold_convert (type1, mult_rhs1),
++				    fold_convert (type2, mult_rhs2),
++				    add_rhs);
++  update_stmt (gsi_stmt (*gsi));
++  return true;
++}
++
+ /* Find integer multiplications where the operands are extended from
+    smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR
+    where appropriate.  */
+@@ -1287,94 +1516,19 @@
+       for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi))
+         {
+ 	  gimple stmt = gsi_stmt (gsi);
+-	  gimple rhs1_stmt = NULL, rhs2_stmt = NULL;
+-	  tree type, type1 = NULL, type2 = NULL;
+-	  tree rhs1, rhs2, rhs1_convop = NULL, rhs2_convop = NULL;
+-	  enum tree_code rhs1_code, rhs2_code;
++	  enum tree_code code;
+ 
+-	  if (!is_gimple_assign (stmt)
+-	      || gimple_assign_rhs_code (stmt) != MULT_EXPR)
++	  if (!is_gimple_assign (stmt))
+ 	    continue;
+ 
+-	  type = TREE_TYPE (gimple_assign_lhs (stmt));
+-
+-	  if (TREE_CODE (type) != INTEGER_TYPE)
+-	    continue;
+-
+-	  rhs1 = gimple_assign_rhs1 (stmt);
+-	  rhs2 = gimple_assign_rhs2 (stmt);
+-
+-	  if (TREE_CODE (rhs1) == SSA_NAME)
+-	    {
+-	      rhs1_stmt = SSA_NAME_DEF_STMT (rhs1);
+-	      if (!is_gimple_assign (rhs1_stmt))
+-		continue;
+-	      rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
+-	      if (!CONVERT_EXPR_CODE_P (rhs1_code))
+-		continue;
+-	      rhs1_convop = gimple_assign_rhs1 (rhs1_stmt);
+-	      type1 = TREE_TYPE (rhs1_convop);
+-	      if (TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type))
+-		continue;
+-	    }
+-	  else if (TREE_CODE (rhs1) != INTEGER_CST)
+-	    continue;
+-
+-	  if (TREE_CODE (rhs2) == SSA_NAME)
+-	    {
+-	      rhs2_stmt = SSA_NAME_DEF_STMT (rhs2);
+-	      if (!is_gimple_assign (rhs2_stmt))
+-		continue;
+-	      rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
+-	      if (!CONVERT_EXPR_CODE_P (rhs2_code))
+-		continue;
+-	      rhs2_convop = gimple_assign_rhs1 (rhs2_stmt);
+-	      type2 = TREE_TYPE (rhs2_convop);
+-	      if (TYPE_PRECISION (type2) * 2 != TYPE_PRECISION (type))
+-		continue;
+-	    }
+-	  else if (TREE_CODE (rhs2) != INTEGER_CST)
+-	    continue;
+-
+-	  if (rhs1_stmt == NULL && rhs2_stmt == NULL)
+-	    continue;
+-
+-	  /* Verify that the machine can perform a widening multiply in this
+-	     mode/signedness combination, otherwise this transformation is
+-	     likely to pessimize code.  */
+-	  if ((rhs1_stmt == NULL || TYPE_UNSIGNED (type1))
+-	      && (rhs2_stmt == NULL || TYPE_UNSIGNED (type2))
+-	      && (optab_handler (umul_widen_optab, TYPE_MODE (type))
+-		  ->insn_code == CODE_FOR_nothing))
+-	    continue;
+-	  else if ((rhs1_stmt == NULL || !TYPE_UNSIGNED (type1))
+-		   && (rhs2_stmt == NULL || !TYPE_UNSIGNED (type2))
+-		   && (optab_handler (smul_widen_optab, TYPE_MODE (type))
+-		       ->insn_code == CODE_FOR_nothing))
+-	    continue;
+-	  else if (rhs1_stmt != NULL && rhs2_stmt != 0
+-		   && (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2))
+-		   && (optab_handler (usmul_widen_optab, TYPE_MODE (type))
+-		       ->insn_code == CODE_FOR_nothing))
+-	    continue;
+-
+-	  if ((rhs1_stmt == NULL && !int_fits_type_p (rhs1, type2))
+-	      || (rhs2_stmt == NULL && !int_fits_type_p (rhs2, type1)))
+-	    continue;
+-
+-	  if (rhs1_stmt == NULL)
+-	    gimple_assign_set_rhs1 (stmt, fold_convert (type2, rhs1));
+-	  else
+-	    gimple_assign_set_rhs1 (stmt, rhs1_convop);
+-	  if (rhs2_stmt == NULL)
+-	    gimple_assign_set_rhs2 (stmt, fold_convert (type1, rhs2));
+-	  else
+-	    gimple_assign_set_rhs2 (stmt, rhs2_convop);
+-	  gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR);
+-	  update_stmt (stmt);
+-	  changed = true;
++	  code = gimple_assign_rhs_code (stmt);
++	  if (code == MULT_EXPR)
++	    changed |= convert_mult_to_widen (stmt);
++	  else if (code == PLUS_EXPR || code == MINUS_EXPR)
++	    changed |= convert_plusminus_to_widen (&gsi, stmt, code);
+ 	}
+     }
++
+   return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa
+ 	  | TODO_verify_stmts : 0);
+ }
+Index: gcc-4_5-branch/gcc/tree-ssa-operands.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-operands.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-ssa-operands.c	2011-07-22 16:59:28.611747691 -0700
+@@ -994,11 +994,13 @@
+ 
+     case DOT_PROD_EXPR:
+     case REALIGN_LOAD_EXPR:
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
+       {
+ 	get_expr_operands (stmt, &TREE_OPERAND (expr, 0), flags);
+-        get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags);
+-        get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags);
+-        return;
++	get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags);
++	get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags);
++	return;
+       }
+ 
+     case FUNCTION_DECL:
+Index: gcc-4_5-branch/gcc/tree-ssa-sccvn.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-sccvn.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-ssa-sccvn.c	2011-07-22 16:59:28.611747691 -0700
+@@ -2298,6 +2298,10 @@
+     case GIMPLE_BINARY_RHS:
+       return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt))
+ 	      || is_gimple_min_invariant (gimple_assign_rhs2 (stmt)));
++    case GIMPLE_TERNARY_RHS:
++      return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt))
++	      || is_gimple_min_invariant (gimple_assign_rhs2 (stmt))
++	      || is_gimple_min_invariant (gimple_assign_rhs3 (stmt)));
+     case GIMPLE_SINGLE_RHS:
+       /* Constants inside reference ops are rarely interesting, but
+ 	 it can take a lot of looking to find them.  */
+Index: gcc-4_5-branch/gcc/tree-ssa-threadedge.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-ssa-threadedge.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-ssa-threadedge.c	2011-07-22 16:59:28.611747691 -0700
+@@ -247,14 +247,14 @@
+ 
+         return fold (rhs);
+       }
+-      break;
++
+     case GIMPLE_UNARY_RHS:
+       {
+         tree lhs = gimple_assign_lhs (stmt);
+         tree op0 = gimple_assign_rhs1 (stmt);
+         return fold_unary (subcode, TREE_TYPE (lhs), op0);
+       }
+-      break;
++
+     case GIMPLE_BINARY_RHS:
+       {
+         tree lhs = gimple_assign_lhs (stmt);
+@@ -262,7 +262,16 @@
+         tree op1 = gimple_assign_rhs2 (stmt);
+         return fold_binary (subcode, TREE_TYPE (lhs), op0, op1);
+       }
+-      break;
++
++    case GIMPLE_TERNARY_RHS:
++      {
++        tree lhs = gimple_assign_lhs (stmt);
++        tree op0 = gimple_assign_rhs1 (stmt);
++        tree op1 = gimple_assign_rhs2 (stmt);
++        tree op2 = gimple_assign_rhs3 (stmt);
++        return fold_ternary (subcode, TREE_TYPE (lhs), op0, op1, op2);
++      }
++
+     default:
+       gcc_unreachable ();
+     }
+Index: gcc-4_5-branch/gcc/tree-vrp.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-vrp.c	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree-vrp.c	2011-07-22 16:59:28.621747691 -0700
+@@ -864,6 +864,8 @@
+ 					      gimple_assign_rhs1 (stmt),
+ 					      gimple_assign_rhs2 (stmt),
+ 					      strict_overflow_p);
++    case GIMPLE_TERNARY_RHS:
++      return false;
+     case GIMPLE_SINGLE_RHS:
+       return tree_single_nonnegative_warnv_p (gimple_assign_rhs1 (stmt),
+ 					      strict_overflow_p);
+@@ -935,6 +937,8 @@
+ 					  gimple_assign_rhs1 (stmt),
+ 					  gimple_assign_rhs2 (stmt),
+ 					  strict_overflow_p);
++    case GIMPLE_TERNARY_RHS:
++      return false;
+     case GIMPLE_SINGLE_RHS:
+       return tree_single_nonzero_warnv_p (gimple_assign_rhs1 (stmt),
+ 					  strict_overflow_p);
+Index: gcc-4_5-branch/gcc/tree.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree.c	2011-07-22 16:59:13.000000000 -0700
++++ gcc-4_5-branch/gcc/tree.c	2011-07-22 16:59:28.621747691 -0700
+@@ -6548,6 +6548,23 @@
+   return false;
+ }
+ 
++/* Return true if CODE represents a ternary tree code for which the
++   first two operands are commutative.  Otherwise return false.  */
++bool
++commutative_ternary_tree_code (enum tree_code code)
++{
++  switch (code)
++    {
++    case WIDEN_MULT_PLUS_EXPR:
++    case WIDEN_MULT_MINUS_EXPR:
++      return true;
++
++    default:
++      break;
++    }
++  return false;
++}
++
+ /* Generate a hash value for an expression.  This can be used iteratively
+    by passing a previous result as the VAL argument.
+ 
+Index: gcc-4_5-branch/gcc/tree.def
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree.def	2011-07-22 16:58:48.000000000 -0700
++++ gcc-4_5-branch/gcc/tree.def	2011-07-22 16:59:28.631747691 -0700
+@@ -1083,6 +1083,18 @@
+    the arguments from type t1 to type t2, and then multiplying them.  */
+ DEFTREECODE (WIDEN_MULT_EXPR, "widen_mult_expr", tcc_binary, 2)
+ 
++/* Widening multiply-accumulate.
++   The first two arguments are of type t1.
++   The third argument and the result are of type t2, such as t2 is at least
++   twice the size of t1.  t1 and t2 must be integral or fixed-point types.
++   The expression is equivalent to a WIDEN_MULT_EXPR operation
++   of the first two operands followed by an add or subtract of the third
++   operand.  */
++DEFTREECODE (WIDEN_MULT_PLUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3)
++/* This is like the above, except in the final expression the multiply result
++   is subtracted from t3.  */
++DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3)
++
+ /* Whole vector left/right shift in bits.
+    Operand 0 is a vector to be shifted.
+    Operand 1 is an integer shift amount in bits.  */
+Index: gcc-4_5-branch/gcc/tree.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree.h	2011-07-22 16:59:13.000000000 -0700
++++ gcc-4_5-branch/gcc/tree.h	2011-07-22 16:59:28.631747691 -0700
+@@ -4687,6 +4687,7 @@
+ extern int type_num_arguments (const_tree);
+ extern bool associative_tree_code (enum tree_code);
+ extern bool commutative_tree_code (enum tree_code);
++extern bool commutative_ternary_tree_code (enum tree_code);
+ extern tree upper_bound_in_type (tree, tree);
+ extern tree lower_bound_in_type (tree, tree);
+ extern int operand_equal_for_phi_arg_p (const_tree, const_tree);
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch
new file mode 100644
index 0000000000..e795d54e0f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch
@@ -0,0 +1,3565 @@
+2010-09-16  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2010-09-01  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/arm/neon-schedgen.ml (core): New type.
+	(allCores): List of supported cores.
+	(availability_table): Add supported cores.
+	(collate_bypasses): Accept core as a parameter.
+	(worst_case_latencies_and_bypasses): Accept core as a
+	 parameter.
+	(emit_insn_reservations): Accept core as a parameter.
+	Use tuneStr and coreStr to get tune attribute and prefix
+	for functional units.
+	(emit_bypasses): Accept core name and use it.
+	(calculate_per_core_availability_table): New.
+	(filter_core): New.
+	(calculate_core_availability_table): New.
+	(main): Use calculate_core_availablity_table.
+	* config/arm/cortex-a8-neon.md: Update copyright year.
+	Regenerated from ml file and merged in.
+	(neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and
+	cortex_a8_neon_mrc.
+
+	2010-09-10  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/arm/neon-schedgen.ml (allCores): Add support for
+	Cortex-A9.
+	* config/arm/cortex-a9-neon.md: New and partially generated.
+	* config/arm/cortex-a9.md (cortex_a9_dp): Adjust for Neon.
+
+ 2010-09-15  Chung-Lin Tang  <cltang@codesourcery.com>
+ 
+ 	Issue #9441
+
+=== modified file 'gcc/config/arm/cortex-a8-neon.md'
+--- old/gcc/config/arm/cortex-a8-neon.md	2009-02-20 15:20:38 +0000
++++ new/gcc/config/arm/cortex-a8-neon.md	2010-09-16 09:47:44 +0000
+@@ -182,12 +182,12 @@
+ 
+ ;; NEON -> core transfers.
+ 
+-(define_insn_reservation "neon_mrc" 20
++(define_insn_reservation "cortex_a8_neon_mrc" 20
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mrc"))
+   "cortex_a8_neon_ls")
+ 
+-(define_insn_reservation "neon_mrrc" 21
++(define_insn_reservation "cortex_a8_neon_mrrc" 21
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mrrc"))
+   "cortex_a8_neon_ls_2")
+@@ -196,48 +196,48 @@
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N3.
+-(define_insn_reservation "neon_int_1" 3
++(define_insn_reservation "cortex_a8_neon_int_1" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_int_1"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their (D|Q)m operands at N1,
+ ;; their (D|Q)n operands at N2, and produce a result at N3.
+-(define_insn_reservation "neon_int_2" 3
++(define_insn_reservation "cortex_a8_neon_int_2" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_int_2"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N3.
+-(define_insn_reservation "neon_int_3" 3
++(define_insn_reservation "cortex_a8_neon_int_3" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_int_3"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N4.
+-(define_insn_reservation "neon_int_4" 4
++(define_insn_reservation "cortex_a8_neon_int_4" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_int_4"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their (D|Q)m operands at N1,
+ ;; their (D|Q)n operands at N2, and produce a result at N4.
+-(define_insn_reservation "neon_int_5" 4
++(define_insn_reservation "cortex_a8_neon_int_5" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_int_5"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N4.
+-(define_insn_reservation "neon_vqneg_vqabs" 4
++(define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vqneg_vqabs"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation produce a result at N3.
+-(define_insn_reservation "neon_vmov" 3
++(define_insn_reservation "cortex_a8_neon_vmov" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vmov"))
+   "cortex_a8_neon_dp")
+@@ -245,7 +245,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N6.
+-(define_insn_reservation "neon_vaba" 6
++(define_insn_reservation "cortex_a8_neon_vaba" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vaba"))
+   "cortex_a8_neon_dp")
+@@ -253,35 +253,35 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N6 on cycle 2.
+-(define_insn_reservation "neon_vaba_qqq" 7
++(define_insn_reservation "cortex_a8_neon_vaba_qqq" 7
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vaba_qqq"))
+   "cortex_a8_neon_dp_2")
+ 
+ ;; Instructions using this reservation read their (D|Q)m operands at N1,
+ ;; their (D|Q)d operands at N3, and produce a result at N6.
+-(define_insn_reservation "neon_vsma" 6
++(define_insn_reservation "cortex_a8_neon_vsma" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vsma"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N6.
+-(define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
++(define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N6 on cycle 2.
+-(define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7
++(define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
+   "cortex_a8_neon_dp_2")
+ 
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
+-(define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
++(define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
+   "cortex_a8_neon_dp_2")
+@@ -289,7 +289,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
+ ;; produce a result at N6.
+-(define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
++(define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
+   "cortex_a8_neon_dp")
+@@ -297,7 +297,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
+ ;; produce a result at N6 on cycle 2.
+-(define_insn_reservation "neon_mla_qqq_8_16" 7
++(define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mla_qqq_8_16"))
+   "cortex_a8_neon_dp_2")
+@@ -305,7 +305,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N6 on cycle 2.
+-(define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
++(define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
+   "cortex_a8_neon_dp_2")
+@@ -313,21 +313,21 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N6 on cycle 4.
+-(define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9
++(define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
+   "cortex_a8_neon_dp_4")
+ 
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, and produce a result at N6.
+-(define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6
++(define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
+-(define_insn_reservation "neon_mul_qqd_32_scalar" 9
++(define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
+   "cortex_a8_neon_dp_4")
+@@ -335,84 +335,84 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N6.
+-(define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
++(define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N3.
+-(define_insn_reservation "neon_shift_1" 3
++(define_insn_reservation "cortex_a8_neon_shift_1" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_shift_1"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N4.
+-(define_insn_reservation "neon_shift_2" 4
++(define_insn_reservation "cortex_a8_neon_shift_2" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_shift_2"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N3 on cycle 2.
+-(define_insn_reservation "neon_shift_3" 4
++(define_insn_reservation "cortex_a8_neon_shift_3" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_shift_3"))
+   "cortex_a8_neon_dp_2")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N1.
+-(define_insn_reservation "neon_vshl_ddd" 1
++(define_insn_reservation "cortex_a8_neon_vshl_ddd" 1
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vshl_ddd"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N4 on cycle 2.
+-(define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5
++(define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
+   "cortex_a8_neon_dp_2")
+ 
+ ;; Instructions using this reservation read their (D|Q)m operands at N1,
+ ;; their (D|Q)d operands at N3, and produce a result at N6.
+-(define_insn_reservation "neon_vsra_vrsra" 6
++(define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vsra_vrsra"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N5.
+-(define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5
++(define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
+   "cortex_a8_neon_fadd")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N5 on cycle 2.
+-(define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6
++(define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
+   "cortex_a8_neon_fadd_2")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N5.
+-(define_insn_reservation "neon_fp_vsum" 5
++(define_insn_reservation "cortex_a8_neon_fp_vsum" 5
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vsum"))
+   "cortex_a8_neon_fadd")
+ 
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, and produce a result at N5.
+-(define_insn_reservation "neon_fp_vmul_ddd" 5
++(define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vmul_ddd"))
+   "cortex_a8_neon_dp")
+ 
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
+-(define_insn_reservation "neon_fp_vmul_qqd" 6
++(define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vmul_qqd"))
+   "cortex_a8_neon_dp_2")
+@@ -420,7 +420,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
+ ;; produce a result at N9.
+-(define_insn_reservation "neon_fp_vmla_ddd" 9
++(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vmla_ddd"))
+   "cortex_a8_neon_fmul_then_fadd")
+@@ -428,7 +428,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
+ ;; produce a result at N9 on cycle 2.
+-(define_insn_reservation "neon_fp_vmla_qqq" 10
++(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vmla_qqq"))
+   "cortex_a8_neon_fmul_then_fadd_2")
+@@ -436,7 +436,7 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N9.
+-(define_insn_reservation "neon_fp_vmla_ddd_scalar" 9
++(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
+   "cortex_a8_neon_fmul_then_fadd")
+@@ -444,869 +444,869 @@
+ ;; Instructions using this reservation read their (D|Q)n operands at N2,
+ ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
+ ;; produce a result at N9 on cycle 2.
+-(define_insn_reservation "neon_fp_vmla_qqq_scalar" 10
++(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
+   "cortex_a8_neon_fmul_then_fadd_2")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N9.
+-(define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9
++(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
+   "cortex_a8_neon_fmul_then_fadd")
+ 
+ ;; Instructions using this reservation read their source operands at N2, and
+ ;; produce a result at N9 on cycle 2.
+-(define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10
++(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
+   "cortex_a8_neon_fmul_then_fadd_2")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N2.
+-(define_insn_reservation "neon_bp_simple" 2
++(define_insn_reservation "cortex_a8_neon_bp_simple" 2
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_bp_simple"))
+   "cortex_a8_neon_perm")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N2 on cycle 2.
+-(define_insn_reservation "neon_bp_2cycle" 3
++(define_insn_reservation "cortex_a8_neon_bp_2cycle" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_bp_2cycle"))
+   "cortex_a8_neon_perm_2")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N2 on cycle 3.
+-(define_insn_reservation "neon_bp_3cycle" 4
++(define_insn_reservation "cortex_a8_neon_bp_3cycle" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_bp_3cycle"))
+   "cortex_a8_neon_perm_3")
+ 
+ ;; Instructions using this reservation produce a result at N1.
+-(define_insn_reservation "neon_ldr" 1
++(define_insn_reservation "cortex_a8_neon_ldr" 1
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_ldr"))
+   "cortex_a8_neon_ls")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_str" 0
++(define_insn_reservation "cortex_a8_neon_str" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_str"))
+   "cortex_a8_neon_ls")
+ 
+ ;; Instructions using this reservation produce a result at N1 on cycle 2.
+-(define_insn_reservation "neon_vld1_1_2_regs" 2
++(define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld1_1_2_regs"))
+   "cortex_a8_neon_ls_2")
+ 
+ ;; Instructions using this reservation produce a result at N1 on cycle 3.
+-(define_insn_reservation "neon_vld1_3_4_regs" 3
++(define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld1_3_4_regs"))
+   "cortex_a8_neon_ls_3")
+ 
+ ;; Instructions using this reservation produce a result at N2 on cycle 2.
+-(define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3
++(define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
+   "cortex_a8_neon_ls_2")
+ 
+ ;; Instructions using this reservation produce a result at N2 on cycle 3.
+-(define_insn_reservation "neon_vld2_4_regs" 4
++(define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld2_4_regs"))
+   "cortex_a8_neon_ls_3")
+ 
+ ;; Instructions using this reservation produce a result at N2 on cycle 4.
+-(define_insn_reservation "neon_vld3_vld4" 5
++(define_insn_reservation "cortex_a8_neon_vld3_vld4" 5
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld3_vld4"))
+   "cortex_a8_neon_ls_4")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0
++(define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
+   "cortex_a8_neon_ls_2")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_vst1_3_4_regs" 0
++(define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vst1_3_4_regs"))
+   "cortex_a8_neon_ls_3")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0
++(define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
+   "cortex_a8_neon_ls_4")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_vst3_vst4" 0
++(define_insn_reservation "cortex_a8_neon_vst3_vst4" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vst3_vst4"))
+   "cortex_a8_neon_ls_4")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N2 on cycle 3.
+-(define_insn_reservation "neon_vld1_vld2_lane" 4
++(define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld1_vld2_lane"))
+   "cortex_a8_neon_ls_3")
+ 
+ ;; Instructions using this reservation read their source operands at N1, and
+ ;; produce a result at N2 on cycle 5.
+-(define_insn_reservation "neon_vld3_vld4_lane" 6
++(define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld3_vld4_lane"))
+   "cortex_a8_neon_ls_5")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_vst1_vst2_lane" 0
++(define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vst1_vst2_lane"))
+   "cortex_a8_neon_ls_2")
+ 
+ ;; Instructions using this reservation read their source operands at N1.
+-(define_insn_reservation "neon_vst3_vst4_lane" 0
++(define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vst3_vst4_lane"))
+   "cortex_a8_neon_ls_3")
+ 
+ ;; Instructions using this reservation produce a result at N2 on cycle 2.
+-(define_insn_reservation "neon_vld3_vld4_all_lanes" 3
++(define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
+   "cortex_a8_neon_ls_3")
+ 
+ ;; Instructions using this reservation produce a result at N2.
+-(define_insn_reservation "neon_mcr" 2
++(define_insn_reservation "cortex_a8_neon_mcr" 2
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mcr"))
+   "cortex_a8_neon_perm")
+ 
+ ;; Instructions using this reservation produce a result at N2.
+-(define_insn_reservation "neon_mcr_2_mcrr" 2
++(define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "neon_type" "neon_mcr_2_mcrr"))
+   "cortex_a8_neon_perm_2")
+ 
+ ;; Exceptions to the default latencies.
+ 
+-(define_bypass 1 "neon_mcr_2_mcrr"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 1 "neon_mcr"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_vld3_vld4_all_lanes"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_vld3_vld4_lane"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_vld1_vld2_lane"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 4 "neon_vld3_vld4"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_vld2_4_regs"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_vld1_3_4_regs"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 1 "neon_vld1_1_2_regs"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 0 "neon_ldr"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_bp_3cycle"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_bp_2cycle"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 1 "neon_bp_simple"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 9 "neon_fp_vmla_qqq_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 8 "neon_fp_vmla_ddd_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 9 "neon_fp_vmla_qqq"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 8 "neon_fp_vmla_ddd"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_fp_vmul_qqd"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 4 "neon_fp_vmul_ddd"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 4 "neon_fp_vsum"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_fp_vadd_qqq_vabs_qq"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 4 "neon_fp_vadd_ddd_vabs_dd"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_vsra_vrsra"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 0 "neon_vshl_ddd"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_shift_3"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_shift_2"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_shift_1"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 8 "neon_mul_qqd_32_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 6 "neon_mla_qqq_8_16"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_vsma"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 6 "neon_vaba_qqq"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 5 "neon_vaba"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_vmov"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_vqneg_vqabs"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_int_5"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 3 "neon_int_4"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_int_3"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_int_2"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
+-
+-(define_bypass 2 "neon_int_1"
+-               "neon_int_1,\
+-               neon_int_4,\
+-               neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mul_qqq_8_16_32_ddd_32,\
+-               neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
+-               neon_mla_qqq_8_16,\
+-               neon_fp_vadd_ddd_vabs_dd,\
+-               neon_fp_vadd_qqq_vabs_qq,\
+-               neon_fp_vmla_ddd,\
+-               neon_fp_vmla_qqq,\
+-               neon_fp_vrecps_vrsqrts_ddd,\
+-               neon_fp_vrecps_vrsqrts_qqq")
++(define_bypass 1 "cortex_a8_neon_mcr_2_mcrr"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 1 "cortex_a8_neon_mcr"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_vld3_vld4_all_lanes"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_vld3_vld4_lane"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_vld1_vld2_lane"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a8_neon_vld3_vld4"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_vld2_4_regs"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_vld1_3_4_regs"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 1 "cortex_a8_neon_vld1_1_2_regs"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 0 "cortex_a8_neon_ldr"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_bp_3cycle"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_bp_2cycle"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 1 "cortex_a8_neon_bp_simple"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 9 "cortex_a8_neon_fp_vrecps_vrsqrts_qqq"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a8_neon_fp_vrecps_vrsqrts_ddd"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_fp_vmul_qqd"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a8_neon_fp_vmul_ddd"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a8_neon_fp_vsum"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_fp_vadd_qqq_vabs_qq"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a8_neon_fp_vadd_ddd_vabs_dd"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_vsra_vrsra"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 0 "cortex_a8_neon_vshl_ddd"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_shift_3"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_shift_2"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_shift_1"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a8_neon_mul_qqd_32_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a8_neon_mla_qqq_32_qqd_32_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a8_neon_mla_qqq_8_16"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a8_neon_mul_qqq_8_16_32_ddd_32"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_vsma"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a8_neon_vaba_qqq"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a8_neon_vaba"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_vmov"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_vqneg_vqabs"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_int_5"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a8_neon_int_4"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_int_3"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_int_2"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a8_neon_int_1"
++               "cortex_a8_neon_int_1,\
++               cortex_a8_neon_int_4,\
++               cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a8_neon_mla_qqq_8_16,\
++               cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a8_neon_fp_vmla_ddd,\
++               cortex_a8_neon_fp_vmla_qqq,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
+ 
+
+=== added file 'gcc/config/arm/cortex-a9-neon.md'
+--- old/gcc/config/arm/cortex-a9-neon.md	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/cortex-a9-neon.md	2010-09-16 09:47:44 +0000
+@@ -0,0 +1,1237 @@
++;; ARM Cortex-A9 pipeline description
++;; Copyright (C) 2010 Free Software Foundation, Inc.
++;;
++;; Neon pipeline description contributed by ARM Ltd.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++
++
++(define_automaton "cortex_a9_neon")
++
++;; Only one instruction can be issued per cycle.
++(define_cpu_unit "cortex_a9_neon_issue_perm" "cortex_a9_neon")
++
++;; Only one data-processing instruction can be issued per cycle.
++(define_cpu_unit "cortex_a9_neon_issue_dp" "cortex_a9_neon")
++
++;; We need a special mutual exclusion (to be used in addition to
++;; cortex_a9_neon_issue_dp) for the case when an instruction such as
++;; vmla.f is forwarded from E5 of the floating-point multiply pipeline to
++;; E2 of the floating-point add pipeline.  On the cycle previous to that
++;; forward we must prevent issue of any instruction to the floating-point
++;; add pipeline, but still allow issue of a data-processing instruction
++;; to any of the other pipelines.
++(define_cpu_unit "cortex_a9_neon_issue_fadd" "cortex_a9_neon")
++(define_cpu_unit "cortex_a9_neon_mcr" "cortex_a9_neon")
++
++
++;; Patterns of reservation.
++;; We model the NEON issue units as running in parallel with the core ones.
++;; We assume that multi-cycle NEON instructions get decomposed into
++;; micro-ops as they are issued into the NEON pipeline.
++
++(define_reservation "cortex_a9_neon_dp"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp")
++(define_reservation "cortex_a9_neon_dp_2"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
++                     cortex_a9_neon_issue_dp")
++(define_reservation "cortex_a9_neon_dp_4"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
++                     cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp")
++
++(define_reservation "cortex_a9_neon_fadd"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp +  \
++                     cortex_a9_neon_issue_fadd")
++(define_reservation "cortex_a9_neon_fadd_2"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
++                     cortex_a9_neon_issue_fadd,\
++                     cortex_a9_neon_issue_dp")
++
++(define_reservation "cortex_a9_neon_perm"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm")
++(define_reservation "cortex_a9_neon_perm_2"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,  \
++                     cortex_a9_neon_issue_perm")
++(define_reservation "cortex_a9_neon_perm_3"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_perm")
++
++(define_reservation "cortex_a9_neon_ls"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm+cortex_a9_ls")
++(define_reservation "cortex_a9_neon_ls_2"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_perm")
++(define_reservation "cortex_a9_neon_ls_3"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_perm")
++(define_reservation "cortex_a9_neon_ls_4"
++                    "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_perm")
++(define_reservation "cortex_a9_neon_ls_5"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
++                     cortex_a9_neon_issue_perm")
++
++(define_reservation "cortex_a9_neon_fmul_then_fadd"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
++		     nothing*3,\
++		     cortex_a9_neon_issue_fadd")
++(define_reservation "cortex_a9_neon_fmul_then_fadd_2"
++                    "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
++		     cortex_a9_neon_issue_dp,\
++		     nothing*2,\
++		     cortex_a9_neon_issue_fadd,\
++		     cortex_a9_neon_issue_fadd")
++
++
++;; NEON -> core transfers.
++(define_insn_reservation "ca9_neon_mrc" 1
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mrc"))
++  "ca9_issue_vfp_neon + cortex_a9_neon_mcr")
++
++(define_insn_reservation "ca9_neon_mrrc" 1
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mrrc"))
++  "ca9_issue_vfp_neon + cortex_a9_neon_mcr")
++
++;; The remainder of this file is auto-generated by neon-schedgen.
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N3.
++(define_insn_reservation "cortex_a9_neon_int_1" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_int_1"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)m operands at N1,
++;; their (D|Q)n operands at N2, and produce a result at N3.
++(define_insn_reservation "cortex_a9_neon_int_2" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_int_2"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N3.
++(define_insn_reservation "cortex_a9_neon_int_3" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_int_3"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N4.
++(define_insn_reservation "cortex_a9_neon_int_4" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_int_4"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)m operands at N1,
++;; their (D|Q)n operands at N2, and produce a result at N4.
++(define_insn_reservation "cortex_a9_neon_int_5" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_int_5"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N4.
++(define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vqneg_vqabs"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation produce a result at N3.
++(define_insn_reservation "cortex_a9_neon_vmov" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vmov"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_vaba" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vaba"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N6 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_vaba_qqq" 7
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vaba_qqq"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)m operands at N1,
++;; their (D|Q)d operands at N3, and produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_vsma" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vsma"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N6 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
++;; produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
++;; produce a result at N6 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mla_qqq_8_16"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N6 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N6 on cycle 4.
++(define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
++  "cortex_a9_neon_dp_4")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, and produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
++(define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
++  "cortex_a9_neon_dp_4")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N3.
++(define_insn_reservation "cortex_a9_neon_shift_1" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_shift_1"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N4.
++(define_insn_reservation "cortex_a9_neon_shift_2" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_shift_2"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N3 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_shift_3" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_shift_3"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N1.
++(define_insn_reservation "cortex_a9_neon_vshl_ddd" 1
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vshl_ddd"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N4 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)m operands at N1,
++;; their (D|Q)d operands at N3, and produce a result at N6.
++(define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vsra_vrsra"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N5.
++(define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
++  "cortex_a9_neon_fadd")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N5 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
++  "cortex_a9_neon_fadd_2")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N5.
++(define_insn_reservation "cortex_a9_neon_fp_vsum" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vsum"))
++  "cortex_a9_neon_fadd")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, and produce a result at N5.
++(define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vmul_ddd"))
++  "cortex_a9_neon_dp")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vmul_qqd"))
++  "cortex_a9_neon_dp_2")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
++;; produce a result at N9.
++(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vmla_ddd"))
++  "cortex_a9_neon_fmul_then_fadd")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
++;; produce a result at N9 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vmla_qqq"))
++  "cortex_a9_neon_fmul_then_fadd_2")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N9.
++(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
++  "cortex_a9_neon_fmul_then_fadd")
++
++;; Instructions using this reservation read their (D|Q)n operands at N2,
++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
++;; produce a result at N9 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
++  "cortex_a9_neon_fmul_then_fadd_2")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N9.
++(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
++  "cortex_a9_neon_fmul_then_fadd")
++
++;; Instructions using this reservation read their source operands at N2, and
++;; produce a result at N9 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
++  "cortex_a9_neon_fmul_then_fadd_2")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N2.
++(define_insn_reservation "cortex_a9_neon_bp_simple" 2
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_bp_simple"))
++  "cortex_a9_neon_perm")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N2 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_bp_2cycle" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_bp_2cycle"))
++  "cortex_a9_neon_perm_2")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N2 on cycle 3.
++(define_insn_reservation "cortex_a9_neon_bp_3cycle" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_bp_3cycle"))
++  "cortex_a9_neon_perm_3")
++
++;; Instructions using this reservation produce a result at N1.
++(define_insn_reservation "cortex_a9_neon_ldr" 1
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_ldr"))
++  "cortex_a9_neon_ls")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_str" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_str"))
++  "cortex_a9_neon_ls")
++
++;; Instructions using this reservation produce a result at N1 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld1_1_2_regs"))
++  "cortex_a9_neon_ls_2")
++
++;; Instructions using this reservation produce a result at N1 on cycle 3.
++(define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld1_3_4_regs"))
++  "cortex_a9_neon_ls_3")
++
++;; Instructions using this reservation produce a result at N2 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
++  "cortex_a9_neon_ls_2")
++
++;; Instructions using this reservation produce a result at N2 on cycle 3.
++(define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld2_4_regs"))
++  "cortex_a9_neon_ls_3")
++
++;; Instructions using this reservation produce a result at N2 on cycle 4.
++(define_insn_reservation "cortex_a9_neon_vld3_vld4" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld3_vld4"))
++  "cortex_a9_neon_ls_4")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
++  "cortex_a9_neon_ls_2")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vst1_3_4_regs"))
++  "cortex_a9_neon_ls_3")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
++  "cortex_a9_neon_ls_4")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_vst3_vst4" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vst3_vst4"))
++  "cortex_a9_neon_ls_4")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N2 on cycle 3.
++(define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld1_vld2_lane"))
++  "cortex_a9_neon_ls_3")
++
++;; Instructions using this reservation read their source operands at N1, and
++;; produce a result at N2 on cycle 5.
++(define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld3_vld4_lane"))
++  "cortex_a9_neon_ls_5")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vst1_vst2_lane"))
++  "cortex_a9_neon_ls_2")
++
++;; Instructions using this reservation read their source operands at N1.
++(define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vst3_vst4_lane"))
++  "cortex_a9_neon_ls_3")
++
++;; Instructions using this reservation produce a result at N2 on cycle 2.
++(define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
++  "cortex_a9_neon_ls_3")
++
++;; Instructions using this reservation produce a result at N2.
++(define_insn_reservation "cortex_a9_neon_mcr" 2
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mcr"))
++  "cortex_a9_neon_perm")
++
++;; Instructions using this reservation produce a result at N2.
++(define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "neon_type" "neon_mcr_2_mcrr"))
++  "cortex_a9_neon_perm_2")
++
++;; Exceptions to the default latencies.
++
++(define_bypass 1 "cortex_a9_neon_mcr_2_mcrr"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 1 "cortex_a9_neon_mcr"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_vld3_vld4_all_lanes"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_vld3_vld4_lane"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_vld1_vld2_lane"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a9_neon_vld3_vld4"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_vld2_4_regs"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_vld1_3_4_regs"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 1 "cortex_a9_neon_vld1_1_2_regs"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 0 "cortex_a9_neon_ldr"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_bp_3cycle"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_bp_2cycle"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 1 "cortex_a9_neon_bp_simple"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 9 "cortex_a9_neon_fp_vrecps_vrsqrts_qqq"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a9_neon_fp_vrecps_vrsqrts_ddd"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_fp_vmul_qqd"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a9_neon_fp_vmul_ddd"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a9_neon_fp_vsum"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_fp_vadd_qqq_vabs_qq"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a9_neon_fp_vadd_ddd_vabs_dd"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_vsra_vrsra"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 4 "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 0 "cortex_a9_neon_vshl_ddd"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_shift_3"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_shift_2"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_shift_1"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a9_neon_mul_qqd_32_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 8 "cortex_a9_neon_mla_qqq_32_qqd_32_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a9_neon_mla_qqq_8_16"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a9_neon_mul_qqq_8_16_32_ddd_32"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_vsma"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 6 "cortex_a9_neon_vaba_qqq"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 5 "cortex_a9_neon_vaba"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_vmov"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_vqneg_vqabs"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_int_5"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 3 "cortex_a9_neon_int_4"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_int_3"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_int_2"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
++(define_bypass 2 "cortex_a9_neon_int_1"
++               "cortex_a9_neon_int_1,\
++               cortex_a9_neon_int_4,\
++               cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
++               cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
++               cortex_a9_neon_mla_qqq_8_16,\
++               cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
++               cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
++               cortex_a9_neon_fp_vmla_ddd,\
++               cortex_a9_neon_fp_vmla_qqq,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
++               cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
++
+
+=== modified file 'gcc/config/arm/cortex-a9.md'
+--- old/gcc/config/arm/cortex-a9.md	2010-08-24 13:15:54 +0000
++++ new/gcc/config/arm/cortex-a9.md	2010-09-16 09:47:44 +0000
+@@ -80,8 +80,9 @@
+ (define_insn_reservation "cortex_a9_dp" 2
+   (and (eq_attr "tune" "cortexa9")
+        (ior (eq_attr "type" "alu")
+-	    (and (eq_attr "type" "alu_shift_reg, alu_shift")
+-		 (eq_attr "insn" "mov"))))
++	    (ior (and (eq_attr "type" "alu_shift_reg, alu_shift")
++		 (eq_attr "insn" "mov"))
++		 (eq_attr "neon_type" "none"))))
+   "cortex_a9_p0_default|cortex_a9_p1_default")
+ 
+ ;; An instruction using the shifter will go down E1.
+
+=== modified file 'gcc/config/arm/neon-schedgen.ml'
+--- old/gcc/config/arm/neon-schedgen.ml	2010-04-02 18:54:46 +0000
++++ new/gcc/config/arm/neon-schedgen.ml	2010-09-16 09:47:44 +0000
+@@ -1,7 +1,6 @@
+ (* Emission of the core of the Cortex-A8 NEON scheduling description.
+    Copyright (C) 2007, 2010 Free Software Foundation, Inc.
+    Contributed by CodeSourcery.
+-
+    This file is part of GCC.
+ 
+    GCC is free software; you can redistribute it and/or modify it under
+@@ -21,7 +20,14 @@
+ 
+ (* This scheduling description generator works as follows.
+    - Each group of instructions has source and destination requirements
+-     specified.  The source requirements may be specified using
++     specified and a list of cores supported. This is then filtered
++     and per core scheduler descriptions are generated out.
++     The reservations generated are prefixed by the name of the
++     core and the check is performed on the basis of what the tuning
++     string is. Running this will generate Neon scheduler descriptions
++     for all cores supported.
++
++     The source requirements may be specified using
+      Source (the stage at which all source operands not otherwise
+      described are read), Source_m (the stage at which Rm operands are
+      read), Source_n (likewise for Rn) and Source_d (likewise for Rd).
+@@ -83,6 +89,17 @@
+ | Ls of int
+ | Fmul_then_fadd | Fmul_then_fadd_2
+ 
++type core = CortexA8 | CortexA9
++let allCores = [CortexA8; CortexA9]
++let coreStr = function
++    CortexA8 -> "cortex_a8"
++  | CortexA9 -> "cortex_a9"
++
++let tuneStr = function
++    CortexA8 -> "cortexa8"
++   | CortexA9 -> "cortexa9"
++
++
+ (* This table must be kept as short as possible by conflating
+    entries with the same availability behavior.
+ 
+@@ -90,129 +107,136 @@
+    Second components: availability requirements, in the order in which
+    they should appear in the comments in the .md file.
+    Third components: reservation info
++   Fourth components: List of supported cores.
+ *)
+ let availability_table = [
+   (* NEON integer ALU instructions.  *)
+   (* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr
+      veor vbic vorn ddd qqq *)
+-  "neon_int_1", [Source n2; Dest n3], ALU;
++  "neon_int_1", [Source n2; Dest n3], ALU, allCores;
+   (* vadd vsub qqd vsub ddd qqq *)
+-  "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU;
++  "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU, allCores;
+   (* vsum vneg dd qq vadd vsub qdd *)
+-  "neon_int_3", [Source n1; Dest n3], ALU;
++  "neon_int_3", [Source n1; Dest n3], ALU, allCores;
+   (* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *)
+   (* vhadd vrhadd vqadd vtst ddd qqq *)
+-  "neon_int_4", [Source n2; Dest n4], ALU;
++  "neon_int_4", [Source n2; Dest n4], ALU, allCores;
+   (* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *)
+-  "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU;
++  "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU, allCores;
+   (* vqneg vqabs dd qq *)
+-  "neon_vqneg_vqabs", [Source n1; Dest n4], ALU;
++  "neon_vqneg_vqabs", [Source n1; Dest n4], ALU, allCores;
+   (* vmov vmvn *)
+-  "neon_vmov", [Dest n3], ALU;
++  "neon_vmov", [Dest n3], ALU, allCores;
+   (* vaba *)
+-  "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU;
++  "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU, allCores;
+   "neon_vaba_qqq",
+-    [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle;
++    [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], 
++   ALU_2cycle, allCores;
+   (* vsma *)
+-  "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU;
++  "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU, allCores;
+ 
+   (* NEON integer multiply instructions.  *)
+   (* vmul, vqdmlh, vqrdmlh *)
+   (* vmul, vqdmul, qdd 16/8 long 32/16 long *)
+-  "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul;
+-  "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle;
++  "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], 
++   Mul, allCores;
++  "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], 
++   Mul_2cycle, allCores;
+   (* vmul, vqdmul again *)
+   "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar",
+-    [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle;
++    [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle, allCores;
+   (* vmla, vmls *)
+   "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long",
+-    [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul;
++    [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul, allCores;
+   "neon_mla_qqq_8_16",
+-    [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
++    [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], 
++   Mul_2cycle, allCores;
+   "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long",
+-    [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
++    [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], 
++   Mul_2cycle, allCores;
+   "neon_mla_qqq_32_qqd_32_scalar",
+-    [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle;
++    [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], 
++   Mul_4cycle, allCores;
+   (* vmul, vqdmulh, vqrdmulh *)
+   (* vmul, vqdmul *)
+   "neon_mul_ddd_16_scalar_32_16_long_scalar",
+-    [Source_n n2; Source_m n1; Dest n6], Mul;
++    [Source_n n2; Source_m n1; Dest n6], Mul, allCores;
+   "neon_mul_qqd_32_scalar",
+-    [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle;
++    [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle, allCores;
+   (* vmla, vmls *)
+   (* vmla, vmla, vqdmla, vqdmls *)
+   "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar",
+-    [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul;
++    [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul, allCores;
+ 
+   (* NEON integer shift instructions.  *)
+   (* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *)
+-  "neon_shift_1", [Source n1; Dest n3], Shift;
+-  (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow;
++  "neon_shift_1", [Source n1; Dest n3], Shift, allCores;
++  (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow, allCores;
+      vqshl_vrshl_vqrshl_ddd *)
+-  "neon_shift_2", [Source n1; Dest n4], Shift;
++  "neon_shift_2", [Source n1; Dest n4], Shift, allCores;
+   (* vsli, vsri and vshl for qqq *)
+-  "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle;
+-  "neon_vshl_ddd", [Source n1; Dest n1], Shift;
++  "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle, allCores;
++  "neon_vshl_ddd", [Source n1; Dest n1], Shift, allCores;
+   "neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)],
+-    Shift_2cycle;
+-  "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift;
++    Shift_2cycle, allCores;
++  "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift, allCores;
+ 
+   (* NEON floating-point instructions.  *)
+   (* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *)
+   (* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *)
+-  "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd;
++  "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd, allCores;
+   "neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)],
+-    Fadd_2cycle;
++    Fadd_2cycle, allCores;
+   (* vsum, fvmx, vfmn *)
+-  "neon_fp_vsum", [Source n1; Dest n5], Fadd;
+-  "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul;
++  "neon_fp_vsum", [Source n1; Dest n5], Fadd, allCores;
++  "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul, allCores;
+   "neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)],
+-    Fmul_2cycle;
++    Fmul_2cycle, allCores;
+   (* vmla, vmls *)
+   "neon_fp_vmla_ddd",
+-    [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd;
++    [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd, allCores;
+   "neon_fp_vmla_qqq",
+     [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)],
+-    Fmul_then_fadd_2;
++    Fmul_then_fadd_2, allCores;
+   "neon_fp_vmla_ddd_scalar",
+-    [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd;
++    [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd, allCores;
+   "neon_fp_vmla_qqq_scalar",
+     [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)],
+-    Fmul_then_fadd_2;
+-  "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd;
++    Fmul_then_fadd_2, allCores;
++  "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd, allCores;
+   "neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)],
+-    Fmul_then_fadd_2;
++    Fmul_then_fadd_2, allCores;
+ 
+   (* NEON byte permute instructions.  *)
+   (* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *)
+-  "neon_bp_simple", [Source n1; Dest n2], Permute 1;
+-  (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1};
++  "neon_bp_simple", [Source n1; Dest n2], Permute 1, allCores;
++  (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}, allCores;
+      similarly for vtbx *)
+-  "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2;
++  "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2, allCores;
+   (* all the rest *)
+-  "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3;
++  "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3, allCores;
+ 
+   (* NEON load/store instructions.  *)
+-  "neon_ldr", [Dest n1], Ls 1;
+-  "neon_str", [Source n1], Ls 1;
+-  "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2;
+-  "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3;
+-  "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2;
+-  "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3;
+-  "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4;
+-  "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2;
+-  "neon_vst1_3_4_regs", [Source n1], Ls 3;
+-  "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4;
+-  "neon_vst3_vst4", [Source n1], Ls 4;
+-  "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3;
+-  "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5;
+-  "neon_vst1_vst2_lane", [Source n1], Ls 2;
+-  "neon_vst3_vst4_lane", [Source n1], Ls 3;
+-  "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3;
++  "neon_ldr", [Dest n1], Ls 1, allCores;
++  "neon_str", [Source n1], Ls 1, allCores;
++  "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2, allCores;
++  "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3, allCores;
++  "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2, allCores;
++  "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3, allCores;
++  "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4, allCores;
++  "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2, allCores;
++  "neon_vst1_3_4_regs", [Source n1], Ls 3, allCores;
++  "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4, allCores;
++  "neon_vst3_vst4", [Source n1], Ls 4, allCores;
++  "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3, allCores;
++  "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5, allCores;
++  "neon_vst1_vst2_lane", [Source n1], Ls 2, allCores;
++  "neon_vst3_vst4_lane", [Source n1], Ls 3, allCores;
++  "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3, allCores;
+ 
+   (* NEON register transfer instructions.  *)
+-  "neon_mcr", [Dest n2], Permute 1;
+-  "neon_mcr_2_mcrr", [Dest n2], Permute 2;
++  "neon_mcr", [Dest n2], Permute 1, allCores;
++  "neon_mcr_2_mcrr", [Dest n2], Permute 2, allCores;
+   (* MRC instructions are in the .tpl file.  *)
+ ]
+ 
+@@ -221,7 +245,7 @@
+    required.  (It is also possible that an entry in the table has no
+    source requirements.)  *)
+ let calculate_sources =
+-  List.map (fun (name, avail, res) ->
++  List.map (fun (name, avail, res, cores) ->
+               let earliest_stage =
+                 List.fold_left
+                   (fun cur -> fun info ->
+@@ -331,7 +355,7 @@
+    of one bypass from this producer to any particular consumer listed
+    in LATENCIES.)  Use a hash table to collate bypasses with the
+    same latency and guard.  *)
+-let collate_bypasses (producer_name, _, _, _) largest latencies =
++let collate_bypasses (producer_name, _, _, _) largest latencies core =
+   let ht = Hashtbl.create 42 in
+   let keys = ref [] in
+     List.iter (
+@@ -350,7 +374,7 @@
+               (if (try ignore (Hashtbl.find ht (guard, latency)); false
+                    with Not_found -> true) then
+                  keys := (guard, latency) :: !keys);
+-              Hashtbl.add ht (guard, latency) consumer
++              Hashtbl.add ht (guard, latency) ((coreStr core) ^ "_" ^ consumer)
+             end
+     ) latencies;
+     (* The hash table now has bypasses collated so that ones with the
+@@ -372,7 +396,7 @@
+    the output in such a way that all bypasses with the same producer
+    and latency are together, and so that bypasses with the worst-case
+    latency are ignored.  *)
+-let worst_case_latencies_and_bypasses =
++let worst_case_latencies_and_bypasses core =
+   let rec f (worst_acc, bypasses_acc) prev xs =
+     match xs with
+       [] -> (worst_acc, bypasses_acc)
+@@ -400,7 +424,7 @@
+           (* Having got the largest latency, collect all bypasses for
+              this producer and filter out those with that larger
+              latency.  Record the others for later emission.  *)
+-          let bypasses = collate_bypasses producer largest latencies in
++          let bypasses = collate_bypasses producer largest latencies core in
+             (* Go on to process remaining producers, having noted
+                the result for this one.  *)
+             f ((producer_name, producer_avail, largest,
+@@ -444,14 +468,18 @@
+     in
+       f avail 0
+ 
++
+ (* Emit a define_insn_reservation for each producer.  The latency
+    written in will be its worst-case latency.  *)
+-let emit_insn_reservations =
+-  List.iter (
++let emit_insn_reservations core =
++  let corestring = coreStr core in
++  let tunestring = tuneStr core
++  in  List.iter (
+      fun (producer, avail, latency, reservation) ->
+         write_comment producer avail;
+-        Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency;
+-        Printf.printf "  (and (eq_attr \"tune\" \"cortexa8\")\n";
++        Printf.printf "(define_insn_reservation \"%s_%s\" %d\n" 
++            corestring producer latency;
++            Printf.printf "  (and (eq_attr \"tune\" \"%s\")\n" tunestring;
+         Printf.printf "       (eq_attr \"neon_type\" \"%s\"))\n" producer;
+         let str =
+           match reservation with
+@@ -467,7 +495,7 @@
+ 	  | Fmul_then_fadd -> "fmul_then_fadd"
+ 	  | Fmul_then_fadd_2 -> "fmul_then_fadd_2"
+         in
+-          Printf.printf "  \"cortex_a8_neon_%s\")\n\n" str
++          Printf.printf "  \"%s_neon_%s\")\n\n" corestring str
+     )
+ 
+ (* Given a guard description, return the name of the C function to
+@@ -480,10 +508,12 @@
+   | Guard_none -> assert false
+ 
+ (* Emit a define_bypass for each bypass.  *)
+-let emit_bypasses =
++let emit_bypasses core =
+   List.iter (
+       fun (producer, consumers, latency, guard) ->
+-        Printf.printf "(define_bypass %d \"%s\"\n" latency producer;
++        Printf.printf "(define_bypass %d \"%s_%s\"\n" 
++	latency (coreStr core) producer;
++
+         if guard = Guard_none then
+           Printf.printf "               \"%s\")\n\n" consumers
+         else
+@@ -493,11 +523,21 @@
+           end
+     )
+ 
++
++let calculate_per_core_availability_table core availability_table =
++  let table = calculate_sources availability_table in
++  let worst_cases, bypasses = worst_case_latencies_and_bypasses core table in
++    emit_insn_reservations core (List.rev worst_cases);
++    Printf.printf ";; Exceptions to the default latencies.\n\n";
++    emit_bypasses core bypasses
++
++let calculate_core_availability_table core availability_table =
++let filter_core = List.filter (fun (_, _, _, cores) 
++				   -> List.exists ((=) core) cores)
++in calculate_per_core_availability_table core (filter_core availability_table)
++
++
+ (* Program entry point.  *)
+ let main =
+-  let table = calculate_sources availability_table in
+-  let worst_cases, bypasses = worst_case_latencies_and_bypasses table in
+-    emit_insn_reservations (List.rev worst_cases);
+-    Printf.printf ";; Exceptions to the default latencies.\n\n";
+-    emit_bypasses bypasses
+-
++  List.map (fun core -> calculate_core_availability_table 
++		core availability_table) allCores
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch
new file mode 100644
index 0000000000..c332d50fa1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch
@@ -0,0 +1,76 @@
+2010-09-21  Yao Qi  <yao@codesourcery.com>
+
+	Backport from FSF to fix ICE found in LP:635409:
+	
+	2010-07-07  Bernd Schmidt  <bernds@codesourcery.com>
+	
+	gcc/
+	PR rtl-optimization/44787
+	* config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2.
+	* config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise.
+	
+	gcc/testsuite/
+	PR rtl-optimization/44787
+	* gcc.c-torture/compile/pr44788.c: New test.
+	* gcc.target/arm/pr44788.c: New test.
+	
+ 2010-09-16  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from FSF:
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-09-16 09:15:46 +0000
++++ new/gcc/config/arm/arm.md	2010-09-22 05:54:42 +0000
+@@ -9268,7 +9268,7 @@
+           [(match_operator:SI 3 "shift_operator"
+              [(match_operand:SI 4 "s_register_operand" "r")
+               (match_operand:SI 5 "reg_or_int_operand" "rI")])
+-           (match_operand:SI 2 "s_register_operand" "r")]))]
++           (match_operand:SI 2 "s_register_operand" "rk")]))]
+   "TARGET_ARM"
+   "%i1%?\\t%0, %2, %4%S3"
+   [(set_attr "predicable" "yes")
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-09-01 13:29:58 +0000
++++ new/gcc/config/arm/thumb2.md	2010-09-22 05:54:42 +0000
+@@ -467,7 +467,7 @@
+           [(match_operator:SI 3 "shift_operator"
+              [(match_operand:SI 4 "s_register_operand" "r")
+               (match_operand:SI 5 "const_shift_count" "M")])
+-           (match_operand:SI 2 "s_register_operand" "r")]))]
++           (match_operand:SI 2 "s_register_operand" "rk")]))]
+   "TARGET_THUMB2"
+   "%i1%?\\t%0, %2, %4%S3"
+   [(set_attr "predicable" "yes")
+
+=== added file 'gcc/testsuite/gcc.c-torture/compile/pr44788.c'
+--- old/gcc/testsuite/gcc.c-torture/compile/pr44788.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/compile/pr44788.c	2010-09-22 05:54:42 +0000
+@@ -0,0 +1,8 @@
++void joint_decode(float* mlt_buffer1, int t) {
++    int i;
++    float decode_buffer[1060];
++    foo(decode_buffer);
++    for (i=0; i<10 ; i++) {
++        mlt_buffer1[i] = i * decode_buffer[t];
++    }
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr44788.c'
+--- old/gcc/testsuite/gcc.target/arm/pr44788.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr44788.c	2010-09-22 05:54:42 +0000
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
++
++void joint_decode(float* mlt_buffer1, int t) {
++    int i;
++    float decode_buffer[1060];
++    foo(decode_buffer);
++    for (i=0; i<10 ; i++) {
++        mlt_buffer1[i] = i * decode_buffer[t];
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99402.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99402.patch
new file mode 100644
index 0000000000..6627a11d4a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99402.patch
@@ -0,0 +1,1268 @@
+2010-09-17  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-07-15  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (last_label_ruid, first_index_reg, last_index_reg):
+	New static variables.
+	(reload_combine_recognize_pattern): New static function, broken out
+	of reload_combine.
+	(reload_combine): Use it.  Only initialize first_index_reg and
+	last_index_reg once.
+
+	2010-07-17  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/42235
+	gcc/
+	* postreload.c (reload_cse_move2add): Return bool, true if anything.
+	changed.  All callers changed.
+	(move2add_use_add2_insn): Likewise.
+	(move2add_use_add3_insn): Likewise.
+	(reload_cse_regs): If reload_cse_move2add changed anything, rerun
+	reload_combine.
+	(RELOAD_COMBINE_MAX_USES): Bump to 16.
+	(last_jump_ruid): New static variable.
+	(struct reg_use): New members CONTAINING_MEM and RUID.
+	(reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID.
+	(reload_combine_split_one_ruid, reload_combine_split_ruids,
+	reload_combine_purge_insn_uses, reload_combine_closest_single_use
+	reload_combine_purge_reg_uses_after_ruid,
+	reload_combine_recognize_const_pattern): New static functions.
+	(reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH
+	is true for our reg and that we have available index regs.
+	(reload_combine_note_use): New args RUID and CONTAINING_MEM.  All
+	callers changed.  Use them to initialize fields in struct reg_use.
+	(reload_combine): Initialize last_jump_ruid.  Be careful when to
+	take PREV_INSN of the scanned insn.  Update REAL_STORE_RUID fields.
+	Call reload_combine_recognize_const_pattern.
+	(reload_combine_note_store): Update REAL_STORE_RUID field.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42235.c: New test.
+
+	2010-07-19  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (reload_combine_closest_single_use): Ignore the
+	number of uses for DEBUG_INSNs.
+	(fixup_debug_insns): New static function.
+	(reload_combine_recognize_const_pattern): Use it.  Don't let the
+	main loop be affected by DEBUG_INSNs.
+	Really disallow moving adds past a jump insn.
+	(reload_combine_recognize_pattern): Don't update use_ruid here.
+	(reload_combine_note_use): Do it here.
+	(reload_combine): Use control_flow_insn_p rather than JUMP_P.
+
+	2010-07-20  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (fixup_debug_insns): Remove arg REGNO.  New args
+	FROM and TO.  All callers changed.  Don't look for tracked uses,
+	just scan the RTL for DEBUG_INSNs and substitute.
+	(reload_combine_recognize_pattern): Call fixup_debug_insns.
+	(reload_combine): Ignore DEBUG_INSNs.
+
+	2010-07-22  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR bootstrap/44970
+	PR middle-end/45009
+	gcc/
+	* postreload.c: Include "target.h".
+	(reload_combine_closest_single_use): Don't take DEBUG_INSNs
+	into account.
+	(fixup_debug_insns): Don't copy the rtx.
+	(reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses.
+	Don't copy when replacing.  Call fixup_debug_insns in the case where
+	we merged one add with another.
+	(reload_combine_recognize_pattern): Fail if there aren't any uses.
+	Try harder to determine whether we're picking a valid index register.
+	Don't set store_ruid for an insn we're going to scan in the
+	next iteration.
+	(reload_combine): Remove unused code.
+	(reload_combine_note_use): When updating use information for
+	an old insn, ignore a use that occurs after store_ruid.
+	* Makefile.in (postreload.o): Update dependencies.
+
+	2010-07-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (reload_combine_recognize_const_pattern): Move test
+	for limiting the insn movement to the right scope.
+
+	2010-07-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (try_replace_in_use): New static function.
+	(reload_combine_recognize_const_pattern): Use it here.  Allow
+	substituting into a final add insn, and substituting into a memory
+	reference in an insn that sets the reg.
+
+=== modified file 'gcc/Makefile.in'
+Index: gcc-4.5/gcc/Makefile.in
+===================================================================
+--- gcc-4.5.orig/gcc/Makefile.in
++++ gcc-4.5/gcc/Makefile.in
+@@ -3159,7 +3159,7 @@ postreload.o : postreload.c $(CONFIG_H) 
+    $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \
+    hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \
+    $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \
+-   $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
++   $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
+ postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
+    $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \
+    $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
+Index: gcc-4.5/gcc/postreload.c
+===================================================================
+--- gcc-4.5.orig/gcc/postreload.c
++++ gcc-4.5/gcc/postreload.c
+@@ -44,6 +44,7 @@ along with GCC; see the file COPYING3.  
+ #include "toplev.h"
+ #include "except.h"
+ #include "tree.h"
++#include "target.h"
+ #include "timevar.h"
+ #include "tree-pass.h"
+ #include "df.h"
+@@ -56,10 +57,10 @@ static int reload_cse_simplify_set (rtx,
+ static int reload_cse_simplify_operands (rtx, rtx);
+ 
+ static void reload_combine (void);
+-static void reload_combine_note_use (rtx *, rtx);
++static void reload_combine_note_use (rtx *, rtx, int, rtx);
+ static void reload_combine_note_store (rtx, const_rtx, void *);
+ 
+-static void reload_cse_move2add (rtx);
++static bool reload_cse_move2add (rtx);
+ static void move2add_note_store (rtx, const_rtx, void *);
+ 
+ /* Call cse / combine like post-reload optimization phases.
+@@ -67,11 +68,16 @@ static void move2add_note_store (rtx, co
+ void
+ reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
+ {
++  bool moves_converted;
+   reload_cse_regs_1 (first);
+   reload_combine ();
+-  reload_cse_move2add (first);
++  moves_converted = reload_cse_move2add (first);
+   if (flag_expensive_optimizations)
+-    reload_cse_regs_1 (first);
++    {
++      if (moves_converted)
++	reload_combine ();
++      reload_cse_regs_1 (first);
++    }
+ }
+ 
+ /* See whether a single set SET is a noop.  */
+@@ -660,30 +666,43 @@ reload_cse_simplify_operands (rtx insn, 
+ 
+ /* The maximum number of uses of a register we can keep track of to
+    replace them with reg+reg addressing.  */
+-#define RELOAD_COMBINE_MAX_USES 6
++#define RELOAD_COMBINE_MAX_USES 16
+ 
+-/* INSN is the insn where a register has been used, and USEP points to the
+-   location of the register within the rtl.  */
+-struct reg_use { rtx insn, *usep; };
++/* Describes a recorded use of a register.  */
++struct reg_use
++{
++  /* The insn where a register has been used.  */
++  rtx insn;
++  /* Points to the memory reference enclosing the use, if any, NULL_RTX
++     otherwise.  */
++  rtx containing_mem;
++  /* Location of the register withing INSN.  */
++  rtx *usep;
++  /* The reverse uid of the insn.  */
++  int ruid;
++};
+ 
+ /* If the register is used in some unknown fashion, USE_INDEX is negative.
+    If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
+-   indicates where it becomes live again.
++   indicates where it is first set or clobbered.
+    Otherwise, USE_INDEX is the index of the last encountered use of the
+-   register (which is first among these we have seen since we scan backwards),
+-   OFFSET contains the constant offset that is added to the register in
+-   all encountered uses, and USE_RUID indicates the first encountered, i.e.
+-   last, of these uses.
++   register (which is first among these we have seen since we scan backwards).
++   USE_RUID indicates the first encountered, i.e. last, of these uses.
++   If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
++   with a constant offset; OFFSET contains this constant in that case.
+    STORE_RUID is always meaningful if we only want to use a value in a
+    register in a different place: it denotes the next insn in the insn
+-   stream (i.e. the last encountered) that sets or clobbers the register.  */
++   stream (i.e. the last encountered) that sets or clobbers the register.
++   REAL_STORE_RUID is similar, but clobbers are ignored when updating it.  */
+ static struct
+   {
+     struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
+-    int use_index;
+     rtx offset;
++    int use_index;
+     int store_ruid;
++    int real_store_ruid;
+     int use_ruid;
++    bool all_offsets_match;
+   } reg_state[FIRST_PSEUDO_REGISTER];
+ 
+ /* Reverse linear uid.  This is increased in reload_combine while scanning
+@@ -691,42 +710,548 @@ static struct
+    and the store_ruid / use_ruid fields in reg_state.  */
+ static int reload_combine_ruid;
+ 
++/* The RUID of the last label we encountered in reload_combine.  */
++static int last_label_ruid;
++
++/* The RUID of the last jump we encountered in reload_combine.  */
++static int last_jump_ruid;
++
++/* The register numbers of the first and last index register.  A value of
++   -1 in LAST_INDEX_REG indicates that we've previously computed these
++   values and found no suitable index registers.  */
++static int first_index_reg = -1;
++static int last_index_reg;
++
+ #define LABEL_LIVE(LABEL) \
+   (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
+ 
++/* Subroutine of reload_combine_split_ruids, called to fix up a single
++   ruid pointed to by *PRUID if it is higher than SPLIT_RUID.  */
++
++static inline void
++reload_combine_split_one_ruid (int *pruid, int split_ruid)
++{
++  if (*pruid > split_ruid)
++    (*pruid)++;
++}
++
++/* Called when we insert a new insn in a position we've already passed in
++   the scan.  Examine all our state, increasing all ruids that are higher
++   than SPLIT_RUID by one in order to make room for a new insn.  */
++
++static void
++reload_combine_split_ruids (int split_ruid)
++{
++  unsigned i;
++
++  reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
++  reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
++  reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
++
++  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
++    {
++      int j, idx = reg_state[i].use_index;
++      reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
++      reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
++      reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
++				     split_ruid);
++      if (idx < 0)
++	continue;
++      for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
++	{
++	  reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
++					 split_ruid);
++	}
++    }
++}
++
++/* Called when we are about to rescan a previously encountered insn with
++   reload_combine_note_use after modifying some part of it.  This clears all
++   information about uses in that particular insn.  */
++
++static void
++reload_combine_purge_insn_uses (rtx insn)
++{
++  unsigned i;
++
++  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
++    {
++      int j, k, idx = reg_state[i].use_index;
++      if (idx < 0)
++	continue;
++      j = k = RELOAD_COMBINE_MAX_USES;
++      while (j-- > idx)
++	{
++	  if (reg_state[i].reg_use[j].insn != insn)
++	    {
++	      k--;
++	      if (k != j)
++		reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
++	    }
++	}
++      reg_state[i].use_index = k;
++    }
++}
++
++/* Called when we need to forget about all uses of REGNO after an insn
++   which is identified by RUID.  */
++
++static void
++reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
++{
++  int j, k, idx = reg_state[regno].use_index;
++  if (idx < 0)
++    return;
++  j = k = RELOAD_COMBINE_MAX_USES;
++  while (j-- > idx)
++    {
++      if (reg_state[regno].reg_use[j].ruid >= ruid)
++	{
++	  k--;
++	  if (k != j)
++	    reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
++	}
++    }
++  reg_state[regno].use_index = k;
++}
++
++/* Find the use of REGNO with the ruid that is highest among those
++   lower than RUID_LIMIT, and return it if it is the only use of this
++   reg in the insn.  Return NULL otherwise.  */
++
++static struct reg_use *
++reload_combine_closest_single_use (unsigned regno, int ruid_limit)
++{
++  int i, best_ruid = 0;
++  int use_idx = reg_state[regno].use_index;
++  struct reg_use *retval;
++
++  if (use_idx < 0)
++    return NULL;
++  retval = NULL;
++  for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
++    {
++      struct reg_use *use = reg_state[regno].reg_use + i; 
++      int this_ruid = use->ruid;
++      if (this_ruid >= ruid_limit)
++	continue;
++      if (this_ruid > best_ruid)
++	{
++	  best_ruid = this_ruid;
++	  retval = use;
++	}
++      else if (this_ruid == best_ruid)
++	retval = NULL;
++    }
++  if (last_label_ruid >= best_ruid)
++    return NULL;
++  return retval;
++}
++
++/* After we've moved an add insn, fix up any debug insns that occur
++   between the old location of the add and the new location.  REG is
++   the destination register of the add insn; REPLACEMENT is the
++   SET_SRC of the add.  FROM and TO specify the range in which we
++   should make this change on debug insns.  */
++
++static void
++fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
++{
++  rtx insn;
++  for (insn = from; insn != to; insn = NEXT_INSN (insn))
++    {
++      rtx t;
++
++      if (!DEBUG_INSN_P (insn))
++	continue;
++      
++      t = INSN_VAR_LOCATION_LOC (insn);
++      t = simplify_replace_rtx (t, reg, replacement);
++      validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
++    }
++}
++
++/* Subroutine of reload_combine_recognize_const_pattern.  Try to replace REG
++   with SRC in the insn described by USE, taking costs into account.  Return
++   true if we made the replacement.  */
++
++static bool
++try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
++{
++  rtx use_insn = use->insn;
++  rtx mem = use->containing_mem;
++  bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
++
++  if (mem != NULL_RTX)
++    {
++      addr_space_t as = MEM_ADDR_SPACE (mem);
++      rtx oldaddr = XEXP (mem, 0);
++      rtx newaddr = NULL_RTX;
++      int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
++      int new_cost;
++
++      newaddr = simplify_replace_rtx (oldaddr, reg, src);
++      if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
++	{
++	  XEXP (mem, 0) = newaddr;
++	  new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
++	  XEXP (mem, 0) = oldaddr;
++	  if (new_cost <= old_cost
++	      && validate_change (use_insn,
++				  &XEXP (mem, 0), newaddr, 0))
++	    return true;
++	}
++    }
++  else
++    {
++      rtx new_set = single_set (use_insn);
++      if (new_set
++	  && REG_P (SET_DEST (new_set))
++	  && GET_CODE (SET_SRC (new_set)) == PLUS
++	  && REG_P (XEXP (SET_SRC (new_set), 0))
++	  && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
++	{
++	  rtx new_src;
++	  int old_cost = rtx_cost (SET_SRC (new_set), SET, speed);
++
++	  gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
++	  new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
++
++	  if (rtx_cost (new_src, SET, speed) <= old_cost
++	      && validate_change (use_insn, &SET_SRC (new_set),
++				  new_src, 0))
++	    return true;
++	}
++    }
++  return false;
++}
++
++/* Called by reload_combine when scanning INSN.  This function tries to detect
++   patterns where a constant is added to a register, and the result is used
++   in an address.
++   Return true if no further processing is needed on INSN; false if it wasn't
++   recognized and should be handled normally.  */
++
++static bool
++reload_combine_recognize_const_pattern (rtx insn)
++{
++  int from_ruid = reload_combine_ruid;
++  rtx set, pat, reg, src, addreg;
++  unsigned int regno;
++  struct reg_use *use;
++  bool must_move_add;
++  rtx add_moved_after_insn = NULL_RTX;
++  int add_moved_after_ruid = 0;
++  int clobbered_regno = -1;
++
++  set = single_set (insn);
++  if (set == NULL_RTX)
++    return false;
++
++  reg = SET_DEST (set);
++  src = SET_SRC (set);
++  if (!REG_P (reg)
++      || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
++      || GET_MODE (reg) != Pmode
++      || reg == stack_pointer_rtx)
++    return false;
++
++  regno = REGNO (reg);
++
++  /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
++     uses of REG1 inside an address, or inside another add insn.  If
++     possible and profitable, merge the addition into subsequent
++     uses.  */
++  if (GET_CODE (src) != PLUS
++      || !REG_P (XEXP (src, 0))
++      || !CONSTANT_P (XEXP (src, 1)))
++    return false;
++
++  addreg = XEXP (src, 0);
++  must_move_add = rtx_equal_p (reg, addreg);
++
++  pat = PATTERN (insn);
++  if (must_move_add && set != pat)
++    {
++      /* We have to be careful when moving the add; apart from the
++	 single_set there may also be clobbers.  Recognize one special
++	 case, that of one clobber alongside the set (likely a clobber
++	 of the CC register).  */
++      gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
++      if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
++	  || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
++	  || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
++	return false;
++      clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
++    }
++
++  do
++    {
++      use = reload_combine_closest_single_use (regno, from_ruid);
++
++      if (use)
++	/* Start the search for the next use from here.  */
++	from_ruid = use->ruid;
++
++      if (use && GET_MODE (*use->usep) == Pmode)
++	{
++	  bool delete_add = false;
++	  rtx use_insn = use->insn;
++	  int use_ruid = use->ruid;
++
++	  /* Avoid moving the add insn past a jump.  */
++	  if (must_move_add && use_ruid <= last_jump_ruid)
++	    break;
++
++	  /* If the add clobbers another hard reg in parallel, don't move
++	     it past a real set of this hard reg.  */
++	  if (must_move_add && clobbered_regno >= 0
++	      && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
++	    break;
++
++	  gcc_assert (reg_state[regno].store_ruid <= use_ruid);
++	  /* Avoid moving a use of ADDREG past a point where it is stored.  */
++	  if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
++	    break;
++
++	  /* We also must not move the addition past an insn that sets
++	     the same register, unless we can combine two add insns.  */
++	  if (must_move_add && reg_state[regno].store_ruid == use_ruid)
++	    {
++	      if (use->containing_mem == NULL_RTX)
++		delete_add = true;
++	      else
++		break;
++	    }
++
++	  if (try_replace_in_use (use, reg, src))
++	    {
++	      reload_combine_purge_insn_uses (use_insn);
++	      reload_combine_note_use (&PATTERN (use_insn), use_insn,
++				       use_ruid, NULL_RTX);
++
++	      if (delete_add)
++		{
++		  fixup_debug_insns (reg, src, insn, use_insn);
++		  delete_insn (insn);
++		  return true;
++		}
++	      if (must_move_add)
++		{
++		  add_moved_after_insn = use_insn;
++		  add_moved_after_ruid = use_ruid;
++		}
++	      continue;
++	    }
++	}
++      /* If we get here, we couldn't handle this use.  */
++      if (must_move_add)
++	break;
++    }
++  while (use);
++
++  if (!must_move_add || add_moved_after_insn == NULL_RTX)
++    /* Process the add normally.  */
++    return false;
++
++  fixup_debug_insns (reg, src, insn, add_moved_after_insn);
++
++  reorder_insns (insn, insn, add_moved_after_insn);
++  reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
++  reload_combine_split_ruids (add_moved_after_ruid - 1);
++  reload_combine_note_use (&PATTERN (insn), insn,
++			   add_moved_after_ruid, NULL_RTX);
++  reg_state[regno].store_ruid = add_moved_after_ruid;
++
++  return true;
++}
++
++/* Called by reload_combine when scanning INSN.  Try to detect a pattern we
++   can handle and improve.  Return true if no further processing is needed on
++   INSN; false if it wasn't recognized and should be handled normally.  */
++
++static bool
++reload_combine_recognize_pattern (rtx insn)
++{
++  rtx set, reg, src;
++  unsigned int regno;
++
++  set = single_set (insn);
++  if (set == NULL_RTX)
++    return false;
++
++  reg = SET_DEST (set);
++  src = SET_SRC (set);
++  if (!REG_P (reg)
++      || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
++    return false;
++
++  regno = REGNO (reg);
++
++  /* Look for (set (REGX) (CONST_INT))
++     (set (REGX) (PLUS (REGX) (REGY)))
++     ...
++     ... (MEM (REGX)) ...
++     and convert it to
++     (set (REGZ) (CONST_INT))
++     ...
++     ... (MEM (PLUS (REGZ) (REGY)))... .
++
++     First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
++     and that we know all uses of REGX before it dies.
++     Also, explicitly check that REGX != REGY; our life information
++     does not yet show whether REGY changes in this insn.  */
++
++  if (GET_CODE (src) == PLUS
++      && reg_state[regno].all_offsets_match
++      && last_index_reg != -1
++      && REG_P (XEXP (src, 1))
++      && rtx_equal_p (XEXP (src, 0), reg)
++      && !rtx_equal_p (XEXP (src, 1), reg)
++      && reg_state[regno].use_index >= 0
++      && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
++      && last_label_ruid < reg_state[regno].use_ruid)
++    {
++      rtx base = XEXP (src, 1);
++      rtx prev = prev_nonnote_insn (insn);
++      rtx prev_set = prev ? single_set (prev) : NULL_RTX;
++      rtx index_reg = NULL_RTX;
++      rtx reg_sum = NULL_RTX;
++      int i;
++
++      /* Now we need to set INDEX_REG to an index register (denoted as
++	 REGZ in the illustration above) and REG_SUM to the expression
++	 register+register that we want to use to substitute uses of REG
++	 (typically in MEMs) with.  First check REG and BASE for being
++	 index registers; we can use them even if they are not dead.  */
++      if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
++	  || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
++				REGNO (base)))
++	{
++	  index_reg = reg;
++	  reg_sum = src;
++	}
++      else
++	{
++	  /* Otherwise, look for a free index register.  Since we have
++	     checked above that neither REG nor BASE are index registers,
++	     if we find anything at all, it will be different from these
++	     two registers.  */
++	  for (i = first_index_reg; i <= last_index_reg; i++)
++	    {
++	      if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
++		  && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
++		  && reg_state[i].store_ruid <= reg_state[regno].use_ruid
++		  && (call_used_regs[i] || df_regs_ever_live_p (i))
++		  && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
++		  && !fixed_regs[i] && !global_regs[i]
++		  && hard_regno_nregs[i][GET_MODE (reg)] == 1
++		  && targetm.hard_regno_scratch_ok (i))
++		{
++		  index_reg = gen_rtx_REG (GET_MODE (reg), i);
++		  reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
++		  break;
++		}
++	    }
++	}
++
++      /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
++	 (REGY), i.e. BASE, is not clobbered before the last use we'll
++	 create.  */
++      if (reg_sum
++	  && prev_set
++	  && CONST_INT_P (SET_SRC (prev_set))
++	  && rtx_equal_p (SET_DEST (prev_set), reg)
++	  && (reg_state[REGNO (base)].store_ruid
++	      <= reg_state[regno].use_ruid))
++	{
++	  /* Change destination register and, if necessary, the constant
++	     value in PREV, the constant loading instruction.  */
++	  validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
++	  if (reg_state[regno].offset != const0_rtx)
++	    validate_change (prev,
++			     &SET_SRC (prev_set),
++			     GEN_INT (INTVAL (SET_SRC (prev_set))
++				      + INTVAL (reg_state[regno].offset)),
++			     1);
++
++	  /* Now for every use of REG that we have recorded, replace REG
++	     with REG_SUM.  */
++	  for (i = reg_state[regno].use_index;
++	       i < RELOAD_COMBINE_MAX_USES; i++)
++	    validate_unshare_change (reg_state[regno].reg_use[i].insn,
++				     reg_state[regno].reg_use[i].usep,
++				     /* Each change must have its own
++					replacement.  */
++				     reg_sum, 1);
++
++	  if (apply_change_group ())
++	    {
++	      struct reg_use *lowest_ruid = NULL;
++
++	      /* For every new use of REG_SUM, we have to record the use
++		 of BASE therein, i.e. operand 1.  */
++	      for (i = reg_state[regno].use_index;
++		   i < RELOAD_COMBINE_MAX_USES; i++)
++		{
++		  struct reg_use *use = reg_state[regno].reg_use + i;
++		  reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
++					   use->ruid, use->containing_mem);
++		  if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
++		    lowest_ruid = use;
++		}
++
++	      fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
++
++	      /* Delete the reg-reg addition.  */
++	      delete_insn (insn);
++
++	      if (reg_state[regno].offset != const0_rtx)
++		/* Previous REG_EQUIV / REG_EQUAL notes for PREV
++		   are now invalid.  */
++		remove_reg_equal_equiv_notes (prev);
++
++	      reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
++	      return true;
++	    }
++	}
++    }
++  return false;
++}
++
+ static void
+ reload_combine (void)
+ {
+-  rtx insn, set;
+-  int first_index_reg = -1;
+-  int last_index_reg = 0;
++  rtx insn, prev;
+   int i;
+   basic_block bb;
+   unsigned int r;
+-  int last_label_ruid;
+   int min_labelno, n_labels;
+   HARD_REG_SET ever_live_at_start, *label_live;
+ 
+-  /* If reg+reg can be used in offsetable memory addresses, the main chunk of
+-     reload has already used it where appropriate, so there is no use in
+-     trying to generate it now.  */
+-  if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
+-    return;
+-
+   /* To avoid wasting too much time later searching for an index register,
+      determine the minimum and maximum index register numbers.  */
+-  for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+-    if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
+-      {
+-	if (first_index_reg == -1)
+-	  first_index_reg = r;
++  if (INDEX_REG_CLASS == NO_REGS)
++    last_index_reg = -1;
++  else if (first_index_reg == -1 && last_index_reg == 0)
++    {
++      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
++	if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
++	  {
++	    if (first_index_reg == -1)
++	      first_index_reg = r;
+ 
+-	last_index_reg = r;
+-      }
++	    last_index_reg = r;
++	  }
+ 
+-  /* If no index register is available, we can quit now.  */
+-  if (first_index_reg == -1)
+-    return;
++      /* If no index register is available, we can quit now.  Set LAST_INDEX_REG
++	 to -1 so we'll know to quit early the next time we get here.  */
++      if (first_index_reg == -1)
++	{
++	  last_index_reg = -1;
++	  return;
++	}
++    }
+ 
+   /* Set up LABEL_LIVE and EVER_LIVE_AT_START.  The register lifetime
+      information is a bit fuzzy immediately after reload, but it's
+@@ -753,20 +1278,23 @@ reload_combine (void)
+     }
+ 
+   /* Initialize last_label_ruid, reload_combine_ruid and reg_state.  */
+-  last_label_ruid = reload_combine_ruid = 0;
++  last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
+   for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+     {
+-      reg_state[r].store_ruid = reload_combine_ruid;
++      reg_state[r].store_ruid = 0;
++      reg_state[r].real_store_ruid = 0;
+       if (fixed_regs[r])
+ 	reg_state[r].use_index = -1;
+       else
+ 	reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+     }
+ 
+-  for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
++  for (insn = get_last_insn (); insn; insn = prev)
+     {
+       rtx note;
+ 
++      prev = PREV_INSN (insn);
++
+       /* We cannot do our optimization across labels.  Invalidating all the use
+ 	 information we have would be costly, so we just note where the label
+ 	 is and then later disable any optimization that would cross it.  */
+@@ -777,141 +1305,17 @@ reload_combine (void)
+ 	  if (! fixed_regs[r])
+ 	      reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+ 
+-      if (! INSN_P (insn))
++      if (! NONDEBUG_INSN_P (insn))
+ 	continue;
+ 
+       reload_combine_ruid++;
+ 
+-      /* Look for (set (REGX) (CONST_INT))
+-	 (set (REGX) (PLUS (REGX) (REGY)))
+-	 ...
+-	 ... (MEM (REGX)) ...
+-	 and convert it to
+-	 (set (REGZ) (CONST_INT))
+-	 ...
+-	 ... (MEM (PLUS (REGZ) (REGY)))... .
+-
+-	 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
+-	 and that we know all uses of REGX before it dies.
+-	 Also, explicitly check that REGX != REGY; our life information
+-	 does not yet show whether REGY changes in this insn.  */
+-      set = single_set (insn);
+-      if (set != NULL_RTX
+-	  && REG_P (SET_DEST (set))
+-	  && (hard_regno_nregs[REGNO (SET_DEST (set))]
+-			      [GET_MODE (SET_DEST (set))]
+-	      == 1)
+-	  && GET_CODE (SET_SRC (set)) == PLUS
+-	  && REG_P (XEXP (SET_SRC (set), 1))
+-	  && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
+-	  && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set))
+-	  && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
+-	{
+-	  rtx reg = SET_DEST (set);
+-	  rtx plus = SET_SRC (set);
+-	  rtx base = XEXP (plus, 1);
+-	  rtx prev = prev_nonnote_nondebug_insn (insn);
+-	  rtx prev_set = prev ? single_set (prev) : NULL_RTX;
+-	  unsigned int regno = REGNO (reg);
+-	  rtx index_reg = NULL_RTX;
+-	  rtx reg_sum = NULL_RTX;
+-
+-	  /* Now we need to set INDEX_REG to an index register (denoted as
+-	     REGZ in the illustration above) and REG_SUM to the expression
+-	     register+register that we want to use to substitute uses of REG
+-	     (typically in MEMs) with.  First check REG and BASE for being
+-	     index registers; we can use them even if they are not dead.  */
+-	  if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
+-	      || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
+-				    REGNO (base)))
+-	    {
+-	      index_reg = reg;
+-	      reg_sum = plus;
+-	    }
+-	  else
+-	    {
+-	      /* Otherwise, look for a free index register.  Since we have
+-		 checked above that neither REG nor BASE are index registers,
+-		 if we find anything at all, it will be different from these
+-		 two registers.  */
+-	      for (i = first_index_reg; i <= last_index_reg; i++)
+-		{
+-		  if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
+-					 i)
+-		      && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
+-		      && reg_state[i].store_ruid <= reg_state[regno].use_ruid
+-		      && hard_regno_nregs[i][GET_MODE (reg)] == 1)
+-		    {
+-		      index_reg = gen_rtx_REG (GET_MODE (reg), i);
+-		      reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
+-		      break;
+-		    }
+-		}
+-	    }
+-
+-	  /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
+-	     (REGY), i.e. BASE, is not clobbered before the last use we'll
+-	     create.  */
+-	  if (reg_sum
+-	      && prev_set
+-	      && CONST_INT_P (SET_SRC (prev_set))
+-	      && rtx_equal_p (SET_DEST (prev_set), reg)
+-	      && reg_state[regno].use_index >= 0
+-	      && (reg_state[REGNO (base)].store_ruid
+-		  <= reg_state[regno].use_ruid))
+-	    {
+-	      int i;
+-
+-	      /* Change destination register and, if necessary, the constant
+-		 value in PREV, the constant loading instruction.  */
+-	      validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
+-	      if (reg_state[regno].offset != const0_rtx)
+-		validate_change (prev,
+-				 &SET_SRC (prev_set),
+-				 GEN_INT (INTVAL (SET_SRC (prev_set))
+-					  + INTVAL (reg_state[regno].offset)),
+-				 1);
++      if (control_flow_insn_p (insn))
++	last_jump_ruid = reload_combine_ruid;
+ 
+-	      /* Now for every use of REG that we have recorded, replace REG
+-		 with REG_SUM.  */
+-	      for (i = reg_state[regno].use_index;
+-		   i < RELOAD_COMBINE_MAX_USES; i++)
+-		validate_unshare_change (reg_state[regno].reg_use[i].insn,
+-				 	 reg_state[regno].reg_use[i].usep,
+-				 	 /* Each change must have its own
+-				    	    replacement.  */
+-				 	 reg_sum, 1);
+-
+-	      if (apply_change_group ())
+-		{
+-		  /* For every new use of REG_SUM, we have to record the use
+-		     of BASE therein, i.e. operand 1.  */
+-		  for (i = reg_state[regno].use_index;
+-		       i < RELOAD_COMBINE_MAX_USES; i++)
+-		    reload_combine_note_use
+-		      (&XEXP (*reg_state[regno].reg_use[i].usep, 1),
+-		       reg_state[regno].reg_use[i].insn);
+-
+-		  if (reg_state[REGNO (base)].use_ruid
+-		      > reg_state[regno].use_ruid)
+-		    reg_state[REGNO (base)].use_ruid
+-		      = reg_state[regno].use_ruid;
+-
+-		  /* Delete the reg-reg addition.  */
+-		  delete_insn (insn);
+-
+-		  if (reg_state[regno].offset != const0_rtx)
+-		    /* Previous REG_EQUIV / REG_EQUAL notes for PREV
+-		       are now invalid.  */
+-		    remove_reg_equal_equiv_notes (prev);
+-
+-		  reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
+-		  reg_state[REGNO (index_reg)].store_ruid
+-		    = reload_combine_ruid;
+-		  continue;
+-		}
+-	    }
+-	}
++      if (reload_combine_recognize_const_pattern (insn)
++	  || reload_combine_recognize_pattern (insn))
++	continue;
+ 
+       note_stores (PATTERN (insn), reload_combine_note_store, NULL);
+ 
+@@ -967,7 +1371,8 @@ reload_combine (void)
+ 	      reg_state[i].use_index = -1;
+ 	}
+ 
+-      reload_combine_note_use (&PATTERN (insn), insn);
++      reload_combine_note_use (&PATTERN (insn), insn,
++			       reload_combine_ruid, NULL_RTX);
+       for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+ 	{
+ 	  if (REG_NOTE_KIND (note) == REG_INC
+@@ -976,6 +1381,7 @@ reload_combine (void)
+ 	      int regno = REGNO (XEXP (note, 0));
+ 
+ 	      reg_state[regno].store_ruid = reload_combine_ruid;
++	      reg_state[regno].real_store_ruid = reload_combine_ruid;
+ 	      reg_state[regno].use_index = -1;
+ 	    }
+ 	}
+@@ -985,8 +1391,8 @@ reload_combine (void)
+ }
+ 
+ /* Check if DST is a register or a subreg of a register; if it is,
+-   update reg_state[regno].store_ruid and reg_state[regno].use_index
+-   accordingly.  Called via note_stores from reload_combine.  */
++   update store_ruid, real_store_ruid and use_index in the reg_state
++   structure accordingly.  Called via note_stores from reload_combine.  */
+ 
+ static void
+ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
+@@ -1010,14 +1416,14 @@ reload_combine_note_store (rtx dst, cons
+   /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
+      careful with registers / register parts that are not full words.
+      Similarly for ZERO_EXTRACT.  */
+-  if (GET_CODE (set) != SET
+-      || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
++  if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
+       || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
+     {
+       for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
+ 	{
+ 	  reg_state[i].use_index = -1;
+ 	  reg_state[i].store_ruid = reload_combine_ruid;
++	  reg_state[i].real_store_ruid = reload_combine_ruid;
+ 	}
+     }
+   else
+@@ -1025,6 +1431,8 @@ reload_combine_note_store (rtx dst, cons
+       for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
+ 	{
+ 	  reg_state[i].store_ruid = reload_combine_ruid;
++	  if (GET_CODE (set) == SET)
++	    reg_state[i].real_store_ruid = reload_combine_ruid;
+ 	  reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
+ 	}
+     }
+@@ -1035,7 +1443,7 @@ reload_combine_note_store (rtx dst, cons
+    *XP is the pattern of INSN, or a part of it.
+    Called from reload_combine, and recursively by itself.  */
+ static void
+-reload_combine_note_use (rtx *xp, rtx insn)
++reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
+ {
+   rtx x = *xp;
+   enum rtx_code code = x->code;
+@@ -1048,7 +1456,7 @@ reload_combine_note_use (rtx *xp, rtx in
+     case SET:
+       if (REG_P (SET_DEST (x)))
+ 	{
+-	  reload_combine_note_use (&SET_SRC (x), insn);
++	  reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
+ 	  return;
+ 	}
+       break;
+@@ -1104,6 +1512,11 @@ reload_combine_note_use (rtx *xp, rtx in
+ 	    return;
+ 	  }
+ 
++	/* We may be called to update uses in previously seen insns.
++	   Don't add uses beyond the last store we saw.  */
++	if (ruid < reg_state[regno].store_ruid)
++	  return;
++
+ 	/* If this register is already used in some unknown fashion, we
+ 	   can't do anything.
+ 	   If we decrement the index from zero to -1, we can't store more
+@@ -1112,29 +1525,34 @@ reload_combine_note_use (rtx *xp, rtx in
+ 	if (use_index < 0)
+ 	  return;
+ 
+-	if (use_index != RELOAD_COMBINE_MAX_USES - 1)
+-	  {
+-	    /* We have found another use for a register that is already
+-	       used later.  Check if the offsets match; if not, mark the
+-	       register as used in an unknown fashion.  */
+-	    if (! rtx_equal_p (offset, reg_state[regno].offset))
+-	      {
+-		reg_state[regno].use_index = -1;
+-		return;
+-	      }
+-	  }
+-	else
++	if (use_index == RELOAD_COMBINE_MAX_USES - 1)
+ 	  {
+ 	    /* This is the first use of this register we have seen since we
+ 	       marked it as dead.  */
+ 	    reg_state[regno].offset = offset;
+-	    reg_state[regno].use_ruid = reload_combine_ruid;
++	    reg_state[regno].all_offsets_match = true;
++	    reg_state[regno].use_ruid = ruid;
++	  }
++	else
++	  {
++	    if (reg_state[regno].use_ruid > ruid)
++	      reg_state[regno].use_ruid = ruid;
++
++	    if (! rtx_equal_p (offset, reg_state[regno].offset))
++	      reg_state[regno].all_offsets_match = false;
+ 	  }
++
+ 	reg_state[regno].reg_use[use_index].insn = insn;
++	reg_state[regno].reg_use[use_index].ruid = ruid;
++	reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
+ 	reg_state[regno].reg_use[use_index].usep = xp;
+ 	return;
+       }
+ 
++    case MEM:
++      containing_mem = x;
++      break;
++
+     default:
+       break;
+     }
+@@ -1144,11 +1562,12 @@ reload_combine_note_use (rtx *xp, rtx in
+   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+     {
+       if (fmt[i] == 'e')
+-	reload_combine_note_use (&XEXP (x, i), insn);
++	reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
+       else if (fmt[i] == 'E')
+ 	{
+ 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+-	    reload_combine_note_use (&XVECEXP (x, i, j), insn);
++	    reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
++				     containing_mem);
+ 	}
+     }
+ }
+@@ -1196,9 +1615,10 @@ static int move2add_last_label_luid;
+    while REG is known to already have value (SYM + offset).
+    This function tries to change INSN into an add instruction
+    (set (REG) (plus (REG) (OFF - offset))) using the known value.
+-   It also updates the information about REG's known value.  */
++   It also updates the information about REG's known value.
++   Return true if we made a change.  */
+ 
+-static void
++static bool
+ move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
+ {
+   rtx pat = PATTERN (insn);
+@@ -1207,6 +1627,7 @@ move2add_use_add2_insn (rtx reg, rtx sym
+   rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
+ 			      GET_MODE (reg));
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
++  bool changed = false;
+ 
+   /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
+      use (set (reg) (reg)) instead.
+@@ -1221,13 +1642,13 @@ move2add_use_add2_insn (rtx reg, rtx sym
+ 	 (reg)), would be discarded.  Maybe we should
+ 	 try a truncMN pattern?  */
+       if (INTVAL (off) == reg_offset [regno])
+-	validate_change (insn, &SET_SRC (pat), reg, 0);
++	changed = validate_change (insn, &SET_SRC (pat), reg, 0);
+     }
+   else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
+ 	   && have_add2_insn (reg, new_src))
+     {
+       rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
+-      validate_change (insn, &SET_SRC (pat), tem, 0);
++      changed = validate_change (insn, &SET_SRC (pat), tem, 0);
+     }
+   else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
+     {
+@@ -1252,8 +1673,9 @@ move2add_use_add2_insn (rtx reg, rtx sym
+ 			     gen_rtx_STRICT_LOW_PART (VOIDmode,
+ 						      narrow_reg),
+ 			     narrow_src);
+-	      if (validate_change (insn, &PATTERN (insn),
+-				   new_set, 0))
++	      changed = validate_change (insn, &PATTERN (insn),
++					 new_set, 0);
++	      if (changed)
+ 		break;
+ 	    }
+ 	}
+@@ -1263,6 +1685,7 @@ move2add_use_add2_insn (rtx reg, rtx sym
+   reg_mode[regno] = GET_MODE (reg);
+   reg_symbol_ref[regno] = sym;
+   reg_offset[regno] = INTVAL (off);
++  return changed;
+ }
+ 
+ 
+@@ -1272,9 +1695,10 @@ move2add_use_add2_insn (rtx reg, rtx sym
+    value (SYM + offset) and change INSN into an add instruction
+    (set (REG) (plus (the found register) (OFF - offset))) if such
+    a register is found.  It also updates the information about
+-   REG's known value.  */
++   REG's known value.
++   Return true iff we made a change.  */
+ 
+-static void
++static bool
+ move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
+ {
+   rtx pat = PATTERN (insn);
+@@ -1284,6 +1708,7 @@ move2add_use_add3_insn (rtx reg, rtx sym
+   int min_regno;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int i;
++  bool changed = false;
+ 
+   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     if (reg_set_luid[i] > move2add_last_label_luid
+@@ -1328,20 +1753,25 @@ move2add_use_add3_insn (rtx reg, rtx sym
+ 				      GET_MODE (reg));
+ 	  tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
+ 	}
+-      validate_change (insn, &SET_SRC (pat), tem, 0);
++      if (validate_change (insn, &SET_SRC (pat), tem, 0))
++	changed = true;
+     }
+   reg_set_luid[regno] = move2add_luid;
+   reg_base_reg[regno] = -1;
+   reg_mode[regno] = GET_MODE (reg);
+   reg_symbol_ref[regno] = sym;
+   reg_offset[regno] = INTVAL (off);
++  return changed;
+ }
+ 
+-static void
++/* Convert move insns with constant inputs to additions if they are cheaper.
++   Return true if any changes were made.  */
++static bool
+ reload_cse_move2add (rtx first)
+ {
+   int i;
+   rtx insn;
++  bool changed = false;
+ 
+   for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
+     {
+@@ -1402,7 +1832,7 @@ reload_cse_move2add (rtx first)
+ 		  && reg_base_reg[regno] < 0
+ 		  && reg_symbol_ref[regno] == NULL_RTX)
+ 		{
+-		  move2add_use_add2_insn (reg, NULL_RTX, src, insn);
++		  changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
+ 		  continue;
+ 		}
+ 
+@@ -1463,6 +1893,7 @@ reload_cse_move2add (rtx first)
+ 			}
+ 		      if (success)
+ 			delete_insn (insn);
++		      changed |= success;
+ 		      insn = next;
+ 		      reg_mode[regno] = GET_MODE (reg);
+ 		      reg_offset[regno] =
+@@ -1508,12 +1939,12 @@ reload_cse_move2add (rtx first)
+ 		  && reg_base_reg[regno] < 0
+ 		  && reg_symbol_ref[regno] != NULL_RTX
+ 		  && rtx_equal_p (sym, reg_symbol_ref[regno]))
+-		move2add_use_add2_insn (reg, sym, off, insn);
++		changed |= move2add_use_add2_insn (reg, sym, off, insn);
+ 
+ 	      /* Otherwise, we have to find a register whose value is sum
+ 		 of sym and some constant value.  */
+ 	      else
+-		move2add_use_add3_insn (reg, sym, off, insn);
++		changed |= move2add_use_add3_insn (reg, sym, off, insn);
+ 
+ 	      continue;
+ 	    }
+@@ -1568,6 +1999,7 @@ reload_cse_move2add (rtx first)
+ 	    }
+ 	}
+     }
++  return changed;
+ }
+ 
+ /* SET is a SET or CLOBBER that sets DST.  DATA is the insn which
+Index: gcc-4.5/testsuite/gcc.target/arm/pr42235.c
+===================================================================
+--- /dev/null
++++ gcc-4.5/testsuite/gcc.target/arm/pr42235.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-mthumb -O2 -march=armv5te" }  */
++/* { dg-require-effective-target arm_thumb1_ok } */
++/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*r.,\[\\t \]*\#1" } } */
++/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*\#1" } } */
++
++#include <string.h>
++
++int foo (char *x)
++{
++  memset (x, 0, 6);
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99403.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99403.patch
new file mode 100644
index 0000000000..093dd1c570
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99403.patch
@@ -0,0 +1,176 @@
+2010-09-20  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #5256
+
+	libstdc++-v3/
+
+	Backport from mainline:
+
+	2010-05-21  Joseph Myers  <joseph@codesourcery.com>
+	* acinclude.m4 (GLIBCXX_ENABLE_CLOCALE): Use GNU locale model for
+	glibc 2.3 and later, but not uClibc, without an execution test.
+	* configure: Regenerate.
+	* doc/xml/manual/configure.xml, doc/xml/manual/prerequisites.xml,
+	doc/xml/faq.xml: Update.
+
+=== modified file 'libstdc++-v3/acinclude.m4'
+Index: gcc-4.5/libstdc++-v3/acinclude.m4
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/acinclude.m4
++++ gcc-4.5/libstdc++-v3/acinclude.m4
+@@ -1740,41 +1740,11 @@ AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [
+   if test $enable_clocale_flag = gnu; then
+     AC_EGREP_CPP([_GLIBCXX_ok], [
+     #include <features.h>
+-    #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2)
++    #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(__UCLIBC__)
+       _GLIBCXX_ok
+     #endif
+     ], enable_clocale_flag=gnu, enable_clocale_flag=generic)
+ 
+-    if test $enable_clocale = auto; then
+-      # Test for bugs early in glibc-2.2.x series
+-      AC_TRY_RUN([
+-      #define _GNU_SOURCE 1
+-      #include <locale.h>
+-      #include <string.h>
+-      #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2)
+-      extern __typeof(newlocale) __newlocale;
+-      extern __typeof(duplocale) __duplocale;
+-      extern __typeof(strcoll_l) __strcoll_l;
+-      #endif
+-      int main()
+-      {
+-	const char __one[] = "Äuglein Augmen";
+-        const char __two[] = "Äuglein";
+-       	int i;
+-        int j;
+-        __locale_t        loc;
+-        __locale_t        loc_dup;
+-        loc = __newlocale(1 << LC_ALL, "de_DE", 0);
+-        loc_dup = __duplocale(loc);
+-        i = __strcoll_l(__one, __two, loc);
+-        j = __strcoll_l(__one, __two, loc_dup);
+-        return 0;
+-      }
+-      ],
+-      [enable_clocale_flag=gnu],[enable_clocale_flag=generic],
+-      [enable_clocale_flag=generic])
+-    fi
+-
+     # Set it to scream when it hurts.
+     ac_save_CFLAGS="$CFLAGS"	
+     CFLAGS="-Wimplicit-function-declaration -Werror"
+Index: gcc-4.5/libstdc++-v3/configure
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/configure
++++ gcc-4.5/libstdc++-v3/configure
+@@ -15627,7 +15627,7 @@ fi
+ /* end confdefs.h.  */
+ 
+     #include <features.h>
+-    #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2)
++    #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(__UCLIBC__)
+       _GLIBCXX_ok
+     #endif
+ 
+@@ -15641,49 +15641,6 @@ fi
+ rm -f conftest*
+ 
+ 
+-    if test $enable_clocale = auto; then
+-      # Test for bugs early in glibc-2.2.x series
+-      if test "$cross_compiling" = yes; then :
+-  enable_clocale_flag=generic
+-else
+-  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+-/* end confdefs.h.  */
+-
+-      #define _GNU_SOURCE 1
+-      #include <locale.h>
+-      #include <string.h>
+-      #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2)
+-      extern __typeof(newlocale) __newlocale;
+-      extern __typeof(duplocale) __duplocale;
+-      extern __typeof(strcoll_l) __strcoll_l;
+-      #endif
+-      int main()
+-      {
+-	const char __one[] = "Äuglein Augmen";
+-        const char __two[] = "Äuglein";
+-       	int i;
+-        int j;
+-        __locale_t        loc;
+-        __locale_t        loc_dup;
+-        loc = __newlocale(1 << LC_ALL, "de_DE", 0);
+-        loc_dup = __duplocale(loc);
+-        i = __strcoll_l(__one, __two, loc);
+-        j = __strcoll_l(__one, __two, loc_dup);
+-        return 0;
+-      }
+-
+-_ACEOF
+-if ac_fn_c_try_run "$LINENO"; then :
+-  enable_clocale_flag=gnu
+-else
+-  enable_clocale_flag=generic
+-fi
+-rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
+-  conftest.$ac_objext conftest.beam conftest.$ac_ext
+-fi
+-
+-    fi
+-
+     # Set it to scream when it hurts.
+     ac_save_CFLAGS="$CFLAGS"
+     CFLAGS="-Wimplicit-function-declaration -Werror"
+Index: gcc-4.5/libstdc++-v3/doc/xml/faq.xml
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/doc/xml/faq.xml
++++ gcc-4.5/libstdc++-v3/doc/xml/faq.xml
+@@ -636,6 +636,8 @@
+          C library (glibc) version 2.2.5.  That version of glibc is over a
+          year old and contains necessary bugfixes.  Many GNU/Linux distros make
+          glibc version 2.3.x available now.
++         libstdc++ 4.6.0 and later require glibc 2.3 or later for this
++         localization and formatting code.
+       </para>
+       <para>The guideline is simple:  the more recent the C++ library, the
+          more recent the C library.  (This is also documented in the main
+Index: gcc-4.5/libstdc++-v3/doc/xml/manual/configure.xml
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/doc/xml/manual/configure.xml
++++ gcc-4.5/libstdc++-v3/doc/xml/manual/configure.xml
+@@ -113,8 +113,7 @@
+      <para>If not explicitly specified, the configure proccess tries
+       to guess the most suitable package from the choices above. The
+       default is 'generic'. On glibc-based systems of sufficient
+-      vintage (2.2.5 and newer) and capability (with installed DE and
+-      FR locale data), 'gnu' is automatically selected. This option
++      vintage (2.3 and newer), 'gnu' is automatically selected. This option
+       can change the library ABI.
+      </para>
+  </listitem></varlistentry>
+Index: gcc-4.5/libstdc++-v3/doc/xml/manual/prerequisites.xml
+===================================================================
+--- gcc-4.5.orig/libstdc++-v3/doc/xml/manual/prerequisites.xml
++++ gcc-4.5/libstdc++-v3/doc/xml/manual/prerequisites.xml
+@@ -52,16 +52,8 @@
+ 	<para>
+ 	  If gcc 3.1.0 or later on is being used on linux, an attempt
+ 	  will be made to use "C" library functionality necessary for
+-	  C++ named locale support.  For gcc 3.2.1 and later, this
+-	  means that glibc 2.2.5 or later is required and the "C"
+-	  library de_DE locale information must be installed.
+-	</para>
+-
+-	<para>
+-	  Note however that the sanity checks involving the de_DE
+-	  locale are skipped when an explicit --enable-clocale=gnu
+-	  configure option is used: only the basic checks are carried
+-	  out, defending against misconfigurations.
++	  C++ named locale support.  For gcc 4.6.0 and later, this
++	  means that glibc 2.3 or later is required.
+ 	</para>
+ 
+ 	<para>
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99404.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99404.patch
new file mode 100644
index 0000000000..2753300925
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99404.patch
@@ -0,0 +1,386 @@
+2010-09-20  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #9019
+
+	Backport from mainline:
+
+	gcc/
+	2010-09-20  Jie Zhang  <jie@codesourcery.com>
+	* config/arm/arm.c (arm_address_offset_is_imm): New.
+	(arm_early_store_addr_dep): New.
+	(arm_early_load_addr_dep): New.
+	* config/arm/arm-protos.h (arm_early_store_addr_dep): Declare.
+	(arm_early_load_addr_dep): Declare.
+	(arm_address_offset_is_imm): Declare.
+	* config/arm/cortex-m4.md: New file.
+	* config/arm/cortex-m4-fpu.md: New file.
+	* config/arm/arm.md: Include cortex-m4.md and cortex-m4-fpu.md.
+	(attr generic_sched): Exclude cortexm4.
+	(attr generic_vfp): Exclude cortexm4.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+Index: gcc-4.5/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm-protos.h
++++ gcc-4.5/gcc/config/arm/arm-protos.h
+@@ -87,6 +87,8 @@ extern int arm_coproc_mem_operand (rtx, 
+ extern int neon_vector_mem_operand (rtx, int);
+ extern int neon_struct_mem_operand (rtx);
+ extern int arm_no_early_store_addr_dep (rtx, rtx);
++extern int arm_early_store_addr_dep (rtx, rtx);
++extern int arm_early_load_addr_dep (rtx, rtx);
+ extern int arm_no_early_alu_shift_dep (rtx, rtx);
+ extern int arm_no_early_alu_shift_value_dep (rtx, rtx);
+ extern int arm_no_early_mul_dep (rtx, rtx);
+@@ -131,6 +133,7 @@ extern const char *output_move_quad (rtx
+ extern const char *output_move_vfp (rtx *operands);
+ extern const char *output_move_neon (rtx *operands);
+ extern int arm_attr_length_move_neon (rtx);
++extern int arm_address_offset_is_imm (rtx);
+ extern const char *output_add_immediate (rtx *);
+ extern const char *arithmetic_instr (rtx, int);
+ extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
+Index: gcc-4.5/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.c
++++ gcc-4.5/gcc/config/arm/arm.c
+@@ -13542,6 +13542,34 @@ arm_attr_length_move_neon (rtx insn)
+     return 4;
+ }
+ 
++/* Return nonzero if the offset in the address is an immediate.  Otherwise,
++   return zero.  */
++
++int
++arm_address_offset_is_imm (rtx insn)
++{
++  rtx mem, addr;
++
++  extract_insn_cached (insn);
++
++  if (REG_P (recog_data.operand[0]))
++    return 0;
++
++  mem = recog_data.operand[0];
++
++  gcc_assert (MEM_P (mem));
++
++  addr = XEXP (mem, 0);
++
++  if (GET_CODE (addr) == REG
++      || (GET_CODE (addr) == PLUS
++	  && GET_CODE (XEXP (addr, 0)) == REG
++	  && GET_CODE (XEXP (addr, 1)) == CONST_INT))
++    return 1;
++  else
++    return 0;
++}
++
+ /* Output an ADD r, s, #n where n may be too big for one instruction.
+    If adding zero to one register, output nothing.  */
+ const char *
+@@ -21620,6 +21648,38 @@ arm_no_early_store_addr_dep (rtx produce
+   return !reg_overlap_mentioned_p (value, addr);
+ }
+ 
++/* Return nonzero if the CONSUMER instruction (a store) does need
++   PRODUCER's value to calculate the address.  */
++
++int
++arm_early_store_addr_dep (rtx producer, rtx consumer)
++{
++  return !arm_no_early_store_addr_dep (producer, consumer);
++}
++
++/* Return nonzero if the CONSUMER instruction (a load) does need
++   PRODUCER's value to calculate the address.  */
++
++int
++arm_early_load_addr_dep (rtx producer, rtx consumer)
++{
++  rtx value = PATTERN (producer);
++  rtx addr = PATTERN (consumer);
++
++  if (GET_CODE (value) == COND_EXEC)
++    value = COND_EXEC_CODE (value);
++  if (GET_CODE (value) == PARALLEL)
++    value = XVECEXP (value, 0, 0);
++  value = XEXP (value, 0);
++  if (GET_CODE (addr) == COND_EXEC)
++    addr = COND_EXEC_CODE (addr);
++  if (GET_CODE (addr) == PARALLEL)
++    addr = XVECEXP (addr, 0, 0);
++  addr = XEXP (addr, 1);
++
++  return reg_overlap_mentioned_p (value, addr);
++}
++
+ /* Return nonzero if the CONSUMER instruction (an ALU op) does not
+    have an early register shift value or amount dependency on the
+    result of PRODUCER.  */
+Index: gcc-4.5/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.md
++++ gcc-4.5/gcc/config/arm/arm.md
+@@ -434,16 +434,16 @@
+ ;; True if the generic scheduling description should be used.
+ 
+ (define_attr "generic_sched" "yes,no"
+-  (const (if_then_else 
+-          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
+-	      (eq_attr "tune_cortexr4" "yes"))
++  (const (if_then_else
++          (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4")
++	       (eq_attr "tune_cortexr4" "yes"))
+           (const_string "no")
+           (const_string "yes"))))
+ 
+ (define_attr "generic_vfp" "yes,no"
+   (const (if_then_else
+ 	  (and (eq_attr "fpu" "vfp")
+-	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
++	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4")
+ 	       (eq_attr "tune_cortexr4" "no"))
+ 	  (const_string "yes")
+ 	  (const_string "no"))))
+@@ -472,6 +472,8 @@
+ (include "cortex-a9.md")
+ (include "cortex-r4.md")
+ (include "cortex-r4f.md")
++(include "cortex-m4.md")
++(include "cortex-m4-fpu.md")
+ (include "vfp11.md")
+ 
+ 
+Index: gcc-4.5/gcc/config/arm/cortex-m4-fpu.md
+===================================================================
+--- /dev/null
++++ gcc-4.5/gcc/config/arm/cortex-m4-fpu.md
+@@ -0,0 +1,111 @@
++;; ARM Cortex-M4 FPU pipeline description
++;; Copyright (C) 2010 Free Software Foundation, Inc.
++;; Contributed by CodeSourcery.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++
++;; Use an artifial unit to model FPU.
++(define_cpu_unit "cortex_m4_v" "cortex_m4")
++
++(define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v")
++
++;; Integer instructions following VDIV or VSQRT complete out-of-order.
++(define_insn_reservation "cortex_m4_fdivs" 15
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "fdivs"))
++  "cortex_m4_ex_v,cortex_m4_v*13")
++
++(define_insn_reservation "cortex_m4_vmov_1" 1
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "fcpys,fconsts"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_vmov_2" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_2_r,r_2_f"))
++  "cortex_m4_ex_v*2")
++
++(define_insn_reservation "cortex_m4_fmuls" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "fmuls"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_fmacs" 4
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "fmacs"))
++  "cortex_m4_ex_v*3")
++
++(define_insn_reservation "cortex_m4_ffariths" 1
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "ffariths"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_fadds" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "fadds"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_fcmps" 1
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "fcmps"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_f_flag" 1
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_flag"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_f_cvt" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_cvt"))
++  "cortex_m4_ex_v")
++
++(define_insn_reservation "cortex_m4_f_load" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_load"))
++  "cortex_m4_ex_v*2")
++
++(define_insn_reservation "cortex_m4_f_store" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_store"))
++  "cortex_m4_ex_v*2")
++
++(define_insn_reservation "cortex_m4_f_loadd" 3
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_loadd"))
++  "cortex_m4_ex_v*3")
++
++(define_insn_reservation "cortex_m4_f_stored" 3
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "f_stored"))
++  "cortex_m4_ex_v*3")
++
++;; MAC instructions consume their addend one cycle later. If the result
++;; of an arithmetic instruction is consumed as the addend of the following
++;; MAC instruction, the latency can be decreased by one.
++
++(define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt"
++		 "cortex_m4_fmacs"
++		 "arm_no_early_mul_dep")
++
++(define_bypass 3 "cortex_m4_fmacs"
++		 "cortex_m4_fmacs"
++		 "arm_no_early_mul_dep")
++
++(define_bypass 14 "cortex_m4_fdivs"
++		  "cortex_m4_fmacs"
++		  "arm_no_early_mul_dep")
+Index: gcc-4.5/gcc/config/arm/cortex-m4.md
+===================================================================
+--- /dev/null
++++ gcc-4.5/gcc/config/arm/cortex-m4.md
+@@ -0,0 +1,111 @@
++;; ARM Cortex-M4 pipeline description
++;; Copyright (C) 2010 Free Software Foundation, Inc.
++;; Contributed by CodeSourcery.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++
++(define_automaton "cortex_m4")
++
++;; We model the pipelining of LDR instructions by using two artificial units.
++
++(define_cpu_unit "cortex_m4_a" "cortex_m4")
++
++(define_cpu_unit "cortex_m4_b" "cortex_m4")
++
++(define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
++
++;; ALU and multiply is one cycle.
++(define_insn_reservation "cortex_m4_alu" 1
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult"))
++  "cortex_m4_ex")
++
++;; Byte, half-word and word load is two cycles.
++(define_insn_reservation "cortex_m4_load1" 2
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "load_byte,load1"))
++  "cortex_m4_a, cortex_m4_b")
++
++;; str rx, [ry, #imm] is always one cycle.
++(define_insn_reservation "cortex_m4_store1_1" 1
++  (and (and (eq_attr "tune" "cortexm4")
++	    (eq_attr "type" "store1"))
++       (ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
++  "cortex_m4_a")
++
++;; Other byte, half-word and word load is two cycles.
++(define_insn_reservation "cortex_m4_store1_2" 2
++  (and (and (eq_attr "tune" "cortexm4")
++	    (eq_attr "type" "store1"))
++       (eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
++  "cortex_m4_a*2")
++
++(define_insn_reservation "cortex_m4_load2" 3
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "load2"))
++  "cortex_m4_ex*3")
++
++(define_insn_reservation "cortex_m4_store2" 3
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "store2"))
++  "cortex_m4_ex*3")
++
++(define_insn_reservation "cortex_m4_load3" 4
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "load3"))
++  "cortex_m4_ex*4")
++
++(define_insn_reservation "cortex_m4_store3" 4
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "store3"))
++  "cortex_m4_ex*4")
++
++(define_insn_reservation "cortex_m4_load4" 5
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "load4"))
++  "cortex_m4_ex*5")
++
++(define_insn_reservation "cortex_m4_store4" 5
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "store4"))
++  "cortex_m4_ex*5")
++
++;; If the address of load or store depends on the result of the preceding
++;; instruction, the latency is increased by one.
++
++(define_bypass 2 "cortex_m4_alu"
++		 "cortex_m4_load1"
++		 "arm_early_load_addr_dep")
++
++(define_bypass 2 "cortex_m4_alu"
++		 "cortex_m4_store1_1,cortex_m4_store1_2"
++		 "arm_early_store_addr_dep")
++
++(define_insn_reservation "cortex_m4_branch" 3
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "branch"))
++  "cortex_m4_ex*3")
++
++(define_insn_reservation "cortex_m4_call" 3
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "call"))
++  "cortex_m4_ex*3")
++
++(define_insn_reservation "cortex_m4_block" 1
++  (and (eq_attr "tune" "cortexm4")
++       (eq_attr "type" "block"))
++  "cortex_m4_ex")
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99405.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99405.patch
new file mode 100644
index 0000000000..7fc943f4bc
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99405.patch
@@ -0,0 +1,36 @@
+2010-09-22  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-09-22  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* postreload.c (move2add_note_store): Add reg_symbol_ref[] checks
+	to update conditions. Fix reg_mode[] check.
+
+=== modified file 'gcc/postreload.c'
+Index: gcc-4.5/gcc/postreload.c
+===================================================================
+--- gcc-4.5.orig/gcc/postreload.c
++++ gcc-4.5/gcc/postreload.c
+@@ -2103,15 +2103,17 @@ move2add_note_store (rtx dst, const_rtx 
+ 		       && (MODES_OK_FOR_MOVE2ADD
+ 			   (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
+ 		{
+-		  if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
++		  if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
++		      && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
+ 		    offset = reg_offset[REGNO (XEXP (src, 1))];
+ 		  /* Maybe the first register is known to be a
+ 		     constant.  */
+ 		  else if (reg_set_luid[REGNO (base_reg)]
+ 			   > move2add_last_label_luid
+ 			   && (MODES_OK_FOR_MOVE2ADD
+-			       (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
+-			   && reg_base_reg[REGNO (base_reg)] < 0)
++			       (dst_mode, reg_mode[REGNO (base_reg)]))
++			   && reg_base_reg[REGNO (base_reg)] < 0
++			   && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
+ 		    {
+ 		      offset = reg_offset[REGNO (base_reg)];
+ 		      base_reg = XEXP (src, 1);
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99406.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99406.patch
new file mode 100644
index 0000000000..54473fa234
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99406.patch
@@ -0,0 +1,20 @@
+2010-09-28  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/testsuite/
+	2010-09-28  Jie Zhang  <jie@codesourcery.com>
+	* gcc.dg/Wcxx-compat-12.c: Add -fno-short-enums.
+
+=== modified file 'gcc/testsuite/gcc.dg/Wcxx-compat-12.c'
+Index: gcc-4.5/gcc/testsuite/gcc.dg/Wcxx-compat-12.c
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/gcc.dg/Wcxx-compat-12.c
++++ gcc-4.5/gcc/testsuite/gcc.dg/Wcxx-compat-12.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-Wc++-compat" } */
++/* { dg-options "-fno-short-enums -Wc++-compat" } */
+ 
+ enum E { A };
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99407.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99407.patch
new file mode 100644
index 0000000000..80f4246ed2
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99407.patch
@@ -0,0 +1,33 @@
+2010-09-30  Jie Zhang  <jie@codesourcery.com>
+
+	gcc/testsuite/
+
+	* c-c++-common/uninit-17.c: Adjust warning message.
+
+	Backport from mainline:
+
+	2010-07-30  Xinliang David Li  <davidxl@google.com>
+	PR tree-optimization/45121
+	* c-c++-common/uninit-17.c: Add -fno-ivops option.
+
+=== modified file 'gcc/testsuite/c-c++-common/uninit-17.c'
+Index: gcc-4.5/gcc/testsuite/c-c++-common/uninit-17.c
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/c-c++-common/uninit-17.c
++++ gcc-4.5/gcc/testsuite/c-c++-common/uninit-17.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -Wuninitialized" } */
++/* { dg-options "-O2 -Wuninitialized -fno-ivopts" } */
+ 
+ inline int foo(int x)
+ {
+@@ -9,7 +9,7 @@ static void bar(int a, int *ptr)
+ {
+   do
+   {
+-    int b; /* { dg-warning "is used uninitialized" } */
++    int b; /* { dg-warning "may be used uninitialized" } */
+     if (b < 40) {
+       ptr[0] = b;
+     }
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch
new file mode 100644
index 0000000000..1d873ba653
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch
@@ -0,0 +1,603 @@
+2010-10-01  Julian Brown  <julian@codesourcery.com>
+
+	Revert:
+
+	Backport from FSF:
+
+	2010-08-07  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	gcc/
+	* config/arm/linux-atomic.c (SUBWORD_VAL_CAS): Instantiate with
+	'unsigned short' and 'unsigned char' instead of 'short' and
+	'char'. (SUBWORD_BOOL_CAS): Likewise.
+	(SUBWORD_SYNC_OP): Likewise.
+	(SUBWORD_TEST_AND_SET): Likewise.
+	(FETCH_AND_OP_WORD): Parenthesise INF_OP
+	(SUBWORD_SYNC_OP): Likewise.
+	(OP_AND_FETCH_WORD): Likewise.
+
+	gcc/testsuite/
+	* lib/target-supports.exp: (check_effective_target_sync_int_long):
+	Add arm*-*-linux-gnueabi.
+	(check_effective_target_sync_char_short): Likewise.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+Index: gcc-4.5/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm-protos.h
++++ gcc-4.5/gcc/config/arm/arm-protos.h
+@@ -151,11 +151,6 @@ extern const char *vfp_output_fstmd (rtx
+ extern void arm_set_return_address (rtx, rtx);
+ extern int arm_eliminable_register (rtx);
+ extern const char *arm_output_shift(rtx *, int);
+-extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *,
+- 			     rtx, rtx, rtx, rtx);
+-extern const char *arm_output_memory_barrier (rtx *);
+-extern const char *arm_output_sync_insn (rtx, rtx *);
+-extern unsigned int arm_sync_loop_insns (rtx , rtx *);
+ 
+ extern bool arm_output_addr_const_extra (FILE *, rtx);
+ 
+Index: gcc-4.5/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.c
++++ gcc-4.5/gcc/config/arm/arm.c
+@@ -605,7 +605,6 @@ static int thumb_call_reg_needed;
+ #define FL_NEON       (1 << 20)       /* Neon instructions.  */
+ #define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
+ 					 architecture.  */
+-#define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
+ 
+ #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+ 
+@@ -626,7 +625,7 @@ static int thumb_call_reg_needed;
+ #define FL_FOR_ARCH6ZK	FL_FOR_ARCH6K
+ #define FL_FOR_ARCH6T2	(FL_FOR_ARCH6 | FL_THUMB2)
+ #define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
+-#define FL_FOR_ARCH7	((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
++#define FL_FOR_ARCH7	(FL_FOR_ARCH6T2 &~ FL_NOTM)
+ #define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+ #define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_DIV)
+ #define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_DIV)
+@@ -664,9 +663,6 @@ int arm_arch6 = 0;
+ /* Nonzero if this chip supports the ARM 6K extensions.  */
+ int arm_arch6k = 0;
+ 
+-/* Nonzero if this chip supports the ARM 7 extensions.  */
+-int arm_arch7 = 0;
+-
+ /* Nonzero if instructions not present in the 'M' profile can be used.  */
+ int arm_arch_notm = 0;
+ 
+@@ -1638,7 +1634,6 @@ arm_override_options (void)
+   arm_arch6 = (insn_flags & FL_ARCH6) != 0;
+   arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
+   arm_arch_notm = (insn_flags & FL_NOTM) != 0;
+-  arm_arch7 = (insn_flags & FL_ARCH7) != 0;
+   arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
+   arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
+   arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
+@@ -16595,17 +16590,6 @@ arm_print_operand (FILE *stream, rtx x, 
+       }
+       return;
+ 
+-    case 'C':
+-      {
+-	rtx addr;
+-
+-	gcc_assert (GET_CODE (x) == MEM);
+-	addr = XEXP (x, 0);
+-	gcc_assert (GET_CODE (addr) == REG);
+-	asm_fprintf (stream, "[%r]", REGNO (addr));
+-      }
+-      return;
+-
+     /* Translate an S register number into a D register number and element index.  */
+     case 'y':
+       {
+@@ -22840,372 +22824,4 @@ arm_builtin_support_vector_misalignment 
+ 						      is_packed);
+ }
+ 
+-/* Legitimize a memory reference for sync primitive implemented using
+-   ldrex / strex.  We currently force the form of the reference to be
+-   indirect without offset.  We do not yet support the indirect offset
+-   addressing supported by some ARM targets for these
+-   instructions.  */
+-static rtx
+-arm_legitimize_sync_memory (rtx memory)
+-{
+-  rtx addr = force_reg (Pmode, XEXP (memory, 0));
+-  rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr);
+-
+-  set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER);
+-  MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory);
+-  return legitimate_memory;
+-}
+-
+-/* An instruction emitter. */
+-typedef void (* emit_f) (int label, const char *, rtx *);
+-
+-/* An instruction emitter that emits via the conventional
+-   output_asm_insn.  */
+-static void
+-arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands)
+-{
+-  output_asm_insn (pattern, operands);
+-}
+-
+-/* Count the number of emitted synchronization instructions.  */
+-static unsigned arm_insn_count;
+-
+-/* An emitter that counts emitted instructions but does not actually
+-   emit instruction into the the instruction stream.  */
+-static void
+-arm_count (int label,
+-	   const char *pattern ATTRIBUTE_UNUSED,
+-	   rtx *operands ATTRIBUTE_UNUSED)
+-{
+-  if (! label)
+-    ++ arm_insn_count;
+-}
+-
+-/* Construct a pattern using conventional output formatting and feed
+-   it to output_asm_insn.  Provides a mechanism to construct the
+-   output pattern on the fly.  Note the hard limit on the pattern
+-   buffer size.  */
+-static void
+-arm_output_asm_insn (emit_f emit, int label, rtx *operands,
+-		     const char *pattern, ...)
+-{
+-  va_list ap;
+-  char buffer[256];
+-
+-  va_start (ap, pattern);
+-  vsprintf (buffer, pattern, ap);
+-  va_end (ap);
+-  emit (label, buffer, operands);
+-}
+-
+-/* Emit the memory barrier instruction, if any, provided by this
+-   target to a specified emitter.  */
+-static void
+-arm_process_output_memory_barrier (emit_f emit, rtx *operands)
+-{
+-  if (TARGET_HAVE_DMB)
+-    {
+-      /* Note we issue a system level barrier. We should consider
+-         issuing a inner shareabilty zone barrier here instead, ie.
+-         "DMB ISH".  */
+-      emit (0, "dmb\tsy", operands);
+-      return;
+-    }
+-
+-  if (TARGET_HAVE_DMB_MCR)
+-    {
+-      emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands);
+-      return;
+-    }
+-
+-  gcc_unreachable ();
+-}
+-
+-/* Emit the memory barrier instruction, if any, provided by this
+-   target.  */
+-const char *
+-arm_output_memory_barrier (rtx *operands)
+-{
+-  arm_process_output_memory_barrier (arm_emit, operands);
+-  return "";
+-}
+-
+-/* Helper to figure out the instruction suffix required on ldrex/strex
+-   for operations on an object of the specified mode.  */
+-static const char *
+-arm_ldrex_suffix (enum machine_mode mode)
+-{
+-  switch (mode)
+-    {
+-    case QImode: return "b";
+-    case HImode: return "h";
+-    case SImode: return "";
+-    case DImode: return "d";
+-    default:
+-      gcc_unreachable ();
+-    }
+-  return "";
+-}
+-
+-/* Emit an ldrex{b,h,d, } instruction appropriate for the specified
+-   mode.  */
+-static void
+-arm_output_ldrex (emit_f emit,
+-		  enum machine_mode mode,
+-		  rtx target,
+-		  rtx memory)
+-{
+-  const char *suffix = arm_ldrex_suffix (mode);
+-  rtx operands[2];
+-
+-  operands[0] = target;
+-  operands[1] = memory;
+-  arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
+-}
+-
+-/* Emit a strex{b,h,d, } instruction appropriate for the specified
+-   mode.  */
+-static void
+-arm_output_strex (emit_f emit,
+-		  enum machine_mode mode,
+-		  const char *cc,
+-		  rtx result,
+-		  rtx value,
+-		  rtx memory)
+-{
+-  const char *suffix = arm_ldrex_suffix (mode);
+-  rtx operands[3];
+-
+-  operands[0] = result;
+-  operands[1] = value;
+-  operands[2] = memory;
+-  arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix,
+-		       cc);
+-}
+-
+-/* Helper to emit a two operand instruction.  */
+-static void
+-arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s)
+-{
+-  rtx operands[2];
+-
+-  operands[0] = d;
+-  operands[1] = s;
+-  arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic);
+-}
+-
+-/* Helper to emit a three operand instruction.  */
+-static void
+-arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b)
+-{
+-  rtx operands[3];
+-
+-  operands[0] = d;
+-  operands[1] = a;
+-  operands[2] = b;
+-  arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic);
+-}
+-
+-/* Emit a load store exclusive synchronization loop.
+-
+-   do
+-     old_value = [mem]
+-     if old_value != required_value
+-       break;
+-     t1 = sync_op (old_value, new_value)
+-     [mem] = t1, t2 = [0|1]
+-   while ! t2
+-
+-   Note:
+-     t1 == t2 is not permitted
+-     t1 == old_value is permitted
+-
+-   required_value:
+-
+-   RTX register or const_int representing the required old_value for
+-   the modify to continue, if NULL no comparsion is performed.  */
+-static void
+-arm_output_sync_loop (emit_f emit,
+-		      enum machine_mode mode,
+-		      rtx old_value,
+-		      rtx memory,
+-		      rtx required_value,
+-		      rtx new_value,
+-		      rtx t1,
+-		      rtx t2,
+-		      enum attr_sync_op sync_op,
+-		      int early_barrier_required)
+-{
+-  rtx operands[1];
+-
+-  gcc_assert (t1 != t2);
+-
+-  if (early_barrier_required)
+-    arm_process_output_memory_barrier (emit, NULL);
+-
+-  arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX);
+-
+-  arm_output_ldrex (emit, mode, old_value, memory);
+-
+-  if (required_value)
+-    {
+-      rtx operands[2];
+-
+-      operands[0] = old_value;
+-      operands[1] = required_value;
+-      arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1");
+-      arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX);
+-    }
+-
+-  switch (sync_op)
+-    {
+-    case SYNC_OP_ADD:
+-      arm_output_op3 (emit, "add", t1, old_value, new_value);
+-      break;
+-
+-    case SYNC_OP_SUB:
+-      arm_output_op3 (emit, "sub", t1, old_value, new_value);
+-      break;
+-
+-    case SYNC_OP_IOR:
+-      arm_output_op3 (emit, "orr", t1, old_value, new_value);
+-      break;
+-
+-    case SYNC_OP_XOR:
+-      arm_output_op3 (emit, "eor", t1, old_value, new_value);
+-      break;
+-
+-    case SYNC_OP_AND:
+-      arm_output_op3 (emit,"and", t1, old_value, new_value);
+-      break;
+-
+-    case SYNC_OP_NAND:
+-      arm_output_op3 (emit, "and", t1, old_value, new_value);
+-      arm_output_op2 (emit, "mvn", t1, t1);
+-      break;
+-
+-    case SYNC_OP_NONE:
+-      t1 = new_value;
+-      break;
+-    }
+-
+-  arm_output_strex (emit, mode, "", t2, t1, memory);
+-  operands[0] = t2;
+-  arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
+-  arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX);
+-
+-  arm_process_output_memory_barrier (emit, NULL);
+-  arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
+-}
+-
+-static rtx
+-arm_get_sync_operand (rtx *operands, int index, rtx default_value)
+-{
+-  if (index > 0)
+-    default_value = operands[index - 1];
+-
+-  return default_value;
+-}
+-
+-#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \
+-  arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT);
+-
+-/* Extract the operands for a synchroniztion instruction from the
+-   instructions attributes and emit the instruction.  */
+-static void
+-arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands)
+-{
+-  rtx result, memory, required_value, new_value, t1, t2;
+-  int early_barrier;
+-  enum machine_mode mode;
+-  enum attr_sync_op sync_op;
+-
+-  result = FETCH_SYNC_OPERAND(result, 0);
+-  memory = FETCH_SYNC_OPERAND(memory, 0);
+-  required_value = FETCH_SYNC_OPERAND(required_value, 0);
+-  new_value = FETCH_SYNC_OPERAND(new_value, 0);
+-  t1 = FETCH_SYNC_OPERAND(t1, 0);
+-  t2 = FETCH_SYNC_OPERAND(t2, 0);
+-  early_barrier =
+-    get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES;
+-  sync_op = get_attr_sync_op (insn);
+-  mode = GET_MODE (memory);
+-
+-  arm_output_sync_loop (emit, mode, result, memory, required_value,
+-			new_value, t1, t2, sync_op, early_barrier);
+-}
+-
+-/* Emit a synchronization instruction loop.  */
+-const char *
+-arm_output_sync_insn (rtx insn, rtx *operands)
+-{
+-  arm_process_output_sync_insn (arm_emit, insn, operands);
+-  return "";
+-}
+-
+-/* Count the number of machine instruction that will be emitted for a
+-   synchronization instruction.  Note that the emitter used does not
+-   emit instructions, it just counts instructions being carefull not
+-   to count labels.  */
+-unsigned int
+-arm_sync_loop_insns (rtx insn, rtx *operands)
+-{
+-  arm_insn_count = 0;
+-  arm_process_output_sync_insn (arm_count, insn, operands);
+-  return arm_insn_count;
+-}
+-
+-/* Helper to call a target sync instruction generator, dealing with
+-   the variation in operands required by the different generators.  */
+-static rtx
+-arm_call_generator (struct arm_sync_generator *generator, rtx old_value,
+-  		    rtx memory, rtx required_value, rtx new_value)
+-{
+-  switch (generator->op)
+-    {
+-    case arm_sync_generator_omn:
+-      gcc_assert (! required_value);
+-      return generator->u.omn (old_value, memory, new_value);
+-
+-    case arm_sync_generator_omrn:
+-      gcc_assert (required_value);
+-      return generator->u.omrn (old_value, memory, required_value, new_value);
+-    }
+-
+-  return NULL;
+-}
+-
+-/* Expand a synchronization loop. The synchronization loop is expanded
+-   as an opaque block of instructions in order to ensure that we do
+-   not subsequently get extraneous memory accesses inserted within the
+-   critical region. The exclusive access property of ldrex/strex is
+-   only guaranteed in there are no intervening memory accesses. */
+-void
+-arm_expand_sync (enum machine_mode mode,
+-		 struct arm_sync_generator *generator,
+-		 rtx target, rtx memory, rtx required_value, rtx new_value)
+-{
+-  if (target == NULL)
+-    target = gen_reg_rtx (mode);
+-
+-  memory = arm_legitimize_sync_memory (memory);
+-  if (mode != SImode)
+-    {
+-      rtx load_temp = gen_reg_rtx (SImode);
+-
+-      if (required_value)
+-	required_value = convert_modes (SImode, mode, required_value, true);
+-
+-      new_value = convert_modes (SImode, mode, new_value, true);
+-      emit_insn (arm_call_generator (generator, load_temp, memory,
+-				     required_value, new_value));
+-      emit_move_insn (target, gen_lowpart (mode, load_temp));
+-    }
+-  else
+-    {
+-      emit_insn (arm_call_generator (generator, target, memory, required_value,
+-				     new_value));
+-    }
+-}
+-
+ #include "gt-arm.h"
+Index: gcc-4.5/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.h
++++ gcc-4.5/gcc/config/arm/arm.h
+@@ -128,24 +128,6 @@ enum target_cpus
+ /* The processor for which instructions should be scheduled.  */
+ extern enum processor_type arm_tune;
+ 
+-enum arm_sync_generator_tag
+-  {
+-    arm_sync_generator_omn,
+-    arm_sync_generator_omrn
+-  };
+-
+-/* Wrapper to pass around a polymorphic pointer to a sync instruction
+-   generator and.  */
+-struct arm_sync_generator
+-{
+-  enum arm_sync_generator_tag op;
+-  union
+-  {
+-    rtx (* omn) (rtx, rtx, rtx);
+-    rtx (* omrn) (rtx, rtx, rtx, rtx);
+-  } u;
+-};
+-
+ typedef enum arm_cond_code
+ {
+   ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
+@@ -290,20 +272,6 @@ extern void (*arm_lang_output_object_att
+    for Thumb-2.  */
+ #define TARGET_UNIFIED_ASM TARGET_THUMB2
+ 
+-/* Nonzero if this chip provides the DMB instruction.  */
+-#define TARGET_HAVE_DMB		(arm_arch7)
+-
+-/* Nonzero if this chip implements a memory barrier via CP15.  */
+-#define TARGET_HAVE_DMB_MCR	(arm_arch6k && ! TARGET_HAVE_DMB)
+-
+-/* Nonzero if this chip implements a memory barrier instruction.  */
+-#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
+-
+-/* Nonzero if this chip supports ldrex and strex */
+-#define TARGET_HAVE_LDREX	((arm_arch6 && TARGET_ARM) || arm_arch7)
+-
+-/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}.  */
+-#define TARGET_HAVE_LDREXBHD	((arm_arch6k && TARGET_ARM) || arm_arch7)
+ 
+ /* True iff the full BPABI is being used.  If TARGET_BPABI is true,
+    then TARGET_AAPCS_BASED must be true -- but the converse does not
+@@ -437,12 +405,6 @@ extern int arm_arch5e;
+ /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
+ extern int arm_arch6;
+ 
+-/* Nonzero if this chip supports the ARM Architecture 6k extensions.  */
+-extern int arm_arch6k;
+-
+-/* Nonzero if this chip supports the ARM Architecture 7 extensions.  */
+-extern int arm_arch7;
+-
+ /* Nonzero if instructions not present in the 'M' profile can be used.  */
+ extern int arm_arch_notm;
+ 
+Index: gcc-4.5/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.md
++++ gcc-4.5/gcc/config/arm/arm.md
+@@ -103,7 +103,6 @@
+    (UNSPEC_RBIT 26)       ; rbit operation.
+    (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
+                              ; another symbolic address.
+-   (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
+   ]
+ )
+ 
+@@ -140,11 +139,6 @@
+    (VUNSPEC_ALIGN32  16) ; Used to force 32-byte alignment.
+    (VUNSPEC_EH_RETURN 20); Use to override the return address for exception
+ 			 ; handling.
+-   (VUNSPEC_SYNC_COMPARE_AND_SWAP 21)	; Represent an atomic compare swap.
+-   (VUNSPEC_SYNC_LOCK             22)	; Represent a sync_lock_test_and_set.
+-   (VUNSPEC_SYNC_OP               23)	; Represent a sync_<op>
+-   (VUNSPEC_SYNC_NEW_OP           24)	; Represent a sync_new_<op>
+-   (VUNSPEC_SYNC_OLD_OP           25)	; Represent a sync_old_<op>
+   ]
+ )
+ 
+@@ -169,21 +163,8 @@
+ (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
+   (const (symbol_ref "arm_fpu_attr")))
+ 
+-(define_attr "sync_result"          "none,0,1,2,3,4,5" (const_string "none"))
+-(define_attr "sync_memory"          "none,0,1,2,3,4,5" (const_string "none"))
+-(define_attr "sync_required_value"  "none,0,1,2,3,4,5" (const_string "none"))
+-(define_attr "sync_new_value"       "none,0,1,2,3,4,5" (const_string "none"))
+-(define_attr "sync_t1"              "none,0,1,2,3,4,5" (const_string "none"))
+-(define_attr "sync_t2"              "none,0,1,2,3,4,5" (const_string "none"))
+-(define_attr "sync_release_barrier" "yes,no"           (const_string "yes"))
+-(define_attr "sync_op"              "none,add,sub,ior,xor,and,nand"
+-                                    (const_string "none"))
+-
+ ; LENGTH of an instruction (in bytes)
+-(define_attr "length" ""
+-  (cond [(not (eq_attr "sync_memory" "none"))
+- 	   (symbol_ref "arm_sync_loop_insns (insn, operands) * 4")
+-	] (const_int 4)))
++(define_attr "length" "" (const_int 4))
+ 
+ ; POOL_RANGE is how far away from a constant pool entry that this insn
+ ; can be placed.  If the distance is zero, then this insn will never
+@@ -11568,5 +11549,4 @@
+ (include "thumb2.md")
+ ;; Neon patterns
+ (include "neon.md")
+-;; Synchronization Primitives
+-(include "sync.md")
++
+Index: gcc-4.5/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/predicates.md
++++ gcc-4.5/gcc/config/arm/predicates.md
+@@ -573,11 +573,6 @@
+ 		(and (match_test "TARGET_32BIT")
+ 		     (match_operand 0 "arm_di_operand"))))
+ 
+-;; True if the operand is memory reference suitable for a ldrex/strex.
+-(define_predicate "arm_sync_memory_operand"
+-  (and (match_operand 0 "memory_operand")
+-       (match_code "reg" "0")))
+-
+ ;; Predicates for parallel expanders based on mode.
+ (define_special_predicate "vect_par_constant_high" 
+   (match_code "parallel")
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99409.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99409.patch
new file mode 100644
index 0000000000..39c3ab0810
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99409.patch
@@ -0,0 +1,18 @@
+2010-09-30  Jie Zhang  <jie@codesourcery.com>
+
+	gcc/testsuite/
+	* gcc.target/arm/neon-thumb2-move.c: Add
+	dg-require-effective-target arm_thumb2_ok.
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon-thumb2-move.c'
+Index: gcc-4.5/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
++++ gcc-4.5/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
+@@ -1,5 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_neon_ok } */
++/* { dg-require-effective-target arm_thumb2_ok } */
+ /* { dg-options "-O2 -mthumb -march=armv7-a" } */
+ /* { dg-add-options arm_neon } */
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99410.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99410.patch
new file mode 100644
index 0000000000..f2a1c95621
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99410.patch
@@ -0,0 +1,32 @@
+2010-10-06  Julian Brown  <julian@codesourcery.com>
+
+	gcc/testsuite/
+	* gcc.dg/Warray-bounds-3.c: Add -fno-unroll-loops for ARM.
+	* gcc.dg/vect/vect.exp: Likewise, for all vect tests.
+
+
+=== modified file 'gcc/testsuite/gcc.dg/Warray-bounds-3.c'
+Index: gcc-4.5/gcc/testsuite/gcc.dg/Warray-bounds-3.c
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/gcc.dg/Warray-bounds-3.c
++++ gcc-4.5/gcc/testsuite/gcc.dg/Warray-bounds-3.c
+@@ -1,5 +1,7 @@
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -Warray-bounds" } */
++/* { dg-options "-O2 -Warray-bounds -fno-unroll-loops" { target arm*-*-* } } */
++
+ /* based on PR 31227 */
+ 
+ typedef __SIZE_TYPE__ size_t;
+Index: gcc-4.5/gcc/testsuite/gcc.dg/vect/vect.exp
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/gcc.dg/vect/vect.exp
++++ gcc-4.5/gcc/testsuite/gcc.dg/vect/vect.exp
+@@ -109,6 +109,7 @@ if  [istarget "powerpc-*paired*"]  {
+     # default to avoid loss of precision.  We must pass -ffast-math to test
+     # vectorization of float operations.
+     lappend DEFAULT_VECTCFLAGS "-ffast-math"
++    lappend DEFAULT_VECTCFLAGS "-fno-unroll-loops"
+     if [is-effective-target arm_neon_hw] {
+       set dg-do-what-default run
+     } else {
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99411.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99411.patch
new file mode 100644
index 0000000000..c9a9316861
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99411.patch
@@ -0,0 +1,21 @@
+2010-10-08  Jie Zhang  <jie@codesourcery.com>
+
+	* config/arm/arm.c (arm_override_options): Disable
+	-fsched-interblock for Cortex-M4.
+
+=== modified file 'gcc/config/arm/arm.c'
+Index: gcc-4.5/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.c
++++ gcc-4.5/gcc/config/arm/arm.c
+@@ -1913,6 +1913,10 @@ arm_override_options (void)
+ 	fix_cm3_ldrd = 0;
+     }
+ 
++  /* Disable -fsched-interblock for Cortex-M4.  */
++  if (arm_selected_tune->core == cortexm4)
++    flag_schedule_interblock = 0;
++
+   if (TARGET_THUMB1 && flag_schedule_insns)
+     {
+       /* Don't warn since it's on by default in -O2.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99412.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99412.patch
new file mode 100644
index 0000000000..c0aabbeb56
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99412.patch
@@ -0,0 +1,316 @@
+2010-10-09  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/
+	2010-06-03  Paul Brook  <paul@codesourcery.com>
+	* config/arm/arm.c (FL_TUNE): Define.
+	(arm_default_cpu, arm_cpu_select): Remove.
+	(all_cores): Populate core field.
+	(arm_selected_arch, arm_selected_cpu, arm_selected_tune): New.
+	(arm_find_cpu): New function.
+	(arm_handle_option): Lookup cpu/architecture names.
+	(arm_override_options): Cleanup mcpu/march/mtune handling.
+	(arm_file_start): Ditto.
+
+=== modified file 'gcc/config/arm/arm.c'
+Index: gcc-4.5/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.c
++++ gcc-4.5/gcc/config/arm/arm.c
+@@ -550,9 +550,6 @@ enum processor_type arm_tune = arm_none;
+ /* The current tuning set.  */
+ const struct tune_params *current_tune;
+ 
+-/* The default processor used if not overridden by commandline.  */
+-static enum processor_type arm_default_cpu = arm_none;
+-
+ /* Which floating point hardware to schedule for.  */
+ int arm_fpu_attr;
+ 
+@@ -608,6 +605,10 @@ static int thumb_call_reg_needed;
+ 
+ #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+ 
++/* Flags that only effect tuning, not available instructions.  */
++#define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
++			 | FL_CO_PROC)
++
+ #define FL_FOR_ARCH2	FL_NOTM
+ #define FL_FOR_ARCH3	(FL_FOR_ARCH2 | FL_MODE32)
+ #define FL_FOR_ARCH3M	(FL_FOR_ARCH3 | FL_ARCH3M)
+@@ -808,7 +809,7 @@ static const struct processors all_cores
+ {
+   /* ARM Cores */
+ #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
+-  {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
++  {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
+ #include "arm-cores.def"
+ #undef ARM_CORE
+   {NULL, arm_none, NULL, 0, NULL}
+@@ -850,29 +851,12 @@ static const struct processors all_archi
+   {NULL, arm_none, NULL, 0 , NULL}
+ };
+ 
+-struct arm_cpu_select
+-{
+-  const char *              string;
+-  const char *              name;
+-  const struct processors * processors;
+-};
+-
+-/* This is a magic structure.  The 'string' field is magically filled in
+-   with a pointer to the value specified by the user on the command line
+-   assuming that the user has specified such a value.  */
+-
+-static struct arm_cpu_select arm_select[] =
+-{
+-  /* string	  name            processors  */
+-  { NULL,	"-mcpu=",	all_cores  },
+-  { NULL,	"-march=",	all_architectures },
+-  { NULL,	"-mtune=",	all_cores }
+-};
+ 
+-/* Defines representing the indexes into the above table.  */
+-#define ARM_OPT_SET_CPU 0
+-#define ARM_OPT_SET_ARCH 1
+-#define ARM_OPT_SET_TUNE 2
++/* These are populated as commandline arguments are processed, or NULL
++   if not specified.  */
++static const struct processors *arm_selected_arch;
++static const struct processors *arm_selected_cpu;
++static const struct processors *arm_selected_tune;
+ 
+ /* The name of the preprocessor macro to define for this architecture.  */
+ 
+@@ -1234,6 +1218,24 @@ arm_gimplify_va_arg_expr (tree valist, t
+   return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
+ }
+ 
++/* Lookup NAME in SEL.  */
++
++static const struct processors *
++arm_find_cpu (const char *name, const struct processors *sel, const char *desc)
++{
++  if (!(name && *name))
++    return NULL;
++
++  for (; sel->name != NULL; sel++)
++    {
++      if (streq (name, sel->name))
++	return sel;
++    }
++
++  error ("bad value (%s) for %s switch", name, desc);
++  return NULL;
++}
++
+ /* Implement TARGET_HANDLE_OPTION.  */
+ 
+ static bool
+@@ -1242,11 +1244,11 @@ arm_handle_option (size_t code, const ch
+   switch (code)
+     {
+     case OPT_march_:
+-      arm_select[1].string = arg;
++      arm_selected_arch = arm_find_cpu(arg, all_architectures, "-march");
+       return true;
+ 
+     case OPT_mcpu_:
+-      arm_select[0].string = arg;
++      arm_selected_cpu = arm_find_cpu(arg, all_cores, "-mcpu");
+       return true;
+ 
+     case OPT_mhard_float:
+@@ -1258,7 +1260,7 @@ arm_handle_option (size_t code, const ch
+       return true;
+ 
+     case OPT_mtune_:
+-      arm_select[2].string = arg;
++      arm_selected_tune = arm_find_cpu(arg, all_cores, "-mtune");
+       return true;
+ 
+     default:
+@@ -1358,88 +1360,52 @@ void
+ arm_override_options (void)
+ {
+   unsigned i;
+-  enum processor_type target_arch_cpu = arm_none;
+-  enum processor_type selected_cpu = arm_none;
+ 
+-  /* Set up the flags based on the cpu/architecture selected by the user.  */
+-  for (i = ARRAY_SIZE (arm_select); i--;)
++  if (arm_selected_arch)
+     {
+-      struct arm_cpu_select * ptr = arm_select + i;
+-
+-      if (ptr->string != NULL && ptr->string[0] != '\0')
+-        {
+-	  const struct processors * sel;
+-
+-          for (sel = ptr->processors; sel->name != NULL; sel++)
+-            if (streq (ptr->string, sel->name))
+-              {
+-		/* Set the architecture define.  */
+-		if (i != ARM_OPT_SET_TUNE)
+-		  sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
+-
+-		/* Determine the processor core for which we should
+-		   tune code-generation.  */
+-		if (/* -mcpu= is a sensible default.  */
+-		    i == ARM_OPT_SET_CPU
+-		    /* -mtune= overrides -mcpu= and -march=.  */
+-		    || i == ARM_OPT_SET_TUNE)
+-		  arm_tune = (enum processor_type) (sel - ptr->processors);
+-
+-		/* Remember the CPU associated with this architecture.
+-		   If no other option is used to set the CPU type,
+-		   we'll use this to guess the most suitable tuning
+-		   options.  */
+-		if (i == ARM_OPT_SET_ARCH)
+-		  target_arch_cpu = sel->core;
+-
+-		if (i == ARM_OPT_SET_CPU)
+-		  selected_cpu = (enum processor_type) (sel - ptr->processors);
+-		  
+-		if (i != ARM_OPT_SET_TUNE)
+-		  {
+-		    /* If we have been given an architecture and a processor
+-		       make sure that they are compatible.  We only generate
+-		       a warning though, and we prefer the CPU over the
+-		       architecture.  */
+-		    if (insn_flags != 0 && (insn_flags ^ sel->flags))
+-		      warning (0, "switch -mcpu=%s conflicts with -march= switch",
+-			       ptr->string);
+-
+-		    insn_flags = sel->flags;
+-		  }
+-
+-                break;
+-              }
++      if (arm_selected_cpu)
++	{
++	  /* Check for conflict between mcpu and march */
++	  if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE)
++	    {
++	      warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
++		       arm_selected_cpu->name, arm_selected_arch->name);
++	      /* -march wins for code generation.
++	         -mcpu wins for default tuning.  */
++	      if (!arm_selected_tune)
++		arm_selected_tune = arm_selected_cpu;
+ 
+-          if (sel->name == NULL)
+-            error ("bad value (%s) for %s switch", ptr->string, ptr->name);
+-        }
++	      arm_selected_cpu = arm_selected_arch;
++	    }
++	  else
++	    /* -mcpu wins.  */
++	    arm_selected_arch = NULL;
++	}
++      else
++	/* Pick a CPU based on the architecture.  */
++	arm_selected_cpu = arm_selected_arch;
+     }
+ 
+-  /* Guess the tuning options from the architecture if necessary.  */
+-  if (arm_tune == arm_none)
+-    arm_tune = target_arch_cpu;
+-
+   /* If the user did not specify a processor, choose one for them.  */
+-  if (insn_flags == 0)
++  if (!arm_selected_cpu)
+     {
+       const struct processors * sel;
+       unsigned int        sought;
+ 
+-      selected_cpu = (enum processor_type) TARGET_CPU_DEFAULT;
+-      if (selected_cpu == arm_none)
++      arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
++      if (!arm_selected_cpu->name)
+ 	{
+ #ifdef SUBTARGET_CPU_DEFAULT
+ 	  /* Use the subtarget default CPU if none was specified by
+ 	     configure.  */
+-	  selected_cpu = (enum processor_type) SUBTARGET_CPU_DEFAULT;
++	  arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT];
+ #endif
+ 	  /* Default to ARM6.  */
+-	  if (selected_cpu == arm_none)
+-	    selected_cpu = arm6;
++	  if (arm_selected_cpu->name)
++	    arm_selected_cpu = &all_cores[arm6];
+ 	}
+-      sel = &all_cores[selected_cpu];
+ 
++      sel = arm_selected_cpu;
+       insn_flags = sel->flags;
+ 
+       /* Now check to see if the user has specified some command line
+@@ -1500,17 +1466,21 @@ arm_override_options (void)
+ 	      sel = best_fit;
+ 	    }
+ 
+-	  insn_flags = sel->flags;
++	  arm_selected_cpu = sel;
+ 	}
+-      sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
+-      arm_default_cpu = (enum processor_type) (sel - all_cores);
+-      if (arm_tune == arm_none)
+-	arm_tune = arm_default_cpu;
+     }
+ 
+-  /* The processor for which we should tune should now have been
+-     chosen.  */
+-  gcc_assert (arm_tune != arm_none);
++  gcc_assert (arm_selected_cpu);
++  /* The selected cpu may be an architecture, so lookup tuning by core ID.  */
++  if (!arm_selected_tune)
++    arm_selected_tune = &all_cores[arm_selected_cpu->core];
++
++  sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch);
++  insn_flags = arm_selected_cpu->flags;
++
++  arm_tune = arm_selected_tune->core;
++  tune_flags = arm_selected_tune->flags;
++  current_tune = arm_selected_tune->tune;
+ 
+   if (arm_tune == cortexa8 && optimize >= 3)
+     {
+@@ -1522,9 +1492,6 @@ arm_override_options (void)
+ 	align_jumps = 16;
+     }
+ 
+-  tune_flags = all_cores[(int)arm_tune].flags;
+-  current_tune = all_cores[(int)arm_tune].tune;
+-
+   if (target_fp16_format_name)
+     {
+       for (i = 0; i < ARRAY_SIZE (all_fp16_formats); i++)
+@@ -1907,7 +1874,7 @@ arm_override_options (void)
+   /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores.  */
+   if (fix_cm3_ldrd == 2)
+     {
+-      if (selected_cpu == cortexm3)
++      if (arm_selected_cpu->core == cortexm3)
+ 	fix_cm3_ldrd = 1;
+       else
+ 	fix_cm3_ldrd = 0;
+@@ -21235,13 +21202,10 @@ arm_file_start (void)
+   if (TARGET_BPABI)
+     {
+       const char *fpu_name;
+-      if (arm_select[0].string)
+-	asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
+-      else if (arm_select[1].string)
+-	asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
++      if (arm_selected_arch)
++	asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
+       else
+-	asm_fprintf (asm_out_file, "\t.cpu %s\n",
+-		     all_cores[arm_default_cpu].name);
++	asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
+ 
+       if (TARGET_SOFT_FLOAT)
+ 	{
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch
new file mode 100644
index 0000000000..3f873e7fe6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch
@@ -0,0 +1,26 @@
+2010-10-13  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-04-20  James E. Wilson  <wilson@codesourcery.com>
+
+	gcc/
+	PR rtl-optimization/43520
+	* ira-lives.c (ira_implicitly_set_insn_hard_regs): Exclude classes with
+	zero available registers.
+
+=== modified file 'gcc/ira-lives.c'
+Index: gcc-4.5/gcc/ira-lives.c
+===================================================================
+--- gcc-4.5.orig/gcc/ira-lives.c
++++ gcc-4.5/gcc/ira-lives.c
+@@ -805,6 +805,9 @@ ira_implicitly_set_insn_hard_regs (HARD_
+ 			? GENERAL_REGS
+ 			: REG_CLASS_FROM_CONSTRAINT (c, p));
+ 		  if (cl != NO_REGS
++		      /* There is no register pressure problem if all of the
++			 regs in this class are fixed.  */
++		      && ira_available_class_regs[cl] != 0
+ 		      && (ira_available_class_regs[cl]
+ 			  <= ira_reg_class_nregs[cl][mode]))
+ 		    IOR_HARD_REG_SET (*set, reg_class_contents[cl]);
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99415.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99415.patch
new file mode 100644
index 0000000000..3622ac4238
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99415.patch
@@ -0,0 +1,46 @@
+2010-10-13  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Issue #8615
+
+	Backport from mainline:
+
+	2010-10-12  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.h (ARM_EXPAND_ALIGNMENT): Rename from
+	DATA_ALIGNMENT and add COND parameter. Update comments above.
+	(DATA_ALIGNMENT): Use ARM_EXPAND_ALIGNMENT, with !optimize_size.
+	(LOCAL_ALIGNMENT): Use ARM_EXPAND_ALIGNMENT, with
+	!flag_conserve_stack.
+
+=== modified file 'gcc/config/arm/arm.h'
+Index: gcc-4.5/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.h
++++ gcc-4.5/gcc/config/arm/arm.h
+@@ -596,15 +596,21 @@ extern int low_irq_latency;
+ /* Align definitions of arrays, unions and structures so that
+    initializations and copies can be made more efficient.  This is not
+    ABI-changing, so it only affects places where we can see the
+-   definition.  */
+-#define DATA_ALIGNMENT(EXP, ALIGN)					\
+-  ((((ALIGN) < BITS_PER_WORD)                                           \
++   definition. Increasing the alignment tends to introduce padding,
++   so don't do this when optimizing for size/conserving stack space. */
++#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN)				\
++  (((COND) && ((ALIGN) < BITS_PER_WORD)					\
+     && (TREE_CODE (EXP) == ARRAY_TYPE					\
+ 	|| TREE_CODE (EXP) == UNION_TYPE				\
+ 	|| TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
+ 
++/* Align global data. */
++#define DATA_ALIGNMENT(EXP, ALIGN)			\
++  ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
++
+ /* Similarly, make sure that objects on the stack are sensibly aligned.  */
+-#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
++#define LOCAL_ALIGNMENT(EXP, ALIGN)				\
++  ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
+ 
+ /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
+    value set in previous versions of this toolchain was 8, which produces more
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch
new file mode 100644
index 0000000000..72a221b1d2
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch
@@ -0,0 +1,130 @@
+2010-10-15  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-10-15  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* ifcvt.c (find_active_insn_before): New function.
+	(find_active_insn_after): New function.
+	(cond_exec_process_if_block): Use new functions to replace
+	prev_active_insn() and next_active_insn().
+
+	gcc/testsuite/
+	* gcc.dg/20101010-1.c: New testcase.
+
+=== modified file 'gcc/ifcvt.c'
+Index: gcc-4.5/gcc/ifcvt.c
+===================================================================
+--- gcc-4.5.orig/gcc/ifcvt.c
++++ gcc-4.5/gcc/ifcvt.c
+@@ -88,6 +88,8 @@ static int count_bb_insns (const_basic_b
+ static bool cheap_bb_rtx_cost_p (const_basic_block, int);
+ static rtx first_active_insn (basic_block);
+ static rtx last_active_insn (basic_block, int);
++static rtx find_active_insn_before (basic_block, rtx);
++static rtx find_active_insn_after (basic_block, rtx);
+ static basic_block block_fallthru (basic_block);
+ static int cond_exec_process_insns (ce_if_block_t *, rtx, rtx, rtx, rtx, int);
+ static rtx cond_exec_get_condition (rtx);
+@@ -230,6 +232,48 @@ last_active_insn (basic_block bb, int sk
+   return insn;
+ }
+ 
++/* Return the active insn before INSN inside basic block CURR_BB. */
++
++static rtx
++find_active_insn_before (basic_block curr_bb, rtx insn)
++{
++  if (!insn || insn == BB_HEAD (curr_bb))
++    return NULL_RTX;
++
++  while ((insn = PREV_INSN (insn)) != NULL_RTX)
++    {
++      if (NONJUMP_INSN_P (insn) || JUMP_P (insn) || CALL_P (insn))
++        break;
++
++      /* No other active insn all the way to the start of the basic block. */
++      if (insn == BB_HEAD (curr_bb))
++        return NULL_RTX;
++    }
++
++  return insn;
++}
++
++/* Return the active insn after INSN inside basic block CURR_BB. */
++
++static rtx
++find_active_insn_after (basic_block curr_bb, rtx insn)
++{
++  if (!insn || insn == BB_END (curr_bb))
++    return NULL_RTX;
++
++  while ((insn = NEXT_INSN (insn)) != NULL_RTX)
++    {
++      if (NONJUMP_INSN_P (insn) || JUMP_P (insn) || CALL_P (insn))
++        break;
++
++      /* No other active insn all the way to the end of the basic block. */
++      if (insn == BB_END (curr_bb))
++        return NULL_RTX;
++    }
++
++  return insn;
++}
++
+ /* Return the basic block reached by falling though the basic block BB.  */
+ 
+ static basic_block
+@@ -448,9 +492,9 @@ cond_exec_process_if_block (ce_if_block_
+       if (n_matching > 0)
+ 	{
+ 	  if (then_end)
+-	    then_end = prev_active_insn (then_first_tail);
++	    then_end = find_active_insn_before (then_bb, then_first_tail);
+ 	  if (else_end)
+-	    else_end = prev_active_insn (else_first_tail);
++	    else_end = find_active_insn_before (else_bb, else_first_tail);
+ 	  n_insns -= 2 * n_matching;
+ 	}
+ 
+@@ -488,9 +532,9 @@ cond_exec_process_if_block (ce_if_block_
+ 	  if (n_matching > 0)
+ 	    {
+ 	      if (then_start)
+-		then_start = next_active_insn (then_last_head);
++		then_start = find_active_insn_after (then_bb, then_last_head);
+ 	      if (else_start)
+-		else_start = next_active_insn (else_last_head);
++		else_start = find_active_insn_after (else_bb, else_last_head);
+ 	      n_insns -= 2 * n_matching;
+ 	    }
+ 	}
+@@ -646,7 +690,7 @@ cond_exec_process_if_block (ce_if_block_
+     {
+       rtx from = then_first_tail;
+       if (!INSN_P (from))
+-	from = next_active_insn (from);
++	from = find_active_insn_after (then_bb, from);
+       delete_insn_chain (from, BB_END (then_bb), false);
+     }
+   if (else_last_head)
+Index: gcc-4.5/gcc/testsuite/gcc.dg/20101010-1.c
+===================================================================
+--- /dev/null
++++ gcc-4.5/gcc/testsuite/gcc.dg/20101010-1.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-crossjumping" } */
++
++int foo (void)
++{
++  int len;
++  if (bar1 (&len))
++    {
++      char devpath [len];
++      if (bar2 (devpath) == len)
++        return len;
++    }
++  return -1;
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch
new file mode 100644
index 0000000000..2ad7e69681
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch
@@ -0,0 +1,53 @@
+2010-10-15  Jie Zhang  <jie@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/testsuite/
+	2010-10-15  Jie Zhang  <jie@codesourcery.com>
+
+	* lib/lto.exp (lto-link-and-maybe-run): Use the default linker
+	script when relocatable linking.
+
+=== modified file 'gcc/testsuite/lib/lto.exp'
+Index: gcc-4.5/gcc/testsuite/lib/lto.exp
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/lib/lto.exp
++++ gcc-4.5/gcc/testsuite/lib/lto.exp
+@@ -156,6 +156,7 @@ proc lto-link-and-maybe-run { testname o
+     global testcase
+     global tool
+     global compile_type
++    global board_info
+ 
+     # Check that all of the objects were built successfully.
+     foreach obj [split $objlist] {
+@@ -170,10 +171,29 @@ proc lto-link-and-maybe-run { testname o
+     set options ""
+     lappend options "additional_flags=$optall $optfile"
+ 
++    set target_board [target_info name]
++    set relocatable 0
++
++    # Some LTO tests do relocatable linking. Some target boards set
++    # a linker script which can't be used for relocatable linking.
++    # Use the default linker script instead.
++    if { [lsearch -exact [split "$optall $optfile"] "-r"] >= 0 } {
++	set relocatable 1
++    }
++
++    if { $relocatable } {
++	set saved_ldscript [board_info $target_board ldscript]
++	set board_info($target_board,ldscript) ""
++    }
++
+     # Link the objects into an executable.
+     set comp_output [${tool}_target_compile "$objlist" $dest executable \
+ 		     "$options"]
+ 
++    if { $relocatable } {
++	set board_info($target_board,ldscript) $saved_ldscript
++    }
++
+     # Prune unimportant visibility warnings before checking output.
+     set comp_output [lto_prune_warns $comp_output]
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch
new file mode 100644
index 0000000000..3ea7956f0f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch
@@ -0,0 +1,25 @@
+2010-10-20  Yao Qi  <yao@codesourcery.com>
+
+	Merge from Sourcery G++ to fix LP:660021
+	2010-10-18  Paul Brook  <paul@codesourcery.com>
+
+	* tree-vect-stmts.c (supportable_widening_operation): Check if wide
+	vector type exists.
+
+=== modified file 'gcc/tree-vect-stmts.c'
+Index: gcc-4.5/gcc/tree-vect-stmts.c
+===================================================================
+--- gcc-4.5.orig/gcc/tree-vect-stmts.c
++++ gcc-4.5/gcc/tree-vect-stmts.c
+@@ -4867,6 +4867,11 @@ supportable_widening_operation (enum tre
+   tree wide_vectype = get_vectype_for_scalar_type (type);
+   enum tree_code c1, c2;
+ 
++  /* Check we have a valid vector type for the result.  */
++  if (!wide_vectype)
++    return false;
++
++
+   /* The result of a vectorized widening operation usually requires two vectors
+      (because the widened results do not fit int one vector). The generated
+      vector results would normally be expected to be generated in the same
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch
new file mode 100644
index 0000000000..cb434082bf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch
@@ -0,0 +1,734 @@
+2010-10-22  Julian Brown  <julian@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-10-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	gcc/testsuite/
+	* gcc.target/arm/synchronize.c: Permit dmb or mcr in assembler scan.
+
+2010-10-14  Julian Brown  <julian@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	gcc/
+	* config/arm/arm-protos.h (arm_expand_sync): New.
+	(arm_output_memory_barrier, arm_output_sync_insn): New.
+	(arm_sync_loop_insns): New.
+	* config/arm/arm.c (FL_ARCH7): New.
+	(FL_FOR_ARCH7): Include FL_ARCH7.
+	(arm_arch7): New.
+	(arm_print_operand): Support %C markup.
+	(arm_legitimize_sync_memory): New.
+	(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
+	(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
+	(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
+	(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
+	(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
+	(arm_process_output_sync_insn, arm_output_sync_insn): New.
+	(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
+	* config/arm/arm.h (struct arm_sync_generator): New.
+	(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
+	(TARGET_HAVE_MEMORY_BARRIER): New.
+	(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
+	* config/arm/arm.md: Include sync.md.
+	(UNSPEC_MEMORY_BARRIER): New.
+	(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
+	(VUNSPEC_SYNC_OP):New.
+	(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
+	(sync_result, sync_memory, sync_required_value): New attributes.
+	(sync_new_value, sync_t1, sync_t2): Likewise.
+	(sync_release_barrier, sync_op): Likewise.
+	(length): Add logic to length attribute defintion to call
+	arm_sync_loop_insns when appropriate.
+	* config/arm/sync.md: New file.
+
+	2010-09-02  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	gcc/
+	* config/arm/predicates.md (arm_sync_memory_operand): New.
+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate
+	to arm_sync_memory_operand and constraint to Q.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_lock_test_and_setsi): Likewise.
+	(arm_sync_lock_test_and_set<mode>): Likewise.
+	(arm_sync_new_<sync_optab>si): Likewise.
+	(arm_sync_new_nandsi): Likewise.
+	(arm_sync_new_<sync_optab><mode>): Likewise.
+	(arm_sync_new_nand<mode>): Likewise.
+	(arm_sync_old_<sync_optab>si): Likewise.
+	(arm_sync_old_nandsi): Likewise.
+	(arm_sync_old_<sync_optab><mode>): Likewise.
+	(arm_sync_old_nand<mode>): Likewise.
+
+	2010-09-13  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	gcc/
+	* config/arm/arm.md: (define_attr "conds"): Update comment.
+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change
+	conds attribute to clob.
+	(arm_sync_compare_and_swapsi): Likewise.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_lock_test_and_setsi): Likewise.
+	(arm_sync_lock_test_and_set<mode>): Likewise.
+	(arm_sync_new_<sync_optab>si): Likewise.
+	(arm_sync_new_nandsi): Likewise.
+	(arm_sync_new_<sync_optab><mode>): Likewise.
+	(arm_sync_new_nand<mode>): Likewise.
+	(arm_sync_old_<sync_optab>si): Likewise.
+	(arm_sync_old_nandsi): Likewise.
+	(arm_sync_old_<sync_optab><mode>): Likewise.
+	(arm_sync_old_nand<mode>): Likewise.
+
+	2010-09-13  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+	gcc/testsuite/
+	* gcc.target/arm/sync-1.c: New.
+
+ 
+ 	Backport from FSF:
+ 
+	gcc/
+	2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	* config/arm/arm-protos.h (arm_expand_sync): New.
+	(arm_output_memory_barrier, arm_output_sync_insn): New.
+	(arm_sync_loop_insns): New.
+	* config/arm/arm.c (FL_ARCH7): New.
+	(FL_FOR_ARCH7): Include FL_ARCH7.
+	(arm_arch7): New.
+	(arm_print_operand): Support %C markup.
+	(arm_legitimize_sync_memory): New.
+	(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
+	(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
+	(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
+	(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
+	(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
+	(arm_process_output_sync_insn, arm_output_sync_insn): New.
+	(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
+	* config/arm/arm.h (struct arm_sync_generator): New.
+	(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
+	(TARGET_HAVE_MEMORY_BARRIER): New.
+	(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
+	* config/arm/arm.md: Include sync.md.
+	(UNSPEC_MEMORY_BARRIER): New.
+	(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
+	(VUNSPEC_SYNC_OP):New.
+	(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
+	(sync_result, sync_memory, sync_required_value): New attributes.
+	(sync_new_value, sync_t1, sync_t2): Likewise.
+	(sync_release_barrier, sync_op): Likewise.
+	(length): Add logic to length attribute defintion to call
+	arm_sync_loop_insns when appropriate.
+	* config/arm/sync.md: New file.
+
+	gcc/
+	2010-09-02  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	* config/arm/predicates.md (arm_sync_memory_operand): New.
+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate
+	to arm_sync_memory_operand and constraint to Q.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_lock_test_and_setsi): Likewise.
+	(arm_sync_lock_test_and_set<mode>): Likewise.
+	(arm_sync_new_<sync_optab>si): Likewise.
+	(arm_sync_new_nandsi): Likewise.
+	(arm_sync_new_<sync_optab><mode>): Likewise.
+	(arm_sync_new_nand<mode>): Likewise.
+	(arm_sync_old_<sync_optab>si): Likewise.
+	(arm_sync_old_nandsi): Likewise.
+	(arm_sync_old_<sync_optab><mode>): Likewise.
+	(arm_sync_old_nand<mode>): Likewise.
+ 
+=== modified file 'gcc/config/arm/arm-protos.h'
+Index: gcc-4.5/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm-protos.h
++++ gcc-4.5/gcc/config/arm/arm-protos.h
+@@ -151,6 +151,11 @@ extern const char *vfp_output_fstmd (rtx
+ extern void arm_set_return_address (rtx, rtx);
+ extern int arm_eliminable_register (rtx);
+ extern const char *arm_output_shift(rtx *, int);
++extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *,
++ 			     rtx, rtx, rtx, rtx);
++extern const char *arm_output_memory_barrier (rtx *);
++extern const char *arm_output_sync_insn (rtx, rtx *);
++extern unsigned int arm_sync_loop_insns (rtx , rtx *);
+ 
+ extern bool arm_output_addr_const_extra (FILE *, rtx);
+ 
+Index: gcc-4.5/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.c
++++ gcc-4.5/gcc/config/arm/arm.c
+@@ -602,6 +602,7 @@ static int thumb_call_reg_needed;
+ #define FL_NEON       (1 << 20)       /* Neon instructions.  */
+ #define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
+ 					 architecture.  */
++#define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
+ 
+ #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+ 
+@@ -626,7 +627,7 @@ static int thumb_call_reg_needed;
+ #define FL_FOR_ARCH6ZK	FL_FOR_ARCH6K
+ #define FL_FOR_ARCH6T2	(FL_FOR_ARCH6 | FL_THUMB2)
+ #define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
+-#define FL_FOR_ARCH7	(FL_FOR_ARCH6T2 &~ FL_NOTM)
++#define FL_FOR_ARCH7	((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
+ #define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+ #define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_DIV)
+ #define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_DIV)
+@@ -664,6 +665,9 @@ int arm_arch6 = 0;
+ /* Nonzero if this chip supports the ARM 6K extensions.  */
+ int arm_arch6k = 0;
+ 
++/* Nonzero if this chip supports the ARM 7 extensions.  */
++int arm_arch7 = 0;
++
+ /* Nonzero if instructions not present in the 'M' profile can be used.  */
+ int arm_arch_notm = 0;
+ 
+@@ -1602,6 +1606,7 @@ arm_override_options (void)
+   arm_arch6 = (insn_flags & FL_ARCH6) != 0;
+   arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
+   arm_arch_notm = (insn_flags & FL_NOTM) != 0;
++  arm_arch7 = (insn_flags & FL_ARCH7) != 0;
+   arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
+   arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
+   arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
+@@ -16562,6 +16567,17 @@ arm_print_operand (FILE *stream, rtx x,
+       }
+       return;
+ 
++    case 'C':
++      {
++	rtx addr;
++
++	gcc_assert (GET_CODE (x) == MEM);
++	addr = XEXP (x, 0);
++	gcc_assert (GET_CODE (addr) == REG);
++	asm_fprintf (stream, "[%r]", REGNO (addr));
++      }
++      return;
++
+     /* Translate an S register number into a D register number and element index.  */
+     case 'y':
+       {
+@@ -22793,4 +22809,372 @@ arm_builtin_support_vector_misalignment
+ 						      is_packed);
+ }
+ 
++/* Legitimize a memory reference for sync primitive implemented using
++   ldrex / strex.  We currently force the form of the reference to be
++   indirect without offset.  We do not yet support the indirect offset
++   addressing supported by some ARM targets for these
++   instructions.  */
++static rtx
++arm_legitimize_sync_memory (rtx memory)
++{
++  rtx addr = force_reg (Pmode, XEXP (memory, 0));
++  rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr);
++
++  set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER);
++  MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory);
++  return legitimate_memory;
++}
++
++/* An instruction emitter. */
++typedef void (* emit_f) (int label, const char *, rtx *);
++
++/* An instruction emitter that emits via the conventional
++   output_asm_insn.  */
++static void
++arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands)
++{
++  output_asm_insn (pattern, operands);
++}
++
++/* Count the number of emitted synchronization instructions.  */
++static unsigned arm_insn_count;
++
++/* An emitter that counts emitted instructions but does not actually
++   emit instruction into the the instruction stream.  */
++static void
++arm_count (int label,
++	   const char *pattern ATTRIBUTE_UNUSED,
++	   rtx *operands ATTRIBUTE_UNUSED)
++{
++  if (! label)
++    ++ arm_insn_count;
++}
++
++/* Construct a pattern using conventional output formatting and feed
++   it to output_asm_insn.  Provides a mechanism to construct the
++   output pattern on the fly.  Note the hard limit on the pattern
++   buffer size.  */
++static void
++arm_output_asm_insn (emit_f emit, int label, rtx *operands,
++		     const char *pattern, ...)
++{
++  va_list ap;
++  char buffer[256];
++
++  va_start (ap, pattern);
++  vsprintf (buffer, pattern, ap);
++  va_end (ap);
++  emit (label, buffer, operands);
++}
++
++/* Emit the memory barrier instruction, if any, provided by this
++   target to a specified emitter.  */
++static void
++arm_process_output_memory_barrier (emit_f emit, rtx *operands)
++{
++  if (TARGET_HAVE_DMB)
++    {
++      /* Note we issue a system level barrier. We should consider
++         issuing a inner shareabilty zone barrier here instead, ie.
++         "DMB ISH".  */
++      emit (0, "dmb\tsy", operands);
++      return;
++    }
++
++  if (TARGET_HAVE_DMB_MCR)
++    {
++      emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands);
++      return;
++    }
++
++  gcc_unreachable ();
++}
++
++/* Emit the memory barrier instruction, if any, provided by this
++   target.  */
++const char *
++arm_output_memory_barrier (rtx *operands)
++{
++  arm_process_output_memory_barrier (arm_emit, operands);
++  return "";
++}
++
++/* Helper to figure out the instruction suffix required on ldrex/strex
++   for operations on an object of the specified mode.  */
++static const char *
++arm_ldrex_suffix (enum machine_mode mode)
++{
++  switch (mode)
++    {
++    case QImode: return "b";
++    case HImode: return "h";
++    case SImode: return "";
++    case DImode: return "d";
++    default:
++      gcc_unreachable ();
++    }
++  return "";
++}
++
++/* Emit an ldrex{b,h,d, } instruction appropriate for the specified
++   mode.  */
++static void
++arm_output_ldrex (emit_f emit,
++		  enum machine_mode mode,
++		  rtx target,
++		  rtx memory)
++{
++  const char *suffix = arm_ldrex_suffix (mode);
++  rtx operands[2];
++
++  operands[0] = target;
++  operands[1] = memory;
++  arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
++}
++
++/* Emit a strex{b,h,d, } instruction appropriate for the specified
++   mode.  */
++static void
++arm_output_strex (emit_f emit,
++		  enum machine_mode mode,
++		  const char *cc,
++		  rtx result,
++		  rtx value,
++		  rtx memory)
++{
++  const char *suffix = arm_ldrex_suffix (mode);
++  rtx operands[3];
++
++  operands[0] = result;
++  operands[1] = value;
++  operands[2] = memory;
++  arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix,
++		       cc);
++}
++
++/* Helper to emit a two operand instruction.  */
++static void
++arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s)
++{
++  rtx operands[2];
++
++  operands[0] = d;
++  operands[1] = s;
++  arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic);
++}
++
++/* Helper to emit a three operand instruction.  */
++static void
++arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b)
++{
++  rtx operands[3];
++
++  operands[0] = d;
++  operands[1] = a;
++  operands[2] = b;
++  arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic);
++}
++
++/* Emit a load store exclusive synchronization loop.
++
++   do
++     old_value = [mem]
++     if old_value != required_value
++       break;
++     t1 = sync_op (old_value, new_value)
++     [mem] = t1, t2 = [0|1]
++   while ! t2
++
++   Note:
++     t1 == t2 is not permitted
++     t1 == old_value is permitted
++
++   required_value:
++
++   RTX register or const_int representing the required old_value for
++   the modify to continue, if NULL no comparsion is performed.  */
++static void
++arm_output_sync_loop (emit_f emit,
++		      enum machine_mode mode,
++		      rtx old_value,
++		      rtx memory,
++		      rtx required_value,
++		      rtx new_value,
++		      rtx t1,
++		      rtx t2,
++		      enum attr_sync_op sync_op,
++		      int early_barrier_required)
++{
++  rtx operands[1];
++
++  gcc_assert (t1 != t2);
++
++  if (early_barrier_required)
++    arm_process_output_memory_barrier (emit, NULL);
++
++  arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX);
++
++  arm_output_ldrex (emit, mode, old_value, memory);
++
++  if (required_value)
++    {
++      rtx operands[2];
++
++      operands[0] = old_value;
++      operands[1] = required_value;
++      arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1");
++      arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX);
++    }
++
++  switch (sync_op)
++    {
++    case SYNC_OP_ADD:
++      arm_output_op3 (emit, "add", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_SUB:
++      arm_output_op3 (emit, "sub", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_IOR:
++      arm_output_op3 (emit, "orr", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_XOR:
++      arm_output_op3 (emit, "eor", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_AND:
++      arm_output_op3 (emit,"and", t1, old_value, new_value);
++      break;
++
++    case SYNC_OP_NAND:
++      arm_output_op3 (emit, "and", t1, old_value, new_value);
++      arm_output_op2 (emit, "mvn", t1, t1);
++      break;
++
++    case SYNC_OP_NONE:
++      t1 = new_value;
++      break;
++    }
++
++  arm_output_strex (emit, mode, "", t2, t1, memory);
++  operands[0] = t2;
++  arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
++  arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX);
++
++  arm_process_output_memory_barrier (emit, NULL);
++  arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
++}
++
++static rtx
++arm_get_sync_operand (rtx *operands, int index, rtx default_value)
++{
++  if (index > 0)
++    default_value = operands[index - 1];
++
++  return default_value;
++}
++
++#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \
++  arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT);
++
++/* Extract the operands for a synchroniztion instruction from the
++   instructions attributes and emit the instruction.  */
++static void
++arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands)
++{
++  rtx result, memory, required_value, new_value, t1, t2;
++  int early_barrier;
++  enum machine_mode mode;
++  enum attr_sync_op sync_op;
++
++  result = FETCH_SYNC_OPERAND(result, 0);
++  memory = FETCH_SYNC_OPERAND(memory, 0);
++  required_value = FETCH_SYNC_OPERAND(required_value, 0);
++  new_value = FETCH_SYNC_OPERAND(new_value, 0);
++  t1 = FETCH_SYNC_OPERAND(t1, 0);
++  t2 = FETCH_SYNC_OPERAND(t2, 0);
++  early_barrier =
++    get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES;
++  sync_op = get_attr_sync_op (insn);
++  mode = GET_MODE (memory);
++
++  arm_output_sync_loop (emit, mode, result, memory, required_value,
++			new_value, t1, t2, sync_op, early_barrier);
++}
++
++/* Emit a synchronization instruction loop.  */
++const char *
++arm_output_sync_insn (rtx insn, rtx *operands)
++{
++  arm_process_output_sync_insn (arm_emit, insn, operands);
++  return "";
++}
++
++/* Count the number of machine instruction that will be emitted for a
++   synchronization instruction.  Note that the emitter used does not
++   emit instructions, it just counts instructions being carefull not
++   to count labels.  */
++unsigned int
++arm_sync_loop_insns (rtx insn, rtx *operands)
++{
++  arm_insn_count = 0;
++  arm_process_output_sync_insn (arm_count, insn, operands);
++  return arm_insn_count;
++}
++
++/* Helper to call a target sync instruction generator, dealing with
++   the variation in operands required by the different generators.  */
++static rtx
++arm_call_generator (struct arm_sync_generator *generator, rtx old_value,
++  		    rtx memory, rtx required_value, rtx new_value)
++{
++  switch (generator->op)
++    {
++    case arm_sync_generator_omn:
++      gcc_assert (! required_value);
++      return generator->u.omn (old_value, memory, new_value);
++
++    case arm_sync_generator_omrn:
++      gcc_assert (required_value);
++      return generator->u.omrn (old_value, memory, required_value, new_value);
++    }
++
++  return NULL;
++}
++
++/* Expand a synchronization loop. The synchronization loop is expanded
++   as an opaque block of instructions in order to ensure that we do
++   not subsequently get extraneous memory accesses inserted within the
++   critical region. The exclusive access property of ldrex/strex is
++   only guaranteed in there are no intervening memory accesses. */
++void
++arm_expand_sync (enum machine_mode mode,
++		 struct arm_sync_generator *generator,
++		 rtx target, rtx memory, rtx required_value, rtx new_value)
++{
++  if (target == NULL)
++    target = gen_reg_rtx (mode);
++
++  memory = arm_legitimize_sync_memory (memory);
++  if (mode != SImode)
++    {
++      rtx load_temp = gen_reg_rtx (SImode);
++
++      if (required_value)
++	required_value = convert_modes (SImode, mode, required_value, true);
++
++      new_value = convert_modes (SImode, mode, new_value, true);
++      emit_insn (arm_call_generator (generator, load_temp, memory,
++				     required_value, new_value));
++      emit_move_insn (target, gen_lowpart (mode, load_temp));
++    }
++  else
++    {
++      emit_insn (arm_call_generator (generator, target, memory, required_value,
++				     new_value));
++    }
++}
++
+ #include "gt-arm.h"
+Index: gcc-4.5/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.h
++++ gcc-4.5/gcc/config/arm/arm.h
+@@ -128,6 +128,24 @@ enum target_cpus
+ /* The processor for which instructions should be scheduled.  */
+ extern enum processor_type arm_tune;
+ 
++enum arm_sync_generator_tag
++  {
++    arm_sync_generator_omn,
++    arm_sync_generator_omrn
++  };
++
++/* Wrapper to pass around a polymorphic pointer to a sync instruction
++   generator and.  */
++struct arm_sync_generator
++{
++  enum arm_sync_generator_tag op;
++  union
++  {
++    rtx (* omn) (rtx, rtx, rtx);
++    rtx (* omrn) (rtx, rtx, rtx, rtx);
++  } u;
++};
++
+ typedef enum arm_cond_code
+ {
+   ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
+@@ -272,6 +290,20 @@ extern void (*arm_lang_output_object_att
+    for Thumb-2.  */
+ #define TARGET_UNIFIED_ASM TARGET_THUMB2
+ 
++/* Nonzero if this chip provides the DMB instruction.  */
++#define TARGET_HAVE_DMB		(arm_arch7)
++
++/* Nonzero if this chip implements a memory barrier via CP15.  */
++#define TARGET_HAVE_DMB_MCR	(arm_arch6k && ! TARGET_HAVE_DMB)
++
++/* Nonzero if this chip implements a memory barrier instruction.  */
++#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
++
++/* Nonzero if this chip supports ldrex and strex */
++#define TARGET_HAVE_LDREX	((arm_arch6 && TARGET_ARM) || arm_arch7)
++
++/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}.  */
++#define TARGET_HAVE_LDREXBHD	((arm_arch6k && TARGET_ARM) || arm_arch7)
+ 
+ /* True iff the full BPABI is being used.  If TARGET_BPABI is true,
+    then TARGET_AAPCS_BASED must be true -- but the converse does not
+@@ -405,6 +437,12 @@ extern int arm_arch5e;
+ /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
+ extern int arm_arch6;
+ 
++/* Nonzero if this chip supports the ARM Architecture 6k extensions.  */
++extern int arm_arch6k;
++
++/* Nonzero if this chip supports the ARM Architecture 7 extensions.  */
++extern int arm_arch7;
++
+ /* Nonzero if instructions not present in the 'M' profile can be used.  */
+ extern int arm_arch_notm;
+ 
+Index: gcc-4.5/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.md
++++ gcc-4.5/gcc/config/arm/arm.md
+@@ -103,6 +103,7 @@
+    (UNSPEC_RBIT 26)       ; rbit operation.
+    (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
+                              ; another symbolic address.
++   (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
+   ]
+ )
+ 
+@@ -139,6 +140,11 @@
+    (VUNSPEC_ALIGN32  16) ; Used to force 32-byte alignment.
+    (VUNSPEC_EH_RETURN 20); Use to override the return address for exception
+ 			 ; handling.
++   (VUNSPEC_SYNC_COMPARE_AND_SWAP 21)	; Represent an atomic compare swap.
++   (VUNSPEC_SYNC_LOCK             22)	; Represent a sync_lock_test_and_set.
++   (VUNSPEC_SYNC_OP               23)	; Represent a sync_<op>
++   (VUNSPEC_SYNC_NEW_OP           24)	; Represent a sync_new_<op>
++   (VUNSPEC_SYNC_OLD_OP           25)	; Represent a sync_old_<op>
+   ]
+ )
+ 
+@@ -163,8 +169,21 @@
+ (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
+   (const (symbol_ref "arm_fpu_attr")))
+ 
++(define_attr "sync_result"          "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_memory"          "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_required_value"  "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_new_value"       "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_t1"              "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_t2"              "none,0,1,2,3,4,5" (const_string "none"))
++(define_attr "sync_release_barrier" "yes,no"           (const_string "yes"))
++(define_attr "sync_op"              "none,add,sub,ior,xor,and,nand"
++                                    (const_string "none"))
++
+ ; LENGTH of an instruction (in bytes)
+-(define_attr "length" "" (const_int 4))
++(define_attr "length" ""
++  (cond [(not (eq_attr "sync_memory" "none"))
++ 	   (symbol_ref "arm_sync_loop_insns (insn, operands) * 4")
++	] (const_int 4)))
+ 
+ ; POOL_RANGE is how far away from a constant pool entry that this insn
+ ; can be placed.  If the distance is zero, then this insn will never
+@@ -11549,4 +11568,5 @@
+ (include "thumb2.md")
+ ;; Neon patterns
+ (include "neon.md")
+-
++;; Synchronization Primitives
++(include "sync.md")
+Index: gcc-4.5/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/predicates.md
++++ gcc-4.5/gcc/config/arm/predicates.md
+@@ -573,6 +573,11 @@
+ 		(and (match_test "TARGET_32BIT")
+ 		     (match_operand 0 "arm_di_operand"))))
+ 
++;; True if the operand is memory reference suitable for a ldrex/strex.
++(define_predicate "arm_sync_memory_operand"
++  (and (match_operand 0 "memory_operand")
++       (match_code "reg" "0")))
++
+ ;; Predicates for parallel expanders based on mode.
+ (define_special_predicate "vect_par_constant_high" 
+   (match_code "parallel")
+Index: gcc-4.5/gcc/testsuite/gcc.target/arm/synchronize.c
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/gcc.target/arm/synchronize.c
++++ gcc-4.5/gcc/testsuite/gcc.target/arm/synchronize.c
+@@ -1,4 +1,4 @@
+-/* { dg-final { scan-assembler "__sync_synchronize" { target arm*-*-linux-*eabi } } } */
++/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi } } } */
+ 
+ void *foo (void)
+ {
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch
new file mode 100644
index 0000000000..4e63a81890
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch
@@ -0,0 +1,38 @@
+2010-10-18  Kazu Hirata  <kazu@codesourcery.com>
+
+	Issue #9720
+	Backport from mainline:
+	gcc/
+	2010-10-07  Tejas Belagod  <tejas.belagod@arm.com>
+	* config/arm/neon.md (neon_unpack<US>_<mode>): Add 'w' to
+	constraint, add register specifier in instruction template.
+	(neon_vec_pack_trunc_<mode>): Likewise.
+	(neon_vec_<US>mult_<mode>): Add register specifier to
+	instruction template.
+
+=== modified file 'gcc/config/arm/neon.md'
+Index: gcc-4.5/gcc/config/arm/neon.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/neon.md
++++ gcc-4.5/gcc/config/arm/neon.md
+@@ -5682,9 +5682,9 @@
+ ;; Vectorize for non-neon-quad case
+ (define_insn "neon_unpack<US>_<mode>"
+  [(set (match_operand:<V_widen> 0 "register_operand" "=w")
+-       (SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))]
++       (SE:<V_widen> (match_operand:VDI 1 "register_operand" "w")))]
+  "TARGET_NEON"
+- "vmovl.<US><V_sz_elem> %q0, %1"
++ "vmovl.<US><V_sz_elem> %q0, %P1"
+   [(set_attr "neon_type" "neon_shift_1")]
+ )
+ 
+@@ -5721,7 +5721,7 @@
+  		       (SE:<V_widen> 
+ 			   (match_operand:VDI 2 "register_operand" "w"))))]
+   "TARGET_NEON"
+-  "vmull.<US><V_sz_elem> %q0, %1, %2"
++  "vmull.<US><V_sz_elem> %q0, %P1, %P2"
+   [(set_attr "neon_type" "neon_shift_1")]
+ )
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99421.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99421.patch
new file mode 100644
index 0000000000..3a45ee5026
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99421.patch
@@ -0,0 +1,94 @@
+2010-10-20  Nathan Froyd  <froydnj@codesourcery.com>
+
+	Issue #9781
+
+	Backport from mainline:
+
+	gcc/
+	2010-10-20  Nathan Froyd  <froydnj@codesourcery.com>
+
+	* ifcvt.c (noce_emit_cmove): If both of the values are SUBREGs, try
+	emitting the conditional move in the inner mode of the SUBREG.
+
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c	2010-10-15 10:01:07 +0000
++++ new/gcc/ifcvt.c	2010-11-04 12:11:15 +0000
+@@ -1338,6 +1338,9 @@
+ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code,
+ 		 rtx cmp_a, rtx cmp_b, rtx vfalse, rtx vtrue)
+ {
++  rtx target;
++  int unsignedp;
++
+   /* If earliest == jump, try to build the cmove insn directly.
+      This is helpful when combine has created some complex condition
+      (like for alpha's cmovlbs) that we can't hope to regenerate
+@@ -1372,10 +1375,62 @@
+     return NULL_RTX;
+ 
+ #if HAVE_conditional_move
+-  return emit_conditional_move (x, code, cmp_a, cmp_b, VOIDmode,
+-				vtrue, vfalse, GET_MODE (x),
+-			        (code == LTU || code == GEU
+-				 || code == LEU || code == GTU));
++  unsignedp = (code == LTU || code == GEU
++	       || code == LEU || code == GTU);
++
++  target = emit_conditional_move (x, code, cmp_a, cmp_b, VOIDmode,
++				  vtrue, vfalse, GET_MODE (x),
++				  unsignedp);
++  if (target)
++    return target;
++
++  /* We might be faced with a situation like:
++
++     x = (reg:M TARGET)
++     vtrue = (subreg:M (reg:N VTRUE) BYTE)
++     vfalse = (subreg:M (reg:N VFALSE) BYTE)
++
++     We can't do a conditional move in mode M, but it's possible that we
++     could do a conditional move in mode N instead and take a subreg of
++     the result.
++
++     If we can't create new pseudos, though, don't bother.  */
++  if (reload_completed)
++    return NULL_RTX;
++
++  if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG)
++    {
++      rtx reg_vtrue = SUBREG_REG (vtrue);
++      rtx reg_vfalse = SUBREG_REG (vfalse);
++      unsigned int byte_vtrue = SUBREG_BYTE (vtrue);
++      unsigned int byte_vfalse = SUBREG_BYTE (vfalse);
++      rtx promoted_target;
++
++      if (GET_MODE (reg_vtrue) != GET_MODE (reg_vfalse)
++	  || byte_vtrue != byte_vfalse
++	  || (SUBREG_PROMOTED_VAR_P (vtrue)
++	      != SUBREG_PROMOTED_VAR_P (vfalse))
++	  || (SUBREG_PROMOTED_UNSIGNED_P (vtrue)
++	      != SUBREG_PROMOTED_UNSIGNED_P (vfalse)))
++	return NULL_RTX;
++
++      promoted_target = gen_reg_rtx (GET_MODE (reg_vtrue));
++
++      target = emit_conditional_move (promoted_target, code, cmp_a, cmp_b,
++				      VOIDmode, reg_vtrue, reg_vfalse,
++				      GET_MODE (reg_vtrue), unsignedp);
++      /* Nope, couldn't do it in that mode either.  */
++      if (!target)
++	return NULL_RTX;
++
++      target = gen_rtx_SUBREG (GET_MODE (vtrue), promoted_target, byte_vtrue);
++      SUBREG_PROMOTED_VAR_P (target) = SUBREG_PROMOTED_VAR_P (vtrue);
++      SUBREG_PROMOTED_UNSIGNED_SET (target, SUBREG_PROMOTED_UNSIGNED_P (vtrue));
++      emit_move_insn (x, target);
++      return x;
++    }
++  else
++    return NULL_RTX;
+ #else
+   /* We'll never get here, as noce_process_if_block doesn't call the
+      functions involved.  Ifdef code, however, should be discouraged
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99423.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99423.patch
new file mode 100644
index 0000000000..80dbe3f71a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99423.patch
@@ -0,0 +1,114 @@
+2010-10-25  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #9812
+
+	Backport from mainline:
+
+	gcc/
+	2010-10-25  Jie Zhang  <jie@codesourcery.com>
+	* combine.c (try_combine): If insns need to be kept around,
+	check that they can be copied in the merged instruction.
+
+	gcc/testsuite/
+	2010-10-25  Jie Zhang  <jie@codesourcery.com>
+	* g++.dg/opt/combine.c: New test.
+
+=== modified file 'gcc/combine.c'
+--- old/gcc/combine.c	2010-09-20 22:37:32 +0000
++++ new/gcc/combine.c	2010-11-04 12:39:28 +0000
+@@ -2809,6 +2809,17 @@
+     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
+ 	       : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
+ 
++  /* We are about to copy insns for the case where they need to be kept
++     around.  Check that they can be copied in the merged instruction.  */
++
++  if (targetm.cannot_copy_insn_p
++      && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
++	  || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))))
++    {
++      undo_all ();
++      return 0;
++    }
++
+   /* If the set in I2 needs to be kept around, we must make a copy of
+      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
+      PATTERN (I2), we are only substituting for the original I1DEST, not into
+
+=== added file 'gcc/testsuite/g++.dg/opt/combine.C'
+--- old/gcc/testsuite/g++.dg/opt/combine.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/opt/combine.C	2010-11-04 12:39:28 +0000
+@@ -0,0 +1,72 @@
++// { dg-do assemble { target fpic } }
++// { dg-options "-O2 -fweb -fPIC -fvisibility=hidden" }
++
++class QBasicAtomicInt
++{
++public:
++  volatile int _q_value;
++  inline operator int () const {return _q_value;}
++};
++class QVariant;
++class QScriptContext;
++class QScriptEngine;
++class QScriptValue
++{
++public:
++  QVariant toVariant () const;
++};
++class QScriptDebuggerBackendPrivate
++{
++  static QScriptValue trace (QScriptContext *context);
++};
++template <typename T> struct QMetaTypeId { };
++template <typename T> struct QMetaTypeId2
++{
++  static inline int qt_metatype_id ()
++  {
++    return QMetaTypeId<T>::qt_metatype_id () ;
++  }
++};
++template <typename T> inline int qMetaTypeId (T * = 0)
++{
++  return QMetaTypeId2<T>::qt_metatype_id () ;
++}
++class QVariant { };
++template<typename T> inline T qvariant_cast (const QVariant &v)
++{
++  const int vid = qMetaTypeId<T> ((0)) ;
++};
++class QScriptContext
++{
++public: 
++  QScriptValue callee () const;
++};
++class QScriptEngine  
++{
++public:
++  static bool convertV2 (const QScriptValue &value , int type , void *ptr) ;
++};
++inline bool qscriptvalue_cast_helper (const QScriptValue &value , int type , void *ptr)
++{
++  return QScriptEngine::convertV2 (value, type, ptr) ;
++}
++template<typename T> T qscriptvalue_cast (const QScriptValue &value)
++{
++  T t;
++  const int id = qMetaTypeId<T> () ;
++  if ( qscriptvalue_cast_helper (value, id, &t))
++    return qvariant_cast<T> (value.toVariant ()) ;
++}
++template <> struct QMetaTypeId< QScriptDebuggerBackendPrivate* >
++{
++  static int qt_metatype_id ()
++  {
++    static QBasicAtomicInt metatype_id = { (0) };
++    return metatype_id;
++  }
++};
++QScriptValue QScriptDebuggerBackendPrivate::trace (QScriptContext *context)
++{
++  QScriptValue data = context->callee () ;
++  QScriptDebuggerBackendPrivate *self = qscriptvalue_cast<QScriptDebuggerBackendPrivate*> (data) ;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch
new file mode 100644
index 0000000000..ac3a1e224d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch
@@ -0,0 +1,697 @@
+	Issue #1259
+
+	Backport from mainline:
+
+	gcc/
+	2010-10-22  Jie Zhang  <jie@codesourcery.com>
+
+	* expr.c (emit_group_load_1): Update calls to extract_bit_field.
+	(copy_blkmode_from_reg): Likewise.
+	(read_complex_part): Likewise.
+	(expand_expr_real_1): Calculate packedp and pass it to
+	extract_bit_field.
+	* expr.h (extract_bit_field): Update declaration.
+	* calls.c (store_unaligned_arguments_into_pseudos): Update call
+	to extract_bit_field.
+	* expmed.c (extract_fixed_bit_field): Update calls to
+	extract_fixed_bit_field.
+	(store_split_bit_field): Likewise.
+	(extract_bit_field_1): Add new argument packedp.
+	(extract_bit_field): Add new argument packedp.
+	(extract_fixed_bit_field): Add new argument packedp and let
+	packed attribute override volatile.
+	* stmt.c (expand_return): Update call to extract_bit_field.
+
+	2010-10-15  Jie Zhang  <jie@codesourcery.com>
+
+	* doc/invoke.texi: Add -fstrict-volatile-bitfields to
+	Option Summary and Index.
+
+	2010-07-13  DJ Delorie  <dj@redhat.com>
+
+	* config/h8300/h8300.c (h8300_init_once): Default to
+	-fstrict_volatile_bitfields.
+
+	* config/sh/sh.c (sh_override_options): Default to
+	-fstrict_volatile_bitfields.
+
+	* config/rx/rx.c (rx_option_override): New.
+
+	* config/m32c/m32c.c (m32c_override_options): Default to
+	-fstrict_volatile_bitfields.
+
+	2010-06-16  DJ Delorie  <dj@redhat.com>
+
+	* common.opt (-fstrict-volatile-bitfields): new.
+	* doc/invoke.texi: Document it.
+	* fold-const.c (optimize_bit_field_compare): For volatile
+	bitfields, use the field's type to determine the mode, not the
+	field's size.
+	* expr.c (expand_assignment): Likewise.
+	(get_inner_reference): Likewise.
+	(expand_expr_real_1): Likewise.
+	* expmed.c (store_fixed_bit_field): Likewise.
+	(extract_bit_field_1): Likewise.
+	(extract_fixed_bit_field): Likewise.
+
+	gcc/testsuite/
+	2010-08-19  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR testsuite/45324
+	* gcc.target/i386/volatile-bitfields-1.c: Also scan movb.
+
+	2010-06-16  DJ Delorie  <dj@redhat.com>
+
+	* gcc.target/i386/volatile-bitfields-1.c: New.
+	* gcc.target/i386/volatile-bitfields-2.c: New.
+
+=== modified file 'gcc/calls.c'
+Index: gcc-4_5-branch/gcc/calls.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/calls.c	2012-03-06 13:05:56.524590011 -0800
++++ gcc-4_5-branch/gcc/calls.c	2012-03-06 13:36:10.276677792 -0800
+@@ -878,7 +878,7 @@
+ 	    int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD);
+ 
+ 	    args[i].aligned_regs[j] = reg;
+-	    word = extract_bit_field (word, bitsize, 0, 1, NULL_RTX,
++	    word = extract_bit_field (word, bitsize, 0, 1, false, NULL_RTX,
+ 				      word_mode, word_mode);
+ 
+ 	    /* There is no need to restrict this code to loading items
+Index: gcc-4_5-branch/gcc/common.opt
+===================================================================
+--- gcc-4_5-branch.orig/gcc/common.opt	2012-03-06 13:05:48.400589618 -0800
++++ gcc-4_5-branch/gcc/common.opt	2012-03-06 13:36:35.608679018 -0800
+@@ -613,6 +613,10 @@
+ Common Report Var(flag_loop_block) Optimization
+ Enable Loop Blocking transformation
+ 
++fstrict-volatile-bitfields
++Common Report Var(flag_strict_volatile_bitfields) Init(-1)
++Force bitfield accesses to match their type width
++
+ fguess-branch-probability
+ Common Report Var(flag_guess_branch_prob) Optimization
+ Enable guessing of branch probabilities
+Index: gcc-4_5-branch/gcc/config/h8300/h8300.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/h8300/h8300.c	2012-03-06 11:53:30.000000000 -0800
++++ gcc-4_5-branch/gcc/config/h8300/h8300.c	2012-03-06 13:36:35.528679014 -0800
+@@ -403,6 +403,10 @@
+ 	 restore er6 though, so bump up the cost.  */
+       h8300_move_ratio = 6;
+     }
++
++  /* This target defaults to strict volatile bitfields.  */
++  if (flag_strict_volatile_bitfields < 0)
++    flag_strict_volatile_bitfields = 1;
+ }
+ 
+ /* Implement REG_CLASS_FROM_LETTER.
+Index: gcc-4_5-branch/gcc/config/m32c/m32c.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/m32c/m32c.c	2012-03-06 11:53:16.000000000 -0800
++++ gcc-4_5-branch/gcc/config/m32c/m32c.c	2012-03-06 13:36:35.488679012 -0800
+@@ -428,6 +428,10 @@
+ 
+   if (TARGET_A24)
+     flag_ivopts = 0;
++
++  /* This target defaults to strict volatile bitfields.  */
++  if (flag_strict_volatile_bitfields < 0)
++    flag_strict_volatile_bitfields = 1;
+ }
+ 
+ /* Defining data structures for per-function information */
+Index: gcc-4_5-branch/gcc/config/rx/rx.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rx/rx.c	2012-03-06 11:53:17.000000000 -0800
++++ gcc-4_5-branch/gcc/config/rx/rx.c	2012-03-06 13:36:35.508679013 -0800
+@@ -2417,6 +2417,14 @@
+   return ! TYPE_PACKED (record_type);
+ }
+ 
++static void
++rx_option_override (void)
++{
++  /* This target defaults to strict volatile bitfields.  */
++  if (flag_strict_volatile_bitfields < 0)
++    flag_strict_volatile_bitfields = 1;
++}
++
+ 
+ /* Returns true if X a legitimate constant for an immediate
+    operand on the RX.  X is already known to satisfy CONSTANT_P.  */
+@@ -2794,6 +2802,9 @@
+ #undef  TARGET_PROMOTE_FUNCTION_MODE
+ #define TARGET_PROMOTE_FUNCTION_MODE		rx_promote_function_mode
+ 
++#undef  TARGET_OPTION_OVERRIDE
++#define TARGET_OPTION_OVERRIDE			rx_option_override
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ /* #include "gt-rx.h" */
+Index: gcc-4_5-branch/gcc/config/sh/sh.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/sh/sh.c	2012-03-06 11:53:20.000000000 -0800
++++ gcc-4_5-branch/gcc/config/sh/sh.c	2012-03-06 13:36:35.516679013 -0800
+@@ -950,6 +950,10 @@
+ 
+   if (sh_fixed_range_str)
+     sh_fix_range (sh_fixed_range_str);
++
++  /* This target defaults to strict volatile bitfields.  */
++  if (flag_strict_volatile_bitfields < 0)
++    flag_strict_volatile_bitfields = 1;
+ }
+ 
+ /* Print the operand address in x to the stream.  */
+Index: gcc-4_5-branch/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/invoke.texi	2012-03-06 13:05:56.988590034 -0800
++++ gcc-4_5-branch/gcc/doc/invoke.texi	2012-03-06 13:36:36.048679039 -0800
+@@ -922,7 +922,7 @@
+ -fargument-noalias-global  -fargument-noalias-anything @gol
+ -fleading-underscore  -ftls-model=@var{model} @gol
+ -ftrapv  -fwrapv  -fbounds-check @gol
+--fvisibility}
++-fvisibility -fstrict-volatile-bitfields}
+ @end table
+ 
+ @menu
+@@ -17629,6 +17629,33 @@
+ An overview of these techniques, their benefits and how to use them
+ is at @w{@uref{http://gcc.gnu.org/wiki/Visibility}}.
+ 
++@item -fstrict-volatile-bitfields
++@opindex fstrict-volatile-bitfields
++This option should be used if accesses to volatile bitfields (or other
++structure fields, although the compiler usually honors those types
++anyway) should use a single access in a mode of the same size as the
++container's type, aligned to a natural alignment if possible.  For
++example, targets with memory-mapped peripheral registers might require
++all such accesses to be 16 bits wide; with this flag the user could
++declare all peripheral bitfields as ``unsigned short'' (assuming short
++is 16 bits on these targets) to force GCC to use 16 bit accesses
++instead of, perhaps, a more efficient 32 bit access.
++
++If this option is disabled, the compiler will use the most efficient
++instruction.  In the previous example, that might be a 32-bit load
++instruction, even though that will access bytes that do not contain
++any portion of the bitfield, or memory-mapped registers unrelated to
++the one being updated.
++
++If the target requires strict alignment, and honoring the container
++type would require violating this alignment, a warning is issued.
++However, the access happens as the user requested, under the
++assumption that the user knows something about the target hardware
++that GCC is unaware of.
++
++The default value of this option is determined by the application binary
++interface for the target processor.
++
+ @end table
+ 
+ @c man end
+Index: gcc-4_5-branch/gcc/expmed.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expmed.c	2012-03-06 13:05:56.876590028 -0800
++++ gcc-4_5-branch/gcc/expmed.c	2012-03-06 13:36:35.104678993 -0800
+@@ -47,7 +47,7 @@
+ static rtx extract_fixed_bit_field (enum machine_mode, rtx,
+ 				    unsigned HOST_WIDE_INT,
+ 				    unsigned HOST_WIDE_INT,
+-				    unsigned HOST_WIDE_INT, rtx, int);
++				    unsigned HOST_WIDE_INT, rtx, int, bool);
+ static rtx mask_rtx (enum machine_mode, int, int, int);
+ static rtx lshift_value (enum machine_mode, rtx, int, int);
+ static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
+@@ -904,8 +904,14 @@
+       if (GET_MODE_BITSIZE (mode) == 0
+ 	  || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
+ 	mode = word_mode;
+-      mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
+-			    MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
++
++      if (MEM_VOLATILE_P (op0)
++          && GET_MODE_BITSIZE (GET_MODE (op0)) > 0
++	  && flag_strict_volatile_bitfields > 0)
++	mode = GET_MODE (op0);
++      else
++	mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
++			      MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
+ 
+       if (mode == VOIDmode)
+ 	{
+@@ -1099,7 +1105,7 @@
+ 	       endianness compensation) to fetch the piece we want.  */
+ 	    part = extract_fixed_bit_field (word_mode, value, 0, thissize,
+ 					    total_bits - bitsize + bitsdone,
+-					    NULL_RTX, 1);
++					    NULL_RTX, 1, false);
+ 	}
+       else
+ 	{
+@@ -1110,7 +1116,7 @@
+ 			    & (((HOST_WIDE_INT) 1 << thissize) - 1));
+ 	  else
+ 	    part = extract_fixed_bit_field (word_mode, value, 0, thissize,
+-					    bitsdone, NULL_RTX, 1);
++					    bitsdone, NULL_RTX, 1, false);
+ 	}
+ 
+       /* If OP0 is a register, then handle OFFSET here.
+@@ -1176,7 +1182,8 @@
+ 
+ static rtx
+ extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
+-		     unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
++		     unsigned HOST_WIDE_INT bitnum,
++		     int unsignedp, bool packedp, rtx target,
+ 		     enum machine_mode mode, enum machine_mode tmode,
+ 		     bool fallback_p)
+ {
+@@ -1378,6 +1385,14 @@
+ 	    ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)
+ 	    : mode);
+ 
++  /* If the bitfield is volatile, we need to make sure the access
++     remains on a type-aligned boundary.  */
++  if (GET_CODE (op0) == MEM
++      && MEM_VOLATILE_P (op0)
++      && GET_MODE_BITSIZE (GET_MODE (op0)) > 0
++      && flag_strict_volatile_bitfields > 0)
++    goto no_subreg_mode_swap;
++
+   if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
+ 	&& bitpos % BITS_PER_WORD == 0)
+        || (mode1 != BLKmode
+@@ -1450,7 +1465,7 @@
+ 	  rtx result_part
+ 	    = extract_bit_field (op0, MIN (BITS_PER_WORD,
+ 					   bitsize - i * BITS_PER_WORD),
+-				 bitnum + bit_offset, 1, target_part, mode,
++				 bitnum + bit_offset, 1, false, target_part, mode,
+ 				 word_mode);
+ 
+ 	  gcc_assert (target_part);
+@@ -1649,7 +1664,7 @@
+ 	      xop0 = adjust_address (op0, bestmode, xoffset);
+ 	      xop0 = force_reg (bestmode, xop0);
+ 	      result = extract_bit_field_1 (xop0, bitsize, xbitpos,
+-					    unsignedp, target,
++					    unsignedp, packedp, target,
+ 					    mode, tmode, false);
+ 	      if (result)
+ 		return result;
+@@ -1663,7 +1678,7 @@
+     return NULL;
+ 
+   target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
+-				    bitpos, target, unsignedp);
++				    bitpos, target, unsignedp, packedp);
+   return convert_extracted_bit_field (target, mode, tmode, unsignedp);
+ }
+ 
+@@ -1674,6 +1689,7 @@
+ 
+    STR_RTX is the structure containing the byte (a REG or MEM).
+    UNSIGNEDP is nonzero if this is an unsigned bit field.
++   PACKEDP is nonzero if the field has the packed attribute.
+    MODE is the natural mode of the field value once extracted.
+    TMODE is the mode the caller would like the value to have;
+    but the value may be returned with type MODE instead.
+@@ -1685,10 +1701,10 @@
+ 
+ rtx
+ extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
+-		   unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
+-		   enum machine_mode mode, enum machine_mode tmode)
++		   unsigned HOST_WIDE_INT bitnum, int unsignedp, bool packedp,
++		   rtx target, enum machine_mode mode, enum machine_mode tmode)
+ {
+-  return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp,
++  return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp, packedp,
+ 			      target, mode, tmode, true);
+ }
+ 
+@@ -1704,6 +1720,8 @@
+      which is significant on bigendian machines.)
+ 
+    UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
++   PACKEDP is true if the field has the packed attribute.
++
+    If TARGET is nonzero, attempts to store the value there
+    and return TARGET, but this is not guaranteed.
+    If TARGET is not used, create a pseudo-reg of mode TMODE for the value.  */
+@@ -1713,7 +1731,7 @@
+ 			 unsigned HOST_WIDE_INT offset,
+ 			 unsigned HOST_WIDE_INT bitsize,
+ 			 unsigned HOST_WIDE_INT bitpos, rtx target,
+-			 int unsignedp)
++			 int unsignedp, bool packedp)
+ {
+   unsigned int total_bits = BITS_PER_WORD;
+   enum machine_mode mode;
+@@ -1730,8 +1748,19 @@
+ 	 includes the entire field.  If such a mode would be larger than
+ 	 a word, we won't be doing the extraction the normal way.  */
+ 
+-      mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
+-			    MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
++      if (MEM_VOLATILE_P (op0)
++	  && flag_strict_volatile_bitfields > 0)
++	{
++	  if (GET_MODE_BITSIZE (GET_MODE (op0)) > 0)
++	    mode = GET_MODE (op0);
++	  else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0)
++	    mode = GET_MODE (target);
++	  else
++	    mode = tmode;
++	}
++      else
++	mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
++			      MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
+ 
+       if (mode == VOIDmode)
+ 	/* The only way this should occur is if the field spans word
+@@ -1752,12 +1781,67 @@
+ 		     * BITS_PER_UNIT);
+ 	}
+ 
+-      /* Get ref to an aligned byte, halfword, or word containing the field.
+-	 Adjust BITPOS to be position within a word,
+-	 and OFFSET to be the offset of that word.
+-	 Then alter OP0 to refer to that word.  */
+-      bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
+-      offset -= (offset % (total_bits / BITS_PER_UNIT));
++      /* If we're accessing a volatile MEM, we can't do the next
++	 alignment step if it results in a multi-word access where we
++	 otherwise wouldn't have one.  So, check for that case
++	 here.  */
++      if (MEM_P (op0)
++	  && MEM_VOLATILE_P (op0)
++	  && flag_strict_volatile_bitfields > 0
++	  && bitpos + bitsize <= total_bits
++	  && bitpos + bitsize + (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT > total_bits)
++	{
++	  if (STRICT_ALIGNMENT)
++	    {
++	      static bool informed_about_misalignment = false;
++	      bool warned;
++
++	      if (packedp)
++		{
++		  if (bitsize == total_bits)
++		    warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
++					 "multiple accesses to volatile structure member"
++					 " because of packed attribute");
++		  else
++		    warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
++					 "multiple accesses to volatile structure bitfield"
++					 " because of packed attribute");
++
++		  return extract_split_bit_field (op0, bitsize,
++						  bitpos + offset * BITS_PER_UNIT,
++						  unsignedp);
++		}
++
++	      if (bitsize == total_bits)
++		warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
++				     "mis-aligned access used for structure member");
++	      else
++		warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
++				     "mis-aligned access used for structure bitfield");
++
++	      if (! informed_about_misalignment && warned)
++		{
++		  informed_about_misalignment = true;
++		  inform (input_location,
++			  "When a volatile object spans multiple type-sized locations,"
++			  " the compiler must choose between using a single mis-aligned access to"
++			  " preserve the volatility, or using multiple aligned accesses to avoid"
++			  " runtime faults.  This code may fail at runtime if the hardware does"
++			  " not allow this access.");
++		}
++	    }
++	}
++      else
++	{
++
++	  /* Get ref to an aligned byte, halfword, or word containing the field.
++	     Adjust BITPOS to be position within a word,
++	     and OFFSET to be the offset of that word.
++	     Then alter OP0 to refer to that word.  */
++	  bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
++	  offset -= (offset % (total_bits / BITS_PER_UNIT));
++	}
++
+       op0 = adjust_address (op0, mode, offset);
+     }
+ 
+@@ -1966,7 +2050,7 @@
+ 	 extract_fixed_bit_field wants offset in bytes.  */
+       part = extract_fixed_bit_field (word_mode, word,
+ 				      offset * unit / BITS_PER_UNIT,
+-				      thissize, thispos, 0, 1);
++				      thissize, thispos, 0, 1, false);
+       bitsdone += thissize;
+ 
+       /* Shift this part into place for the result.  */
+Index: gcc-4_5-branch/gcc/expr.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expr.c	2012-03-06 13:05:57.720590069 -0800
++++ gcc-4_5-branch/gcc/expr.c	2012-03-06 13:40:14.504689612 -0800
+@@ -1749,7 +1749,7 @@
+ 		  && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode))
+ 		tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
+ 					     (bytepos % slen0) * BITS_PER_UNIT,
+-					     1, NULL_RTX, mode, mode);
++					     1, false, NULL_RTX, mode, mode);
+ 	    }
+ 	  else
+ 	    {
+@@ -1759,7 +1759,7 @@
+ 	      mem = assign_stack_temp (GET_MODE (src), slen, 0);
+ 	      emit_move_insn (mem, src);
+ 	      tmps[i] = extract_bit_field (mem, bytelen * BITS_PER_UNIT,
+-					   0, 1, NULL_RTX, mode, mode);
++					   0, 1, false, NULL_RTX, mode, mode);
+ 	    }
+ 	}
+       /* FIXME: A SIMD parallel will eventually lead to a subreg of a
+@@ -1800,7 +1800,7 @@
+ 	tmps[i] = src;
+       else
+ 	tmps[i] = extract_bit_field (src, bytelen * BITS_PER_UNIT,
+-				     bytepos * BITS_PER_UNIT, 1, NULL_RTX,
++				     bytepos * BITS_PER_UNIT, 1, false, NULL_RTX,
+ 				     mode, mode);
+ 
+       if (shift)
+@@ -2213,7 +2213,7 @@
+ 	 bitpos for the destination store (left justified).  */
+       store_bit_field (dst, bitsize, bitpos % BITS_PER_WORD, copy_mode,
+ 		       extract_bit_field (src, bitsize,
+-					  xbitpos % BITS_PER_WORD, 1,
++					  xbitpos % BITS_PER_WORD, 1, false,
+ 					  NULL_RTX, copy_mode, copy_mode));
+     }
+ 
+@@ -2291,7 +2291,7 @@
+ 	 xbitpos for the destination store (right justified).  */
+       store_bit_field (dst_word, bitsize, xbitpos % BITS_PER_WORD, word_mode,
+ 		       extract_bit_field (src_word, bitsize,
+-					  bitpos % BITS_PER_WORD, 1,
++					  bitpos % BITS_PER_WORD, 1, false,
+ 					  NULL_RTX, word_mode, word_mode));
+     }
+ 
+@@ -3075,7 +3075,7 @@
+     }
+ 
+   return extract_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0,
+-			    true, NULL_RTX, imode, imode);
++			    true, false, NULL_RTX, imode, imode);
+ }
+ 
+ /* A subroutine of emit_move_insn_1.  Yet another lowpart generator.
+@@ -4338,6 +4338,13 @@
+ 
+       to_rtx = expand_normal (tem);
+ 
++      /* If the bitfield is volatile, we want to access it in the
++	 field's mode, not the computed mode.  */
++      if (volatilep
++	  && GET_CODE (to_rtx) == MEM
++	  && flag_strict_volatile_bitfields > 0)
++	to_rtx = adjust_address (to_rtx, mode1, 0);
++
+       if (offset != 0)
+ 	{
+ 	  enum machine_mode address_mode;
+@@ -6106,6 +6113,12 @@
+ 	mode = DECL_MODE (field);
+       else if (DECL_MODE (field) == BLKmode)
+ 	blkmode_bitfield = true;
++      else if (TREE_THIS_VOLATILE (exp)
++	       && flag_strict_volatile_bitfields > 0)
++	/* Volatile bitfields should be accessed in the mode of the
++	     field's type, not the mode computed based on the bit
++	     size.  */
++	mode = TYPE_MODE (DECL_BIT_FIELD_TYPE (field));
+ 
+       *punsignedp = DECL_UNSIGNED (field);
+     }
+@@ -8978,6 +8991,7 @@
+ 	HOST_WIDE_INT bitsize, bitpos;
+ 	tree offset;
+ 	int volatilep = 0, must_force_mem;
++	bool packedp = false;
+ 	tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset,
+ 					&mode1, &unsignedp, &volatilep, true);
+ 	rtx orig_op0, memloc;
+@@ -8987,6 +9001,11 @@
+ 	   infinitely recurse.  */
+ 	gcc_assert (tem != exp);
+ 
++	if (TYPE_PACKED (TREE_TYPE (TREE_OPERAND (exp, 0)))
++	    || (TREE_CODE (TREE_OPERAND (exp, 1)) == FIELD_DECL
++		&& DECL_PACKED (TREE_OPERAND (exp, 1))))
++	  packedp = true;
++
+ 	/* If TEM's type is a union of variable size, pass TARGET to the inner
+ 	   computation, since it will need a temporary and TARGET is known
+ 	   to have to do.  This occurs in unchecked conversion in Ada.  */
+@@ -9003,6 +9022,14 @@
+ 			  || modifier == EXPAND_STACK_PARM)
+ 			 ? modifier : EXPAND_NORMAL);
+ 
++
++	/* If the bitfield is volatile, we want to access it in the
++	   field's mode, not the computed mode.  */
++	if (volatilep
++	    && GET_CODE (op0) == MEM
++	    && flag_strict_volatile_bitfields > 0)
++	  op0 = adjust_address (op0, mode1, 0);
++
+ 	mode2
+ 	  = CONSTANT_P (op0) ? TYPE_MODE (TREE_TYPE (tem)) : GET_MODE (op0);
+ 
+@@ -9128,6 +9155,9 @@
+ 		&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
+ 		&& modifier != EXPAND_CONST_ADDRESS
+ 		&& modifier != EXPAND_INITIALIZER)
++	    /* If the field is volatile, we always want an aligned
++	       access.  */
++	    || (volatilep && flag_strict_volatile_bitfields > 0)
+ 	    /* If the field isn't aligned enough to fetch as a memref,
+ 	       fetch it as a bit field.  */
+ 	    || (mode1 != BLKmode
+@@ -9188,7 +9218,7 @@
+ 	    if (MEM_P (op0) && REG_P (XEXP (op0, 0)))
+ 	      mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0));
+ 
+-	    op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp,
++	    op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp, packedp,
+ 				     (modifier == EXPAND_STACK_PARM
+ 				      ? NULL_RTX : target),
+ 				     ext_mode, ext_mode);
+Index: gcc-4_5-branch/gcc/expr.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expr.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/expr.h	2012-03-06 13:05:59.668590163 -0800
+@@ -804,7 +804,7 @@
+ extern void store_bit_field (rtx, unsigned HOST_WIDE_INT,
+ 			     unsigned HOST_WIDE_INT, enum machine_mode, rtx);
+ extern rtx extract_bit_field (rtx, unsigned HOST_WIDE_INT,
+-			      unsigned HOST_WIDE_INT, int, rtx,
++			      unsigned HOST_WIDE_INT, int, bool, rtx,
+ 			      enum machine_mode, enum machine_mode);
+ extern rtx extract_low_bits (enum machine_mode, enum machine_mode, rtx);
+ extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int);
+Index: gcc-4_5-branch/gcc/fold-const.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/fold-const.c	2012-03-06 13:05:56.880590028 -0800
++++ gcc-4_5-branch/gcc/fold-const.c	2012-03-06 13:36:03.276677454 -0800
+@@ -4215,11 +4215,16 @@
+ 
+   /* See if we can find a mode to refer to this field.  We should be able to,
+      but fail if we can't.  */
+-  nmode = get_best_mode (lbitsize, lbitpos,
+-			 const_p ? TYPE_ALIGN (TREE_TYPE (linner))
+-			 : MIN (TYPE_ALIGN (TREE_TYPE (linner)),
+-				TYPE_ALIGN (TREE_TYPE (rinner))),
+-			 word_mode, lvolatilep || rvolatilep);
++  if (lvolatilep
++      && GET_MODE_BITSIZE (lmode) > 0
++      && flag_strict_volatile_bitfields > 0)
++    nmode = lmode;
++  else
++    nmode = get_best_mode (lbitsize, lbitpos,
++			   const_p ? TYPE_ALIGN (TREE_TYPE (linner))
++			   : MIN (TYPE_ALIGN (TREE_TYPE (linner)),
++				  TYPE_ALIGN (TREE_TYPE (rinner))),
++			   word_mode, lvolatilep || rvolatilep);
+   if (nmode == VOIDmode)
+     return 0;
+ 
+Index: gcc-4_5-branch/gcc/stmt.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/stmt.c	2012-03-06 13:05:54.568589917 -0800
++++ gcc-4_5-branch/gcc/stmt.c	2012-03-06 13:36:34.948678986 -0800
+@@ -1754,7 +1754,7 @@
+ 	     xbitpos for the destination store (right justified).  */
+ 	  store_bit_field (dst, bitsize, xbitpos % BITS_PER_WORD, word_mode,
+ 			   extract_bit_field (src, bitsize,
+-					      bitpos % BITS_PER_WORD, 1,
++					      bitpos % BITS_PER_WORD, 1, false,
+ 					      NULL_RTX, word_mode, word_mode));
+ 	}
+ 
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c	2012-03-06 13:05:59.672590164 -0800
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
++
++typedef struct {
++  char a:1;
++  char b:7;
++  int c;
++} BitStruct;
++
++volatile BitStruct bits;
++
++int foo ()
++{
++  return bits.b;
++}
++
++/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c	2012-03-06 13:05:59.672590164 -0800
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */
++
++typedef struct {
++  char a:1;
++  char b:7;
++  int c;
++} BitStruct;
++
++volatile BitStruct bits;
++
++int foo ()
++{
++  return bits.b;
++}
++
++/* { dg-final { scan-assembler "movl.*bits" } } */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99425.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99425.patch
new file mode 100644
index 0000000000..17839c03dc
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99425.patch
@@ -0,0 +1,128 @@
+2010-10-26  Jie Zhang  <jie@codesourcery.com>
+
+	Issue #1259
+
+	Backport from mainline:
+
+	gcc/
+	2010-10-26  Jie Zhang  <jie@codesourcery.com>
+
+	* stor-layout.c (layout_decl): Use the field's type to
+	determine the mode and keep DECL_BIT_FIELD for a volatile
+	bit-field.
+	* config/arm/arm.c (arm_override_options): Default to
+	-fstrict-volatile-bitfields.
+
+	gcc/testsuite/
+	2010-10-26  Jie Zhang  <jie@codesourcery.com>
+
+	* gcc.target/arm/volatile-bitfields-1.c: New test.
+	* gcc.target/arm/volatile-bitfields-2.c: New test.
+	* gcc.target/arm/volatile-bitfields-3.c: New test.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/arm.c	2010-11-04 12:49:37 +0000
+@@ -1933,6 +1933,10 @@
+        calculation, which is 2 instructions.  */
+     set_param_value ("gcse-unrestricted-cost", 2);
+ 
++  /* ARM EABI defaults to strict volatile bitfields.  */
++  if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0)
++    flag_strict_volatile_bitfields = 1;
++
+   /* Register global variables with the garbage collector.  */
+   arm_add_gc_roots ();
+ 
+
+=== modified file 'gcc/stor-layout.c'
+--- old/gcc/stor-layout.c	2010-04-02 18:54:46 +0000
++++ new/gcc/stor-layout.c	2010-11-04 12:49:37 +0000
+@@ -593,11 +593,14 @@
+ 	    }
+ 
+ 	  /* See if we can use an ordinary integer mode for a bit-field.
+-	     Conditions are: a fixed size that is correct for another mode
+-	     and occupying a complete byte or bytes on proper boundary.  */
++	     Conditions are: a fixed size that is correct for another mode,
++	     occupying a complete byte or bytes on proper boundary,
++	     and not volatile or not -fstrict-volatile-bitfields.  */
+ 	  if (TYPE_SIZE (type) != 0
+ 	      && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
+-	      && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT)
++	      && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT
++	      && !(TREE_THIS_VOLATILE (decl)
++		   && flag_strict_volatile_bitfields > 0))
+ 	    {
+ 	      enum machine_mode xmode
+ 		= mode_for_size_tree (DECL_SIZE (decl), MODE_INT, 1);
+
+=== added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c'
+--- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c	2010-11-04 12:49:37 +0000
+@@ -0,0 +1,18 @@
++/* { dg-require-effective-target arm_eabi } */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef struct {
++  char a:1;
++  char b:7;
++  int c;
++} BitStruct;
++
++volatile BitStruct bits;
++
++int foo ()
++{
++  return bits.b;
++}
++
++/* { dg-final { scan-assembler "ldrb\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c'
+--- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c	2010-11-04 12:49:37 +0000
+@@ -0,0 +1,18 @@
++/* { dg-require-effective-target arm_eabi } */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef struct {
++  volatile unsigned long a:8;
++  volatile unsigned long b:8;
++  volatile unsigned long c:16;
++} BitStruct;
++
++BitStruct bits;
++
++unsigned long foo ()
++{
++  return bits.b;
++}
++
++/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c'
+--- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c	2010-11-04 12:49:37 +0000
+@@ -0,0 +1,18 @@
++/* { dg-require-effective-target arm_eabi } */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++typedef struct {
++  volatile unsigned long a:8;
++  volatile unsigned long b:8;
++  volatile unsigned long c:16;
++} BitStruct;
++
++BitStruct bits;
++
++unsigned long foo ()
++{
++  return bits.c;
++}
++
++/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch
new file mode 100644
index 0000000000..cf06e1ff74
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch
@@ -0,0 +1,41 @@
+	Backport from mainline:
+
+	gcc/
+	2010-10-26  Jie Zhang  <jie@codesourcery.com>
+
+	* doc/invoke.texi: Improve documentation of
+	-fstrict-volatile-bitfields.
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-11-04 12:43:52 +0000
++++ new/gcc/doc/invoke.texi	2010-11-04 14:29:09 +0000
+@@ -17633,8 +17633,8 @@
+ @opindex fstrict-volatile-bitfields
+ This option should be used if accesses to volatile bitfields (or other
+ structure fields, although the compiler usually honors those types
+-anyway) should use a single access in a mode of the same size as the
+-container's type, aligned to a natural alignment if possible.  For
++anyway) should use a single access of the width of the
++field's type, aligned to a natural alignment if possible.  For
+ example, targets with memory-mapped peripheral registers might require
+ all such accesses to be 16 bits wide; with this flag the user could
+ declare all peripheral bitfields as ``unsigned short'' (assuming short
+@@ -17647,11 +17647,13 @@
+ any portion of the bitfield, or memory-mapped registers unrelated to
+ the one being updated.
+ 
+-If the target requires strict alignment, and honoring the container
++If the target requires strict alignment, and honoring the field
+ type would require violating this alignment, a warning is issued.
+-However, the access happens as the user requested, under the
+-assumption that the user knows something about the target hardware
+-that GCC is unaware of.
++If the field has @code{packed} attribute, the access is done without
++honoring the field type.  If the field doesn't have @code{packed}
++attribute, the access is done honoring the field type.  In both cases,
++GCC assumes that the user knows something about the target hardware
++that it is unaware of.
+ 
+ The default value of this option is determined by the application binary
+ interface for the target processor.
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99429.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99429.patch
new file mode 100644
index 0000000000..63ba95e0e3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99429.patch
@@ -0,0 +1,1257 @@
+2010-11-09  Michael Hope  <michael.hope@linaro.org>
+
+	Revert:
+
+	Backport from mainline:
+
+	2010-07-15  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (last_label_ruid, first_index_reg, last_index_reg):
+	New static variables.
+	(reload_combine_recognize_pattern): New static function, broken out
+	of reload_combine.
+	(reload_combine): Use it.  Only initialize first_index_reg and
+	last_index_reg once.
+
+	2010-07-17  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/42235
+	gcc/
+	* postreload.c (reload_cse_move2add): Return bool, true if anything.
+	changed.  All callers changed.
+	(move2add_use_add2_insn): Likewise.
+	(move2add_use_add3_insn): Likewise.
+	(reload_cse_regs): If reload_cse_move2add changed anything, rerun
+	reload_combine.
+	(RELOAD_COMBINE_MAX_USES): Bump to 16.
+	(last_jump_ruid): New static variable.
+	(struct reg_use): New members CONTAINING_MEM and RUID.
+	(reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID.
+	(reload_combine_split_one_ruid, reload_combine_split_ruids,
+	reload_combine_purge_insn_uses, reload_combine_closest_single_use
+	reload_combine_purge_reg_uses_after_ruid,
+	reload_combine_recognize_const_pattern): New static functions.
+	(reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH
+	is true for our reg and that we have available index regs.
+	(reload_combine_note_use): New args RUID and CONTAINING_MEM.  All
+	callers changed.  Use them to initialize fields in struct reg_use.
+	(reload_combine): Initialize last_jump_ruid.  Be careful when to
+	take PREV_INSN of the scanned insn.  Update REAL_STORE_RUID fields.
+	Call reload_combine_recognize_const_pattern.
+	(reload_combine_note_store): Update REAL_STORE_RUID field.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42235.c: New test.
+
+	2010-07-19  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (reload_combine_closest_single_use): Ignore the
+	number of uses for DEBUG_INSNs.
+	(fixup_debug_insns): New static function.
+	(reload_combine_recognize_const_pattern): Use it.  Don't let the
+	main loop be affected by DEBUG_INSNs.
+	Really disallow moving adds past a jump insn.
+	(reload_combine_recognize_pattern): Don't update use_ruid here.
+	(reload_combine_note_use): Do it here.
+	(reload_combine): Use control_flow_insn_p rather than JUMP_P.
+
+	2010-07-20  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (fixup_debug_insns): Remove arg REGNO.  New args
+	FROM and TO.  All callers changed.  Don't look for tracked uses,
+	just scan the RTL for DEBUG_INSNs and substitute.
+	(reload_combine_recognize_pattern): Call fixup_debug_insns.
+	(reload_combine): Ignore DEBUG_INSNs.
+
+	2010-07-22  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR bootstrap/44970
+	PR middle-end/45009
+	gcc/
+	* postreload.c: Include "target.h".
+	(reload_combine_closest_single_use): Don't take DEBUG_INSNs
+	into account.
+	(fixup_debug_insns): Don't copy the rtx.
+	(reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses.
+	Don't copy when replacing.  Call fixup_debug_insns in the case where
+	we merged one add with another.
+	(reload_combine_recognize_pattern): Fail if there aren't any uses.
+	Try harder to determine whether we're picking a valid index register.
+	Don't set store_ruid for an insn we're going to scan in the
+	next iteration.
+	(reload_combine): Remove unused code.
+	(reload_combine_note_use): When updating use information for
+	an old insn, ignore a use that occurs after store_ruid.
+	* Makefile.in (postreload.o): Update dependencies.
+
+	2010-07-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (reload_combine_recognize_const_pattern): Move test
+	for limiting the insn movement to the right scope.
+
+	2010-07-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (try_replace_in_use): New static function.
+	(reload_combine_recognize_const_pattern): Use it here.  Allow
+	substituting into a final add insn, and substituting into a memory
+	reference in an insn that sets the reg.
+
+=== modified file 'gcc/Makefile.in'
+--- old/gcc/Makefile.in	2010-10-14 11:25:44 +0000
++++ new/gcc/Makefile.in	2010-11-08 22:08:43 +0000
+@@ -3155,7 +3155,7 @@
+    $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \
+    hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \
+    $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \
+-   $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
++   $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
+ postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
+    $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \
+    $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
+
+=== modified file 'gcc/postreload.c'
+--- old/gcc/postreload.c	2010-10-14 11:32:02 +0000
++++ new/gcc/postreload.c	2010-11-08 22:08:43 +0000
+@@ -44,7 +44,6 @@
+ #include "toplev.h"
+ #include "except.h"
+ #include "tree.h"
+-#include "target.h"
+ #include "timevar.h"
+ #include "tree-pass.h"
+ #include "df.h"
+@@ -57,10 +56,10 @@
+ static int reload_cse_simplify_operands (rtx, rtx);
+ 
+ static void reload_combine (void);
+-static void reload_combine_note_use (rtx *, rtx, int, rtx);
++static void reload_combine_note_use (rtx *, rtx);
+ static void reload_combine_note_store (rtx, const_rtx, void *);
+ 
+-static bool reload_cse_move2add (rtx);
++static void reload_cse_move2add (rtx);
+ static void move2add_note_store (rtx, const_rtx, void *);
+ 
+ /* Call cse / combine like post-reload optimization phases.
+@@ -68,16 +67,11 @@
+ void
+ reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
+ {
+-  bool moves_converted;
+   reload_cse_regs_1 (first);
+   reload_combine ();
+-  moves_converted = reload_cse_move2add (first);
++  reload_cse_move2add (first);
+   if (flag_expensive_optimizations)
+-    {
+-      if (moves_converted)
+-	reload_combine ();
+-      reload_cse_regs_1 (first);
+-    }
++    reload_cse_regs_1 (first);
+ }
+ 
+ /* See whether a single set SET is a noop.  */
+@@ -666,43 +660,30 @@
+ 
+ /* The maximum number of uses of a register we can keep track of to
+    replace them with reg+reg addressing.  */
+-#define RELOAD_COMBINE_MAX_USES 16
++#define RELOAD_COMBINE_MAX_USES 6
+ 
+-/* Describes a recorded use of a register.  */
+-struct reg_use
+-{
+-  /* The insn where a register has been used.  */
+-  rtx insn;
+-  /* Points to the memory reference enclosing the use, if any, NULL_RTX
+-     otherwise.  */
+-  rtx containing_mem;
+-  /* Location of the register withing INSN.  */
+-  rtx *usep;
+-  /* The reverse uid of the insn.  */
+-  int ruid;
+-};
++/* INSN is the insn where a register has been used, and USEP points to the
++   location of the register within the rtl.  */
++struct reg_use { rtx insn, *usep; };
+ 
+ /* If the register is used in some unknown fashion, USE_INDEX is negative.
+    If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
+-   indicates where it is first set or clobbered.
++   indicates where it becomes live again.
+    Otherwise, USE_INDEX is the index of the last encountered use of the
+-   register (which is first among these we have seen since we scan backwards).
+-   USE_RUID indicates the first encountered, i.e. last, of these uses.
+-   If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
+-   with a constant offset; OFFSET contains this constant in that case.
++   register (which is first among these we have seen since we scan backwards),
++   OFFSET contains the constant offset that is added to the register in
++   all encountered uses, and USE_RUID indicates the first encountered, i.e.
++   last, of these uses.
+    STORE_RUID is always meaningful if we only want to use a value in a
+    register in a different place: it denotes the next insn in the insn
+-   stream (i.e. the last encountered) that sets or clobbers the register.
+-   REAL_STORE_RUID is similar, but clobbers are ignored when updating it.  */
++   stream (i.e. the last encountered) that sets or clobbers the register.  */
+ static struct
+   {
+     struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
++    int use_index;
+     rtx offset;
+-    int use_index;
+     int store_ruid;
+-    int real_store_ruid;
+     int use_ruid;
+-    bool all_offsets_match;
+   } reg_state[FIRST_PSEUDO_REGISTER];
+ 
+ /* Reverse linear uid.  This is increased in reload_combine while scanning
+@@ -710,548 +691,42 @@
+    and the store_ruid / use_ruid fields in reg_state.  */
+ static int reload_combine_ruid;
+ 
+-/* The RUID of the last label we encountered in reload_combine.  */
+-static int last_label_ruid;
+-
+-/* The RUID of the last jump we encountered in reload_combine.  */
+-static int last_jump_ruid;
+-
+-/* The register numbers of the first and last index register.  A value of
+-   -1 in LAST_INDEX_REG indicates that we've previously computed these
+-   values and found no suitable index registers.  */
+-static int first_index_reg = -1;
+-static int last_index_reg;
+-
+ #define LABEL_LIVE(LABEL) \
+   (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
+ 
+-/* Subroutine of reload_combine_split_ruids, called to fix up a single
+-   ruid pointed to by *PRUID if it is higher than SPLIT_RUID.  */
+-
+-static inline void
+-reload_combine_split_one_ruid (int *pruid, int split_ruid)
+-{
+-  if (*pruid > split_ruid)
+-    (*pruid)++;
+-}
+-
+-/* Called when we insert a new insn in a position we've already passed in
+-   the scan.  Examine all our state, increasing all ruids that are higher
+-   than SPLIT_RUID by one in order to make room for a new insn.  */
+-
+-static void
+-reload_combine_split_ruids (int split_ruid)
+-{
+-  unsigned i;
+-
+-  reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
+-  reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
+-  reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
+-
+-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+-    {
+-      int j, idx = reg_state[i].use_index;
+-      reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
+-      reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
+-      reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
+-				     split_ruid);
+-      if (idx < 0)
+-	continue;
+-      for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
+-	{
+-	  reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
+-					 split_ruid);
+-	}
+-    }
+-}
+-
+-/* Called when we are about to rescan a previously encountered insn with
+-   reload_combine_note_use after modifying some part of it.  This clears all
+-   information about uses in that particular insn.  */
+-
+-static void
+-reload_combine_purge_insn_uses (rtx insn)
+-{
+-  unsigned i;
+-
+-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+-    {
+-      int j, k, idx = reg_state[i].use_index;
+-      if (idx < 0)
+-	continue;
+-      j = k = RELOAD_COMBINE_MAX_USES;
+-      while (j-- > idx)
+-	{
+-	  if (reg_state[i].reg_use[j].insn != insn)
+-	    {
+-	      k--;
+-	      if (k != j)
+-		reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
+-	    }
+-	}
+-      reg_state[i].use_index = k;
+-    }
+-}
+-
+-/* Called when we need to forget about all uses of REGNO after an insn
+-   which is identified by RUID.  */
+-
+-static void
+-reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
+-{
+-  int j, k, idx = reg_state[regno].use_index;
+-  if (idx < 0)
+-    return;
+-  j = k = RELOAD_COMBINE_MAX_USES;
+-  while (j-- > idx)
+-    {
+-      if (reg_state[regno].reg_use[j].ruid >= ruid)
+-	{
+-	  k--;
+-	  if (k != j)
+-	    reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
+-	}
+-    }
+-  reg_state[regno].use_index = k;
+-}
+-
+-/* Find the use of REGNO with the ruid that is highest among those
+-   lower than RUID_LIMIT, and return it if it is the only use of this
+-   reg in the insn.  Return NULL otherwise.  */
+-
+-static struct reg_use *
+-reload_combine_closest_single_use (unsigned regno, int ruid_limit)
+-{
+-  int i, best_ruid = 0;
+-  int use_idx = reg_state[regno].use_index;
+-  struct reg_use *retval;
+-
+-  if (use_idx < 0)
+-    return NULL;
+-  retval = NULL;
+-  for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
+-    {
+-      struct reg_use *use = reg_state[regno].reg_use + i; 
+-      int this_ruid = use->ruid;
+-      if (this_ruid >= ruid_limit)
+-	continue;
+-      if (this_ruid > best_ruid)
+-	{
+-	  best_ruid = this_ruid;
+-	  retval = use;
+-	}
+-      else if (this_ruid == best_ruid)
+-	retval = NULL;
+-    }
+-  if (last_label_ruid >= best_ruid)
+-    return NULL;
+-  return retval;
+-}
+-
+-/* After we've moved an add insn, fix up any debug insns that occur
+-   between the old location of the add and the new location.  REG is
+-   the destination register of the add insn; REPLACEMENT is the
+-   SET_SRC of the add.  FROM and TO specify the range in which we
+-   should make this change on debug insns.  */
+-
+-static void
+-fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
+-{
+-  rtx insn;
+-  for (insn = from; insn != to; insn = NEXT_INSN (insn))
+-    {
+-      rtx t;
+-
+-      if (!DEBUG_INSN_P (insn))
+-	continue;
+-      
+-      t = INSN_VAR_LOCATION_LOC (insn);
+-      t = simplify_replace_rtx (t, reg, replacement);
+-      validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
+-    }
+-}
+-
+-/* Subroutine of reload_combine_recognize_const_pattern.  Try to replace REG
+-   with SRC in the insn described by USE, taking costs into account.  Return
+-   true if we made the replacement.  */
+-
+-static bool
+-try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
+-{
+-  rtx use_insn = use->insn;
+-  rtx mem = use->containing_mem;
+-  bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
+-
+-  if (mem != NULL_RTX)
+-    {
+-      addr_space_t as = MEM_ADDR_SPACE (mem);
+-      rtx oldaddr = XEXP (mem, 0);
+-      rtx newaddr = NULL_RTX;
+-      int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
+-      int new_cost;
+-
+-      newaddr = simplify_replace_rtx (oldaddr, reg, src);
+-      if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
+-	{
+-	  XEXP (mem, 0) = newaddr;
+-	  new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
+-	  XEXP (mem, 0) = oldaddr;
+-	  if (new_cost <= old_cost
+-	      && validate_change (use_insn,
+-				  &XEXP (mem, 0), newaddr, 0))
+-	    return true;
+-	}
+-    }
+-  else
+-    {
+-      rtx new_set = single_set (use_insn);
+-      if (new_set
+-	  && REG_P (SET_DEST (new_set))
+-	  && GET_CODE (SET_SRC (new_set)) == PLUS
+-	  && REG_P (XEXP (SET_SRC (new_set), 0))
+-	  && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
+-	{
+-	  rtx new_src;
+-	  int old_cost = rtx_cost (SET_SRC (new_set), SET, speed);
+-
+-	  gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
+-	  new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
+-
+-	  if (rtx_cost (new_src, SET, speed) <= old_cost
+-	      && validate_change (use_insn, &SET_SRC (new_set),
+-				  new_src, 0))
+-	    return true;
+-	}
+-    }
+-  return false;
+-}
+-
+-/* Called by reload_combine when scanning INSN.  This function tries to detect
+-   patterns where a constant is added to a register, and the result is used
+-   in an address.
+-   Return true if no further processing is needed on INSN; false if it wasn't
+-   recognized and should be handled normally.  */
+-
+-static bool
+-reload_combine_recognize_const_pattern (rtx insn)
+-{
+-  int from_ruid = reload_combine_ruid;
+-  rtx set, pat, reg, src, addreg;
+-  unsigned int regno;
+-  struct reg_use *use;
+-  bool must_move_add;
+-  rtx add_moved_after_insn = NULL_RTX;
+-  int add_moved_after_ruid = 0;
+-  int clobbered_regno = -1;
+-
+-  set = single_set (insn);
+-  if (set == NULL_RTX)
+-    return false;
+-
+-  reg = SET_DEST (set);
+-  src = SET_SRC (set);
+-  if (!REG_P (reg)
+-      || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
+-      || GET_MODE (reg) != Pmode
+-      || reg == stack_pointer_rtx)
+-    return false;
+-
+-  regno = REGNO (reg);
+-
+-  /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
+-     uses of REG1 inside an address, or inside another add insn.  If
+-     possible and profitable, merge the addition into subsequent
+-     uses.  */
+-  if (GET_CODE (src) != PLUS
+-      || !REG_P (XEXP (src, 0))
+-      || !CONSTANT_P (XEXP (src, 1)))
+-    return false;
+-
+-  addreg = XEXP (src, 0);
+-  must_move_add = rtx_equal_p (reg, addreg);
+-
+-  pat = PATTERN (insn);
+-  if (must_move_add && set != pat)
+-    {
+-      /* We have to be careful when moving the add; apart from the
+-	 single_set there may also be clobbers.  Recognize one special
+-	 case, that of one clobber alongside the set (likely a clobber
+-	 of the CC register).  */
+-      gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
+-      if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
+-	  || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
+-	  || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
+-	return false;
+-      clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
+-    }
+-
+-  do
+-    {
+-      use = reload_combine_closest_single_use (regno, from_ruid);
+-
+-      if (use)
+-	/* Start the search for the next use from here.  */
+-	from_ruid = use->ruid;
+-
+-      if (use && GET_MODE (*use->usep) == Pmode)
+-	{
+-	  bool delete_add = false;
+-	  rtx use_insn = use->insn;
+-	  int use_ruid = use->ruid;
+-
+-	  /* Avoid moving the add insn past a jump.  */
+-	  if (must_move_add && use_ruid <= last_jump_ruid)
+-	    break;
+-
+-	  /* If the add clobbers another hard reg in parallel, don't move
+-	     it past a real set of this hard reg.  */
+-	  if (must_move_add && clobbered_regno >= 0
+-	      && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
+-	    break;
+-
+-	  gcc_assert (reg_state[regno].store_ruid <= use_ruid);
+-	  /* Avoid moving a use of ADDREG past a point where it is stored.  */
+-	  if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
+-	    break;
+-
+-	  /* We also must not move the addition past an insn that sets
+-	     the same register, unless we can combine two add insns.  */
+-	  if (must_move_add && reg_state[regno].store_ruid == use_ruid)
+-	    {
+-	      if (use->containing_mem == NULL_RTX)
+-		delete_add = true;
+-	      else
+-		break;
+-	    }
+-
+-	  if (try_replace_in_use (use, reg, src))
+-	    {
+-	      reload_combine_purge_insn_uses (use_insn);
+-	      reload_combine_note_use (&PATTERN (use_insn), use_insn,
+-				       use_ruid, NULL_RTX);
+-
+-	      if (delete_add)
+-		{
+-		  fixup_debug_insns (reg, src, insn, use_insn);
+-		  delete_insn (insn);
+-		  return true;
+-		}
+-	      if (must_move_add)
+-		{
+-		  add_moved_after_insn = use_insn;
+-		  add_moved_after_ruid = use_ruid;
+-		}
+-	      continue;
+-	    }
+-	}
+-      /* If we get here, we couldn't handle this use.  */
+-      if (must_move_add)
+-	break;
+-    }
+-  while (use);
+-
+-  if (!must_move_add || add_moved_after_insn == NULL_RTX)
+-    /* Process the add normally.  */
+-    return false;
+-
+-  fixup_debug_insns (reg, src, insn, add_moved_after_insn);
+-
+-  reorder_insns (insn, insn, add_moved_after_insn);
+-  reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
+-  reload_combine_split_ruids (add_moved_after_ruid - 1);
+-  reload_combine_note_use (&PATTERN (insn), insn,
+-			   add_moved_after_ruid, NULL_RTX);
+-  reg_state[regno].store_ruid = add_moved_after_ruid;
+-
+-  return true;
+-}
+-
+-/* Called by reload_combine when scanning INSN.  Try to detect a pattern we
+-   can handle and improve.  Return true if no further processing is needed on
+-   INSN; false if it wasn't recognized and should be handled normally.  */
+-
+-static bool
+-reload_combine_recognize_pattern (rtx insn)
+-{
+-  rtx set, reg, src;
+-  unsigned int regno;
+-
+-  set = single_set (insn);
+-  if (set == NULL_RTX)
+-    return false;
+-
+-  reg = SET_DEST (set);
+-  src = SET_SRC (set);
+-  if (!REG_P (reg)
+-      || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
+-    return false;
+-
+-  regno = REGNO (reg);
+-
+-  /* Look for (set (REGX) (CONST_INT))
+-     (set (REGX) (PLUS (REGX) (REGY)))
+-     ...
+-     ... (MEM (REGX)) ...
+-     and convert it to
+-     (set (REGZ) (CONST_INT))
+-     ...
+-     ... (MEM (PLUS (REGZ) (REGY)))... .
+-
+-     First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
+-     and that we know all uses of REGX before it dies.
+-     Also, explicitly check that REGX != REGY; our life information
+-     does not yet show whether REGY changes in this insn.  */
+-
+-  if (GET_CODE (src) == PLUS
+-      && reg_state[regno].all_offsets_match
+-      && last_index_reg != -1
+-      && REG_P (XEXP (src, 1))
+-      && rtx_equal_p (XEXP (src, 0), reg)
+-      && !rtx_equal_p (XEXP (src, 1), reg)
+-      && reg_state[regno].use_index >= 0
+-      && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
+-      && last_label_ruid < reg_state[regno].use_ruid)
+-    {
+-      rtx base = XEXP (src, 1);
+-      rtx prev = prev_nonnote_insn (insn);
+-      rtx prev_set = prev ? single_set (prev) : NULL_RTX;
+-      rtx index_reg = NULL_RTX;
+-      rtx reg_sum = NULL_RTX;
+-      int i;
+-
+-      /* Now we need to set INDEX_REG to an index register (denoted as
+-	 REGZ in the illustration above) and REG_SUM to the expression
+-	 register+register that we want to use to substitute uses of REG
+-	 (typically in MEMs) with.  First check REG and BASE for being
+-	 index registers; we can use them even if they are not dead.  */
+-      if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
+-	  || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
+-				REGNO (base)))
+-	{
+-	  index_reg = reg;
+-	  reg_sum = src;
+-	}
+-      else
+-	{
+-	  /* Otherwise, look for a free index register.  Since we have
+-	     checked above that neither REG nor BASE are index registers,
+-	     if we find anything at all, it will be different from these
+-	     two registers.  */
+-	  for (i = first_index_reg; i <= last_index_reg; i++)
+-	    {
+-	      if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
+-		  && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
+-		  && reg_state[i].store_ruid <= reg_state[regno].use_ruid
+-		  && (call_used_regs[i] || df_regs_ever_live_p (i))
+-		  && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
+-		  && !fixed_regs[i] && !global_regs[i]
+-		  && hard_regno_nregs[i][GET_MODE (reg)] == 1
+-		  && targetm.hard_regno_scratch_ok (i))
+-		{
+-		  index_reg = gen_rtx_REG (GET_MODE (reg), i);
+-		  reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
+-		  break;
+-		}
+-	    }
+-	}
+-
+-      /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
+-	 (REGY), i.e. BASE, is not clobbered before the last use we'll
+-	 create.  */
+-      if (reg_sum
+-	  && prev_set
+-	  && CONST_INT_P (SET_SRC (prev_set))
+-	  && rtx_equal_p (SET_DEST (prev_set), reg)
+-	  && (reg_state[REGNO (base)].store_ruid
+-	      <= reg_state[regno].use_ruid))
+-	{
+-	  /* Change destination register and, if necessary, the constant
+-	     value in PREV, the constant loading instruction.  */
+-	  validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
+-	  if (reg_state[regno].offset != const0_rtx)
+-	    validate_change (prev,
+-			     &SET_SRC (prev_set),
+-			     GEN_INT (INTVAL (SET_SRC (prev_set))
+-				      + INTVAL (reg_state[regno].offset)),
+-			     1);
+-
+-	  /* Now for every use of REG that we have recorded, replace REG
+-	     with REG_SUM.  */
+-	  for (i = reg_state[regno].use_index;
+-	       i < RELOAD_COMBINE_MAX_USES; i++)
+-	    validate_unshare_change (reg_state[regno].reg_use[i].insn,
+-				     reg_state[regno].reg_use[i].usep,
+-				     /* Each change must have its own
+-					replacement.  */
+-				     reg_sum, 1);
+-
+-	  if (apply_change_group ())
+-	    {
+-	      struct reg_use *lowest_ruid = NULL;
+-
+-	      /* For every new use of REG_SUM, we have to record the use
+-		 of BASE therein, i.e. operand 1.  */
+-	      for (i = reg_state[regno].use_index;
+-		   i < RELOAD_COMBINE_MAX_USES; i++)
+-		{
+-		  struct reg_use *use = reg_state[regno].reg_use + i;
+-		  reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
+-					   use->ruid, use->containing_mem);
+-		  if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
+-		    lowest_ruid = use;
+-		}
+-
+-	      fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
+-
+-	      /* Delete the reg-reg addition.  */
+-	      delete_insn (insn);
+-
+-	      if (reg_state[regno].offset != const0_rtx)
+-		/* Previous REG_EQUIV / REG_EQUAL notes for PREV
+-		   are now invalid.  */
+-		remove_reg_equal_equiv_notes (prev);
+-
+-	      reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
+-	      return true;
+-	    }
+-	}
+-    }
+-  return false;
+-}
+-
+ static void
+ reload_combine (void)
+ {
+-  rtx insn, prev;
++  rtx insn, set;
++  int first_index_reg = -1;
++  int last_index_reg = 0;
+   int i;
+   basic_block bb;
+   unsigned int r;
++  int last_label_ruid;
+   int min_labelno, n_labels;
+   HARD_REG_SET ever_live_at_start, *label_live;
+ 
++  /* If reg+reg can be used in offsetable memory addresses, the main chunk of
++     reload has already used it where appropriate, so there is no use in
++     trying to generate it now.  */
++  if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
++    return;
++
+   /* To avoid wasting too much time later searching for an index register,
+      determine the minimum and maximum index register numbers.  */
+-  if (INDEX_REG_CLASS == NO_REGS)
+-    last_index_reg = -1;
+-  else if (first_index_reg == -1 && last_index_reg == 0)
+-    {
+-      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+-	if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
+-	  {
+-	    if (first_index_reg == -1)
+-	      first_index_reg = r;
+-
+-	    last_index_reg = r;
+-	  }
+-
+-      /* If no index register is available, we can quit now.  Set LAST_INDEX_REG
+-	 to -1 so we'll know to quit early the next time we get here.  */
+-      if (first_index_reg == -1)
+-	{
+-	  last_index_reg = -1;
+-	  return;
+-	}
+-    }
++  for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
++    if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
++      {
++	if (first_index_reg == -1)
++	  first_index_reg = r;
++
++	last_index_reg = r;
++      }
++
++  /* If no index register is available, we can quit now.  */
++  if (first_index_reg == -1)
++    return;
+ 
+   /* Set up LABEL_LIVE and EVER_LIVE_AT_START.  The register lifetime
+      information is a bit fuzzy immediately after reload, but it's
+@@ -1278,23 +753,20 @@
+     }
+ 
+   /* Initialize last_label_ruid, reload_combine_ruid and reg_state.  */
+-  last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
++  last_label_ruid = reload_combine_ruid = 0;
+   for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+     {
+-      reg_state[r].store_ruid = 0;
+-      reg_state[r].real_store_ruid = 0;
++      reg_state[r].store_ruid = reload_combine_ruid;
+       if (fixed_regs[r])
+ 	reg_state[r].use_index = -1;
+       else
+ 	reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+     }
+ 
+-  for (insn = get_last_insn (); insn; insn = prev)
++  for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
+     {
+       rtx note;
+ 
+-      prev = PREV_INSN (insn);
+-
+       /* We cannot do our optimization across labels.  Invalidating all the use
+ 	 information we have would be costly, so we just note where the label
+ 	 is and then later disable any optimization that would cross it.  */
+@@ -1305,17 +777,141 @@
+ 	  if (! fixed_regs[r])
+ 	      reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+ 
+-      if (! NONDEBUG_INSN_P (insn))
++      if (! INSN_P (insn))
+ 	continue;
+ 
+       reload_combine_ruid++;
+ 
+-      if (control_flow_insn_p (insn))
+-	last_jump_ruid = reload_combine_ruid;
+-
+-      if (reload_combine_recognize_const_pattern (insn)
+-	  || reload_combine_recognize_pattern (insn))
+-	continue;
++      /* Look for (set (REGX) (CONST_INT))
++	 (set (REGX) (PLUS (REGX) (REGY)))
++	 ...
++	 ... (MEM (REGX)) ...
++	 and convert it to
++	 (set (REGZ) (CONST_INT))
++	 ...
++	 ... (MEM (PLUS (REGZ) (REGY)))... .
++
++	 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
++	 and that we know all uses of REGX before it dies.
++	 Also, explicitly check that REGX != REGY; our life information
++	 does not yet show whether REGY changes in this insn.  */
++      set = single_set (insn);
++      if (set != NULL_RTX
++	  && REG_P (SET_DEST (set))
++	  && (hard_regno_nregs[REGNO (SET_DEST (set))]
++			      [GET_MODE (SET_DEST (set))]
++	      == 1)
++	  && GET_CODE (SET_SRC (set)) == PLUS
++	  && REG_P (XEXP (SET_SRC (set), 1))
++	  && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
++	  && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set))
++	  && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
++	{
++	  rtx reg = SET_DEST (set);
++	  rtx plus = SET_SRC (set);
++	  rtx base = XEXP (plus, 1);
++	  rtx prev = prev_nonnote_nondebug_insn (insn);
++	  rtx prev_set = prev ? single_set (prev) : NULL_RTX;
++	  unsigned int regno = REGNO (reg);
++	  rtx index_reg = NULL_RTX;
++	  rtx reg_sum = NULL_RTX;
++
++	  /* Now we need to set INDEX_REG to an index register (denoted as
++	     REGZ in the illustration above) and REG_SUM to the expression
++	     register+register that we want to use to substitute uses of REG
++	     (typically in MEMs) with.  First check REG and BASE for being
++	     index registers; we can use them even if they are not dead.  */
++	  if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
++	      || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
++				    REGNO (base)))
++	    {
++	      index_reg = reg;
++	      reg_sum = plus;
++	    }
++	  else
++	    {
++	      /* Otherwise, look for a free index register.  Since we have
++		 checked above that neither REG nor BASE are index registers,
++		 if we find anything at all, it will be different from these
++		 two registers.  */
++	      for (i = first_index_reg; i <= last_index_reg; i++)
++		{
++		  if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
++					 i)
++		      && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
++		      && reg_state[i].store_ruid <= reg_state[regno].use_ruid
++		      && hard_regno_nregs[i][GET_MODE (reg)] == 1)
++		    {
++		      index_reg = gen_rtx_REG (GET_MODE (reg), i);
++		      reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
++		      break;
++		    }
++		}
++	    }
++
++	  /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
++	     (REGY), i.e. BASE, is not clobbered before the last use we'll
++	     create.  */
++	  if (reg_sum
++	      && prev_set
++	      && CONST_INT_P (SET_SRC (prev_set))
++	      && rtx_equal_p (SET_DEST (prev_set), reg)
++	      && reg_state[regno].use_index >= 0
++	      && (reg_state[REGNO (base)].store_ruid
++		  <= reg_state[regno].use_ruid))
++	    {
++	      int i;
++
++	      /* Change destination register and, if necessary, the constant
++		 value in PREV, the constant loading instruction.  */
++	      validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
++	      if (reg_state[regno].offset != const0_rtx)
++		validate_change (prev,
++				 &SET_SRC (prev_set),
++				 GEN_INT (INTVAL (SET_SRC (prev_set))
++					  + INTVAL (reg_state[regno].offset)),
++				 1);
++
++	      /* Now for every use of REG that we have recorded, replace REG
++		 with REG_SUM.  */
++	      for (i = reg_state[regno].use_index;
++		   i < RELOAD_COMBINE_MAX_USES; i++)
++		validate_unshare_change (reg_state[regno].reg_use[i].insn,
++				 	 reg_state[regno].reg_use[i].usep,
++				 	 /* Each change must have its own
++				    	    replacement.  */
++				 	 reg_sum, 1);
++
++	      if (apply_change_group ())
++		{
++		  /* For every new use of REG_SUM, we have to record the use
++		     of BASE therein, i.e. operand 1.  */
++		  for (i = reg_state[regno].use_index;
++		       i < RELOAD_COMBINE_MAX_USES; i++)
++		    reload_combine_note_use
++		      (&XEXP (*reg_state[regno].reg_use[i].usep, 1),
++		       reg_state[regno].reg_use[i].insn);
++
++		  if (reg_state[REGNO (base)].use_ruid
++		      > reg_state[regno].use_ruid)
++		    reg_state[REGNO (base)].use_ruid
++		      = reg_state[regno].use_ruid;
++
++		  /* Delete the reg-reg addition.  */
++		  delete_insn (insn);
++
++		  if (reg_state[regno].offset != const0_rtx)
++		    /* Previous REG_EQUIV / REG_EQUAL notes for PREV
++		       are now invalid.  */
++		    remove_reg_equal_equiv_notes (prev);
++
++		  reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
++		  reg_state[REGNO (index_reg)].store_ruid
++		    = reload_combine_ruid;
++		  continue;
++		}
++	    }
++	}
+ 
+       note_stores (PATTERN (insn), reload_combine_note_store, NULL);
+ 
+@@ -1371,8 +967,7 @@
+ 	      reg_state[i].use_index = -1;
+ 	}
+ 
+-      reload_combine_note_use (&PATTERN (insn), insn,
+-			       reload_combine_ruid, NULL_RTX);
++      reload_combine_note_use (&PATTERN (insn), insn);
+       for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+ 	{
+ 	  if (REG_NOTE_KIND (note) == REG_INC
+@@ -1381,7 +976,6 @@
+ 	      int regno = REGNO (XEXP (note, 0));
+ 
+ 	      reg_state[regno].store_ruid = reload_combine_ruid;
+-	      reg_state[regno].real_store_ruid = reload_combine_ruid;
+ 	      reg_state[regno].use_index = -1;
+ 	    }
+ 	}
+@@ -1391,8 +985,8 @@
+ }
+ 
+ /* Check if DST is a register or a subreg of a register; if it is,
+-   update store_ruid, real_store_ruid and use_index in the reg_state
+-   structure accordingly.  Called via note_stores from reload_combine.  */
++   update reg_state[regno].store_ruid and reg_state[regno].use_index
++   accordingly.  Called via note_stores from reload_combine.  */
+ 
+ static void
+ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
+@@ -1416,14 +1010,14 @@
+   /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
+      careful with registers / register parts that are not full words.
+      Similarly for ZERO_EXTRACT.  */
+-  if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
++  if (GET_CODE (set) != SET
++      || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
+       || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
+     {
+       for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
+ 	{
+ 	  reg_state[i].use_index = -1;
+ 	  reg_state[i].store_ruid = reload_combine_ruid;
+-	  reg_state[i].real_store_ruid = reload_combine_ruid;
+ 	}
+     }
+   else
+@@ -1431,8 +1025,6 @@
+       for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
+ 	{
+ 	  reg_state[i].store_ruid = reload_combine_ruid;
+-	  if (GET_CODE (set) == SET)
+-	    reg_state[i].real_store_ruid = reload_combine_ruid;
+ 	  reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
+ 	}
+     }
+@@ -1443,7 +1035,7 @@
+    *XP is the pattern of INSN, or a part of it.
+    Called from reload_combine, and recursively by itself.  */
+ static void
+-reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
++reload_combine_note_use (rtx *xp, rtx insn)
+ {
+   rtx x = *xp;
+   enum rtx_code code = x->code;
+@@ -1456,7 +1048,7 @@
+     case SET:
+       if (REG_P (SET_DEST (x)))
+ 	{
+-	  reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
++	  reload_combine_note_use (&SET_SRC (x), insn);
+ 	  return;
+ 	}
+       break;
+@@ -1512,11 +1104,6 @@
+ 	    return;
+ 	  }
+ 
+-	/* We may be called to update uses in previously seen insns.
+-	   Don't add uses beyond the last store we saw.  */
+-	if (ruid < reg_state[regno].store_ruid)
+-	  return;
+-
+ 	/* If this register is already used in some unknown fashion, we
+ 	   can't do anything.
+ 	   If we decrement the index from zero to -1, we can't store more
+@@ -1525,34 +1112,29 @@
+ 	if (use_index < 0)
+ 	  return;
+ 
+-	if (use_index == RELOAD_COMBINE_MAX_USES - 1)
++	if (use_index != RELOAD_COMBINE_MAX_USES - 1)
++	  {
++	    /* We have found another use for a register that is already
++	       used later.  Check if the offsets match; if not, mark the
++	       register as used in an unknown fashion.  */
++	    if (! rtx_equal_p (offset, reg_state[regno].offset))
++	      {
++		reg_state[regno].use_index = -1;
++		return;
++	      }
++	  }
++	else
+ 	  {
+ 	    /* This is the first use of this register we have seen since we
+ 	       marked it as dead.  */
+ 	    reg_state[regno].offset = offset;
+-	    reg_state[regno].all_offsets_match = true;
+-	    reg_state[regno].use_ruid = ruid;
+-	  }
+-	else
+-	  {
+-	    if (reg_state[regno].use_ruid > ruid)
+-	      reg_state[regno].use_ruid = ruid;
+-
+-	    if (! rtx_equal_p (offset, reg_state[regno].offset))
+-	      reg_state[regno].all_offsets_match = false;
+-	  }
+-
++	    reg_state[regno].use_ruid = reload_combine_ruid;
++	  }
+ 	reg_state[regno].reg_use[use_index].insn = insn;
+-	reg_state[regno].reg_use[use_index].ruid = ruid;
+-	reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
+ 	reg_state[regno].reg_use[use_index].usep = xp;
+ 	return;
+       }
+ 
+-    case MEM:
+-      containing_mem = x;
+-      break;
+-
+     default:
+       break;
+     }
+@@ -1562,12 +1144,11 @@
+   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+     {
+       if (fmt[i] == 'e')
+-	reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
++	reload_combine_note_use (&XEXP (x, i), insn);
+       else if (fmt[i] == 'E')
+ 	{
+ 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+-	    reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
+-				     containing_mem);
++	    reload_combine_note_use (&XVECEXP (x, i, j), insn);
+ 	}
+     }
+ }
+@@ -1615,10 +1196,9 @@
+    while REG is known to already have value (SYM + offset).
+    This function tries to change INSN into an add instruction
+    (set (REG) (plus (REG) (OFF - offset))) using the known value.
+-   It also updates the information about REG's known value.
+-   Return true if we made a change.  */
++   It also updates the information about REG's known value.  */
+ 
+-static bool
++static void
+ move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
+ {
+   rtx pat = PATTERN (insn);
+@@ -1627,7 +1207,6 @@
+   rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
+ 			      GET_MODE (reg));
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+-  bool changed = false;
+ 
+   /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
+      use (set (reg) (reg)) instead.
+@@ -1642,13 +1221,13 @@
+ 	 (reg)), would be discarded.  Maybe we should
+ 	 try a truncMN pattern?  */
+       if (INTVAL (off) == reg_offset [regno])
+-	changed = validate_change (insn, &SET_SRC (pat), reg, 0);
++	validate_change (insn, &SET_SRC (pat), reg, 0);
+     }
+   else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
+ 	   && have_add2_insn (reg, new_src))
+     {
+       rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
+-      changed = validate_change (insn, &SET_SRC (pat), tem, 0);
++      validate_change (insn, &SET_SRC (pat), tem, 0);
+     }
+   else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
+     {
+@@ -1673,9 +1252,8 @@
+ 			     gen_rtx_STRICT_LOW_PART (VOIDmode,
+ 						      narrow_reg),
+ 			     narrow_src);
+-	      changed = validate_change (insn, &PATTERN (insn),
+-					 new_set, 0);
+-	      if (changed)
++	      if (validate_change (insn, &PATTERN (insn),
++				   new_set, 0))
+ 		break;
+ 	    }
+ 	}
+@@ -1685,7 +1263,6 @@
+   reg_mode[regno] = GET_MODE (reg);
+   reg_symbol_ref[regno] = sym;
+   reg_offset[regno] = INTVAL (off);
+-  return changed;
+ }
+ 
+ 
+@@ -1695,10 +1272,9 @@
+    value (SYM + offset) and change INSN into an add instruction
+    (set (REG) (plus (the found register) (OFF - offset))) if such
+    a register is found.  It also updates the information about
+-   REG's known value.
+-   Return true iff we made a change.  */
++   REG's known value.  */
+ 
+-static bool
++static void
+ move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
+ {
+   rtx pat = PATTERN (insn);
+@@ -1708,7 +1284,6 @@
+   int min_regno;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int i;
+-  bool changed = false;
+ 
+   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     if (reg_set_luid[i] > move2add_last_label_luid
+@@ -1753,25 +1328,20 @@
+ 				      GET_MODE (reg));
+ 	  tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
+ 	}
+-      if (validate_change (insn, &SET_SRC (pat), tem, 0))
+-	changed = true;
++      validate_change (insn, &SET_SRC (pat), tem, 0);
+     }
+   reg_set_luid[regno] = move2add_luid;
+   reg_base_reg[regno] = -1;
+   reg_mode[regno] = GET_MODE (reg);
+   reg_symbol_ref[regno] = sym;
+   reg_offset[regno] = INTVAL (off);
+-  return changed;
+ }
+ 
+-/* Convert move insns with constant inputs to additions if they are cheaper.
+-   Return true if any changes were made.  */
+-static bool
++static void
+ reload_cse_move2add (rtx first)
+ {
+   int i;
+   rtx insn;
+-  bool changed = false;
+ 
+   for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
+     {
+@@ -1832,7 +1402,7 @@
+ 		  && reg_base_reg[regno] < 0
+ 		  && reg_symbol_ref[regno] == NULL_RTX)
+ 		{
+-		  changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
++		  move2add_use_add2_insn (reg, NULL_RTX, src, insn);
+ 		  continue;
+ 		}
+ 
+@@ -1893,7 +1463,6 @@
+ 			}
+ 		      if (success)
+ 			delete_insn (insn);
+-		      changed |= success;
+ 		      insn = next;
+ 		      reg_mode[regno] = GET_MODE (reg);
+ 		      reg_offset[regno] =
+@@ -1939,12 +1508,12 @@
+ 		  && reg_base_reg[regno] < 0
+ 		  && reg_symbol_ref[regno] != NULL_RTX
+ 		  && rtx_equal_p (sym, reg_symbol_ref[regno]))
+-		changed |= move2add_use_add2_insn (reg, sym, off, insn);
++		move2add_use_add2_insn (reg, sym, off, insn);
+ 
+ 	      /* Otherwise, we have to find a register whose value is sum
+ 		 of sym and some constant value.  */
+ 	      else
+-		changed |= move2add_use_add3_insn (reg, sym, off, insn);
++		move2add_use_add3_insn (reg, sym, off, insn);
+ 
+ 	      continue;
+ 	    }
+@@ -1999,7 +1568,6 @@
+ 	    }
+ 	}
+     }
+-  return changed;
+ }
+ 
+ /* SET is a SET or CLOBBER that sets DST.  DATA is the insn which
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch
new file mode 100644
index 0000000000..b63c9b35e7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch
@@ -0,0 +1,70 @@
+2010-11-03  Nathan Froyd  <froydnj@codesourcery.com>
+
+	Issue #10002
+
+	gcc/
+	* config/arm/arm.c (arm_legitimate_index_p): Split
+	VALID_NEON_QREG_MODE and VALID_NEON_DREG_MODE cases.  Permit
+	slightly larger constants in the latter case.
+	(thumb2_legitimate_index_p): Likewise.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-11-04 12:49:37 +0000
++++ new/gcc/config/arm/arm.c	2010-11-11 11:00:53 +0000
+@@ -5611,13 +5611,25 @@
+ 	    && INTVAL (index) > -1024
+ 	    && (INTVAL (index) & 3) == 0);
+ 
+-  if (TARGET_NEON
+-      && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)))
++  /* For quad modes, we restrict the constant offset to be slightly less
++     than what the instruction format permits.  We do this because for
++     quad mode moves, we will actually decompose them into two separate
++     double-mode reads or writes.  INDEX must therefore be a valid
++     (double-mode) offset and so should INDEX+8.  */
++  if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
+     return (code == CONST_INT
+ 	    && INTVAL (index) < 1016
+ 	    && INTVAL (index) > -1024
+ 	    && (INTVAL (index) & 3) == 0);
+ 
++  /* We have no such constraint on double mode offsets, so we permit the
++     full range of the instruction format.  */
++  if (TARGET_NEON && VALID_NEON_DREG_MODE (mode))
++    return (code == CONST_INT
++	    && INTVAL (index) < 1024
++	    && INTVAL (index) > -1024
++	    && (INTVAL (index) & 3) == 0);
++
+   if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
+     return (code == CONST_INT
+ 	    && INTVAL (index) < 1024
+@@ -5731,13 +5743,25 @@
+ 		&& (INTVAL (index) & 3) == 0);
+     }
+ 
+-  if (TARGET_NEON
+-      && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)))
++  /* For quad modes, we restrict the constant offset to be slightly less
++     than what the instruction format permits.  We do this because for
++     quad mode moves, we will actually decompose them into two separate
++     double-mode reads or writes.  INDEX must therefore be a valid
++     (double-mode) offset and so should INDEX+8.  */
++  if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
+     return (code == CONST_INT
+ 	    && INTVAL (index) < 1016
+ 	    && INTVAL (index) > -1024
+ 	    && (INTVAL (index) & 3) == 0);
+ 
++  /* We have no such constraint on double mode offsets, so we permit the
++     full range of the instruction format.  */
++  if (TARGET_NEON && VALID_NEON_DREG_MODE (mode))
++    return (code == CONST_INT
++	    && INTVAL (index) < 1024
++	    && INTVAL (index) > -1024
++	    && (INTVAL (index) & 3) == 0);
++
+   if (arm_address_register_rtx_p (index, strict_p)
+       && (GET_MODE_SIZE (mode) <= 4))
+     return 1;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99433.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99433.patch
new file mode 100644
index 0000000000..6bc33f2be2
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99433.patch
@@ -0,0 +1,40 @@
+2010-10-29  Julian Brown  <julian@codesourcery.com>
+
+	Launchpad #629671
+
+	gcc/
+	* config/arm/arm.h (REG_CLASS_CONTENTS): Remove soft frame pointer
+	from CORE_REGS and GENERAL_REGS classes.
+	* config/arm/arm.md (*thumb1_movsi_insn): Ignore all parts of final
+	constraint for register preferencing.
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/arm.h	2010-11-11 11:12:14 +0000
+@@ -1262,8 +1262,8 @@
+   { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */	\
+   { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */	\
+   { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */	\
+-  { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
+-  { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */	\
++  { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
++  { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */	\
+   { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF }  /* ALL_REGS */	\
+ }
+ 
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/arm.md	2010-11-11 11:12:14 +0000
+@@ -5160,8 +5160,8 @@
+ })
+ 
+ (define_insn "*thumb1_movsi_insn"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk")
+-	(match_operand:SI 1 "general_operand"      "l, I,J,K,>,l,mi,l,*lhk"))]
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*l*h*k")
++	(match_operand:SI 1 "general_operand"      "l, I,J,K,>,l,mi,l,*l*h*k"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], SImode) 
+        || register_operand (operands[1], SImode))"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99434.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99434.patch
new file mode 100644
index 0000000000..adda68c62e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99434.patch
@@ -0,0 +1,30 @@
+2010-11-3  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-11-02  Chung-Lin Tang <cltang@codesourcery.com>
+
+	gcc/
+	* Makefile.in (LIBGCC2_CFLAGS): Add -fno-stack-protector, to
+	explicitly disable stack protection when building libgcc.
+	(CRTSTUFF_CFLAGS): Same, for crtbegin/end.
+
+--- old/gcc/Makefile.in	2010-11-08 22:08:43 +0000
++++ new/gcc/Makefile.in	2010-11-11 11:34:59 +0000
+@@ -646,6 +646,7 @@
+ LIBGCC2_CFLAGS = -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) $(TARGET_LIBGCC2_CFLAGS) \
+ 		 $(LIBGCC2_DEBUG_CFLAGS) $(GTHREAD_FLAGS) \
+ 		 -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED \
++		 -fno-stack-protector \
+ 		 $(INHIBIT_LIBC_CFLAGS)
+ 
+ # Additional options to use when compiling libgcc2.a.
+@@ -659,6 +660,7 @@
+ CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
+   -finhibit-size-directive -fno-inline -fno-exceptions \
+   -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \
++  -fno-stack-protector \
+   $(INHIBIT_LIBC_CFLAGS)
+ 
+ # Additional sources to handle exceptions; overridden by targets as needed.
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99435.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99435.patch
new file mode 100644
index 0000000000..d66df137fa
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99435.patch
@@ -0,0 +1,32 @@
+2010-11-08  Yao Qi  <yao@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/
+	2010-08-02  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the
+	if statement which adds extra costs to frame-related
+	expressions.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-11-11 11:00:53 +0000
++++ new/gcc/config/arm/arm.c	2010-11-11 11:50:33 +0000
+@@ -6805,12 +6805,10 @@
+ 	 since then they might not be moved outside of loops.  As a compromise
+ 	 we allow integration with ops that have a constant as their second
+ 	 operand.  */
+-      if ((REG_OR_SUBREG_REG (XEXP (x, 0))
+-	   && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
+-	   && GET_CODE (XEXP (x, 1)) != CONST_INT)
+-	  || (REG_OR_SUBREG_REG (XEXP (x, 0))
+-	      && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
+-	*total = 4;
++      if (REG_OR_SUBREG_REG (XEXP (x, 0))
++	  && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
++	  && GET_CODE (XEXP (x, 1)) != CONST_INT)
++	*total = COSTS_N_INSNS (1);
+ 
+       if (mode == DImode)
+ 	{
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99436.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99436.patch
new file mode 100644
index 0000000000..1373b83ed7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99436.patch
@@ -0,0 +1,210 @@
+2010-11-24  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	gcc/
+	* combine.c (subst, combine_simlify_rtx): Add new argument, use it
+	to track processing of conditionals.  Update all callers.
+	(try_combine, simplify_if_then_else): Update.
+
+=== modified file 'gcc/combine.c'
+Index: gcc-4_5-branch/gcc/combine.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/combine.c	2011-07-22 17:24:46.000000000 -0700
++++ gcc-4_5-branch/gcc/combine.c	2011-07-22 17:34:41.961747206 -0700
+@@ -392,8 +392,8 @@
+ static void undo_all (void);
+ static void undo_commit (void);
+ static rtx *find_split_point (rtx *, rtx);
+-static rtx subst (rtx, rtx, rtx, int, int);
+-static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
++static rtx subst (rtx, rtx, rtx, int, int, int);
++static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
+ static rtx simplify_if_then_else (rtx);
+ static rtx simplify_set (rtx);
+ static rtx simplify_logical (rtx);
+@@ -2962,12 +2962,12 @@
+ 	  if (i1)
+ 	    {
+ 	      subst_low_luid = DF_INSN_LUID (i1);
+-	      i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
++	      i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	    }
+ 	  else
+ 	    {
+ 	      subst_low_luid = DF_INSN_LUID (i2);
+-	      i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
++	      i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	    }
+ 	}
+ 
+@@ -2978,7 +2978,7 @@
+ 	 to avoid self-referential rtl.  */
+ 
+       subst_low_luid = DF_INSN_LUID (i2);
+-      newpat = subst (PATTERN (i3), i2dest, i2src, 0,
++      newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
+ 		      ! i1_feeds_i3 && i1dest_in_i1src);
+       substed_i2 = 1;
+ 
+@@ -3009,7 +3009,7 @@
+ 
+       n_occurrences = 0;
+       subst_low_luid = DF_INSN_LUID (i1);
+-      newpat = subst (newpat, i1dest, i1src, 0, 0);
++      newpat = subst (newpat, i1dest, i1src, 0, 0, 0);
+       substed_i1 = 1;
+     }
+ 
+@@ -3071,7 +3071,7 @@
+ 	  else
+ 	    /* See comment where i2pat is assigned.  */
+ 	    XVECEXP (newpat, 0, --total_sets)
+-	      = subst (i2pat, i1dest, i1src, 0, 0);
++	      = subst (i2pat, i1dest, i1src, 0, 0, 0);
+ 	}
+     }
+ 
+@@ -4623,11 +4623,13 @@
+ 
+    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
+ 
++   IN_COND is nonzero if we are on top level of the condition.
++
+    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
+    by copying if `n_occurrences' is nonzero.  */
+ 
+ static rtx
+-subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
++subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
+ {
+   enum rtx_code code = GET_CODE (x);
+   enum machine_mode op0_mode = VOIDmode;
+@@ -4688,7 +4690,7 @@
+       && GET_CODE (XVECEXP (x, 0, 0)) == SET
+       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
+     {
+-      new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
++      new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
+ 
+       /* If this substitution failed, this whole thing fails.  */
+       if (GET_CODE (new_rtx) == CLOBBER
+@@ -4705,7 +4707,7 @@
+ 	      && GET_CODE (dest) != CC0
+ 	      && GET_CODE (dest) != PC)
+ 	    {
+-	      new_rtx = subst (dest, from, to, 0, unique_copy);
++	      new_rtx = subst (dest, from, to, 0, 0, unique_copy);
+ 
+ 	      /* If this substitution failed, this whole thing fails.  */
+ 	      if (GET_CODE (new_rtx) == CLOBBER
+@@ -4751,8 +4753,8 @@
+ 		    }
+ 		  else
+ 		    {
+-		      new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
+-				   unique_copy);
++		      new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
++				       unique_copy);
+ 
+ 		      /* If this substitution failed, this whole thing
+ 			 fails.  */
+@@ -4829,7 +4831,9 @@
+ 				&& (code == SUBREG || code == STRICT_LOW_PART
+ 				    || code == ZERO_EXTRACT))
+ 			       || code == SET)
+-			      && i == 0), unique_copy);
++			      && i == 0),
++				 code == IF_THEN_ELSE && i == 0,
++				 unique_copy);
+ 
+ 	      /* If we found that we will have to reject this combination,
+ 		 indicate that by returning the CLOBBER ourselves, rather than
+@@ -4886,7 +4890,7 @@
+       /* If X is sufficiently simple, don't bother trying to do anything
+ 	 with it.  */
+       if (code != CONST_INT && code != REG && code != CLOBBER)
+-	x = combine_simplify_rtx (x, op0_mode, in_dest);
++	x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
+ 
+       if (GET_CODE (x) == code)
+ 	break;
+@@ -4906,10 +4910,12 @@
+    expression.
+ 
+    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
+-   if we are inside a SET_DEST.  */
++   if we are inside a SET_DEST.  IN_COND is nonzero if we are on the top level
++   of a condition.  */
+ 
+ static rtx
+-combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
++combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
++		      int in_cond)
+ {
+   enum rtx_code code = GET_CODE (x);
+   enum machine_mode mode = GET_MODE (x);
+@@ -4964,8 +4970,8 @@
+ 	     false arms to store-flag values.  Be careful to use copy_rtx
+ 	     here since true_rtx or false_rtx might share RTL with x as a
+ 	     result of the if_then_else_cond call above.  */
+-	  true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
+-	  false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
++	  true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
++	  false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
+ 
+ 	  /* If true_rtx and false_rtx are not general_operands, an if_then_else
+ 	     is unlikely to be simpler.  */
+@@ -5309,7 +5315,7 @@
+ 	{
+ 	  /* Try to simplify the expression further.  */
+ 	  rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
+-	  temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
++	  temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
+ 
+ 	  /* If we could, great.  If not, do not go ahead with the IOR
+ 	     replacement, since PLUS appears in many special purpose
+@@ -5402,7 +5408,16 @@
+ 	     ZERO_EXTRACT is indeed appropriate, it will be placed back by
+ 	     the call to make_compound_operation in the SET case.  */
+ 
+-	  if (STORE_FLAG_VALUE == 1
++	  if (in_cond)
++	    /* Don't apply below optimizations if the caller would
++	       prefer a comparison rather than a value.
++	       E.g., for the condition in an IF_THEN_ELSE most targets need
++	       an explicit comparison.  */
++	    {
++	      ;
++	    }
++
++	  else if (STORE_FLAG_VALUE == 1
+ 	      && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
+ 	      && op1 == const0_rtx
+ 	      && mode == GET_MODE (op0)
+@@ -5646,11 +5661,11 @@
+       if (reg_mentioned_p (from, true_rtx))
+ 	true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
+ 				      from, true_val),
+-		      pc_rtx, pc_rtx, 0, 0);
++			  pc_rtx, pc_rtx, 0, 0, 0);
+       if (reg_mentioned_p (from, false_rtx))
+ 	false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
+ 				   from, false_val),
+-		       pc_rtx, pc_rtx, 0, 0);
++			   pc_rtx, pc_rtx, 0, 0, 0);
+ 
+       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
+       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
+@@ -5867,11 +5882,11 @@
+ 	{
+ 	  temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
+ 						 cond_op0, cond_op1),
+-			pc_rtx, pc_rtx, 0, 0);
++			pc_rtx, pc_rtx, 0, 0, 0);
+ 	  temp = simplify_gen_binary (MULT, m, temp,
+ 				      simplify_gen_binary (MULT, m, c1,
+ 							   const_true_rtx));
+-	  temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
++	  temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
+ 	  temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
+ 
+ 	  if (extend_op != UNKNOWN)
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99437.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99437.patch
new file mode 100644
index 0000000000..94d9666084
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99437.patch
@@ -0,0 +1,27 @@
+2010-11-24  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	Launchpad #618684
+
+	Backport from mainline:
+
+	2010-04-10  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* reload1.c (eliminate_regs_in_insn): Don't restore an operand
+	if doing so would replace the entire pattern.
+
+=== modified file 'gcc/reload1.c'
+--- old/gcc/reload1.c	2010-10-04 00:50:43 +0000
++++ new/gcc/reload1.c	2010-11-24 13:40:23 +0000
+@@ -3567,7 +3567,10 @@
+     {
+       /* Restore the old body.  */
+       for (i = 0; i < recog_data.n_operands; i++)
+-	*recog_data.operand_loc[i] = orig_operand[i];
++	/* Restoring a top-level match_parallel would clobber the new_body
++	   we installed in the insn.  */
++	if (recog_data.operand_loc[i] != &PATTERN (insn))
++	  *recog_data.operand_loc[i] = orig_operand[i];
+       for (i = 0; i < recog_data.n_dups; i++)
+ 	*recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
+     }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch
new file mode 100644
index 0000000000..cec7f57d47
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch
@@ -0,0 +1,1500 @@
+2010-11-16  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	2010-07-21  Richard Henderson  <rth@redhat.com>
+
+	gcc/
+	* config/i386/i386.c (setup_incoming_varargs_64): Emit a simple
+	comparison for avoiding xmm register saves.  Emit the xmm register
+	saves explicitly.
+	* config/i386/i386.md (UNSPEC_SSE_PROLOGUE_SAVE): Remove.
+	(UNSPEC_SSE_PROLOGUE_SAVE_LOW): Remove.
+	(sse_prologue_save, sse_prologue_save_insn1, sse_prologue_save_insn):
+	Remove patterns and the associated splitters.
+
+	2010-07-22  Richard Henderson  <rth@redhat.com>
+
+	gcc/
+	PR target/45027
+	* config/i386/i386.c (setup_incoming_varargs_64): Force the use
+	of V4SFmode for the SSE saves; increase stack alignment if needed.
+
+2010-11-16  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Re-merge, backport from mainline:
+
+	2010-07-15  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (last_label_ruid, first_index_reg, last_index_reg):
+	New static variables.
+	(reload_combine_recognize_pattern): New static function, broken out
+	of reload_combine.
+	(reload_combine): Use it.  Only initialize first_index_reg and
+	last_index_reg once.
+
+	2010-07-17  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/42235
+	gcc/
+	* postreload.c (reload_cse_move2add): Return bool, true if anything.
+	changed.  All callers changed.
+	(move2add_use_add2_insn): Likewise.
+	(move2add_use_add3_insn): Likewise.
+	(reload_cse_regs): If reload_cse_move2add changed anything, rerun
+	reload_combine.
+	(RELOAD_COMBINE_MAX_USES): Bump to 16.
+	(last_jump_ruid): New static variable.
+	(struct reg_use): New members CONTAINING_MEM and RUID.
+	(reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID.
+	(reload_combine_split_one_ruid, reload_combine_split_ruids,
+	reload_combine_purge_insn_uses, reload_combine_closest_single_use
+	reload_combine_purge_reg_uses_after_ruid,
+	reload_combine_recognize_const_pattern): New static functions.
+	(reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH
+	is true for our reg and that we have available index regs.
+	(reload_combine_note_use): New args RUID and CONTAINING_MEM.  All
+	callers changed.  Use them to initialize fields in struct reg_use.
+	(reload_combine): Initialize last_jump_ruid.  Be careful when to
+	take PREV_INSN of the scanned insn.  Update REAL_STORE_RUID fields.
+	Call reload_combine_recognize_const_pattern.
+	(reload_combine_note_store): Update REAL_STORE_RUID field.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr42235.c: New test.
+
+	2010-07-19  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (reload_combine_closest_single_use): Ignore the
+	number of uses for DEBUG_INSNs.
+	(fixup_debug_insns): New static function.
+	(reload_combine_recognize_const_pattern): Use it.  Don't let the
+	main loop be affected by DEBUG_INSNs.
+	Really disallow moving adds past a jump insn.
+	(reload_combine_recognize_pattern): Don't update use_ruid here.
+	(reload_combine_note_use): Do it here.
+	(reload_combine): Use control_flow_insn_p rather than JUMP_P.
+
+	2010-07-20  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (fixup_debug_insns): Remove arg REGNO.  New args
+	FROM and TO.  All callers changed.  Don't look for tracked uses,
+	just scan the RTL for DEBUG_INSNs and substitute.
+	(reload_combine_recognize_pattern): Call fixup_debug_insns.
+	(reload_combine): Ignore DEBUG_INSNs.
+
+	2010-07-22  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR bootstrap/44970
+	PR middle-end/45009
+	gcc/
+	* postreload.c: Include "target.h".
+	(reload_combine_closest_single_use): Don't take DEBUG_INSNs
+	into account.
+	(fixup_debug_insns): Don't copy the rtx.
+	(reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses.
+	Don't copy when replacing.  Call fixup_debug_insns in the case where
+	we merged one add with another.
+	(reload_combine_recognize_pattern): Fail if there aren't any uses.
+	Try harder to determine whether we're picking a valid index register.
+	Don't set store_ruid for an insn we're going to scan in the
+	next iteration.
+	(reload_combine): Remove unused code.
+	(reload_combine_note_use): When updating use information for
+	an old insn, ignore a use that occurs after store_ruid.
+	* Makefile.in (postreload.o): Update dependencies.
+
+	2010-07-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (reload_combine_recognize_const_pattern): Move test
+	for limiting the insn movement to the right scope.
+
+	2010-07-27  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* postreload.c (try_replace_in_use): New static function.
+	(reload_combine_recognize_const_pattern): Use it here.  Allow
+	substituting into a final add insn, and substituting into a memory
+	reference in an insn that sets the reg.
+
+=== modified file 'gcc/Makefile.in'
+--- old/gcc/Makefile.in	2010-11-11 11:34:59 +0000
++++ new/gcc/Makefile.in	2010-11-16 18:05:53 +0000
+@@ -3157,7 +3157,7 @@
+    $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \
+    hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \
+    $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \
+-   $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
++   $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
+ postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
+    $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \
+    $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
+
+=== modified file 'gcc/config/i386/i386.c'
+--- old/gcc/config/i386/i386.c	2010-09-30 20:24:54 +0000
++++ new/gcc/config/i386/i386.c	2010-11-16 18:05:53 +0000
+@@ -6737,12 +6737,8 @@
+ setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
+ {
+   rtx save_area, mem;
+-  rtx label;
+-  rtx label_ref;
+-  rtx tmp_reg;
+-  rtx nsse_reg;
+   alias_set_type set;
+-  int i;
++  int i, max;
+ 
+   /* GPR size of varargs save area.  */
+   if (cfun->va_list_gpr_size)
+@@ -6752,7 +6748,7 @@
+ 
+   /* FPR size of varargs save area.  We don't need it if we don't pass
+      anything in SSE registers.  */
+-  if (cum->sse_nregs && cfun->va_list_fpr_size)
++  if (TARGET_SSE && cfun->va_list_fpr_size)
+     ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
+   else
+     ix86_varargs_fpr_size = 0;
+@@ -6763,10 +6759,11 @@
+   save_area = frame_pointer_rtx;
+   set = get_varargs_alias_set ();
+ 
+-  for (i = cum->regno;
+-       i < X86_64_REGPARM_MAX
+-       && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
+-       i++)
++  max = cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
++  if (max > X86_64_REGPARM_MAX)
++    max = X86_64_REGPARM_MAX;
++
++  for (i = cum->regno; i < max; i++)
+     {
+       mem = gen_rtx_MEM (Pmode,
+ 			 plus_constant (save_area, i * UNITS_PER_WORD));
+@@ -6778,62 +6775,42 @@
+ 
+   if (ix86_varargs_fpr_size)
+     {
+-      /* Stack must be aligned to 16byte for FP register save area.  */
+-      if (crtl->stack_alignment_needed < 128)
+-	crtl->stack_alignment_needed = 128;
++      enum machine_mode smode;
++      rtx label, test;
+ 
+       /* Now emit code to save SSE registers.  The AX parameter contains number
+-	 of SSE parameter registers used to call this function.  We use
+-	 sse_prologue_save insn template that produces computed jump across
+-	 SSE saves.  We need some preparation work to get this working.  */
++	 of SSE parameter registers used to call this function, though all we
++	 actually check here is the zero/non-zero status.  */
+ 
+       label = gen_label_rtx ();
+-      label_ref = gen_rtx_LABEL_REF (Pmode, label);
+-
+-      /* Compute address to jump to :
+-         label - eax*4 + nnamed_sse_arguments*4 Or
+-         label - eax*5 + nnamed_sse_arguments*5 for AVX.  */
+-      tmp_reg = gen_reg_rtx (Pmode);
+-      nsse_reg = gen_reg_rtx (Pmode);
+-      emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
+-      emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
+-			      gen_rtx_MULT (Pmode, nsse_reg,
+-					    GEN_INT (4))));
+-
+-      /* vmovaps is one byte longer than movaps.  */
+-      if (TARGET_AVX)
+-	emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
+-				gen_rtx_PLUS (Pmode, tmp_reg,
+-					      nsse_reg)));
+-
+-      if (cum->sse_regno)
+-	emit_move_insn
+-	  (nsse_reg,
+-	   gen_rtx_CONST (DImode,
+-			  gen_rtx_PLUS (DImode,
+-					label_ref,
+-					GEN_INT (cum->sse_regno
+-						 * (TARGET_AVX ? 5 : 4)))));
+-      else
+-	emit_move_insn (nsse_reg, label_ref);
+-      emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
+-
+-      /* Compute address of memory block we save into.  We always use pointer
+-	 pointing 127 bytes after first byte to store - this is needed to keep
+-	 instruction size limited by 4 bytes (5 bytes for AVX) with one
+-	 byte displacement.  */
+-      tmp_reg = gen_reg_rtx (Pmode);
+-      emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
+-			      plus_constant (save_area,
+-					     ix86_varargs_gpr_size + 127)));
+-      mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
+-      MEM_NOTRAP_P (mem) = 1;
+-      set_mem_alias_set (mem, set);
+-      set_mem_align (mem, BITS_PER_WORD);
+-
+-      /* And finally do the dirty job!  */
+-      emit_insn (gen_sse_prologue_save (mem, nsse_reg,
+-					GEN_INT (cum->sse_regno), label));
++      test = gen_rtx_EQ (VOIDmode, gen_rtx_REG (QImode, AX_REG), const0_rtx);
++      emit_jump_insn (gen_cbranchqi4 (test, XEXP (test, 0), XEXP (test, 1),
++				      label));
++
++      /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
++	 we used movdqa (i.e. TImode) instead?  Perhaps even better would
++	 be if we could determine the real mode of the data, via a hook
++	 into pass_stdarg.  Ignore all that for now.  */
++      smode = V4SFmode;
++      if (crtl->stack_alignment_needed < GET_MODE_ALIGNMENT (smode))
++	crtl->stack_alignment_needed = GET_MODE_ALIGNMENT (smode);
++
++      max = cum->sse_regno + cfun->va_list_fpr_size / 16;
++      if (max > X86_64_SSE_REGPARM_MAX)
++	max = X86_64_SSE_REGPARM_MAX;
++
++      for (i = cum->sse_regno; i < max; ++i)
++	{
++	  mem = plus_constant (save_area, i * 16 + ix86_varargs_gpr_size);
++	  mem = gen_rtx_MEM (smode, mem);
++	  MEM_NOTRAP_P (mem) = 1;
++	  set_mem_alias_set (mem, set);
++	  set_mem_align (mem, GET_MODE_ALIGNMENT (smode));
++
++	  emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i)));
++	}
++
++      emit_label (label);
+     }
+ }
+ 
+
+=== modified file 'gcc/config/i386/i386.md'
+--- old/gcc/config/i386/i386.md	2010-10-22 04:56:41 +0000
++++ new/gcc/config/i386/i386.md	2010-11-27 15:24:12 +0000
+@@ -80,7 +80,6 @@
+    ; Prologue support
+    (UNSPEC_STACK_ALLOC		11)
+    (UNSPEC_SET_GOT		12)
+-   (UNSPEC_SSE_PROLOGUE_SAVE	13)
+    (UNSPEC_REG_SAVE		14)
+    (UNSPEC_DEF_CFA		15)
+    (UNSPEC_SET_RIP		16)
+@@ -20252,74 +20251,6 @@
+   { return ASM_SHORT "0x0b0f"; }
+   [(set_attr "length" "2")])
+ 
+-(define_expand "sse_prologue_save"
+-  [(parallel [(set (match_operand:BLK 0 "" "")
+-		   (unspec:BLK [(reg:DI XMM0_REG)
+-				(reg:DI XMM1_REG)
+-				(reg:DI XMM2_REG)
+-				(reg:DI XMM3_REG)
+-				(reg:DI XMM4_REG)
+-				(reg:DI XMM5_REG)
+-				(reg:DI XMM6_REG)
+-				(reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
+-	      (use (match_operand:DI 1 "register_operand" ""))
+-	      (use (match_operand:DI 2 "immediate_operand" ""))
+-	      (use (label_ref:DI (match_operand 3 "" "")))])]
+-  "TARGET_64BIT"
+-  "")
+-
+-(define_insn "*sse_prologue_save_insn"
+-  [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
+-			  (match_operand:DI 4 "const_int_operand" "n")))
+-	(unspec:BLK [(reg:DI XMM0_REG)
+-		     (reg:DI XMM1_REG)
+-		     (reg:DI XMM2_REG)
+-		     (reg:DI XMM3_REG)
+-		     (reg:DI XMM4_REG)
+-		     (reg:DI XMM5_REG)
+-		     (reg:DI XMM6_REG)
+-		     (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
+-   (use (match_operand:DI 1 "register_operand" "r"))
+-   (use (match_operand:DI 2 "const_int_operand" "i"))
+-   (use (label_ref:DI (match_operand 3 "" "X")))]
+-  "TARGET_64BIT
+-   && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128
+-   && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
+-{
+-  int i;
+-  operands[0] = gen_rtx_MEM (Pmode,
+-			     gen_rtx_PLUS (Pmode, operands[0], operands[4]));
+-  /* VEX instruction with a REX prefix will #UD.  */
+-  if (TARGET_AVX && GET_CODE (XEXP (operands[0], 0)) != PLUS)
+-    gcc_unreachable ();
+-
+-  output_asm_insn ("jmp\t%A1", operands);
+-  for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
+-    {
+-      operands[4] = adjust_address (operands[0], DImode, i*16);
+-      operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
+-      PUT_MODE (operands[4], TImode);
+-      if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
+-        output_asm_insn ("rex", operands);
+-      output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands);
+-    }
+-  (*targetm.asm_out.internal_label) (asm_out_file, "L",
+-				     CODE_LABEL_NUMBER (operands[3]));
+-  return "";
+-}
+-  [(set_attr "type" "other")
+-   (set_attr "length_immediate" "0")
+-   (set_attr "length_address" "0")
+-   (set (attr "length")
+-     (if_then_else
+-       (eq (symbol_ref "TARGET_AVX") (const_int 0))
+-       (const_string "34")
+-       (const_string "42")))
+-   (set_attr "memory" "store")
+-   (set_attr "modrm" "0")
+-   (set_attr "prefix" "maybe_vex")
+-   (set_attr "mode" "DI")])
+-
+ (define_expand "prefetch"
+   [(prefetch (match_operand 0 "address_operand" "")
+ 	     (match_operand:SI 1 "const_int_operand" "")
+
+=== modified file 'gcc/postreload.c'
+--- old/gcc/postreload.c	2010-11-08 22:08:43 +0000
++++ new/gcc/postreload.c	2010-11-16 18:05:53 +0000
+@@ -44,6 +44,7 @@
+ #include "toplev.h"
+ #include "except.h"
+ #include "tree.h"
++#include "target.h"
+ #include "timevar.h"
+ #include "tree-pass.h"
+ #include "df.h"
+@@ -56,10 +57,10 @@
+ static int reload_cse_simplify_operands (rtx, rtx);
+ 
+ static void reload_combine (void);
+-static void reload_combine_note_use (rtx *, rtx);
++static void reload_combine_note_use (rtx *, rtx, int, rtx);
+ static void reload_combine_note_store (rtx, const_rtx, void *);
+ 
+-static void reload_cse_move2add (rtx);
++static bool reload_cse_move2add (rtx);
+ static void move2add_note_store (rtx, const_rtx, void *);
+ 
+ /* Call cse / combine like post-reload optimization phases.
+@@ -67,11 +68,16 @@
+ void
+ reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
+ {
++  bool moves_converted;
+   reload_cse_regs_1 (first);
+   reload_combine ();
+-  reload_cse_move2add (first);
++  moves_converted = reload_cse_move2add (first);
+   if (flag_expensive_optimizations)
+-    reload_cse_regs_1 (first);
++    {
++      if (moves_converted)
++	reload_combine ();
++      reload_cse_regs_1 (first);
++    }
+ }
+ 
+ /* See whether a single set SET is a noop.  */
+@@ -660,30 +666,43 @@
+ 
+ /* The maximum number of uses of a register we can keep track of to
+    replace them with reg+reg addressing.  */
+-#define RELOAD_COMBINE_MAX_USES 6
++#define RELOAD_COMBINE_MAX_USES 16
+ 
+-/* INSN is the insn where a register has been used, and USEP points to the
+-   location of the register within the rtl.  */
+-struct reg_use { rtx insn, *usep; };
++/* Describes a recorded use of a register.  */
++struct reg_use
++{
++  /* The insn where a register has been used.  */
++  rtx insn;
++  /* Points to the memory reference enclosing the use, if any, NULL_RTX
++     otherwise.  */
++  rtx containing_mem;
++  /* Location of the register withing INSN.  */
++  rtx *usep;
++  /* The reverse uid of the insn.  */
++  int ruid;
++};
+ 
+ /* If the register is used in some unknown fashion, USE_INDEX is negative.
+    If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
+-   indicates where it becomes live again.
++   indicates where it is first set or clobbered.
+    Otherwise, USE_INDEX is the index of the last encountered use of the
+-   register (which is first among these we have seen since we scan backwards),
+-   OFFSET contains the constant offset that is added to the register in
+-   all encountered uses, and USE_RUID indicates the first encountered, i.e.
+-   last, of these uses.
++   register (which is first among these we have seen since we scan backwards).
++   USE_RUID indicates the first encountered, i.e. last, of these uses.
++   If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
++   with a constant offset; OFFSET contains this constant in that case.
+    STORE_RUID is always meaningful if we only want to use a value in a
+    register in a different place: it denotes the next insn in the insn
+-   stream (i.e. the last encountered) that sets or clobbers the register.  */
++   stream (i.e. the last encountered) that sets or clobbers the register.
++   REAL_STORE_RUID is similar, but clobbers are ignored when updating it.  */
+ static struct
+   {
+     struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
++    rtx offset;
+     int use_index;
+-    rtx offset;
+     int store_ruid;
++    int real_store_ruid;
+     int use_ruid;
++    bool all_offsets_match;
+   } reg_state[FIRST_PSEUDO_REGISTER];
+ 
+ /* Reverse linear uid.  This is increased in reload_combine while scanning
+@@ -691,42 +710,548 @@
+    and the store_ruid / use_ruid fields in reg_state.  */
+ static int reload_combine_ruid;
+ 
++/* The RUID of the last label we encountered in reload_combine.  */
++static int last_label_ruid;
++
++/* The RUID of the last jump we encountered in reload_combine.  */
++static int last_jump_ruid;
++
++/* The register numbers of the first and last index register.  A value of
++   -1 in LAST_INDEX_REG indicates that we've previously computed these
++   values and found no suitable index registers.  */
++static int first_index_reg = -1;
++static int last_index_reg;
++
+ #define LABEL_LIVE(LABEL) \
+   (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
+ 
++/* Subroutine of reload_combine_split_ruids, called to fix up a single
++   ruid pointed to by *PRUID if it is higher than SPLIT_RUID.  */
++
++static inline void
++reload_combine_split_one_ruid (int *pruid, int split_ruid)
++{
++  if (*pruid > split_ruid)
++    (*pruid)++;
++}
++
++/* Called when we insert a new insn in a position we've already passed in
++   the scan.  Examine all our state, increasing all ruids that are higher
++   than SPLIT_RUID by one in order to make room for a new insn.  */
++
++static void
++reload_combine_split_ruids (int split_ruid)
++{
++  unsigned i;
++
++  reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
++  reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
++  reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
++
++  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
++    {
++      int j, idx = reg_state[i].use_index;
++      reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
++      reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
++      reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
++				     split_ruid);
++      if (idx < 0)
++	continue;
++      for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
++	{
++	  reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
++					 split_ruid);
++	}
++    }
++}
++
++/* Called when we are about to rescan a previously encountered insn with
++   reload_combine_note_use after modifying some part of it.  This clears all
++   information about uses in that particular insn.  */
++
++static void
++reload_combine_purge_insn_uses (rtx insn)
++{
++  unsigned i;
++
++  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
++    {
++      int j, k, idx = reg_state[i].use_index;
++      if (idx < 0)
++	continue;
++      j = k = RELOAD_COMBINE_MAX_USES;
++      while (j-- > idx)
++	{
++	  if (reg_state[i].reg_use[j].insn != insn)
++	    {
++	      k--;
++	      if (k != j)
++		reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
++	    }
++	}
++      reg_state[i].use_index = k;
++    }
++}
++
++/* Called when we need to forget about all uses of REGNO after an insn
++   which is identified by RUID.  */
++
++static void
++reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
++{
++  int j, k, idx = reg_state[regno].use_index;
++  if (idx < 0)
++    return;
++  j = k = RELOAD_COMBINE_MAX_USES;
++  while (j-- > idx)
++    {
++      if (reg_state[regno].reg_use[j].ruid >= ruid)
++	{
++	  k--;
++	  if (k != j)
++	    reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
++	}
++    }
++  reg_state[regno].use_index = k;
++}
++
++/* Find the use of REGNO with the ruid that is highest among those
++   lower than RUID_LIMIT, and return it if it is the only use of this
++   reg in the insn.  Return NULL otherwise.  */
++
++static struct reg_use *
++reload_combine_closest_single_use (unsigned regno, int ruid_limit)
++{
++  int i, best_ruid = 0;
++  int use_idx = reg_state[regno].use_index;
++  struct reg_use *retval;
++
++  if (use_idx < 0)
++    return NULL;
++  retval = NULL;
++  for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
++    {
++      struct reg_use *use = reg_state[regno].reg_use + i; 
++      int this_ruid = use->ruid;
++      if (this_ruid >= ruid_limit)
++	continue;
++      if (this_ruid > best_ruid)
++	{
++	  best_ruid = this_ruid;
++	  retval = use;
++	}
++      else if (this_ruid == best_ruid)
++	retval = NULL;
++    }
++  if (last_label_ruid >= best_ruid)
++    return NULL;
++  return retval;
++}
++
++/* After we've moved an add insn, fix up any debug insns that occur
++   between the old location of the add and the new location.  REG is
++   the destination register of the add insn; REPLACEMENT is the
++   SET_SRC of the add.  FROM and TO specify the range in which we
++   should make this change on debug insns.  */
++
++static void
++fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
++{
++  rtx insn;
++  for (insn = from; insn != to; insn = NEXT_INSN (insn))
++    {
++      rtx t;
++
++      if (!DEBUG_INSN_P (insn))
++	continue;
++      
++      t = INSN_VAR_LOCATION_LOC (insn);
++      t = simplify_replace_rtx (t, reg, replacement);
++      validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
++    }
++}
++
++/* Subroutine of reload_combine_recognize_const_pattern.  Try to replace REG
++   with SRC in the insn described by USE, taking costs into account.  Return
++   true if we made the replacement.  */
++
++static bool
++try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
++{
++  rtx use_insn = use->insn;
++  rtx mem = use->containing_mem;
++  bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
++
++  if (mem != NULL_RTX)
++    {
++      addr_space_t as = MEM_ADDR_SPACE (mem);
++      rtx oldaddr = XEXP (mem, 0);
++      rtx newaddr = NULL_RTX;
++      int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
++      int new_cost;
++
++      newaddr = simplify_replace_rtx (oldaddr, reg, src);
++      if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
++	{
++	  XEXP (mem, 0) = newaddr;
++	  new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
++	  XEXP (mem, 0) = oldaddr;
++	  if (new_cost <= old_cost
++	      && validate_change (use_insn,
++				  &XEXP (mem, 0), newaddr, 0))
++	    return true;
++	}
++    }
++  else
++    {
++      rtx new_set = single_set (use_insn);
++      if (new_set
++	  && REG_P (SET_DEST (new_set))
++	  && GET_CODE (SET_SRC (new_set)) == PLUS
++	  && REG_P (XEXP (SET_SRC (new_set), 0))
++	  && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
++	{
++	  rtx new_src;
++	  int old_cost = rtx_cost (SET_SRC (new_set), SET, speed);
++
++	  gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
++	  new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
++
++	  if (rtx_cost (new_src, SET, speed) <= old_cost
++	      && validate_change (use_insn, &SET_SRC (new_set),
++				  new_src, 0))
++	    return true;
++	}
++    }
++  return false;
++}
++
++/* Called by reload_combine when scanning INSN.  This function tries to detect
++   patterns where a constant is added to a register, and the result is used
++   in an address.
++   Return true if no further processing is needed on INSN; false if it wasn't
++   recognized and should be handled normally.  */
++
++static bool
++reload_combine_recognize_const_pattern (rtx insn)
++{
++  int from_ruid = reload_combine_ruid;
++  rtx set, pat, reg, src, addreg;
++  unsigned int regno;
++  struct reg_use *use;
++  bool must_move_add;
++  rtx add_moved_after_insn = NULL_RTX;
++  int add_moved_after_ruid = 0;
++  int clobbered_regno = -1;
++
++  set = single_set (insn);
++  if (set == NULL_RTX)
++    return false;
++
++  reg = SET_DEST (set);
++  src = SET_SRC (set);
++  if (!REG_P (reg)
++      || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
++      || GET_MODE (reg) != Pmode
++      || reg == stack_pointer_rtx)
++    return false;
++
++  regno = REGNO (reg);
++
++  /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
++     uses of REG1 inside an address, or inside another add insn.  If
++     possible and profitable, merge the addition into subsequent
++     uses.  */
++  if (GET_CODE (src) != PLUS
++      || !REG_P (XEXP (src, 0))
++      || !CONSTANT_P (XEXP (src, 1)))
++    return false;
++
++  addreg = XEXP (src, 0);
++  must_move_add = rtx_equal_p (reg, addreg);
++
++  pat = PATTERN (insn);
++  if (must_move_add && set != pat)
++    {
++      /* We have to be careful when moving the add; apart from the
++	 single_set there may also be clobbers.  Recognize one special
++	 case, that of one clobber alongside the set (likely a clobber
++	 of the CC register).  */
++      gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
++      if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
++	  || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
++	  || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
++	return false;
++      clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
++    }
++
++  do
++    {
++      use = reload_combine_closest_single_use (regno, from_ruid);
++
++      if (use)
++	/* Start the search for the next use from here.  */
++	from_ruid = use->ruid;
++
++      if (use && GET_MODE (*use->usep) == Pmode)
++	{
++	  bool delete_add = false;
++	  rtx use_insn = use->insn;
++	  int use_ruid = use->ruid;
++
++	  /* Avoid moving the add insn past a jump.  */
++	  if (must_move_add && use_ruid <= last_jump_ruid)
++	    break;
++
++	  /* If the add clobbers another hard reg in parallel, don't move
++	     it past a real set of this hard reg.  */
++	  if (must_move_add && clobbered_regno >= 0
++	      && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
++	    break;
++
++	  gcc_assert (reg_state[regno].store_ruid <= use_ruid);
++	  /* Avoid moving a use of ADDREG past a point where it is stored.  */
++	  if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
++	    break;
++
++	  /* We also must not move the addition past an insn that sets
++	     the same register, unless we can combine two add insns.  */
++	  if (must_move_add && reg_state[regno].store_ruid == use_ruid)
++	    {
++	      if (use->containing_mem == NULL_RTX)
++		delete_add = true;
++	      else
++		break;
++	    }
++
++	  if (try_replace_in_use (use, reg, src))
++	    {
++	      reload_combine_purge_insn_uses (use_insn);
++	      reload_combine_note_use (&PATTERN (use_insn), use_insn,
++				       use_ruid, NULL_RTX);
++
++	      if (delete_add)
++		{
++		  fixup_debug_insns (reg, src, insn, use_insn);
++		  delete_insn (insn);
++		  return true;
++		}
++	      if (must_move_add)
++		{
++		  add_moved_after_insn = use_insn;
++		  add_moved_after_ruid = use_ruid;
++		}
++	      continue;
++	    }
++	}
++      /* If we get here, we couldn't handle this use.  */
++      if (must_move_add)
++	break;
++    }
++  while (use);
++
++  if (!must_move_add || add_moved_after_insn == NULL_RTX)
++    /* Process the add normally.  */
++    return false;
++
++  fixup_debug_insns (reg, src, insn, add_moved_after_insn);
++
++  reorder_insns (insn, insn, add_moved_after_insn);
++  reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
++  reload_combine_split_ruids (add_moved_after_ruid - 1);
++  reload_combine_note_use (&PATTERN (insn), insn,
++			   add_moved_after_ruid, NULL_RTX);
++  reg_state[regno].store_ruid = add_moved_after_ruid;
++
++  return true;
++}
++
++/* Called by reload_combine when scanning INSN.  Try to detect a pattern we
++   can handle and improve.  Return true if no further processing is needed on
++   INSN; false if it wasn't recognized and should be handled normally.  */
++
++static bool
++reload_combine_recognize_pattern (rtx insn)
++{
++  rtx set, reg, src;
++  unsigned int regno;
++
++  set = single_set (insn);
++  if (set == NULL_RTX)
++    return false;
++
++  reg = SET_DEST (set);
++  src = SET_SRC (set);
++  if (!REG_P (reg)
++      || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
++    return false;
++
++  regno = REGNO (reg);
++
++  /* Look for (set (REGX) (CONST_INT))
++     (set (REGX) (PLUS (REGX) (REGY)))
++     ...
++     ... (MEM (REGX)) ...
++     and convert it to
++     (set (REGZ) (CONST_INT))
++     ...
++     ... (MEM (PLUS (REGZ) (REGY)))... .
++
++     First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
++     and that we know all uses of REGX before it dies.
++     Also, explicitly check that REGX != REGY; our life information
++     does not yet show whether REGY changes in this insn.  */
++
++  if (GET_CODE (src) == PLUS
++      && reg_state[regno].all_offsets_match
++      && last_index_reg != -1
++      && REG_P (XEXP (src, 1))
++      && rtx_equal_p (XEXP (src, 0), reg)
++      && !rtx_equal_p (XEXP (src, 1), reg)
++      && reg_state[regno].use_index >= 0
++      && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
++      && last_label_ruid < reg_state[regno].use_ruid)
++    {
++      rtx base = XEXP (src, 1);
++      rtx prev = prev_nonnote_insn (insn);
++      rtx prev_set = prev ? single_set (prev) : NULL_RTX;
++      rtx index_reg = NULL_RTX;
++      rtx reg_sum = NULL_RTX;
++      int i;
++
++      /* Now we need to set INDEX_REG to an index register (denoted as
++	 REGZ in the illustration above) and REG_SUM to the expression
++	 register+register that we want to use to substitute uses of REG
++	 (typically in MEMs) with.  First check REG and BASE for being
++	 index registers; we can use them even if they are not dead.  */
++      if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
++	  || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
++				REGNO (base)))
++	{
++	  index_reg = reg;
++	  reg_sum = src;
++	}
++      else
++	{
++	  /* Otherwise, look for a free index register.  Since we have
++	     checked above that neither REG nor BASE are index registers,
++	     if we find anything at all, it will be different from these
++	     two registers.  */
++	  for (i = first_index_reg; i <= last_index_reg; i++)
++	    {
++	      if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
++		  && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
++		  && reg_state[i].store_ruid <= reg_state[regno].use_ruid
++		  && (call_used_regs[i] || df_regs_ever_live_p (i))
++		  && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
++		  && !fixed_regs[i] && !global_regs[i]
++		  && hard_regno_nregs[i][GET_MODE (reg)] == 1
++		  && targetm.hard_regno_scratch_ok (i))
++		{
++		  index_reg = gen_rtx_REG (GET_MODE (reg), i);
++		  reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
++		  break;
++		}
++	    }
++	}
++
++      /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
++	 (REGY), i.e. BASE, is not clobbered before the last use we'll
++	 create.  */
++      if (reg_sum
++	  && prev_set
++	  && CONST_INT_P (SET_SRC (prev_set))
++	  && rtx_equal_p (SET_DEST (prev_set), reg)
++	  && (reg_state[REGNO (base)].store_ruid
++	      <= reg_state[regno].use_ruid))
++	{
++	  /* Change destination register and, if necessary, the constant
++	     value in PREV, the constant loading instruction.  */
++	  validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
++	  if (reg_state[regno].offset != const0_rtx)
++	    validate_change (prev,
++			     &SET_SRC (prev_set),
++			     GEN_INT (INTVAL (SET_SRC (prev_set))
++				      + INTVAL (reg_state[regno].offset)),
++			     1);
++
++	  /* Now for every use of REG that we have recorded, replace REG
++	     with REG_SUM.  */
++	  for (i = reg_state[regno].use_index;
++	       i < RELOAD_COMBINE_MAX_USES; i++)
++	    validate_unshare_change (reg_state[regno].reg_use[i].insn,
++				     reg_state[regno].reg_use[i].usep,
++				     /* Each change must have its own
++					replacement.  */
++				     reg_sum, 1);
++
++	  if (apply_change_group ())
++	    {
++	      struct reg_use *lowest_ruid = NULL;
++
++	      /* For every new use of REG_SUM, we have to record the use
++		 of BASE therein, i.e. operand 1.  */
++	      for (i = reg_state[regno].use_index;
++		   i < RELOAD_COMBINE_MAX_USES; i++)
++		{
++		  struct reg_use *use = reg_state[regno].reg_use + i;
++		  reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
++					   use->ruid, use->containing_mem);
++		  if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
++		    lowest_ruid = use;
++		}
++
++	      fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
++
++	      /* Delete the reg-reg addition.  */
++	      delete_insn (insn);
++
++	      if (reg_state[regno].offset != const0_rtx)
++		/* Previous REG_EQUIV / REG_EQUAL notes for PREV
++		   are now invalid.  */
++		remove_reg_equal_equiv_notes (prev);
++
++	      reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
++	      return true;
++	    }
++	}
++    }
++  return false;
++}
++
+ static void
+ reload_combine (void)
+ {
+-  rtx insn, set;
+-  int first_index_reg = -1;
+-  int last_index_reg = 0;
++  rtx insn, prev;
+   int i;
+   basic_block bb;
+   unsigned int r;
+-  int last_label_ruid;
+   int min_labelno, n_labels;
+   HARD_REG_SET ever_live_at_start, *label_live;
+ 
+-  /* If reg+reg can be used in offsetable memory addresses, the main chunk of
+-     reload has already used it where appropriate, so there is no use in
+-     trying to generate it now.  */
+-  if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
+-    return;
+-
+   /* To avoid wasting too much time later searching for an index register,
+      determine the minimum and maximum index register numbers.  */
+-  for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+-    if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
+-      {
+-	if (first_index_reg == -1)
+-	  first_index_reg = r;
+-
+-	last_index_reg = r;
+-      }
+-
+-  /* If no index register is available, we can quit now.  */
+-  if (first_index_reg == -1)
+-    return;
++  if (INDEX_REG_CLASS == NO_REGS)
++    last_index_reg = -1;
++  else if (first_index_reg == -1 && last_index_reg == 0)
++    {
++      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
++	if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
++	  {
++	    if (first_index_reg == -1)
++	      first_index_reg = r;
++
++	    last_index_reg = r;
++	  }
++
++      /* If no index register is available, we can quit now.  Set LAST_INDEX_REG
++	 to -1 so we'll know to quit early the next time we get here.  */
++      if (first_index_reg == -1)
++	{
++	  last_index_reg = -1;
++	  return;
++	}
++    }
+ 
+   /* Set up LABEL_LIVE and EVER_LIVE_AT_START.  The register lifetime
+      information is a bit fuzzy immediately after reload, but it's
+@@ -753,20 +1278,23 @@
+     }
+ 
+   /* Initialize last_label_ruid, reload_combine_ruid and reg_state.  */
+-  last_label_ruid = reload_combine_ruid = 0;
++  last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
+   for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+     {
+-      reg_state[r].store_ruid = reload_combine_ruid;
++      reg_state[r].store_ruid = 0;
++      reg_state[r].real_store_ruid = 0;
+       if (fixed_regs[r])
+ 	reg_state[r].use_index = -1;
+       else
+ 	reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+     }
+ 
+-  for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
++  for (insn = get_last_insn (); insn; insn = prev)
+     {
+       rtx note;
+ 
++      prev = PREV_INSN (insn);
++
+       /* We cannot do our optimization across labels.  Invalidating all the use
+ 	 information we have would be costly, so we just note where the label
+ 	 is and then later disable any optimization that would cross it.  */
+@@ -777,141 +1305,17 @@
+ 	  if (! fixed_regs[r])
+ 	      reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
+ 
+-      if (! INSN_P (insn))
++      if (! NONDEBUG_INSN_P (insn))
+ 	continue;
+ 
+       reload_combine_ruid++;
+ 
+-      /* Look for (set (REGX) (CONST_INT))
+-	 (set (REGX) (PLUS (REGX) (REGY)))
+-	 ...
+-	 ... (MEM (REGX)) ...
+-	 and convert it to
+-	 (set (REGZ) (CONST_INT))
+-	 ...
+-	 ... (MEM (PLUS (REGZ) (REGY)))... .
+-
+-	 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
+-	 and that we know all uses of REGX before it dies.
+-	 Also, explicitly check that REGX != REGY; our life information
+-	 does not yet show whether REGY changes in this insn.  */
+-      set = single_set (insn);
+-      if (set != NULL_RTX
+-	  && REG_P (SET_DEST (set))
+-	  && (hard_regno_nregs[REGNO (SET_DEST (set))]
+-			      [GET_MODE (SET_DEST (set))]
+-	      == 1)
+-	  && GET_CODE (SET_SRC (set)) == PLUS
+-	  && REG_P (XEXP (SET_SRC (set), 1))
+-	  && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
+-	  && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set))
+-	  && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
+-	{
+-	  rtx reg = SET_DEST (set);
+-	  rtx plus = SET_SRC (set);
+-	  rtx base = XEXP (plus, 1);
+-	  rtx prev = prev_nonnote_nondebug_insn (insn);
+-	  rtx prev_set = prev ? single_set (prev) : NULL_RTX;
+-	  unsigned int regno = REGNO (reg);
+-	  rtx index_reg = NULL_RTX;
+-	  rtx reg_sum = NULL_RTX;
+-
+-	  /* Now we need to set INDEX_REG to an index register (denoted as
+-	     REGZ in the illustration above) and REG_SUM to the expression
+-	     register+register that we want to use to substitute uses of REG
+-	     (typically in MEMs) with.  First check REG and BASE for being
+-	     index registers; we can use them even if they are not dead.  */
+-	  if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
+-	      || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
+-				    REGNO (base)))
+-	    {
+-	      index_reg = reg;
+-	      reg_sum = plus;
+-	    }
+-	  else
+-	    {
+-	      /* Otherwise, look for a free index register.  Since we have
+-		 checked above that neither REG nor BASE are index registers,
+-		 if we find anything at all, it will be different from these
+-		 two registers.  */
+-	      for (i = first_index_reg; i <= last_index_reg; i++)
+-		{
+-		  if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
+-					 i)
+-		      && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
+-		      && reg_state[i].store_ruid <= reg_state[regno].use_ruid
+-		      && hard_regno_nregs[i][GET_MODE (reg)] == 1)
+-		    {
+-		      index_reg = gen_rtx_REG (GET_MODE (reg), i);
+-		      reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
+-		      break;
+-		    }
+-		}
+-	    }
+-
+-	  /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
+-	     (REGY), i.e. BASE, is not clobbered before the last use we'll
+-	     create.  */
+-	  if (reg_sum
+-	      && prev_set
+-	      && CONST_INT_P (SET_SRC (prev_set))
+-	      && rtx_equal_p (SET_DEST (prev_set), reg)
+-	      && reg_state[regno].use_index >= 0
+-	      && (reg_state[REGNO (base)].store_ruid
+-		  <= reg_state[regno].use_ruid))
+-	    {
+-	      int i;
+-
+-	      /* Change destination register and, if necessary, the constant
+-		 value in PREV, the constant loading instruction.  */
+-	      validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
+-	      if (reg_state[regno].offset != const0_rtx)
+-		validate_change (prev,
+-				 &SET_SRC (prev_set),
+-				 GEN_INT (INTVAL (SET_SRC (prev_set))
+-					  + INTVAL (reg_state[regno].offset)),
+-				 1);
+-
+-	      /* Now for every use of REG that we have recorded, replace REG
+-		 with REG_SUM.  */
+-	      for (i = reg_state[regno].use_index;
+-		   i < RELOAD_COMBINE_MAX_USES; i++)
+-		validate_unshare_change (reg_state[regno].reg_use[i].insn,
+-				 	 reg_state[regno].reg_use[i].usep,
+-				 	 /* Each change must have its own
+-				    	    replacement.  */
+-				 	 reg_sum, 1);
+-
+-	      if (apply_change_group ())
+-		{
+-		  /* For every new use of REG_SUM, we have to record the use
+-		     of BASE therein, i.e. operand 1.  */
+-		  for (i = reg_state[regno].use_index;
+-		       i < RELOAD_COMBINE_MAX_USES; i++)
+-		    reload_combine_note_use
+-		      (&XEXP (*reg_state[regno].reg_use[i].usep, 1),
+-		       reg_state[regno].reg_use[i].insn);
+-
+-		  if (reg_state[REGNO (base)].use_ruid
+-		      > reg_state[regno].use_ruid)
+-		    reg_state[REGNO (base)].use_ruid
+-		      = reg_state[regno].use_ruid;
+-
+-		  /* Delete the reg-reg addition.  */
+-		  delete_insn (insn);
+-
+-		  if (reg_state[regno].offset != const0_rtx)
+-		    /* Previous REG_EQUIV / REG_EQUAL notes for PREV
+-		       are now invalid.  */
+-		    remove_reg_equal_equiv_notes (prev);
+-
+-		  reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
+-		  reg_state[REGNO (index_reg)].store_ruid
+-		    = reload_combine_ruid;
+-		  continue;
+-		}
+-	    }
+-	}
++      if (control_flow_insn_p (insn))
++	last_jump_ruid = reload_combine_ruid;
++
++      if (reload_combine_recognize_const_pattern (insn)
++	  || reload_combine_recognize_pattern (insn))
++	continue;
+ 
+       note_stores (PATTERN (insn), reload_combine_note_store, NULL);
+ 
+@@ -967,7 +1371,8 @@
+ 	      reg_state[i].use_index = -1;
+ 	}
+ 
+-      reload_combine_note_use (&PATTERN (insn), insn);
++      reload_combine_note_use (&PATTERN (insn), insn,
++			       reload_combine_ruid, NULL_RTX);
+       for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+ 	{
+ 	  if (REG_NOTE_KIND (note) == REG_INC
+@@ -976,6 +1381,7 @@
+ 	      int regno = REGNO (XEXP (note, 0));
+ 
+ 	      reg_state[regno].store_ruid = reload_combine_ruid;
++	      reg_state[regno].real_store_ruid = reload_combine_ruid;
+ 	      reg_state[regno].use_index = -1;
+ 	    }
+ 	}
+@@ -985,8 +1391,8 @@
+ }
+ 
+ /* Check if DST is a register or a subreg of a register; if it is,
+-   update reg_state[regno].store_ruid and reg_state[regno].use_index
+-   accordingly.  Called via note_stores from reload_combine.  */
++   update store_ruid, real_store_ruid and use_index in the reg_state
++   structure accordingly.  Called via note_stores from reload_combine.  */
+ 
+ static void
+ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
+@@ -1010,14 +1416,14 @@
+   /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
+      careful with registers / register parts that are not full words.
+      Similarly for ZERO_EXTRACT.  */
+-  if (GET_CODE (set) != SET
+-      || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
++  if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
+       || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
+     {
+       for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
+ 	{
+ 	  reg_state[i].use_index = -1;
+ 	  reg_state[i].store_ruid = reload_combine_ruid;
++	  reg_state[i].real_store_ruid = reload_combine_ruid;
+ 	}
+     }
+   else
+@@ -1025,6 +1431,8 @@
+       for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
+ 	{
+ 	  reg_state[i].store_ruid = reload_combine_ruid;
++	  if (GET_CODE (set) == SET)
++	    reg_state[i].real_store_ruid = reload_combine_ruid;
+ 	  reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
+ 	}
+     }
+@@ -1035,7 +1443,7 @@
+    *XP is the pattern of INSN, or a part of it.
+    Called from reload_combine, and recursively by itself.  */
+ static void
+-reload_combine_note_use (rtx *xp, rtx insn)
++reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
+ {
+   rtx x = *xp;
+   enum rtx_code code = x->code;
+@@ -1048,7 +1456,7 @@
+     case SET:
+       if (REG_P (SET_DEST (x)))
+ 	{
+-	  reload_combine_note_use (&SET_SRC (x), insn);
++	  reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
+ 	  return;
+ 	}
+       break;
+@@ -1104,6 +1512,11 @@
+ 	    return;
+ 	  }
+ 
++	/* We may be called to update uses in previously seen insns.
++	   Don't add uses beyond the last store we saw.  */
++	if (ruid < reg_state[regno].store_ruid)
++	  return;
++
+ 	/* If this register is already used in some unknown fashion, we
+ 	   can't do anything.
+ 	   If we decrement the index from zero to -1, we can't store more
+@@ -1112,29 +1525,34 @@
+ 	if (use_index < 0)
+ 	  return;
+ 
+-	if (use_index != RELOAD_COMBINE_MAX_USES - 1)
+-	  {
+-	    /* We have found another use for a register that is already
+-	       used later.  Check if the offsets match; if not, mark the
+-	       register as used in an unknown fashion.  */
+-	    if (! rtx_equal_p (offset, reg_state[regno].offset))
+-	      {
+-		reg_state[regno].use_index = -1;
+-		return;
+-	      }
+-	  }
+-	else
++	if (use_index == RELOAD_COMBINE_MAX_USES - 1)
+ 	  {
+ 	    /* This is the first use of this register we have seen since we
+ 	       marked it as dead.  */
+ 	    reg_state[regno].offset = offset;
+-	    reg_state[regno].use_ruid = reload_combine_ruid;
+-	  }
++	    reg_state[regno].all_offsets_match = true;
++	    reg_state[regno].use_ruid = ruid;
++	  }
++	else
++	  {
++	    if (reg_state[regno].use_ruid > ruid)
++	      reg_state[regno].use_ruid = ruid;
++
++	    if (! rtx_equal_p (offset, reg_state[regno].offset))
++	      reg_state[regno].all_offsets_match = false;
++	  }
++
+ 	reg_state[regno].reg_use[use_index].insn = insn;
++	reg_state[regno].reg_use[use_index].ruid = ruid;
++	reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
+ 	reg_state[regno].reg_use[use_index].usep = xp;
+ 	return;
+       }
+ 
++    case MEM:
++      containing_mem = x;
++      break;
++
+     default:
+       break;
+     }
+@@ -1144,11 +1562,12 @@
+   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+     {
+       if (fmt[i] == 'e')
+-	reload_combine_note_use (&XEXP (x, i), insn);
++	reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
+       else if (fmt[i] == 'E')
+ 	{
+ 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+-	    reload_combine_note_use (&XVECEXP (x, i, j), insn);
++	    reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
++				     containing_mem);
+ 	}
+     }
+ }
+@@ -1196,9 +1615,10 @@
+    while REG is known to already have value (SYM + offset).
+    This function tries to change INSN into an add instruction
+    (set (REG) (plus (REG) (OFF - offset))) using the known value.
+-   It also updates the information about REG's known value.  */
++   It also updates the information about REG's known value.
++   Return true if we made a change.  */
+ 
+-static void
++static bool
+ move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
+ {
+   rtx pat = PATTERN (insn);
+@@ -1207,6 +1627,7 @@
+   rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
+ 			      GET_MODE (reg));
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
++  bool changed = false;
+ 
+   /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
+      use (set (reg) (reg)) instead.
+@@ -1221,13 +1642,13 @@
+ 	 (reg)), would be discarded.  Maybe we should
+ 	 try a truncMN pattern?  */
+       if (INTVAL (off) == reg_offset [regno])
+-	validate_change (insn, &SET_SRC (pat), reg, 0);
++	changed = validate_change (insn, &SET_SRC (pat), reg, 0);
+     }
+   else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
+ 	   && have_add2_insn (reg, new_src))
+     {
+       rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
+-      validate_change (insn, &SET_SRC (pat), tem, 0);
++      changed = validate_change (insn, &SET_SRC (pat), tem, 0);
+     }
+   else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
+     {
+@@ -1252,8 +1673,9 @@
+ 			     gen_rtx_STRICT_LOW_PART (VOIDmode,
+ 						      narrow_reg),
+ 			     narrow_src);
+-	      if (validate_change (insn, &PATTERN (insn),
+-				   new_set, 0))
++	      changed = validate_change (insn, &PATTERN (insn),
++					 new_set, 0);
++	      if (changed)
+ 		break;
+ 	    }
+ 	}
+@@ -1263,6 +1685,7 @@
+   reg_mode[regno] = GET_MODE (reg);
+   reg_symbol_ref[regno] = sym;
+   reg_offset[regno] = INTVAL (off);
++  return changed;
+ }
+ 
+ 
+@@ -1272,9 +1695,10 @@
+    value (SYM + offset) and change INSN into an add instruction
+    (set (REG) (plus (the found register) (OFF - offset))) if such
+    a register is found.  It also updates the information about
+-   REG's known value.  */
++   REG's known value.
++   Return true iff we made a change.  */
+ 
+-static void
++static bool
+ move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
+ {
+   rtx pat = PATTERN (insn);
+@@ -1284,6 +1708,7 @@
+   int min_regno;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int i;
++  bool changed = false;
+ 
+   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+     if (reg_set_luid[i] > move2add_last_label_luid
+@@ -1328,20 +1753,25 @@
+ 				      GET_MODE (reg));
+ 	  tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
+ 	}
+-      validate_change (insn, &SET_SRC (pat), tem, 0);
++      if (validate_change (insn, &SET_SRC (pat), tem, 0))
++	changed = true;
+     }
+   reg_set_luid[regno] = move2add_luid;
+   reg_base_reg[regno] = -1;
+   reg_mode[regno] = GET_MODE (reg);
+   reg_symbol_ref[regno] = sym;
+   reg_offset[regno] = INTVAL (off);
++  return changed;
+ }
+ 
+-static void
++/* Convert move insns with constant inputs to additions if they are cheaper.
++   Return true if any changes were made.  */
++static bool
+ reload_cse_move2add (rtx first)
+ {
+   int i;
+   rtx insn;
++  bool changed = false;
+ 
+   for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
+     {
+@@ -1402,7 +1832,7 @@
+ 		  && reg_base_reg[regno] < 0
+ 		  && reg_symbol_ref[regno] == NULL_RTX)
+ 		{
+-		  move2add_use_add2_insn (reg, NULL_RTX, src, insn);
++		  changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
+ 		  continue;
+ 		}
+ 
+@@ -1463,6 +1893,7 @@
+ 			}
+ 		      if (success)
+ 			delete_insn (insn);
++		      changed |= success;
+ 		      insn = next;
+ 		      reg_mode[regno] = GET_MODE (reg);
+ 		      reg_offset[regno] =
+@@ -1508,12 +1939,12 @@
+ 		  && reg_base_reg[regno] < 0
+ 		  && reg_symbol_ref[regno] != NULL_RTX
+ 		  && rtx_equal_p (sym, reg_symbol_ref[regno]))
+-		move2add_use_add2_insn (reg, sym, off, insn);
++		changed |= move2add_use_add2_insn (reg, sym, off, insn);
+ 
+ 	      /* Otherwise, we have to find a register whose value is sum
+ 		 of sym and some constant value.  */
+ 	      else
+-		move2add_use_add3_insn (reg, sym, off, insn);
++		changed |= move2add_use_add3_insn (reg, sym, off, insn);
+ 
+ 	      continue;
+ 	    }
+@@ -1568,6 +1999,7 @@
+ 	    }
+ 	}
+     }
++  return changed;
+ }
+ 
+ /* SET is a SET or CLOBBER that sets DST.  DATA is the insn which
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99440.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99440.patch
new file mode 100644
index 0000000000..b7a28de658
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99440.patch
@@ -0,0 +1,78 @@
+2010-11-24  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	2010-07-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	PR bootstrap/44768
+
+	* cfgexpand.c (estimated_stack_frame_size): Make self-contained
+	with respect to current_function_decl. Pass decl of the function.
+	* tree-inline.h (estimated_stack_frame_size): Adjust prototype.
+	* ipa-inline.c (compute_inline_parameters): Pass decl to
+	estimated_stack_frame_size.
+
+=== modified file 'gcc/cfgexpand.c'
+--- old/gcc/cfgexpand.c	2010-10-04 00:50:43 +0000
++++ new/gcc/cfgexpand.c	2010-11-24 08:43:48 +0000
+@@ -1248,8 +1248,8 @@
+   stack_vars_alloc = stack_vars_num = 0;
+ }
+ 
+-/* Make a fair guess for the size of the stack frame of the current
+-   function.  This doesn't have to be exact, the result is only used
++/* Make a fair guess for the size of the stack frame of the decl
++   passed.  This doesn't have to be exact, the result is only used
+    in the inline heuristics.  So we don't want to run the full stack
+    var packing algorithm (which is quadratic in the number of stack
+    vars).  Instead, we calculate the total size of all stack vars.
+@@ -1257,11 +1257,14 @@
+    vars doesn't happen very often.  */
+ 
+ HOST_WIDE_INT
+-estimated_stack_frame_size (void)
++estimated_stack_frame_size (tree decl)
+ {
+   HOST_WIDE_INT size = 0;
+   size_t i;
+   tree t, outer_block = DECL_INITIAL (current_function_decl);
++  tree old_cur_fun_decl = current_function_decl;
++  current_function_decl = decl;
++  push_cfun (DECL_STRUCT_FUNCTION (decl));
+ 
+   init_vars_expansion ();
+ 
+@@ -1284,7 +1287,8 @@
+       size += account_stack_vars ();
+       fini_vars_expansion ();
+     }
+-
++  pop_cfun ();
++  current_function_decl = old_cur_fun_decl;
+   return size;
+ }
+ 
+
+=== modified file 'gcc/ipa-inline.c'
+--- old/gcc/ipa-inline.c	2010-06-30 21:30:12 +0000
++++ new/gcc/ipa-inline.c	2010-11-24 08:43:48 +0000
+@@ -1967,7 +1967,7 @@
+ 
+   /* Estimate the stack size for the function.  But not at -O0
+      because estimated_stack_frame_size is a quadratic problem.  */
+-  self_stack_size = optimize ? estimated_stack_frame_size () : 0;
++  self_stack_size = optimize ? estimated_stack_frame_size (node->decl) : 0;
+   inline_summary (node)->estimated_self_stack_size = self_stack_size;
+   node->global.estimated_stack_size = self_stack_size;
+   node->global.stack_frame_offset = 0;
+
+=== modified file 'gcc/tree-inline.h'
+--- old/gcc/tree-inline.h	2009-09-14 18:18:58 +0000
++++ new/gcc/tree-inline.h	2010-11-24 08:43:48 +0000
+@@ -187,6 +187,6 @@
+ extern tree remap_type (tree type, copy_body_data *id);
+ extern gimple_seq copy_gimple_seq_and_replace_locals (gimple_seq seq);
+ 
+-extern HOST_WIDE_INT estimated_stack_frame_size (void);
++extern HOST_WIDE_INT estimated_stack_frame_size (tree);
+ 
+ #endif /* GCC_TREE_INLINE_H */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99441.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99441.patch
new file mode 100644
index 0000000000..5495b8d80a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99441.patch
@@ -0,0 +1,33 @@
+2010-11-25  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-10-28  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (const_ok_for_arm): Support 0xXY00XY00 pattern
+	constants in thumb2.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-11-11 11:50:33 +0000
++++ new/gcc/config/arm/arm.c	2010-12-10 15:30:47 +0000
+@@ -2340,11 +2340,17 @@
+     {
+       HOST_WIDE_INT v;
+ 
+-      /* Allow repeated pattern.  */
++      /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY.  */
+       v = i & 0xff;
+       v |= v << 16;
+       if (i == v || i == (v | (v << 8)))
+ 	return TRUE;
++
++      /* Allow repeated pattern 0xXY00XY00.  */
++      v = i & 0xff00;
++      v |= v << 16;
++      if (i == v)
++	return TRUE;
+     }
+ 
+   return FALSE;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99442.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99442.patch
new file mode 100644
index 0000000000..62c44784b6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99442.patch
@@ -0,0 +1,23 @@
+2010-11-24  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	gcc/
+	* loop-iv.c (get_biv_step): Workaround loop analysis ICE.
+
+=== modified file 'gcc/loop-iv.c'
+--- old/gcc/loop-iv.c	2009-11-25 10:55:54 +0000
++++ new/gcc/loop-iv.c	2010-12-10 15:32:04 +0000
+@@ -796,6 +796,13 @@
+ 		       outer_step))
+     return false;
+ 
++  /* CSL local: workaround get_biv_step_1() inability to handle DU
++     chains originating at sets of subregs.  Such subregs are introduced
++     by Tom's extension elimination pass.  For upstream duscussion see
++     http://gcc.gnu.org/ml/gcc/2010-11/msg00552.html .  */
++  if (!((*inner_mode == *outer_mode) != (*extend != UNKNOWN)))
++    return false;
++
+   gcc_assert ((*inner_mode == *outer_mode) != (*extend != UNKNOWN));
+   gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99443.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99443.patch
new file mode 100644
index 0000000000..802c3816f1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99443.patch
@@ -0,0 +1,873 @@
+2010-11-26  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	* gcc/ee.c: New file.
+	* gcc/tree-pass.h (pass_ee): Declare.
+	* gcc/opts.c (decode_options): Set flag_ee at -O2.
+	* gcc/timevar.def (TV_EE): New timevar.
+	* gcc/common.opt (fextension-elimination): New option.
+	* gcc/Makefile.in (ee.o): New rule.
+	* gcc/passes.c (pass_ee): Add it.
+	* gcc/testsuite/gcc.dg/extend-4.c: New test.
+	* gcc/testsuite/gcc.dg/extend-1.c: New test.
+	* gcc/testsuite/gcc.dg/extend-2.c: New test.
+	* gcc/testsuite/gcc.dg/extend-2-64.c: New test.
+	* gcc/testsuite/gcc.dg/extend-3.c: New test.
+
+=== modified file 'gcc/Makefile.in'
+--- old/gcc/Makefile.in	2010-11-16 18:05:53 +0000
++++ new/gcc/Makefile.in	2010-12-10 15:33:37 +0000
+@@ -1194,6 +1194,7 @@
+ 	dse.o \
+ 	dwarf2asm.o \
+ 	dwarf2out.o \
++	ee.o \
+ 	ebitmap.o \
+ 	emit-rtl.o \
+ 	et-forest.o \
+@@ -2965,6 +2966,11 @@
+ web.o : web.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \
+    hard-reg-set.h $(FLAGS_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
+    $(DF_H) $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H)
++ee.o : ee.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \
++   hard-reg-set.h $(FLAGS_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h \
++   $(DF_H) $(TIMEVAR_H) tree-pass.h $(RECOG_H) $(EXPR_H) \
++   $(REGS_H) $(TREE_H) $(TM_P_H) insn-config.h $(INSN_ATTR_H) $(TOPLEV_H) $(DIAGNOSTIC_CORE_H) \
++   $(TARGET_H) $(OPTABS_H) insn-codes.h rtlhooks-def.h $(PARAMS_H) $(CGRAPH_H)
+ gcse.o : gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \
+    $(REGS_H) hard-reg-set.h $(FLAGS_H) $(REAL_H) insn-config.h $(GGC_H) \
+    $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
+
+=== modified file 'gcc/common.opt'
+--- old/gcc/common.opt	2010-11-04 12:43:52 +0000
++++ new/gcc/common.opt	2010-12-10 15:33:37 +0000
+@@ -496,6 +496,10 @@
+ Common Report Var(flag_early_inlining) Init(1) Optimization
+ Perform early inlining
+ 
++fextension-elimination
++Common Report Var(flag_ee) Init(0) Optimization
++Perform extension elimination
++
+ feliminate-dwarf2-dups
+ Common Report Var(flag_eliminate_dwarf2_dups)
+ Perform DWARF2 duplicate elimination
+
+=== added file 'gcc/ee.c'
+--- old/gcc/ee.c	1970-01-01 00:00:00 +0000
++++ new/gcc/ee.c	2010-12-10 15:33:37 +0000
+@@ -0,0 +1,662 @@
++/* Redundant extension elimination 
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   Contributed by Tom de Vries (tom@codesourcery.com)
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++/*
++
++  MOTIVATING EXAMPLE
++
++  The motivating example for this pass is:
++
++    void f(unsigned char *p, short s, int c, int *z)
++    {
++      if (c)
++        *z = 0;
++      *p ^= (unsigned char)s;
++    }
++
++  For MIPS, compilation results in the following insns.
++
++    (set (reg/v:SI 199)
++         (sign_extend:SI (subreg:HI (reg:SI 200) 2)))
++
++    ...
++
++    (set (reg:QI 203)
++         (subreg:QI (reg/v:SI 199) 3))
++
++  These insns are the only def and the only use of reg 199, each located in a
++  different bb.
++
++  The sign-extension preserves the lower half of reg 200 and copies them to 
++  reg 199, and the subreg use of reg 199 only reads the least significant byte.
++  The sign extension is therefore redundant (the extension part, not the copy 
++  part), and can safely be replaced with a regcopy from reg 200 to reg 199.
++
++
++  OTHER SIGN/ZERO EXTENSION ELIMINATION PASSES
++
++  There are other passes which eliminate sign/zero-extension: combine and
++  implicit_zee. Both attempt to eliminate extensions by combining them with
++  other instructions. The combine pass does this at bb level,
++  implicit_zee works at inter-bb level.
++
++  The combine pass combine an extension with either:
++  - all uses of the extension, or 
++  - all defs of the operand of the extension.
++  The implicit_zee pass only implements the latter.
++
++  For our motivating example, combine doesn't work since the def and the use of
++  reg 199 are in a different bb.
++
++  Implicit_zee does not work since it only combines an extension with the defs
++  of its operand.
++
++
++  INTENDED EFFECT
++
++  This pass works by removing sign/zero-extensions, or replacing them with
++  regcopies. The idea there is that the regcopy might be eliminated by a later
++  pass. In case the regcopy cannot be eliminated, it might at least be cheaper
++  than the extension.
++
++
++  IMPLEMENTATION
++
++  The pass scans twice over all instructions.
++
++  The first scan registers all uses of a reg in the biggest_use array. After
++  that first scan, the biggest_use array contains the size in bits of the
++  biggest use of each reg.
++
++  The second scan finds extensions, determines whether they are redundant based
++  on the biggest use, and deletes or replaces them.
++
++  In case that the src and dest reg of the replacement are not of the same size,
++  we do not replace with a normal regcopy, but with a truncate or with the copy
++  of a paradoxical subreg instead.
++
++
++  LIMITATIONS
++
++  The scope of the analysis is limited to an extension and its uses. The other
++  type of analysis (related to the defs of the operand of an extension) is not
++  done.
++
++  Furthermore, we do the analysis of biggest use per reg. So when determining
++  whether an extension is redundant, we take all uses of a the dest reg into
++  account, also the ones that are not uses of the extension. This could be
++  overcome by calculating the def-use chains and using those for analysis
++  instead.
++
++  Finally, during the analysis each insn is looked at in isolation. There is no
++  propagation of information during the analysis.  To overcome this limitation,
++  a backward iterative bit-level liveness analysis is needed.  */
++
++
++#include "config.h"
++#include "system.h"
++#include "coretypes.h"
++#include "tm.h"
++#include "rtl.h"
++#include "tree.h"
++#include "tm_p.h"
++#include "flags.h"
++#include "regs.h"
++#include "hard-reg-set.h"
++#include "basic-block.h"
++#include "insn-config.h"
++#include "function.h"
++#include "expr.h"
++#include "insn-attr.h"
++#include "recog.h"
++#include "toplev.h"
++#include "target.h"
++#include "timevar.h"
++#include "optabs.h"
++#include "insn-codes.h"
++#include "rtlhooks-def.h"
++#include "output.h"
++#include "params.h"
++#include "timevar.h"
++#include "tree-pass.h"
++#include "cgraph.h"
++
++#define SKIP_REG (-1)
++
++/* Array to register the biggest use of a reg, in bits.  */
++
++static int *biggest_use;
++
++/* Forward declaration.  */
++
++static void note_use (rtx *x, void *data);
++
++/* The following two functions are borrowed from trunk/gcc/toplev.c. They can be
++   removed for a check-in into gcc trunk.  */
++
++/* Given X, an unsigned number, return the number of least significant bits
++   that are zero.  When X == 0, the result is the word size.  */
++
++static int
++ctz_hwi (unsigned HOST_WIDE_INT x)
++{
++  return x ? floor_log2 (x & -x) : HOST_BITS_PER_WIDE_INT;
++}
++
++/* Similarly for most significant bits.  */
++
++static int
++clz_hwi (unsigned HOST_WIDE_INT x)
++{
++  return HOST_BITS_PER_WIDE_INT - 1 - floor_log2(x);
++}
++
++/* Check whether this is a paradoxical subreg. */
++
++static bool
++paradoxical_subreg_p (rtx subreg)
++{
++  enum machine_mode subreg_mode, reg_mode;
++
++  if (GET_CODE (subreg) != SUBREG)
++    return false;
++
++  subreg_mode = GET_MODE (subreg);
++  reg_mode = GET_MODE (SUBREG_REG (subreg));
++
++  if (GET_MODE_SIZE (subreg_mode) > GET_MODE_SIZE (reg_mode))
++    return true;
++
++  return false;
++}
++
++/* Get the size and reg number of a REG or SUBREG use.  */
++
++static bool
++reg_use_p (rtx use, int *size, unsigned int *regno)
++{
++  rtx reg;
++      
++  if (REG_P (use))
++    {
++      *regno = REGNO (use);
++      *size = GET_MODE_BITSIZE (GET_MODE (use));
++      return true;
++    }
++  else if (GET_CODE (use) == SUBREG)
++    {
++      reg = SUBREG_REG (use);
++
++      if (!REG_P (reg))
++        return false;
++
++      *regno = REGNO (reg);
++
++      if (paradoxical_subreg_p (use))
++        *size = GET_MODE_BITSIZE (GET_MODE (reg));
++      else
++        *size = subreg_lsb (use) + GET_MODE_BITSIZE (GET_MODE (use));
++
++      return true;
++    }
++
++  return false;
++}
++
++/* Register the use of a reg.  */
++
++static void
++register_use (int size, unsigned int regno)
++{
++  int *current = &biggest_use[regno];
++
++  if (*current == SKIP_REG)
++    return;
++  
++  *current = MAX (*current, size);
++}
++
++/* Handle embedded uses.  */
++
++static void
++note_embedded_uses (rtx use, rtx pattern)
++{
++  const char *format_ptr;
++  int i, j;
++
++  format_ptr = GET_RTX_FORMAT (GET_CODE (use));
++  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (use)); i++)
++    if (format_ptr[i] == 'e')
++      note_use (&XEXP (use, i), pattern);
++    else if (format_ptr[i] == 'E')
++      for (j = 0; j < XVECLEN (use, i); j++)
++        note_use (&XVECEXP (use, i, j), pattern);
++}
++
++/* Get the set that has use as its SRC operand.  */
++
++static rtx
++get_set (rtx use, rtx pattern)
++{
++  rtx sub;
++  int i;
++
++  if (GET_CODE (pattern) == SET && SET_SRC (pattern) == use)
++    return pattern;
++
++  if (GET_CODE (pattern) == PARALLEL)
++    for (i = 0; i < XVECLEN (pattern, 0); ++i)
++      {
++        sub = XVECEXP (pattern, 0, i);
++        if (GET_CODE (sub) == SET && SET_SRC (sub) == use)
++          return sub;
++      }
++  
++  return NULL_RTX;
++}
++
++/* Handle a restricted op use. In this context restricted means that a bit in an
++   operand influences only the same bit or more significant bits in the result.
++   The bitwise ops are a subclass, but PLUS is one as well.  */
++
++static void
++note_restricted_op_use (rtx use, unsigned int nr_operands, rtx pattern)
++{
++  unsigned int i, smallest;
++  int operand_size[2];
++  int used_size;
++  unsigned int operand_regno[2];
++  bool operand_reg[2];
++  bool operand_ignore[2];
++  rtx set;
++
++  /* Init operand_reg, operand_size, operand_regno and operand_ignore.  */
++  for (i = 0; i < nr_operands; ++i)
++    {
++      operand_reg[i] = reg_use_p (XEXP (use, i), &operand_size[i],
++                                  &operand_regno[i]);
++      operand_ignore[i] = false;
++    }
++
++  /* Handle case of reg and-masked with const.  */
++  if (GET_CODE (use) == AND && CONST_INT_P (XEXP (use, 1)) && operand_reg[0])
++    {
++      used_size =
++        HOST_BITS_PER_WIDE_INT - clz_hwi (UINTVAL (XEXP (use, 1)));
++      operand_size[0] = MIN (operand_size[0], used_size);
++    }
++
++  /* Handle case of reg or-masked with const.  */
++  if (GET_CODE (use) == IOR && CONST_INT_P (XEXP (use, 1)) && operand_reg[0])
++    {
++      used_size =
++        HOST_BITS_PER_WIDE_INT - clz_hwi (~UINTVAL (XEXP (use, 1)));
++      operand_size[0] = MIN (operand_size[0], used_size);
++    }
++
++  /* Ignore the use of a in 'a = a + b'.  */
++  set = get_set (use, pattern);
++  if (set != NULL_RTX && REG_P (SET_DEST (set)))
++    for (i = 0; i < nr_operands; ++i)
++      operand_ignore[i] = (operand_reg[i]
++                           && (REGNO (SET_DEST (set)) == operand_regno[i]));
++
++  /* Handle the case a reg is combined with don't care bits.  */
++  if (nr_operands == 2 && operand_reg[0] && operand_reg[1]
++      && operand_size[0] != operand_size[1])
++    {
++      smallest = operand_size[0] > operand_size[1];
++
++      if (paradoxical_subreg_p (XEXP (use, smallest))
++          && !SUBREG_PROMOTED_VAR_P (XEXP (use, smallest)))
++        operand_size[1 - smallest] = operand_size[smallest];
++    }
++
++  /* Register the operand use, if necessary.  */
++  for (i = 0; i < nr_operands; ++i)
++    if (!operand_reg[i])
++      note_use (&XEXP (use, i), pattern);
++    else if (!operand_ignore[i])
++      register_use (operand_size[i], operand_regno[i]);
++}
++
++/* Handle all uses noted by note_uses.  */
++
++static void
++note_use (rtx *x, void *data)
++{
++  rtx use = *x;
++  rtx pattern = (rtx)data;
++  int use_size;
++  unsigned int use_regno;
++
++  switch (GET_CODE (use))
++    {
++    case REG:
++    case SUBREG:
++      if (!reg_use_p (use, &use_size, &use_regno))
++        {
++          note_embedded_uses (use, pattern);
++          return;
++        }
++      register_use (use_size, use_regno);
++      return;
++    case IOR:
++    case AND:
++    case XOR:
++    case PLUS:
++    case MINUS:
++      note_restricted_op_use (use, 2, pattern);
++      return;
++    case NOT:
++    case NEG:
++      note_restricted_op_use (use, 1, pattern);
++      return;
++    case ASHIFT:
++      if (!reg_use_p (XEXP (use, 0), &use_size, &use_regno)
++	  || !CONST_INT_P (XEXP (use, 1))
++          || INTVAL (XEXP (use, 1)) <= 0
++          || paradoxical_subreg_p (XEXP (use, 0)))
++        {
++          note_embedded_uses (use, pattern);
++          return;
++        }
++      register_use (use_size - INTVAL (XEXP (use, 1)), use_regno);
++      return;
++    default:
++      note_embedded_uses (use, pattern);
++      return;
++    }
++}
++
++/* Check whether reg is implicitly used.  */
++
++static bool
++implicit_use_p (int regno)
++{
++#ifdef EPILOGUE_USES
++  if (EPILOGUE_USES (regno))
++    return true;
++#endif
++
++#ifdef EH_USES
++  if (EH_USES (regno))
++    return true;
++#endif
++
++  return false;
++}
++
++/* Note the uses of argument registers in a call.  */
++
++static void
++note_call_uses (rtx insn)
++{
++  rtx link, link_expr;
++
++  if (!CALL_P (insn))
++    return;
++
++  for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
++    {
++      link_expr = XEXP (link, 0);
++
++      if (GET_CODE (link_expr) == USE)
++        note_use (&XEXP (link_expr, 0), link);
++    }
++}
++
++/* Calculate the biggest use mode for all regs. */
++
++static void
++calculate_biggest_use (void)
++{
++  int i;
++  basic_block bb;
++  rtx insn;
++
++  /* Initialize biggest_use for all regs to 0. If a reg is used implicitly, we
++     handle that reg conservatively and set it to SKIP_REG instead.  */
++  for (i = 0; i < max_reg_num (); i++)
++    biggest_use[i] = ((implicit_use_p (i) || HARD_REGISTER_NUM_P (i))
++                      ? SKIP_REG : 0);
++
++  /* For all insns, call note_use for each use in insn.  */
++  FOR_EACH_BB (bb)
++    FOR_BB_INSNS (bb, insn)
++      {
++        if (!NONDEBUG_INSN_P (insn))
++          continue;
++
++        note_uses (&PATTERN (insn), note_use, PATTERN (insn));
++
++        if (CALL_P (insn))
++          note_call_uses (insn);
++      }
++
++  /* Dump the biggest uses found.  */
++  if (dump_file)
++    for (i = 0; i < max_reg_num (); i++)
++      if (biggest_use[i] > 0)
++        fprintf (dump_file, "reg %d: size %d\n", i, biggest_use[i]);
++}
++
++/* Check whether this is a sign/zero extension.  */
++
++static bool
++extension_p (rtx insn, rtx *dest, rtx *inner, int *preserved_size)
++{
++  rtx src, op0;
++
++  /* Detect set of reg.  */
++  if (GET_CODE (PATTERN (insn)) != SET)
++    return false;
++
++  src = SET_SRC (PATTERN (insn));
++  *dest = SET_DEST (PATTERN (insn));
++          
++  if (!REG_P (*dest))
++    return false;
++
++  /* Detect sign or zero extension.  */
++  if (GET_CODE (src) == ZERO_EXTEND || GET_CODE (src) == SIGN_EXTEND
++      || (GET_CODE (src) == AND && CONST_INT_P (XEXP (src, 1))))
++    {
++      op0 = XEXP (src, 0);
++
++      /* Determine amount of least significant bits preserved by operation.  */
++      if (GET_CODE (src) == AND)
++        *preserved_size = ctz_hwi (~UINTVAL (XEXP (src, 1)));
++      else
++        *preserved_size = GET_MODE_BITSIZE (GET_MODE (op0));
++
++      if (GET_CODE (op0) == SUBREG)
++        {
++          if (subreg_lsb (op0) != 0)
++            return false;
++      
++          *inner = SUBREG_REG (op0);
++          return true;
++        }
++      else if (REG_P (op0))
++        {
++          *inner = op0;
++          return true;
++        }
++    }
++
++  return false;
++}
++
++/* Check whether this is a redundant sign/zero extension.  */
++
++static bool
++redundant_extension_p (rtx insn, rtx *dest, rtx *inner)
++{
++  int biggest_dest_use;
++  int preserved_size;
++
++  if (!extension_p (insn, dest, inner, &preserved_size))
++    return false;
++
++  if (dump_file)
++    fprintf (dump_file, "considering extension %u with preserved size %d\n", 
++             INSN_UID (insn), preserved_size);
++
++  biggest_dest_use = biggest_use[REGNO (*dest)];
++      
++  if (biggest_dest_use == SKIP_REG)
++    return false;
++
++  if (preserved_size < biggest_dest_use)
++    return false;
++
++  if (dump_file)
++    fprintf (dump_file, "found superfluous extension %u\n", INSN_UID (insn));
++
++  return true;
++}
++
++/* Try to remove or replace the redundant extension.  */
++
++static void
++try_remove_or_replace_extension (rtx insn, rtx dest, rtx inner)
++{
++  rtx cp_src, cp_dest, seq, one;
++
++  if (GET_MODE_CLASS (GET_MODE (dest)) != GET_MODE_CLASS (GET_MODE (inner)))
++    return;
++
++  /* Check whether replacement is needed.  */
++  if (dest != inner)
++    {
++      start_sequence ();
++
++      /* Determine the proper replacement operation.  */
++      if (GET_MODE (dest) == GET_MODE (inner))
++        {
++          cp_src = inner;
++          cp_dest = dest;
++        }
++      else if (GET_MODE_SIZE (GET_MODE (dest))
++               > GET_MODE_SIZE (GET_MODE (inner)))
++        {
++          emit_clobber (dest);
++          cp_src = inner;
++          cp_dest = gen_lowpart_SUBREG (GET_MODE (inner), dest);
++        }
++      else 
++        {
++          cp_src = gen_rtx_TRUNCATE (GET_MODE (dest), inner);
++          cp_dest = dest;
++        }
++
++      emit_move_insn (cp_dest, cp_src);
++
++      seq = get_insns ();
++      end_sequence ();
++
++      /* If the replacement is not supported, bail out.  */
++      for (one = seq; one != NULL_RTX; one = NEXT_INSN (one))
++        if (recog_memoized (one) < 0 && GET_CODE (PATTERN (one)) != CLOBBER)
++          return;
++
++      /* Insert the replacement.  */
++      emit_insn_before (seq, insn);
++    }
++
++  /* Note replacement/removal in the dump.  */
++  if (dump_file)
++    {
++      fprintf (dump_file, "superfluous extension %u ", INSN_UID (insn));
++      if (dest != inner)
++        fprintf (dump_file, "replaced by %u\n", INSN_UID (seq));
++      else
++        fprintf (dump_file, "removed\n");
++    }
++
++  /* Remove the extension.  */
++  delete_insn (insn);  
++}
++
++/* Find redundant extensions and remove or replace them if possible.  */
++
++static void
++remove_redundant_extensions (void)
++{
++  basic_block bb;
++  rtx insn, next, dest, inner;
++
++  biggest_use = XNEWVEC (int, max_reg_num ());
++  calculate_biggest_use ();
++
++  /* Remove redundant extensions.  */
++  FOR_EACH_BB (bb)
++    FOR_BB_INSNS_SAFE (bb, insn, next)
++      {
++        if (!NONDEBUG_INSN_P (insn))
++          continue;
++
++        if (!redundant_extension_p (insn, &dest, &inner))
++          continue;
++
++        try_remove_or_replace_extension (insn, dest, inner);
++      }
++
++  free (biggest_use);
++}
++
++/* Remove redundant extensions.  */
++
++static unsigned int
++rest_of_handle_ee (void)
++{
++  remove_redundant_extensions ();
++  return 0;
++}
++
++/* Run ee pass when flag_ee is set at optimization level > 0.  */
++
++static bool
++gate_handle_ee (void)
++{
++  return (optimize > 0 && flag_ee);
++}
++
++struct rtl_opt_pass pass_ee =
++{
++ {
++  RTL_PASS,
++  "ee",                                 /* name */
++  gate_handle_ee,                       /* gate */
++  rest_of_handle_ee,                    /* execute */
++  NULL,                                 /* sub */
++  NULL,                                 /* next */
++  0,                                    /* static_pass_number */
++  TV_EE,                                /* tv_id */
++  0,                                    /* properties_required */
++  0,                                    /* properties_provided */
++  0,                                    /* properties_destroyed */
++  0,                                    /* todo_flags_start */
++  TODO_ggc_collect |
++  TODO_dump_func |
++  TODO_verify_rtl_sharing,              /* todo_flags_finish */
++ }
++};
+
+=== modified file 'gcc/opts.c'
+--- old/gcc/opts.c	2010-05-17 09:13:28 +0000
++++ new/gcc/opts.c	2010-12-10 15:33:37 +0000
+@@ -907,6 +907,7 @@
+   flag_tree_switch_conversion = opt2;
+   flag_ipa_cp = opt2;
+   flag_ipa_sra = opt2;
++  flag_ee = opt2;
+ 
+   /* Track fields in field-sensitive alias analysis.  */
+   set_param_value ("max-fields-for-field-sensitive",
+
+=== modified file 'gcc/passes.c'
+--- old/gcc/passes.c	2010-09-01 13:29:58 +0000
++++ new/gcc/passes.c	2010-12-10 15:33:37 +0000
+@@ -974,6 +974,7 @@
+       NEXT_PASS (pass_lower_subreg);
+       NEXT_PASS (pass_df_initialize_opt);
+       NEXT_PASS (pass_cse);
++      NEXT_PASS (pass_ee);
+       NEXT_PASS (pass_rtl_fwprop);
+       NEXT_PASS (pass_rtl_cprop);
+       NEXT_PASS (pass_rtl_pre);
+
+=== added file 'gcc/testsuite/gcc.dg/extend-1.c'
+--- old/gcc/testsuite/gcc.dg/extend-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/extend-1.c	2010-12-10 15:33:37 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ee" } */
++
++void f(unsigned char * p, short s, int c, int *z)
++{
++  if (c)
++    *z = 0;
++  *p ^= (unsigned char)s;
++}
++
++/* { dg-final { scan-rtl-dump-times "sign_extend:" 0 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 1 "ee" { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "ee" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/extend-2-64.c'
+--- old/gcc/testsuite/gcc.dg/extend-2-64.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/extend-2-64.c	2010-12-10 15:33:37 +0000
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ee" } */
++/* { dg-require-effective-target mips64 } */
++
++void f(unsigned char * p, short *s, int c)
++{
++  short or = 0;
++  while (c)
++    {
++      or = or | s[c];
++      c --;
++    }
++  *p = (unsigned char)or;
++}
++
++/* { dg-final { scan-rtl-dump-times "zero_extend:" 1 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "sign_extend:" 0 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 3 "ee" { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "ee" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/extend-2.c'
+--- old/gcc/testsuite/gcc.dg/extend-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/extend-2.c	2010-12-10 15:33:37 +0000
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ee" } */
++/* { dg-require-effective-target ilp32 } */
++
++void f(unsigned char * p, short *s, int c)
++{
++  short or = 0;
++  while (c)
++    {
++      or = or | s[c];
++      c --;
++    }
++  *p = (unsigned char)or;
++}
++
++/* { dg-final { scan-rtl-dump-times "zero_extend" 0 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "sign_extend" 0 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 2 "ee" { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "ee" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/extend-3.c'
+--- old/gcc/testsuite/gcc.dg/extend-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/extend-3.c	2010-12-10 15:33:37 +0000
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ee" } */
++
++unsigned int f(unsigned char byte)
++{
++  return byte << 25;
++}
++
++/* { dg-final { scan-rtl-dump-times "zero_extend:" 0 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump "superfluous extension \[0-9\]+ replaced" "ee" { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "ee" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/extend-4.c'
+--- old/gcc/testsuite/gcc.dg/extend-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/extend-4.c	2010-12-10 15:33:37 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ee" } */
++
++unsigned char f(unsigned int a)
++{
++  unsigned int b = a & 0x10ff;
++  return b;
++}
++
++/* { dg-final { scan-rtl-dump-times "and:" 0 "ee" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 1 "ee" { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "ee" } } */
++
+
+=== modified file 'gcc/timevar.def'
+--- old/gcc/timevar.def	2009-11-27 12:43:08 +0000
++++ new/gcc/timevar.def	2010-12-10 15:33:37 +0000
+@@ -162,6 +162,7 @@
+ DEFTIMEVAR (TV_VARCONST              , "varconst")
+ DEFTIMEVAR (TV_LOWER_SUBREG	     , "lower subreg")
+ DEFTIMEVAR (TV_JUMP                  , "jump")
++DEFTIMEVAR (TV_EE                    , "extension elimination")
+ DEFTIMEVAR (TV_FWPROP                , "forward prop")
+ DEFTIMEVAR (TV_CSE                   , "CSE")
+ DEFTIMEVAR (TV_DCE                   , "dead code elimination")
+
+=== modified file 'gcc/tree-pass.h'
+--- old/gcc/tree-pass.h	2010-09-01 13:29:58 +0000
++++ new/gcc/tree-pass.h	2010-12-10 15:33:37 +0000
+@@ -468,6 +468,7 @@
+ extern struct rtl_opt_pass pass_initial_value_sets;
+ extern struct rtl_opt_pass pass_unshare_all_rtl;
+ extern struct rtl_opt_pass pass_instantiate_virtual_regs;
++extern struct rtl_opt_pass pass_ee;
+ extern struct rtl_opt_pass pass_rtl_fwprop;
+ extern struct rtl_opt_pass pass_rtl_fwprop_addr;
+ extern struct rtl_opt_pass pass_jump2;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99444.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99444.patch
new file mode 100644
index 0000000000..80eebeec0c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99444.patch
@@ -0,0 +1,183 @@
+2010-12-02  Bernd Schmidt  <bernds@codesourcery.com>
+
+	Issue #10089
+
+	gcc/
+	* expr.c (store_field): Avoid a direct store if the mode is larger
+	than the size of the bit field.
+	* stor-layout.c (layout_decl): If flag_strict_volatile_bitfields,
+	treat non-volatile bit fields like volatile ones.
+	* toplev.c (process_options): Disallow combination of
+	-fstrict-volatile-bitfields and ABI versions less than 2.
+	* config/arm/arm.c (arm_option_override): Don't enable
+	flag_strict_volatile_bitfields if the ABI version is less than 2.
+	* config/h8300/h8300.c (h8300_option_override): Likewise.
+	* config/rx/rx.c (rx_option_override): Likewise.
+	* config/m32c/m32c.c (m32c_option_override): Likewise.
+	* config/sh/sh.c (sh_option_override): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/volatile-bitfields-4.c: New test.
+	* c-c++-common/abi-bf.c: New test.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-12-10 15:30:47 +0000
++++ new/gcc/config/arm/arm.c	2010-12-10 15:34:19 +0000
+@@ -1934,7 +1934,8 @@
+     set_param_value ("gcse-unrestricted-cost", 2);
+ 
+   /* ARM EABI defaults to strict volatile bitfields.  */
+-  if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0)
++  if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0
++      && abi_version_at_least(2))
+     flag_strict_volatile_bitfields = 1;
+ 
+   /* Register global variables with the garbage collector.  */
+
+=== modified file 'gcc/config/h8300/h8300.c'
+--- old/gcc/config/h8300/h8300.c	2010-11-04 12:43:52 +0000
++++ new/gcc/config/h8300/h8300.c	2010-12-10 15:34:19 +0000
+@@ -405,7 +405,7 @@
+     }
+ 
+   /* This target defaults to strict volatile bitfields.  */
+-  if (flag_strict_volatile_bitfields < 0)
++  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
+     flag_strict_volatile_bitfields = 1;
+ }
+ 
+
+=== modified file 'gcc/config/m32c/m32c.c'
+--- old/gcc/config/m32c/m32c.c	2010-11-04 12:43:52 +0000
++++ new/gcc/config/m32c/m32c.c	2010-12-10 15:34:19 +0000
+@@ -430,7 +430,7 @@
+     flag_ivopts = 0;
+ 
+   /* This target defaults to strict volatile bitfields.  */
+-  if (flag_strict_volatile_bitfields < 0)
++  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
+     flag_strict_volatile_bitfields = 1;
+ }
+ 
+
+=== modified file 'gcc/config/rx/rx.c'
+--- old/gcc/config/rx/rx.c	2010-11-04 12:43:52 +0000
++++ new/gcc/config/rx/rx.c	2010-12-10 15:34:19 +0000
+@@ -2191,7 +2191,7 @@
+ rx_option_override (void)
+ {
+   /* This target defaults to strict volatile bitfields.  */
+-  if (flag_strict_volatile_bitfields < 0)
++  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
+     flag_strict_volatile_bitfields = 1;
+ }
+ 
+
+=== modified file 'gcc/config/sh/sh.c'
+--- old/gcc/config/sh/sh.c	2010-11-04 12:43:52 +0000
++++ new/gcc/config/sh/sh.c	2010-12-10 15:34:19 +0000
+@@ -952,7 +952,7 @@
+     sh_fix_range (sh_fixed_range_str);
+ 
+   /* This target defaults to strict volatile bitfields.  */
+-  if (flag_strict_volatile_bitfields < 0)
++  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
+     flag_strict_volatile_bitfields = 1;
+ }
+ 
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2010-11-04 12:43:52 +0000
++++ new/gcc/expr.c	2010-12-10 15:34:19 +0000
+@@ -5848,6 +5848,8 @@
+ 		|| bitpos % GET_MODE_ALIGNMENT (mode))
+ 	       && SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (target)))
+ 	      || (bitpos % BITS_PER_UNIT != 0)))
++      || (bitsize >= 0 && mode != BLKmode
++	  && GET_MODE_BITSIZE (mode) > bitsize)
+       /* If the RHS and field are a constant size and the size of the
+ 	 RHS isn't the same size as the bitfield, we must use bitfield
+ 	 operations.  */
+
+=== modified file 'gcc/stor-layout.c'
+--- old/gcc/stor-layout.c	2010-11-26 12:03:32 +0000
++++ new/gcc/stor-layout.c	2010-12-10 15:34:19 +0000
+@@ -621,12 +621,13 @@
+ 	  /* See if we can use an ordinary integer mode for a bit-field.
+ 	     Conditions are: a fixed size that is correct for another mode,
+ 	     occupying a complete byte or bytes on proper boundary,
+-	     and not volatile or not -fstrict-volatile-bitfields.  */
++	     and not -fstrict-volatile-bitfields.  If the latter is set,
++	     we unfortunately can't check TREE_THIS_VOLATILE, as a cast
++	     may make a volatile object later.  */
+ 	  if (TYPE_SIZE (type) != 0
+ 	      && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
+ 	      && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT
+-	      && !(TREE_THIS_VOLATILE (decl)
+-		   && flag_strict_volatile_bitfields > 0))
++	      && flag_strict_volatile_bitfields <= 0)
+ 	    {
+ 	      enum machine_mode xmode
+ 		= mode_for_size_tree (DECL_SIZE (decl), MODE_INT, 1);
+
+=== added file 'gcc/testsuite/c-c++-common/abi-bf.c'
+--- old/gcc/testsuite/c-c++-common/abi-bf.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/c-c++-common/abi-bf.c	2010-12-10 15:34:19 +0000
+@@ -0,0 +1,3 @@
++/* { dg-warning "incompatible" } */
++/* { dg-do compile } */
++/* { dg-options "-fstrict-volatile-bitfields -fabi-version=1" } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c'
+--- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c	2010-12-10 15:34:19 +0000
+@@ -0,0 +1,30 @@
++/* { dg-require-effective-target arm_eabi } */

++/* { dg-do compile } */

++/* { dg-options "-O2" } */

++/* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */

++/* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */

++/* { dg-final { scan-assembler-not "strb" } } */

++

++struct thing {

++  unsigned a: 8;

++  unsigned b: 8;

++  unsigned c: 8;

++  unsigned d: 8;

++};

++

++struct thing2 {

++  volatile unsigned a: 8;

++  volatile unsigned b: 8;

++  volatile unsigned c: 8;

++  volatile unsigned d: 8;

++};

++

++void test1(volatile struct thing *t)

++{

++  t->a = 5;

++}

++

++void test2(struct thing2 *t)

++{

++  t->a = 5;

++}

+
+=== modified file 'gcc/toplev.c'
+--- old/gcc/toplev.c	2010-03-31 01:44:10 +0000
++++ new/gcc/toplev.c	2010-12-10 15:34:19 +0000
+@@ -1851,6 +1851,13 @@
+     sorry ("Graphite loop optimizations cannot be used");
+ #endif
+ 
++  if (flag_strict_volatile_bitfields > 0 && !abi_version_at_least (2))
++    {
++      warning (0, "-fstrict-volatile-bitfield disabled; "
++	       "it is incompatible with ABI versions < 2");
++      flag_strict_volatile_bitfields = 0;
++    }
++
+   /* Unrolling all loops implies that standard loop unrolling must also
+      be done.  */
+   if (flag_unroll_all_loops)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99449.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99449.patch
new file mode 100644
index 0000000000..e6b0fad08f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99449.patch
@@ -0,0 +1,34 @@
+2010-12-21  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	LP: #617384
+	Backport from mainline:
+
+	gcc/
+	* config/arm/arm.c (require_pic_register): Set INSN_LOCATOR for all
+	instructions injected into the prologue to prologue_locator.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-12-10 15:34:19 +0000
++++ new/gcc/config/arm/arm.c	2010-12-21 14:13:38 +0000
+@@ -5080,7 +5080,7 @@
+ 	}
+       else
+ 	{
+-	  rtx seq;
++	  rtx seq, insn;
+ 
+ 	  if (!cfun->machine->pic_reg)
+ 	    cfun->machine->pic_reg = gen_reg_rtx (Pmode);
+@@ -5097,6 +5097,11 @@
+ 
+ 	      seq = get_insns ();
+ 	      end_sequence ();
++
++	      for (insn = seq; insn; insn = NEXT_INSN (insn))
++		if (INSN_P (insn))
++		  INSN_LOCATOR (insn) = prologue_locator;
++
+ 	      /* We can be called during expansion of PHI nodes, where
+ 	         we can't yet emit instructions directly in the final
+ 		 insn stream.  Queue the insns on the entry edge, they will
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99450.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99450.patch
new file mode 100644
index 0000000000..49fa07fca2
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99450.patch
@@ -0,0 +1,104 @@
+ 2010-12-21  Ulrich Weigand  <uweigand@de.ibm.com>
+ 
+	LP: #662324
+	Backport from mainline:
+
+	2010-12-17  Dodji Seketeli  <dodji@redhat.com>
+
+	gcc/
+	* dwarf2out.c (gen_type_die_with_usage): Do not try to emit debug
+	info for a redundant typedef that has DECL_ORIGINAL_TYPE set. Use
+	that underlying type instead.
+
+	gcc/testsuite/
+	* g++.dg/debug/dwarf2/self-ref-1.C: New test.
+	* g++.dg/debug/dwarf2/self-ref-2.C: Likewise.
+
+=== modified file 'gcc/dwarf2out.c'
+--- old/gcc/dwarf2out.c	2010-10-04 00:50:43 +0000
++++ new/gcc/dwarf2out.c	2010-12-21 18:46:10 +0000
+@@ -18993,6 +18993,16 @@
+   if (type == NULL_TREE || type == error_mark_node)
+     return;
+ 
++  if (TYPE_NAME (type) != NULL_TREE
++      && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
++      && is_redundant_typedef (TYPE_NAME (type))
++      && DECL_ORIGINAL_TYPE (TYPE_NAME (type)))
++    /* The DECL of this type is a typedef we don't want to emit debug
++       info for but we want debug info for its underlying typedef.
++       This can happen for e.g, the injected-class-name of a C++
++       type.  */
++    type = DECL_ORIGINAL_TYPE (TYPE_NAME (type));
++
+   /* If TYPE is a typedef type variant, let's generate debug info
+      for the parent typedef which TYPE is a type of.  */
+   if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
+
+=== added file 'gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C'
+--- old/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C	2010-12-21 18:46:10 +0000
+@@ -0,0 +1,28 @@
++// Origin: PR debug/45088
++// { dg-do compile }
++// { dg-options "-g -dA" }
++// { dg-final { scan-assembler-times "\[^\n\r\]*\\(DIE\[^\n\r\]*DW_TAG_pointer_type\\)\[\n\r\]{1,2}\[^\n\r\]*DW_AT_byte_size\[\n\r\]{1,2}\[^\n\r\]*DW_AT_type" 4 } }
++
++struct A
++{
++    virtual ~A();
++};
++
++struct B : public A
++{
++    virtual ~B(){}
++};
++
++struct C : public B
++{
++    A* a1;
++};
++
++int
++main()
++{
++    C c;
++    c.a1 = 0;
++    return 0;
++}
++
+
+=== added file 'gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C'
+--- old/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C	2010-12-21 18:46:10 +0000
+@@ -0,0 +1,29 @@
++// Origin: PR debug/45088
++// { dg-do compile }
++// { dg-options "-g -dA" }
++// { dg-final { scan-assembler-times "\[^\n\r\]*\\(DIE\[^\n\r\]*DW_TAG_pointer_type\\)\[\n\r\]{1,2}\[^\n\r\]*DW_AT_byte_size\[\n\r\]{1,2}\[^\n\r\]*DW_AT_type" 4 } }
++
++template<class T>
++struct A
++{
++    virtual ~A();
++};
++
++struct B : public A<int>
++{
++    virtual ~B(){}
++};
++
++struct C : public B
++{
++    A<int>* a1;
++};
++
++int
++main()
++{
++    C c;
++    c.a1 = 0;
++    return 0;
++}
++
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99451.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99451.patch
new file mode 100644
index 0000000000..d87c312d07
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99451.patch
@@ -0,0 +1,45 @@
+2010-12-22  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	LP: #693425
+	Backport from mainline:
+
+	gcc/
+	* config/spu/spu.md ("mov<mode>"): Use nonimmediate_operand
+	predicate for destination operand.
+	* config/spu/spu.c (spu_expand_mov): If move destination is an
+	invalid subreg, perform move in the subreg's inner mode instead.
+
+=== modified file 'gcc/config/spu/spu.c'
+--- old/gcc/config/spu/spu.c	2010-08-04 09:53:04 +0000
++++ new/gcc/config/spu/spu.c	2010-12-22 15:20:44 +0000
+@@ -4572,7 +4572,13 @@
+ spu_expand_mov (rtx * ops, enum machine_mode mode)
+ {
+   if (GET_CODE (ops[0]) == SUBREG && !valid_subreg (ops[0]))
+-    abort ();
++    {
++      /* Perform the move in the destination SUBREG's inner mode.  */
++      ops[0] = SUBREG_REG (ops[0]);
++      mode = GET_MODE (ops[0]);
++      ops[1] = gen_lowpart_common (mode, ops[1]);
++      gcc_assert (ops[1]);
++    }
+ 
+   if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1]))
+     {
+
+=== modified file 'gcc/config/spu/spu.md'
+--- old/gcc/config/spu/spu.md	2009-05-23 01:28:14 +0000
++++ new/gcc/config/spu/spu.md	2010-12-22 15:20:44 +0000
+@@ -269,8 +269,8 @@
+ ;; mov
+ 
+ (define_expand "mov<mode>"
+-  [(set (match_operand:ALL 0 "spu_nonimm_operand" "=r,r,r,m")
+-	(match_operand:ALL 1 "general_operand" "r,i,m,r"))]
++  [(set (match_operand:ALL 0 "nonimmediate_operand" "")
++	(match_operand:ALL 1 "general_operand" ""))]
+   ""
+   {
+     if (spu_expand_mov(operands, <MODE>mode))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99452.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99452.patch
new file mode 100644
index 0000000000..6cfc01feff
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99452.patch
@@ -0,0 +1,201 @@
+2010-12-14  Sandra Loosemore  <sandra@codesourcery.com>
+
+	Backport from mainline:
+
+	2010-12-14  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/46909
+
+	gcc/
+	* tree-ssa-ccp.c (and_var_with_comparison_1): Save partial
+	result even in the is_and case, if both partial results
+	are the same, return it.
+	(or_var_with_comparison_1): Use is_or predicate instead of
+	innercode == TRUTH_OR_EXPR test.  Save partial result
+	even in the is_or case, if both partial results are the
+	same, return it.  In the !is_or case when both partial
+	results are the same, return the partial result instead
+	of boolean_true_node.
+
+	gcc/testsuite/
+	* gcc.c-torture/execute/pr46909-1.c: New test.
+	* gcc.c-torture/execute/pr46909-2.c: New test.
+	* gcc.dg/pr46909.c: New test.
+
+=== added file 'gcc/testsuite/gcc.c-torture/execute/pr46909-1.c'
+--- old/gcc/testsuite/gcc.c-torture/execute/pr46909-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/execute/pr46909-1.c	2011-01-05 11:27:00 +0000
+@@ -0,0 +1,22 @@
++/* PR tree-optimization/46909 */
++
++extern void abort ();
++
++int
++__attribute__ ((__noinline__))
++foo (unsigned int x)
++{
++  if (! (x == 4 || x == 6) || (x == 2 || x == 6))
++    return 1;
++  return -1;
++}
++
++int
++main ()
++{
++  int i;
++  for (i = -10; i < 10; i++)
++    if (foo (i) != 1 - 2 * (i == 4))
++      abort ();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.c-torture/execute/pr46909-2.c'
+--- old/gcc/testsuite/gcc.c-torture/execute/pr46909-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/execute/pr46909-2.c	2011-01-05 11:27:00 +0000
+@@ -0,0 +1,22 @@
++/* PR tree-optimization/46909 */
++
++extern void abort (void);
++
++int
++__attribute__((noinline))
++foo (int x)
++{
++  if ((x != 0 && x != 13) || x == 5 || x == 20)
++    return 1;
++  return -1;
++}
++
++int
++main (void)
++{
++  int i;
++  for (i = -10; i < 30; i++)
++    if (foo (i) != 1 - 2 * (i == 0) - 2 * (i == 13))
++      abort ();
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.dg/pr46909.c'
+--- old/gcc/testsuite/gcc.dg/pr46909.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr46909.c	2011-01-05 11:27:00 +0000
+@@ -0,0 +1,17 @@
++/* PR tree-optimization/46909 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-ifcombine" } */
++
++extern void abort ();
++
++int
++__attribute__ ((__noinline__))
++foo (unsigned int x)
++{
++  if (! (x == 4 || x == 6) || (x == 2 || x == 6))
++    return 1;
++  return -1;
++}
++
++/* { dg-final { scan-tree-dump "optimizing two comparisons to x_\[0-9\]+\\(D\\) != 4" "ifcombine" } } */
++/* { dg-final { cleanup-tree-dump "ifcombine" } } */
+
+=== modified file 'gcc/tree-ssa-ccp.c'
+--- old/gcc/tree-ssa-ccp.c	2010-09-16 09:15:46 +0000
++++ new/gcc/tree-ssa-ccp.c	2011-01-05 11:27:00 +0000
+@@ -3508,14 +3508,11 @@
+ 	  /* Handle the OR case, where we are redistributing:
+ 	     (inner1 OR inner2) AND (op2a code2 op2b)
+ 	     => (t OR (inner2 AND (op2a code2 op2b)))  */
+-	  else
+-	    {
+-	      if (integer_onep (t))
+-		return boolean_true_node;
+-	      else
+-		/* Save partial result for later.  */
+-		partial = t;
+-	    }
++	  else if (integer_onep (t))
++	    return boolean_true_node;
++
++	  /* Save partial result for later.  */
++	  partial = t;
+ 	}
+       
+       /* Compute the second partial result, (inner2 AND (op2a code op2b)) */
+@@ -3536,6 +3533,10 @@
+ 		return inner1;
+ 	      else if (integer_zerop (t))
+ 		return boolean_false_node;
++	      /* If both are the same, we can apply the identity
++		 (x AND x) == x.  */
++	      else if (partial && same_bool_result_p (t, partial))
++		return t;
+ 	    }
+ 
+ 	  /* Handle the OR case. where we are redistributing:
+@@ -3945,7 +3946,7 @@
+ 	     => (t OR inner2)
+ 	     If the partial result t is a constant, we win.  Otherwise
+ 	     continue on to try reassociating with the other inner test.  */
+-	  if (innercode == TRUTH_OR_EXPR)
++	  if (is_or)
+ 	    {
+ 	      if (integer_onep (t))
+ 		return boolean_true_node;
+@@ -3956,14 +3957,11 @@
+ 	  /* Handle the AND case, where we are redistributing:
+ 	     (inner1 AND inner2) OR (op2a code2 op2b)
+ 	     => (t AND (inner2 OR (op2a code op2b)))  */
+-	  else
+-	    {
+-	      if (integer_zerop (t))
+-		return boolean_false_node;
+-	      else
+-		/* Save partial result for later.  */
+-		partial = t;
+-	    }
++	  else if (integer_zerop (t))
++	    return boolean_false_node;
++
++	  /* Save partial result for later.  */
++	  partial = t;
+ 	}
+       
+       /* Compute the second partial result, (inner2 OR (op2a code op2b)) */
+@@ -3977,13 +3975,18 @@
+ 	{
+ 	  /* Handle the OR case, where we are reassociating:
+ 	     (inner1 OR inner2) OR (op2a code2 op2b)
+-	     => (inner1 OR t)  */
+-	  if (innercode == TRUTH_OR_EXPR)
++	     => (inner1 OR t)
++	     => (t OR partial)  */
++	  if (is_or)
+ 	    {
+ 	      if (integer_zerop (t))
+ 		return inner1;
+ 	      else if (integer_onep (t))
+ 		return boolean_true_node;
++	      /* If both are the same, we can apply the identity
++		 (x OR x) == x.  */
++	      else if (partial && same_bool_result_p (t, partial))
++		return t;
+ 	    }
+ 	  
+ 	  /* Handle the AND case, where we are redistributing:
+@@ -4000,13 +4003,13 @@
+ 		     operand to the redistributed AND expression.  The
+ 		     interesting case is when at least one is true.
+ 		     Or, if both are the same, we can apply the identity
+-		     (x AND x) == true.  */
++		     (x AND x) == x.  */
+ 		  if (integer_onep (partial))
+ 		    return t;
+ 		  else if (integer_onep (t))
+ 		    return partial;
+ 		  else if (same_bool_result_p (t, partial))
+-		    return boolean_true_node;
++		    return t;
+ 		}
+ 	    }
+ 	}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99453.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99453.patch
new file mode 100644
index 0000000000..8eb35325ee
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99453.patch
@@ -0,0 +1,72 @@
+2010-12-17  Bernd Schmidt  <bernds@codesourcery.com>
+
+	Issue #10208
+
+	gcc/
+	* config/arm/arm.c (arm_select_cc_mode): Before calling
+	arm_select_dominance_cc_mode for AND or IOR operations, ensure
+	that op is NE or EQ.
+
+	gcc/testsuite/
+	* gcc.c-torture/compile/20101217-1.c: New test.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2010-12-21 14:13:38 +0000
++++ new/gcc/config/arm/arm.c	2011-01-05 11:32:50 +0000
+@@ -10609,12 +10609,14 @@
+ 
+   /* Alternate canonicalizations of the above.  These are somewhat cleaner.  */
+   if (GET_CODE (x) == AND
++      && (op == EQ || op == NE)
+       && COMPARISON_P (XEXP (x, 0))
+       && COMPARISON_P (XEXP (x, 1)))
+     return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
+ 					 DOM_CC_X_AND_Y);
+ 
+   if (GET_CODE (x) == IOR
++      && (op == EQ || op == NE)
+       && COMPARISON_P (XEXP (x, 0))
+       && COMPARISON_P (XEXP (x, 1)))
+     return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
+
+=== added file 'gcc/testsuite/gcc.c-torture/compile/20101217-1.c'
+--- old/gcc/testsuite/gcc.c-torture/compile/20101217-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/compile/20101217-1.c	2011-01-05 11:32:50 +0000
+@@ -0,0 +1,36 @@
++/* Testcase provided by HUAWEI.  */
++#include <stdio.h>
++int main()
++{
++        int cur_k;
++        int cur_j=0;
++        int cur_i=28;
++        unsigned char temp_data[8];
++        unsigned int Data_Size=20;
++
++        for (cur_k=0;cur_j<7;cur_j++,cur_i++) {
++                if (cur_j%2==0) {
++                        temp_data[cur_k++]=0;
++                }
++                if (cur_k==7) {
++                        for (;cur_k>0;cur_k--) {
++                                if (cur_k>2) {
++                                        if ((temp_data[7-cur_k]=='n' || temp_data[7-cur_k]=='N' ) && (temp_data[7-cur_k+1]=='a' || temp_data[7-cur_k+1]=='A' )) {
++                                                break;
++                                        }
++                                }
++                                if (cur_k==1) {
++                                        if (temp_data[7-cur_k]=='n' || temp_data[7-cur_k]=='N' ) {
++                                                break;
++                                        }
++                                }
++                        }
++                        if (cur_k==7) {
++                        } else {
++                                if (cur_k>0)
++                                        printf("dfjk");
++                        }
++                }
++        }
++return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99454.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99454.patch
new file mode 100644
index 0000000000..8aa06cc510
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99454.patch
@@ -0,0 +1,46 @@
+2010-12-18  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+
+	gcc/
+	2010-12-17  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical
+	operand order for plus.
+	Drop redundant % from constraints.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2010-11-11 11:12:14 +0000
++++ new/gcc/config/arm/arm.md	2011-01-05 11:42:19 +0000
+@@ -1791,11 +1791,11 @@
+ 
+ (define_insn "maddhisi4"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+-	(plus:SI (match_operand:SI 3 "s_register_operand" "r")
+-		 (mult:SI (sign_extend:SI
+-			   (match_operand:HI 1 "s_register_operand" "%r"))
++	(plus:SI (mult:SI (sign_extend:SI
++			   (match_operand:HI 1 "s_register_operand" "r"))
+ 			  (sign_extend:SI
+-			   (match_operand:HI 2 "s_register_operand" "r")))))]
++			   (match_operand:HI 2 "s_register_operand" "r")))
++		 (match_operand:SI 3 "s_register_operand" "r")))]
+   "TARGET_DSP_MULTIPLY"
+   "smlabb%?\\t%0, %1, %2, %3"
+   [(set_attr "insn" "smlaxy")
+@@ -1805,11 +1805,11 @@
+ (define_insn "*maddhidi4"
+   [(set (match_operand:DI 0 "s_register_operand" "=r")
+ 	(plus:DI
+-	  (match_operand:DI 3 "s_register_operand" "0")
+ 	  (mult:DI (sign_extend:DI
+-	 	    (match_operand:HI 1 "s_register_operand" "%r"))
++	 	    (match_operand:HI 1 "s_register_operand" "r"))
+ 		   (sign_extend:DI
+-		    (match_operand:HI 2 "s_register_operand" "r")))))]
++		    (match_operand:HI 2 "s_register_operand" "r")))
++	  (match_operand:DI 3 "s_register_operand" "0")))]
+   "TARGET_DSP_MULTIPLY"
+   "smlalbb%?\\t%Q0, %R0, %1, %2"
+   [(set_attr "insn" "smlalxy")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99455.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99455.patch
new file mode 100644
index 0000000000..5e8383a7d9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99455.patch
@@ -0,0 +1,65 @@
+2010-12-21  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Issue #10201
+
+	Backport from mainline:
+
+	2010-12-16  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	PR target/46883
+	gcc/
+	* config/arm/arm.md
+	(zero_extendhisi2 for register input splitter): Change
+	"register_operand" to "s_register_operand".
+	(zero_extendqisi2 for register input splitter): Same.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr46883.c: New testcase.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-01-05 11:42:19 +0000
++++ new/gcc/config/arm/arm.md	2011-01-05 11:52:16 +0000
+@@ -4114,8 +4114,8 @@
+ })
+ 
+ (define_split
+-  [(set (match_operand:SI 0 "register_operand" "")
+-	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(zero_extend:SI (match_operand:HI 1 "s_register_operand" "")))]
+   "!TARGET_THUMB2 && !arm_arch6"
+   [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
+    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
+@@ -4234,8 +4234,8 @@
+ })
+ 
+ (define_split
+-  [(set (match_operand:SI 0 "register_operand" "")
+-	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(zero_extend:SI (match_operand:QI 1 "s_register_operand" "")))]
+   "!arm_arch6"
+   [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
+    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr46883.c'
+--- old/gcc/testsuite/gcc.target/arm/pr46883.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr46883.c	2011-01-05 11:52:16 +0000
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++/* { dg-options "-O1 -march=armv5te" } */
++
++void bar (unsigned char *q, unsigned short *data16s, int len)
++{
++  int i;
++
++  for (i = 0; i < len; i++)
++    {
++      q[2 * i] =
++        (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF)) & 0xFF;
++      q[2 * i + 1] =
++        ((unsigned short)
++         (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF))) >> 8;
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch
new file mode 100644
index 0000000000..35f98d24ab
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch
@@ -0,0 +1,3163 @@
+2011-01-03  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* doc/tm.texi (RETURN_ADDR_REGNUM): Document.
+	* doc/md.texi (simple_return): Document pattern.
+	(return): Add a sentence to clarify.
+	* doc/rtl.texi (simple_return): Document.
+	* doc/invoke.texi (Optimize Options): Document -fshrink-wrap.
+	* common.opt (fshrink-wrap): New.
+	* opts.c (decode_options): Set it for -O2 and above.
+	* gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN
+	are special.
+	* rtl.h (ANY_RETURN_P): New macro.
+	(global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN.
+	(ret_rtx, simple_return_rtx): New macros.
+	* genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs.
+	(gen_expand, gen_split): Use ANY_RETURN_P.
+	* rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared.
+	* emit-rtl.c (verify_rtx_sharing): Likewise.
+	(skip_consecutive_labels): Return the argument if it is a return rtx.
+	(classify_insn): Handle both kinds of return.
+	(init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx.
+	* df-scan.c (df_uses_record): Handle SIMPLE_RETURN.
+	* rtl.def (SIMPLE_RETURN): New.
+	* rtlanal.c (tablejump_p): Check JUMP_LABEL for returns.
+	* final.c (final_scan_insn): Recognize both kinds of return.
+	* reorg.c (function_return_label, function_simple_return_label): New
+	static variables.
+	(end_of_function_label): Remove.
+	(simplejump_or_return_p): New static function.
+	(find_end_label): Add a new arg, KIND.  All callers changed.
+	Depending on KIND, look for a label suitable for return or
+	simple_return.
+	(make_return_insns): Make corresponding changes.
+	(get_jump_flags): Check JUMP_LABELs for returns.
+	(follow_jumps): Likewise.
+	(get_branch_condition): Check target for return patterns rather
+	than NULL.
+	(own_thread_p): Likewise for thread.
+	(steal_delay_list_from_target): Check JUMP_LABELs for returns.
+	Use simplejump_or_return_p.
+	(fill_simple_delay_slots): Likewise.
+	(optimize_skip): Likewise.
+	(fill_slots_from_thread): Likewise.
+	(relax_delay_slots): Likewise.
+	(dbr_schedule): Adjust handling of end_of_function_label for the
+	two new variables.
+	* ifcvt.c (find_if_case_1): Take care when redirecting jumps to the
+	exit block.
+	(dead_or_predicable): Change NEW_DEST arg to DEST_EDGE.  All callers
+	changed.  Ensure that the right label is passed to redirect_jump.
+	* jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p,
+	returnjump_p): Handle SIMPLE_RETURNs.
+	(delete_related_insns): Check JUMP_LABEL for returns.
+	(redirect_target): New static function.
+	(redirect_exp_1): Use it.  Handle any kind of return rtx as a label
+	rather than interpreting NULL as a return.
+	(redirect_jump_1): Assert that nlabel is not NULL.
+	(redirect_jump): Likewise.
+	(redirect_jump_2): Handle any kind of return rtx as a label rather
+	than interpreting NULL as a return.
+	* dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for
+	returns.
+	* function.c (emit_return_into_block): Remove useless declaration.
+	(record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern,
+	requires_stack_frame_p): New static functions.
+	(emit_return_into_block): New arg SIMPLE_P.  All callers changed.
+	Generate either kind of return pattern and update the JUMP_LABEL.
+	(thread_prologue_and_epilogue_insns): Implement a form of
+	shrink-wrapping.  Ensure JUMP_LABELs for return insns are set.
+	* print-rtl.c (print_rtx): Handle returns in JUMP_LABELs.
+	* cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns
+	remain correct.
+	* resource.c (find_dead_or_set_registers): Check JUMP_LABELs for
+	returns.
+	(mark_target_live_regs): Don't pass a return rtx to next_active_insn.
+	* basic-block.h (force_nonfallthru_and_redirect): Declare.
+	* sched-vis.c (print_pattern): Add case for SIMPLE_RETURN.
+	* cfgrtl.c (force_nonfallthru_and_redirect): No longer static.  New arg
+	JUMP_LABEL.  All callers changed.  Use the label when generating
+	return insns.
+
+	* config/i386/i386.md (returns, return_str, return_cond): New
+	code_iterator and corresponding code_attrs.
+	(<return_str>return): Renamed from return and adapted.
+	(<return_str>return_internal): Likewise for return_internal.
+	(<return_str>return_internal_long): Likewise for return_internal_long.
+	(<return_str>return_pop_internal): Likewise for return_pop_internal.
+	(<return_str>return_indirect_internal): Likewise for
+	return_indirect_internal.
+	* config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as
+	the last insn.
+	(ix86_pad_returns): Handle both kinds of return rtx.
+	* config/arm/arm.c (use_simple_return_p): new function.
+	(is_jump_table): Handle returns in JUMP_LABELs.
+	(output_return_instruction): New arg SIMPLE.  All callers changed.
+	Use it to determine which kind of return to generate.
+	(arm_final_prescan_insn): Handle both kinds of return.
+	* config/arm/arm.md (returns, return_str, return_simple_p,
+	return_cond): New code_iterator and corresponding code_attrs.
+	(<return_str>return): Renamed from return and adapted.
+	(arm_<return_str>return): Renamed from arm_return and adapted.
+	(cond_<return_str>return): Renamed from cond_return and adapted.
+	(cond_<return_str>return_inverted): Renamed from cond_return_inverted
+	and adapted.
+	(epilogue): Use ret_rtx instead of gen_rtx_RETURN.
+	* config/arm/thumb2.md (thumb2_<return_str>return): Renamed from
+	thumb2_return and adapted.
+	* config/arm/arm.h (RETURN_ADDR_REGNUM): Define.
+	* config/arm/arm-protos.h (use_simple_return_p): Declare.
+	(output_return_instruction): Adjust declaration.
+	* config/mips/mips.c (mips_expand_epilogue): Generate a simple_return
+	as final insn.
+	* config/mips/mips.md (simple_return): New expander.
+	(*simple_return, simple_return_internal): New patterns.
+	* config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL.
+	(split_branches): Don't pass a null label to redirect_jump.
+
+	From mainline:
+	* vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros.
+	* haifa-sched.c (find_fallthru_edge_from): Rename from
+	find_fallthru_edge.  All callers changed.
+	* sched-int.h (find_fallthru_edge_from): Rename declaration as well.
+	* basic-block.h (find_fallthru_edge): New inline function.
+
+=== modified file 'gcc/basic-block.h'
+--- old/gcc/basic-block.h	2010-09-01 13:29:58 +0000
++++ new/gcc/basic-block.h	2011-01-05 12:12:18 +0000
+@@ -884,6 +884,7 @@
+ 
+ /* In cfgrtl.c  */
+ extern basic_block force_nonfallthru (edge);
++extern basic_block force_nonfallthru_and_redirect (edge, basic_block, rtx);
+ extern rtx block_label (basic_block);
+ extern bool purge_all_dead_edges (void);
+ extern bool purge_dead_edges (basic_block);
+@@ -1004,6 +1005,20 @@
+   return false;
+ }
+ 
++/* Return the fallthru edge in EDGES if it exists, NULL otherwise.  */
++static inline edge
++find_fallthru_edge (VEC(edge,gc) *edges)
++{
++  edge e;
++  edge_iterator ei;
++
++  FOR_EACH_EDGE (e, ei, edges)
++    if (e->flags & EDGE_FALLTHRU)
++      break;
++
++  return e;
++}
++
+ /* In cfgloopmanip.c.  */
+ extern edge mfb_kj_edge;
+ extern bool mfb_keep_just (edge);
+
+=== modified file 'gcc/cfganal.c'
+--- old/gcc/cfganal.c	2009-11-25 10:55:54 +0000
++++ new/gcc/cfganal.c	2011-01-05 12:12:18 +0000
+@@ -271,6 +271,37 @@
+       EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU;
+       EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU;
+     }
++  /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired
++     with a return or a sibcall.  Ensure that this remains the case if
++     they are in different basic blocks.  */
++  FOR_EACH_BB (bb)
++    {
++      edge e;
++      edge_iterator ei;
++      rtx insn, end;
++
++      end = BB_END (bb);
++      FOR_BB_INSNS (bb, insn)
++	if (GET_CODE (insn) == NOTE
++	    && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG
++	    && !(CALL_P (end) && SIBLING_CALL_P (end))
++	    && !returnjump_p (end))
++	  {
++	    basic_block other_bb = NULL;
++	    FOR_EACH_EDGE (e, ei, bb->succs)
++	      {
++		if (e->flags & EDGE_FALLTHRU)
++		  other_bb = e->dest;
++		else
++		  e->flags &= ~EDGE_CAN_FALLTHRU;
++	      }
++	    FOR_EACH_EDGE (e, ei, other_bb->preds)
++	      {
++		if (!(e->flags & EDGE_FALLTHRU))
++		  e->flags &= ~EDGE_CAN_FALLTHRU;
++	      }	    
++	  }
++    }
+ }
+ 
+ /* Find unreachable blocks.  An unreachable block will have 0 in
+
+=== modified file 'gcc/cfglayout.c'
+--- old/gcc/cfglayout.c	2010-05-17 16:30:54 +0000
++++ new/gcc/cfglayout.c	2011-01-05 12:12:18 +0000
+@@ -766,6 +766,7 @@
+     {
+       edge e_fall, e_taken, e;
+       rtx bb_end_insn;
++      rtx ret_label = NULL_RTX;
+       basic_block nb;
+       edge_iterator ei;
+ 
+@@ -785,6 +786,7 @@
+       bb_end_insn = BB_END (bb);
+       if (JUMP_P (bb_end_insn))
+ 	{
++	  ret_label = JUMP_LABEL (bb_end_insn);
+ 	  if (any_condjump_p (bb_end_insn))
+ 	    {
+ 	      /* This might happen if the conditional jump has side
+@@ -899,7 +901,7 @@
+ 	}
+ 
+       /* We got here if we need to add a new jump insn.  */
+-      nb = force_nonfallthru (e_fall);
++      nb = force_nonfallthru_and_redirect (e_fall, e_fall->dest, ret_label);
+       if (nb)
+ 	{
+ 	  nb->il.rtl->visited = 1;
+@@ -1118,24 +1120,30 @@
+ bool
+ cfg_layout_can_duplicate_bb_p (const_basic_block bb)
+ {
++  rtx insn;
++
+   /* Do not attempt to duplicate tablejumps, as we need to unshare
+      the dispatch table.  This is difficult to do, as the instructions
+      computing jump destination may be hoisted outside the basic block.  */
+   if (tablejump_p (BB_END (bb), NULL, NULL))
+     return false;
+ 
+-  /* Do not duplicate blocks containing insns that can't be copied.  */
+-  if (targetm.cannot_copy_insn_p)
++  insn = BB_HEAD (bb);
++  while (1)
+     {
+-      rtx insn = BB_HEAD (bb);
+-      while (1)
+-	{
+-	  if (INSN_P (insn) && targetm.cannot_copy_insn_p (insn))
+-	    return false;
+-	  if (insn == BB_END (bb))
+-	    break;
+-	  insn = NEXT_INSN (insn);
+-	}
++      /* Do not duplicate blocks containing insns that can't be copied.  */
++      if (INSN_P (insn) && targetm.cannot_copy_insn_p
++	  && targetm.cannot_copy_insn_p (insn))
++	return false;
++      /* dwarf2out expects that these notes are always paired with a
++	 returnjump or sibling call.  */
++      if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG
++	  && !returnjump_p (BB_END (bb))
++	  && (!CALL_P (BB_END (bb)) || !SIBLING_CALL_P (BB_END (bb))))
++	return false;
++      if (insn == BB_END (bb))
++	break;
++      insn = NEXT_INSN (insn);
+     }
+ 
+   return true;
+@@ -1167,6 +1175,9 @@
+ 	      || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
+ 	    break;
+ 	  copy = emit_copy_of_insn_after (insn, get_last_insn ());
++	  if (JUMP_P (insn) && JUMP_LABEL (insn) != NULL_RTX
++	      && ANY_RETURN_P (JUMP_LABEL (insn)))
++	    JUMP_LABEL (copy) = JUMP_LABEL (insn);
+           maybe_copy_epilogue_insn (insn, copy);
+ 	  break;
+ 
+
+=== modified file 'gcc/cfgrtl.c'
+--- old/gcc/cfgrtl.c	2010-09-20 21:30:35 +0000
++++ new/gcc/cfgrtl.c	2011-01-05 12:12:18 +0000
+@@ -1107,10 +1107,13 @@
+ }
+ 
+ /* Like force_nonfallthru below, but additionally performs redirection
+-   Used by redirect_edge_and_branch_force.  */
++   Used by redirect_edge_and_branch_force.  JUMP_LABEL is used only
++   when redirecting to the EXIT_BLOCK, it is either a return or a
++   simple_return rtx indicating which kind of returnjump to create.
++   It should be NULL otherwise.  */
+ 
+-static basic_block
+-force_nonfallthru_and_redirect (edge e, basic_block target)
++basic_block
++force_nonfallthru_and_redirect (edge e, basic_block target, rtx jump_label)
+ {
+   basic_block jump_block, new_bb = NULL, src = e->src;
+   rtx note;
+@@ -1242,11 +1245,25 @@
+   e->flags &= ~EDGE_FALLTHRU;
+   if (target == EXIT_BLOCK_PTR)
+     {
++      if (jump_label == ret_rtx)
++	{
+ #ifdef HAVE_return
+-	emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), loc);
+-#else
+-	gcc_unreachable ();
+-#endif
++	  emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block),
++				       loc);
++#else
++	  gcc_unreachable ();
++#endif
++	}
++      else
++	{
++	  gcc_assert (jump_label == simple_return_rtx);
++#ifdef HAVE_simple_return
++	  emit_jump_insn_after_setloc (gen_simple_return (),
++				       BB_END (jump_block), loc);
++#else
++	  gcc_unreachable ();
++#endif
++	}
+     }
+   else
+     {
+@@ -1273,7 +1290,7 @@
+ basic_block
+ force_nonfallthru (edge e)
+ {
+-  return force_nonfallthru_and_redirect (e, e->dest);
++  return force_nonfallthru_and_redirect (e, e->dest, NULL_RTX);
+ }
+ 
+ /* Redirect edge even at the expense of creating new jump insn or
+@@ -1290,7 +1307,7 @@
+   /* In case the edge redirection failed, try to force it to be non-fallthru
+      and redirect newly created simplejump.  */
+   df_set_bb_dirty (e->src);
+-  return force_nonfallthru_and_redirect (e, target);
++  return force_nonfallthru_and_redirect (e, target, NULL_RTX);
+ }
+ 
+ /* The given edge should potentially be a fallthru edge.  If that is in
+
+=== modified file 'gcc/common.opt'
+--- old/gcc/common.opt	2010-12-10 15:33:37 +0000
++++ new/gcc/common.opt	2011-01-05 12:12:18 +0000
+@@ -1147,6 +1147,11 @@
+ Common C ObjC C++ ObjC++ Report Var(flag_show_column) Init(1)
+ Show column numbers in diagnostics, when available.  Default on
+ 
++fshrink-wrap
++Common Report Var(flag_shrink_wrap) Optimization
++Emit function prologues only before parts of the function that need it,
++rather than at the top of the function.
++
+ fsignaling-nans
+ Common Report Var(flag_signaling_nans) Optimization
+ Disable optimizations observable by IEEE signaling NaNs
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-01-05 12:12:18 +0000
+@@ -26,6 +26,7 @@
+ extern void arm_override_options (void);
+ extern void arm_optimization_options (int, int);
+ extern int use_return_insn (int, rtx);
++extern bool use_simple_return_p (void);
+ extern enum reg_class arm_regno_class (int);
+ extern void arm_load_pic_register (unsigned long);
+ extern int arm_volatile_func (void);
+@@ -137,7 +138,7 @@
+ extern const char *output_add_immediate (rtx *);
+ extern const char *arithmetic_instr (rtx, int);
+ extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
+-extern const char *output_return_instruction (rtx, int, int);
++extern const char *output_return_instruction (rtx, bool, bool, bool);
+ extern void arm_poke_function_name (FILE *, const char *);
+ extern void arm_print_operand (FILE *, rtx, int);
+ extern void arm_print_operand_address (FILE *, rtx);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-01-05 11:32:50 +0000
++++ new/gcc/config/arm/arm.c	2011-01-05 12:12:18 +0000
+@@ -2163,6 +2163,18 @@
+   return addr;
+ }
+ 
++/* Return true if we should try to use a simple_return insn, i.e. perform
++   shrink-wrapping if possible.  This is the case if we need to emit a
++   prologue, which we can test by looking at the offsets.  */
++bool
++use_simple_return_p (void)
++{
++  arm_stack_offsets *offsets;
++
++  offsets = arm_get_frame_offsets ();
++  return offsets->outgoing_args != 0;
++}
++
+ /* Return 1 if it is possible to return using a single instruction.
+    If SIBLING is non-null, this is a test for a return before a sibling
+    call.  SIBLING is the call insn, so we can examine its register usage.  */
+@@ -11284,6 +11296,7 @@
+ 
+   if (GET_CODE (insn) == JUMP_INSN
+       && JUMP_LABEL (insn) != NULL
++      && !ANY_RETURN_P (JUMP_LABEL (insn))
+       && ((table = next_real_insn (JUMP_LABEL (insn)))
+ 	  == next_real_insn (insn))
+       && table != NULL
+@@ -14168,7 +14181,7 @@
+ /* Generate a function exit sequence.  If REALLY_RETURN is false, then do
+    everything bar the final return instruction.  */
+ const char *
+-output_return_instruction (rtx operand, int really_return, int reverse)
++output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple)
+ {
+   char conditional[10];
+   char instr[100];
+@@ -14206,10 +14219,15 @@
+ 
+   sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
+ 
+-  cfun->machine->return_used_this_function = 1;
++  if (simple)
++    live_regs_mask = 0;
++  else
++    {
++      cfun->machine->return_used_this_function = 1;
+ 
+-  offsets = arm_get_frame_offsets ();
+-  live_regs_mask = offsets->saved_regs_mask;
++      offsets = arm_get_frame_offsets ();
++      live_regs_mask = offsets->saved_regs_mask;
++    }
+ 
+   if (live_regs_mask)
+     {
+@@ -17108,6 +17126,7 @@
+ 
+   /* If we start with a return insn, we only succeed if we find another one.  */
+   int seeking_return = 0;
++  enum rtx_code return_code = UNKNOWN;
+ 
+   /* START_INSN will hold the insn from where we start looking.  This is the
+      first insn after the following code_label if REVERSE is true.  */
+@@ -17146,7 +17165,7 @@
+ 	  else
+ 	    return;
+ 	}
+-      else if (GET_CODE (body) == RETURN)
++      else if (ANY_RETURN_P (body))
+         {
+ 	  start_insn = next_nonnote_insn (start_insn);
+ 	  if (GET_CODE (start_insn) == BARRIER)
+@@ -17157,6 +17176,7 @@
+ 	    {
+ 	      reverse = TRUE;
+ 	      seeking_return = 1;
++	      return_code = GET_CODE (body);
+ 	    }
+ 	  else
+ 	    return;
+@@ -17197,11 +17217,15 @@
+ 	  label = XEXP (XEXP (SET_SRC (body), 2), 0);
+ 	  then_not_else = FALSE;
+ 	}
+-      else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
+-	seeking_return = 1;
+-      else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
++      else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1)))
++	{
++	  seeking_return = 1;
++	  return_code = GET_CODE (XEXP (SET_SRC (body), 1));
++	}
++      else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2)))
+         {
+ 	  seeking_return = 1;
++	  return_code = GET_CODE (XEXP (SET_SRC (body), 2));
+ 	  then_not_else = FALSE;
+         }
+       else
+@@ -17302,8 +17326,7 @@
+ 		       && !use_return_insn (TRUE, NULL)
+ 		       && !optimize_size)
+ 		fail = TRUE;
+-	      else if (GET_CODE (scanbody) == RETURN
+-		       && seeking_return)
++	      else if (GET_CODE (scanbody) == return_code)
+ 	        {
+ 		  arm_ccfsm_state = 2;
+ 		  succeed = TRUE;
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2010-11-11 11:12:14 +0000
++++ new/gcc/config/arm/arm.h	2011-01-05 12:12:18 +0000
+@@ -2622,6 +2622,8 @@
+ #define RETURN_ADDR_RTX(COUNT, FRAME) \
+   arm_return_addr (COUNT, FRAME)
+ 
++#define RETURN_ADDR_REGNUM LR_REGNUM
++
+ /* Mask of the bits in the PC that contain the real return address
+    when running in 26-bit mode.  */
+ #define RETURN_ADDR_MASK26 (0x03fffffc)
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-01-05 11:52:16 +0000
++++ new/gcc/config/arm/arm.md	2011-01-05 12:12:18 +0000
+@@ -8882,66 +8882,72 @@
+   [(set_attr "type" "call")]
+ )
+ 
+-(define_expand "return"
+-  [(return)]
+-  "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
++;; Both kinds of return insn.
++(define_code_iterator returns [return simple_return])
++(define_code_attr return_str [(return "") (simple_return "simple_")])
++(define_code_attr return_simple_p [(return "false") (simple_return "true")])
++(define_code_attr return_cond [(return " && USE_RETURN_INSN (FALSE)")
++			       (simple_return " && use_simple_return_p ()")])
++
++(define_expand "<return_str>return"
++  [(returns)]
++  "TARGET_32BIT<return_cond>"
+   "")
+ 
+-;; Often the return insn will be the same as loading from memory, so set attr
+-(define_insn "*arm_return"
+-  [(return)]
+-  "TARGET_ARM && USE_RETURN_INSN (FALSE)"
+-  "*
+-  {
+-    if (arm_ccfsm_state == 2)
+-      {
+-        arm_ccfsm_state += 2;
+-        return \"\";
+-      }
+-    return output_return_instruction (const_true_rtx, TRUE, FALSE);
+-  }"
++(define_insn "*arm_<return_str>return"
++  [(returns)]
++  "TARGET_ARM<return_cond>"
++{
++  if (arm_ccfsm_state == 2)
++    {
++      arm_ccfsm_state += 2;
++      return "";
++    }
++  return output_return_instruction (const_true_rtx, true, false,
++				    <return_simple_p>);
++}
+   [(set_attr "type" "load1")
+    (set_attr "length" "12")
+    (set_attr "predicable" "yes")]
+ )
+ 
+-(define_insn "*cond_return"
++(define_insn "*cond_<return_str>return"
+   [(set (pc)
+         (if_then_else (match_operator 0 "arm_comparison_operator"
+ 		       [(match_operand 1 "cc_register" "") (const_int 0)])
+-                      (return)
++                      (returns)
+                       (pc)))]
+-  "TARGET_ARM && USE_RETURN_INSN (TRUE)"
+-  "*
+-  {
+-    if (arm_ccfsm_state == 2)
+-      {
+-        arm_ccfsm_state += 2;
+-        return \"\";
+-      }
+-    return output_return_instruction (operands[0], TRUE, FALSE);
+-  }"
++  "TARGET_ARM<return_cond>"
++{
++  if (arm_ccfsm_state == 2)
++    {
++      arm_ccfsm_state += 2;
++      return "";
++    }
++  return output_return_instruction (operands[0], true, false,
++				    <return_simple_p>);
++}
+   [(set_attr "conds" "use")
+    (set_attr "length" "12")
+    (set_attr "type" "load1")]
+ )
+ 
+-(define_insn "*cond_return_inverted"
++(define_insn "*cond_<return_str>return_inverted"
+   [(set (pc)
+         (if_then_else (match_operator 0 "arm_comparison_operator"
+ 		       [(match_operand 1 "cc_register" "") (const_int 0)])
+                       (pc)
+-		      (return)))]
+-  "TARGET_ARM && USE_RETURN_INSN (TRUE)"
+-  "*
+-  {
+-    if (arm_ccfsm_state == 2)
+-      {
+-        arm_ccfsm_state += 2;
+-        return \"\";
+-      }
+-    return output_return_instruction (operands[0], TRUE, TRUE);
+-  }"
++		      (returns)))]
++  "TARGET_ARM<return_cond>"
++{
++  if (arm_ccfsm_state == 2)
++    {
++      arm_ccfsm_state += 2;
++      return "";
++    }
++  return output_return_instruction (operands[0], true, true,
++				    <return_simple_p>);
++}
+   [(set_attr "conds" "use")
+    (set_attr "length" "12")
+    (set_attr "type" "load1")]
+@@ -10809,8 +10815,7 @@
+       DONE;
+     }
+   emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
+-	gen_rtvec (1,
+-		gen_rtx_RETURN (VOIDmode)),
++	gen_rtvec (1, ret_rtx),
+ 	VUNSPEC_EPILOGUE));
+   DONE;
+   "
+@@ -10827,7 +10832,7 @@
+   "TARGET_32BIT"
+   "*
+   if (use_return_insn (FALSE, next_nonnote_insn (insn)))
+-    return output_return_instruction (const_true_rtx, FALSE, FALSE);
++    return output_return_instruction (const_true_rtx, false, false, false);
+   return arm_output_epilogue (next_nonnote_insn (insn));
+   "
+ ;; Length is absolute worst case
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2010-09-22 05:54:42 +0000
++++ new/gcc/config/arm/thumb2.md	2011-01-05 12:12:18 +0000
+@@ -1020,16 +1020,15 @@
+ 
+ ;; Note: this is not predicable, to avoid issues with linker-generated
+ ;; interworking stubs.
+-(define_insn "*thumb2_return"
+-  [(return)]
+-  "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
+-  "*
+-  {
+-    return output_return_instruction (const_true_rtx, TRUE, FALSE);
+-  }"
++(define_insn "*thumb2_<return_str>return"
++  [(returns)]
++  "TARGET_THUMB2<return_cond>"
++{
++  return output_return_instruction (const_true_rtx, true, false,
++				    <return_simple_p>);
++}
+   [(set_attr "type" "load1")
+-   (set_attr "length" "12")]
+-)
++   (set_attr "length" "12")])
+ 
+ (define_insn_and_split "thumb2_eh_return"
+   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
+
+=== modified file 'gcc/config/i386/i386.c'
+--- old/gcc/config/i386/i386.c	2010-11-16 18:05:53 +0000
++++ new/gcc/config/i386/i386.c	2011-01-05 12:12:18 +0000
+@@ -9308,13 +9308,13 @@
+ 
+ 	  pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
+ 				     popc, -1, true);
+-	  emit_jump_insn (gen_return_indirect_internal (ecx));
++	  emit_jump_insn (gen_simple_return_indirect_internal (ecx));
+ 	}
+       else
+-	emit_jump_insn (gen_return_pop_internal (popc));
++	emit_jump_insn (gen_simple_return_pop_internal (popc));
+     }
+   else
+-    emit_jump_insn (gen_return_internal ());
++    emit_jump_insn (gen_simple_return_internal ());
+ 
+   /* Restore the state back to the state from the prologue,
+      so that it's correct for the next epilogue.  */
+@@ -26596,7 +26596,7 @@
+       rtx prev;
+       bool replace = false;
+ 
+-      if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
++      if (!JUMP_P (ret) || !ANY_RETURN_P (PATTERN (ret))
+ 	  || optimize_bb_for_size_p (bb))
+ 	continue;
+       for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
+@@ -26626,7 +26626,10 @@
+ 	}
+       if (replace)
+ 	{
+-	  emit_jump_insn_before (gen_return_internal_long (), ret);
++	  if (PATTERN (ret) == ret_rtx)
++	    emit_jump_insn_before (gen_return_internal_long (), ret);
++	  else
++	    emit_jump_insn_before (gen_simple_return_internal_long (), ret);
+ 	  delete_insn (ret);
+ 	}
+     }
+
+=== modified file 'gcc/config/i386/i386.md'
+--- old/gcc/config/i386/i386.md	2010-11-27 15:24:12 +0000
++++ new/gcc/config/i386/i386.md	2011-01-05 12:12:18 +0000
+@@ -13797,24 +13797,29 @@
+   ""
+   [(set_attr "length" "0")])
+ 
++(define_code_iterator returns [return simple_return])
++(define_code_attr return_str [(return "") (simple_return "simple_")])
++(define_code_attr return_cond [(return "ix86_can_use_return_insn_p ()")
++			       (simple_return "")])
++
+ ;; Insn emitted into the body of a function to return from a function.
+ ;; This is only done if the function's epilogue is known to be simple.
+ ;; See comments for ix86_can_use_return_insn_p in i386.c.
+ 
+-(define_expand "return"
+-  [(return)]
+-  "ix86_can_use_return_insn_p ()"
++(define_expand "<return_str>return"
++  [(returns)]
++  "<return_cond>"
+ {
+   if (crtl->args.pops_args)
+     {
+       rtx popc = GEN_INT (crtl->args.pops_args);
+-      emit_jump_insn (gen_return_pop_internal (popc));
++      emit_jump_insn (gen_<return_str>return_pop_internal (popc));
+       DONE;
+     }
+ })
+ 
+-(define_insn "return_internal"
+-  [(return)]
++(define_insn "<return_str>return_internal"
++  [(returns)]
+   "reload_completed"
+   "ret"
+   [(set_attr "length" "1")
+@@ -13825,8 +13830,8 @@
+ ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
+ ;; instruction Athlon and K8 have.
+ 
+-(define_insn "return_internal_long"
+-  [(return)
++(define_insn "<return_str>return_internal_long"
++  [(returns)
+    (unspec [(const_int 0)] UNSPEC_REP)]
+   "reload_completed"
+   "rep\;ret"
+@@ -13836,8 +13841,8 @@
+    (set_attr "prefix_rep" "1")
+    (set_attr "modrm" "0")])
+ 
+-(define_insn "return_pop_internal"
+-  [(return)
++(define_insn "<return_str>return_pop_internal"
++  [(returns)
+    (use (match_operand:SI 0 "const_int_operand" ""))]
+   "reload_completed"
+   "ret\t%0"
+@@ -13846,8 +13851,8 @@
+    (set_attr "length_immediate" "2")
+    (set_attr "modrm" "0")])
+ 
+-(define_insn "return_indirect_internal"
+-  [(return)
++(define_insn "<return_str>return_indirect_internal"
++  [(returns)
+    (use (match_operand:SI 0 "register_operand" "r"))]
+   "reload_completed"
+   "jmp\t%A0"
+
+=== modified file 'gcc/config/mips/mips.c'
+--- old/gcc/config/mips/mips.c	2010-11-21 10:38:43 +0000
++++ new/gcc/config/mips/mips.c	2011-01-05 12:12:18 +0000
+@@ -10497,7 +10497,8 @@
+ 	    regno = GP_REG_FIRST + 7;
+ 	  else
+ 	    regno = RETURN_ADDR_REGNUM;
+-	  emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
++	  emit_jump_insn (gen_simple_return_internal (gen_rtx_REG (Pmode,
++								   regno)));
+ 	}
+     }
+ 
+
+=== modified file 'gcc/config/mips/mips.md'
+--- old/gcc/config/mips/mips.md	2010-04-02 18:54:46 +0000
++++ new/gcc/config/mips/mips.md	2011-01-05 12:12:18 +0000
+@@ -5815,6 +5815,18 @@
+   [(set_attr "type"	"jump")
+    (set_attr "mode"	"none")])
+ 
++(define_expand "simple_return"
++  [(simple_return)]
++  "!mips_can_use_return_insn ()"
++  { mips_expand_before_return (); })
++
++(define_insn "*simple_return"
++  [(simple_return)]
++  "!mips_can_use_return_insn ()"
++  "%*j\t$31%/"
++  [(set_attr "type"	"jump")
++   (set_attr "mode"	"none")])
++
+ ;; Normal return.
+ 
+ (define_insn "return_internal"
+@@ -5825,6 +5837,14 @@
+   [(set_attr "type"	"jump")
+    (set_attr "mode"	"none")])
+ 
++(define_insn "simple_return_internal"
++  [(simple_return)
++   (use (match_operand 0 "pmode_register_operand" ""))]
++  ""
++  "%*j\t%0%/"
++  [(set_attr "type"	"jump")
++   (set_attr "mode"	"none")])
++
+ ;; Exception return.
+ (define_insn "mips_eret"
+   [(return)
+
+=== modified file 'gcc/config/sh/sh.c'
+--- old/gcc/config/sh/sh.c	2010-12-10 15:34:19 +0000
++++ new/gcc/config/sh/sh.c	2011-01-05 12:12:18 +0000
+@@ -5252,7 +5252,8 @@
+ 	}
+       if (prev
+ 	  && JUMP_P (prev)
+-	  && JUMP_LABEL (prev))
++	  && JUMP_LABEL (prev)
++	  && !ANY_RETURN_P (JUMP_LABEL (prev)))
+ 	{
+ 	  rtx x;
+ 	  if (jump_to_next
+@@ -5951,7 +5952,7 @@
+ 			JUMP_LABEL (insn) = far_label;
+ 			LABEL_NUSES (far_label)++;
+ 		      }
+-		    redirect_jump (insn, NULL_RTX, 1);
++		    redirect_jump (insn, ret_rtx, 1);
+ 		    far_label = 0;
+ 		  }
+ 	      }
+
+=== modified file 'gcc/df-scan.c'
+--- old/gcc/df-scan.c	2010-11-16 22:17:17 +0000
++++ new/gcc/df-scan.c	2011-01-05 12:12:18 +0000
+@@ -3296,6 +3296,7 @@
+       }
+ 
+     case RETURN:
++    case SIMPLE_RETURN:
+       break;
+ 
+     case ASM_OPERANDS:
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2010-11-04 14:29:09 +0000
++++ new/gcc/doc/invoke.texi	2011-01-05 12:12:18 +0000
+@@ -5750,6 +5750,7 @@
+ -fipa-pure-const @gol
+ -fipa-reference @gol
+ -fmerge-constants
++-fshrink-wrap @gol
+ -fsplit-wide-types @gol
+ -ftree-builtin-call-dce @gol
+ -ftree-ccp @gol
+@@ -6504,6 +6505,12 @@
+ When pipelining loops during selective scheduling, also pipeline outer loops.
+ This option has no effect until @option{-fsel-sched-pipelining} is turned on.
+ 
++@item -fshrink-wrap
++@opindex fshrink-wrap
++Emit function prologues only before parts of the function that need it,
++rather than at the top of the function.  This flag is enabled by default at
++@option{-O} and higher.
++
+ @item -fcaller-saves
+ @opindex fcaller-saves
+ Enable values to be allocated in registers that will be clobbered by
+
+=== modified file 'gcc/doc/md.texi'
+--- old/gcc/doc/md.texi	2009-12-15 18:36:44 +0000
++++ new/gcc/doc/md.texi	2011-01-05 12:12:18 +0000
+@@ -4801,7 +4801,19 @@
+ multiple instructions are usually needed to return from a function, but
+ some class of functions only requires one instruction to implement a
+ return.  Normally, the applicable functions are those which do not need
+-to save any registers or allocate stack space.
++to save any registers or allocate stack space, although some targets
++have instructions that can perform both the epilogue and function return
++in one instruction.
++
++@cindex @code{simple_return} instruction pattern
++@item @samp{simple_return}
++Subroutine return instruction.  This instruction pattern name should be
++defined only if a single instruction can do all the work of returning
++from a function on a path where no epilogue is required.  This pattern
++is very similar to the @code{return} instruction pattern, but it is emitted
++only by the shrink-wrapping optimization on paths where the function
++prologue has not been executed, and a function return should occur without
++any of the effects of the epilogue.
+ 
+ @findex reload_completed
+ @findex leaf_function_p
+
+=== modified file 'gcc/doc/rtl.texi'
+--- old/gcc/doc/rtl.texi	2010-07-06 19:23:53 +0000
++++ new/gcc/doc/rtl.texi	2011-01-05 12:12:18 +0000
+@@ -2888,6 +2888,13 @@
+ Note that an insn pattern of @code{(return)} is logically equivalent to
+ @code{(set (pc) (return))}, but the latter form is never used.
+ 
++@findex simple_return
++@item (simple_return)
++Like @code{(return)}, but truly represents only a function return, while
++@code{(return)} may represent an insn that also performs other functions
++of the function epilogue.  Like @code{(return)}, this may also occur in
++conditional jumps.
++
+ @findex call
+ @item (call @var{function} @var{nargs})
+ Represents a function call.  @var{function} is a @code{mem} expression
+@@ -3017,7 +3024,7 @@
+ brackets stand for a vector; the operand of @code{parallel} is a
+ vector of expressions.  @var{x0}, @var{x1} and so on are individual
+ side effect expressions---expressions of code @code{set}, @code{call},
+-@code{return}, @code{clobber} or @code{use}.
++@code{return}, @code{simple_return}, @code{clobber} or @code{use}.
+ 
+ ``In parallel'' means that first all the values used in the individual
+ side-effects are computed, and second all the actual side-effects are
+@@ -3656,14 +3663,16 @@
+ @table @code
+ @findex PATTERN
+ @item PATTERN (@var{i})
+-An expression for the side effect performed by this insn.  This must be
+-one of the following codes: @code{set}, @code{call}, @code{use},
+-@code{clobber}, @code{return}, @code{asm_input}, @code{asm_output},
+-@code{addr_vec}, @code{addr_diff_vec}, @code{trap_if}, @code{unspec},
+-@code{unspec_volatile}, @code{parallel}, @code{cond_exec}, or @code{sequence}.  If it is a @code{parallel},
+-each element of the @code{parallel} must be one these codes, except that
+-@code{parallel} expressions cannot be nested and @code{addr_vec} and
+-@code{addr_diff_vec} are not permitted inside a @code{parallel} expression.
++An expression for the side effect performed by this insn.  This must
++be one of the following codes: @code{set}, @code{call}, @code{use},
++@code{clobber}, @code{return}, @code{simple_return}, @code{asm_input},
++@code{asm_output}, @code{addr_vec}, @code{addr_diff_vec},
++@code{trap_if}, @code{unspec}, @code{unspec_volatile},
++@code{parallel}, @code{cond_exec}, or @code{sequence}.  If it is a
++@code{parallel}, each element of the @code{parallel} must be one these
++codes, except that @code{parallel} expressions cannot be nested and
++@code{addr_vec} and @code{addr_diff_vec} are not permitted inside a
++@code{parallel} expression.
+ 
+ @findex INSN_CODE
+ @item INSN_CODE (@var{i})
+
+=== modified file 'gcc/doc/tm.texi'
+--- old/gcc/doc/tm.texi	2010-09-01 13:29:58 +0000
++++ new/gcc/doc/tm.texi	2011-01-05 12:12:18 +0000
+@@ -3287,6 +3287,12 @@
+ from the frame pointer of the previous stack frame.
+ @end defmac
+ 
++@defmac RETURN_ADDR_REGNUM
++If defined, a C expression whose value is the register number of the return
++address for the current function.  Targets that pass the return address on
++the stack should not define this macro.
++@end defmac
++
+ @defmac INCOMING_RETURN_ADDR_RTX
+ A C expression whose value is RTL representing the location of the
+ incoming return address at the beginning of any function, before the
+
+=== modified file 'gcc/dwarf2out.c'
+--- old/gcc/dwarf2out.c	2010-12-21 18:46:10 +0000
++++ new/gcc/dwarf2out.c	2011-01-05 12:12:18 +0000
+@@ -1396,7 +1396,7 @@
+     {
+       rtx dest = JUMP_LABEL (insn);
+ 
+-      if (dest)
++      if (dest && !ANY_RETURN_P (dest))
+ 	{
+ 	  if (barrier_args_size [INSN_UID (dest)] < 0)
+ 	    {
+
+=== modified file 'gcc/emit-rtl.c'
+--- old/gcc/emit-rtl.c	2010-10-04 00:50:43 +0000
++++ new/gcc/emit-rtl.c	2011-01-05 12:12:18 +0000
+@@ -2432,6 +2432,8 @@
+     case CODE_LABEL:
+     case PC:
+     case CC0:
++    case RETURN:
++    case SIMPLE_RETURN:
+     case SCRATCH:
+       return;
+       /* SCRATCH must be shared because they represent distinct values.  */
+@@ -3323,14 +3325,17 @@
+   return insn;
+ }
+ 
+-/* Return the last label to mark the same position as LABEL.  Return null
+-   if LABEL itself is null.  */
++/* Return the last label to mark the same position as LABEL.  Return LABEL
++   itself if it is null or any return rtx.  */
+ 
+ rtx
+ skip_consecutive_labels (rtx label)
+ {
+   rtx insn;
+ 
++  if (label && ANY_RETURN_P (label))
++    return label;
++
+   for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn))
+     if (LABEL_P (insn))
+       label = insn;
+@@ -5209,7 +5214,7 @@
+     return CODE_LABEL;
+   if (GET_CODE (x) == CALL)
+     return CALL_INSN;
+-  if (GET_CODE (x) == RETURN)
++  if (GET_CODE (x) == RETURN || GET_CODE (x) == SIMPLE_RETURN)
+     return JUMP_INSN;
+   if (GET_CODE (x) == SET)
+     {
+@@ -5715,8 +5720,10 @@
+   init_reg_modes_target ();
+ 
+   /* Assign register numbers to the globally defined register rtx.  */
+-  pc_rtx = gen_rtx_PC (VOIDmode);
+-  cc0_rtx = gen_rtx_CC0 (VOIDmode);
++  pc_rtx = gen_rtx_fmt_ (PC, VOIDmode);
++  ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode);
++  simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode);
++  cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode);
+   stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
+   frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
+   hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
+
+=== modified file 'gcc/final.c'
+--- old/gcc/final.c	2010-03-26 16:18:51 +0000
++++ new/gcc/final.c	2011-01-05 12:12:18 +0000
+@@ -2428,7 +2428,7 @@
+ 	        delete_insn (insn);
+ 		break;
+ 	      }
+-	    else if (GET_CODE (SET_SRC (body)) == RETURN)
++	    else if (ANY_RETURN_P (SET_SRC (body)))
+ 	      /* Replace (set (pc) (return)) with (return).  */
+ 	      PATTERN (insn) = body = SET_SRC (body);
+ 
+
+=== modified file 'gcc/function.c'
+--- old/gcc/function.c	2010-08-16 19:18:08 +0000
++++ new/gcc/function.c	2011-01-05 12:12:18 +0000
+@@ -147,9 +147,6 @@
+    can always export `prologue_epilogue_contains'.  */
+ static void record_insns (rtx, rtx, htab_t *) ATTRIBUTE_UNUSED;
+ static bool contains (const_rtx, htab_t);
+-#ifdef HAVE_return
+-static void emit_return_into_block (basic_block);
+-#endif
+ static void prepare_function_start (void);
+ static void do_clobber_return_reg (rtx, void *);
+ static void do_use_return_reg (rtx, void *);
+@@ -4987,35 +4984,189 @@
+   return 0;
+ }
+ 
++#ifdef HAVE_simple_return
++/* This collects sets and clobbers of hard registers in a HARD_REG_SET,
++   which is pointed to by DATA.  */
++static void
++record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
++{
++  HARD_REG_SET *pset = (HARD_REG_SET *)data;
++  if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
++    {
++      int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)];
++      while (nregs-- > 0)
++	SET_HARD_REG_BIT (*pset, REGNO (x) + nregs);
++    }
++}
++
++/* A subroutine of requires_stack_frame_p, called via for_each_rtx.
++   If any change is made, set CHANGED
++   to true.  */
++
++static int
++frame_required_for_rtx (rtx *loc, void *data ATTRIBUTE_UNUSED)
++{
++  rtx x = *loc;
++  if (x == stack_pointer_rtx || x == hard_frame_pointer_rtx
++      || x == arg_pointer_rtx || x == pic_offset_table_rtx
++#ifdef RETURN_ADDR_REGNUM
++      || (REG_P (x) && REGNO (x) == RETURN_ADDR_REGNUM)
++#endif
++      )
++    return 1;
++  return 0;
++}
++
++static bool
++requires_stack_frame_p (rtx insn)
++{
++  HARD_REG_SET hardregs;
++  unsigned regno;
++
++  if (!INSN_P (insn) || DEBUG_INSN_P (insn))
++    return false;
++  if (CALL_P (insn))
++    return !SIBLING_CALL_P (insn);
++  if (for_each_rtx (&PATTERN (insn), frame_required_for_rtx, NULL))
++    return true;
++  CLEAR_HARD_REG_SET (hardregs);
++  note_stores (PATTERN (insn), record_hard_reg_sets, &hardregs);
++  AND_COMPL_HARD_REG_SET (hardregs, call_used_reg_set);
++  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
++    if (TEST_HARD_REG_BIT (hardregs, regno)
++	&& df_regs_ever_live_p (regno))
++      return true;
++  return false;
++}
++#endif
++
+ #ifdef HAVE_return
+-/* Insert gen_return at the end of block BB.  This also means updating
+-   block_for_insn appropriately.  */
++
++static rtx
++gen_return_pattern (bool simple_p)
++{
++#ifdef HAVE_simple_return
++  return simple_p ? gen_simple_return () : gen_return ();
++#else
++  gcc_assert (!simple_p);
++  return gen_return ();
++#endif
++}
++
++/* Insert an appropriate return pattern at the end of block BB.  This
++   also means updating block_for_insn appropriately.  */
+ 
+ static void
+-emit_return_into_block (basic_block bb)
++emit_return_into_block (bool simple_p, basic_block bb)
+ {
+-  emit_jump_insn_after (gen_return (), BB_END (bb));
++  rtx jump;
++  jump = emit_jump_insn_after (gen_return_pattern (simple_p), BB_END (bb));
++  JUMP_LABEL (jump) = simple_p ? simple_return_rtx : ret_rtx;
+ }
+-#endif /* HAVE_return */
++#endif
+ 
+ /* Generate the prologue and epilogue RTL if the machine supports it.  Thread
+    this into place with notes indicating where the prologue ends and where
+-   the epilogue begins.  Update the basic block information when possible.  */
++   the epilogue begins.  Update the basic block information when possible.
++
++   Notes on epilogue placement:
++   There are several kinds of edges to the exit block:
++   * a single fallthru edge from LAST_BB
++   * possibly, edges from blocks containing sibcalls
++   * possibly, fake edges from infinite loops
++
++   The epilogue is always emitted on the fallthru edge from the last basic
++   block in the function, LAST_BB, into the exit block.
++
++   If LAST_BB is empty except for a label, it is the target of every
++   other basic block in the function that ends in a return.  If a
++   target has a return or simple_return pattern (possibly with
++   conditional variants), these basic blocks can be changed so that a
++   return insn is emitted into them, and their target is adjusted to
++   the real exit block.
++
++   Notes on shrink wrapping: We implement a fairly conservative
++   version of shrink-wrapping rather than the textbook one.  We only
++   generate a single prologue and a single epilogue.  This is
++   sufficient to catch a number of interesting cases involving early
++   exits.
++
++   First, we identify the blocks that require the prologue to occur before
++   them.  These are the ones that modify a call-saved register, or reference
++   any of the stack or frame pointer registers.  To simplify things, we then
++   mark everything reachable from these blocks as also requiring a prologue.
++   This takes care of loops automatically, and avoids the need to examine
++   whether MEMs reference the frame, since it is sufficient to check for
++   occurrences of the stack or frame pointer.
++
++   We then compute the set of blocks for which the need for a prologue
++   is anticipatable (borrowing terminology from the shrink-wrapping
++   description in Muchnick's book).  These are the blocks which either
++   require a prologue themselves, or those that have only successors
++   where the prologue is anticipatable.  The prologue needs to be
++   inserted on all edges from BB1->BB2 where BB2 is in ANTIC and BB1
++   is not.  For the moment, we ensure that only one such edge exists.
++
++   The epilogue is placed as described above, but we make a
++   distinction between inserting return and simple_return patterns
++   when modifying other blocks that end in a return.  Blocks that end
++   in a sibcall omit the sibcall_epilogue if the block is not in
++   ANTIC.  */
+ 
+ static void
+ thread_prologue_and_epilogue_insns (void)
+ {
+   int inserted = 0;
++  basic_block last_bb;
++  bool last_bb_active;
++#ifdef HAVE_simple_return
++  bool unconverted_simple_returns = false;
++  basic_block simple_return_block = NULL;
++#endif
++  rtx returnjump ATTRIBUTE_UNUSED;
++  rtx seq ATTRIBUTE_UNUSED, epilogue_end ATTRIBUTE_UNUSED;
++  rtx prologue_seq ATTRIBUTE_UNUSED, split_prologue_seq ATTRIBUTE_UNUSED;
++  edge entry_edge, orig_entry_edge, exit_fallthru_edge;
+   edge e;
+-#if defined (HAVE_sibcall_epilogue) || defined (HAVE_epilogue) || defined (HAVE_return) || defined (HAVE_prologue)
+-  rtx seq;
+-#endif
+-#if defined (HAVE_epilogue) || defined(HAVE_return)
+-  rtx epilogue_end = NULL_RTX;
+-#endif
+   edge_iterator ei;
++  bitmap_head bb_flags;
++
++  df_analyze ();
+ 
+   rtl_profile_for_bb (ENTRY_BLOCK_PTR);
++
++  epilogue_end = NULL_RTX;
++
++  /* Can't deal with multiple successors of the entry block at the
++     moment.  Function should always have at least one entry
++     point.  */
++  gcc_assert (single_succ_p (ENTRY_BLOCK_PTR));
++  entry_edge = single_succ_edge (ENTRY_BLOCK_PTR);
++  orig_entry_edge = entry_edge;
++
++  exit_fallthru_edge = find_fallthru_edge (EXIT_BLOCK_PTR->preds);
++  if (exit_fallthru_edge != NULL)
++    {
++      rtx label;
++
++      last_bb = exit_fallthru_edge->src;
++      /* Test whether there are active instructions in the last block.  */
++      label = BB_END (last_bb);
++      while (label && !LABEL_P (label))
++	{
++	  if (active_insn_p (label))
++	    break;
++	  label = PREV_INSN (label);
++	}
++
++      last_bb_active = BB_HEAD (last_bb) != label || !LABEL_P (label);
++    }
++  else
++    {
++      last_bb = NULL;
++      last_bb_active = false;
++    }
++
+ #ifdef HAVE_prologue
+   if (HAVE_prologue)
+     {
+@@ -5040,19 +5191,168 @@
+         emit_insn (gen_blockage ());
+ #endif
+ 
+-      seq = get_insns ();
++      prologue_seq = get_insns ();
+       end_sequence ();
+       set_insn_locators (seq, prologue_locator);
+-
+-      /* Can't deal with multiple successors of the entry block
+-         at the moment.  Function should always have at least one
+-         entry point.  */
+-      gcc_assert (single_succ_p (ENTRY_BLOCK_PTR));
+-
+-      insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
+-      inserted = 1;
+-    }
+-#endif
++    }
++#endif
++
++  bitmap_initialize (&bb_flags, &bitmap_default_obstack);
++
++#ifdef HAVE_simple_return
++  /* Try to perform a kind of shrink-wrapping, making sure the
++     prologue/epilogue is emitted only around those parts of the
++     function that require it.  */
++
++  if (flag_shrink_wrap && HAVE_simple_return && !flag_non_call_exceptions
++      && HAVE_prologue && !crtl->calls_eh_return)
++    {
++      HARD_REG_SET prologue_clobbered, live_on_edge;
++      rtx p_insn;
++      VEC(basic_block, heap) *vec;
++      basic_block bb;
++      bitmap_head bb_antic_flags;
++      bitmap_head bb_on_list;
++
++      bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack);
++      bitmap_initialize (&bb_on_list, &bitmap_default_obstack);
++
++      vec = VEC_alloc (basic_block, heap, n_basic_blocks);
++
++      FOR_EACH_BB (bb)
++	{
++	  rtx insn;
++	  FOR_BB_INSNS (bb, insn)
++	    {
++	      if (requires_stack_frame_p (insn))
++		{
++		  bitmap_set_bit (&bb_flags, bb->index);
++		  VEC_quick_push (basic_block, vec, bb);
++		  break;
++		}
++	    }
++	}
++
++      /* For every basic block that needs a prologue, mark all blocks
++	 reachable from it, so as to ensure they are also seen as
++	 requiring a prologue.  */
++      while (!VEC_empty (basic_block, vec))
++	{
++	  basic_block tmp_bb = VEC_pop (basic_block, vec);
++	  edge e;
++	  edge_iterator ei;
++	  FOR_EACH_EDGE (e, ei, tmp_bb->succs)
++	    {
++	      if (e->dest == EXIT_BLOCK_PTR
++		  || bitmap_bit_p (&bb_flags, e->dest->index))
++		continue;
++	      bitmap_set_bit (&bb_flags, e->dest->index);
++	      VEC_quick_push (basic_block, vec, e->dest);
++	    }
++	}
++      /* If the last basic block contains only a label, we'll be able
++	 to convert jumps to it to (potentially conditional) return
++	 insns later.  This means we don't necessarily need a prologue
++	 for paths reaching it.  */
++      if (last_bb)
++	{
++	  if (!last_bb_active)
++	    bitmap_clear_bit (&bb_flags, last_bb->index);
++	  else if (!bitmap_bit_p (&bb_flags, last_bb->index))
++	    goto fail_shrinkwrap;
++	}
++
++      /* Now walk backwards from every block that is marked as needing
++	 a prologue to compute the bb_antic_flags bitmap.  */
++      bitmap_copy (&bb_antic_flags, &bb_flags);
++      FOR_EACH_BB (bb)
++	{
++	  edge e;
++	  edge_iterator ei;
++	  if (!bitmap_bit_p (&bb_flags, bb->index))
++	    continue;
++	  FOR_EACH_EDGE (e, ei, bb->preds)
++	    if (!bitmap_bit_p (&bb_antic_flags, e->src->index))
++	      {
++		VEC_quick_push (basic_block, vec, e->src);
++		bitmap_set_bit (&bb_on_list, e->src->index);
++	      }
++	}
++      while (!VEC_empty (basic_block, vec))
++	{
++	  basic_block tmp_bb = VEC_pop (basic_block, vec);
++	  edge e;
++	  edge_iterator ei;
++	  bool all_set = true;
++	  
++	  bitmap_clear_bit (&bb_on_list, tmp_bb->index);
++	  FOR_EACH_EDGE (e, ei, tmp_bb->succs)
++	    {
++	      if (!bitmap_bit_p (&bb_antic_flags, e->dest->index))
++		{
++		  all_set = false;
++		  break;
++		}
++	    }
++	  if (all_set)
++	    {
++	      bitmap_set_bit (&bb_antic_flags, tmp_bb->index);
++	      FOR_EACH_EDGE (e, ei, tmp_bb->preds)
++		if (!bitmap_bit_p (&bb_antic_flags, e->src->index))
++		  {
++		    VEC_quick_push (basic_block, vec, e->src);
++		    bitmap_set_bit (&bb_on_list, e->src->index);
++		  }
++	    }
++	}
++      /* Find exactly one edge that leads to a block in ANTIC from
++	 a block that isn't.  */
++      if (!bitmap_bit_p (&bb_antic_flags, entry_edge->dest->index))
++	FOR_EACH_BB (bb)
++	  {
++	    if (!bitmap_bit_p (&bb_antic_flags, bb->index))
++	      continue;
++	    FOR_EACH_EDGE (e, ei, bb->preds)
++	      if (!bitmap_bit_p (&bb_antic_flags, e->src->index))
++		{
++		  if (entry_edge != orig_entry_edge)
++		    {
++		      entry_edge = orig_entry_edge;
++		      goto fail_shrinkwrap;
++		    }
++		  entry_edge = e;
++		}
++	  }
++
++      /* Test whether the prologue is known to clobber any register
++	 (other than FP or SP) which are live on the edge.  */
++      CLEAR_HARD_REG_SET (prologue_clobbered);
++      for (p_insn = prologue_seq; p_insn; p_insn = NEXT_INSN (p_insn))
++	if (NONDEBUG_INSN_P (p_insn))
++	  note_stores (PATTERN (p_insn), record_hard_reg_sets,
++		       &prologue_clobbered);
++      CLEAR_HARD_REG_BIT (prologue_clobbered, STACK_POINTER_REGNUM);
++      if (frame_pointer_needed)
++	CLEAR_HARD_REG_BIT (prologue_clobbered, HARD_FRAME_POINTER_REGNUM);
++
++      CLEAR_HARD_REG_SET (live_on_edge);
++      reg_set_to_hard_reg_set (&live_on_edge,
++			       df_get_live_in (entry_edge->dest));
++      if (hard_reg_set_intersect_p (live_on_edge, prologue_clobbered))
++	entry_edge = orig_entry_edge;
++
++    fail_shrinkwrap:
++      bitmap_clear (&bb_antic_flags);
++      bitmap_clear (&bb_on_list);
++      VEC_free (basic_block, heap, vec);
++    }
++#endif
++
++  if (prologue_seq != NULL_RTX)
++    {
++      insert_insn_on_edge (prologue_seq, entry_edge);
++      inserted = true;
++    }
+ 
+   /* If the exit block has no non-fake predecessors, we don't need
+      an epilogue.  */
+@@ -5063,100 +5363,130 @@
+     goto epilogue_done;
+ 
+   rtl_profile_for_bb (EXIT_BLOCK_PTR);
++
+ #ifdef HAVE_return
+-  if (optimize && HAVE_return)
++  /* If we're allowed to generate a simple return instruction, then by
++     definition we don't need a full epilogue.  If the last basic
++     block before the exit block does not contain active instructions,
++     examine its predecessors and try to emit (conditional) return
++     instructions.  */
++  if (optimize && !last_bb_active
++      && (HAVE_return || entry_edge != orig_entry_edge))
+     {
+-      /* If we're allowed to generate a simple return instruction,
+-	 then by definition we don't need a full epilogue.  Examine
+-	 the block that falls through to EXIT.   If it does not
+-	 contain any code, examine its predecessors and try to
+-	 emit (conditional) return instructions.  */
+-
+-      basic_block last;
++      edge_iterator ei2;
++      int i;
++      basic_block bb;
+       rtx label;
++      VEC(basic_block,heap) *src_bbs;
+ 
+-      FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
+-	if (e->flags & EDGE_FALLTHRU)
+-	  break;
+-      if (e == NULL)
++      if (exit_fallthru_edge == NULL)
+ 	goto epilogue_done;
+-      last = e->src;
+-
+-      /* Verify that there are no active instructions in the last block.  */
+-      label = BB_END (last);
+-      while (label && !LABEL_P (label))
++      label = BB_HEAD (last_bb);
++
++      src_bbs = VEC_alloc (basic_block, heap, EDGE_COUNT (last_bb->preds));
++      FOR_EACH_EDGE (e, ei2, last_bb->preds)
++	if (e->src != ENTRY_BLOCK_PTR)
++	  VEC_quick_push (basic_block, src_bbs, e->src);
++
++      FOR_EACH_VEC_ELT (basic_block, src_bbs, i, bb)
+ 	{
+-	  if (active_insn_p (label))
+-	    break;
+-	  label = PREV_INSN (label);
++	  bool simple_p;
++	  rtx jump;
++	  e = find_edge (bb, last_bb);
++
++	  jump = BB_END (bb);
++
++#ifdef HAVE_simple_return
++	  simple_p = (entry_edge != orig_entry_edge
++		      ? !bitmap_bit_p (&bb_flags, bb->index) : false);
++#else
++	  simple_p = false;
++#endif
++
++	  if (!simple_p
++	      && (!HAVE_return || !JUMP_P (jump)
++		  || JUMP_LABEL (jump) != label))
++	    continue;
++
++	  /* If we have an unconditional jump, we can replace that
++	     with a simple return instruction.  */
++	  if (!JUMP_P (jump))
++	    {
++	      emit_barrier_after (BB_END (bb));
++	      emit_return_into_block (simple_p, bb);
++	    }
++	  else if (simplejump_p (jump))
++	    {
++	      emit_return_into_block (simple_p, bb);
++	      delete_insn (jump);
++	    }
++	  else if (condjump_p (jump) && JUMP_LABEL (jump) != label)
++	    {
++	      basic_block new_bb;
++	      edge new_e;
++
++	      gcc_assert (simple_p);
++	      new_bb = split_edge (e);
++	      emit_barrier_after (BB_END (new_bb));
++	      emit_return_into_block (simple_p, new_bb);
++#ifdef HAVE_simple_return
++	      simple_return_block = new_bb;
++#endif
++	      new_e = single_succ_edge (new_bb);
++	      redirect_edge_succ (new_e, EXIT_BLOCK_PTR);
++
++	      continue;
++	    }
++	  /* If we have a conditional jump branching to the last
++	     block, we can try to replace that with a conditional
++	     return instruction.  */
++	  else if (condjump_p (jump))
++	    {
++	      rtx dest;
++	      if (simple_p)
++		dest = simple_return_rtx;
++	      else
++		dest = ret_rtx;
++	      if (! redirect_jump (jump, dest, 0))
++		{
++#ifdef HAVE_simple_return
++		  if (simple_p)
++		    unconverted_simple_returns = true;
++#endif
++		  continue;
++		}
++
++	      /* If this block has only one successor, it both jumps
++		 and falls through to the fallthru block, so we can't
++		 delete the edge.  */
++	      if (single_succ_p (bb))
++		continue;
++	    }
++	  else
++	    {
++#ifdef HAVE_simple_return
++	      if (simple_p)
++		unconverted_simple_returns = true;
++#endif
++	      continue;
++	    }
++
++	  /* Fix up the CFG for the successful change we just made.  */
++	  redirect_edge_succ (e, EXIT_BLOCK_PTR);
+ 	}
++      VEC_free (basic_block, heap, src_bbs);
+ 
+-      if (BB_HEAD (last) == label && LABEL_P (label))
++      if (HAVE_return)
+ 	{
+-	  edge_iterator ei2;
+-
+-	  for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); )
+-	    {
+-	      basic_block bb = e->src;
+-	      rtx jump;
+-
+-	      if (bb == ENTRY_BLOCK_PTR)
+-		{
+-		  ei_next (&ei2);
+-		  continue;
+-		}
+-
+-	      jump = BB_END (bb);
+-	      if (!JUMP_P (jump) || JUMP_LABEL (jump) != label)
+-		{
+-		  ei_next (&ei2);
+-		  continue;
+-		}
+-
+-	      /* If we have an unconditional jump, we can replace that
+-		 with a simple return instruction.  */
+-	      if (simplejump_p (jump))
+-		{
+-		  emit_return_into_block (bb);
+-		  delete_insn (jump);
+-		}
+-
+-	      /* If we have a conditional jump, we can try to replace
+-		 that with a conditional return instruction.  */
+-	      else if (condjump_p (jump))
+-		{
+-		  if (! redirect_jump (jump, 0, 0))
+-		    {
+-		      ei_next (&ei2);
+-		      continue;
+-		    }
+-
+-		  /* If this block has only one successor, it both jumps
+-		     and falls through to the fallthru block, so we can't
+-		     delete the edge.  */
+-		  if (single_succ_p (bb))
+-		    {
+-		      ei_next (&ei2);
+-		      continue;
+-		    }
+-		}
+-	      else
+-		{
+-		  ei_next (&ei2);
+-		  continue;
+-		}
+-
+-	      /* Fix up the CFG for the successful change we just made.  */
+-	      redirect_edge_succ (e, EXIT_BLOCK_PTR);
+-	    }
+-
+ 	  /* Emit a return insn for the exit fallthru block.  Whether
+ 	     this is still reachable will be determined later.  */
+ 
+-	  emit_barrier_after (BB_END (last));
+-	  emit_return_into_block (last);
+-	  epilogue_end = BB_END (last);
+-	  single_succ_edge (last)->flags &= ~EDGE_FALLTHRU;
++	  emit_barrier_after (BB_END (last_bb));
++	  emit_return_into_block (false, last_bb);
++	  epilogue_end = BB_END (last_bb);
++	  if (JUMP_P (epilogue_end))
++	    JUMP_LABEL (epilogue_end) = ret_rtx;
++	  single_succ_edge (last_bb)->flags &= ~EDGE_FALLTHRU;
+ 	  goto epilogue_done;
+ 	}
+     }
+@@ -5193,15 +5523,10 @@
+     }
+ #endif
+ 
+-  /* Find the edge that falls through to EXIT.  Other edges may exist
+-     due to RETURN instructions, but those don't need epilogues.
+-     There really shouldn't be a mixture -- either all should have
+-     been converted or none, however...  */
++  /* If nothing falls through into the exit block, we don't need an
++     epilogue.  */
+ 
+-  FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
+-    if (e->flags & EDGE_FALLTHRU)
+-      break;
+-  if (e == NULL)
++  if (exit_fallthru_edge == NULL)
+     goto epilogue_done;
+ 
+ #ifdef HAVE_epilogue
+@@ -5217,25 +5542,38 @@
+       set_insn_locators (seq, epilogue_locator);
+ 
+       seq = get_insns ();
++      returnjump = get_last_insn ();
+       end_sequence ();
+ 
+-      insert_insn_on_edge (seq, e);
++      insert_insn_on_edge (seq, exit_fallthru_edge);
+       inserted = 1;
++      if (JUMP_P (returnjump))
++	{
++ 	  rtx pat = PATTERN (returnjump);
++ 	  if (GET_CODE (pat) == PARALLEL)
++	    pat = XVECEXP (pat, 0, 0);
++	  if (ANY_RETURN_P (pat))
++	    JUMP_LABEL (returnjump) = pat;
++	  else
++	    JUMP_LABEL (returnjump) = ret_rtx;
++	}
++      else
++	returnjump = NULL_RTX;
+     }
+   else
+ #endif
+     {
+       basic_block cur_bb;
+ 
+-      if (! next_active_insn (BB_END (e->src)))
++      if (! next_active_insn (BB_END (exit_fallthru_edge->src)))
+ 	goto epilogue_done;
+       /* We have a fall-through edge to the exit block, the source is not
+-         at the end of the function, and there will be an assembler epilogue
+-         at the end of the function.
+-         We can't use force_nonfallthru here, because that would try to
+-         use return.  Inserting a jump 'by hand' is extremely messy, so
++	 at the end of the function, and there will be an assembler epilogue
++	 at the end of the function.
++	 We can't use force_nonfallthru here, because that would try to
++	 use return.  Inserting a jump 'by hand' is extremely messy, so
+ 	 we take advantage of cfg_layout_finalize using
+-	fixup_fallthru_exit_predecessor.  */
++	 fixup_fallthru_exit_predecessor.  */
+       cfg_layout_initialize (0);
+       FOR_EACH_BB (cur_bb)
+ 	if (cur_bb->index >= NUM_FIXED_BLOCKS
+@@ -5244,6 +5582,7 @@
+       cfg_layout_finalize ();
+     }
+ epilogue_done:
++
+   default_rtl_profile ();
+ 
+   if (inserted)
+@@ -5260,33 +5599,93 @@
+ 	}
+     }
+ 
++#ifdef HAVE_simple_return
++  /* If there were branches to an empty LAST_BB which we tried to
++     convert to conditional simple_returns, but couldn't for some
++     reason, create a block to hold a simple_return insn and redirect
++     those remaining edges.  */
++  if (unconverted_simple_returns)
++    {
++      edge_iterator ei2;
++      basic_block exit_pred = EXIT_BLOCK_PTR->prev_bb;
++
++      gcc_assert (entry_edge != orig_entry_edge);
++
++#ifdef HAVE_epilogue
++      if (simple_return_block == NULL && returnjump != NULL_RTX
++	  && JUMP_LABEL (returnjump) == simple_return_rtx)
++	{
++	  edge e = split_block (exit_fallthru_edge->src,
++				PREV_INSN (returnjump));
++	  simple_return_block = e->dest;
++	}
++#endif
++      if (simple_return_block == NULL)
++	{
++	  basic_block bb;
++	  rtx start;
++
++	  bb = create_basic_block (NULL, NULL, exit_pred);
++	  start = emit_jump_insn_after (gen_simple_return (),
++					BB_END (bb));
++	  JUMP_LABEL (start) = simple_return_rtx;
++	  emit_barrier_after (start);
++
++	  simple_return_block = bb;
++	  make_edge (bb, EXIT_BLOCK_PTR, 0);
++	}
++
++    restart_scan:
++      for (ei2 = ei_start (last_bb->preds); (e = ei_safe_edge (ei2)); )
++	{
++	  basic_block bb = e->src;
++
++	  if (bb != ENTRY_BLOCK_PTR
++	      && !bitmap_bit_p (&bb_flags, bb->index))
++	    {
++	      redirect_edge_and_branch_force (e, simple_return_block);
++	      goto restart_scan;
++	    }
++	  ei_next (&ei2);
++
++	}
++    }
++#endif
++
+ #ifdef HAVE_sibcall_epilogue
+   /* Emit sibling epilogues before any sibling call sites.  */
+   for (ei = ei_start (EXIT_BLOCK_PTR->preds); (e = ei_safe_edge (ei)); )
+     {
+       basic_block bb = e->src;
+       rtx insn = BB_END (bb);
++      rtx ep_seq;
+ 
+       if (!CALL_P (insn)
+-	  || ! SIBLING_CALL_P (insn))
++	  || ! SIBLING_CALL_P (insn)
++	  || (entry_edge != orig_entry_edge
++	      && !bitmap_bit_p (&bb_flags, bb->index)))
+ 	{
+ 	  ei_next (&ei);
+ 	  continue;
+ 	}
+ 
+-      start_sequence ();
+-      emit_note (NOTE_INSN_EPILOGUE_BEG);
+-      emit_insn (gen_sibcall_epilogue ());
+-      seq = get_insns ();
+-      end_sequence ();
+-
+-      /* Retain a map of the epilogue insns.  Used in life analysis to
+-	 avoid getting rid of sibcall epilogue insns.  Do this before we
+-	 actually emit the sequence.  */
+-      record_insns (seq, NULL, &epilogue_insn_hash);
+-      set_insn_locators (seq, epilogue_locator);
+-
+-      emit_insn_before (seq, insn);
++      ep_seq = gen_sibcall_epilogue ();
++      if (ep_seq)
++	{
++	  start_sequence ();
++	  emit_note (NOTE_INSN_EPILOGUE_BEG);
++	  emit_insn (ep_seq);
++	  seq = get_insns ();
++	  end_sequence ();
++
++	  /* Retain a map of the epilogue insns.  Used in life analysis to
++	     avoid getting rid of sibcall epilogue insns.  Do this before we
++	     actually emit the sequence.  */
++	  record_insns (seq, NULL, &epilogue_insn_hash);
++	  set_insn_locators (seq, epilogue_locator);
++
++	  emit_insn_before (seq, insn);
++	}
+       ei_next (&ei);
+     }
+ #endif
+@@ -5311,6 +5710,8 @@
+     }
+ #endif
+ 
++  bitmap_clear (&bb_flags);
++
+   /* Threading the prologue and epilogue changes the artificial refs
+      in the entry and exit blocks.  */
+   epilogue_completed = 1;
+
+=== modified file 'gcc/genemit.c'
+--- old/gcc/genemit.c	2009-11-27 11:37:06 +0000
++++ new/gcc/genemit.c	2011-01-05 12:12:18 +0000
+@@ -222,6 +222,12 @@
+     case PC:
+       printf ("pc_rtx");
+       return;
++    case RETURN:
++      printf ("ret_rtx");
++      return;
++    case SIMPLE_RETURN:
++      printf ("simple_return_rtx");
++      return;
+     case CLOBBER:
+       if (REG_P (XEXP (x, 0)))
+ 	{
+@@ -544,8 +550,8 @@
+ 	  || (GET_CODE (next) == PARALLEL
+ 	      && ((GET_CODE (XVECEXP (next, 0, 0)) == SET
+ 		   && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC)
+-		  || GET_CODE (XVECEXP (next, 0, 0)) == RETURN))
+-	  || GET_CODE (next) == RETURN)
++		  || ANY_RETURN_P (XVECEXP (next, 0, 0))))
++	  || ANY_RETURN_P (next))
+ 	printf ("  emit_jump_insn (");
+       else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL)
+ 	       || GET_CODE (next) == CALL
+@@ -660,7 +666,7 @@
+ 	  || (GET_CODE (next) == PARALLEL
+ 	      && GET_CODE (XVECEXP (next, 0, 0)) == SET
+ 	      && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC)
+-	  || GET_CODE (next) == RETURN)
++	  || ANY_RETURN_P (next))
+ 	printf ("  emit_jump_insn (");
+       else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL)
+ 	       || GET_CODE (next) == CALL
+
+=== modified file 'gcc/gengenrtl.c'
+--- old/gcc/gengenrtl.c	2007-08-22 23:30:39 +0000
++++ new/gcc/gengenrtl.c	2011-01-05 12:12:18 +0000
+@@ -146,6 +146,10 @@
+ 	  || strcmp (defs[idx].enumname, "REG") == 0
+ 	  || strcmp (defs[idx].enumname, "SUBREG") == 0
+ 	  || strcmp (defs[idx].enumname, "MEM") == 0
++	  || strcmp (defs[idx].enumname, "PC") == 0
++	  || strcmp (defs[idx].enumname, "CC0") == 0
++	  || strcmp (defs[idx].enumname, "RETURN") == 0
++	  || strcmp (defs[idx].enumname, "SIMPLE_RETURN") == 0
+ 	  || strcmp (defs[idx].enumname, "CONST_VECTOR") == 0);
+ }
+ 
+
+=== modified file 'gcc/haifa-sched.c'
+--- old/gcc/haifa-sched.c	2010-08-12 08:14:47 +0000
++++ new/gcc/haifa-sched.c	2011-01-05 12:12:18 +0000
+@@ -4231,7 +4231,7 @@
+ /* Helper function.
+    Find fallthru edge from PRED.  */
+ edge
+-find_fallthru_edge (basic_block pred)
++find_fallthru_edge_from (basic_block pred)
+ {
+   edge e;
+   edge_iterator ei;
+@@ -4298,7 +4298,7 @@
+   edge e;
+ 
+   last = EXIT_BLOCK_PTR->prev_bb;
+-  e = find_fallthru_edge (last);
++  e = find_fallthru_edge_from (last);
+ 
+   if (e)
+     {
+@@ -5234,6 +5234,11 @@
+ 		    gcc_assert (/* Usual case.  */
+                                 (EDGE_COUNT (bb->succs) > 1
+                                  && !BARRIER_P (NEXT_INSN (head)))
++				/* Special cases, see cfglayout.c:
++				   fixup_reorder_chain.  */
++				|| (EDGE_COUNT (bb->succs) == 1
++				    && (!onlyjump_p (head)
++					|| returnjump_p (head)))
+                                 /* Or jump to the next instruction.  */
+                                 || (EDGE_COUNT (bb->succs) == 1
+                                     && (BB_HEAD (EDGE_I (bb->succs, 0)->dest)
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c	2010-11-26 12:03:32 +0000
++++ new/gcc/ifcvt.c	2011-01-05 12:12:18 +0000
+@@ -105,7 +105,7 @@
+ static int find_if_case_2 (basic_block, edge, edge);
+ static int find_memory (rtx *, void *);
+ static int dead_or_predicable (basic_block, basic_block, basic_block,
+-			       basic_block, int);
++			       edge, int);
+ static void noce_emit_move_insn (rtx, rtx);
+ static rtx block_has_only_trap (basic_block);
+ 
+@@ -3791,6 +3791,7 @@
+   basic_block then_bb = then_edge->dest;
+   basic_block else_bb = else_edge->dest;
+   basic_block new_bb;
++  rtx else_target = NULL_RTX;
+   int then_bb_index;
+ 
+   /* If we are partitioning hot/cold basic blocks, we don't want to
+@@ -3840,9 +3841,16 @@
+ 				    predictable_edge_p (then_edge)))))
+     return FALSE;
+ 
++  if (else_bb == EXIT_BLOCK_PTR)
++    {
++      rtx jump = BB_END (else_edge->src);
++      gcc_assert (JUMP_P (jump));
++      else_target = JUMP_LABEL (jump);
++    }
++
+   /* Registers set are dead, or are predicable.  */
+   if (! dead_or_predicable (test_bb, then_bb, else_bb,
+-			    single_succ (then_bb), 1))
++			    single_succ_edge (then_bb), 1))
+     return FALSE;
+ 
+   /* Conversion went ok, including moving the insns and fixing up the
+@@ -3859,6 +3867,9 @@
+       redirect_edge_succ (FALLTHRU_EDGE (test_bb), else_bb);
+       new_bb = 0;
+     }
++  else if (else_bb == EXIT_BLOCK_PTR)
++    new_bb = force_nonfallthru_and_redirect (FALLTHRU_EDGE (test_bb),
++					     else_bb, else_target);
+   else
+     new_bb = redirect_edge_and_branch_force (FALLTHRU_EDGE (test_bb),
+ 					     else_bb);
+@@ -3957,7 +3968,7 @@
+     return FALSE;
+ 
+   /* Registers set are dead, or are predicable.  */
+-  if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ->dest, 0))
++  if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ, 0))
+     return FALSE;
+ 
+   /* Conversion went ok, including moving the insns and fixing up the
+@@ -3995,12 +4006,34 @@
+ 
+ static int
+ dead_or_predicable (basic_block test_bb, basic_block merge_bb,
+-		    basic_block other_bb, basic_block new_dest, int reversep)
++		    basic_block other_bb, edge dest_edge, int reversep)
+ {
+-  rtx head, end, jump, earliest = NULL_RTX, old_dest, new_label = NULL_RTX;
++  basic_block new_dest = dest_edge->dest;
++  rtx head, end, jump, earliest = NULL_RTX, old_dest;
+   bitmap merge_set = NULL;
+   /* Number of pending changes.  */
+   int n_validated_changes = 0;
++  rtx new_dest_label;
++
++  jump = BB_END (dest_edge->src);
++  if (JUMP_P (jump))
++    {
++      new_dest_label = JUMP_LABEL (jump);
++      if (new_dest_label == NULL_RTX)
++	{
++	  new_dest_label = PATTERN (jump);
++	  gcc_assert (ANY_RETURN_P (new_dest_label));
++	}
++    }
++  else if (other_bb != new_dest)
++    {
++      if (new_dest == EXIT_BLOCK_PTR)
++	new_dest_label = ret_rtx;
++      else
++	new_dest_label = block_label (new_dest);
++    }
++  else
++    new_dest_label = NULL_RTX;
+ 
+   jump = BB_END (test_bb);
+ 
+@@ -4220,10 +4253,9 @@
+   old_dest = JUMP_LABEL (jump);
+   if (other_bb != new_dest)
+     {
+-      new_label = block_label (new_dest);
+       if (reversep
+-	  ? ! invert_jump_1 (jump, new_label)
+-	  : ! redirect_jump_1 (jump, new_label))
++	  ? ! invert_jump_1 (jump, new_dest_label)
++	  : ! redirect_jump_1 (jump, new_dest_label))
+ 	goto cancel;
+     }
+ 
+@@ -4234,7 +4266,7 @@
+ 
+   if (other_bb != new_dest)
+     {
+-      redirect_jump_2 (jump, old_dest, new_label, 0, reversep);
++      redirect_jump_2 (jump, old_dest, new_dest_label, 0, reversep);
+ 
+       redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest);
+       if (reversep)
+
+=== modified file 'gcc/jump.c'
+--- old/gcc/jump.c	2010-12-13 10:05:52 +0000
++++ new/gcc/jump.c	2011-01-05 12:12:18 +0000
+@@ -29,7 +29,8 @@
+    JUMP_LABEL internal field.  With this we can detect labels that
+    become unused because of the deletion of all the jumps that
+    formerly used them.  The JUMP_LABEL info is sometimes looked
+-   at by later passes.
++   at by later passes.  For return insns, it contains either a
++   RETURN or a SIMPLE_RETURN rtx.
+ 
+    The subroutines redirect_jump and invert_jump are used
+    from other passes as well.  */
+@@ -742,10 +743,10 @@
+     return (GET_CODE (x) == IF_THEN_ELSE
+ 	    && ((GET_CODE (XEXP (x, 2)) == PC
+ 		 && (GET_CODE (XEXP (x, 1)) == LABEL_REF
+-		     || GET_CODE (XEXP (x, 1)) == RETURN))
++		     || ANY_RETURN_P (XEXP (x, 1))))
+ 		|| (GET_CODE (XEXP (x, 1)) == PC
+ 		    && (GET_CODE (XEXP (x, 2)) == LABEL_REF
+-			|| GET_CODE (XEXP (x, 2)) == RETURN))));
++			|| ANY_RETURN_P (XEXP (x, 2))))));
+ }
+ 
+ /* Return nonzero if INSN is a (possibly) conditional jump inside a
+@@ -774,11 +775,11 @@
+     return 0;
+   if (XEXP (SET_SRC (x), 2) == pc_rtx
+       && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF
+-	  || GET_CODE (XEXP (SET_SRC (x), 1)) == RETURN))
++	  || ANY_RETURN_P (XEXP (SET_SRC (x), 1)) == RETURN))
+     return 1;
+   if (XEXP (SET_SRC (x), 1) == pc_rtx
+       && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF
+-	  || GET_CODE (XEXP (SET_SRC (x), 2)) == RETURN))
++	  || ANY_RETURN_P (XEXP (SET_SRC (x), 2))))
+     return 1;
+   return 0;
+ }
+@@ -840,8 +841,9 @@
+   a = GET_CODE (XEXP (SET_SRC (x), 1));
+   b = GET_CODE (XEXP (SET_SRC (x), 2));
+ 
+-  return ((b == PC && (a == LABEL_REF || a == RETURN))
+-	  || (a == PC && (b == LABEL_REF || b == RETURN)));
++  return ((b == PC && (a == LABEL_REF || a == RETURN || a == SIMPLE_RETURN))
++	  || (a == PC
++	      && (b == LABEL_REF || b == RETURN || b == SIMPLE_RETURN)));
+ }
+ 
+ /* Return the label of a conditional jump.  */
+@@ -878,6 +880,7 @@
+   switch (GET_CODE (x))
+     {
+     case RETURN:
++    case SIMPLE_RETURN:
+     case EH_RETURN:
+       return true;
+ 
+@@ -1200,7 +1203,7 @@
+   /* If deleting a jump, decrement the count of the label,
+      and delete the label if it is now unused.  */
+ 
+-  if (JUMP_P (insn) && JUMP_LABEL (insn))
++  if (JUMP_P (insn) && JUMP_LABEL (insn) && !ANY_RETURN_P (JUMP_LABEL (insn)))
+     {
+       rtx lab = JUMP_LABEL (insn), lab_next;
+ 
+@@ -1331,6 +1334,18 @@
+      is also an unconditional jump in that case.  */
+ }
+ 
++/* A helper function for redirect_exp_1; examines its input X and returns
++   either a LABEL_REF around a label, or a RETURN if X was NULL.  */
++static rtx
++redirect_target (rtx x)
++{
++  if (x == NULL_RTX)
++    return ret_rtx;
++  if (!ANY_RETURN_P (x))
++    return gen_rtx_LABEL_REF (Pmode, x);
++  return x;
++}
++
+ /* Throughout LOC, redirect OLABEL to NLABEL.  Treat null OLABEL or
+    NLABEL as a return.  Accrue modifications into the change group.  */
+ 
+@@ -1342,37 +1357,19 @@
+   int i;
+   const char *fmt;
+ 
+-  if (code == LABEL_REF)
+-    {
+-      if (XEXP (x, 0) == olabel)
+-	{
+-	  rtx n;
+-	  if (nlabel)
+-	    n = gen_rtx_LABEL_REF (Pmode, nlabel);
+-	  else
+-	    n = gen_rtx_RETURN (VOIDmode);
+-
+-	  validate_change (insn, loc, n, 1);
+-	  return;
+-	}
+-    }
+-  else if (code == RETURN && olabel == 0)
+-    {
+-      if (nlabel)
+-	x = gen_rtx_LABEL_REF (Pmode, nlabel);
+-      else
+-	x = gen_rtx_RETURN (VOIDmode);
+-      if (loc == &PATTERN (insn))
+-	x = gen_rtx_SET (VOIDmode, pc_rtx, x);
+-      validate_change (insn, loc, x, 1);
++  if ((code == LABEL_REF && XEXP (x, 0) == olabel)
++      || x == olabel)
++    {
++      validate_change (insn, loc, redirect_target (nlabel), 1);
+       return;
+     }
+ 
+-  if (code == SET && nlabel == 0 && SET_DEST (x) == pc_rtx
++  if (code == SET && SET_DEST (x) == pc_rtx
++      && ANY_RETURN_P (nlabel)
+       && GET_CODE (SET_SRC (x)) == LABEL_REF
+       && XEXP (SET_SRC (x), 0) == olabel)
+     {
+-      validate_change (insn, loc, gen_rtx_RETURN (VOIDmode), 1);
++      validate_change (insn, loc, nlabel, 1);
+       return;
+     }
+ 
+@@ -1409,6 +1406,7 @@
+   int ochanges = num_validated_changes ();
+   rtx *loc, asmop;
+ 
++  gcc_assert (nlabel);
+   asmop = extract_asm_operands (PATTERN (jump));
+   if (asmop)
+     {
+@@ -1430,17 +1428,20 @@
+    jump target label is unused as a result, it and the code following
+    it may be deleted.
+ 
+-   If NLABEL is zero, we are to turn the jump into a (possibly conditional)
+-   RETURN insn.
++   Normally, NLABEL will be a label, but it may also be a RETURN or
++   SIMPLE_RETURN rtx; in that case we are to turn the jump into a
++   (possibly conditional) return insn.
+ 
+    The return value will be 1 if the change was made, 0 if it wasn't
+-   (this can only occur for NLABEL == 0).  */
++   (this can only occur when trying to produce return insns).  */
+ 
+ int
+ redirect_jump (rtx jump, rtx nlabel, int delete_unused)
+ {
+   rtx olabel = JUMP_LABEL (jump);
+ 
++  gcc_assert (nlabel != NULL_RTX);
++
+   if (nlabel == olabel)
+     return 1;
+ 
+@@ -1452,7 +1453,7 @@
+ }
+ 
+ /* Fix up JUMP_LABEL and label ref counts after OLABEL has been replaced with
+-   NLABEL in JUMP.
++   NEW_DEST in JUMP.
+    If DELETE_UNUSED is positive, delete related insn to OLABEL if its ref
+    count has dropped to zero.  */
+ void
+@@ -1468,13 +1469,14 @@
+      about this.  */
+   gcc_assert (delete_unused >= 0);
+   JUMP_LABEL (jump) = nlabel;
+-  if (nlabel)
++  if (nlabel && !ANY_RETURN_P (nlabel))
+     ++LABEL_NUSES (nlabel);
+ 
+   /* Update labels in any REG_EQUAL note.  */
+   if ((note = find_reg_note (jump, REG_EQUAL, NULL_RTX)) != NULL_RTX)
+     {
+-      if (!nlabel || (invert && !invert_exp_1 (XEXP (note, 0), jump)))
++      if (ANY_RETURN_P (nlabel)
++	  || (invert && !invert_exp_1 (XEXP (note, 0), jump)))
+ 	remove_note (jump, note);
+       else
+ 	{
+@@ -1483,7 +1485,8 @@
+ 	}
+     }
+ 
+-  if (olabel && --LABEL_NUSES (olabel) == 0 && delete_unused > 0
++  if (olabel && !ANY_RETURN_P (olabel)
++      && --LABEL_NUSES (olabel) == 0 && delete_unused > 0
+       /* Undefined labels will remain outside the insn stream.  */
+       && INSN_UID (olabel))
+     delete_related_insns (olabel);
+
+=== modified file 'gcc/opts.c'
+--- old/gcc/opts.c	2010-12-10 15:33:37 +0000
++++ new/gcc/opts.c	2011-01-05 12:12:18 +0000
+@@ -908,6 +908,7 @@
+   flag_ipa_cp = opt2;
+   flag_ipa_sra = opt2;
+   flag_ee = opt2;
++  flag_shrink_wrap = opt2;
+ 
+   /* Track fields in field-sensitive alias analysis.  */
+   set_param_value ("max-fields-for-field-sensitive",
+
+=== modified file 'gcc/print-rtl.c'
+--- old/gcc/print-rtl.c	2010-03-26 16:18:51 +0000
++++ new/gcc/print-rtl.c	2011-01-05 12:12:18 +0000
+@@ -308,9 +308,16 @@
+ 	      }
+ 	  }
+ 	else if (i == 8 && JUMP_P (in_rtx) && JUMP_LABEL (in_rtx) != NULL)
+-	  /* Output the JUMP_LABEL reference.  */
+-	  fprintf (outfile, "\n%s%*s -> %d", print_rtx_head, indent * 2, "",
+-		   INSN_UID (JUMP_LABEL (in_rtx)));
++	  {
++	    /* Output the JUMP_LABEL reference.  */
++	    fprintf (outfile, "\n%s%*s -> ", print_rtx_head, indent * 2, "");
++	    if (GET_CODE (JUMP_LABEL (in_rtx)) == RETURN)
++	      fprintf (outfile, "return");
++	    else if (GET_CODE (JUMP_LABEL (in_rtx)) == SIMPLE_RETURN)
++	      fprintf (outfile, "simple_return");
++	    else
++	      fprintf (outfile, "%d", INSN_UID (JUMP_LABEL (in_rtx)));
++	  }
+ 	else if (i == 0 && GET_CODE (in_rtx) == VALUE)
+ 	  {
+ #ifndef GENERATOR_FILE
+
+=== modified file 'gcc/reorg.c'
+--- old/gcc/reorg.c	2010-09-15 22:51:44 +0000
++++ new/gcc/reorg.c	2011-01-05 12:12:18 +0000
+@@ -161,8 +161,11 @@
+ #define unfilled_slots_next	\
+   ((rtx *) obstack_next_free (&unfilled_slots_obstack))
+ 
+-/* Points to the label before the end of the function.  */
+-static rtx end_of_function_label;
++/* Points to the label before the end of the function, or before a
++   return insn.  */
++static rtx function_return_label;
++/* Likewise for a simple_return.  */
++static rtx function_simple_return_label;
+ 
+ /* Mapping between INSN_UID's and position in the code since INSN_UID's do
+    not always monotonically increase.  */
+@@ -175,7 +178,7 @@
+ static int resource_conflicts_p (struct resources *, struct resources *);
+ static int insn_references_resource_p (rtx, struct resources *, bool);
+ static int insn_sets_resource_p (rtx, struct resources *, bool);
+-static rtx find_end_label (void);
++static rtx find_end_label (rtx);
+ static rtx emit_delay_sequence (rtx, rtx, int);
+ static rtx add_to_delay_list (rtx, rtx);
+ static rtx delete_from_delay_slot (rtx);
+@@ -220,6 +223,15 @@
+ static void make_return_insns (rtx);
+ #endif
+ 
++/* Return true iff INSN is a simplejump, or any kind of return insn.  */
++
++static bool
++simplejump_or_return_p (rtx insn)
++{
++  return (JUMP_P (insn)
++	  && (simplejump_p (insn) || ANY_RETURN_P (PATTERN (insn))));
++}
++
+ /* Return TRUE if this insn should stop the search for insn to fill delay
+    slots.  LABELS_P indicates that labels should terminate the search.
+    In all cases, jumps terminate the search.  */
+@@ -335,23 +347,29 @@
+ 
+    ??? There may be a problem with the current implementation.  Suppose
+    we start with a bare RETURN insn and call find_end_label.  It may set
+-   end_of_function_label just before the RETURN.  Suppose the machinery
++   function_return_label just before the RETURN.  Suppose the machinery
+    is able to fill the delay slot of the RETURN insn afterwards.  Then
+-   end_of_function_label is no longer valid according to the property
++   function_return_label is no longer valid according to the property
+    described above and find_end_label will still return it unmodified.
+    Note that this is probably mitigated by the following observation:
+-   once end_of_function_label is made, it is very likely the target of
++   once function_return_label is made, it is very likely the target of
+    a jump, so filling the delay slot of the RETURN will be much more
+    difficult.  */
+ 
+ static rtx
+-find_end_label (void)
++find_end_label (rtx kind)
+ {
+   rtx insn;
++  rtx *plabel;
++
++  if (kind == ret_rtx)
++    plabel = &function_return_label;
++  else
++    plabel = &function_simple_return_label;
+ 
+   /* If we found one previously, return it.  */
+-  if (end_of_function_label)
+-    return end_of_function_label;
++  if (*plabel)
++    return *plabel;
+ 
+   /* Otherwise, see if there is a label at the end of the function.  If there
+      is, it must be that RETURN insns aren't needed, so that is our return
+@@ -366,44 +384,44 @@
+ 
+   /* When a target threads its epilogue we might already have a
+      suitable return insn.  If so put a label before it for the
+-     end_of_function_label.  */
++     function_return_label.  */
+   if (BARRIER_P (insn)
+       && JUMP_P (PREV_INSN (insn))
+-      && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN)
++      && PATTERN (PREV_INSN (insn)) == kind)
+     {
+       rtx temp = PREV_INSN (PREV_INSN (insn));
+-      end_of_function_label = gen_label_rtx ();
+-      LABEL_NUSES (end_of_function_label) = 0;
++      rtx label = gen_label_rtx ();
++      LABEL_NUSES (label) = 0;
+ 
+       /* Put the label before an USE insns that may precede the RETURN insn.  */
+       while (GET_CODE (temp) == USE)
+ 	temp = PREV_INSN (temp);
+ 
+-      emit_label_after (end_of_function_label, temp);
++      emit_label_after (label, temp);
++      *plabel = label;
+     }
+ 
+   else if (LABEL_P (insn))
+-    end_of_function_label = insn;
++    *plabel = insn;
+   else
+     {
+-      end_of_function_label = gen_label_rtx ();
+-      LABEL_NUSES (end_of_function_label) = 0;
++      rtx label = gen_label_rtx ();
++      LABEL_NUSES (label) = 0;
+       /* If the basic block reorder pass moves the return insn to
+ 	 some other place try to locate it again and put our
+-	 end_of_function_label there.  */
+-      while (insn && ! (JUMP_P (insn)
+-		        && (GET_CODE (PATTERN (insn)) == RETURN)))
++	 function_return_label there.  */
++      while (insn && ! (JUMP_P (insn) && (PATTERN (insn) == kind)))
+ 	insn = PREV_INSN (insn);
+       if (insn)
+ 	{
+ 	  insn = PREV_INSN (insn);
+ 
+-	  /* Put the label before an USE insns that may proceed the
++	  /* Put the label before an USE insns that may precede the
+ 	     RETURN insn.  */
+ 	  while (GET_CODE (insn) == USE)
+ 	    insn = PREV_INSN (insn);
+ 
+-	  emit_label_after (end_of_function_label, insn);
++	  emit_label_after (label, insn);
+ 	}
+       else
+ 	{
+@@ -413,19 +431,16 @@
+ 	      && ! HAVE_return
+ #endif
+ 	      )
+-	    {
+-	      /* The RETURN insn has its delay slot filled so we cannot
+-		 emit the label just before it.  Since we already have
+-		 an epilogue and cannot emit a new RETURN, we cannot
+-		 emit the label at all.  */
+-	      end_of_function_label = NULL_RTX;
+-	      return end_of_function_label;
+-	    }
++	    /* The RETURN insn has its delay slot filled so we cannot
++	       emit the label just before it.  Since we already have
++	       an epilogue and cannot emit a new RETURN, we cannot
++	       emit the label at all.  */
++	    return NULL_RTX;
+ #endif /* HAVE_epilogue */
+ 
+ 	  /* Otherwise, make a new label and emit a RETURN and BARRIER,
+ 	     if needed.  */
+-	  emit_label (end_of_function_label);
++	  emit_label (label);
+ #ifdef HAVE_return
+ 	  /* We don't bother trying to create a return insn if the
+ 	     epilogue has filled delay-slots; we would have to try and
+@@ -437,19 +452,21 @@
+ 	      /* The return we make may have delay slots too.  */
+ 	      rtx insn = gen_return ();
+ 	      insn = emit_jump_insn (insn);
++	      JUMP_LABEL (insn) = ret_rtx;
+ 	      emit_barrier ();
+ 	      if (num_delay_slots (insn) > 0)
+ 		obstack_ptr_grow (&unfilled_slots_obstack, insn);
+ 	    }
+ #endif
+ 	}
++      *plabel = label;
+     }
+ 
+   /* Show one additional use for this label so it won't go away until
+      we are done.  */
+-  ++LABEL_NUSES (end_of_function_label);
++  ++LABEL_NUSES (*plabel);
+ 
+-  return end_of_function_label;
++  return *plabel;
+ }
+ 
+ /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
+@@ -797,10 +814,8 @@
+   if ((next_trial == next_active_insn (JUMP_LABEL (insn))
+        && ! (next_trial == 0 && crtl->epilogue_delay_list != 0))
+       || (next_trial != 0
+-	  && JUMP_P (next_trial)
+-	  && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)
+-	  && (simplejump_p (next_trial)
+-	      || GET_CODE (PATTERN (next_trial)) == RETURN)))
++	  && simplejump_or_return_p (next_trial)
++	  && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)))
+     {
+       if (eligible_for_annul_false (insn, 0, trial, flags))
+ 	{
+@@ -819,13 +834,11 @@
+ 	 branch, thread our jump to the target of that branch.  Don't
+ 	 change this into a RETURN here, because it may not accept what
+ 	 we have in the delay slot.  We'll fix this up later.  */
+-      if (next_trial && JUMP_P (next_trial)
+-	  && (simplejump_p (next_trial)
+-	      || GET_CODE (PATTERN (next_trial)) == RETURN))
++      if (next_trial && simplejump_or_return_p (next_trial))
+ 	{
+ 	  rtx target_label = JUMP_LABEL (next_trial);
+-	  if (target_label == 0)
+-	    target_label = find_end_label ();
++	  if (ANY_RETURN_P (target_label))
++	    target_label = find_end_label (target_label);
+ 
+ 	  if (target_label)
+ 	    {
+@@ -866,7 +879,7 @@
+   if (JUMP_P (insn)
+       && (condjump_p (insn) || condjump_in_parallel_p (insn))
+       && INSN_UID (insn) <= max_uid
+-      && label != 0
++      && label != 0 && !ANY_RETURN_P (label)
+       && INSN_UID (label) <= max_uid)
+     flags
+       = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
+@@ -1038,7 +1051,7 @@
+     pat = XVECEXP (pat, 0, 0);
+ 
+   if (GET_CODE (pat) == RETURN)
+-    return target == 0 ? const_true_rtx : 0;
++    return ANY_RETURN_P (target) ? const_true_rtx : 0;
+ 
+   else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
+     return 0;
+@@ -1318,7 +1331,11 @@
+     }
+ 
+   /* Show the place to which we will be branching.  */
+-  *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
++  temp = JUMP_LABEL (XVECEXP (seq, 0, 0));
++  if (ANY_RETURN_P (temp))
++    *pnew_thread = temp;
++  else
++    *pnew_thread = next_active_insn (temp);
+ 
+   /* Add any new insns to the delay list and update the count of the
+      number of slots filled.  */
+@@ -1358,8 +1375,7 @@
+   /* We can't do anything if SEQ's delay insn isn't an
+      unconditional branch.  */
+ 
+-  if (! simplejump_p (XVECEXP (seq, 0, 0))
+-      && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN)
++  if (! simplejump_or_return_p (XVECEXP (seq, 0, 0)))
+     return delay_list;
+ 
+   for (i = 1; i < XVECLEN (seq, 0); i++)
+@@ -1827,7 +1843,7 @@
+   rtx insn;
+ 
+   /* We don't own the function end.  */
+-  if (thread == 0)
++  if (ANY_RETURN_P (thread))
+     return 0;
+ 
+   /* Get the first active insn, or THREAD, if it is an active insn.  */
+@@ -2245,7 +2261,8 @@
+ 	  && (!JUMP_P (insn)
+ 	      || ((condjump_p (insn) || condjump_in_parallel_p (insn))
+ 		  && ! simplejump_p (insn)
+-		  && JUMP_LABEL (insn) != 0)))
++		  && JUMP_LABEL (insn) != 0
++		  && !ANY_RETURN_P (JUMP_LABEL (insn)))))
+ 	{
+ 	  /* Invariant: If insn is a JUMP_INSN, the insn's jump
+ 	     label.  Otherwise, zero.  */
+@@ -2270,7 +2287,7 @@
+ 		target = JUMP_LABEL (insn);
+ 	    }
+ 
+-	  if (target == 0)
++	  if (target == 0 || ANY_RETURN_P (target))
+ 	    for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
+ 	      {
+ 		next_trial = next_nonnote_insn (trial);
+@@ -2349,6 +2366,7 @@
+ 	      && JUMP_P (trial)
+ 	      && simplejump_p (trial)
+ 	      && (target == 0 || JUMP_LABEL (trial) == target)
++	      && !ANY_RETURN_P (JUMP_LABEL (trial))
+ 	      && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
+ 	      && ! (NONJUMP_INSN_P (next_trial)
+ 		    && GET_CODE (PATTERN (next_trial)) == SEQUENCE)
+@@ -2371,7 +2389,7 @@
+ 	      if (new_label != 0)
+ 		new_label = get_label_before (new_label);
+ 	      else
+-		new_label = find_end_label ();
++		new_label = find_end_label (simple_return_rtx);
+ 
+ 	      if (new_label)
+ 	        {
+@@ -2503,7 +2521,8 @@
+ 
+ /* Follow any unconditional jump at LABEL;
+    return the ultimate label reached by any such chain of jumps.
+-   Return null if the chain ultimately leads to a return instruction.
++   Return a suitable return rtx if the chain ultimately leads to a
++   return instruction.
+    If LABEL is not followed by a jump, return LABEL.
+    If the chain loops or we can't find end, return LABEL,
+    since that tells caller to avoid changing the insn.  */
+@@ -2518,6 +2537,7 @@
+ 
+   for (depth = 0;
+        (depth < 10
++	&& !ANY_RETURN_P (value)
+ 	&& (insn = next_active_insn (value)) != 0
+ 	&& JUMP_P (insn)
+ 	&& ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn)
+@@ -2527,18 +2547,22 @@
+ 	&& BARRIER_P (next));
+        depth++)
+     {
+-      rtx tem;
++      rtx this_label = JUMP_LABEL (insn);
+ 
+       /* If we have found a cycle, make the insn jump to itself.  */
+-      if (JUMP_LABEL (insn) == label)
++      if (this_label == label)
+ 	return label;
+ 
+-      tem = next_active_insn (JUMP_LABEL (insn));
+-      if (tem && (GET_CODE (PATTERN (tem)) == ADDR_VEC
++      if (!ANY_RETURN_P (this_label))
++	{
++	  rtx tem = next_active_insn (this_label);
++	  if (tem
++	      && (GET_CODE (PATTERN (tem)) == ADDR_VEC
+ 		  || GET_CODE (PATTERN (tem)) == ADDR_DIFF_VEC))
+-	break;
++	    break;
++	}
+ 
+-      value = JUMP_LABEL (insn);
++      value = this_label;
+     }
+   if (depth == 10)
+     return label;
+@@ -2901,6 +2925,7 @@
+      arithmetic insn after the jump insn and put the arithmetic insn in the
+      delay slot.  If we can't do this, return.  */
+   if (delay_list == 0 && likely && new_thread
++      && !ANY_RETURN_P (new_thread)
+       && NONJUMP_INSN_P (new_thread)
+       && GET_CODE (PATTERN (new_thread)) != ASM_INPUT
+       && asm_noperands (PATTERN (new_thread)) < 0)
+@@ -2985,16 +3010,14 @@
+ 
+       gcc_assert (thread_if_true);
+ 
+-      if (new_thread && JUMP_P (new_thread)
+-	  && (simplejump_p (new_thread)
+-	      || GET_CODE (PATTERN (new_thread)) == RETURN)
++      if (new_thread && simplejump_or_return_p (new_thread)
+ 	  && redirect_with_delay_list_safe_p (insn,
+ 					      JUMP_LABEL (new_thread),
+ 					      delay_list))
+ 	new_thread = follow_jumps (JUMP_LABEL (new_thread));
+ 
+-      if (new_thread == 0)
+-	label = find_end_label ();
++      if (ANY_RETURN_P (new_thread))
++	label = find_end_label (new_thread);
+       else if (LABEL_P (new_thread))
+ 	label = new_thread;
+       else
+@@ -3340,11 +3363,12 @@
+ 	 group of consecutive labels.  */
+       if (JUMP_P (insn)
+ 	  && (condjump_p (insn) || condjump_in_parallel_p (insn))
+-	  && (target_label = JUMP_LABEL (insn)) != 0)
++	  && (target_label = JUMP_LABEL (insn)) != 0
++	  && !ANY_RETURN_P (target_label))
+ 	{
+ 	  target_label = skip_consecutive_labels (follow_jumps (target_label));
+-	  if (target_label == 0)
+-	    target_label = find_end_label ();
++	  if (ANY_RETURN_P (target_label))
++	    target_label = find_end_label (target_label);
+ 
+ 	  if (target_label && next_active_insn (target_label) == next
+ 	      && ! condjump_in_parallel_p (insn))
+@@ -3359,9 +3383,8 @@
+ 	  /* See if this jump conditionally branches around an unconditional
+ 	     jump.  If so, invert this jump and point it to the target of the
+ 	     second jump.  */
+-	  if (next && JUMP_P (next)
++	  if (next && simplejump_or_return_p (next)
+ 	      && any_condjump_p (insn)
+-	      && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
+ 	      && target_label
+ 	      && next_active_insn (target_label) == next_active_insn (next)
+ 	      && no_labels_between_p (insn, next))
+@@ -3403,8 +3426,7 @@
+ 	 Don't do this if we expect the conditional branch to be true, because
+ 	 we would then be making the more common case longer.  */
+ 
+-      if (JUMP_P (insn)
+-	  && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
++      if (simplejump_or_return_p (insn)
+ 	  && (other = prev_active_insn (insn)) != 0
+ 	  && any_condjump_p (other)
+ 	  && no_labels_between_p (other, insn)
+@@ -3445,10 +3467,10 @@
+ 	 Only do so if optimizing for size since this results in slower, but
+ 	 smaller code.  */
+       if (optimize_function_for_size_p (cfun)
+-	  && GET_CODE (PATTERN (delay_insn)) == RETURN
++	  && ANY_RETURN_P (PATTERN (delay_insn))
+ 	  && next
+ 	  && JUMP_P (next)
+-	  && GET_CODE (PATTERN (next)) == RETURN)
++	  && PATTERN (next) == PATTERN (delay_insn))
+ 	{
+ 	  rtx after;
+ 	  int i;
+@@ -3487,14 +3509,16 @@
+ 	continue;
+ 
+       target_label = JUMP_LABEL (delay_insn);
++      if (target_label && ANY_RETURN_P (target_label))
++	continue;
+ 
+       if (target_label)
+ 	{
+ 	  /* If this jump goes to another unconditional jump, thread it, but
+ 	     don't convert a jump into a RETURN here.  */
+ 	  trial = skip_consecutive_labels (follow_jumps (target_label));
+-	  if (trial == 0)
+-	    trial = find_end_label ();
++	  if (ANY_RETURN_P (trial))
++	    trial = find_end_label (trial);
+ 
+ 	  if (trial && trial != target_label
+ 	      && redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
+@@ -3517,7 +3541,7 @@
+ 		 later incorrectly compute register live/death info.  */
+ 	      rtx tmp = next_active_insn (trial);
+ 	      if (tmp == 0)
+-		tmp = find_end_label ();
++		tmp = find_end_label (simple_return_rtx);
+ 
+ 	      if (tmp)
+ 	        {
+@@ -3537,14 +3561,12 @@
+ 	     delay list and that insn is redundant, thread the jump.  */
+ 	  if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
+ 	      && XVECLEN (PATTERN (trial), 0) == 2
+-	      && JUMP_P (XVECEXP (PATTERN (trial), 0, 0))
+-	      && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0))
+-		  || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN)
++	      && simplejump_or_return_p (XVECEXP (PATTERN (trial), 0, 0))
+ 	      && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0))
+ 	    {
+ 	      target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0));
+-	      if (target_label == 0)
+-		target_label = find_end_label ();
++	      if (ANY_RETURN_P (target_label))
++		target_label = find_end_label (target_label);
+ 
+ 	      if (target_label
+ 	          && redirect_with_delay_slots_safe_p (delay_insn, target_label,
+@@ -3622,16 +3644,15 @@
+ 	 a RETURN here.  */
+       if (! INSN_ANNULLED_BRANCH_P (delay_insn)
+ 	  && any_condjump_p (delay_insn)
+-	  && next && JUMP_P (next)
+-	  && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
++	  && next && simplejump_or_return_p (next)
+ 	  && next_active_insn (target_label) == next_active_insn (next)
+ 	  && no_labels_between_p (insn, next))
+ 	{
+ 	  rtx label = JUMP_LABEL (next);
+ 	  rtx old_label = JUMP_LABEL (delay_insn);
+ 
+-	  if (label == 0)
+-	    label = find_end_label ();
++	  if (ANY_RETURN_P (label))
++	    label = find_end_label (label);
+ 
+ 	  /* find_end_label can generate a new label. Check this first.  */
+ 	  if (label
+@@ -3692,7 +3713,8 @@
+ make_return_insns (rtx first)
+ {
+   rtx insn, jump_insn, pat;
+-  rtx real_return_label = end_of_function_label;
++  rtx real_return_label = function_return_label;
++  rtx real_simple_return_label = function_simple_return_label;
+   int slots, i;
+ 
+ #ifdef DELAY_SLOTS_FOR_EPILOGUE
+@@ -3707,18 +3729,25 @@
+ #endif
+ 
+   /* See if there is a RETURN insn in the function other than the one we
+-     made for END_OF_FUNCTION_LABEL.  If so, set up anything we can't change
++     made for FUNCTION_RETURN_LABEL.  If so, set up anything we can't change
+      into a RETURN to jump to it.  */
+   for (insn = first; insn; insn = NEXT_INSN (insn))
+-    if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN)
++    if (JUMP_P (insn) && ANY_RETURN_P (PATTERN (insn)))
+       {
+-	real_return_label = get_label_before (insn);
++	rtx t = get_label_before (insn);
++	if (PATTERN (insn) == ret_rtx)
++	  real_return_label = t;
++	else
++	  real_simple_return_label = t;
+ 	break;
+       }
+ 
+   /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
+-     was equal to END_OF_FUNCTION_LABEL.  */
+-  LABEL_NUSES (real_return_label)++;
++     was equal to FUNCTION_RETURN_LABEL.  */
++  if (real_return_label)
++    LABEL_NUSES (real_return_label)++;
++  if (real_simple_return_label)
++    LABEL_NUSES (real_simple_return_label)++;
+ 
+   /* Clear the list of insns to fill so we can use it.  */
+   obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
+@@ -3726,13 +3755,27 @@
+   for (insn = first; insn; insn = NEXT_INSN (insn))
+     {
+       int flags;
++      rtx kind, real_label;
+ 
+       /* Only look at filled JUMP_INSNs that go to the end of function
+ 	 label.  */
+       if (!NONJUMP_INSN_P (insn)
+ 	  || GET_CODE (PATTERN (insn)) != SEQUENCE
+-	  || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0))
+-	  || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label)
++	  || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0)))
++	continue;
++
++      if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) == function_return_label)
++	{
++	  kind = ret_rtx;
++	  real_label = real_return_label;
++	}
++      else if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0))
++	       == function_simple_return_label)
++	{
++	  kind = simple_return_rtx;
++	  real_label = real_simple_return_label;
++	}
++      else
+ 	continue;
+ 
+       pat = PATTERN (insn);
+@@ -3740,14 +3783,12 @@
+ 
+       /* If we can't make the jump into a RETURN, try to redirect it to the best
+ 	 RETURN and go on to the next insn.  */
+-      if (! reorg_redirect_jump (jump_insn, NULL_RTX))
++      if (! reorg_redirect_jump (jump_insn, kind))
+ 	{
+ 	  /* Make sure redirecting the jump will not invalidate the delay
+ 	     slot insns.  */
+-	  if (redirect_with_delay_slots_safe_p (jump_insn,
+-						real_return_label,
+-						insn))
+-	    reorg_redirect_jump (jump_insn, real_return_label);
++	  if (redirect_with_delay_slots_safe_p (jump_insn, real_label, insn))
++	    reorg_redirect_jump (jump_insn, real_label);
+ 	  continue;
+ 	}
+ 
+@@ -3787,7 +3828,7 @@
+ 	 RETURN, delete the SEQUENCE and output the individual insns,
+ 	 followed by the RETURN.  Then set things up so we try to find
+ 	 insns for its delay slots, if it needs some.  */
+-      if (GET_CODE (PATTERN (jump_insn)) == RETURN)
++      if (ANY_RETURN_P (PATTERN (jump_insn)))
+ 	{
+ 	  rtx prev = PREV_INSN (insn);
+ 
+@@ -3804,13 +3845,16 @@
+       else
+ 	/* It is probably more efficient to keep this with its current
+ 	   delay slot as a branch to a RETURN.  */
+-	reorg_redirect_jump (jump_insn, real_return_label);
++	reorg_redirect_jump (jump_insn, real_label);
+     }
+ 
+   /* Now delete REAL_RETURN_LABEL if we never used it.  Then try to fill any
+      new delay slots we have created.  */
+-  if (--LABEL_NUSES (real_return_label) == 0)
++  if (real_return_label != NULL_RTX && --LABEL_NUSES (real_return_label) == 0)
+     delete_related_insns (real_return_label);
++  if (real_simple_return_label != NULL_RTX
++      && --LABEL_NUSES (real_simple_return_label) == 0)
++    delete_related_insns (real_simple_return_label);
+ 
+   fill_simple_delay_slots (1);
+   fill_simple_delay_slots (0);
+@@ -3878,7 +3922,7 @@
+   init_resource_info (epilogue_insn);
+ 
+   /* Show we haven't computed an end-of-function label yet.  */
+-  end_of_function_label = 0;
++  function_return_label = function_simple_return_label = NULL_RTX;
+ 
+   /* Initialize the statistics for this function.  */
+   memset (num_insns_needing_delays, 0, sizeof num_insns_needing_delays);
+@@ -3900,11 +3944,23 @@
+   /* If we made an end of function label, indicate that it is now
+      safe to delete it by undoing our prior adjustment to LABEL_NUSES.
+      If it is now unused, delete it.  */
+-  if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0)
+-    delete_related_insns (end_of_function_label);
++  if (function_return_label && --LABEL_NUSES (function_return_label) == 0)
++    delete_related_insns (function_return_label);
++  if (function_simple_return_label
++      && --LABEL_NUSES (function_simple_return_label) == 0)
++    delete_related_insns (function_simple_return_label);
+ 
++#if defined HAVE_return || defined HAVE_simple_return
++  if (
+ #ifdef HAVE_return
+-  if (HAVE_return && end_of_function_label != 0)
++      (HAVE_return && function_return_label != 0)
++#else
++      0
++#endif
++#ifdef HAVE_simple_return
++      || (HAVE_simple_return && function_simple_return_label != 0)
++#endif
++      )
+     make_return_insns (first);
+ #endif
+ 
+
+=== modified file 'gcc/resource.c'
+--- old/gcc/resource.c	2009-11-25 10:55:54 +0000
++++ new/gcc/resource.c	2011-01-05 12:12:18 +0000
+@@ -495,6 +495,8 @@
+ 		  || GET_CODE (PATTERN (this_jump_insn)) == RETURN)
+ 		{
+ 		  next = JUMP_LABEL (this_jump_insn);
++		  if (next && ANY_RETURN_P (next))
++		    next = NULL_RTX;
+ 		  if (jump_insn == 0)
+ 		    {
+ 		      jump_insn = insn;
+@@ -562,9 +564,10 @@
+ 		  AND_COMPL_HARD_REG_SET (scratch, needed.regs);
+ 		  AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch);
+ 
+-		  find_dead_or_set_registers (JUMP_LABEL (this_jump_insn),
+-					      &target_res, 0, jump_count,
+-					      target_set, needed);
++		  if (!ANY_RETURN_P (JUMP_LABEL (this_jump_insn)))
++		    find_dead_or_set_registers (JUMP_LABEL (this_jump_insn),
++						&target_res, 0, jump_count,
++						target_set, needed);
+ 		  find_dead_or_set_registers (next,
+ 					      &fallthrough_res, 0, jump_count,
+ 					      set, needed);
+@@ -1097,6 +1100,8 @@
+       struct resources new_resources;
+       rtx stop_insn = next_active_insn (jump_insn);
+ 
++      if (jump_target && ANY_RETURN_P (jump_target))
++	jump_target = NULL_RTX;
+       mark_target_live_regs (insns, next_active_insn (jump_target),
+ 			     &new_resources);
+       CLEAR_RESOURCE (&set);
+
+=== modified file 'gcc/rtl.c'
+--- old/gcc/rtl.c	2010-12-13 10:05:52 +0000
++++ new/gcc/rtl.c	2011-01-05 12:12:18 +0000
+@@ -256,6 +256,8 @@
+     case CODE_LABEL:
+     case PC:
+     case CC0:
++    case RETURN:
++    case SIMPLE_RETURN:
+     case SCRATCH:
+       /* SCRATCH must be shared because they represent distinct values.  */
+       return orig;
+
+=== modified file 'gcc/rtl.def'
+--- old/gcc/rtl.def	2010-04-02 18:54:46 +0000
++++ new/gcc/rtl.def	2011-01-05 12:12:18 +0000
+@@ -296,6 +296,10 @@
+ 
+ DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
+ 
++/* A plain return, to be used on paths that are reached without going
++   through the function prologue.  */
++DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
++
+ /* Special for EH return from subroutine.  */
+ 
+ DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
+
+=== modified file 'gcc/rtl.h'
+--- old/gcc/rtl.h	2010-11-16 22:17:17 +0000
++++ new/gcc/rtl.h	2011-01-05 12:12:18 +0000
+@@ -411,6 +411,10 @@
+   (JUMP_P (INSN) && (GET_CODE (PATTERN (INSN)) == ADDR_VEC || \
+ 		     GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC))
+ 
++/* Predicate yielding nonzero iff X is a return or simple_preturn.  */
++#define ANY_RETURN_P(X) \
++  (GET_CODE (X) == RETURN || GET_CODE (X) == SIMPLE_RETURN)
++
+ /* 1 if X is a unary operator.  */
+ 
+ #define UNARY_P(X)   \
+@@ -1998,6 +2002,8 @@
+ {
+   GR_PC,
+   GR_CC0,
++  GR_RETURN,
++  GR_SIMPLE_RETURN,
+   GR_STACK_POINTER,
+   GR_FRAME_POINTER,
+ /* For register elimination to work properly these hard_frame_pointer_rtx,
+@@ -2032,6 +2038,8 @@
+ 
+ /* Standard pieces of rtx, to be substituted directly into things.  */
+ #define pc_rtx                  (global_rtl[GR_PC])
++#define ret_rtx                 (global_rtl[GR_RETURN])
++#define simple_return_rtx       (global_rtl[GR_SIMPLE_RETURN])
+ #define cc0_rtx                 (global_rtl[GR_CC0])
+ 
+ /* All references to certain hard regs, except those created
+
+=== modified file 'gcc/rtlanal.c'
+--- old/gcc/rtlanal.c	2010-11-16 22:17:17 +0000
++++ new/gcc/rtlanal.c	2011-01-05 12:12:18 +0000
+@@ -2673,6 +2673,7 @@
+ 
+   if (JUMP_P (insn)
+       && (label = JUMP_LABEL (insn)) != NULL_RTX
++      && !ANY_RETURN_P (label)
+       && (table = next_active_insn (label)) != NULL_RTX
+       && JUMP_TABLE_DATA_P (table))
+     {
+
+=== modified file 'gcc/sched-int.h'
+--- old/gcc/sched-int.h	2010-06-02 16:31:39 +0000
++++ new/gcc/sched-int.h	2011-01-05 12:12:18 +0000
+@@ -199,7 +199,7 @@
+ 
+ extern void ebb_compute_jump_reg_dependencies (rtx, regset, regset, regset);
+ 
+-extern edge find_fallthru_edge (basic_block);
++extern edge find_fallthru_edge_from (basic_block);
+ 
+ extern void (* sched_init_only_bb) (basic_block, basic_block);
+ extern basic_block (* sched_split_block) (basic_block, rtx);
+
+=== modified file 'gcc/sched-vis.c'
+--- old/gcc/sched-vis.c	2009-11-25 10:55:54 +0000
++++ new/gcc/sched-vis.c	2011-01-05 12:12:18 +0000
+@@ -549,6 +549,9 @@
+     case RETURN:
+       sprintf (buf, "return");
+       break;
++    case SIMPLE_RETURN:
++      sprintf (buf, "simple_return");
++      break;
+     case CALL:
+       print_exp (buf, x, verbose);
+       break;
+
+=== modified file 'gcc/sel-sched-ir.c'
+--- old/gcc/sel-sched-ir.c	2010-08-31 11:52:01 +0000
++++ new/gcc/sel-sched-ir.c	2011-01-05 12:12:18 +0000
+@@ -686,7 +686,7 @@
+ 
+       /* Find fallthrough edge.  */
+       gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb);
+-      candidate = find_fallthru_edge (BLOCK_FOR_INSN (insn)->prev_bb);
++      candidate = find_fallthru_edge_from (BLOCK_FOR_INSN (insn)->prev_bb);
+ 
+       if (!candidate
+           || (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn)
+
+=== modified file 'gcc/sel-sched.c'
+--- old/gcc/sel-sched.c	2010-11-12 15:47:38 +0000
++++ new/gcc/sel-sched.c	2011-01-05 12:12:18 +0000
+@@ -617,8 +617,8 @@
+   if (bb == BLOCK_FOR_INSN (succ))
+     return true;
+ 
+-  if (find_fallthru_edge (bb))
+-    bb = find_fallthru_edge (bb)->dest;
++  if (find_fallthru_edge_from (bb))
++    bb = find_fallthru_edge_from (bb)->dest;
+   else
+     return false;
+ 
+@@ -4911,7 +4911,7 @@
+   next = PREV_INSN (insn);
+   BND_TO (bnd) = insn;
+ 
+-  ft_edge = find_fallthru_edge (block_from);
++  ft_edge = find_fallthru_edge_from (block_from);
+   block_next = ft_edge->dest;
+   /* There must be a fallthrough block (or where should go
+   control flow in case of false jump predicate otherwise?).  */
+
+=== modified file 'gcc/vec.h'
+--- old/gcc/vec.h	2010-01-09 14:46:25 +0000
++++ new/gcc/vec.h	2011-01-05 12:12:18 +0000
+@@ -188,6 +188,18 @@
+ 
+ #define VEC_iterate(T,V,I,P)	(VEC_OP(T,base,iterate)(VEC_BASE(V),I,&(P)))
+ 
++/* Convenience macro for forward iteration.  */
++
++#define FOR_EACH_VEC_ELT(T, V, I, P)		\
++  for (I = 0; VEC_iterate (T, (V), (I), (P)); ++(I))
++
++/* Convenience macro for reverse iteration.  */
++
++#define FOR_EACH_VEC_ELT_REVERSE(T,V,I,P) \
++  for (I = VEC_length (T, (V)) - 1;           \
++       VEC_iterate (T, (V), (I), (P));	  \
++       (I)--)
++
+ /* Allocate new vector.
+    VEC(T,A) *VEC_T_A_alloc(int reserve);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch
new file mode 100644
index 0000000000..47b897d5e7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch
@@ -0,0 +1,4236 @@
+2010-12-03  Yao Qi  <yao@codesourcery.com>
+
+	* config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix
+	regressions.
+	* config/arm/ldmstm.md: Regenreate.
+
+2010-12-03  Yao Qi  <yao@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2010-08-02  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/40457
+	* config/arm/arm.h (arm_regs_in_sequence): Declare.
+	* config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq,
+	load_multiple_sequence, store_multiple_sequence): Delete
+	declarations.
+	(arm_gen_load_multiple, arm_gen_store_multiple): Adjust
+	declarations.
+	* config/arm/ldmstm.md: New file.
+	* config/arm/arm.c (arm_regs_in_sequence): New array.
+	(load_multiple_sequence): Now static.  New args SAVED_ORDER,
+	CHECK_REGS.  All callers changed.
+	If SAVED_ORDER is nonnull, copy the computed order into it.
+	If CHECK_REGS is false, don't sort REGS.  Handle Thumb mode.
+	(store_multiple_sequence): Now static.  New args NOPS_TOTAL,
+	SAVED_ORDER, REG_RTXS and CHECK_REGS.  All callers changed.
+	If SAVED_ORDER is nonnull, copy the computed order into it.
+	If CHECK_REGS is false, don't sort REGS.  Set up REG_RTXS just
+	like REGS.  Handle Thumb mode.
+	(arm_gen_load_multiple_1): New function, broken out of
+	arm_gen_load_multiple.
+	(arm_gen_store_multiple_1): New function, broken out of
+	arm_gen_store_multiple.
+	(arm_gen_multiple_op): New function, with code from
+	arm_gen_load_multiple and arm_gen_store_multiple moved here.
+	(arm_gen_load_multiple, arm_gen_store_multiple): Now just
+	wrappers around arm_gen_multiple_op.  Remove argument UP, all callers
+	changed.
+	(gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions.
+	* config/arm/predicates.md (commutative_binary_operator): New.
+	(load_multiple_operation, store_multiple_operation): Handle more
+	variants of these patterns with different starting offsets.  Handle
+	Thumb-1.
+	* config/arm/arm.md: Include "ldmstm.md".
+	(ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2,
+	ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1,
+	stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related
+	peepholes): Delete.
+	* config/arm/ldmstm.md: New file.
+	* config/arm/arm-ldmstm.ml: New file.
+
+	* config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the
+	if statement which adds extra costs to frame-related expressions.
+
+	2010-05-06  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* config/arm/arm.h (MAX_LDM_STM_OPS): New macro.
+	* config/arm/arm.c (multiple_operation_profitable_p,
+	compute_offset_order): New static functions.
+	(load_multiple_sequence, store_multiple_sequence): Use them.
+	Replace constant 4 with MAX_LDM_STM_OPS.  Compute order[0] from
+	memory offsets, not register numbers.
+	(emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS.
+
+	2010-04-16  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* recog.h (struct recog_data): New field is_operator.
+	(struct insn_operand_data): New field is_operator.
+	* recog.c (extract_insn): Set recog_data.is_operator.
+	* genoutput.c (output_operand_data): Emit code to set the
+	is_operator field.
+	* reload.c (find_reloads): Use it rather than testing for an
+	empty constraint string.
+
+=== added file 'gcc/config/arm/arm-ldmstm.ml'
+--- old/gcc/config/arm/arm-ldmstm.ml	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/arm-ldmstm.ml	2010-11-16 13:08:47 +0000
+@@ -0,0 +1,333 @@
++(* Auto-generate ARM ldm/stm patterns
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   Contributed by CodeSourcery.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it under
++   the terms of the GNU General Public License as published by the Free
++   Software Foundation; either version 3, or (at your option) any later
++   version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or
++   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++   for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.
++
++   This is an O'Caml program.  The O'Caml compiler is available from:
++
++     http://caml.inria.fr/
++
++   Or from your favourite OS's friendly packaging system. Tested with version
++   3.09.2, though other versions will probably work too.
++
++   Run with:
++     ocaml arm-ldmstm.ml >/path/to/gcc/config/arm/ldmstm.ml
++*)
++
++type amode = IA | IB | DA | DB
++
++type optype = IN | OUT | INOUT
++
++let rec string_of_addrmode addrmode =
++  match addrmode with
++    IA -> "ia" | IB -> "ib" | DA -> "da" | DB -> "db"
++
++let rec initial_offset addrmode nregs =
++  match addrmode with
++    IA -> 0
++  | IB -> 4
++  | DA -> -4 * nregs + 4
++  | DB -> -4 * nregs
++
++let rec final_offset addrmode nregs =
++  match addrmode with
++    IA -> nregs * 4
++  | IB -> nregs * 4
++  | DA -> -4 * nregs
++  | DB -> -4 * nregs
++
++let constr thumb =
++  if thumb then "l" else "rk"
++
++let inout_constr op_type =
++  match op_type with
++  OUT -> "="
++  | INOUT -> "+&"
++  | IN -> ""
++
++let destreg nregs first op_type thumb =
++  if not first then
++    Printf.sprintf "(match_dup %d)" (nregs)
++  else
++    Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")")
++    (nregs) (inout_constr op_type) (constr thumb)
++
++let write_ldm_set thumb nregs offset opnr first =
++  let indent = "     " in
++  Printf.printf "%s" (if first then "    [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr;
++  Printf.printf "%s     (mem:SI " indent;
++  begin if offset != 0 then Printf.printf "(plus:SI " end;
++  Printf.printf "%s" (destreg nregs first IN thumb);
++  begin if offset != 0 then Printf.printf "\n%s             (const_int %d))" indent offset end;
++  Printf.printf "))"
++
++let write_stm_set thumb nregs offset opnr first =
++  let indent = "     " in
++  Printf.printf "%s" (if first then "    [" else indent);
++  Printf.printf "(set (mem:SI ";
++  begin if offset != 0 then Printf.printf "(plus:SI " end;
++  Printf.printf "%s" (destreg nregs first IN thumb);
++  begin if offset != 0 then Printf.printf " (const_int %d))" offset end;
++  Printf.printf ")\n%s     (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr 
++
++let write_ldm_peep_set extra_indent nregs opnr first =
++  let indent = "   " ^ extra_indent in
++  Printf.printf "%s" (if first then extra_indent ^ "  [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr;
++  Printf.printf "%s     (match_operand:SI %d \"memory_operand\" \"\"))" indent (nregs + opnr)
++
++let write_stm_peep_set extra_indent nregs opnr first =
++  let indent = "   " ^ extra_indent in
++  Printf.printf "%s" (if first then extra_indent ^ "  [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"memory_operand\" \"\")\n" (nregs + opnr);
++  Printf.printf "%s     (match_operand:SI %d \"s_register_operand\" \"\"))" indent opnr
++
++let write_any_load optype nregs opnr first =
++  let indent = "   " in
++  Printf.printf "%s" (if first then "  [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr;
++  Printf.printf "%s     (match_operand:SI %d \"%s\" \"\"))" indent (nregs * 2 + opnr) optype
++
++let write_const_store nregs opnr first =
++  let indent = "   " in
++  Printf.printf "%s(set (match_operand:SI %d \"memory_operand\" \"\")\n" indent (nregs + opnr);
++  Printf.printf "%s     (match_dup %d))" indent opnr
++
++let write_const_stm_peep_set nregs opnr first =
++  write_any_load "const_int_operand" nregs opnr first;
++  Printf.printf "\n";
++  write_const_store nregs opnr false
++
++  
++let rec write_pat_sets func opnr offset first n_left =
++  func offset opnr first;
++  begin
++    if n_left > 1 then begin
++      Printf.printf "\n";
++      write_pat_sets func (opnr + 1) (offset + 4) false (n_left - 1);
++    end else
++      Printf.printf "]"
++  end
++
++let rec write_peep_sets func opnr first n_left =
++  func opnr first;
++  begin
++    if n_left > 1 then begin
++      Printf.printf "\n";
++      write_peep_sets func (opnr + 1) false (n_left - 1);
++    end
++  end
++    
++let can_thumb addrmode update is_store =
++  match addrmode, update, is_store with
++    (* Thumb1 mode only supports IA with update.  However, for LDMIA,
++       if the address register also appears in the list of loaded
++       registers, the loaded value is stored, hence the RTL pattern
++       to describe such an insn does not have an update.  We check
++       in the match_parallel predicate that the condition described
++       above is met.  *)
++    IA, _, false -> true
++  | IA, true, true -> true
++  | _ -> false
++
++let target addrmode thumb =
++  match addrmode, thumb with
++    IA, true -> "TARGET_THUMB1"
++  | IA, false -> "TARGET_32BIT"
++  | DB, false -> "TARGET_32BIT"
++  | _, false -> "TARGET_ARM"
++
++let write_pattern_1 name ls addrmode nregs write_set_fn update thumb =
++  let astr = string_of_addrmode addrmode in
++  Printf.printf "(define_insn \"*%s%s%d_%s%s\"\n"
++    (if thumb then "thumb_" else "") name nregs astr
++    (if update then "_update" else "");
++  Printf.printf "  [(match_parallel 0 \"%s_multiple_operation\"\n" ls;
++  begin
++    if update then begin
++      Printf.printf "    [(set %s\n          (plus:SI "
++	(destreg 1 true OUT thumb); (*destreg 2 true IN thumb*)
++      Printf.printf "(match_operand:SI 2 \"s_register_operand\" \"1\")";
++      Printf.printf " (const_int %d)))\n"
++	(final_offset addrmode nregs)
++    end
++  end;
++  write_pat_sets
++    (write_set_fn thumb (if update then 2 else 1)) (if update then 3 else 2)
++    (initial_offset addrmode nregs)
++    (not update) nregs;
++  Printf.printf ")]\n  \"%s && XVECLEN (operands[0], 0) == %d\"\n"
++    (target addrmode thumb)
++    (if update then nregs + 1 else nregs);
++  Printf.printf "  \"%s%%(%s%%)\\t%%%d%s, {"
++    name astr (1) (if update then "!" else "");
++  for n = 1 to nregs; do
++    Printf.printf "%%%d%s" (n+(if update then 2 else 1)) (if n < nregs then ", " else "")
++  done;
++  Printf.printf "}\"\n";
++  Printf.printf "  [(set_attr \"type\" \"%s%d\")" ls nregs;
++  begin if not thumb then
++    Printf.printf "\n   (set_attr \"predicable\" \"yes\")";
++  end;
++  Printf.printf "])\n\n"
++
++let write_ldm_pattern addrmode nregs update =
++  write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update false;
++  begin if can_thumb addrmode update false then
++    write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update true;
++  end
++
++let write_stm_pattern addrmode nregs update =
++  write_pattern_1 "stm" "store" addrmode nregs write_stm_set update false;
++  begin if can_thumb addrmode update true then
++    write_pattern_1 "stm" "store" addrmode nregs write_stm_set update true;
++  end
++
++let write_ldm_commutative_peephole thumb =
++  let nregs = 2 in
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs;
++  let indent = "   " in
++  if thumb then begin
++    Printf.printf "\n%s(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2);
++    Printf.printf "%s     (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1);
++    Printf.printf "%s      [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2);
++    Printf.printf "%s       (match_operand:SI %d \"s_register_operand\" \"\")]))]\n" indent (nregs * 2 + 3)
++  end else begin
++    Printf.printf "\n%s(parallel\n" indent;
++    Printf.printf "%s  [(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2);
++    Printf.printf "%s        (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1);
++    Printf.printf "%s         [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2);
++    Printf.printf "%s          (match_operand:SI %d \"s_register_operand\" \"\")]))\n" indent (nregs * 2 + 3);
++    Printf.printf "%s   (clobber (reg:CC CC_REGNUM))])]\n" indent
++  end;
++  Printf.printf "  \"(((operands[%d] == operands[0] && operands[%d] == operands[1])\n" (nregs * 2 + 2) (nregs * 2 + 3);
++  Printf.printf "     || (operands[%d] == operands[0] && operands[%d] == operands[1]))\n" (nregs * 2 + 3) (nregs * 2 + 2);
++  Printf.printf "    && peep2_reg_dead_p (%d, operands[0]) && peep2_reg_dead_p (%d, operands[1]))\"\n" (nregs + 1) (nregs + 1);
++  begin
++    if thumb then
++      Printf.printf "  [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))]\n"
++	(nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3)
++    else begin
++      Printf.printf "  [(parallel\n";
++      Printf.printf "    [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))\n"
++	(nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3);
++      Printf.printf "     (clobber (reg:CC CC_REGNUM))])]\n"
++    end
++  end;
++  Printf.printf "{\n  if (!gen_ldm_seq (operands, %d, true))\n    FAIL;\n" nregs;
++  Printf.printf "})\n\n"
++
++let write_ldm_peephole nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_ldm_seq (operands, %d, false))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let write_ldm_peephole_b nregs =
++  if nregs > 2 then begin
++    Printf.printf "(define_peephole2\n";
++    write_ldm_peep_set "" nregs 0 true;
++    Printf.printf "\n   (parallel\n";
++    write_peep_sets (write_ldm_peep_set "  " nregs) 1 true (nregs - 1);
++    Printf.printf "])]\n  \"\"\n  [(const_int 0)]\n{\n";
++    Printf.printf "  if (gen_ldm_seq (operands, %d, false))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++  end
++
++let write_stm_peephole nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_stm_peep_set "" nregs) 0 true nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let write_stm_peephole_b nregs =
++  if nregs > 2 then begin
++    Printf.printf "(define_peephole2\n";
++    write_stm_peep_set "" nregs 0 true;
++    Printf.printf "\n   (parallel\n";
++    write_peep_sets (write_stm_peep_set "" nregs) 1 true (nregs - 1);
++    Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++    Printf.printf "  if (gen_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++  end
++
++let write_const_stm_peephole_a nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_const_stm_peep_set nregs) 0 true nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_const_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let write_const_stm_peephole_b nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_any_load "const_int_operand" nregs) 0 true nregs;
++  Printf.printf "\n";
++  write_peep_sets (write_const_store nregs) 0 false nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_const_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let patterns () =
++  let addrmodes = [ IA; IB; DA; DB ]  in
++  let sizes = [ 4; 3; 2] in
++  List.iter
++    (fun n ->
++      List.iter
++	(fun addrmode ->
++	  write_ldm_pattern addrmode n false;
++	  write_ldm_pattern addrmode n true;
++	  write_stm_pattern addrmode n false;
++	  write_stm_pattern addrmode n true)
++	addrmodes;
++      write_ldm_peephole n;
++      write_ldm_peephole_b n;
++      write_const_stm_peephole_a n;
++      write_const_stm_peephole_b n;
++      write_stm_peephole n;)
++    sizes;
++  write_ldm_commutative_peephole false;
++  write_ldm_commutative_peephole true
++
++let print_lines = List.iter (fun s -> Format.printf "%s@\n" s)
++
++(* Do it.  *)
++
++let _ = 
++  print_lines [
++"/* ARM ldm/stm instruction patterns.  This file was automatically generated";
++"   using arm-ldmstm.ml.  Please do not edit manually.";
++"";
++"   Copyright (C) 2010 Free Software Foundation, Inc.";
++"   Contributed by CodeSourcery.";
++"";
++"   This file is part of GCC.";
++"";
++"   GCC is free software; you can redistribute it and/or modify it";
++"   under the terms of the GNU General Public License as published";
++"   by the Free Software Foundation; either version 3, or (at your";
++"   option) any later version.";
++"";
++"   GCC is distributed in the hope that it will be useful, but WITHOUT";
++"   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY";
++"   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public";
++"   License for more details.";
++"";
++"   You should have received a copy of the GNU General Public License and";
++"   a copy of the GCC Runtime Library Exception along with this program;";
++"   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see";
++"   <http://www.gnu.org/licenses/>.  */";
++""];
++  patterns ();
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-01-05 18:20:37 +0000
+@@ -100,14 +100,11 @@
+ extern int label_mentioned_p (rtx);
+ extern RTX_CODE minmax_code (rtx);
+ extern int adjacent_mem_locations (rtx, rtx);
+-extern int load_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *);
+-extern const char *emit_ldm_seq (rtx *, int);
+-extern int store_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *);
+-extern const char * emit_stm_seq (rtx *, int);
+-extern rtx arm_gen_load_multiple (int, int, rtx, int, int,
+-				  rtx, HOST_WIDE_INT *);
+-extern rtx arm_gen_store_multiple (int, int, rtx, int, int,
+-				   rtx, HOST_WIDE_INT *);
++extern bool gen_ldm_seq (rtx *, int, bool);
++extern bool gen_stm_seq (rtx *, int);
++extern bool gen_const_stm_seq (rtx *, int);
++extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
++extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
+ extern int arm_gen_movmemqi (rtx *);
+ extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
+ extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm.c	2011-01-05 18:20:37 +0000
+@@ -753,6 +753,12 @@
+   "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
+ };
+ 
++/* The register numbers in sequence, for passing to arm_gen_load_multiple.  */
++int arm_regs_in_sequence[] =
++{
++  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
++};
++
+ #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
+ #define streq(string1, string2) (strcmp (string1, string2) == 0)
+ 
+@@ -9680,142 +9686,16 @@
+   return 0;
+ }
+ 
+-int
+-load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
+-			HOST_WIDE_INT *load_offset)
+-{
+-  int unsorted_regs[4];
+-  HOST_WIDE_INT unsorted_offsets[4];
+-  int order[4];
+-  int base_reg = -1;
+-  int i;
+-
+-  if (low_irq_latency)
+-    return 0;
+-
+-  /* Can only handle 2, 3, or 4 insns at present,
+-     though could be easily extended if required.  */
+-  gcc_assert (nops >= 2 && nops <= 4);
+-
+-  memset (order, 0, 4 * sizeof (int));
+-
+-  /* Loop over the operands and check that the memory references are
+-     suitable (i.e. immediate offsets from the same base register).  At
+-     the same time, extract the target register, and the memory
+-     offsets.  */
+-  for (i = 0; i < nops; i++)
+-    {
+-      rtx reg;
+-      rtx offset;
+-
+-      /* Convert a subreg of a mem into the mem itself.  */
+-      if (GET_CODE (operands[nops + i]) == SUBREG)
+-	operands[nops + i] = alter_subreg (operands + (nops + i));
+-
+-      gcc_assert (GET_CODE (operands[nops + i]) == MEM);
+-
+-      /* Don't reorder volatile memory references; it doesn't seem worth
+-	 looking for the case where the order is ok anyway.  */
+-      if (MEM_VOLATILE_P (operands[nops + i]))
+-	return 0;
+-
+-      offset = const0_rtx;
+-
+-      if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
+-	   || (GET_CODE (reg) == SUBREG
+-	       && GET_CODE (reg = SUBREG_REG (reg)) == REG))
+-	  || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
+-	      && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
+-		   == REG)
+-		  || (GET_CODE (reg) == SUBREG
+-		      && GET_CODE (reg = SUBREG_REG (reg)) == REG))
+-	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
+-		  == CONST_INT)))
+-	{
+-	  if (i == 0)
+-	    {
+-	      base_reg = REGNO (reg);
+-	      unsorted_regs[0] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      order[0] = 0;
+-	    }
+-	  else
+-	    {
+-	      if (base_reg != (int) REGNO (reg))
+-		/* Not addressed from the same base register.  */
+-		return 0;
+-
+-	      unsorted_regs[i] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      if (unsorted_regs[i] < unsorted_regs[order[0]])
+-		order[0] = i;
+-	    }
+-
+-	  /* If it isn't an integer register, or if it overwrites the
+-	     base register but isn't the last insn in the list, then
+-	     we can't do this.  */
+-	  if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
+-	      || (i != nops - 1 && unsorted_regs[i] == base_reg))
+-	    return 0;
+-
+-	  unsorted_offsets[i] = INTVAL (offset);
+-	}
+-      else
+-	/* Not a suitable memory address.  */
+-	return 0;
+-    }
+-
+-  /* All the useful information has now been extracted from the
+-     operands into unsorted_regs and unsorted_offsets; additionally,
+-     order[0] has been set to the lowest numbered register in the
+-     list.  Sort the registers into order, and check that the memory
+-     offsets are ascending and adjacent.  */
+-
+-  for (i = 1; i < nops; i++)
+-    {
+-      int j;
+-
+-      order[i] = order[i - 1];
+-      for (j = 0; j < nops; j++)
+-	if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
+-	    && (order[i] == order[i - 1]
+-		|| unsorted_regs[j] < unsorted_regs[order[i]]))
+-	  order[i] = j;
+-
+-      /* Have we found a suitable register? if not, one must be used more
+-	 than once.  */
+-      if (order[i] == order[i - 1])
+-	return 0;
+-
+-      /* Is the memory address adjacent and ascending? */
+-      if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
+-	return 0;
+-    }
+-
+-  if (base)
+-    {
+-      *base = base_reg;
+-
+-      for (i = 0; i < nops; i++)
+-	regs[i] = unsorted_regs[order[i]];
+-
+-      *load_offset = unsorted_offsets[order[0]];
+-    }
+-
+-  if (unsorted_offsets[order[0]] == 0)
+-    return 1; /* ldmia */
+-
+-  if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
+-    return 2; /* ldmib */
+-
+-  if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
+-    return 3; /* ldmda */
+-
+-  if (unsorted_offsets[order[nops - 1]] == -4)
+-    return 4; /* ldmdb */
+-
++
++/* Return true iff it would be profitable to turn a sequence of NOPS loads
++   or stores (depending on IS_STORE) into a load-multiple or store-multiple
++   instruction.  ADD_OFFSET is nonzero if the base address register needs
++   to be modified with an add instruction before we can use it.  */
++
++static bool
++multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED,
++				 int nops, HOST_WIDE_INT add_offset)
++ {
+   /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
+      if the offset isn't small enough.  The reason 2 ldrs are faster
+      is because these ARMs are able to do more than one cache access
+@@ -9845,91 +9725,239 @@
+      We cheat here and test 'arm_ld_sched' which we currently know to
+      only be true for the ARM8, ARM9 and StrongARM.  If this ever
+      changes, then the test below needs to be reworked.  */
+-  if (nops == 2 && arm_ld_sched)
++  if (nops == 2 && arm_ld_sched && add_offset != 0)
++    return false;
++
++  return true;
++}
++
++/* Subroutine of load_multiple_sequence and store_multiple_sequence.
++   Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
++   an array ORDER which describes the sequence to use when accessing the
++   offsets that produces an ascending order.  In this sequence, each
++   offset must be larger by exactly 4 than the previous one.  ORDER[0]
++   must have been filled in with the lowest offset by the caller.
++   If UNSORTED_REGS is nonnull, it is an array of register numbers that
++   we use to verify that ORDER produces an ascending order of registers.
++   Return true if it was possible to construct such an order, false if
++   not.  */
++
++static bool
++compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order,
++		      int *unsorted_regs)
++{
++  int i;
++  for (i = 1; i < nops; i++)
++    {
++      int j;
++
++      order[i] = order[i - 1];
++      for (j = 0; j < nops; j++)
++	if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4)
++	  {
++	    /* We must find exactly one offset that is higher than the
++	       previous one by 4.  */
++	    if (order[i] != order[i - 1])
++	      return false;
++	    order[i] = j;
++	  }
++      if (order[i] == order[i - 1])
++	return false;
++      /* The register numbers must be ascending.  */
++      if (unsorted_regs != NULL
++	  && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]])
++	return false;
++    }
++  return true;
++}
++
++/* Used to determine in a peephole whether a sequence of load
++   instructions can be changed into a load-multiple instruction.
++   NOPS is the number of separate load instructions we are examining.  The
++   first NOPS entries in OPERANDS are the destination registers, the
++   next NOPS entries are memory operands.  If this function is
++   successful, *BASE is set to the common base register of the memory
++   accesses; *LOAD_OFFSET is set to the first memory location's offset
++   from that base register.
++   REGS is an array filled in with the destination register numbers.
++   SAVED_ORDER (if nonnull), is an array filled in with an order that maps
++   insn numbers to to an ascending order of stores.  If CHECK_REGS is true,
++   the sequence of registers in REGS matches the loads from ascending memory
++   locations, and the function verifies that the register numbers are
++   themselves ascending.  If CHECK_REGS is false, the register numbers
++   are stored in the order they are found in the operands.  */
++static int
++load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
++			int *base, HOST_WIDE_INT *load_offset, bool check_regs)
++{
++  int unsorted_regs[MAX_LDM_STM_OPS];
++  HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
++  int order[MAX_LDM_STM_OPS];
++  rtx base_reg_rtx = NULL;
++  int base_reg = -1;
++  int i, ldm_case;
++
++  if (low_irq_latency)
+     return 0;
+ 
+-  /* Can't do it without setting up the offset, only do this if it takes
+-     no more than one insn.  */
+-  return (const_ok_for_arm (unsorted_offsets[order[0]])
+-	  || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
+-}
+-
+-const char *
+-emit_ldm_seq (rtx *operands, int nops)
+-{
+-  int regs[4];
+-  int base_reg;
+-  HOST_WIDE_INT offset;
+-  char buf[100];
+-  int i;
+-
+-  switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
++  /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
++     easily extended if required.  */
++  gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
++
++  memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
++
++  /* Loop over the operands and check that the memory references are
++     suitable (i.e. immediate offsets from the same base register).  At
++     the same time, extract the target register, and the memory
++     offsets.  */
++  for (i = 0; i < nops; i++)
+     {
+-    case 1:
+-      strcpy (buf, "ldm%(ia%)\t");
+-      break;
+-
+-    case 2:
+-      strcpy (buf, "ldm%(ib%)\t");
+-      break;
+-
+-    case 3:
+-      strcpy (buf, "ldm%(da%)\t");
+-      break;
+-
+-    case 4:
+-      strcpy (buf, "ldm%(db%)\t");
+-      break;
+-
+-    case 5:
+-      if (offset >= 0)
+-	sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
+-		 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
+-		 (long) offset);
++      rtx reg;
++      rtx offset;
++
++      /* Convert a subreg of a mem into the mem itself.  */
++      if (GET_CODE (operands[nops + i]) == SUBREG)
++	operands[nops + i] = alter_subreg (operands + (nops + i));
++
++      gcc_assert (GET_CODE (operands[nops + i]) == MEM);
++
++      /* Don't reorder volatile memory references; it doesn't seem worth
++	 looking for the case where the order is ok anyway.  */
++      if (MEM_VOLATILE_P (operands[nops + i]))
++	return 0;
++
++      offset = const0_rtx;
++
++      if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
++	   || (GET_CODE (reg) == SUBREG
++	       && GET_CODE (reg = SUBREG_REG (reg)) == REG))
++	  || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
++	      && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
++		   == REG)
++		  || (GET_CODE (reg) == SUBREG
++		      && GET_CODE (reg = SUBREG_REG (reg)) == REG))
++	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
++		  == CONST_INT)))
++	{
++	  if (i == 0)
++	    {
++	      base_reg = REGNO (reg);
++	      base_reg_rtx = reg;
++	      if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
++		return 0;
++	    }
++	  else if (base_reg != (int) REGNO (reg))
++	    /* Not addressed from the same base register.  */
++	    return 0;
++
++	  unsorted_regs[i] = (GET_CODE (operands[i]) == REG
++			      ? REGNO (operands[i])
++			      : REGNO (SUBREG_REG (operands[i])));
++
++	  /* If it isn't an integer register, or if it overwrites the
++	     base register but isn't the last insn in the list, then
++	     we can't do this.  */
++	  if (unsorted_regs[i] < 0
++	      || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
++	      || unsorted_regs[i] > 14
++	      || (i != nops - 1 && unsorted_regs[i] == base_reg))
++	    return 0;
++
++	  unsorted_offsets[i] = INTVAL (offset);
++	  if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
++	    order[0] = i;
++	}
+       else
+-	sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
+-		 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
+-		 (long) -offset);
+-      output_asm_insn (buf, operands);
+-      base_reg = regs[0];
+-      strcpy (buf, "ldm%(ia%)\t");
+-      break;
+-
+-    default:
+-      gcc_unreachable ();
+-    }
+-
+-  sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
+-	   reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
+-
+-  for (i = 1; i < nops; i++)
+-    sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
+-	     reg_names[regs[i]]);
+-
+-  strcat (buf, "}\t%@ phole ldm");
+-
+-  output_asm_insn (buf, operands);
+-  return "";
++	/* Not a suitable memory address.  */
++	return 0;
++    }
++
++  /* All the useful information has now been extracted from the
++     operands into unsorted_regs and unsorted_offsets; additionally,
++     order[0] has been set to the lowest offset in the list.  Sort
++     the offsets into order, verifying that they are adjacent, and
++     check that the register numbers are ascending.  */
++  if (!compute_offset_order (nops, unsorted_offsets, order,
++			     check_regs ? unsorted_regs : NULL))
++    return 0;
++
++  if (saved_order)
++    memcpy (saved_order, order, sizeof order);
++
++  if (base)
++    {
++      *base = base_reg;
++
++      for (i = 0; i < nops; i++)
++	regs[i] = unsorted_regs[check_regs ? order[i] : i];
++
++      *load_offset = unsorted_offsets[order[0]];
++    }
++
++  if (TARGET_THUMB1
++      && !peep2_reg_dead_p (nops, base_reg_rtx))
++    return 0;
++
++  if (unsorted_offsets[order[0]] == 0)
++    ldm_case = 1; /* ldmia */
++  else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
++    ldm_case = 2; /* ldmib */
++  else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
++    ldm_case = 3; /* ldmda */
++  else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
++    ldm_case = 4; /* ldmdb */
++  else if (const_ok_for_arm (unsorted_offsets[order[0]])
++	   || const_ok_for_arm (-unsorted_offsets[order[0]]))
++    ldm_case = 5;
++  else
++    return 0;
++
++  if (!multiple_operation_profitable_p (false, nops,
++					ldm_case == 5
++					? unsorted_offsets[order[0]] : 0))
++    return 0;
++
++  return ldm_case;
+ }
+ 
+-int
+-store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
+-			 HOST_WIDE_INT * load_offset)
++/* Used to determine in a peephole whether a sequence of store instructions can
++   be changed into a store-multiple instruction.
++   NOPS is the number of separate store instructions we are examining.
++   NOPS_TOTAL is the total number of instructions recognized by the peephole
++   pattern.
++   The first NOPS entries in OPERANDS are the source registers, the next
++   NOPS entries are memory operands.  If this function is successful, *BASE is
++   set to the common base register of the memory accesses; *LOAD_OFFSET is set
++   to the first memory location's offset from that base register.  REGS is an
++   array filled in with the source register numbers, REG_RTXS (if nonnull) is
++   likewise filled with the corresponding rtx's.
++   SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
++   numbers to to an ascending order of stores.
++   If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
++   from ascending memory locations, and the function verifies that the register
++   numbers are themselves ascending.  If CHECK_REGS is false, the register
++   numbers are stored in the order they are found in the operands.  */
++static int
++store_multiple_sequence (rtx *operands, int nops, int nops_total,
++			 int *regs, rtx *reg_rtxs, int *saved_order, int *base,
++			 HOST_WIDE_INT *load_offset, bool check_regs)
+ {
+-  int unsorted_regs[4];
+-  HOST_WIDE_INT unsorted_offsets[4];
+-  int order[4];
++  int unsorted_regs[MAX_LDM_STM_OPS];
++  rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS];
++  HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
++  int order[MAX_LDM_STM_OPS];
+   int base_reg = -1;
+-  int i;
++  rtx base_reg_rtx = NULL;
++  int i, stm_case;
+ 
+   if (low_irq_latency)
+     return 0;
+ 
+-  /* Can only handle 2, 3, or 4 insns at present, though could be easily
+-     extended if required.  */
+-  gcc_assert (nops >= 2 && nops <= 4);
++  /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
++     easily extended if required.  */
++  gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
+ 
+-  memset (order, 0, 4 * sizeof (int));
++  memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
+ 
+   /* Loop over the operands and check that the memory references are
+      suitable (i.e. immediate offsets from the same base register).  At
+@@ -9964,32 +9992,32 @@
+ 	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
+ 		  == CONST_INT)))
+ 	{
++	  unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG
++				  ? operands[i] : SUBREG_REG (operands[i]));
++	  unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]);
++
+ 	  if (i == 0)
+ 	    {
+ 	      base_reg = REGNO (reg);
+-	      unsorted_regs[0] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      order[0] = 0;
+-	    }
+-	  else
+-	    {
+-	      if (base_reg != (int) REGNO (reg))
+-		/* Not addressed from the same base register.  */
++	      base_reg_rtx = reg;
++	      if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
+ 		return 0;
+-
+-	      unsorted_regs[i] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      if (unsorted_regs[i] < unsorted_regs[order[0]])
+-		order[0] = i;
+ 	    }
++	  else if (base_reg != (int) REGNO (reg))
++	    /* Not addressed from the same base register.  */
++	    return 0;
+ 
+ 	  /* If it isn't an integer register, then we can't do this.  */
+-	  if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
++	  if (unsorted_regs[i] < 0
++	      || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
++	      || (TARGET_THUMB2 && unsorted_regs[i] == base_reg)
++	      || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM)
++	      || unsorted_regs[i] > 14)
+ 	    return 0;
+ 
+ 	  unsorted_offsets[i] = INTVAL (offset);
++	  if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
++	    order[0] = i;
+ 	}
+       else
+ 	/* Not a suitable memory address.  */
+@@ -9998,111 +10026,65 @@
+ 
+   /* All the useful information has now been extracted from the
+      operands into unsorted_regs and unsorted_offsets; additionally,
+-     order[0] has been set to the lowest numbered register in the
+-     list.  Sort the registers into order, and check that the memory
+-     offsets are ascending and adjacent.  */
+-
+-  for (i = 1; i < nops; i++)
+-    {
+-      int j;
+-
+-      order[i] = order[i - 1];
+-      for (j = 0; j < nops; j++)
+-	if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
+-	    && (order[i] == order[i - 1]
+-		|| unsorted_regs[j] < unsorted_regs[order[i]]))
+-	  order[i] = j;
+-
+-      /* Have we found a suitable register? if not, one must be used more
+-	 than once.  */
+-      if (order[i] == order[i - 1])
+-	return 0;
+-
+-      /* Is the memory address adjacent and ascending? */
+-      if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
+-	return 0;
+-    }
++     order[0] has been set to the lowest offset in the list.  Sort
++     the offsets into order, verifying that they are adjacent, and
++     check that the register numbers are ascending.  */
++  if (!compute_offset_order (nops, unsorted_offsets, order,
++			     check_regs ? unsorted_regs : NULL))
++    return 0;
++
++  if (saved_order)
++    memcpy (saved_order, order, sizeof order);
+ 
+   if (base)
+     {
+       *base = base_reg;
+ 
+       for (i = 0; i < nops; i++)
+-	regs[i] = unsorted_regs[order[i]];
++	{
++	  regs[i] = unsorted_regs[check_regs ? order[i] : i];
++	  if (reg_rtxs)
++	    reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i];
++	}
+ 
+       *load_offset = unsorted_offsets[order[0]];
+     }
+ 
++  if (TARGET_THUMB1
++      && !peep2_reg_dead_p (nops_total, base_reg_rtx))
++    return 0;
++
+   if (unsorted_offsets[order[0]] == 0)
+-    return 1; /* stmia */
+-
+-  if (unsorted_offsets[order[0]] == 4)
+-    return 2; /* stmib */
+-
+-  if (unsorted_offsets[order[nops - 1]] == 0)
+-    return 3; /* stmda */
+-
+-  if (unsorted_offsets[order[nops - 1]] == -4)
+-    return 4; /* stmdb */
+-
+-  return 0;
+-}
+-
+-const char *
+-emit_stm_seq (rtx *operands, int nops)
+-{
+-  int regs[4];
+-  int base_reg;
+-  HOST_WIDE_INT offset;
+-  char buf[100];
+-  int i;
+-
+-  switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
+-    {
+-    case 1:
+-      strcpy (buf, "stm%(ia%)\t");
+-      break;
+-
+-    case 2:
+-      strcpy (buf, "stm%(ib%)\t");
+-      break;
+-
+-    case 3:
+-      strcpy (buf, "stm%(da%)\t");
+-      break;
+-
+-    case 4:
+-      strcpy (buf, "stm%(db%)\t");
+-      break;
+-
+-    default:
+-      gcc_unreachable ();
+-    }
+-
+-  sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
+-	   reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
+-
+-  for (i = 1; i < nops; i++)
+-    sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
+-	     reg_names[regs[i]]);
+-
+-  strcat (buf, "}\t%@ phole stm");
+-
+-  output_asm_insn (buf, operands);
+-  return "";
++    stm_case = 1; /* stmia */
++  else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
++    stm_case = 2; /* stmib */
++  else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
++    stm_case = 3; /* stmda */
++  else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
++    stm_case = 4; /* stmdb */
++  else
++    return 0;
++
++  if (!multiple_operation_profitable_p (false, nops, 0))
++    return 0;
++
++  return stm_case;
+ }
+ 
+ /* Routines for use in generating RTL.  */
+ 
+-rtx
+-arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
+-		       int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
++/* Generate a load-multiple instruction.  COUNT is the number of loads in
++   the instruction; REGS and MEMS are arrays containing the operands.
++   BASEREG is the base register to be used in addressing the memory operands.
++   WBACK_OFFSET is nonzero if the instruction should update the base
++   register.  */
++
++static rtx
++arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
++			 HOST_WIDE_INT wback_offset)
+ {
+-  HOST_WIDE_INT offset = *offsetp;
+   int i = 0, j;
+   rtx result;
+-  int sign = up ? 1 : -1;
+-  rtx mem, addr;
+ 
+   /* XScale has load-store double instructions, but they have stricter
+      alignment requirements than load-store multiple, so we cannot
+@@ -10139,18 +10121,10 @@
+       start_sequence ();
+ 
+       for (i = 0; i < count; i++)
+-	{
+-	  addr = plus_constant (from, i * 4 * sign);
+-	  mem = adjust_automodify_address (basemem, SImode, addr, offset);
+-	  emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
+-	  offset += 4 * sign;
+-	}
++	emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]);
+ 
+-      if (write_back)
+-	{
+-	  emit_move_insn (from, plus_constant (from, count * 4 * sign));
+-	  *offsetp = offset;
+-	}
++      if (wback_offset != 0)
++	emit_move_insn (basereg, plus_constant (basereg, wback_offset));
+ 
+       seq = get_insns ();
+       end_sequence ();
+@@ -10159,41 +10133,40 @@
+     }
+ 
+   result = gen_rtx_PARALLEL (VOIDmode,
+-			     rtvec_alloc (count + (write_back ? 1 : 0)));
+-  if (write_back)
++			     rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
++  if (wback_offset != 0)
+     {
+       XVECEXP (result, 0, 0)
+-	= gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
++	= gen_rtx_SET (VOIDmode, basereg,
++		       plus_constant (basereg, wback_offset));
+       i = 1;
+       count++;
+     }
+ 
+   for (j = 0; i < count; i++, j++)
+-    {
+-      addr = plus_constant (from, j * 4 * sign);
+-      mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
+-      XVECEXP (result, 0, i)
+-	= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
+-      offset += 4 * sign;
+-    }
+-
+-  if (write_back)
+-    *offsetp = offset;
++    XVECEXP (result, 0, i)
++      = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]);
+ 
+   return result;
+ }
+ 
+-rtx
+-arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
+-			int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
++/* Generate a store-multiple instruction.  COUNT is the number of stores in
++   the instruction; REGS and MEMS are arrays containing the operands.
++   BASEREG is the base register to be used in addressing the memory operands.
++   WBACK_OFFSET is nonzero if the instruction should update the base
++   register.  */
++
++static rtx
++arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
++			  HOST_WIDE_INT wback_offset)
+ {
+-  HOST_WIDE_INT offset = *offsetp;
+   int i = 0, j;
+   rtx result;
+-  int sign = up ? 1 : -1;
+-  rtx mem, addr;
+-
+-  /* See arm_gen_load_multiple for discussion of
++
++  if (GET_CODE (basereg) == PLUS)
++    basereg = XEXP (basereg, 0);
++
++  /* See arm_gen_load_multiple_1 for discussion of
+      the pros/cons of ldm/stm usage for XScale.  */
+   if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
+     {
+@@ -10202,18 +10175,10 @@
+       start_sequence ();
+ 
+       for (i = 0; i < count; i++)
+-	{
+-	  addr = plus_constant (to, i * 4 * sign);
+-	  mem = adjust_automodify_address (basemem, SImode, addr, offset);
+-	  emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
+-	  offset += 4 * sign;
+-	}
++	emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i]));
+ 
+-      if (write_back)
+-	{
+-	  emit_move_insn (to, plus_constant (to, count * 4 * sign));
+-	  *offsetp = offset;
+-	}
++      if (wback_offset != 0)
++	emit_move_insn (basereg, plus_constant (basereg, wback_offset));
+ 
+       seq = get_insns ();
+       end_sequence ();
+@@ -10222,29 +10187,319 @@
+     }
+ 
+   result = gen_rtx_PARALLEL (VOIDmode,
+-			     rtvec_alloc (count + (write_back ? 1 : 0)));
+-  if (write_back)
++			     rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
++  if (wback_offset != 0)
+     {
+       XVECEXP (result, 0, 0)
+-	= gen_rtx_SET (VOIDmode, to,
+-		       plus_constant (to, count * 4 * sign));
++	= gen_rtx_SET (VOIDmode, basereg,
++		       plus_constant (basereg, wback_offset));
+       i = 1;
+       count++;
+     }
+ 
+   for (j = 0; i < count; i++, j++)
++    XVECEXP (result, 0, i)
++      = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j]));
++
++  return result;
++}
++
++/* Generate either a load-multiple or a store-multiple instruction.  This
++   function can be used in situations where we can start with a single MEM
++   rtx and adjust its address upwards.
++   COUNT is the number of operations in the instruction, not counting a
++   possible update of the base register.  REGS is an array containing the
++   register operands.
++   BASEREG is the base register to be used in addressing the memory operands,
++   which are constructed from BASEMEM.
++   WRITE_BACK specifies whether the generated instruction should include an
++   update of the base register.
++   OFFSETP is used to pass an offset to and from this function; this offset
++   is not used when constructing the address (instead BASEMEM should have an
++   appropriate offset in its address), it is used only for setting
++   MEM_OFFSET.  It is updated only if WRITE_BACK is true.*/
++
++static rtx
++arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg,
++		     bool write_back, rtx basemem, HOST_WIDE_INT *offsetp)
++{
++  rtx mems[MAX_LDM_STM_OPS];
++  HOST_WIDE_INT offset = *offsetp;
++  int i;
++
++  gcc_assert (count <= MAX_LDM_STM_OPS);
++
++  if (GET_CODE (basereg) == PLUS)
++    basereg = XEXP (basereg, 0);
++
++  for (i = 0; i < count; i++)
+     {
+-      addr = plus_constant (to, j * 4 * sign);
+-      mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
+-      XVECEXP (result, 0, i)
+-	= gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
+-      offset += 4 * sign;
++      rtx addr = plus_constant (basereg, i * 4);
++      mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset);
++      offset += 4;
+     }
+ 
+   if (write_back)
+     *offsetp = offset;
+ 
+-  return result;
++  if (is_load)
++    return arm_gen_load_multiple_1 (count, regs, mems, basereg,
++				    write_back ? 4 * count : 0);
++  else
++    return arm_gen_store_multiple_1 (count, regs, mems, basereg,
++				     write_back ? 4 * count : 0);
++}
++
++rtx
++arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back,
++		       rtx basemem, HOST_WIDE_INT *offsetp)
++{
++  return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem,
++			      offsetp);
++}
++
++rtx
++arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back,
++			rtx basemem, HOST_WIDE_INT *offsetp)
++{
++  return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem,
++			      offsetp);
++}
++
++/* Called from a peephole2 expander to turn a sequence of loads into an
++   LDM instruction.  OPERANDS are the operands found by the peephole matcher;
++   NOPS indicates how many separate loads we are trying to combine.  SORT_REGS
++   is true if we can reorder the registers because they are used commutatively
++   subsequently.
++   Returns true iff we could generate a new instruction.  */
++
++bool
++gen_ldm_seq (rtx *operands, int nops, bool sort_regs)
++{
++  int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
++  rtx mems[MAX_LDM_STM_OPS];
++  int i, j, base_reg;
++  rtx base_reg_rtx;
++  HOST_WIDE_INT offset;
++  int write_back = FALSE;
++  int ldm_case;
++  rtx addr;
++
++  ldm_case = load_multiple_sequence (operands, nops, regs, mem_order,
++				     &base_reg, &offset, !sort_regs);
++
++  if (ldm_case == 0)
++    return false;
++
++  if (sort_regs)
++    for (i = 0; i < nops - 1; i++)
++      for (j = i + 1; j < nops; j++)
++	if (regs[i] > regs[j])
++	  {
++	    int t = regs[i];
++	    regs[i] = regs[j];
++	    regs[j] = t;
++	  }
++  base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
++
++  if (TARGET_THUMB1)
++    {
++      gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx));
++      gcc_assert (ldm_case == 1 || ldm_case == 5);
++      write_back = TRUE;
++    }
++
++  if (ldm_case == 5)
++    {
++      rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]);
++      emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset)));
++      offset = 0;
++      if (!TARGET_THUMB1)
++	{
++	  base_reg = regs[0];
++	  base_reg_rtx = newbase;
++	}
++    }
++
++  for (i = 0; i < nops; i++)
++    {
++      addr = plus_constant (base_reg_rtx, offset + i * 4);
++      mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
++					      SImode, addr, 0);
++    }
++  emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx,
++				      write_back ? offset + i * 4 : 0));
++  return true;
++}
++
++/* Called from a peephole2 expander to turn a sequence of stores into an
++   STM instruction.  OPERANDS are the operands found by the peephole matcher;
++   NOPS indicates how many separate stores we are trying to combine.
++   Returns true iff we could generate a new instruction.  */
++
++bool
++gen_stm_seq (rtx *operands, int nops)
++{
++  int i;
++  int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
++  rtx mems[MAX_LDM_STM_OPS];
++  int base_reg;
++  rtx base_reg_rtx;
++  HOST_WIDE_INT offset;
++  int write_back = FALSE;
++  int stm_case;
++  rtx addr;
++  bool base_reg_dies;
++
++  stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL,
++				      mem_order, &base_reg, &offset, true);
++
++  if (stm_case == 0)
++    return false;
++
++  base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
++
++  base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx);
++  if (TARGET_THUMB1)
++    {
++      gcc_assert (base_reg_dies);
++      write_back = TRUE;
++    }
++
++  if (stm_case == 5)
++    {
++      gcc_assert (base_reg_dies);
++      emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
++      offset = 0;
++    }
++
++  addr = plus_constant (base_reg_rtx, offset);
++
++  for (i = 0; i < nops; i++)
++    {
++      addr = plus_constant (base_reg_rtx, offset + i * 4);
++      mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
++					      SImode, addr, 0);
++    }
++  emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx,
++				       write_back ? offset + i * 4 : 0));
++  return true;
++}
++
++/* Called from a peephole2 expander to turn a sequence of stores that are
++   preceded by constant loads into an STM instruction.  OPERANDS are the
++   operands found by the peephole matcher; NOPS indicates how many
++   separate stores we are trying to combine; there are 2 * NOPS
++   instructions in the peephole.
++   Returns true iff we could generate a new instruction.  */
++
++bool
++gen_const_stm_seq (rtx *operands, int nops)
++{
++  int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS];
++  int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
++  rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS];
++  rtx mems[MAX_LDM_STM_OPS];
++  int base_reg;
++  rtx base_reg_rtx;
++  HOST_WIDE_INT offset;
++  int write_back = FALSE;
++  int stm_case;
++  rtx addr;
++  bool base_reg_dies;
++  int i, j;
++  HARD_REG_SET allocated;
++
++  stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs,
++				      mem_order, &base_reg, &offset, false);
++
++  if (stm_case == 0)
++    return false;
++
++  memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs);
++
++  /* If the same register is used more than once, try to find a free
++     register.  */
++  CLEAR_HARD_REG_SET (allocated);
++  for (i = 0; i < nops; i++)
++    {
++      for (j = i + 1; j < nops; j++)
++	if (regs[i] == regs[j])
++	  {
++	    rtx t = peep2_find_free_register (0, nops * 2,
++					      TARGET_THUMB1 ? "l" : "r",
++					      SImode, &allocated);
++	    if (t == NULL_RTX)
++	      return false;
++	    reg_rtxs[i] = t;
++	    regs[i] = REGNO (t);
++	  }
++    }
++
++  /* Compute an ordering that maps the register numbers to an ascending
++     sequence.  */
++  reg_order[0] = 0;
++  for (i = 0; i < nops; i++)
++    if (regs[i] < regs[reg_order[0]])
++      reg_order[0] = i;
++
++  for (i = 1; i < nops; i++)
++    {
++      int this_order = reg_order[i - 1];
++      for (j = 0; j < nops; j++)
++	if (regs[j] > regs[reg_order[i - 1]]
++	    && (this_order == reg_order[i - 1]
++		|| regs[j] < regs[this_order]))
++	  this_order = j;
++      reg_order[i] = this_order;
++    }
++
++  /* Ensure that registers that must be live after the instruction end
++     up with the correct value.  */
++  for (i = 0; i < nops; i++)
++    {
++      int this_order = reg_order[i];
++      if ((this_order != mem_order[i]
++	   || orig_reg_rtxs[this_order] != reg_rtxs[this_order])
++	  && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order]))
++	return false;
++    }
++
++  /* Load the constants.  */
++  for (i = 0; i < nops; i++)
++    {
++      rtx op = operands[2 * nops + mem_order[i]];
++      sorted_regs[i] = regs[reg_order[i]];
++      emit_move_insn (reg_rtxs[reg_order[i]], op);
++    }
++
++  base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
++
++  base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx);
++  if (TARGET_THUMB1)
++    {
++      gcc_assert (base_reg_dies);
++      write_back = TRUE;
++    }
++
++  if (stm_case == 5)
++    {
++      gcc_assert (base_reg_dies);
++      emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
++      offset = 0;
++    }
++
++  addr = plus_constant (base_reg_rtx, offset);
++
++  for (i = 0; i < nops; i++)
++    {
++      addr = plus_constant (base_reg_rtx, offset + i * 4);
++      mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
++					      SImode, addr, 0);
++    }
++  emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx,
++				       write_back ? offset + i * 4 : 0));
++  return true;
+ }
+ 
+ int
+@@ -10280,20 +10535,21 @@
+   for (i = 0; in_words_to_go >= 2; i+=4)
+     {
+       if (in_words_to_go > 4)
+-	emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
+-					  srcbase, &srcoffset));
++	emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src,
++					  TRUE, srcbase, &srcoffset));
+       else
+-	emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
+-					  FALSE, srcbase, &srcoffset));
++	emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go,
++					  src, FALSE, srcbase,
++					  &srcoffset));
+ 
+       if (out_words_to_go)
+ 	{
+ 	  if (out_words_to_go > 4)
+-	    emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
+-					       dstbase, &dstoffset));
++	    emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst,
++					       TRUE, dstbase, &dstoffset));
+ 	  else if (out_words_to_go != 1)
+-	    emit_insn (arm_gen_store_multiple (0, out_words_to_go,
+-					       dst, TRUE,
++	    emit_insn (arm_gen_store_multiple (arm_regs_in_sequence,
++					       out_words_to_go, dst,
+ 					       (last_bytes == 0
+ 						? FALSE : TRUE),
+ 					       dstbase, &dstoffset));
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm.h	2011-01-05 18:20:37 +0000
+@@ -1143,6 +1143,9 @@
+   ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
+    || (MODE) == CImode || (MODE) == XImode)
+ 
++/* The register numbers in sequence, for passing to arm_gen_load_multiple.  */
++extern int arm_regs_in_sequence[];
++
+ /* The order in which register should be allocated.  It is good to use ip
+    since no saving is required (though calls clobber it) and it never contains
+    function parameters.  It is quite good to use lr since other calls may
+@@ -2823,4 +2826,8 @@
+ #define NEED_INDICATE_EXEC_STACK	0
+ #endif
+ 
++/* The maximum number of parallel loads or stores we support in an ldm/stm
++   instruction.  */
++#define MAX_LDM_STM_OPS 4
++
+ #endif /* ! GCC_ARM_H */
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm.md	2011-01-05 18:20:37 +0000
+@@ -6282,7 +6282,7 @@
+ 
+ ;; load- and store-multiple insns
+ ;; The arm can load/store any set of registers, provided that they are in
+-;; ascending order; but that is beyond GCC so stick with what it knows.
++;; ascending order, but these expanders assume a contiguous set.
+ 
+ (define_expand "load_multiple"
+   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+@@ -6303,126 +6303,12 @@
+     FAIL;
+ 
+   operands[3]
+-    = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]),
++    = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]),
++			     INTVAL (operands[2]),
+ 			     force_reg (SImode, XEXP (operands[1], 0)),
+-			     TRUE, FALSE, operands[1], &offset);
++			     FALSE, operands[1], &offset);
+ })
+ 
+-;; Load multiple with write-back
+-
+-(define_insn "*ldmsi_postinc4"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+-     (set (match_operand:SI 6 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
+-  "ldm%(ia%)\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi_postinc4_thumb1"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=l")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+-     (set (match_operand:SI 6 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))])]
+-  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
+-  "ldmia\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "type" "load4")]
+-)
+-
+-(define_insn "*ldmsi_postinc3"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 12)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "ldm%(ia%)\\t%1!, {%3, %4, %5}"
+-  [(set_attr "type" "load3")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi_postinc2"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 8)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "ldm%(ia%)\\t%1!, {%3, %4}"
+-  [(set_attr "type" "load2")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-;; Ordinary load multiple
+-
+-(define_insn "*ldmsi4"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
+-	  (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "ldm%(ia%)\\t%1, {%2, %3, %4, %5}"
+-  [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi3"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
+-	  (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "ldm%(ia%)\\t%1, {%2, %3, %4}"
+-  [(set_attr "type" "load3")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi2"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
+-	  (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
+-  "ldm%(ia%)\\t%1, {%2, %3}"
+-  [(set_attr "type" "load2")
+-   (set_attr "predicable" "yes")]
+-)
+-
+ (define_expand "store_multiple"
+   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+                           (match_operand:SI 1 "" ""))
+@@ -6442,125 +6328,12 @@
+     FAIL;
+ 
+   operands[3]
+-    = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]),
++    = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]),
++			      INTVAL (operands[2]),
+ 			      force_reg (SImode, XEXP (operands[0], 0)),
+-			      TRUE, FALSE, operands[0], &offset);
++			      FALSE, operands[0], &offset);
+ })
+ 
+-;; Store multiple with write-back
+-
+-(define_insn "*stmsi_postinc4"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+-	  (match_operand:SI 6 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
+-  "stm%(ia%)\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store4")]
+-)
+-
+-(define_insn "*stmsi_postinc4_thumb1"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=l")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+-	  (match_operand:SI 6 "arm_hard_register_operand" ""))])]
+-  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
+-  "stmia\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "type" "store4")]
+-)
+-
+-(define_insn "*stmsi_postinc3"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 12)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "stm%(ia%)\\t%1!, {%3, %4, %5}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store3")]
+-)
+-
+-(define_insn "*stmsi_postinc2"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 8)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "stm%(ia%)\\t%1!, {%3, %4}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store2")]
+-)
+-
+-;; Ordinary store multiple
+-
+-(define_insn "*stmsi4"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+-	  (match_operand:SI 2 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "stm%(ia%)\\t%1, {%2, %3, %4, %5}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store4")]
+-)
+-
+-(define_insn "*stmsi3"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+-	  (match_operand:SI 2 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "stm%(ia%)\\t%1, {%2, %3, %4}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store3")]
+-)
+-
+-(define_insn "*stmsi2"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+-	  (match_operand:SI 2 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
+-  "stm%(ia%)\\t%1, {%2, %3}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store2")]
+-)
+ 
+ ;; Move a block of memory if it is word aligned and MORE than 2 words long.
+ ;; We could let this apply for blocks of less than this, but it clobbers so
+@@ -9031,8 +8804,8 @@
+ 	if (REGNO (reg) == R0_REGNUM)
+ 	  {
+ 	    /* On thumb we have to use a write-back instruction.  */
+-	    emit_insn (arm_gen_store_multiple (R0_REGNUM, 4, addr, TRUE,
+-			TARGET_THUMB ? TRUE : FALSE, mem, &offset));
++	    emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr,
++ 		       TARGET_THUMB ? TRUE : FALSE, mem, &offset));
+ 	    size = TARGET_ARM ? 16 : 0;
+ 	  }
+ 	else
+@@ -9078,8 +8851,8 @@
+ 	if (REGNO (reg) == R0_REGNUM)
+ 	  {
+ 	    /* On thumb we have to use a write-back instruction.  */
+-	    emit_insn (arm_gen_load_multiple (R0_REGNUM, 4, addr, TRUE,
+-			TARGET_THUMB ? TRUE : FALSE, mem, &offset));
++	    emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr,
++ 		       TARGET_THUMB ? TRUE : FALSE, mem, &offset));
+ 	    size = TARGET_ARM ? 16 : 0;
+ 	  }
+ 	else
+@@ -10672,87 +10445,6 @@
+   ""
+ )
+ 
+-; Peepholes to spot possible load- and store-multiples, if the ordering is
+-; reversed, check that the memory references aren't volatile.
+-
+-(define_peephole
+-  [(set (match_operand:SI 0 "s_register_operand" "=rk")
+-        (match_operand:SI 4 "memory_operand" "m"))
+-   (set (match_operand:SI 1 "s_register_operand" "=rk")
+-        (match_operand:SI 5 "memory_operand" "m"))
+-   (set (match_operand:SI 2 "s_register_operand" "=rk")
+-        (match_operand:SI 6 "memory_operand" "m"))
+-   (set (match_operand:SI 3 "s_register_operand" "=rk")
+-        (match_operand:SI 7 "memory_operand" "m"))]
+-  "TARGET_ARM && load_multiple_sequence (operands, 4, NULL, NULL, NULL)"
+-  "*
+-  return emit_ldm_seq (operands, 4);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 0 "s_register_operand" "=rk")
+-        (match_operand:SI 3 "memory_operand" "m"))
+-   (set (match_operand:SI 1 "s_register_operand" "=rk")
+-        (match_operand:SI 4 "memory_operand" "m"))
+-   (set (match_operand:SI 2 "s_register_operand" "=rk")
+-        (match_operand:SI 5 "memory_operand" "m"))]
+-  "TARGET_ARM && load_multiple_sequence (operands, 3, NULL, NULL, NULL)"
+-  "*
+-  return emit_ldm_seq (operands, 3);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 0 "s_register_operand" "=rk")
+-        (match_operand:SI 2 "memory_operand" "m"))
+-   (set (match_operand:SI 1 "s_register_operand" "=rk")
+-        (match_operand:SI 3 "memory_operand" "m"))]
+-  "TARGET_ARM && load_multiple_sequence (operands, 2, NULL, NULL, NULL)"
+-  "*
+-  return emit_ldm_seq (operands, 2);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 4 "memory_operand" "=m")
+-        (match_operand:SI 0 "s_register_operand" "rk"))
+-   (set (match_operand:SI 5 "memory_operand" "=m")
+-        (match_operand:SI 1 "s_register_operand" "rk"))
+-   (set (match_operand:SI 6 "memory_operand" "=m")
+-        (match_operand:SI 2 "s_register_operand" "rk"))
+-   (set (match_operand:SI 7 "memory_operand" "=m")
+-        (match_operand:SI 3 "s_register_operand" "rk"))]
+-  "TARGET_ARM && store_multiple_sequence (operands, 4, NULL, NULL, NULL)"
+-  "*
+-  return emit_stm_seq (operands, 4);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 3 "memory_operand" "=m")
+-        (match_operand:SI 0 "s_register_operand" "rk"))
+-   (set (match_operand:SI 4 "memory_operand" "=m")
+-        (match_operand:SI 1 "s_register_operand" "rk"))
+-   (set (match_operand:SI 5 "memory_operand" "=m")
+-        (match_operand:SI 2 "s_register_operand" "rk"))]
+-  "TARGET_ARM && store_multiple_sequence (operands, 3, NULL, NULL, NULL)"
+-  "*
+-  return emit_stm_seq (operands, 3);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 2 "memory_operand" "=m")
+-        (match_operand:SI 0 "s_register_operand" "rk"))
+-   (set (match_operand:SI 3 "memory_operand" "=m")
+-        (match_operand:SI 1 "s_register_operand" "rk"))]
+-  "TARGET_ARM && store_multiple_sequence (operands, 2, NULL, NULL, NULL)"
+-  "*
+-  return emit_stm_seq (operands, 2);
+-  "
+-)
+-
+ (define_split
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
+@@ -11559,6 +11251,8 @@
+   "
+ )
+ 
++;; Load the load/store multiple patterns
++(include "ldmstm.md")
+ ;; Load the FPA co-processor patterns
+ (include "fpa.md")
+ ;; Load the Maverick co-processor patterns
+
+=== added file 'gcc/config/arm/ldmstm.md'
+--- old/gcc/config/arm/ldmstm.md	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/ldmstm.md	2010-11-16 13:08:47 +0000
+@@ -0,0 +1,1191 @@
++/* ARM ldm/stm instruction patterns.  This file was automatically generated
++   using arm-ldmstm.ml.  Please do not edit manually.
++
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   Contributed by CodeSourcery.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++(define_insn "*ldm4_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm4_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "l")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")])
++
++(define_insn "*ldm4_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "ldm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm4_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
++  "ldm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")])
++
++(define_insn "*stm4_ia"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(ia%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "stm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_stm4_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
++  "stm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")])
++
++(define_insn "*ldm4_ib"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int 4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 16))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ib%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_ib_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 16))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "ldm%(ib%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_ib"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(ib%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_ib_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "stm%(ib%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_da"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -12))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 1)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(da%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_da_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -12))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "ldm%(da%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_da"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 1))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(da%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_da_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -12)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "stm%(da%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_db"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -16))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -12))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(db%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_db_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -16))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -12))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "ldm%(db%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_db"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -16)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -12)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(db%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_db_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -16)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -12)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "stm%(db%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 5 "memory_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 6 "memory_operand" ""))
++   (set (match_operand:SI 3 "s_register_operand" "")
++        (match_operand:SI 7 "memory_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 4, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "memory_operand" ""))
++   (parallel
++    [(set (match_operand:SI 1 "s_register_operand" "")
++          (match_operand:SI 5 "memory_operand" ""))
++     (set (match_operand:SI 2 "s_register_operand" "")
++          (match_operand:SI 6 "memory_operand" ""))
++     (set (match_operand:SI 3 "s_register_operand" "")
++          (match_operand:SI 7 "memory_operand" ""))])]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 4, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 9 "const_int_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 10 "const_int_operand" ""))
++   (set (match_operand:SI 6 "memory_operand" "")
++        (match_dup 2))
++   (set (match_operand:SI 3 "s_register_operand" "")
++        (match_operand:SI 11 "const_int_operand" ""))
++   (set (match_operand:SI 7 "memory_operand" "")
++        (match_dup 3))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 4))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 9 "const_int_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 10 "const_int_operand" ""))
++   (set (match_operand:SI 3 "s_register_operand" "")
++        (match_operand:SI 11 "const_int_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 6 "memory_operand" "")
++        (match_dup 2))
++   (set (match_operand:SI 7 "memory_operand" "")
++        (match_dup 3))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 4))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 4 "memory_operand" "")
++        (match_operand:SI 0 "s_register_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_operand:SI 1 "s_register_operand" ""))
++   (set (match_operand:SI 6 "memory_operand" "")
++        (match_operand:SI 2 "s_register_operand" ""))
++   (set (match_operand:SI 7 "memory_operand" "")
++        (match_operand:SI 3 "s_register_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_stm_seq (operands, 4))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_insn "*ldm3_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm3_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "l")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")])
++
++(define_insn "*ldm3_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm3_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")])
++
++(define_insn "*stm3_ia"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(ia%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_stm3_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
++  "stm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")])
++
++(define_insn "*ldm3_ib"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int 4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ib%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_ib_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ib%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_ib"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(ib%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_ib_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(ib%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_da"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -8))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 1)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(da%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_da_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(da%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_da"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 1))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(da%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_da_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(da%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_db"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -12))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(db%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_db_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -12))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(db%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_db"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(db%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_db_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -12)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(db%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 4 "memory_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 5 "memory_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 3, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (parallel
++    [(set (match_operand:SI 1 "s_register_operand" "")
++          (match_operand:SI 4 "memory_operand" ""))
++     (set (match_operand:SI 2 "s_register_operand" "")
++          (match_operand:SI 5 "memory_operand" ""))])]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 3, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 6 "const_int_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 7 "const_int_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 2))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 3))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 6 "const_int_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 7 "const_int_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 2))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 3))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 3 "memory_operand" "")
++        (match_operand:SI 0 "s_register_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_operand:SI 1 "s_register_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_operand:SI 2 "s_register_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_stm_seq (operands, 3))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_insn "*ldm2_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "ldm%(ia%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm2_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "l")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
++  "ldm%(ia%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")])
++
++(define_insn "*ldm2_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm2_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")])
++
++(define_insn "*stm2_ia"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "stm%(ia%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_stm2_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
++  "stm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")])
++
++(define_insn "*ldm2_ib"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int 4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "ldm%(ib%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_ib_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ib%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_ib"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "stm%(ib%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_ib_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(ib%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_da"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 1)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "ldm%(da%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_da_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(da%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_da"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 1))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "stm%(da%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_da_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(da%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_db"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -8))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "ldm%(db%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_db_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(db%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_db"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "stm%(db%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_db_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(db%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 2 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 2, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "const_int_operand" ""))
++   (set (match_operand:SI 2 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 5 "const_int_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 1))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 2))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "const_int_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 5 "const_int_operand" ""))
++   (set (match_operand:SI 2 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 1))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 2))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 2 "memory_operand" "")
++        (match_operand:SI 0 "s_register_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_operand:SI 1 "s_register_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_stm_seq (operands, 2))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 2 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (parallel
++     [(set (match_operand:SI 4 "s_register_operand" "")
++           (match_operator:SI 5 "commutative_binary_operator"
++            [(match_operand:SI 6 "s_register_operand" "")
++             (match_operand:SI 7 "s_register_operand" "")]))
++      (clobber (reg:CC CC_REGNUM))])]
++  "(((operands[6] == operands[0] && operands[7] == operands[1])
++     || (operands[7] == operands[0] && operands[6] == operands[1]))
++    && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))"
++  [(parallel
++    [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))
++     (clobber (reg:CC CC_REGNUM))])]
++{
++  if (!gen_ldm_seq (operands, 2, true))
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 2 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (set (match_operand:SI 4 "s_register_operand" "")
++        (match_operator:SI 5 "commutative_binary_operator"
++         [(match_operand:SI 6 "s_register_operand" "")
++          (match_operand:SI 7 "s_register_operand" "")]))]
++  "(((operands[6] == operands[0] && operands[7] == operands[1])
++     || (operands[7] == operands[0] && operands[6] == operands[1]))
++    && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))"
++  [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))]
++{
++  if (!gen_ldm_seq (operands, 2, true))
++    FAIL;
++})
++
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/predicates.md	2010-11-16 12:32:34 +0000
+@@ -211,6 +211,11 @@
+   (and (match_code "ior,xor,and")
+        (match_test "mode == GET_MODE (op)")))
+ 
++;; True for commutative operators
++(define_special_predicate "commutative_binary_operator"
++  (and (match_code "ior,xor,and,plus")
++       (match_test "mode == GET_MODE (op)")))
++
+ ;; True for shift operators.
+ (define_special_predicate "shift_operator"
+   (and (ior (ior (and (match_code "mult")
+@@ -334,16 +339,20 @@
+   (match_code "parallel")
+ {
+   HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int dest_regno;
++  unsigned dest_regno;
+   rtx src_addr;
+   HOST_WIDE_INT i = 1, base = 0;
++  HOST_WIDE_INT offset = 0;
+   rtx elt;
++  bool addr_reg_loaded = false;
++  bool update = false;
+ 
+   if (low_irq_latency)
+     return false;
+ 
+   if (count <= 1
+-      || GET_CODE (XVECEXP (op, 0, 0)) != SET)
++      || GET_CODE (XVECEXP (op, 0, 0)) != SET
++      || !REG_P (SET_DEST (XVECEXP (op, 0, 0))))
+     return false;
+ 
+   /* Check to see if this might be a write-back.  */
+@@ -351,6 +360,7 @@
+     {
+       i++;
+       base = 1;
++      update = true;
+ 
+       /* Now check it more carefully.  */
+       if (GET_CODE (SET_DEST (elt)) != REG
+@@ -369,6 +379,15 @@
+ 
+   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
+   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
++  if (GET_CODE (src_addr) == PLUS)
++    {
++      if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT)
++	return false;
++      offset = INTVAL (XEXP (src_addr, 1));
++      src_addr = XEXP (src_addr, 0);
++    }
++  if (!REG_P (src_addr))
++    return false;
+ 
+   for (; i < count; i++)
+     {
+@@ -377,16 +396,28 @@
+       if (GET_CODE (elt) != SET
+           || GET_CODE (SET_DEST (elt)) != REG
+           || GET_MODE (SET_DEST (elt)) != SImode
+-          || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
++          || REGNO (SET_DEST (elt)) <= dest_regno
+           || GET_CODE (SET_SRC (elt)) != MEM
+           || GET_MODE (SET_SRC (elt)) != SImode
+-          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
+-          || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
+-          || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+-          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
++          || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
++	       || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
++	       || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
++	       || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4)
++	      && (!REG_P (XEXP (SET_SRC (elt), 0))
++		  || offset + (i - base) * 4 != 0)))
+         return false;
++      dest_regno = REGNO (SET_DEST (elt));
++      if (dest_regno == REGNO (src_addr))
++        addr_reg_loaded = true;
+     }
+-
++  /* For Thumb, we only have updating instructions.  If the pattern does
++     not describe an update, it must be because the address register is
++     in the list of loaded registers - on the hardware, this has the effect
++     of overriding the update.  */
++  if (update && addr_reg_loaded)
++    return false;
++  if (TARGET_THUMB1)
++    return update || addr_reg_loaded;
+   return true;
+ })
+ 
+@@ -394,9 +425,9 @@
+   (match_code "parallel")
+ {
+   HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int src_regno;
++  unsigned src_regno;
+   rtx dest_addr;
+-  HOST_WIDE_INT i = 1, base = 0;
++  HOST_WIDE_INT i = 1, base = 0, offset = 0;
+   rtx elt;
+ 
+   if (low_irq_latency)
+@@ -430,6 +461,16 @@
+   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
+   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
+ 
++  if (GET_CODE (dest_addr) == PLUS)
++    {
++      if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT)
++	return false;
++      offset = INTVAL (XEXP (dest_addr, 1));
++      dest_addr = XEXP (dest_addr, 0);
++    }
++  if (!REG_P (dest_addr))
++    return false;
++
+   for (; i < count; i++)
+     {
+       elt = XVECEXP (op, 0, i);
+@@ -437,14 +478,17 @@
+       if (GET_CODE (elt) != SET
+           || GET_CODE (SET_SRC (elt)) != REG
+           || GET_MODE (SET_SRC (elt)) != SImode
+-          || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
++          || REGNO (SET_SRC (elt)) <= src_regno
+           || GET_CODE (SET_DEST (elt)) != MEM
+           || GET_MODE (SET_DEST (elt)) != SImode
+-          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
+-          || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
+-          || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+-          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
++          || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
++	       || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
++	       || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
++               || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4)
++	      && (!REG_P (XEXP (SET_DEST (elt), 0))
++		  || offset + (i - base) * 4 != 0)))
+         return false;
++      src_regno = REGNO (SET_SRC (elt));
+     }
+ 
+   return true;
+
+=== modified file 'gcc/config/i386/i386.md'
+--- old/gcc/config/i386/i386.md	2011-01-05 12:12:18 +0000
++++ new/gcc/config/i386/i386.md	2011-01-05 18:20:37 +0000
+@@ -20023,15 +20023,14 @@
+ ;;  leal    (%edx,%eax,4), %eax
+ 
+ (define_peephole2
+-  [(parallel [(set (match_operand 0 "register_operand" "")
++  [(match_scratch:SI 5 "r")
++   (parallel [(set (match_operand 0 "register_operand" "")
+ 		   (ashift (match_operand 1 "register_operand" "")
+ 			   (match_operand 2 "const_int_operand" "")))
+ 	       (clobber (reg:CC FLAGS_REG))])
+-   (set (match_operand 3 "register_operand")
+-        (match_operand 4 "x86_64_general_operand" ""))
+-   (parallel [(set (match_operand 5 "register_operand" "")
+-		   (plus (match_operand 6 "register_operand" "")
+-			 (match_operand 7 "register_operand" "")))
++   (parallel [(set (match_operand 3 "register_operand" "")
++		   (plus (match_dup 0)
++			 (match_operand 4 "x86_64_general_operand" "")))
+ 		   (clobber (reg:CC FLAGS_REG))])]
+   "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
+    /* Validate MODE for lea.  */
+@@ -20041,30 +20040,21 @@
+        || GET_MODE (operands[0]) == SImode
+        || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
+    /* We reorder load and the shift.  */
+-   && !rtx_equal_p (operands[1], operands[3])
+-   && !reg_overlap_mentioned_p (operands[0], operands[4])
+-   /* Last PLUS must consist of operand 0 and 3.  */
+-   && !rtx_equal_p (operands[0], operands[3])
+-   && (rtx_equal_p (operands[3], operands[6])
+-       || rtx_equal_p (operands[3], operands[7]))
+-   && (rtx_equal_p (operands[0], operands[6])
+-       || rtx_equal_p (operands[0], operands[7]))
+-   /* The intermediate operand 0 must die or be same as output.  */
+-   && (rtx_equal_p (operands[0], operands[5])
+-       || peep2_reg_dead_p (3, operands[0]))"
+-  [(set (match_dup 3) (match_dup 4))
++   && !reg_overlap_mentioned_p (operands[0], operands[4])"
++  [(set (match_dup 5) (match_dup 4))
+    (set (match_dup 0) (match_dup 1))]
+ {
+-  enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode;
++  enum machine_mode mode = GET_MODE (operands[1]) == DImode ? DImode : SImode;
+   int scale = 1 << INTVAL (operands[2]);
+   rtx index = gen_lowpart (Pmode, operands[1]);
+-  rtx base = gen_lowpart (Pmode, operands[3]);
+-  rtx dest = gen_lowpart (mode, operands[5]);
++  rtx base = gen_lowpart (Pmode, operands[5]);
++  rtx dest = gen_lowpart (mode, operands[3]);
+ 
+   operands[1] = gen_rtx_PLUS (Pmode, base,
+   			      gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
+   if (mode != Pmode)
+     operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
++  operands[5] = base;
+   operands[0] = dest;
+ })
+ 
+
+=== modified file 'gcc/df-problems.c'
+--- old/gcc/df-problems.c	2010-11-16 22:17:17 +0000
++++ new/gcc/df-problems.c	2010-12-02 13:42:47 +0000
+@@ -3748,9 +3748,22 @@
+   for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
+     {
+       df_ref def = *def_rec;
+-      /* If the def is to only part of the reg, it does
+-	 not kill the other defs that reach here.  */
+-      if (!(DF_REF_FLAGS (def) & (DF_REF_PARTIAL | DF_REF_CONDITIONAL)))
++      bitmap_set_bit (defs, DF_REF_REGNO (def));
++    }
++}
++
++/* Find the set of real DEFs, which are not clobbers, for INSN.  */
++
++void
++df_simulate_find_noclobber_defs (rtx insn, bitmap defs)
++{
++  df_ref *def_rec;
++  unsigned int uid = INSN_UID (insn);
++
++  for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
++    {
++      df_ref def = *def_rec;
++      if (!(DF_REF_FLAGS (def) & (DF_REF_MUST_CLOBBER | DF_REF_MAY_CLOBBER)))
+ 	bitmap_set_bit (defs, DF_REF_REGNO (def));
+     }
+ }
+@@ -3921,7 +3934,7 @@
+     {
+       df_ref def = *def_rec;
+       if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)
+-	bitmap_clear_bit (live, DF_REF_REGNO (def));
++	bitmap_set_bit (live, DF_REF_REGNO (def));
+     }
+ }
+ 
+@@ -3942,7 +3955,7 @@
+      while here the scan is performed forwards!  So, first assume that the
+      def is live, and if this is not true REG_UNUSED notes will rectify the
+      situation.  */
+-  df_simulate_find_defs (insn, live);
++  df_simulate_find_noclobber_defs (insn, live);
+ 
+   /* Clear all of the registers that go dead.  */
+   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
+
+=== modified file 'gcc/df.h'
+--- old/gcc/df.h	2010-01-29 12:14:47 +0000
++++ new/gcc/df.h	2010-12-02 13:42:47 +0000
+@@ -978,6 +978,7 @@
+ extern void df_md_add_problem (void);
+ extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap);
+ extern void df_md_simulate_one_insn (basic_block, rtx, bitmap);
++extern void df_simulate_find_noclobber_defs (rtx, bitmap);
+ extern void df_simulate_find_defs (rtx, bitmap);
+ extern void df_simulate_defs (rtx, bitmap);
+ extern void df_simulate_uses (rtx, bitmap);
+
+=== modified file 'gcc/fwprop.c'
+--- old/gcc/fwprop.c	2010-04-02 18:54:46 +0000
++++ new/gcc/fwprop.c	2010-11-16 12:32:34 +0000
+@@ -228,7 +228,10 @@
+ 
+   process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP);
+   process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP);
+-  df_simulate_initialize_forwards (bb, local_lr);
++
++  /* We don't call df_simulate_initialize_forwards, as it may overestimate
++     the live registers if there are unused artificial defs.  We prefer
++     liveness to be underestimated.  */
+ 
+   FOR_BB_INSNS (bb, insn)
+     if (INSN_P (insn))
+
+=== modified file 'gcc/genoutput.c'
+--- old/gcc/genoutput.c	2009-04-08 14:00:34 +0000
++++ new/gcc/genoutput.c	2010-11-16 12:32:34 +0000
+@@ -266,6 +266,8 @@
+ 
+       printf ("    %d,\n", d->strict_low);
+ 
++      printf ("    %d,\n", d->constraint == NULL ? 1 : 0);
++
+       printf ("    %d\n", d->eliminable);
+ 
+       printf("  },\n");
+
+=== modified file 'gcc/genrecog.c'
+--- old/gcc/genrecog.c	2009-06-22 09:29:13 +0000
++++ new/gcc/genrecog.c	2010-11-16 12:32:34 +0000
+@@ -1782,20 +1782,11 @@
+   int odepth = strlen (oldpos);
+   int ndepth = strlen (newpos);
+   int depth;
+-  int old_has_insn, new_has_insn;
+ 
+   /* Pop up as many levels as necessary.  */
+   for (depth = odepth; strncmp (oldpos, newpos, depth) != 0; --depth)
+     continue;
+ 
+-  /* Hunt for the last [A-Z] in both strings.  */
+-  for (old_has_insn = odepth - 1; old_has_insn >= 0; --old_has_insn)
+-    if (ISUPPER (oldpos[old_has_insn]))
+-      break;
+-  for (new_has_insn = ndepth - 1; new_has_insn >= 0; --new_has_insn)
+-    if (ISUPPER (newpos[new_has_insn]))
+-      break;
+-
+   /* Go down to desired level.  */
+   while (depth < ndepth)
+     {
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c	2011-01-05 12:12:18 +0000
++++ new/gcc/ifcvt.c	2011-01-05 18:20:37 +0000
+@@ -4011,6 +4011,7 @@
+   basic_block new_dest = dest_edge->dest;
+   rtx head, end, jump, earliest = NULL_RTX, old_dest;
+   bitmap merge_set = NULL;
++  bitmap merge_set_noclobber  = NULL;
+   /* Number of pending changes.  */
+   int n_validated_changes = 0;
+   rtx new_dest_label;
+@@ -4169,6 +4170,7 @@
+ 		       end of the block.  */
+ 
+       merge_set = BITMAP_ALLOC (&reg_obstack);
++      merge_set_noclobber = BITMAP_ALLOC (&reg_obstack);
+ 
+       /* If we allocated new pseudos (e.g. in the conditional move
+ 	 expander called from noce_emit_cmove), we must resize the
+@@ -4187,6 +4189,7 @@
+ 		  df_ref def = *def_rec;
+ 		  bitmap_set_bit (merge_set, DF_REF_REGNO (def));
+ 		}
++              df_simulate_find_noclobber_defs (insn, merge_set_noclobber);
+ 	    }
+ 	}
+ 
+@@ -4197,7 +4200,7 @@
+ 	  unsigned i;
+ 	  bitmap_iterator bi;
+ 
+-          EXECUTE_IF_SET_IN_BITMAP (merge_set, 0, i, bi)
++          EXECUTE_IF_SET_IN_BITMAP (merge_set_noclobber, 0, i, bi)
+ 	    {
+ 	      if (i < FIRST_PSEUDO_REGISTER
+ 		  && ! fixed_regs[i]
+@@ -4233,7 +4236,7 @@
+ 	   TEST_SET & DF_LIVE_IN (merge_bb)
+ 	 are empty.  */
+ 
+-      if (bitmap_intersect_p (merge_set, test_set)
++      if (bitmap_intersect_p (merge_set_noclobber, test_set)
+ 	  || bitmap_intersect_p (merge_set, test_live)
+ 	  || bitmap_intersect_p (test_set, df_get_live_in (merge_bb)))
+ 	intersect = true;
+@@ -4320,6 +4323,7 @@
+ 	    remove_reg_equal_equiv_notes_for_regno (i);
+ 
+ 	  BITMAP_FREE (merge_set);
++          BITMAP_FREE (merge_set_noclobber);
+ 	}
+ 
+       reorder_insns (head, end, PREV_INSN (earliest));
+@@ -4340,7 +4344,10 @@
+   cancel_changes (0);
+  fail:
+   if (merge_set)
+-    BITMAP_FREE (merge_set);
++    {
++      BITMAP_FREE (merge_set);
++      BITMAP_FREE (merge_set_noclobber);
++    }
+   return FALSE;
+ }
+ 
+
+=== modified file 'gcc/recog.c'
+--- old/gcc/recog.c	2010-08-05 15:28:47 +0000
++++ new/gcc/recog.c	2010-11-16 12:32:34 +0000
+@@ -2082,6 +2082,7 @@
+ 			       recog_data.operand_loc,
+ 			       recog_data.constraints,
+ 			       recog_data.operand_mode, NULL);
++	  memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
+ 	  if (noperands > 0)
+ 	    {
+ 	      const char *p =  recog_data.constraints[0];
+@@ -2111,6 +2112,7 @@
+       for (i = 0; i < noperands; i++)
+ 	{
+ 	  recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
++	  recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
+ 	  recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
+ 	  /* VOIDmode match_operands gets mode from their real operand.  */
+ 	  if (recog_data.operand_mode[i] == VOIDmode)
+@@ -2909,6 +2911,10 @@
+ 
+ static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
+ static int peep2_current;
++
++static bool peep2_do_rebuild_jump_labels;
++static bool peep2_do_cleanup_cfg;
++
+ /* The number of instructions available to match a peep2.  */
+ int peep2_current_count;
+ 
+@@ -2917,6 +2923,16 @@
+    DF_LIVE_OUT for the block.  */
+ #define PEEP2_EOB	pc_rtx
+ 
++/* Wrap N to fit into the peep2_insn_data buffer.  */
++
++static int
++peep2_buf_position (int n)
++{
++  if (n >= MAX_INSNS_PER_PEEP2 + 1)
++    n -= MAX_INSNS_PER_PEEP2 + 1;
++  return n;
++}
++
+ /* Return the Nth non-note insn after `current', or return NULL_RTX if it
+    does not exist.  Used by the recognizer to find the next insn to match
+    in a multi-insn pattern.  */
+@@ -2926,9 +2942,7 @@
+ {
+   gcc_assert (n <= peep2_current_count);
+ 
+-  n += peep2_current;
+-  if (n >= MAX_INSNS_PER_PEEP2 + 1)
+-    n -= MAX_INSNS_PER_PEEP2 + 1;
++  n = peep2_buf_position (peep2_current + n);
+ 
+   return peep2_insn_data[n].insn;
+ }
+@@ -2941,9 +2955,7 @@
+ {
+   gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
+ 
+-  ofs += peep2_current;
+-  if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+-    ofs -= MAX_INSNS_PER_PEEP2 + 1;
++  ofs = peep2_buf_position (peep2_current + ofs);
+ 
+   gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
+ 
+@@ -2959,9 +2971,7 @@
+ 
+   gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
+ 
+-  ofs += peep2_current;
+-  if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+-    ofs -= MAX_INSNS_PER_PEEP2 + 1;
++  ofs = peep2_buf_position (peep2_current + ofs);
+ 
+   gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
+ 
+@@ -2996,12 +3006,8 @@
+   gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
+   gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
+ 
+-  from += peep2_current;
+-  if (from >= MAX_INSNS_PER_PEEP2 + 1)
+-    from -= MAX_INSNS_PER_PEEP2 + 1;
+-  to += peep2_current;
+-  if (to >= MAX_INSNS_PER_PEEP2 + 1)
+-    to -= MAX_INSNS_PER_PEEP2 + 1;
++  from = peep2_buf_position (peep2_current + from);
++  to = peep2_buf_position (peep2_current + to);
+ 
+   gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
+   REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
+@@ -3010,8 +3016,7 @@
+     {
+       HARD_REG_SET this_live;
+ 
+-      if (++from >= MAX_INSNS_PER_PEEP2 + 1)
+-	from = 0;
++      from = peep2_buf_position (from + 1);
+       gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
+       REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
+       IOR_HARD_REG_SET (live, this_live);
+@@ -3104,19 +3109,234 @@
+   COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
+ }
+ 
++/* While scanning basic block BB, we found a match of length MATCH_LEN,
++   starting at INSN.  Perform the replacement, removing the old insns and
++   replacing them with ATTEMPT.  Returns the last insn emitted.  */
++
++static rtx
++peep2_attempt (basic_block bb, rtx insn, int match_len, rtx attempt)
++{
++  int i;
++  rtx last, note, before_try, x;
++  bool was_call = false;
++
++  /* If we are splitting a CALL_INSN, look for the CALL_INSN
++     in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
++     cfg-related call notes.  */
++  for (i = 0; i <= match_len; ++i)
++    {
++      int j;
++      rtx old_insn, new_insn, note;
++
++      j = peep2_buf_position (peep2_current + i);
++      old_insn = peep2_insn_data[j].insn;
++      if (!CALL_P (old_insn))
++	continue;
++      was_call = true;
++
++      new_insn = attempt;
++      while (new_insn != NULL_RTX)
++	{
++	  if (CALL_P (new_insn))
++	    break;
++	  new_insn = NEXT_INSN (new_insn);
++	}
++
++      gcc_assert (new_insn != NULL_RTX);
++
++      CALL_INSN_FUNCTION_USAGE (new_insn)
++	= CALL_INSN_FUNCTION_USAGE (old_insn);
++
++      for (note = REG_NOTES (old_insn);
++	   note;
++	   note = XEXP (note, 1))
++	switch (REG_NOTE_KIND (note))
++	  {
++	  case REG_NORETURN:
++	  case REG_SETJMP:
++	    add_reg_note (new_insn, REG_NOTE_KIND (note),
++			  XEXP (note, 0));
++	    break;
++	  default:
++	    /* Discard all other reg notes.  */
++	    break;
++	  }
++
++      /* Croak if there is another call in the sequence.  */
++      while (++i <= match_len)
++	{
++	  j = peep2_buf_position (peep2_current + i);
++	  old_insn = peep2_insn_data[j].insn;
++	  gcc_assert (!CALL_P (old_insn));
++	}
++      break;
++    }
++
++  i = peep2_buf_position (peep2_current + match_len);
++
++  note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
++
++  /* Replace the old sequence with the new.  */
++  last = emit_insn_after_setloc (attempt,
++				 peep2_insn_data[i].insn,
++				 INSN_LOCATOR (peep2_insn_data[i].insn));
++  before_try = PREV_INSN (insn);
++  delete_insn_chain (insn, peep2_insn_data[i].insn, false);
++
++  /* Re-insert the EH_REGION notes.  */
++  if (note || (was_call && nonlocal_goto_handler_labels))
++    {
++      edge eh_edge;
++      edge_iterator ei;
++
++      FOR_EACH_EDGE (eh_edge, ei, bb->succs)
++	if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
++	  break;
++
++      if (note)
++	copy_reg_eh_region_note_backward (note, last, before_try);
++
++      if (eh_edge)
++	for (x = last; x != before_try; x = PREV_INSN (x))
++	  if (x != BB_END (bb)
++	      && (can_throw_internal (x)
++		  || can_nonlocal_goto (x)))
++	    {
++	      edge nfte, nehe;
++	      int flags;
++
++	      nfte = split_block (bb, x);
++	      flags = (eh_edge->flags
++		       & (EDGE_EH | EDGE_ABNORMAL));
++	      if (CALL_P (x))
++		flags |= EDGE_ABNORMAL_CALL;
++	      nehe = make_edge (nfte->src, eh_edge->dest,
++				flags);
++
++	      nehe->probability = eh_edge->probability;
++	      nfte->probability
++		= REG_BR_PROB_BASE - nehe->probability;
++
++	      peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
++	      bb = nfte->src;
++	      eh_edge = nehe;
++	    }
++
++      /* Converting possibly trapping insn to non-trapping is
++	 possible.  Zap dummy outgoing edges.  */
++      peep2_do_cleanup_cfg |= purge_dead_edges (bb);
++    }
++
++  /* If we generated a jump instruction, it won't have
++     JUMP_LABEL set.  Recompute after we're done.  */
++  for (x = last; x != before_try; x = PREV_INSN (x))
++    if (JUMP_P (x))
++      {
++	peep2_do_rebuild_jump_labels = true;
++	break;
++      }
++
++  return last;
++}
++
++/* After performing a replacement in basic block BB, fix up the life
++   information in our buffer.  LAST is the last of the insns that we
++   emitted as a replacement.  PREV is the insn before the start of
++   the replacement.  MATCH_LEN is the number of instructions that were
++   matched, and which now need to be replaced in the buffer.  */
++
++static void
++peep2_update_life (basic_block bb, int match_len, rtx last, rtx prev)
++{
++  int i = peep2_buf_position (peep2_current + match_len + 1);
++  rtx x;
++  regset_head live;
++
++  INIT_REG_SET (&live);
++  COPY_REG_SET (&live, peep2_insn_data[i].live_before);
++
++  gcc_assert (peep2_current_count >= match_len + 1);
++  peep2_current_count -= match_len + 1;
++
++  x = last;
++  do
++    {
++      if (INSN_P (x))
++	{
++	  df_insn_rescan (x);
++	  if (peep2_current_count < MAX_INSNS_PER_PEEP2)
++	    {
++	      peep2_current_count++;
++	      if (--i < 0)
++		i = MAX_INSNS_PER_PEEP2;
++	      peep2_insn_data[i].insn = x;
++	      df_simulate_one_insn_backwards (bb, x, &live);
++	      COPY_REG_SET (peep2_insn_data[i].live_before, &live);
++	    }
++	}
++      x = PREV_INSN (x);
++    }
++  while (x != prev);
++  CLEAR_REG_SET (&live);
++
++  peep2_current = i;
++}
++
++/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
++   Return true if we added it, false otherwise.  The caller will try to match
++   peepholes against the buffer if we return false; otherwise it will try to
++   add more instructions to the buffer.  */
++
++static bool
++peep2_fill_buffer (basic_block bb, rtx insn, regset live)
++{
++  int pos;
++
++  /* Once we have filled the maximum number of insns the buffer can hold,
++     allow the caller to match the insns against peepholes.  We wait until
++     the buffer is full in case the target has similar peepholes of different
++     length; we always want to match the longest if possible.  */
++  if (peep2_current_count == MAX_INSNS_PER_PEEP2)
++    return false;
++
++  /* If an insn has RTX_FRAME_RELATED_P set, peephole substitution would lose
++     the REG_FRAME_RELATED_EXPR that is attached.  */
++  if (RTX_FRAME_RELATED_P (insn))
++    {
++      /* Let the buffer drain first.  */
++      if (peep2_current_count > 0)
++	return false;
++      /* Step over the insn then return true without adding the insn
++	 to the buffer; this will cause us to process the next
++	 insn.  */
++      df_simulate_one_insn_forwards (bb, insn, live);
++      return true;
++    }
++
++  pos = peep2_buf_position (peep2_current + peep2_current_count);
++  peep2_insn_data[pos].insn = insn;
++  COPY_REG_SET (peep2_insn_data[pos].live_before, live);
++  peep2_current_count++;
++
++  df_simulate_one_insn_forwards (bb, insn, live);
++  return true;
++}
++
+ /* Perform the peephole2 optimization pass.  */
+ 
+ static void
+ peephole2_optimize (void)
+ {
+-  rtx insn, prev;
++  rtx insn;
+   bitmap live;
+   int i;
+   basic_block bb;
+-  bool do_cleanup_cfg = false;
+-  bool do_rebuild_jump_labels = false;
++
++  peep2_do_cleanup_cfg = false;
++  peep2_do_rebuild_jump_labels = false;
+ 
+   df_set_flags (DF_LR_RUN_DCE);
++  df_note_add_problem ();
+   df_analyze ();
+ 
+   /* Initialize the regsets we're going to use.  */
+@@ -3126,214 +3346,59 @@
+ 
+   FOR_EACH_BB_REVERSE (bb)
+     {
++      bool past_end = false;
++      int pos;
++
+       rtl_profile_for_bb (bb);
+ 
+       /* Start up propagation.  */
+-      bitmap_copy (live, DF_LR_OUT (bb));
+-      df_simulate_initialize_backwards (bb, live);
++      bitmap_copy (live, DF_LR_IN (bb));
++      df_simulate_initialize_forwards (bb, live);
+       peep2_reinit_state (live);
+ 
+-      for (insn = BB_END (bb); ; insn = prev)
++      insn = BB_HEAD (bb);
++      for (;;)
+ 	{
+-	  prev = PREV_INSN (insn);
+-	  if (NONDEBUG_INSN_P (insn))
++	  rtx attempt, head;
++	  int match_len;
++
++	  if (!past_end && !NONDEBUG_INSN_P (insn))
+ 	    {
+-	      rtx attempt, before_try, x;
+-	      int match_len;
+-	      rtx note;
+-	      bool was_call = false;
+-
+-	      /* Record this insn.  */
+-	      if (--peep2_current < 0)
+-		peep2_current = MAX_INSNS_PER_PEEP2;
+-	      if (peep2_current_count < MAX_INSNS_PER_PEEP2
+-		  && peep2_insn_data[peep2_current].insn == NULL_RTX)
+-		peep2_current_count++;
+-	      peep2_insn_data[peep2_current].insn = insn;
+-	      df_simulate_one_insn_backwards (bb, insn, live);
+-	      COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
+-
+-	      if (RTX_FRAME_RELATED_P (insn))
+-		{
+-		  /* If an insn has RTX_FRAME_RELATED_P set, peephole
+-		     substitution would lose the
+-		     REG_FRAME_RELATED_EXPR that is attached.  */
+-		  peep2_reinit_state (live);
+-		  attempt = NULL;
+-		}
+-	      else
+-		/* Match the peephole.  */
+-		attempt = peephole2_insns (PATTERN (insn), insn, &match_len);
+-
+-	      if (attempt != NULL)
+-		{
+-		  /* If we are splitting a CALL_INSN, look for the CALL_INSN
+-		     in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
+-		     cfg-related call notes.  */
+-		  for (i = 0; i <= match_len; ++i)
+-		    {
+-		      int j;
+-		      rtx old_insn, new_insn, note;
+-
+-		      j = i + peep2_current;
+-		      if (j >= MAX_INSNS_PER_PEEP2 + 1)
+-			j -= MAX_INSNS_PER_PEEP2 + 1;
+-		      old_insn = peep2_insn_data[j].insn;
+-		      if (!CALL_P (old_insn))
+-			continue;
+-		      was_call = true;
+-
+-		      new_insn = attempt;
+-		      while (new_insn != NULL_RTX)
+-			{
+-			  if (CALL_P (new_insn))
+-			    break;
+-			  new_insn = NEXT_INSN (new_insn);
+-			}
+-
+-		      gcc_assert (new_insn != NULL_RTX);
+-
+-		      CALL_INSN_FUNCTION_USAGE (new_insn)
+-			= CALL_INSN_FUNCTION_USAGE (old_insn);
+-
+-		      for (note = REG_NOTES (old_insn);
+-			   note;
+-			   note = XEXP (note, 1))
+-			switch (REG_NOTE_KIND (note))
+-			  {
+-			  case REG_NORETURN:
+-			  case REG_SETJMP:
+-			    add_reg_note (new_insn, REG_NOTE_KIND (note),
+-					  XEXP (note, 0));
+-			    break;
+-			  default:
+-			    /* Discard all other reg notes.  */
+-			    break;
+-			  }
+-
+-		      /* Croak if there is another call in the sequence.  */
+-		      while (++i <= match_len)
+-			{
+-			  j = i + peep2_current;
+-			  if (j >= MAX_INSNS_PER_PEEP2 + 1)
+-			    j -= MAX_INSNS_PER_PEEP2 + 1;
+-			  old_insn = peep2_insn_data[j].insn;
+-			  gcc_assert (!CALL_P (old_insn));
+-			}
+-		      break;
+-		    }
+-
+-		  i = match_len + peep2_current;
+-		  if (i >= MAX_INSNS_PER_PEEP2 + 1)
+-		    i -= MAX_INSNS_PER_PEEP2 + 1;
+-
+-		  note = find_reg_note (peep2_insn_data[i].insn,
+-					REG_EH_REGION, NULL_RTX);
+-
+-		  /* Replace the old sequence with the new.  */
+-		  attempt = emit_insn_after_setloc (attempt,
+-						    peep2_insn_data[i].insn,
+-				       INSN_LOCATOR (peep2_insn_data[i].insn));
+-		  before_try = PREV_INSN (insn);
+-		  delete_insn_chain (insn, peep2_insn_data[i].insn, false);
+-
+-		  /* Re-insert the EH_REGION notes.  */
+-		  if (note || (was_call && nonlocal_goto_handler_labels))
+-		    {
+-		      edge eh_edge;
+-		      edge_iterator ei;
+-
+-		      FOR_EACH_EDGE (eh_edge, ei, bb->succs)
+-			if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
+-			  break;
+-
+-		      if (note)
+-			copy_reg_eh_region_note_backward (note, attempt,
+-							  before_try);
+-
+-		      if (eh_edge)
+-			for (x = attempt ; x != before_try ; x = PREV_INSN (x))
+-			  if (x != BB_END (bb)
+-			      && (can_throw_internal (x)
+-				  || can_nonlocal_goto (x)))
+-			    {
+-			      edge nfte, nehe;
+-			      int flags;
+-
+-			      nfte = split_block (bb, x);
+-			      flags = (eh_edge->flags
+-				       & (EDGE_EH | EDGE_ABNORMAL));
+-			      if (CALL_P (x))
+-				flags |= EDGE_ABNORMAL_CALL;
+-			      nehe = make_edge (nfte->src, eh_edge->dest,
+-						flags);
+-
+-			      nehe->probability = eh_edge->probability;
+-			      nfte->probability
+-				= REG_BR_PROB_BASE - nehe->probability;
+-
+-			      do_cleanup_cfg |= purge_dead_edges (nfte->dest);
+-			      bb = nfte->src;
+-			      eh_edge = nehe;
+-			    }
+-
+-		      /* Converting possibly trapping insn to non-trapping is
+-			 possible.  Zap dummy outgoing edges.  */
+-		      do_cleanup_cfg |= purge_dead_edges (bb);
+-		    }
+-
+-		  if (targetm.have_conditional_execution ())
+-		    {
+-		      for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+-			peep2_insn_data[i].insn = NULL_RTX;
+-		      peep2_insn_data[peep2_current].insn = PEEP2_EOB;
+-		      peep2_current_count = 0;
+-		    }
+-		  else
+-		    {
+-		      /* Back up lifetime information past the end of the
+-			 newly created sequence.  */
+-		      if (++i >= MAX_INSNS_PER_PEEP2 + 1)
+-			i = 0;
+-		      bitmap_copy (live, peep2_insn_data[i].live_before);
+-
+-		      /* Update life information for the new sequence.  */
+-		      x = attempt;
+-		      do
+-			{
+-			  if (INSN_P (x))
+-			    {
+-			      if (--i < 0)
+-				i = MAX_INSNS_PER_PEEP2;
+-			      if (peep2_current_count < MAX_INSNS_PER_PEEP2
+-				  && peep2_insn_data[i].insn == NULL_RTX)
+-				peep2_current_count++;
+-			      peep2_insn_data[i].insn = x;
+-			      df_insn_rescan (x);
+-			      df_simulate_one_insn_backwards (bb, x, live);
+-			      bitmap_copy (peep2_insn_data[i].live_before,
+-					   live);
+-			    }
+-			  x = PREV_INSN (x);
+-			}
+-		      while (x != prev);
+-
+-		      peep2_current = i;
+-		    }
+-
+-		  /* If we generated a jump instruction, it won't have
+-		     JUMP_LABEL set.  Recompute after we're done.  */
+-		  for (x = attempt; x != before_try; x = PREV_INSN (x))
+-		    if (JUMP_P (x))
+-		      {
+-		        do_rebuild_jump_labels = true;
+-			break;
+-		      }
+-		}
++	    next_insn:
++	      insn = NEXT_INSN (insn);
++	      if (insn == NEXT_INSN (BB_END (bb)))
++		past_end = true;
++	      continue;
+ 	    }
++	  if (!past_end && peep2_fill_buffer (bb, insn, live))
++	    goto next_insn;
+ 
+-	  if (insn == BB_HEAD (bb))
++	  /* If we did not fill an empty buffer, it signals the end of the
++	     block.  */
++	  if (peep2_current_count == 0)
+ 	    break;
++
++	  /* The buffer filled to the current maximum, so try to match.  */
++
++	  pos = peep2_buf_position (peep2_current + peep2_current_count);
++	  peep2_insn_data[pos].insn = PEEP2_EOB;
++	  COPY_REG_SET (peep2_insn_data[pos].live_before, live);
++
++	  /* Match the peephole.  */
++	  head = peep2_insn_data[peep2_current].insn;
++	  attempt = peephole2_insns (PATTERN (head), head, &match_len);
++	  if (attempt != NULL)
++	    {
++	      rtx last;
++	      last = peep2_attempt (bb, head, match_len, attempt);
++	      peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
++	    }
++	  else
++	    {
++	      /* If no match, advance the buffer by one insn.  */
++	      peep2_current = peep2_buf_position (peep2_current + 1);
++	      peep2_current_count--;
++	    }
+ 	}
+     }
+ 
+@@ -3341,7 +3406,7 @@
+   for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+     BITMAP_FREE (peep2_insn_data[i].live_before);
+   BITMAP_FREE (live);
+-  if (do_rebuild_jump_labels)
++  if (peep2_do_rebuild_jump_labels)
+     rebuild_jump_labels (get_insns ());
+ }
+ #endif /* HAVE_peephole2 */
+
+=== modified file 'gcc/recog.h'
+--- old/gcc/recog.h	2009-10-26 21:55:59 +0000
++++ new/gcc/recog.h	2010-11-16 12:32:34 +0000
+@@ -194,6 +194,9 @@
+   /* Gives the constraint string for operand N.  */
+   const char *constraints[MAX_RECOG_OPERANDS];
+ 
++  /* Nonzero if operand N is a match_operator or a match_parallel.  */
++  char is_operator[MAX_RECOG_OPERANDS];
++
+   /* Gives the mode of operand N.  */
+   enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
+ 
+@@ -260,6 +263,8 @@
+ 
+   const char strict_low;
+ 
++  const char is_operator;
++
+   const char eliminable;
+ };
+ 
+
+=== modified file 'gcc/reload.c'
+--- old/gcc/reload.c	2009-12-21 16:32:44 +0000
++++ new/gcc/reload.c	2010-11-16 12:32:34 +0000
+@@ -3631,7 +3631,7 @@
+ 		   || modified[j] != RELOAD_WRITE)
+ 		  && j != i
+ 		  /* Ignore things like match_operator operands.  */
+-		  && *recog_data.constraints[j] != 0
++		  && !recog_data.is_operator[j]
+ 		  /* Don't count an input operand that is constrained to match
+ 		     the early clobber operand.  */
+ 		  && ! (this_alternative_matches[j] == i
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch
new file mode 100644
index 0000000000..e8c8e63883
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch
@@ -0,0 +1,157 @@
+	LP: #681138
+	Backport from mainline:
+
+	gcc/
+	* config/arm/sync.md (sync_clobber, sync_t2_reqd): New code attribute.
+	(arm_sync_old_<sync_optab>si, arm_sync_old_<sync_optab><mode>): Use
+	the sync_clobber and sync_t2_reqd code attributes.
+	* config/arm/arm.c (arm_output_sync_loop): Reverse the operation if
+	the t2 argument is NULL.
+
+=== modified file 'gcc/config/arm/arm.c'
+Index: gcc-4_5-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.c
++++ gcc-4_5-branch/gcc/config/arm/arm.c
+@@ -23098,10 +23098,46 @@ arm_output_sync_loop (emit_f emit,
+       break;
+     }
+ 
+-  arm_output_strex (emit, mode, "", t2, t1, memory);
+-  operands[0] = t2;
+-  arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
+-  arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX);
++  if (t2)
++    {
++       arm_output_strex (emit, mode, "", t2, t1, memory);
++       operands[0] = t2;
++       arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
++       arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
++			    LOCAL_LABEL_PREFIX);
++    }
++  else
++    {
++      /* Use old_value for the return value because for some operations
++	 the old_value can easily be restored.  This saves one register.  */
++      arm_output_strex (emit, mode, "", old_value, t1, memory);
++      operands[0] = old_value;
++      arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
++      arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
++			   LOCAL_LABEL_PREFIX);
++
++      switch (sync_op)
++	{
++	case SYNC_OP_ADD:
++	  arm_output_op3 (emit, "sub", old_value, t1, new_value);
++	  break;
++
++	case SYNC_OP_SUB:
++	  arm_output_op3 (emit, "add", old_value, t1, new_value);
++	  break;
++
++	case SYNC_OP_XOR:
++	  arm_output_op3 (emit, "eor", old_value, t1, new_value);
++	  break;
++
++	case SYNC_OP_NONE:
++	  arm_output_op2 (emit, "mov", old_value, required_value);
++	  break;
++
++	default:
++	  gcc_unreachable ();
++	}
++    }
+ 
+   arm_process_output_memory_barrier (emit, NULL);
+   arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
+Index: gcc-4_5-branch/gcc/config/arm/sync.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/sync.md
++++ gcc-4_5-branch/gcc/config/arm/sync.md
+@@ -103,6 +103,18 @@
+ 			      (plus "add")
+ 			      (minus "sub")])
+ 
++(define_code_attr sync_clobber [(ior "=&r")
++				(and "=&r")
++				(xor "X")
++				(plus "X")
++				(minus "X")])
++
++(define_code_attr sync_t2_reqd [(ior "4")
++				(and "4")
++				(xor "*")
++				(plus "*")
++				(minus "*")])
++
+ (define_expand "sync_<sync_optab>si"
+   [(match_operand:SI 0 "memory_operand")
+    (match_operand:SI 1 "s_register_operand")
+@@ -286,7 +298,6 @@
+ 	  VUNSPEC_SYNC_COMPARE_AND_SWAP))
+    (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)]
+                                           VUNSPEC_SYNC_COMPARE_AND_SWAP))
+-   (clobber:SI (match_scratch:SI 4 "=&r"))
+    (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
+                                                 VUNSPEC_SYNC_COMPARE_AND_SWAP))
+    ]
+@@ -299,7 +310,6 @@
+    (set_attr "sync_required_value"  "2")
+    (set_attr "sync_new_value"       "3")
+    (set_attr "sync_t1"              "0")
+-   (set_attr "sync_t2"              "4")
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+@@ -313,7 +323,6 @@
+ 	    VUNSPEC_SYNC_COMPARE_AND_SWAP)))
+    (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)]
+                                           VUNSPEC_SYNC_COMPARE_AND_SWAP))
+-   (clobber:SI (match_scratch:SI 4 "=&r"))
+    (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
+                                                 VUNSPEC_SYNC_COMPARE_AND_SWAP))
+    ]
+@@ -326,7 +335,6 @@
+    (set_attr "sync_required_value"  "2")
+    (set_attr "sync_new_value"       "3")
+    (set_attr "sync_t1"              "0")
+-   (set_attr "sync_t2"              "4")
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+@@ -487,7 +495,7 @@
+ 	                    VUNSPEC_SYNC_OLD_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "<sync_clobber>"))]
+   "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+   {
+     return arm_output_sync_insn (insn, operands);
+@@ -496,7 +504,7 @@
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_new_value"       "2")
+    (set_attr "sync_t1"              "3")
+-   (set_attr "sync_t2"              "4")
++   (set_attr "sync_t2"              "<sync_t2_reqd>")
+    (set_attr "sync_op"              "<sync_optab>")
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+@@ -540,7 +548,7 @@
+ 	                    VUNSPEC_SYNC_OLD_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "<sync_clobber>"))]
+   "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
+   {
+     return arm_output_sync_insn (insn, operands);
+@@ -549,7 +557,7 @@
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_new_value"       "2")
+    (set_attr "sync_t1"              "3")
+-   (set_attr "sync_t2"              "4")
++   (set_attr "sync_t2"              "<sync_t2_reqd>")
+    (set_attr "sync_op"              "<sync_optab>")
+    (set_attr "conds" 		    "clob")
+    (set_attr "predicable" "no")])
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch
new file mode 100644
index 0000000000..32c2999a7c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch
@@ -0,0 +1,94 @@
+2011-01-18  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	LP: #685352
+	Backport from mainline:
+
+	2011-01-18  Jakub Jelinek  <jakub@redhat.com>
+
+	gcc/
+	PR rtl-optimization/47299
+	* expr.c (expand_expr_real_2) <case WIDEN_MULT_EXPR>: Don't use
+	subtarget.  Use normal multiplication if both operands are
+	constants.
+	* expmed.c (expand_widening_mult): Don't try to optimize constant
+	multiplication if op0 has VOIDmode.  Convert op1 constant to mode
+	before using it.
+
+	gcc/testsuite/
+	PR rtl-optimization/47299
+	* gcc.c-torture/execute/pr47299.c: New test.
+
+=== modified file 'gcc/expmed.c'
+Index: gcc-4_5-branch/gcc/expmed.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expmed.c
++++ gcc-4_5-branch/gcc/expmed.c
+@@ -3355,12 +3355,17 @@ expand_widening_mult (enum machine_mode 
+ 		      int unsignedp, optab this_optab)
+ {
+   bool speed = optimize_insn_for_speed_p ();
++  rtx cop1;
+ 
+   if (CONST_INT_P (op1)
+-      && (INTVAL (op1) >= 0
++      && GET_MODE (op0) != VOIDmode
++      && (cop1 = convert_modes (mode, GET_MODE (op0), op1,
++				this_optab == umul_widen_optab))
++      && CONST_INT_P (cop1)
++      && (INTVAL (cop1) >= 0
+ 	  || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT))
+     {
+-      HOST_WIDE_INT coeff = INTVAL (op1);
++      HOST_WIDE_INT coeff = INTVAL (cop1);
+       int max_cost;
+       enum mult_variant variant;
+       struct algorithm algorithm;
+Index: gcc-4_5-branch/gcc/expr.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/expr.c
++++ gcc-4_5-branch/gcc/expr.c
+@@ -7624,10 +7624,10 @@ expand_expr_real_2 (sepops ops, rtx targ
+ 	      if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
+ 		{
+ 		  if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
+-		    expand_operands (treeop0, treeop1, subtarget, &op0, &op1,
++		    expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
+ 				     EXPAND_NORMAL);
+ 		  else
+-		    expand_operands (treeop0, treeop1, subtarget, &op1, &op0,
++		    expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
+ 				     EXPAND_NORMAL);
+ 		  goto binop3;
+ 		}
+@@ -7645,7 +7645,8 @@ expand_expr_real_2 (sepops ops, rtx targ
+ 	  optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
+ 	  this_optab = zextend_p ? umul_widen_optab : smul_widen_optab;
+ 
+-	  if (mode == GET_MODE_2XWIDER_MODE (innermode))
++	  if (mode == GET_MODE_2XWIDER_MODE (innermode)
++	      && TREE_CODE (treeop0) != INTEGER_CST)
+ 	    {
+ 	      if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
+ 		{
+Index: gcc-4_5-branch/gcc/testsuite/gcc.c-torture/execute/pr47299.c
+===================================================================
+--- /dev/null
++++ gcc-4_5-branch/gcc/testsuite/gcc.c-torture/execute/pr47299.c
+@@ -0,0 +1,17 @@
++/* PR rtl-optimization/47299 */
++
++extern void abort (void);
++
++__attribute__ ((noinline, noclone)) unsigned short
++foo (unsigned char x)
++{
++  return x * 255;
++}
++
++int
++main ()
++{
++  if (foo (0x40) != 0x3fc0)
++    abort ();
++  return 0;
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch
new file mode 100644
index 0000000000..580d4f4724
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch
@@ -0,0 +1,38 @@
+2011-01-19  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	Backport from FSF mainline
+
+	2011-01-18  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+        * config/arm/cortex-a9.md (cortex-a9-neon.md): Actually
+        include.
+        (cortex_a9_dp): Handle neon types correctly.
+
+=== modified file 'gcc/config/arm/cortex-a9.md'
+Index: gcc-4_5-branch/gcc/config/arm/cortex-a9.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/cortex-a9.md
++++ gcc-4_5-branch/gcc/config/arm/cortex-a9.md
+@@ -79,10 +79,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cort
+ ;; which can go down E2 without any problem.
+ (define_insn_reservation "cortex_a9_dp" 2
+   (and (eq_attr "tune" "cortexa9")
+-       (ior (eq_attr "type" "alu")
+-	    (ior (and (eq_attr "type" "alu_shift_reg, alu_shift")
+-		 (eq_attr "insn" "mov"))
+-		 (eq_attr "neon_type" "none"))))
++         (ior (and (eq_attr "type" "alu")
++                        (eq_attr "neon_type" "none"))
++	      (and (and (eq_attr "type" "alu_shift_reg, alu_shift")
++			(eq_attr "insn" "mov"))
++                 (eq_attr "neon_type" "none"))))
+   "cortex_a9_p0_default|cortex_a9_p1_default")
+ 
+ ;; An instruction using the shifter will go down E1.
+@@ -263,3 +264,6 @@ cortex_a9_store3_4, cortex_a9_store1_2, 
+   (and (eq_attr "tune" "cortexa9")
+        (eq_attr "type" "fdivd"))
+   "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
++
++;; Include Neon pipeline description
++(include "cortex-a9-neon.md")
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch
new file mode 100644
index 0000000000..cf22aaf16f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch
@@ -0,0 +1,811 @@
+2010-12-13  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	* tree-if-switch-conversion.c: New pass.
+	* tree-pass.h (pass_if_to_switch): Declare.
+	* common.opt (ftree-if-to-switch-conversion): New switch.
+	* opts.c (decode_options): Set flag_tree_if_to_switch_conversion at -O2
+	and higher.
+	* passes.c (init_optimization_passes): Use new pass.
+	* params.def (PARAM_IF_TO_SWITCH_THRESHOLD): New param.
+	* doc/invoke.texi (-ftree-if-to-switch-conversion)
+	(if-to-switch-threshold): New item.
+	* doc/invoke.texi (Optimization Options, option -O2): Add
+	-ftree-if-to-switch-conversion.
+	* Makefile.in (OBJS-common): Add tree-if-switch-conversion.o.
+	* Makefile.in (tree-if-switch-conversion.o): New rule.
+
+=== modified file 'gcc/Makefile.in'
+Index: gcc-4_5-branch/gcc/Makefile.in
+===================================================================
+--- gcc-4_5-branch.orig/gcc/Makefile.in
++++ gcc-4_5-branch/gcc/Makefile.in
+@@ -1354,6 +1354,7 @@ OBJS-common = \
+ 	tree-profile.o \
+ 	tree-scalar-evolution.o \
+ 	tree-sra.o \
++	tree-if-switch-conversion.o \
+ 	tree-switch-conversion.o \
+ 	tree-ssa-address.o \
+ 	tree-ssa-alias.o \
+@@ -3013,6 +3014,11 @@ tree-sra.o : tree-sra.c $(CONFIG_H) $(SY
+    $(TM_H) $(TREE_H) $(GIMPLE_H) $(CGRAPH_H) $(TREE_FLOW_H) $(IPA_PROP_H) \
+    $(DIAGNOSTIC_H) statistics.h $(TREE_DUMP_H) $(TIMEVAR_H) $(PARAMS_H) \
+    $(TARGET_H) $(FLAGS_H) $(EXPR_H) $(TREE_INLINE_H)
++tree-if-switch-conversion.o : tree-if-switch-conversion.c $(CONFIG_H) \
++    $(SYSTEM_H) $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) \
++    $(TREE_INLINE_H) $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) \
++    $(GIMPLE_H) $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) output.h \
++    $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H)
+ tree-switch-conversion.o : tree-switch-conversion.c $(CONFIG_H) $(SYSTEM_H) \
+     $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) $(TREE_INLINE_H) \
+     $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) $(GIMPLE_H) \
+Index: gcc-4_5-branch/gcc/common.opt
+===================================================================
+--- gcc-4_5-branch.orig/gcc/common.opt
++++ gcc-4_5-branch/gcc/common.opt
+@@ -1285,6 +1285,10 @@ ftree-switch-conversion
+ Common Report Var(flag_tree_switch_conversion) Optimization
+ Perform conversions of switch initializations.
+ 
++ftree-if-to-switch-conversion
++Common Report Var(flag_tree_if_to_switch_conversion) Optimization
++Perform conversions of chains of ifs into switches.
++
+ ftree-dce
+ Common Report Var(flag_tree_dce) Optimization
+ Enable SSA dead code elimination optimization on trees
+Index: gcc-4_5-branch/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/invoke.texi
++++ gcc-4_5-branch/gcc/doc/invoke.texi
+@@ -382,7 +382,8 @@ Objective-C and Objective-C++ Dialects}.
+ -fstrict-aliasing -fstrict-overflow -fthread-jumps -ftracer @gol
+ -ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol
+ -ftree-copyrename -ftree-dce @gol
+--ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre -ftree-loop-im @gol
++-ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre @gol
++-ftree-if-to-switch-conversion -ftree-loop-im @gol
+ -ftree-phiprop -ftree-loop-distribution @gol
+ -ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol
+ -ftree-parallelize-loops=@var{n} -ftree-pre -ftree-pta -ftree-reassoc @gol
+@@ -5798,6 +5799,7 @@ also turns on the following optimization
+ -fsched-interblock  -fsched-spec @gol
+ -fschedule-insns  -fschedule-insns2 @gol
+ -fstrict-aliasing -fstrict-overflow @gol
++-ftree-if-to-switch-conversion @gol
+ -ftree-switch-conversion @gol
+ -ftree-pre @gol
+ -ftree-vrp}
+@@ -6634,6 +6636,10 @@ Perform conversion of simple initializat
+ initializations from a scalar array.  This flag is enabled by default
+ at @option{-O2} and higher.
+ 
++@item -ftree-if-to-switch-conversion
++Perform conversion of chains of ifs into switches.  This flag is enabled by
++default at @option{-O2} and higher.
++
+ @item -ftree-dce
+ @opindex ftree-dce
+ Perform dead code elimination (DCE) on trees.  This flag is enabled by
+@@ -8577,6 +8583,12 @@ loop in the loop nest by a given number 
+ length can be changed using the @option{loop-block-tile-size}
+ parameter.  The default value is 51 iterations.
+ 
++@item if-to-switch-threshold
++If-chain to switch conversion, enabled by
++@option{-ftree-if-to-switch-conversion} convert chains of ifs of sufficient
++length into switches.  The parameter @option{if-to-switch-threshold} can be
++used to set the minimal required length.  The default value is 3.
++
+ @end table
+ @end table
+ 
+Index: gcc-4_5-branch/gcc/opts.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/opts.c
++++ gcc-4_5-branch/gcc/opts.c
+@@ -905,6 +905,7 @@ decode_options (unsigned int argc, const
+   flag_tree_builtin_call_dce = opt2;
+   flag_tree_pre = opt2;
+   flag_tree_switch_conversion = opt2;
++  flag_tree_if_to_switch_conversion = opt2;
+   flag_ipa_cp = opt2;
+   flag_ipa_sra = opt2;
+   flag_ee = opt2;
+Index: gcc-4_5-branch/gcc/params.def
+===================================================================
+--- gcc-4_5-branch.orig/gcc/params.def
++++ gcc-4_5-branch/gcc/params.def
+@@ -826,6 +826,11 @@ DEFPARAM (PARAM_IPA_SRA_PTR_GROWTH_FACTO
+ 	  "a pointer to an aggregate with",
+ 	  2, 0, 0)
+ 
++DEFPARAM (PARAM_IF_TO_SWITCH_THRESHOLD,
++	  "if-to-switch-threshold",
++	  "Threshold for converting an if-chain into a switch",
++	  3, 0, 0)
++
+ /*
+ Local variables:
+ mode:c
+Index: gcc-4_5-branch/gcc/passes.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/passes.c
++++ gcc-4_5-branch/gcc/passes.c
+@@ -788,6 +788,7 @@ init_optimization_passes (void)
+ 	  NEXT_PASS (pass_cd_dce);
+ 	  NEXT_PASS (pass_early_ipa_sra);
+ 	  NEXT_PASS (pass_tail_recursion);
++	  NEXT_PASS (pass_if_to_switch);
+ 	  NEXT_PASS (pass_convert_switch);
+           NEXT_PASS (pass_cleanup_eh);
+           NEXT_PASS (pass_profile);
+@@ -844,6 +845,7 @@ init_optimization_passes (void)
+       NEXT_PASS (pass_phiprop);
+       NEXT_PASS (pass_fre);
+       NEXT_PASS (pass_copy_prop);
++      NEXT_PASS (pass_if_to_switch);
+       NEXT_PASS (pass_merge_phi);
+       NEXT_PASS (pass_vrp);
+       NEXT_PASS (pass_dce);
+Index: gcc-4_5-branch/gcc/tree-if-switch-conversion.c
+===================================================================
+--- /dev/null
++++ gcc-4_5-branch/gcc/tree-if-switch-conversion.c
+@@ -0,0 +1,643 @@
++/* Convert a chain of ifs into a switch.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   Contributed by Tom de Vries <tom@codesourcery.com>
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it
++under the terms of the GNU General Public License as published by the
++Free Software Foundation; either version 3, or (at your option) any
++later version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT
++ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not, write to the Free
++Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
++02110-1301, USA.  */
++
++
++/* The following pass converts a chain of ifs into a switch.
++
++   The if-chain has the following properties:
++   - all bbs end in a GIMPLE_COND.
++   - all but the first bb are empty, apart from the GIMPLE_COND.
++   - the GIMPLE_CONDs compare the same variable against integer constants.
++   - the true gotos all target the same bb.
++   - the false gotos target the next in the if-chain.
++
++   F.i., consider the following if-chain:
++   ...
++   <bb 4>:
++   ...
++   if (D.1993_3 == 32)
++     goto <bb 3>;
++   else
++     goto <bb 5>;
++
++   <bb 5>:
++   if (D.1993_3 == 13)
++     goto <bb 3>;
++   else
++     goto <bb 6>;
++
++   <bb 6>:
++   if (D.1993_3 == 10)
++     goto <bb 3>;
++   else
++     goto <bb 7>;
++
++   <bb 7>:
++   if (D.1993_3 == 9)
++     goto <bb 3>;
++   else
++     goto <bb 8>;
++   ...
++
++   The pass will report this if-chain like this:
++   ...
++   var: D.1993_3
++   first: <bb 4>
++   true: <bb 3>
++   last: <bb 7>
++   constants: 9 10 13 32
++   ...
++
++   and then convert the if-chain into a switch:
++   ...
++   <bb 4>:
++   ...
++   switch (D.1993_3) <default: <L8>,
++                      case 9: <L7>,
++                      case 10: <L7>,
++                      case 13: <L7>,
++                      case 32: <L7>>
++   ...
++
++   The conversion does not happen if the chain is too short.  The threshold is
++   determined by the parameter PARAM_IF_TO_SWITCH_THRESHOLD.
++
++   The pass will try to construct a chain for each bb, unless the bb it is
++   already contained in a chain.  This ensures that all chains will be found,
++   and that no chain will be constructed twice.  The pass constructs and
++   converts the chains one-by-one, rather than first calculating all the chains
++   and then doing the conversions.
++
++   The pass could detect range-checks in analyze_bb as well, and handle them.
++   Simple ones, like 'c <= 5', and more complex ones, like
++   '(unsigned char) c + 247 <= 1', which is generated by the C front-end from
++   code like '(c == 9 || c == 10)' or '(9 <= c && c <= 10)'.  */
++
++#include "config.h"
++#include "system.h"
++#include "coretypes.h"
++#include "tm.h"
++
++#include "params.h"
++#include "flags.h"
++#include "tree.h"
++#include "basic-block.h"
++#include "tree-flow.h"
++#include "tree-flow-inline.h"
++#include "tree-ssa-operands.h"
++#include "diagnostic.h"
++#include "tree-pass.h"
++#include "tree-dump.h"
++#include "timevar.h"
++
++/* Information we've collected about a single bb.  */
++
++struct ifsc_info
++{
++  /* The variable of the bb's ending GIMPLE_COND, NULL_TREE if not present.  */
++  tree var;
++  /* The cond_code of the bb's ending GIMPLE_COND.  */
++  enum tree_code cond_code;
++  /* The constant of the bb's ending GIMPLE_COND.  */
++  tree constant;
++  /* Successor edge of the bb if its GIMPLE_COND is true.  */
++  edge true_edge;
++  /* Successor edge of the bb if its GIMPLE_COND is false.  */
++  edge false_edge;
++  /* Set if the bb has valid ifsc_info.  */
++   bool valid;
++  /* Set if the bb is part of a chain.  */
++  bool chained;
++};
++
++/* Macros to access the fields of struct ifsc_info.  */
++
++#define BB_IFSC_VAR(bb) (((struct ifsc_info *)bb->aux)->var)
++#define BB_IFSC_COND_CODE(bb) (((struct ifsc_info *)bb->aux)->cond_code)
++#define BB_IFSC_CONSTANT(bb) (((struct ifsc_info *)bb->aux)->constant)
++#define BB_IFSC_TRUE_EDGE(bb) (((struct ifsc_info *)bb->aux)->true_edge)
++#define BB_IFSC_FALSE_EDGE(bb) (((struct ifsc_info *)bb->aux)->false_edge)
++#define BB_IFSC_VALID(bb) (((struct ifsc_info *)bb->aux)->valid)
++#define BB_IFSC_CHAINED(bb) (((struct ifsc_info *)bb->aux)->chained)
++
++/* Data-type describing an if-chain.  */
++
++struct if_chain
++{
++  /* First bb in the chain.  */
++  basic_block first;
++  /* Last bb in the chain.  */
++  basic_block last;
++  /* Variable that GIMPLE_CONDs of all bbs in chain compare against.  */
++  tree var;
++  /* bb that all GIMPLE_CONDs jump to if comparison succeeds.  */
++  basic_block true_dest;
++  /* Constants that GIMPLE_CONDs of all bbs in chain compare var against.  */
++  VEC (tree, heap) *constants;
++  /* Same as previous, but sorted and with duplicates removed.  */
++  VEC (tree, heap) *unique_constants;
++};
++
++/* Utility macro.  */
++
++#define SWAP(T, X, Y) do { T tmp = (X); (X) = (Y); (Y) = tmp; } while (0)
++
++/* Helper function for sort_constants.  */
++
++static int
++compare_constants (const void *p1, const void *p2)
++{
++  const_tree const c1 = *(const_tree const*)p1;
++  const_tree const c2 = *(const_tree const*)p2;
++
++  return tree_int_cst_compare (c1, c2);
++}
++
++/* Sort constants in constants and copy to unique_constants, while skipping
++   duplicates.  */
++
++static void
++sort_constants (VEC (tree,heap) *constants, VEC (tree,heap) **unique_constants)
++{
++  size_t len = VEC_length (tree, constants);
++  unsigned int ix;
++  tree prev = NULL_TREE, constant;
++
++  /* Sort constants.  */
++  qsort (VEC_address (tree, constants), len, sizeof (tree),
++         compare_constants);
++
++  /* Copy to unique_constants, while skipping duplicates.  */
++  for (ix = 0; VEC_iterate (tree, constants, ix, constant); ix++)
++    {
++      if (prev != NULL_TREE && tree_int_cst_compare (prev, constant) == 0)
++        continue;
++      prev = constant;
++
++      VEC_safe_push (tree, heap, *unique_constants, constant);
++    }
++}
++
++/* Get true_edge and false_edge of a bb ending in a conditional jump.  */
++
++static void
++get_edges (basic_block bb, edge *true_edge, edge *false_edge)
++{
++  edge e0, e1;
++  int e0_true;
++  int n = EDGE_COUNT (bb->succs);
++  gcc_assert (n == 2);
++
++  e0 = EDGE_SUCC (bb, 0);
++  e1 = EDGE_SUCC (bb, 1);
++
++  e0_true = e0->flags & EDGE_TRUE_VALUE;
++
++  *true_edge = e0_true ? e0 : e1;
++  *false_edge = e0_true ? e1 : e0;
++
++  gcc_assert ((*true_edge)->flags & EDGE_TRUE_VALUE);
++  gcc_assert ((*false_edge)->flags & EDGE_FALSE_VALUE);
++
++  gcc_assert (((*true_edge)->flags & EDGE_FALLTHRU) == 0);
++  gcc_assert (((*false_edge)->flags & EDGE_FALLTHRU) == 0);
++}
++
++/* Analyze bb and store results in ifsc_info struct.  */
++
++static void
++analyze_bb (basic_block bb)
++{
++  gimple stmt = last_stmt (bb);
++  tree lhs, rhs, var, constant;
++  edge true_edge, false_edge;
++  enum tree_code cond_code;
++
++  /* Don't redo analysis.  */
++  if (BB_IFSC_VALID (bb))
++    return;
++  BB_IFSC_VALID (bb) = true;
++
++
++  /* bb needs to end in GIMPLE_COND.  */
++  if (!stmt || gimple_code (stmt) != GIMPLE_COND)
++    return;
++
++  /* bb needs to end in EQ_EXPR or NE_EXPR.  */
++  cond_code = gimple_cond_code (stmt);
++  if (cond_code != EQ_EXPR && cond_code != NE_EXPR)
++    return;
++
++  lhs = gimple_cond_lhs (stmt);
++  rhs = gimple_cond_rhs (stmt);
++
++  /* GIMPLE_COND needs to compare variable to constant.  */
++  if ((TREE_CONSTANT (lhs) == 0)
++      == (TREE_CONSTANT (rhs) == 0))
++    return;
++
++  var = TREE_CONSTANT (lhs) ? rhs : lhs;
++  constant = TREE_CONSTANT (lhs)? lhs : rhs;
++
++  /* Switches cannot handle non-integral types.  */
++  if (!INTEGRAL_TYPE_P(TREE_TYPE (var)))
++    return;
++
++  get_edges (bb, &true_edge, &false_edge);
++
++  if (cond_code == NE_EXPR)
++    SWAP (edge, true_edge, false_edge);
++
++  /* TODO: loosen this constraint.  In principle it's ok if true_edge->dest has
++     phis, as long as for each phi all the edges coming from the chain have the
++     same value.  */
++  if (!gimple_seq_empty_p (phi_nodes (true_edge->dest)))
++    return;
++
++  /* Store analysis in ifsc_info struct.  */
++  BB_IFSC_VAR (bb) = var;
++  BB_IFSC_COND_CODE (bb) = cond_code;
++  BB_IFSC_CONSTANT (bb) = constant;
++  BB_IFSC_TRUE_EDGE (bb) = true_edge;
++  BB_IFSC_FALSE_EDGE (bb) = false_edge;
++}
++
++/* Grow if-chain forward.  */
++
++static void
++grow_if_chain_forward (struct if_chain *chain)
++{
++  basic_block next_bb;
++
++  while (1)
++    {
++      next_bb = BB_IFSC_FALSE_EDGE (chain->last)->dest;
++
++      /* next_bb is already part of another chain.  */
++      if (BB_IFSC_CHAINED (next_bb))
++        break;
++
++      /* next_bb needs to be dominated by the last bb.  */
++      if (!single_pred_p (next_bb))
++        break;
++
++      analyze_bb (next_bb);
++
++      /* Does next_bb fit in chain?  */
++      if (BB_IFSC_VAR (next_bb) != chain->var
++          || BB_IFSC_TRUE_EDGE (next_bb)->dest != chain->true_dest)
++        break;
++
++      /* We can only add empty bbs at the end of the chain.  */
++      if (first_stmt (next_bb) != last_stmt (next_bb))
++        break;
++
++      /* Add next_bb at end of chain.  */
++      VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (next_bb));
++      BB_IFSC_CHAINED (next_bb) = true;
++      chain->last = next_bb;
++    }
++}
++
++/* Grow if-chain backward.  */
++
++static void
++grow_if_chain_backward (struct if_chain *chain)
++{
++  basic_block prev_bb;
++
++  while (1)
++    {
++      /* First bb is not empty, cannot grow backwards.  */
++      if (first_stmt (chain->first) != last_stmt (chain->first))
++        break;
++
++      /* First bb has no single predecessor, cannot grow backwards.  */
++      if (!single_pred_p (chain->first))
++        break;
++
++      prev_bb = single_pred (chain->first);
++
++      /* prev_bb is already part of another chain.  */
++      if (BB_IFSC_CHAINED (prev_bb))
++        break;
++
++      analyze_bb (prev_bb);
++
++      /* Does prev_bb fit in chain?  */
++      if (BB_IFSC_VAR (prev_bb) != chain->var
++          || BB_IFSC_TRUE_EDGE (prev_bb)->dest != chain->true_dest)
++        break;
++
++      /* Add prev_bb at beginning of chain.  */
++      VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (prev_bb));
++      BB_IFSC_CHAINED (prev_bb) = true;
++      chain->first = prev_bb;
++    }
++}
++
++/* Grow if-chain containing bb.  */
++
++static void
++grow_if_chain (basic_block bb, struct if_chain *chain)
++{
++  /* Initialize chain to empty.  */
++  VEC_truncate (tree, chain->constants, 0);
++  VEC_truncate (tree, chain->unique_constants, 0);
++
++  /* bb is already part of another chain.  */
++  if (BB_IFSC_CHAINED (bb))
++    return;
++
++  analyze_bb (bb);
++
++  /* bb is not fit to be part of a chain.  */
++  if (BB_IFSC_VAR (bb) == NULL_TREE)
++    return;
++
++  /* Set bb as initial part of the chain.  */
++  VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (bb));
++  chain->first = chain->last = bb;
++  chain->var = BB_IFSC_VAR (bb);
++  chain->true_dest = BB_IFSC_TRUE_EDGE (bb)->dest;
++
++  /* bb is part of a chain now.  */
++  BB_IFSC_CHAINED (bb) = true;
++
++  /* Grow chain to its maximum size.  */
++  grow_if_chain_forward (chain);
++  grow_if_chain_backward (chain);
++
++  /* Sort constants and skip duplicates.  */
++  sort_constants (chain->constants, &chain->unique_constants);
++}
++
++static void
++dump_tree_vector (VEC (tree, heap) *vec)
++{
++  unsigned int ix;
++  tree constant;
++
++  for (ix = 0; VEC_iterate (tree, vec, ix, constant); ix++)
++    {
++      if (ix != 0)
++        fprintf (dump_file, " ");
++      print_generic_expr (dump_file, constant, 0);
++    }
++  fprintf (dump_file, "\n");
++}
++
++/* Dump if-chain to dump_file.  */
++
++static void
++dump_if_chain (struct if_chain *chain)
++{
++  if (!dump_file)
++    return;
++
++  fprintf (dump_file, "var: ");
++  print_generic_expr (dump_file, chain->var, 0);
++  fprintf (dump_file, "\n");
++  fprintf (dump_file, "first: <bb %d>\n", chain->first->index);
++  fprintf (dump_file, "true: <bb %d>\n", chain->true_dest->index);
++  fprintf (dump_file, "last: <bb %d>\n",chain->last->index);
++
++  fprintf (dump_file, "constants: ");
++  dump_tree_vector (chain->constants);
++
++  if (VEC_length (tree, chain->unique_constants)
++      != VEC_length (tree, chain->constants))
++    {
++      fprintf (dump_file, "unique_constants: ");
++      dump_tree_vector (chain->unique_constants);
++    }
++}
++
++/* Remove redundant bbs and edges.  */
++
++static void
++remove_redundant_bbs_and_edges (struct if_chain *chain, int *false_prob)
++{
++  basic_block bb, next;
++  edge true_edge, false_edge;
++
++  for (bb = chain->first;; bb = next)
++    {
++      true_edge = BB_IFSC_TRUE_EDGE (bb);
++      false_edge = BB_IFSC_FALSE_EDGE (bb);
++
++      /* Determine next, before we delete false_edge.  */
++      next = false_edge->dest;
++
++      /* Accumulate probability.  */
++      *false_prob = (*false_prob * false_edge->probability) / REG_BR_PROB_BASE;
++
++      /* Don't remove the new true_edge.  */
++      if (bb != chain->first)
++        remove_edge (true_edge);
++
++      /* Don't remove the new false_edge.  */
++      if (bb != chain->last)
++        remove_edge (false_edge);
++
++      /* Don't remove the first bb.  */
++      if (bb != chain->first)
++        delete_basic_block (bb);
++
++      /* Stop after last.  */
++      if (bb == chain->last)
++        break;
++    }
++}
++
++/* Update control flow graph.  */
++
++static void
++update_cfg (struct if_chain *chain)
++{
++  edge true_edge, false_edge;
++  int false_prob;
++  int flags_mask = ~(EDGE_FALLTHRU|EDGE_TRUE_VALUE|EDGE_FALSE_VALUE);
++
++  /* We keep these 2 edges, and remove the rest.  We need this specific
++     false_edge, because a phi in chain->last->dest might reference (the index
++     of) this edge.  For true_edge, we could pick any of them.  */
++  true_edge = BB_IFSC_TRUE_EDGE (chain->first);
++  false_edge = BB_IFSC_FALSE_EDGE (chain->last);
++
++  /* Update true edge.  */
++  true_edge->flags &= flags_mask;
++
++  /* Update false edge.  */
++  redirect_edge_pred (false_edge, chain->first);
++  false_edge->flags &= flags_mask;
++
++  false_prob = REG_BR_PROB_BASE;
++  remove_redundant_bbs_and_edges (chain, &false_prob);
++
++  /* Repair probabilities.  */
++  true_edge->probability = REG_BR_PROB_BASE - false_prob;
++  false_edge->probability = false_prob;
++
++  /* Force recalculation of dominance info.  */
++  free_dominance_info (CDI_DOMINATORS);
++  free_dominance_info (CDI_POST_DOMINATORS);
++}
++
++/* Create switch statement.  Borrows from gimplify_switch_expr.  */
++
++static void
++convert_if_chain_to_switch (struct if_chain *chain)
++{
++  tree label_decl_true, label_decl_false;
++  gimple label_true, label_false, gimple_switch;
++  gimple_stmt_iterator gsi;
++  tree default_case, other_case, constant;
++  unsigned int ix;
++  VEC (tree, heap) *labels;
++
++  labels = VEC_alloc (tree, heap, 8);
++
++  /* Create and insert true jump label.  */
++  label_decl_true = create_artificial_label (UNKNOWN_LOCATION);
++  label_true = gimple_build_label (label_decl_true);
++  gsi = gsi_start_bb (chain->true_dest);
++  gsi_insert_before (&gsi, label_true, GSI_SAME_STMT);
++
++  /* Create and insert false jump label.  */
++  label_decl_false = create_artificial_label (UNKNOWN_LOCATION);
++  label_false = gimple_build_label (label_decl_false);
++  gsi = gsi_start_bb (BB_IFSC_FALSE_EDGE (chain->last)->dest);
++  gsi_insert_before (&gsi, label_false, GSI_SAME_STMT);
++
++  /* Create default case label.  */
++  default_case = build3 (CASE_LABEL_EXPR, void_type_node,
++                         NULL_TREE, NULL_TREE,
++                         label_decl_false);
++
++  /* Create case labels.  */
++  for (ix = 0; VEC_iterate (tree, chain->unique_constants, ix, constant); ix++)
++    {
++      /* TODO: use ranges, as in gimplify_switch_expr.  */
++      other_case = build3 (CASE_LABEL_EXPR, void_type_node,
++                           constant, NULL_TREE,
++                           label_decl_true);
++      VEC_safe_push (tree, heap, labels, other_case);
++    }
++
++  /* Create and insert switch.  */
++  gimple_switch = gimple_build_switch_vec (chain->var, default_case, labels);
++  gsi = gsi_for_stmt (last_stmt (chain->first));
++  gsi_insert_before (&gsi, gimple_switch, GSI_SAME_STMT);
++
++  /* Remove now obsolete if.  */
++  gsi_remove (&gsi, true);
++
++  VEC_free (tree, heap, labels);
++}
++
++/* Allocation and initialization.  */
++
++static void
++init_pass (struct if_chain *chain)
++{
++  alloc_aux_for_blocks (sizeof (struct ifsc_info));
++
++  chain->constants = VEC_alloc (tree, heap, 8);
++  chain->unique_constants = VEC_alloc (tree, heap, 8);
++}
++
++/* Deallocation.  */
++
++static void
++finish_pass (struct if_chain *chain)
++{
++  free_aux_for_blocks ();
++
++  VEC_free (tree, heap, chain->constants);
++  VEC_free (tree, heap, chain->unique_constants);
++}
++
++/* Find if-chains and convert them to switches.  */
++
++static unsigned int
++do_if_to_switch (void)
++{
++  basic_block bb;
++  struct if_chain chain;
++  unsigned int convert_threshold = PARAM_VALUE (PARAM_IF_TO_SWITCH_THRESHOLD);
++
++  init_pass (&chain);
++
++  for (bb = cfun->cfg->x_entry_block_ptr->next_bb;
++       bb != cfun->cfg->x_exit_block_ptr;)
++    {
++      grow_if_chain (bb, &chain);
++
++      do
++        bb = bb->next_bb;
++      while (BB_IFSC_CHAINED (bb));
++
++      /* Determine if the chain is long enough.  */
++      if (VEC_length (tree, chain.unique_constants) < convert_threshold)
++        continue;
++
++      dump_if_chain (&chain);
++
++      convert_if_chain_to_switch (&chain);
++
++      update_cfg (&chain);
++    }
++
++  finish_pass (&chain);
++
++  return 0;
++}
++
++/* The pass gate.  */
++
++static bool
++if_to_switch_gate (void)
++{
++  return flag_tree_if_to_switch_conversion;
++}
++
++/* The pass definition.  */
++
++struct gimple_opt_pass pass_if_to_switch =
++{
++ {
++  GIMPLE_PASS,
++  "iftoswitch",                         /* name */
++  if_to_switch_gate,                    /* gate */
++  do_if_to_switch,                      /* execute */
++  NULL,                                 /* sub */
++  NULL,                                 /* next */
++  0,                                    /* static_pass_number */
++  TV_TREE_SWITCH_CONVERSION,            /* tv_id */
++  PROP_cfg | PROP_ssa,                  /* properties_required */
++  0,                                    /* properties_provided */
++  0,                                    /* properties_destroyed */
++  0,                                    /* todo_flags_start */
++  TODO_update_ssa | TODO_dump_func
++  | TODO_ggc_collect | TODO_verify_ssa  /* todo_flags_finish */
++ }
++};
+Index: gcc-4_5-branch/gcc/tree-pass.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/tree-pass.h
++++ gcc-4_5-branch/gcc/tree-pass.h
+@@ -560,6 +560,7 @@ extern struct gimple_opt_pass pass_inlin
+ extern struct gimple_opt_pass pass_all_early_optimizations;
+ extern struct gimple_opt_pass pass_update_address_taken;
+ extern struct gimple_opt_pass pass_convert_switch;
++extern struct gimple_opt_pass pass_if_to_switch;
+ 
+ /* The root of the compilation pass tree, once constructed.  */
+ extern struct opt_pass *all_passes, *all_small_ipa_passes, *all_lowering_passes,
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch
new file mode 100644
index 0000000000..3ac7f7f6fd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch
@@ -0,0 +1,409 @@
+2010-02-04  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	stmt.c (set_jump_prob): Fix assert condition.
+
+2010-01-27  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	stmt.c (rtx_seq_cost): Use insn_rtx_cost instead of rtx_cost.
+
+2010-01-26  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	* stmt.c (struct  case_bit_test): Add rev_hi and rev_lo field.
+	* stmt.c (emit_case_bit_test_jump): New function.
+	* stmt.c (rtx_seq_cost): New function.
+	* stmt.c (choose_case_bit_test_expand_method): New function.
+	* stmt.c (set_bit): New function.
+	* stmt.c (emit_case_bit_test): Adjust comment.
+	* stmt.c (emit_case_bit_test): Set and update rev_hi and rev_lo fields.
+	* stmt.c (emit_case_bit_test): Use set_bit.
+	* stmt.c (emit_case_bit_test): Use choose_case_bit_test_expand_method.
+	* stmt.c (emit_case_bit_test): Use emit_case_bit_test_jump.
+	* testsuite/gcc.dg/switch-bittest.c: New test.
+
+2010-01-25  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	* stmt.c (emit_case_bit_tests): Change prototype.
+	* stmt.c (struct case_bit_test): Add prob field.
+	* stmt.c (get_label_prob): New function.
+	* stmt.c (set_jump_prob): New function.
+	* stmt.c (emit_case_bit_tests): Use get_label_prob.
+	* stmt.c (emit_case_bit_tests): Set prob field.
+	* stmt.c (emit_case_bit_tests): Use set_jump_prob.
+	* stmt.c (expand_case): Add new args to emit_case_bit_tests invocation.
+	* testsuite/gcc.dg/switch-prob.c: Add test.
+
+=== modified file 'gcc/stmt.c'
+Index: gcc-4_5-branch/gcc/stmt.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/stmt.c
++++ gcc-4_5-branch/gcc/stmt.c
+@@ -117,7 +117,8 @@ static void expand_value_return (rtx);
+ static int estimate_case_costs (case_node_ptr);
+ static bool lshift_cheap_p (void);
+ static int case_bit_test_cmp (const void *, const void *);
+-static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, rtx);
++static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, tree,
++                                 rtx, basic_block);
+ static void balance_case_nodes (case_node_ptr *, case_node_ptr);
+ static int node_has_low_bound (case_node_ptr, tree);
+ static int node_has_high_bound (case_node_ptr, tree);
+@@ -2107,8 +2108,11 @@ struct case_bit_test
+ {
+   HOST_WIDE_INT hi;
+   HOST_WIDE_INT lo;
++  HOST_WIDE_INT rev_hi;
++  HOST_WIDE_INT rev_lo;
+   rtx label;
+   int bits;
++  int prob;
+ };
+ 
+ /* Determine whether "1 << x" is relatively cheap in word_mode.  */
+@@ -2148,10 +2152,193 @@ case_bit_test_cmp (const void *p1, const
+   return CODE_LABEL_NUMBER (d2->label) - CODE_LABEL_NUMBER (d1->label);
+ }
+ 
++/* Emit a bit test and a conditional jump.  */
++
++static void
++emit_case_bit_test_jump (unsigned int count, rtx index, rtx label,
++                         unsigned int method, HOST_WIDE_INT hi,
++                         HOST_WIDE_INT lo, HOST_WIDE_INT rev_hi,
++                         HOST_WIDE_INT rev_lo)
++{
++  rtx expr;
++
++  if (method == 1)
++    {
++      /* (1 << index). */
++      if (count == 0)
++        index = expand_binop (word_mode, ashl_optab, const1_rtx,
++                              index, NULL_RTX, 1, OPTAB_WIDEN);
++      /* CST.  */
++      expr = immed_double_const (lo, hi, word_mode);
++      /* ((1 << index) & CST).  */
++      expr = expand_binop (word_mode, and_optab, index, expr,
++                           NULL_RTX, 1, OPTAB_WIDEN);
++      /* if (((1 << index) & CST)).   */
++      emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX,
++                               word_mode, 1, label);
++    }
++  else if (method == 2)
++    {
++      /* (bit_reverse (CST)) */
++      expr = immed_double_const (rev_lo, rev_hi, word_mode);
++      /* ((bit_reverse (CST)) << index) */
++      expr = expand_binop (word_mode, ashl_optab, expr,
++                           index, NULL_RTX, 1, OPTAB_WIDEN);
++      /* if (((bit_reverse (CST)) << index) < 0).  */
++      emit_cmp_and_jump_insns (expr, const0_rtx, LT, NULL_RTX,
++                               word_mode, 0, label);
++    }
++  else
++    gcc_unreachable ();
++}
++
++/* Return the cost of rtx sequence SEQ.  The sequence is supposed to contain one
++   jump, which has no effect in the cost.  */
++
++static unsigned int
++rtx_seq_cost (rtx seq)
++{
++  rtx one;
++  unsigned int nr_branches = 0;
++  unsigned int sum = 0, cost;
++
++  for (one = seq; one != NULL_RTX; one = NEXT_INSN (one))
++    if (JUMP_P (one))
++      nr_branches++;
++    else
++      {
++        cost = insn_rtx_cost (PATTERN (one), optimize_insn_for_speed_p ());
++        if (dump_file)
++          {
++            print_rtl_single (dump_file, one);
++            fprintf (dump_file, "cost: %u\n", cost);
++          }
++        sum += cost;
++      }
++
++  gcc_assert (nr_branches == 1);
++
++  if (dump_file)
++    fprintf (dump_file, "total cost: %u\n", sum);
++  return sum;
++}
++
++/* Generate the rtx sequences for 2 bit test expansion methods, measure the cost
++   and choose the cheapest.  */
++
++static unsigned int
++choose_case_bit_test_expand_method (rtx label)
++{
++  rtx seq, index;
++  unsigned int cost[2];
++  static bool method_known = false;
++  static unsigned int method;
++
++  /* If already known, return the method.  */
++  if (method_known)
++    return method;
++
++  index = gen_rtx_REG (word_mode, 10000);
++
++  for (method = 1; method <= 2; ++method)
++    {
++      start_sequence ();
++      emit_case_bit_test_jump (0, index, label, method, 0, 0x0f0f0f0f, 0,
++                               0x0f0f0f0f);
++      seq = get_insns ();
++      end_sequence ();
++      cost[method - 1] = rtx_seq_cost (seq);
++    }
++
++  /* Determine method based on heuristic.  */
++  method = ((cost[1] < cost[0]) ? 1 : 0) + 1;
++
++  /* Save and return method.  */
++  method_known = true;
++  return method;
++}
++
++/* Get the edge probability of the edge from SRC to LABEL_DECL.  */
++
++static int
++get_label_prob (basic_block src, tree label_decl)
++{
++  basic_block dest;
++  int prob = 0, nr_prob = 0;
++  unsigned int i;
++  edge e;
++
++  if (label_decl == NULL_TREE)
++    return 0;
++
++  dest = VEC_index (basic_block, label_to_block_map,
++                    LABEL_DECL_UID (label_decl));
++
++  for (i = 0; i < EDGE_COUNT (src->succs); ++i)
++    {
++      e = EDGE_SUCC (src, i);
++
++      if (e->dest != dest)
++        continue;
++
++      prob += e->probability;
++      nr_prob++;
++    }
++
++  gcc_assert (nr_prob == 1);
++
++  return prob;
++}
++
++/* Add probability note with scaled PROB to JUMP and update INV_SCALE.  This
++   function is intended to be used with a series of conditional jumps to L[i]
++   where the probabilities p[i] to get to L[i] are known, and the jump
++   probabilities j[i] need to be computed.
++
++   The algorithm to calculate the probabilities is
++
++   scale = REG_BR_PROB_BASE;
++   for (i = 0; i < n; ++i)
++     {
++       j[i] = p[i] * scale / REG_BR_PROB_BASE;
++       f[i] = REG_BR_PROB_BASE - j[i];
++       scale = scale / (f[i] / REG_BR_PROB_BASE);
++     }
++
++   The implementation uses inv_scale (REG_BR_PROB_BASE / scale) instead of
++   scale, because scale tends to grow bigger than REG_BR_PROB_BASE.  */
++
++static void
++set_jump_prob (rtx jump, int prob, int *inv_scale)
++{
++  /* j[i] = p[i] * scale / REG_BR_PROB_BASE.  */
++  int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale;
++  /* f[i] = REG_BR_PROB_BASE - j[i].  */
++  int fallthrough_prob = REG_BR_PROB_BASE - jump_prob;
++
++  gcc_assert (jump_prob <= REG_BR_PROB_BASE);
++  add_reg_note (jump, REG_BR_PROB, GEN_INT (jump_prob));
++
++  /* scale = scale / (f[i] / REG_BR_PROB_BASE).  */
++  *inv_scale = *inv_scale * fallthrough_prob / REG_BR_PROB_BASE;
++}
++
++/* Set bit in hwi hi/lo pair.  */
++
++static void
++set_bit (HOST_WIDE_INT *hi, HOST_WIDE_INT *lo, unsigned int j)
++{
++  if (j >= HOST_BITS_PER_WIDE_INT)
++    *hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT);
++  else
++    *lo |= (HOST_WIDE_INT) 1 << j;
++}
++
+ /*  Expand a switch statement by a short sequence of bit-wise
+     comparisons.  "switch(x)" is effectively converted into
+-    "if ((1 << (x-MINVAL)) & CST)" where CST and MINVAL are
+-    integer constants.
++    "if ((1 << (x-MINVAL)) & CST)" or
++    "if (((bit_reverse (CST)) << (x-MINVAL)) < 0)", where CST
++    and MINVAL are integer constants.
+ 
+     INDEX_EXPR is the value being switched on, which is of
+     type INDEX_TYPE.  MINVAL is the lowest case value of in
+@@ -2165,14 +2352,17 @@ case_bit_test_cmp (const void *p1, const
+ 
+ static void
+ emit_case_bit_tests (tree index_type, tree index_expr, tree minval,
+-		     tree range, case_node_ptr nodes, rtx default_label)
++		     tree range, case_node_ptr nodes, tree default_label_decl,
++		     rtx default_label, basic_block bb)
+ {
+   struct case_bit_test test[MAX_CASE_BIT_TESTS];
+   enum machine_mode mode;
+   rtx expr, index, label;
+   unsigned int i,j,lo,hi;
+   struct case_node *n;
+-  unsigned int count;
++  unsigned int count, method;
++  int inv_scale = REG_BR_PROB_BASE;
++  int default_prob = get_label_prob (bb, default_label_decl);
+ 
+   count = 0;
+   for (n = nodes; n; n = n->right)
+@@ -2187,8 +2377,11 @@ emit_case_bit_tests (tree index_type, tr
+ 	  gcc_assert (count < MAX_CASE_BIT_TESTS);
+ 	  test[i].hi = 0;
+ 	  test[i].lo = 0;
++	  test[i].rev_hi = 0;
++	  test[i].rev_lo = 0;
+ 	  test[i].label = label;
+ 	  test[i].bits = 1;
++	  test[i].prob = get_label_prob (bb, n->code_label);
+ 	  count++;
+ 	}
+       else
+@@ -2199,10 +2392,11 @@ emit_case_bit_tests (tree index_type, tr
+       hi = tree_low_cst (fold_build2 (MINUS_EXPR, index_type,
+ 				      n->high, minval), 1);
+       for (j = lo; j <= hi; j++)
+-        if (j >= HOST_BITS_PER_WIDE_INT)
+-	  test[i].hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT);
+-	else
+-	  test[i].lo |= (HOST_WIDE_INT) 1 << j;
++        {
++          set_bit (&test[i].hi, &test[i].lo, j);
++          set_bit (&test[i].rev_hi, &test[i].rev_lo,
++                   GET_MODE_BITSIZE (word_mode) - j - 1);
++        }
+     }
+ 
+   qsort (test, count, sizeof(*test), case_bit_test_cmp);
+@@ -2216,20 +2410,20 @@ emit_case_bit_tests (tree index_type, tr
+   mode = TYPE_MODE (index_type);
+   expr = expand_normal (range);
+   if (default_label)
+-    emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1,
+-			     default_label);
++    {
++      emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1,
++                               default_label);
++      set_jump_prob (get_last_insn (), default_prob / 2, &inv_scale);
++    }
+ 
+   index = convert_to_mode (word_mode, index, 0);
+-  index = expand_binop (word_mode, ashl_optab, const1_rtx,
+-			index, NULL_RTX, 1, OPTAB_WIDEN);
+ 
++  method = choose_case_bit_test_expand_method (test[0].label);
+   for (i = 0; i < count; i++)
+     {
+-      expr = immed_double_const (test[i].lo, test[i].hi, word_mode);
+-      expr = expand_binop (word_mode, and_optab, index, expr,
+-			   NULL_RTX, 1, OPTAB_WIDEN);
+-      emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX,
+-			       word_mode, 1, test[i].label);
++      emit_case_bit_test_jump (i, index, test[i].label, method, test[i].hi,
++                               test[i].lo, test[i].rev_hi, test[i].rev_lo);
++      set_jump_prob (get_last_insn (), test[i].prob, &inv_scale);
+     }
+ 
+   if (default_label)
+@@ -2400,7 +2594,8 @@ expand_case (gimple stmt)
+ 	      range = maxval;
+ 	    }
+ 	  emit_case_bit_tests (index_type, index_expr, minval, range,
+-			       case_list, default_label);
++			       case_list, default_label_decl, default_label,
++			       gimple_bb (stmt));
+ 	}
+ 
+       /* If range of values is much bigger than number of values,
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-bittest.c
+===================================================================
+--- /dev/null
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-bittest.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-expand" } */
++
++const char *
++f (const char *p)
++{
++  while (1)
++    {
++      switch (*p)
++        {
++        case 9:
++        case 10:
++        case 13:
++        case 32:
++          break;
++        default:
++          return p;
++        }
++    }
++}
++
++/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "lt " 1 "expand"  { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "expand" } } */
+Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-prob.c
+===================================================================
+--- /dev/null
++++ gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-prob.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-expand" } */
++
++const char *
++f (const char *p)
++{
++  while (1)
++    {
++      switch (*p)
++        {
++        case 9:
++        case 10:
++        case 13:
++        case 32:
++          break;
++        default:
++          return p;
++        }
++    }
++}
++
++/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */
++/* { dg-final { scan-rtl-dump-times "heuristics" 0 "expand"  { target mips*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "expand" } } */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch
new file mode 100644
index 0000000000..9b0fb0b488
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch
@@ -0,0 +1,3346 @@
+2011-01-14  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* function.c (thread_prologue_and_epilogue_insns): Avoid uninitialized
+	variable.
+
+2011-01-12  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* config/s390/s390.c (s390_emit_epilogue): Don't use gen_rtx_RETURN.
+	* config/rx/rx.c (gen_rx_rtsd_vector): Likewise.
+	* config/m68hc11/m68hc11.md (return): Likewise.
+	* config/cris/cris.c (cris_expand_return): Likewise.
+	* config/m68k/m68k.c (m68k_expand_epilogue): Likewise.
+	* config/picochip/picochip.c (picochip_expand_epilogue): Likewise.
+	* config/h8300/h8300.c (h8300_push_pop, h8300_expand_epilogue):
+	Likewise.
+	* config/v850/v850.c (expand_epilogue): Likewise.
+	* config/bfin/bfin.c (bfin_expand_call): Likewise.
+
+2011-01-04  Catherine Moore  <clm@codesourcery.com>
+
+	gcc/
+	* config/rs6000/rs6000.c (rs6000_make_savres_rtx): Change
+	gen_rtx_RETURN to ret_rtx.
+	(rs6000_emit_epilogue): Likewise.
+	(rs6000_output_mi_thunk): Likewise.
+
+2011-01-03  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* doc/tm.texi (RETURN_ADDR_REGNUM): Document.
+	* doc/md.texi (simple_return): Document pattern.
+	(return): Add a sentence to clarify.
+	* doc/rtl.texi (simple_return): Document.
+	* doc/invoke.texi (Optimize Options): Document -fshrink-wrap.
+	* common.opt (fshrink-wrap): New.
+	* opts.c (decode_options): Set it for -O2 and above.
+	* gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN
+	are special.
+	* rtl.h (ANY_RETURN_P): New macro.
+	(global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN.
+	(ret_rtx, simple_return_rtx): New macros.
+	* genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs.
+	(gen_expand, gen_split): Use ANY_RETURN_P.
+	* rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared.
+	* emit-rtl.c (verify_rtx_sharing): Likewise.
+	(skip_consecutive_labels): Return the argument if it is a return rtx.
+	(classify_insn): Handle both kinds of return.
+	(init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx.
+	* df-scan.c (df_uses_record): Handle SIMPLE_RETURN.
+	* rtl.def (SIMPLE_RETURN): New.
+	* rtlanal.c (tablejump_p): Check JUMP_LABEL for returns.
+	* final.c (final_scan_insn): Recognize both kinds of return.
+	* reorg.c (function_return_label, function_simple_return_label): New
+	static variables.
+	(end_of_function_label): Remove.
+	(simplejump_or_return_p): New static function.
+	(find_end_label): Add a new arg, KIND.  All callers changed.
+	Depending on KIND, look for a label suitable for return or
+	simple_return.
+	(make_return_insns): Make corresponding changes.
+	(get_jump_flags): Check JUMP_LABELs for returns.
+	(follow_jumps): Likewise.
+	(get_branch_condition): Check target for return patterns rather
+	than NULL.
+	(own_thread_p): Likewise for thread.
+	(steal_delay_list_from_target): Check JUMP_LABELs for returns.
+	Use simplejump_or_return_p.
+	(fill_simple_delay_slots): Likewise.
+	(optimize_skip): Likewise.
+	(fill_slots_from_thread): Likewise.
+	(relax_delay_slots): Likewise.
+	(dbr_schedule): Adjust handling of end_of_function_label for the
+	two new variables.
+	* ifcvt.c (find_if_case_1): Take care when redirecting jumps to the
+	exit block.
+	(dead_or_predicable): Change NEW_DEST arg to DEST_EDGE.  All callers
+	changed.  Ensure that the right label is passed to redirect_jump.
+	* jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p,
+	returnjump_p): Handle SIMPLE_RETURNs.
+	(delete_related_insns): Check JUMP_LABEL for returns.
+	(redirect_target): New static function.
+	(redirect_exp_1): Use it.  Handle any kind of return rtx as a label
+	rather than interpreting NULL as a return.
+	(redirect_jump_1): Assert that nlabel is not NULL.
+	(redirect_jump): Likewise.
+	(redirect_jump_2): Handle any kind of return rtx as a label rather
+	than interpreting NULL as a return.
+	* dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for
+	returns.
+	* function.c (emit_return_into_block): Remove useless declaration.
+	(record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern,
+	requires_stack_frame_p): New static functions.
+	(emit_return_into_block): New arg SIMPLE_P.  All callers changed.
+	Generate either kind of return pattern and update the JUMP_LABEL.
+	(thread_prologue_and_epilogue_insns): Implement a form of
+	shrink-wrapping.  Ensure JUMP_LABELs for return insns are set.
+	* print-rtl.c (print_rtx): Handle returns in JUMP_LABELs.
+	* cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns
+	remain correct.
+	* resource.c (find_dead_or_set_registers): Check JUMP_LABELs for
+	returns.
+	(mark_target_live_regs): Don't pass a return rtx to next_active_insn.
+	* basic-block.h (force_nonfallthru_and_redirect): Declare.
+	* sched-vis.c (print_pattern): Add case for SIMPLE_RETURN.
+	* cfgrtl.c (force_nonfallthru_and_redirect): No longer static.  New arg
+	JUMP_LABEL.  All callers changed.  Use the label when generating
+	return insns.
+
+	* config/i386/i386.md (returns, return_str, return_cond): New
+	code_iterator and corresponding code_attrs.
+	(<return_str>return): Renamed from return and adapted.
+	(<return_str>return_internal): Likewise for return_internal.
+	(<return_str>return_internal_long): Likewise for return_internal_long.
+	(<return_str>return_pop_internal): Likewise for return_pop_internal.
+	(<return_str>return_indirect_internal): Likewise for
+	return_indirect_internal.
+	* config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as
+	the last insn.
+	(ix86_pad_returns): Handle both kinds of return rtx.
+	* config/arm/arm.c (use_simple_return_p): new function.
+	(is_jump_table): Handle returns in JUMP_LABELs.
+	(output_return_instruction): New arg SIMPLE.  All callers changed.
+	Use it to determine which kind of return to generate.
+	(arm_final_prescan_insn): Handle both kinds of return.
+	* config/arm/arm.md (returns, return_str, return_simple_p,
+	return_cond): New code_iterator and corresponding code_attrs.
+	(<return_str>return): Renamed from return and adapted.
+	(arm_<return_str>return): Renamed from arm_return and adapted.
+	(cond_<return_str>return): Renamed from cond_return and adapted.
+	(cond_<return_str>return_inverted): Renamed from cond_return_inverted
+	and adapted.
+	(epilogue): Use ret_rtx instead of gen_rtx_RETURN.
+	* config/arm/thumb2.md (thumb2_<return_str>return): Renamed from
+	thumb2_return and adapted.
+	* config/arm/arm.h (RETURN_ADDR_REGNUM): Define.
+	* config/arm/arm-protos.h (use_simple_return_p): Declare.
+	(output_return_instruction): Adjust declaration.
+	* config/mips/mips.c (mips_expand_epilogue): Generate a simple_return
+	as final insn.
+	* config/mips/mips.md (simple_return): New expander.
+	(*simple_return, simple_return_internal): New patterns.
+	* config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL.
+	(split_branches): Don't pass a null label to redirect_jump.
+
+	From mainline:
+	* vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros.
+	* haifa-sched.c (find_fallthru_edge_from): Rename from
+	find_fallthru_edge.  All callers changed.
+	* sched-int.h (find_fallthru_edge_from): Rename declaration as well.
+	* basic-block.h (find_fallthru_edge): New inline function.
+
+=== modified file 'gcc/basic-block.h'
+Index: gcc-4_5-branch/gcc/basic-block.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/basic-block.h
++++ gcc-4_5-branch/gcc/basic-block.h
+@@ -884,6 +884,7 @@ extern void flow_edge_list_print (const 
+ 
+ /* In cfgrtl.c  */
+ extern basic_block force_nonfallthru (edge);
++extern basic_block force_nonfallthru_and_redirect (edge, basic_block, rtx);
+ extern rtx block_label (basic_block);
+ extern bool purge_all_dead_edges (void);
+ extern bool purge_dead_edges (basic_block);
+@@ -1004,6 +1005,20 @@ bb_has_abnormal_pred (basic_block bb)
+   return false;
+ }
+ 
++/* Return the fallthru edge in EDGES if it exists, NULL otherwise.  */
++static inline edge
++find_fallthru_edge (VEC(edge,gc) *edges)
++{
++  edge e;
++  edge_iterator ei;
++
++  FOR_EACH_EDGE (e, ei, edges)
++    if (e->flags & EDGE_FALLTHRU)
++      break;
++
++  return e;
++}
++
+ /* In cfgloopmanip.c.  */
+ extern edge mfb_kj_edge;
+ extern bool mfb_keep_just (edge);
+Index: gcc-4_5-branch/gcc/cfganal.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/cfganal.c
++++ gcc-4_5-branch/gcc/cfganal.c
+@@ -271,6 +271,37 @@ set_edge_can_fallthru_flag (void)
+       EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU;
+       EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU;
+     }
++  /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired
++     with a return or a sibcall.  Ensure that this remains the case if
++     they are in different basic blocks.  */
++  FOR_EACH_BB (bb)
++    {
++      edge e;
++      edge_iterator ei;
++      rtx insn, end;
++
++      end = BB_END (bb);
++      FOR_BB_INSNS (bb, insn)
++	if (GET_CODE (insn) == NOTE
++	    && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG
++	    && !(CALL_P (end) && SIBLING_CALL_P (end))
++	    && !returnjump_p (end))
++	  {
++	    basic_block other_bb = NULL;
++	    FOR_EACH_EDGE (e, ei, bb->succs)
++	      {
++		if (e->flags & EDGE_FALLTHRU)
++		  other_bb = e->dest;
++		else
++		  e->flags &= ~EDGE_CAN_FALLTHRU;
++	      }
++	    FOR_EACH_EDGE (e, ei, other_bb->preds)
++	      {
++		if (!(e->flags & EDGE_FALLTHRU))
++		  e->flags &= ~EDGE_CAN_FALLTHRU;
++	      }	    
++	  }
++    }
+ }
+ 
+ /* Find unreachable blocks.  An unreachable block will have 0 in
+Index: gcc-4_5-branch/gcc/cfglayout.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/cfglayout.c
++++ gcc-4_5-branch/gcc/cfglayout.c
+@@ -766,6 +766,7 @@ fixup_reorder_chain (void)
+     {
+       edge e_fall, e_taken, e;
+       rtx bb_end_insn;
++      rtx ret_label = NULL_RTX;
+       basic_block nb;
+       edge_iterator ei;
+ 
+@@ -785,6 +786,7 @@ fixup_reorder_chain (void)
+       bb_end_insn = BB_END (bb);
+       if (JUMP_P (bb_end_insn))
+ 	{
++	  ret_label = JUMP_LABEL (bb_end_insn);
+ 	  if (any_condjump_p (bb_end_insn))
+ 	    {
+ 	      /* This might happen if the conditional jump has side
+@@ -899,7 +901,7 @@ fixup_reorder_chain (void)
+ 	}
+ 
+       /* We got here if we need to add a new jump insn.  */
+-      nb = force_nonfallthru (e_fall);
++      nb = force_nonfallthru_and_redirect (e_fall, e_fall->dest, ret_label);
+       if (nb)
+ 	{
+ 	  nb->il.rtl->visited = 1;
+@@ -1118,24 +1120,30 @@ extern bool cfg_layout_can_duplicate_bb_
+ bool
+ cfg_layout_can_duplicate_bb_p (const_basic_block bb)
+ {
++  rtx insn;
++
+   /* Do not attempt to duplicate tablejumps, as we need to unshare
+      the dispatch table.  This is difficult to do, as the instructions
+      computing jump destination may be hoisted outside the basic block.  */
+   if (tablejump_p (BB_END (bb), NULL, NULL))
+     return false;
+ 
+-  /* Do not duplicate blocks containing insns that can't be copied.  */
+-  if (targetm.cannot_copy_insn_p)
++  insn = BB_HEAD (bb);
++  while (1)
+     {
+-      rtx insn = BB_HEAD (bb);
+-      while (1)
+-	{
+-	  if (INSN_P (insn) && targetm.cannot_copy_insn_p (insn))
+-	    return false;
+-	  if (insn == BB_END (bb))
+-	    break;
+-	  insn = NEXT_INSN (insn);
+-	}
++      /* Do not duplicate blocks containing insns that can't be copied.  */
++      if (INSN_P (insn) && targetm.cannot_copy_insn_p
++	  && targetm.cannot_copy_insn_p (insn))
++	return false;
++      /* dwarf2out expects that these notes are always paired with a
++	 returnjump or sibling call.  */
++      if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG
++	  && !returnjump_p (BB_END (bb))
++	  && (!CALL_P (BB_END (bb)) || !SIBLING_CALL_P (BB_END (bb))))
++	return false;
++      if (insn == BB_END (bb))
++	break;
++      insn = NEXT_INSN (insn);
+     }
+ 
+   return true;
+@@ -1180,6 +1188,9 @@ duplicate_insn_chain (rtx from, rtx to)
+ 	      break;
+ 	    }
+ 	  copy = emit_copy_of_insn_after (insn, get_last_insn ());
++	  if (JUMP_P (insn) && JUMP_LABEL (insn) != NULL_RTX
++	      && ANY_RETURN_P (JUMP_LABEL (insn)))
++	    JUMP_LABEL (copy) = JUMP_LABEL (insn);
+           maybe_copy_epilogue_insn (insn, copy);
+ 	  break;
+ 
+Index: gcc-4_5-branch/gcc/cfgrtl.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/cfgrtl.c
++++ gcc-4_5-branch/gcc/cfgrtl.c
+@@ -1107,10 +1107,13 @@ rtl_redirect_edge_and_branch (edge e, ba
+ }
+ 
+ /* Like force_nonfallthru below, but additionally performs redirection
+-   Used by redirect_edge_and_branch_force.  */
++   Used by redirect_edge_and_branch_force.  JUMP_LABEL is used only
++   when redirecting to the EXIT_BLOCK, it is either a return or a
++   simple_return rtx indicating which kind of returnjump to create.
++   It should be NULL otherwise.  */
+ 
+-static basic_block
+-force_nonfallthru_and_redirect (edge e, basic_block target)
++basic_block
++force_nonfallthru_and_redirect (edge e, basic_block target, rtx jump_label)
+ {
+   basic_block jump_block, new_bb = NULL, src = e->src;
+   rtx note;
+@@ -1242,11 +1245,25 @@ force_nonfallthru_and_redirect (edge e, 
+   e->flags &= ~EDGE_FALLTHRU;
+   if (target == EXIT_BLOCK_PTR)
+     {
++      if (jump_label == ret_rtx)
++	{
+ #ifdef HAVE_return
+-	emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), loc);
++	  emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block),
++				       loc);
+ #else
+-	gcc_unreachable ();
++	  gcc_unreachable ();
+ #endif
++	}
++      else
++	{
++	  gcc_assert (jump_label == simple_return_rtx);
++#ifdef HAVE_simple_return
++	  emit_jump_insn_after_setloc (gen_simple_return (),
++				       BB_END (jump_block), loc);
++#else
++	  gcc_unreachable ();
++#endif
++	}
+     }
+   else
+     {
+@@ -1273,7 +1290,7 @@ force_nonfallthru_and_redirect (edge e, 
+ basic_block
+ force_nonfallthru (edge e)
+ {
+-  return force_nonfallthru_and_redirect (e, e->dest);
++  return force_nonfallthru_and_redirect (e, e->dest, NULL_RTX);
+ }
+ 
+ /* Redirect edge even at the expense of creating new jump insn or
+@@ -1290,7 +1307,7 @@ rtl_redirect_edge_and_branch_force (edge
+   /* In case the edge redirection failed, try to force it to be non-fallthru
+      and redirect newly created simplejump.  */
+   df_set_bb_dirty (e->src);
+-  return force_nonfallthru_and_redirect (e, target);
++  return force_nonfallthru_and_redirect (e, target, NULL_RTX);
+ }
+ 
+ /* The given edge should potentially be a fallthru edge.  If that is in
+Index: gcc-4_5-branch/gcc/common.opt
+===================================================================
+--- gcc-4_5-branch.orig/gcc/common.opt
++++ gcc-4_5-branch/gcc/common.opt
+@@ -1147,6 +1147,11 @@ fshow-column
+ Common C ObjC C++ ObjC++ Report Var(flag_show_column) Init(1)
+ Show column numbers in diagnostics, when available.  Default on
+ 
++fshrink-wrap
++Common Report Var(flag_shrink_wrap) Optimization
++Emit function prologues only before parts of the function that need it,
++rather than at the top of the function.
++
+ fsignaling-nans
+ Common Report Var(flag_signaling_nans) Optimization
+ Disable optimizations observable by IEEE signaling NaNs
+Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h
++++ gcc-4_5-branch/gcc/config/arm/arm-protos.h
+@@ -26,6 +26,7 @@
+ extern void arm_override_options (void);
+ extern void arm_optimization_options (int, int);
+ extern int use_return_insn (int, rtx);
++extern bool use_simple_return_p (void);
+ extern enum reg_class arm_regno_class (int);
+ extern void arm_load_pic_register (unsigned long);
+ extern int arm_volatile_func (void);
+@@ -137,7 +138,7 @@ extern int arm_address_offset_is_imm (rt
+ extern const char *output_add_immediate (rtx *);
+ extern const char *arithmetic_instr (rtx, int);
+ extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
+-extern const char *output_return_instruction (rtx, int, int);
++extern const char *output_return_instruction (rtx, bool, bool, bool);
+ extern void arm_poke_function_name (FILE *, const char *);
+ extern void arm_print_operand (FILE *, rtx, int);
+ extern void arm_print_operand_address (FILE *, rtx);
+Index: gcc-4_5-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.c
++++ gcc-4_5-branch/gcc/config/arm/arm.c
+@@ -2163,6 +2163,18 @@ arm_trampoline_adjust_address (rtx addr)
+   return addr;
+ }
+ 
++/* Return true if we should try to use a simple_return insn, i.e. perform
++   shrink-wrapping if possible.  This is the case if we need to emit a
++   prologue, which we can test by looking at the offsets.  */
++bool
++use_simple_return_p (void)
++{
++  arm_stack_offsets *offsets;
++
++  offsets = arm_get_frame_offsets ();
++  return offsets->outgoing_args != 0;
++}
++
+ /* Return 1 if it is possible to return using a single instruction.
+    If SIBLING is non-null, this is a test for a return before a sibling
+    call.  SIBLING is the call insn, so we can examine its register usage.  */
+@@ -11284,6 +11296,7 @@ is_jump_table (rtx insn)
+ 
+   if (GET_CODE (insn) == JUMP_INSN
+       && JUMP_LABEL (insn) != NULL
++      && !ANY_RETURN_P (JUMP_LABEL (insn))
+       && ((table = next_real_insn (JUMP_LABEL (insn)))
+ 	  == next_real_insn (insn))
+       && table != NULL
+@@ -14168,7 +14181,7 @@ arm_get_vfp_saved_size (void)
+ /* Generate a function exit sequence.  If REALLY_RETURN is false, then do
+    everything bar the final return instruction.  */
+ const char *
+-output_return_instruction (rtx operand, int really_return, int reverse)
++output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple)
+ {
+   char conditional[10];
+   char instr[100];
+@@ -14206,10 +14219,15 @@ output_return_instruction (rtx operand, 
+ 
+   sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
+ 
+-  cfun->machine->return_used_this_function = 1;
++  if (simple)
++    live_regs_mask = 0;
++  else
++    {
++      cfun->machine->return_used_this_function = 1;
+ 
+-  offsets = arm_get_frame_offsets ();
+-  live_regs_mask = offsets->saved_regs_mask;
++      offsets = arm_get_frame_offsets ();
++      live_regs_mask = offsets->saved_regs_mask;
++    }
+ 
+   if (live_regs_mask)
+     {
+@@ -17108,6 +17126,7 @@ arm_final_prescan_insn (rtx insn)
+ 
+   /* If we start with a return insn, we only succeed if we find another one.  */
+   int seeking_return = 0;
++  enum rtx_code return_code = UNKNOWN;
+ 
+   /* START_INSN will hold the insn from where we start looking.  This is the
+      first insn after the following code_label if REVERSE is true.  */
+@@ -17146,7 +17165,7 @@ arm_final_prescan_insn (rtx insn)
+ 	  else
+ 	    return;
+ 	}
+-      else if (GET_CODE (body) == RETURN)
++      else if (ANY_RETURN_P (body))
+         {
+ 	  start_insn = next_nonnote_insn (start_insn);
+ 	  if (GET_CODE (start_insn) == BARRIER)
+@@ -17157,6 +17176,7 @@ arm_final_prescan_insn (rtx insn)
+ 	    {
+ 	      reverse = TRUE;
+ 	      seeking_return = 1;
++	      return_code = GET_CODE (body);
+ 	    }
+ 	  else
+ 	    return;
+@@ -17197,11 +17217,15 @@ arm_final_prescan_insn (rtx insn)
+ 	  label = XEXP (XEXP (SET_SRC (body), 2), 0);
+ 	  then_not_else = FALSE;
+ 	}
+-      else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
+-	seeking_return = 1;
+-      else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
++      else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1)))
++	{
++	  seeking_return = 1;
++	  return_code = GET_CODE (XEXP (SET_SRC (body), 1));
++	}
++      else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2)))
+         {
+ 	  seeking_return = 1;
++	  return_code = GET_CODE (XEXP (SET_SRC (body), 2));
+ 	  then_not_else = FALSE;
+         }
+       else
+@@ -17302,8 +17326,7 @@ arm_final_prescan_insn (rtx insn)
+ 		       && !use_return_insn (TRUE, NULL)
+ 		       && !optimize_size)
+ 		fail = TRUE;
+-	      else if (GET_CODE (scanbody) == RETURN
+-		       && seeking_return)
++	      else if (GET_CODE (scanbody) == return_code)
+ 	        {
+ 		  arm_ccfsm_state = 2;
+ 		  succeed = TRUE;
+Index: gcc-4_5-branch/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.h
++++ gcc-4_5-branch/gcc/config/arm/arm.h
+@@ -2622,6 +2622,8 @@ extern int making_const_table;
+ #define RETURN_ADDR_RTX(COUNT, FRAME) \
+   arm_return_addr (COUNT, FRAME)
+ 
++#define RETURN_ADDR_REGNUM LR_REGNUM
++
+ /* Mask of the bits in the PC that contain the real return address
+    when running in 26-bit mode.  */
+ #define RETURN_ADDR_MASK26 (0x03fffffc)
+Index: gcc-4_5-branch/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.md
++++ gcc-4_5-branch/gcc/config/arm/arm.md
+@@ -8882,66 +8882,72 @@
+   [(set_attr "type" "call")]
+ )
+ 
+-(define_expand "return"
+-  [(return)]
+-  "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
++;; Both kinds of return insn.
++(define_code_iterator returns [return simple_return])
++(define_code_attr return_str [(return "") (simple_return "simple_")])
++(define_code_attr return_simple_p [(return "false") (simple_return "true")])
++(define_code_attr return_cond [(return " && USE_RETURN_INSN (FALSE)")
++			       (simple_return " && use_simple_return_p ()")])
++
++(define_expand "<return_str>return"
++  [(returns)]
++  "TARGET_32BIT<return_cond>"
+   "")
+ 
+-;; Often the return insn will be the same as loading from memory, so set attr
+-(define_insn "*arm_return"
+-  [(return)]
+-  "TARGET_ARM && USE_RETURN_INSN (FALSE)"
+-  "*
+-  {
+-    if (arm_ccfsm_state == 2)
+-      {
+-        arm_ccfsm_state += 2;
+-        return \"\";
+-      }
+-    return output_return_instruction (const_true_rtx, TRUE, FALSE);
+-  }"
++(define_insn "*arm_<return_str>return"
++  [(returns)]
++  "TARGET_ARM<return_cond>"
++{
++  if (arm_ccfsm_state == 2)
++    {
++      arm_ccfsm_state += 2;
++      return "";
++    }
++  return output_return_instruction (const_true_rtx, true, false,
++				    <return_simple_p>);
++}
+   [(set_attr "type" "load1")
+    (set_attr "length" "12")
+    (set_attr "predicable" "yes")]
+ )
+ 
+-(define_insn "*cond_return"
++(define_insn "*cond_<return_str>return"
+   [(set (pc)
+         (if_then_else (match_operator 0 "arm_comparison_operator"
+ 		       [(match_operand 1 "cc_register" "") (const_int 0)])
+-                      (return)
++                      (returns)
+                       (pc)))]
+-  "TARGET_ARM && USE_RETURN_INSN (TRUE)"
+-  "*
+-  {
+-    if (arm_ccfsm_state == 2)
+-      {
+-        arm_ccfsm_state += 2;
+-        return \"\";
+-      }
+-    return output_return_instruction (operands[0], TRUE, FALSE);
+-  }"
++  "TARGET_ARM<return_cond>"
++{
++  if (arm_ccfsm_state == 2)
++    {
++      arm_ccfsm_state += 2;
++      return "";
++    }
++  return output_return_instruction (operands[0], true, false,
++				    <return_simple_p>);
++}
+   [(set_attr "conds" "use")
+    (set_attr "length" "12")
+    (set_attr "type" "load1")]
+ )
+ 
+-(define_insn "*cond_return_inverted"
++(define_insn "*cond_<return_str>return_inverted"
+   [(set (pc)
+         (if_then_else (match_operator 0 "arm_comparison_operator"
+ 		       [(match_operand 1 "cc_register" "") (const_int 0)])
+                       (pc)
+-		      (return)))]
+-  "TARGET_ARM && USE_RETURN_INSN (TRUE)"
+-  "*
+-  {
+-    if (arm_ccfsm_state == 2)
+-      {
+-        arm_ccfsm_state += 2;
+-        return \"\";
+-      }
+-    return output_return_instruction (operands[0], TRUE, TRUE);
+-  }"
++		      (returns)))]
++  "TARGET_ARM<return_cond>"
++{
++  if (arm_ccfsm_state == 2)
++    {
++      arm_ccfsm_state += 2;
++      return "";
++    }
++  return output_return_instruction (operands[0], true, true,
++				    <return_simple_p>);
++}
+   [(set_attr "conds" "use")
+    (set_attr "length" "12")
+    (set_attr "type" "load1")]
+@@ -10809,8 +10815,7 @@
+       DONE;
+     }
+   emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
+-	gen_rtvec (1,
+-		gen_rtx_RETURN (VOIDmode)),
++	gen_rtvec (1, ret_rtx),
+ 	VUNSPEC_EPILOGUE));
+   DONE;
+   "
+@@ -10827,7 +10832,7 @@
+   "TARGET_32BIT"
+   "*
+   if (use_return_insn (FALSE, next_nonnote_insn (insn)))
+-    return output_return_instruction (const_true_rtx, FALSE, FALSE);
++    return output_return_instruction (const_true_rtx, false, false, false);
+   return arm_output_epilogue (next_nonnote_insn (insn));
+   "
+ ;; Length is absolute worst case
+Index: gcc-4_5-branch/gcc/config/arm/thumb2.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/thumb2.md
++++ gcc-4_5-branch/gcc/config/arm/thumb2.md
+@@ -1020,16 +1020,15 @@
+ 
+ ;; Note: this is not predicable, to avoid issues with linker-generated
+ ;; interworking stubs.
+-(define_insn "*thumb2_return"
+-  [(return)]
+-  "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
+-  "*
+-  {
+-    return output_return_instruction (const_true_rtx, TRUE, FALSE);
+-  }"
++(define_insn "*thumb2_<return_str>return"
++  [(returns)]
++  "TARGET_THUMB2<return_cond>"
++{
++  return output_return_instruction (const_true_rtx, true, false,
++				    <return_simple_p>);
++}
+   [(set_attr "type" "load1")
+-   (set_attr "length" "12")]
+-)
++   (set_attr "length" "12")])
+ 
+ (define_insn_and_split "thumb2_eh_return"
+   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
+Index: gcc-4_5-branch/gcc/config/bfin/bfin.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/bfin/bfin.c
++++ gcc-4_5-branch/gcc/config/bfin/bfin.c
+@@ -2359,7 +2359,7 @@ bfin_expand_call (rtx retval, rtx fnaddr
+     XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg);
+   XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie);
+   if (sibcall)
+-    XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode);
++    XVECEXP (pat, 0, n++) = ret_rtx;
+   else
+     XVECEXP (pat, 0, n++) = gen_rtx_CLOBBER (VOIDmode, retsreg);
+   call = emit_call_insn (pat);
+Index: gcc-4_5-branch/gcc/config/cris/cris.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/cris/cris.c
++++ gcc-4_5-branch/gcc/config/cris/cris.c
+@@ -1771,7 +1771,7 @@ cris_expand_return (bool on_stack)
+      we do that until they're fixed.  Currently, all return insns in a
+      function must be the same (not really a limiting factor) so we need
+      to check that it doesn't change half-way through.  */
+-  emit_jump_insn (gen_rtx_RETURN (VOIDmode));
++  emit_jump_insn (ret_rtx);
+ 
+   CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
+   CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
+Index: gcc-4_5-branch/gcc/config/h8300/h8300.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/h8300/h8300.c
++++ gcc-4_5-branch/gcc/config/h8300/h8300.c
+@@ -691,7 +691,7 @@ h8300_push_pop (int regno, int nregs, bo
+   /* Add the return instruction.  */
+   if (return_p)
+     {
+-      RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
++      RTVEC_ELT (vec, i) = ret_rtx;
+       i++;
+     }
+ 
+@@ -975,7 +975,7 @@ h8300_expand_epilogue (void)
+     }
+ 
+   if (!returned_p)
+-    emit_jump_insn (gen_rtx_RETURN (VOIDmode));
++    emit_jump_insn (ret_rtx);
+ }
+ 
+ /* Return nonzero if the current function is an interrupt
+Index: gcc-4_5-branch/gcc/config/i386/i386.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/i386/i386.c
++++ gcc-4_5-branch/gcc/config/i386/i386.c
+@@ -9308,13 +9308,13 @@ ix86_expand_epilogue (int style)
+ 
+ 	  pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
+ 				     popc, -1, true);
+-	  emit_jump_insn (gen_return_indirect_internal (ecx));
++	  emit_jump_insn (gen_simple_return_indirect_internal (ecx));
+ 	}
+       else
+-	emit_jump_insn (gen_return_pop_internal (popc));
++	emit_jump_insn (gen_simple_return_pop_internal (popc));
+     }
+   else
+-    emit_jump_insn (gen_return_internal ());
++    emit_jump_insn (gen_simple_return_internal ());
+ 
+   /* Restore the state back to the state from the prologue,
+      so that it's correct for the next epilogue.  */
+@@ -26615,7 +26615,7 @@ ix86_pad_returns (void)
+       rtx prev;
+       bool replace = false;
+ 
+-      if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
++      if (!JUMP_P (ret) || !ANY_RETURN_P (PATTERN (ret))
+ 	  || optimize_bb_for_size_p (bb))
+ 	continue;
+       for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
+@@ -26645,7 +26645,10 @@ ix86_pad_returns (void)
+ 	}
+       if (replace)
+ 	{
+-	  emit_jump_insn_before (gen_return_internal_long (), ret);
++	  if (PATTERN (ret) == ret_rtx)
++	    emit_jump_insn_before (gen_return_internal_long (), ret);
++	  else
++	    emit_jump_insn_before (gen_simple_return_internal_long (), ret);
+ 	  delete_insn (ret);
+ 	}
+     }
+Index: gcc-4_5-branch/gcc/config/i386/i386.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/i386/i386.md
++++ gcc-4_5-branch/gcc/config/i386/i386.md
+@@ -13798,24 +13798,29 @@
+   ""
+   [(set_attr "length" "0")])
+ 
++(define_code_iterator returns [return simple_return])
++(define_code_attr return_str [(return "") (simple_return "simple_")])
++(define_code_attr return_cond [(return "ix86_can_use_return_insn_p ()")
++			       (simple_return "")])
++
+ ;; Insn emitted into the body of a function to return from a function.
+ ;; This is only done if the function's epilogue is known to be simple.
+ ;; See comments for ix86_can_use_return_insn_p in i386.c.
+ 
+-(define_expand "return"
+-  [(return)]
+-  "ix86_can_use_return_insn_p ()"
++(define_expand "<return_str>return"
++  [(returns)]
++  "<return_cond>"
+ {
+   if (crtl->args.pops_args)
+     {
+       rtx popc = GEN_INT (crtl->args.pops_args);
+-      emit_jump_insn (gen_return_pop_internal (popc));
++      emit_jump_insn (gen_<return_str>return_pop_internal (popc));
+       DONE;
+     }
+ })
+ 
+-(define_insn "return_internal"
+-  [(return)]
++(define_insn "<return_str>return_internal"
++  [(returns)]
+   "reload_completed"
+   "ret"
+   [(set_attr "length" "1")
+@@ -13826,8 +13831,8 @@
+ ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
+ ;; instruction Athlon and K8 have.
+ 
+-(define_insn "return_internal_long"
+-  [(return)
++(define_insn "<return_str>return_internal_long"
++  [(returns)
+    (unspec [(const_int 0)] UNSPEC_REP)]
+   "reload_completed"
+   "rep\;ret"
+@@ -13837,8 +13842,8 @@
+    (set_attr "prefix_rep" "1")
+    (set_attr "modrm" "0")])
+ 
+-(define_insn "return_pop_internal"
+-  [(return)
++(define_insn "<return_str>return_pop_internal"
++  [(returns)
+    (use (match_operand:SI 0 "const_int_operand" ""))]
+   "reload_completed"
+   "ret\t%0"
+@@ -13847,8 +13852,8 @@
+    (set_attr "length_immediate" "2")
+    (set_attr "modrm" "0")])
+ 
+-(define_insn "return_indirect_internal"
+-  [(return)
++(define_insn "<return_str>return_indirect_internal"
++  [(returns)
+    (use (match_operand:SI 0 "register_operand" "r"))]
+   "reload_completed"
+   "jmp\t%A0"
+Index: gcc-4_5-branch/gcc/config/m68hc11/m68hc11.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/m68hc11/m68hc11.md
++++ gcc-4_5-branch/gcc/config/m68hc11/m68hc11.md
+@@ -6576,7 +6576,7 @@
+   if (ret_size && ret_size <= 2)
+     {
+       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode,
+-		      gen_rtvec (2, gen_rtx_RETURN (VOIDmode),
++		      gen_rtvec (2, ret_rtx,
+ 			         gen_rtx_USE (VOIDmode,
+ 					      gen_rtx_REG (HImode, 1)))));
+       DONE;
+@@ -6584,7 +6584,7 @@
+   if (ret_size)
+     {
+       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode,
+-		      gen_rtvec (2, gen_rtx_RETURN (VOIDmode),
++		      gen_rtvec (2, ret_rtx,
+ 			         gen_rtx_USE (VOIDmode,
+ 					      gen_rtx_REG (SImode, 0)))));
+       DONE;
+Index: gcc-4_5-branch/gcc/config/m68k/m68k.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/m68k/m68k.c
++++ gcc-4_5-branch/gcc/config/m68k/m68k.c
+@@ -1366,7 +1366,7 @@ m68k_expand_epilogue (bool sibcall_p)
+ 			   EH_RETURN_STACKADJ_RTX));
+ 
+   if (!sibcall_p)
+-    emit_jump_insn (gen_rtx_RETURN (VOIDmode));
++    emit_jump_insn (ret_rtx);
+ }
+ 
+ /* Return true if X is a valid comparison operator for the dbcc 
+Index: gcc-4_5-branch/gcc/config/mips/mips.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/mips/mips.c
++++ gcc-4_5-branch/gcc/config/mips/mips.c
+@@ -10497,7 +10497,8 @@ mips_expand_epilogue (bool sibcall_p)
+ 	    regno = GP_REG_FIRST + 7;
+ 	  else
+ 	    regno = RETURN_ADDR_REGNUM;
+-	  emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
++	  emit_jump_insn (gen_simple_return_internal (gen_rtx_REG (Pmode,
++								   regno)));
+ 	}
+     }
+ 
+Index: gcc-4_5-branch/gcc/config/mips/mips.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/mips/mips.md
++++ gcc-4_5-branch/gcc/config/mips/mips.md
+@@ -5815,6 +5815,18 @@
+   [(set_attr "type"	"jump")
+    (set_attr "mode"	"none")])
+ 
++(define_expand "simple_return"
++  [(simple_return)]
++  "!mips_can_use_return_insn ()"
++  { mips_expand_before_return (); })
++
++(define_insn "*simple_return"
++  [(simple_return)]
++  "!mips_can_use_return_insn ()"
++  "%*j\t$31%/"
++  [(set_attr "type"	"jump")
++   (set_attr "mode"	"none")])
++
+ ;; Normal return.
+ 
+ (define_insn "return_internal"
+@@ -5825,6 +5837,14 @@
+   [(set_attr "type"	"jump")
+    (set_attr "mode"	"none")])
+ 
++(define_insn "simple_return_internal"
++  [(simple_return)
++   (use (match_operand 0 "pmode_register_operand" ""))]
++  ""
++  "%*j\t%0%/"
++  [(set_attr "type"	"jump")
++   (set_attr "mode"	"none")])
++
+ ;; Exception return.
+ (define_insn "mips_eret"
+   [(return)
+Index: gcc-4_5-branch/gcc/config/picochip/picochip.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/picochip/picochip.c
++++ gcc-4_5-branch/gcc/config/picochip/picochip.c
+@@ -1996,7 +1996,7 @@ picochip_expand_epilogue (int is_sibling
+     rtvec p;
+     p = rtvec_alloc (2);
+ 
+-    RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
++    RTVEC_ELT (p, 0) = ret_rtx;
+     RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
+ 				    gen_rtx_REG (Pmode, LINK_REGNUM));
+     emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
+Index: gcc-4_5-branch/gcc/config/rs6000/rs6000.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/rs6000.c
++++ gcc-4_5-branch/gcc/config/rs6000/rs6000.c
+@@ -18563,7 +18563,7 @@ rs6000_make_savres_rtx (rs6000_stack_t *
+   p = rtvec_alloc ((lr ? 4 : 3) + n_regs);
+ 
+   if (!savep && lr)
+-    RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode);
++    RTVEC_ELT (p, offset++) = ret_rtx;
+ 
+   RTVEC_ELT (p, offset++)
+     = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65));
+@@ -19638,7 +19638,7 @@ rs6000_emit_epilogue (int sibcall)
+       alloc_rname = ggc_strdup (rname);
+ 
+       j = 0;
+-      RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
++      RTVEC_ELT (p, j++) = ret_rtx;
+       RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
+ 					gen_rtx_REG (Pmode,
+ 						     LR_REGNO));
+@@ -20254,7 +20254,7 @@ rs6000_emit_epilogue (int sibcall)
+       else
+ 	p = rtvec_alloc (2);
+ 
+-      RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
++      RTVEC_ELT (p, 0) = ret_rtx;
+       RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
+ 			  ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
+ 			  : gen_rtx_CLOBBER (VOIDmode,
+@@ -20695,7 +20695,7 @@ rs6000_output_mi_thunk (FILE *file, tree
+ 			gen_rtx_USE (VOIDmode,
+ 				     gen_rtx_REG (SImode,
+ 						  LR_REGNO)),
+-			gen_rtx_RETURN (VOIDmode))));
++			ret_rtx)));
+   SIBLING_CALL_P (insn) = 1;
+   emit_barrier ();
+ 
+Index: gcc-4_5-branch/gcc/config/rx/rx.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rx/rx.c
++++ gcc-4_5-branch/gcc/config/rx/rx.c
+@@ -1562,7 +1562,7 @@ gen_rx_rtsd_vector (unsigned int adjust,
+ 				: plus_constant (stack_pointer_rtx,
+ 						 i * UNITS_PER_WORD)));
+ 
+-  XVECEXP (vector, 0, count - 1) = gen_rtx_RETURN (VOIDmode);
++  XVECEXP (vector, 0, count - 1) = ret_rtx;
+ 
+   return vector;
+ }
+Index: gcc-4_5-branch/gcc/config/s390/s390.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/s390/s390.c
++++ gcc-4_5-branch/gcc/config/s390/s390.c
+@@ -8170,7 +8170,7 @@ s390_emit_epilogue (bool sibcall)
+ 
+       p = rtvec_alloc (2);
+ 
+-      RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
++      RTVEC_ELT (p, 0) = ret_rtx;
+       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
+       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
+     }
+Index: gcc-4_5-branch/gcc/config/sh/sh.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/sh/sh.c
++++ gcc-4_5-branch/gcc/config/sh/sh.c
+@@ -5252,7 +5252,8 @@ barrier_align (rtx barrier_or_label)
+ 	}
+       if (prev
+ 	  && JUMP_P (prev)
+-	  && JUMP_LABEL (prev))
++	  && JUMP_LABEL (prev)
++	  && !ANY_RETURN_P (JUMP_LABEL (prev)))
+ 	{
+ 	  rtx x;
+ 	  if (jump_to_next
+@@ -5951,7 +5952,7 @@ split_branches (rtx first)
+ 			JUMP_LABEL (insn) = far_label;
+ 			LABEL_NUSES (far_label)++;
+ 		      }
+-		    redirect_jump (insn, NULL_RTX, 1);
++		    redirect_jump (insn, ret_rtx, 1);
+ 		    far_label = 0;
+ 		  }
+ 	      }
+Index: gcc-4_5-branch/gcc/config/v850/v850.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/v850/v850.c
++++ gcc-4_5-branch/gcc/config/v850/v850.c
+@@ -1832,7 +1832,7 @@ expand_epilogue (void)
+ 	{
+ 	  restore_all = gen_rtx_PARALLEL (VOIDmode,
+ 					  rtvec_alloc (num_restore + 2));
+-	  XVECEXP (restore_all, 0, 0) = gen_rtx_RETURN (VOIDmode);
++	  XVECEXP (restore_all, 0, 0) = ret_rtx;
+ 	  XVECEXP (restore_all, 0, 1)
+ 	    = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
+ 			    gen_rtx_PLUS (Pmode,
+Index: gcc-4_5-branch/gcc/df-scan.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/df-scan.c
++++ gcc-4_5-branch/gcc/df-scan.c
+@@ -3296,6 +3296,7 @@ df_uses_record (enum df_ref_class cl, st
+       }
+ 
+     case RETURN:
++    case SIMPLE_RETURN:
+       break;
+ 
+     case ASM_OPERANDS:
+Index: gcc-4_5-branch/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/invoke.texi
++++ gcc-4_5-branch/gcc/doc/invoke.texi
+@@ -5751,6 +5751,7 @@ compilation time.
+ -fipa-pure-const @gol
+ -fipa-reference @gol
+ -fmerge-constants
++-fshrink-wrap @gol
+ -fsplit-wide-types @gol
+ -ftree-builtin-call-dce @gol
+ -ftree-ccp @gol
+@@ -6506,6 +6507,12 @@ This option has no effect until one of @
+ When pipelining loops during selective scheduling, also pipeline outer loops.
+ This option has no effect until @option{-fsel-sched-pipelining} is turned on.
+ 
++@item -fshrink-wrap
++@opindex fshrink-wrap
++Emit function prologues only before parts of the function that need it,
++rather than at the top of the function.  This flag is enabled by default at
++@option{-O} and higher.
++
+ @item -fcaller-saves
+ @opindex fcaller-saves
+ Enable values to be allocated in registers that will be clobbered by
+Index: gcc-4_5-branch/gcc/doc/md.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/md.texi
++++ gcc-4_5-branch/gcc/doc/md.texi
+@@ -4801,7 +4801,19 @@ RTL generation phase.  In this case it i
+ multiple instructions are usually needed to return from a function, but
+ some class of functions only requires one instruction to implement a
+ return.  Normally, the applicable functions are those which do not need
+-to save any registers or allocate stack space.
++to save any registers or allocate stack space, although some targets
++have instructions that can perform both the epilogue and function return
++in one instruction.
++
++@cindex @code{simple_return} instruction pattern
++@item @samp{simple_return}
++Subroutine return instruction.  This instruction pattern name should be
++defined only if a single instruction can do all the work of returning
++from a function on a path where no epilogue is required.  This pattern
++is very similar to the @code{return} instruction pattern, but it is emitted
++only by the shrink-wrapping optimization on paths where the function
++prologue has not been executed, and a function return should occur without
++any of the effects of the epilogue.
+ 
+ @findex reload_completed
+ @findex leaf_function_p
+Index: gcc-4_5-branch/gcc/doc/rtl.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/rtl.texi
++++ gcc-4_5-branch/gcc/doc/rtl.texi
+@@ -2888,6 +2888,13 @@ placed in @code{pc} to return to the cal
+ Note that an insn pattern of @code{(return)} is logically equivalent to
+ @code{(set (pc) (return))}, but the latter form is never used.
+ 
++@findex simple_return
++@item (simple_return)
++Like @code{(return)}, but truly represents only a function return, while
++@code{(return)} may represent an insn that also performs other functions
++of the function epilogue.  Like @code{(return)}, this may also occur in
++conditional jumps.
++
+ @findex call
+ @item (call @var{function} @var{nargs})
+ Represents a function call.  @var{function} is a @code{mem} expression
+@@ -3017,7 +3024,7 @@ Represents several side effects performe
+ brackets stand for a vector; the operand of @code{parallel} is a
+ vector of expressions.  @var{x0}, @var{x1} and so on are individual
+ side effect expressions---expressions of code @code{set}, @code{call},
+-@code{return}, @code{clobber} or @code{use}.
++@code{return}, @code{simple_return}, @code{clobber} or @code{use}.
+ 
+ ``In parallel'' means that first all the values used in the individual
+ side-effects are computed, and second all the actual side-effects are
+@@ -3656,14 +3663,16 @@ and @code{call_insn} insns:
+ @table @code
+ @findex PATTERN
+ @item PATTERN (@var{i})
+-An expression for the side effect performed by this insn.  This must be
+-one of the following codes: @code{set}, @code{call}, @code{use},
+-@code{clobber}, @code{return}, @code{asm_input}, @code{asm_output},
+-@code{addr_vec}, @code{addr_diff_vec}, @code{trap_if}, @code{unspec},
+-@code{unspec_volatile}, @code{parallel}, @code{cond_exec}, or @code{sequence}.  If it is a @code{parallel},
+-each element of the @code{parallel} must be one these codes, except that
+-@code{parallel} expressions cannot be nested and @code{addr_vec} and
+-@code{addr_diff_vec} are not permitted inside a @code{parallel} expression.
++An expression for the side effect performed by this insn.  This must
++be one of the following codes: @code{set}, @code{call}, @code{use},
++@code{clobber}, @code{return}, @code{simple_return}, @code{asm_input},
++@code{asm_output}, @code{addr_vec}, @code{addr_diff_vec},
++@code{trap_if}, @code{unspec}, @code{unspec_volatile},
++@code{parallel}, @code{cond_exec}, or @code{sequence}.  If it is a
++@code{parallel}, each element of the @code{parallel} must be one these
++codes, except that @code{parallel} expressions cannot be nested and
++@code{addr_vec} and @code{addr_diff_vec} are not permitted inside a
++@code{parallel} expression.
+ 
+ @findex INSN_CODE
+ @item INSN_CODE (@var{i})
+Index: gcc-4_5-branch/gcc/doc/tm.texi
+===================================================================
+--- gcc-4_5-branch.orig/gcc/doc/tm.texi
++++ gcc-4_5-branch/gcc/doc/tm.texi
+@@ -3287,6 +3287,12 @@ Define this if the return address of a p
+ from the frame pointer of the previous stack frame.
+ @end defmac
+ 
++@defmac RETURN_ADDR_REGNUM
++If defined, a C expression whose value is the register number of the return
++address for the current function.  Targets that pass the return address on
++the stack should not define this macro.
++@end defmac
++
+ @defmac INCOMING_RETURN_ADDR_RTX
+ A C expression whose value is RTL representing the location of the
+ incoming return address at the beginning of any function, before the
+Index: gcc-4_5-branch/gcc/dwarf2out.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/dwarf2out.c
++++ gcc-4_5-branch/gcc/dwarf2out.c
+@@ -1396,7 +1396,7 @@ compute_barrier_args_size_1 (rtx insn, H
+     {
+       rtx dest = JUMP_LABEL (insn);
+ 
+-      if (dest)
++      if (dest && !ANY_RETURN_P (dest))
+ 	{
+ 	  if (barrier_args_size [INSN_UID (dest)] < 0)
+ 	    {
+Index: gcc-4_5-branch/gcc/emit-rtl.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/emit-rtl.c
++++ gcc-4_5-branch/gcc/emit-rtl.c
+@@ -2432,6 +2432,8 @@ verify_rtx_sharing (rtx orig, rtx insn)
+     case CODE_LABEL:
+     case PC:
+     case CC0:
++    case RETURN:
++    case SIMPLE_RETURN:
+     case SCRATCH:
+       return;
+       /* SCRATCH must be shared because they represent distinct values.  */
+@@ -3323,14 +3325,17 @@ prev_label (rtx insn)
+   return insn;
+ }
+ 
+-/* Return the last label to mark the same position as LABEL.  Return null
+-   if LABEL itself is null.  */
++/* Return the last label to mark the same position as LABEL.  Return LABEL
++   itself if it is null or any return rtx.  */
+ 
+ rtx
+ skip_consecutive_labels (rtx label)
+ {
+   rtx insn;
+ 
++  if (label && ANY_RETURN_P (label))
++    return label;
++
+   for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn))
+     if (LABEL_P (insn))
+       label = insn;
+@@ -5209,7 +5214,7 @@ classify_insn (rtx x)
+     return CODE_LABEL;
+   if (GET_CODE (x) == CALL)
+     return CALL_INSN;
+-  if (GET_CODE (x) == RETURN)
++  if (GET_CODE (x) == RETURN || GET_CODE (x) == SIMPLE_RETURN)
+     return JUMP_INSN;
+   if (GET_CODE (x) == SET)
+     {
+@@ -5715,8 +5720,10 @@ init_emit_regs (void)
+   init_reg_modes_target ();
+ 
+   /* Assign register numbers to the globally defined register rtx.  */
+-  pc_rtx = gen_rtx_PC (VOIDmode);
+-  cc0_rtx = gen_rtx_CC0 (VOIDmode);
++  pc_rtx = gen_rtx_fmt_ (PC, VOIDmode);
++  ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode);
++  simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode);
++  cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode);
+   stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
+   frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
+   hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
+Index: gcc-4_5-branch/gcc/final.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/final.c
++++ gcc-4_5-branch/gcc/final.c
+@@ -2428,7 +2428,7 @@ final_scan_insn (rtx insn, FILE *file, i
+ 	        delete_insn (insn);
+ 		break;
+ 	      }
+-	    else if (GET_CODE (SET_SRC (body)) == RETURN)
++	    else if (ANY_RETURN_P (SET_SRC (body)))
+ 	      /* Replace (set (pc) (return)) with (return).  */
+ 	      PATTERN (insn) = body = SET_SRC (body);
+ 
+Index: gcc-4_5-branch/gcc/function.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/function.c
++++ gcc-4_5-branch/gcc/function.c
+@@ -147,9 +147,6 @@ extern tree debug_find_var_in_block_tree
+    can always export `prologue_epilogue_contains'.  */
+ static void record_insns (rtx, rtx, htab_t *) ATTRIBUTE_UNUSED;
+ static bool contains (const_rtx, htab_t);
+-#ifdef HAVE_return
+-static void emit_return_into_block (basic_block);
+-#endif
+ static void prepare_function_start (void);
+ static void do_clobber_return_reg (rtx, void *);
+ static void do_use_return_reg (rtx, void *);
+@@ -4987,35 +4984,190 @@ prologue_epilogue_contains (const_rtx in
+   return 0;
+ }
+ 
++#ifdef HAVE_simple_return
++/* This collects sets and clobbers of hard registers in a HARD_REG_SET,
++   which is pointed to by DATA.  */
++static void
++record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
++{
++  HARD_REG_SET *pset = (HARD_REG_SET *)data;
++  if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
++    {
++      int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)];
++      while (nregs-- > 0)
++	SET_HARD_REG_BIT (*pset, REGNO (x) + nregs);
++    }
++}
++
++/* A subroutine of requires_stack_frame_p, called via for_each_rtx.
++   If any change is made, set CHANGED
++   to true.  */
++
++static int
++frame_required_for_rtx (rtx *loc, void *data ATTRIBUTE_UNUSED)
++{
++  rtx x = *loc;
++  if (x == stack_pointer_rtx || x == hard_frame_pointer_rtx
++      || x == arg_pointer_rtx || x == pic_offset_table_rtx
++#ifdef RETURN_ADDR_REGNUM
++      || (REG_P (x) && REGNO (x) == RETURN_ADDR_REGNUM)
++#endif
++      )
++    return 1;
++  return 0;
++}
++
++static bool
++requires_stack_frame_p (rtx insn)
++{
++  HARD_REG_SET hardregs;
++  unsigned regno;
++
++  if (!INSN_P (insn) || DEBUG_INSN_P (insn))
++    return false;
++  if (CALL_P (insn))
++    return !SIBLING_CALL_P (insn);
++  if (for_each_rtx (&PATTERN (insn), frame_required_for_rtx, NULL))
++    return true;
++  CLEAR_HARD_REG_SET (hardregs);
++  note_stores (PATTERN (insn), record_hard_reg_sets, &hardregs);
++  AND_COMPL_HARD_REG_SET (hardregs, call_used_reg_set);
++  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
++    if (TEST_HARD_REG_BIT (hardregs, regno)
++	&& df_regs_ever_live_p (regno))
++      return true;
++  return false;
++}
++#endif
++
+ #ifdef HAVE_return
+-/* Insert gen_return at the end of block BB.  This also means updating
+-   block_for_insn appropriately.  */
++
++static rtx
++gen_return_pattern (bool simple_p)
++{
++#ifdef HAVE_simple_return
++  return simple_p ? gen_simple_return () : gen_return ();
++#else
++  gcc_assert (!simple_p);
++  return gen_return ();
++#endif
++}
++
++/* Insert an appropriate return pattern at the end of block BB.  This
++   also means updating block_for_insn appropriately.  */
+ 
+ static void
+-emit_return_into_block (basic_block bb)
++emit_return_into_block (bool simple_p, basic_block bb)
+ {
+-  emit_jump_insn_after (gen_return (), BB_END (bb));
++  rtx jump;
++  jump = emit_jump_insn_after (gen_return_pattern (simple_p), BB_END (bb));
++  JUMP_LABEL (jump) = simple_p ? simple_return_rtx : ret_rtx;
+ }
+-#endif /* HAVE_return */
++#endif
+ 
+ /* Generate the prologue and epilogue RTL if the machine supports it.  Thread
+    this into place with notes indicating where the prologue ends and where
+-   the epilogue begins.  Update the basic block information when possible.  */
++   the epilogue begins.  Update the basic block information when possible.
++
++   Notes on epilogue placement:
++   There are several kinds of edges to the exit block:
++   * a single fallthru edge from LAST_BB
++   * possibly, edges from blocks containing sibcalls
++   * possibly, fake edges from infinite loops
++
++   The epilogue is always emitted on the fallthru edge from the last basic
++   block in the function, LAST_BB, into the exit block.
++
++   If LAST_BB is empty except for a label, it is the target of every
++   other basic block in the function that ends in a return.  If a
++   target has a return or simple_return pattern (possibly with
++   conditional variants), these basic blocks can be changed so that a
++   return insn is emitted into them, and their target is adjusted to
++   the real exit block.
++
++   Notes on shrink wrapping: We implement a fairly conservative
++   version of shrink-wrapping rather than the textbook one.  We only
++   generate a single prologue and a single epilogue.  This is
++   sufficient to catch a number of interesting cases involving early
++   exits.
++
++   First, we identify the blocks that require the prologue to occur before
++   them.  These are the ones that modify a call-saved register, or reference
++   any of the stack or frame pointer registers.  To simplify things, we then
++   mark everything reachable from these blocks as also requiring a prologue.
++   This takes care of loops automatically, and avoids the need to examine
++   whether MEMs reference the frame, since it is sufficient to check for
++   occurrences of the stack or frame pointer.
++
++   We then compute the set of blocks for which the need for a prologue
++   is anticipatable (borrowing terminology from the shrink-wrapping
++   description in Muchnick's book).  These are the blocks which either
++   require a prologue themselves, or those that have only successors
++   where the prologue is anticipatable.  The prologue needs to be
++   inserted on all edges from BB1->BB2 where BB2 is in ANTIC and BB1
++   is not.  For the moment, we ensure that only one such edge exists.
++
++   The epilogue is placed as described above, but we make a
++   distinction between inserting return and simple_return patterns
++   when modifying other blocks that end in a return.  Blocks that end
++   in a sibcall omit the sibcall_epilogue if the block is not in
++   ANTIC.  */
+ 
+ static void
+ thread_prologue_and_epilogue_insns (void)
+ {
+   int inserted = 0;
++  basic_block last_bb;
++  bool last_bb_active;
++#ifdef HAVE_simple_return
++  bool unconverted_simple_returns = false;
++  basic_block simple_return_block = NULL;
++#endif
++  rtx returnjump ATTRIBUTE_UNUSED;
++  rtx seq ATTRIBUTE_UNUSED, epilogue_end ATTRIBUTE_UNUSED;
++  rtx prologue_seq ATTRIBUTE_UNUSED, split_prologue_seq ATTRIBUTE_UNUSED;
++  edge entry_edge, orig_entry_edge, exit_fallthru_edge;
+   edge e;
+-#if defined (HAVE_sibcall_epilogue) || defined (HAVE_epilogue) || defined (HAVE_return) || defined (HAVE_prologue)
+-  rtx seq;
+-#endif
+-#if defined (HAVE_epilogue) || defined(HAVE_return)
+-  rtx epilogue_end = NULL_RTX;
+-#endif
+   edge_iterator ei;
++  bitmap_head bb_flags;
++
++  df_analyze ();
+ 
+   rtl_profile_for_bb (ENTRY_BLOCK_PTR);
++
++  epilogue_end = NULL_RTX;
++  returnjump = NULL_RTX;
++
++  /* Can't deal with multiple successors of the entry block at the
++     moment.  Function should always have at least one entry
++     point.  */
++  gcc_assert (single_succ_p (ENTRY_BLOCK_PTR));
++  entry_edge = single_succ_edge (ENTRY_BLOCK_PTR);
++  orig_entry_edge = entry_edge;
++
++  exit_fallthru_edge = find_fallthru_edge (EXIT_BLOCK_PTR->preds);
++  if (exit_fallthru_edge != NULL)
++    {
++      rtx label;
++
++      last_bb = exit_fallthru_edge->src;
++      /* Test whether there are active instructions in the last block.  */
++      label = BB_END (last_bb);
++      while (label && !LABEL_P (label))
++	{
++	  if (active_insn_p (label))
++	    break;
++	  label = PREV_INSN (label);
++	}
++
++      last_bb_active = BB_HEAD (last_bb) != label || !LABEL_P (label);
++    }
++  else
++    {
++      last_bb = NULL;
++      last_bb_active = false;
++    }
++
+ #ifdef HAVE_prologue
+   if (HAVE_prologue)
+     {
+@@ -5040,20 +5192,169 @@ thread_prologue_and_epilogue_insns (void
+         emit_insn (gen_blockage ());
+ #endif
+ 
+-      seq = get_insns ();
++      prologue_seq = get_insns ();
+       end_sequence ();
+       set_insn_locators (seq, prologue_locator);
++    }
++#endif
+ 
+-      /* Can't deal with multiple successors of the entry block
+-         at the moment.  Function should always have at least one
+-         entry point.  */
+-      gcc_assert (single_succ_p (ENTRY_BLOCK_PTR));
++  bitmap_initialize (&bb_flags, &bitmap_default_obstack);
+ 
+-      insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
+-      inserted = 1;
++#ifdef HAVE_simple_return
++  /* Try to perform a kind of shrink-wrapping, making sure the
++     prologue/epilogue is emitted only around those parts of the
++     function that require it.  */
++
++  if (flag_shrink_wrap && HAVE_simple_return && !flag_non_call_exceptions
++      && HAVE_prologue && !crtl->calls_eh_return)
++    {
++      HARD_REG_SET prologue_clobbered, live_on_edge;
++      rtx p_insn;
++      VEC(basic_block, heap) *vec;
++      basic_block bb;
++      bitmap_head bb_antic_flags;
++      bitmap_head bb_on_list;
++
++      bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack);
++      bitmap_initialize (&bb_on_list, &bitmap_default_obstack);
++
++      vec = VEC_alloc (basic_block, heap, n_basic_blocks);
++
++      FOR_EACH_BB (bb)
++	{
++	  rtx insn;
++	  FOR_BB_INSNS (bb, insn)
++	    {
++	      if (requires_stack_frame_p (insn))
++		{
++		  bitmap_set_bit (&bb_flags, bb->index);
++		  VEC_quick_push (basic_block, vec, bb);
++		  break;
++		}
++	    }
++	}
++
++      /* For every basic block that needs a prologue, mark all blocks
++	 reachable from it, so as to ensure they are also seen as
++	 requiring a prologue.  */
++      while (!VEC_empty (basic_block, vec))
++	{
++	  basic_block tmp_bb = VEC_pop (basic_block, vec);
++	  edge e;
++	  edge_iterator ei;
++	  FOR_EACH_EDGE (e, ei, tmp_bb->succs)
++	    {
++	      if (e->dest == EXIT_BLOCK_PTR
++		  || bitmap_bit_p (&bb_flags, e->dest->index))
++		continue;
++	      bitmap_set_bit (&bb_flags, e->dest->index);
++	      VEC_quick_push (basic_block, vec, e->dest);
++	    }
++	}
++      /* If the last basic block contains only a label, we'll be able
++	 to convert jumps to it to (potentially conditional) return
++	 insns later.  This means we don't necessarily need a prologue
++	 for paths reaching it.  */
++      if (last_bb)
++	{
++	  if (!last_bb_active)
++	    bitmap_clear_bit (&bb_flags, last_bb->index);
++	  else if (!bitmap_bit_p (&bb_flags, last_bb->index))
++	    goto fail_shrinkwrap;
++	}
++
++      /* Now walk backwards from every block that is marked as needing
++	 a prologue to compute the bb_antic_flags bitmap.  */
++      bitmap_copy (&bb_antic_flags, &bb_flags);
++      FOR_EACH_BB (bb)
++	{
++	  edge e;
++	  edge_iterator ei;
++	  if (!bitmap_bit_p (&bb_flags, bb->index))
++	    continue;
++	  FOR_EACH_EDGE (e, ei, bb->preds)
++	    if (!bitmap_bit_p (&bb_antic_flags, e->src->index))
++	      {
++		VEC_quick_push (basic_block, vec, e->src);
++		bitmap_set_bit (&bb_on_list, e->src->index);
++	      }
++	}
++      while (!VEC_empty (basic_block, vec))
++	{
++	  basic_block tmp_bb = VEC_pop (basic_block, vec);
++	  edge e;
++	  edge_iterator ei;
++	  bool all_set = true;
++	  
++	  bitmap_clear_bit (&bb_on_list, tmp_bb->index);
++	  FOR_EACH_EDGE (e, ei, tmp_bb->succs)
++	    {
++	      if (!bitmap_bit_p (&bb_antic_flags, e->dest->index))
++		{
++		  all_set = false;
++		  break;
++		}
++	    }
++	  if (all_set)
++	    {
++	      bitmap_set_bit (&bb_antic_flags, tmp_bb->index);
++	      FOR_EACH_EDGE (e, ei, tmp_bb->preds)
++		if (!bitmap_bit_p (&bb_antic_flags, e->src->index))
++		  {
++		    VEC_quick_push (basic_block, vec, e->src);
++		    bitmap_set_bit (&bb_on_list, e->src->index);
++		  }
++	    }
++	}
++      /* Find exactly one edge that leads to a block in ANTIC from
++	 a block that isn't.  */
++      if (!bitmap_bit_p (&bb_antic_flags, entry_edge->dest->index))
++	FOR_EACH_BB (bb)
++	  {
++	    if (!bitmap_bit_p (&bb_antic_flags, bb->index))
++	      continue;
++	    FOR_EACH_EDGE (e, ei, bb->preds)
++	      if (!bitmap_bit_p (&bb_antic_flags, e->src->index))
++		{
++		  if (entry_edge != orig_entry_edge)
++		    {
++		      entry_edge = orig_entry_edge;
++		      goto fail_shrinkwrap;
++		    }
++		  entry_edge = e;
++		}
++	  }
++
++      /* Test whether the prologue is known to clobber any register
++	 (other than FP or SP) which are live on the edge.  */
++      CLEAR_HARD_REG_SET (prologue_clobbered);
++      for (p_insn = prologue_seq; p_insn; p_insn = NEXT_INSN (p_insn))
++	if (NONDEBUG_INSN_P (p_insn))
++	  note_stores (PATTERN (p_insn), record_hard_reg_sets,
++		       &prologue_clobbered);
++      CLEAR_HARD_REG_BIT (prologue_clobbered, STACK_POINTER_REGNUM);
++      if (frame_pointer_needed)
++	CLEAR_HARD_REG_BIT (prologue_clobbered, HARD_FRAME_POINTER_REGNUM);
++
++      CLEAR_HARD_REG_SET (live_on_edge);
++      reg_set_to_hard_reg_set (&live_on_edge,
++			       df_get_live_in (entry_edge->dest));
++      if (hard_reg_set_intersect_p (live_on_edge, prologue_clobbered))
++	entry_edge = orig_entry_edge;
++
++    fail_shrinkwrap:
++      bitmap_clear (&bb_antic_flags);
++      bitmap_clear (&bb_on_list);
++      VEC_free (basic_block, heap, vec);
+     }
+ #endif
+ 
++  if (prologue_seq != NULL_RTX)
++    {
++      insert_insn_on_edge (prologue_seq, entry_edge);
++      inserted = true;
++    }
++
+   /* If the exit block has no non-fake predecessors, we don't need
+      an epilogue.  */
+   FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
+@@ -5063,100 +5364,130 @@ thread_prologue_and_epilogue_insns (void
+     goto epilogue_done;
+ 
+   rtl_profile_for_bb (EXIT_BLOCK_PTR);
++
+ #ifdef HAVE_return
+-  if (optimize && HAVE_return)
++  /* If we're allowed to generate a simple return instruction, then by
++     definition we don't need a full epilogue.  If the last basic
++     block before the exit block does not contain active instructions,
++     examine its predecessors and try to emit (conditional) return
++     instructions.  */
++  if (optimize && !last_bb_active
++      && (HAVE_return || entry_edge != orig_entry_edge))
+     {
+-      /* If we're allowed to generate a simple return instruction,
+-	 then by definition we don't need a full epilogue.  Examine
+-	 the block that falls through to EXIT.   If it does not
+-	 contain any code, examine its predecessors and try to
+-	 emit (conditional) return instructions.  */
+-
+-      basic_block last;
++      edge_iterator ei2;
++      int i;
++      basic_block bb;
+       rtx label;
++      VEC(basic_block,heap) *src_bbs;
+ 
+-      FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
+-	if (e->flags & EDGE_FALLTHRU)
+-	  break;
+-      if (e == NULL)
++      if (exit_fallthru_edge == NULL)
+ 	goto epilogue_done;
+-      last = e->src;
++      label = BB_HEAD (last_bb);
+ 
+-      /* Verify that there are no active instructions in the last block.  */
+-      label = BB_END (last);
+-      while (label && !LABEL_P (label))
+-	{
+-	  if (active_insn_p (label))
+-	    break;
+-	  label = PREV_INSN (label);
+-	}
++      src_bbs = VEC_alloc (basic_block, heap, EDGE_COUNT (last_bb->preds));
++      FOR_EACH_EDGE (e, ei2, last_bb->preds)
++	if (e->src != ENTRY_BLOCK_PTR)
++	  VEC_quick_push (basic_block, src_bbs, e->src);
+ 
+-      if (BB_HEAD (last) == label && LABEL_P (label))
++      FOR_EACH_VEC_ELT (basic_block, src_bbs, i, bb)
+ 	{
+-	  edge_iterator ei2;
++	  bool simple_p;
++	  rtx jump;
++	  e = find_edge (bb, last_bb);
+ 
+-	  for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); )
+-	    {
+-	      basic_block bb = e->src;
+-	      rtx jump;
++	  jump = BB_END (bb);
+ 
+-	      if (bb == ENTRY_BLOCK_PTR)
+-		{
+-		  ei_next (&ei2);
+-		  continue;
+-		}
++#ifdef HAVE_simple_return
++	  simple_p = (entry_edge != orig_entry_edge
++		      ? !bitmap_bit_p (&bb_flags, bb->index) : false);
++#else
++	  simple_p = false;
++#endif
+ 
+-	      jump = BB_END (bb);
+-	      if (!JUMP_P (jump) || JUMP_LABEL (jump) != label)
+-		{
+-		  ei_next (&ei2);
+-		  continue;
+-		}
++	  if (!simple_p
++	      && (!HAVE_return || !JUMP_P (jump)
++		  || JUMP_LABEL (jump) != label))
++	    continue;
+ 
+-	      /* If we have an unconditional jump, we can replace that
+-		 with a simple return instruction.  */
+-	      if (simplejump_p (jump))
+-		{
+-		  emit_return_into_block (bb);
+-		  delete_insn (jump);
+-		}
++	  /* If we have an unconditional jump, we can replace that
++	     with a simple return instruction.  */
++	  if (!JUMP_P (jump))
++	    {
++	      emit_barrier_after (BB_END (bb));
++	      emit_return_into_block (simple_p, bb);
++	    }
++	  else if (simplejump_p (jump))
++	    {
++	      emit_return_into_block (simple_p, bb);
++	      delete_insn (jump);
++	    }
++	  else if (condjump_p (jump) && JUMP_LABEL (jump) != label)
++	    {
++	      basic_block new_bb;
++	      edge new_e;
+ 
+-	      /* If we have a conditional jump, we can try to replace
+-		 that with a conditional return instruction.  */
+-	      else if (condjump_p (jump))
+-		{
+-		  if (! redirect_jump (jump, 0, 0))
+-		    {
+-		      ei_next (&ei2);
+-		      continue;
+-		    }
++	      gcc_assert (simple_p);
++	      new_bb = split_edge (e);
++	      emit_barrier_after (BB_END (new_bb));
++	      emit_return_into_block (simple_p, new_bb);
++#ifdef HAVE_simple_return
++	      simple_return_block = new_bb;
++#endif
++	      new_e = single_succ_edge (new_bb);
++	      redirect_edge_succ (new_e, EXIT_BLOCK_PTR);
+ 
+-		  /* If this block has only one successor, it both jumps
+-		     and falls through to the fallthru block, so we can't
+-		     delete the edge.  */
+-		  if (single_succ_p (bb))
+-		    {
+-		      ei_next (&ei2);
+-		      continue;
+-		    }
+-		}
++	      continue;
++	    }
++	  /* If we have a conditional jump branching to the last
++	     block, we can try to replace that with a conditional
++	     return instruction.  */
++	  else if (condjump_p (jump))
++	    {
++	      rtx dest;
++	      if (simple_p)
++		dest = simple_return_rtx;
+ 	      else
++		dest = ret_rtx;
++	      if (! redirect_jump (jump, dest, 0))
+ 		{
+-		  ei_next (&ei2);
++#ifdef HAVE_simple_return
++		  if (simple_p)
++		    unconverted_simple_returns = true;
++#endif
+ 		  continue;
+ 		}
+ 
+-	      /* Fix up the CFG for the successful change we just made.  */
+-	      redirect_edge_succ (e, EXIT_BLOCK_PTR);
++	      /* If this block has only one successor, it both jumps
++		 and falls through to the fallthru block, so we can't
++		 delete the edge.  */
++	      if (single_succ_p (bb))
++		continue;
++	    }
++	  else
++	    {
++#ifdef HAVE_simple_return
++	      if (simple_p)
++		unconverted_simple_returns = true;
++#endif
++	      continue;
+ 	    }
+ 
++	  /* Fix up the CFG for the successful change we just made.  */
++	  redirect_edge_succ (e, EXIT_BLOCK_PTR);
++	}
++      VEC_free (basic_block, heap, src_bbs);
++
++      if (HAVE_return)
++	{
+ 	  /* Emit a return insn for the exit fallthru block.  Whether
+ 	     this is still reachable will be determined later.  */
+ 
+-	  emit_barrier_after (BB_END (last));
+-	  emit_return_into_block (last);
+-	  epilogue_end = BB_END (last);
+-	  single_succ_edge (last)->flags &= ~EDGE_FALLTHRU;
++	  emit_barrier_after (BB_END (last_bb));
++	  emit_return_into_block (false, last_bb);
++	  epilogue_end = BB_END (last_bb);
++	  if (JUMP_P (epilogue_end))
++	    JUMP_LABEL (epilogue_end) = ret_rtx;
++	  single_succ_edge (last_bb)->flags &= ~EDGE_FALLTHRU;
+ 	  goto epilogue_done;
+ 	}
+     }
+@@ -5193,15 +5524,10 @@ thread_prologue_and_epilogue_insns (void
+     }
+ #endif
+ 
+-  /* Find the edge that falls through to EXIT.  Other edges may exist
+-     due to RETURN instructions, but those don't need epilogues.
+-     There really shouldn't be a mixture -- either all should have
+-     been converted or none, however...  */
++  /* If nothing falls through into the exit block, we don't need an
++     epilogue.  */
+ 
+-  FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
+-    if (e->flags & EDGE_FALLTHRU)
+-      break;
+-  if (e == NULL)
++  if (exit_fallthru_edge == NULL)
+     goto epilogue_done;
+ 
+ #ifdef HAVE_epilogue
+@@ -5217,25 +5543,36 @@ thread_prologue_and_epilogue_insns (void
+       set_insn_locators (seq, epilogue_locator);
+ 
+       seq = get_insns ();
++      returnjump = get_last_insn ();
+       end_sequence ();
+ 
+-      insert_insn_on_edge (seq, e);
++      insert_insn_on_edge (seq, exit_fallthru_edge);
+       inserted = 1;
++      if (JUMP_P (returnjump))
++	{
++ 	  rtx pat = PATTERN (returnjump);
++ 	  if (GET_CODE (pat) == PARALLEL)
++	    pat = XVECEXP (pat, 0, 0);
++	  if (ANY_RETURN_P (pat))
++	    JUMP_LABEL (returnjump) = pat;
++	  else
++	    JUMP_LABEL (returnjump) = ret_rtx;
++	}
+     }
+   else
+ #endif
+     {
+       basic_block cur_bb;
+ 
+-      if (! next_active_insn (BB_END (e->src)))
++      if (! next_active_insn (BB_END (exit_fallthru_edge->src)))
+ 	goto epilogue_done;
+       /* We have a fall-through edge to the exit block, the source is not
+-         at the end of the function, and there will be an assembler epilogue
+-         at the end of the function.
+-         We can't use force_nonfallthru here, because that would try to
+-         use return.  Inserting a jump 'by hand' is extremely messy, so
++	 at the end of the function, and there will be an assembler epilogue
++	 at the end of the function.
++	 We can't use force_nonfallthru here, because that would try to
++	 use return.  Inserting a jump 'by hand' is extremely messy, so
+ 	 we take advantage of cfg_layout_finalize using
+-	fixup_fallthru_exit_predecessor.  */
++	 fixup_fallthru_exit_predecessor.  */
+       cfg_layout_initialize (0);
+       FOR_EACH_BB (cur_bb)
+ 	if (cur_bb->index >= NUM_FIXED_BLOCKS
+@@ -5244,6 +5581,7 @@ thread_prologue_and_epilogue_insns (void
+       cfg_layout_finalize ();
+     }
+ epilogue_done:
++
+   default_rtl_profile ();
+ 
+   if (inserted)
+@@ -5260,33 +5598,93 @@ epilogue_done:
+ 	}
+     }
+ 
++#ifdef HAVE_simple_return
++  /* If there were branches to an empty LAST_BB which we tried to
++     convert to conditional simple_returns, but couldn't for some
++     reason, create a block to hold a simple_return insn and redirect
++     those remaining edges.  */
++  if (unconverted_simple_returns)
++    {
++      edge_iterator ei2;
++      basic_block exit_pred = EXIT_BLOCK_PTR->prev_bb;
++
++      gcc_assert (entry_edge != orig_entry_edge);
++
++#ifdef HAVE_epilogue
++      if (simple_return_block == NULL && returnjump != NULL_RTX
++	  && JUMP_LABEL (returnjump) == simple_return_rtx)
++	{
++	  edge e = split_block (exit_fallthru_edge->src,
++				PREV_INSN (returnjump));
++	  simple_return_block = e->dest;
++	}
++#endif
++      if (simple_return_block == NULL)
++	{
++	  basic_block bb;
++	  rtx start;
++
++	  bb = create_basic_block (NULL, NULL, exit_pred);
++	  start = emit_jump_insn_after (gen_simple_return (),
++					BB_END (bb));
++	  JUMP_LABEL (start) = simple_return_rtx;
++	  emit_barrier_after (start);
++
++	  simple_return_block = bb;
++	  make_edge (bb, EXIT_BLOCK_PTR, 0);
++	}
++
++    restart_scan:
++      for (ei2 = ei_start (last_bb->preds); (e = ei_safe_edge (ei2)); )
++	{
++	  basic_block bb = e->src;
++
++	  if (bb != ENTRY_BLOCK_PTR
++	      && !bitmap_bit_p (&bb_flags, bb->index))
++	    {
++	      redirect_edge_and_branch_force (e, simple_return_block);
++	      goto restart_scan;
++	    }
++	  ei_next (&ei2);
++
++	}
++    }
++#endif
++
+ #ifdef HAVE_sibcall_epilogue
+   /* Emit sibling epilogues before any sibling call sites.  */
+   for (ei = ei_start (EXIT_BLOCK_PTR->preds); (e = ei_safe_edge (ei)); )
+     {
+       basic_block bb = e->src;
+       rtx insn = BB_END (bb);
++      rtx ep_seq;
+ 
+       if (!CALL_P (insn)
+-	  || ! SIBLING_CALL_P (insn))
++	  || ! SIBLING_CALL_P (insn)
++	  || (entry_edge != orig_entry_edge
++	      && !bitmap_bit_p (&bb_flags, bb->index)))
+ 	{
+ 	  ei_next (&ei);
+ 	  continue;
+ 	}
+ 
+-      start_sequence ();
+-      emit_note (NOTE_INSN_EPILOGUE_BEG);
+-      emit_insn (gen_sibcall_epilogue ());
+-      seq = get_insns ();
+-      end_sequence ();
++      ep_seq = gen_sibcall_epilogue ();
++      if (ep_seq)
++	{
++	  start_sequence ();
++	  emit_note (NOTE_INSN_EPILOGUE_BEG);
++	  emit_insn (ep_seq);
++	  seq = get_insns ();
++	  end_sequence ();
+ 
+-      /* Retain a map of the epilogue insns.  Used in life analysis to
+-	 avoid getting rid of sibcall epilogue insns.  Do this before we
+-	 actually emit the sequence.  */
+-      record_insns (seq, NULL, &epilogue_insn_hash);
+-      set_insn_locators (seq, epilogue_locator);
++	  /* Retain a map of the epilogue insns.  Used in life analysis to
++	     avoid getting rid of sibcall epilogue insns.  Do this before we
++	     actually emit the sequence.  */
++	  record_insns (seq, NULL, &epilogue_insn_hash);
++	  set_insn_locators (seq, epilogue_locator);
+ 
+-      emit_insn_before (seq, insn);
++	  emit_insn_before (seq, insn);
++	}
+       ei_next (&ei);
+     }
+ #endif
+@@ -5311,6 +5709,8 @@ epilogue_done:
+     }
+ #endif
+ 
++  bitmap_clear (&bb_flags);
++
+   /* Threading the prologue and epilogue changes the artificial refs
+      in the entry and exit blocks.  */
+   epilogue_completed = 1;
+Index: gcc-4_5-branch/gcc/genemit.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/genemit.c
++++ gcc-4_5-branch/gcc/genemit.c
+@@ -222,6 +222,12 @@ gen_exp (rtx x, enum rtx_code subroutine
+     case PC:
+       printf ("pc_rtx");
+       return;
++    case RETURN:
++      printf ("ret_rtx");
++      return;
++    case SIMPLE_RETURN:
++      printf ("simple_return_rtx");
++      return;
+     case CLOBBER:
+       if (REG_P (XEXP (x, 0)))
+ 	{
+@@ -544,8 +550,8 @@ gen_expand (rtx expand)
+ 	  || (GET_CODE (next) == PARALLEL
+ 	      && ((GET_CODE (XVECEXP (next, 0, 0)) == SET
+ 		   && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC)
+-		  || GET_CODE (XVECEXP (next, 0, 0)) == RETURN))
+-	  || GET_CODE (next) == RETURN)
++		  || ANY_RETURN_P (XVECEXP (next, 0, 0))))
++	  || ANY_RETURN_P (next))
+ 	printf ("  emit_jump_insn (");
+       else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL)
+ 	       || GET_CODE (next) == CALL
+@@ -660,7 +666,7 @@ gen_split (rtx split)
+ 	  || (GET_CODE (next) == PARALLEL
+ 	      && GET_CODE (XVECEXP (next, 0, 0)) == SET
+ 	      && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC)
+-	  || GET_CODE (next) == RETURN)
++	  || ANY_RETURN_P (next))
+ 	printf ("  emit_jump_insn (");
+       else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL)
+ 	       || GET_CODE (next) == CALL
+Index: gcc-4_5-branch/gcc/gengenrtl.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/gengenrtl.c
++++ gcc-4_5-branch/gcc/gengenrtl.c
+@@ -146,6 +146,10 @@ special_rtx (int idx)
+ 	  || strcmp (defs[idx].enumname, "REG") == 0
+ 	  || strcmp (defs[idx].enumname, "SUBREG") == 0
+ 	  || strcmp (defs[idx].enumname, "MEM") == 0
++	  || strcmp (defs[idx].enumname, "PC") == 0
++	  || strcmp (defs[idx].enumname, "CC0") == 0
++	  || strcmp (defs[idx].enumname, "RETURN") == 0
++	  || strcmp (defs[idx].enumname, "SIMPLE_RETURN") == 0
+ 	  || strcmp (defs[idx].enumname, "CONST_VECTOR") == 0);
+ }
+ 
+Index: gcc-4_5-branch/gcc/haifa-sched.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/haifa-sched.c
++++ gcc-4_5-branch/gcc/haifa-sched.c
+@@ -4231,7 +4231,7 @@ xrecalloc (void *p, size_t new_nmemb, si
+ /* Helper function.
+    Find fallthru edge from PRED.  */
+ edge
+-find_fallthru_edge (basic_block pred)
++find_fallthru_edge_from (basic_block pred)
+ {
+   edge e;
+   edge_iterator ei;
+@@ -4298,7 +4298,7 @@ init_before_recovery (basic_block *befor
+   edge e;
+ 
+   last = EXIT_BLOCK_PTR->prev_bb;
+-  e = find_fallthru_edge (last);
++  e = find_fallthru_edge_from (last);
+ 
+   if (e)
+     {
+@@ -5234,6 +5234,11 @@ check_cfg (rtx head, rtx tail)
+ 		    gcc_assert (/* Usual case.  */
+                                 (EDGE_COUNT (bb->succs) > 1
+                                  && !BARRIER_P (NEXT_INSN (head)))
++				/* Special cases, see cfglayout.c:
++				   fixup_reorder_chain.  */
++				|| (EDGE_COUNT (bb->succs) == 1
++				    && (!onlyjump_p (head)
++					|| returnjump_p (head)))
+                                 /* Or jump to the next instruction.  */
+                                 || (EDGE_COUNT (bb->succs) == 1
+                                     && (BB_HEAD (EDGE_I (bb->succs, 0)->dest)
+Index: gcc-4_5-branch/gcc/ifcvt.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/ifcvt.c
++++ gcc-4_5-branch/gcc/ifcvt.c
+@@ -105,7 +105,7 @@ static int find_if_case_1 (basic_block, 
+ static int find_if_case_2 (basic_block, edge, edge);
+ static int find_memory (rtx *, void *);
+ static int dead_or_predicable (basic_block, basic_block, basic_block,
+-			       basic_block, int);
++			       edge, int);
+ static void noce_emit_move_insn (rtx, rtx);
+ static rtx block_has_only_trap (basic_block);
+ 
+@@ -3791,6 +3791,7 @@ find_if_case_1 (basic_block test_bb, edg
+   basic_block then_bb = then_edge->dest;
+   basic_block else_bb = else_edge->dest;
+   basic_block new_bb;
++  rtx else_target = NULL_RTX;
+   int then_bb_index;
+ 
+   /* If we are partitioning hot/cold basic blocks, we don't want to
+@@ -3840,9 +3841,16 @@ find_if_case_1 (basic_block test_bb, edg
+ 				    predictable_edge_p (then_edge)))))
+     return FALSE;
+ 
++  if (else_bb == EXIT_BLOCK_PTR)
++    {
++      rtx jump = BB_END (else_edge->src);
++      gcc_assert (JUMP_P (jump));
++      else_target = JUMP_LABEL (jump);
++    }
++
+   /* Registers set are dead, or are predicable.  */
+   if (! dead_or_predicable (test_bb, then_bb, else_bb,
+-			    single_succ (then_bb), 1))
++			    single_succ_edge (then_bb), 1))
+     return FALSE;
+ 
+   /* Conversion went ok, including moving the insns and fixing up the
+@@ -3859,6 +3867,9 @@ find_if_case_1 (basic_block test_bb, edg
+       redirect_edge_succ (FALLTHRU_EDGE (test_bb), else_bb);
+       new_bb = 0;
+     }
++  else if (else_bb == EXIT_BLOCK_PTR)
++    new_bb = force_nonfallthru_and_redirect (FALLTHRU_EDGE (test_bb),
++					     else_bb, else_target);
+   else
+     new_bb = redirect_edge_and_branch_force (FALLTHRU_EDGE (test_bb),
+ 					     else_bb);
+@@ -3957,7 +3968,7 @@ find_if_case_2 (basic_block test_bb, edg
+     return FALSE;
+ 
+   /* Registers set are dead, or are predicable.  */
+-  if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ->dest, 0))
++  if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ, 0))
+     return FALSE;
+ 
+   /* Conversion went ok, including moving the insns and fixing up the
+@@ -3995,12 +4006,34 @@ find_memory (rtx *px, void *data ATTRIBU
+ 
+ static int
+ dead_or_predicable (basic_block test_bb, basic_block merge_bb,
+-		    basic_block other_bb, basic_block new_dest, int reversep)
++		    basic_block other_bb, edge dest_edge, int reversep)
+ {
+-  rtx head, end, jump, earliest = NULL_RTX, old_dest, new_label = NULL_RTX;
++  basic_block new_dest = dest_edge->dest;
++  rtx head, end, jump, earliest = NULL_RTX, old_dest;
+   bitmap merge_set = NULL;
+   /* Number of pending changes.  */
+   int n_validated_changes = 0;
++  rtx new_dest_label;
++
++  jump = BB_END (dest_edge->src);
++  if (JUMP_P (jump))
++    {
++      new_dest_label = JUMP_LABEL (jump);
++      if (new_dest_label == NULL_RTX)
++	{
++	  new_dest_label = PATTERN (jump);
++	  gcc_assert (ANY_RETURN_P (new_dest_label));
++	}
++    }
++  else if (other_bb != new_dest)
++    {
++      if (new_dest == EXIT_BLOCK_PTR)
++	new_dest_label = ret_rtx;
++      else
++	new_dest_label = block_label (new_dest);
++    }
++  else
++    new_dest_label = NULL_RTX;
+ 
+   jump = BB_END (test_bb);
+ 
+@@ -4220,10 +4253,9 @@ dead_or_predicable (basic_block test_bb,
+   old_dest = JUMP_LABEL (jump);
+   if (other_bb != new_dest)
+     {
+-      new_label = block_label (new_dest);
+       if (reversep
+-	  ? ! invert_jump_1 (jump, new_label)
+-	  : ! redirect_jump_1 (jump, new_label))
++	  ? ! invert_jump_1 (jump, new_dest_label)
++	  : ! redirect_jump_1 (jump, new_dest_label))
+ 	goto cancel;
+     }
+ 
+@@ -4234,7 +4266,7 @@ dead_or_predicable (basic_block test_bb,
+ 
+   if (other_bb != new_dest)
+     {
+-      redirect_jump_2 (jump, old_dest, new_label, 0, reversep);
++      redirect_jump_2 (jump, old_dest, new_dest_label, 0, reversep);
+ 
+       redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest);
+       if (reversep)
+Index: gcc-4_5-branch/gcc/jump.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/jump.c
++++ gcc-4_5-branch/gcc/jump.c
+@@ -29,7 +29,8 @@ along with GCC; see the file COPYING3.  
+    JUMP_LABEL internal field.  With this we can detect labels that
+    become unused because of the deletion of all the jumps that
+    formerly used them.  The JUMP_LABEL info is sometimes looked
+-   at by later passes.
++   at by later passes.  For return insns, it contains either a
++   RETURN or a SIMPLE_RETURN rtx.
+ 
+    The subroutines redirect_jump and invert_jump are used
+    from other passes as well.  */
+@@ -742,10 +743,10 @@ condjump_p (const_rtx insn)
+     return (GET_CODE (x) == IF_THEN_ELSE
+ 	    && ((GET_CODE (XEXP (x, 2)) == PC
+ 		 && (GET_CODE (XEXP (x, 1)) == LABEL_REF
+-		     || GET_CODE (XEXP (x, 1)) == RETURN))
++		     || ANY_RETURN_P (XEXP (x, 1))))
+ 		|| (GET_CODE (XEXP (x, 1)) == PC
+ 		    && (GET_CODE (XEXP (x, 2)) == LABEL_REF
+-			|| GET_CODE (XEXP (x, 2)) == RETURN))));
++			|| ANY_RETURN_P (XEXP (x, 2))))));
+ }
+ 
+ /* Return nonzero if INSN is a (possibly) conditional jump inside a
+@@ -774,11 +775,11 @@ condjump_in_parallel_p (const_rtx insn)
+     return 0;
+   if (XEXP (SET_SRC (x), 2) == pc_rtx
+       && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF
+-	  || GET_CODE (XEXP (SET_SRC (x), 1)) == RETURN))
++	  || ANY_RETURN_P (XEXP (SET_SRC (x), 1)) == RETURN))
+     return 1;
+   if (XEXP (SET_SRC (x), 1) == pc_rtx
+       && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF
+-	  || GET_CODE (XEXP (SET_SRC (x), 2)) == RETURN))
++	  || ANY_RETURN_P (XEXP (SET_SRC (x), 2))))
+     return 1;
+   return 0;
+ }
+@@ -840,8 +841,9 @@ any_condjump_p (const_rtx insn)
+   a = GET_CODE (XEXP (SET_SRC (x), 1));
+   b = GET_CODE (XEXP (SET_SRC (x), 2));
+ 
+-  return ((b == PC && (a == LABEL_REF || a == RETURN))
+-	  || (a == PC && (b == LABEL_REF || b == RETURN)));
++  return ((b == PC && (a == LABEL_REF || a == RETURN || a == SIMPLE_RETURN))
++	  || (a == PC
++	      && (b == LABEL_REF || b == RETURN || b == SIMPLE_RETURN)));
+ }
+ 
+ /* Return the label of a conditional jump.  */
+@@ -878,6 +880,7 @@ returnjump_p_1 (rtx *loc, void *data ATT
+   switch (GET_CODE (x))
+     {
+     case RETURN:
++    case SIMPLE_RETURN:
+     case EH_RETURN:
+       return true;
+ 
+@@ -1200,7 +1203,7 @@ delete_related_insns (rtx insn)
+   /* If deleting a jump, decrement the count of the label,
+      and delete the label if it is now unused.  */
+ 
+-  if (JUMP_P (insn) && JUMP_LABEL (insn))
++  if (JUMP_P (insn) && JUMP_LABEL (insn) && !ANY_RETURN_P (JUMP_LABEL (insn)))
+     {
+       rtx lab = JUMP_LABEL (insn), lab_next;
+ 
+@@ -1331,6 +1334,18 @@ delete_for_peephole (rtx from, rtx to)
+      is also an unconditional jump in that case.  */
+ }
+ 
++/* A helper function for redirect_exp_1; examines its input X and returns
++   either a LABEL_REF around a label, or a RETURN if X was NULL.  */
++static rtx
++redirect_target (rtx x)
++{
++  if (x == NULL_RTX)
++    return ret_rtx;
++  if (!ANY_RETURN_P (x))
++    return gen_rtx_LABEL_REF (Pmode, x);
++  return x;
++}
++
+ /* Throughout LOC, redirect OLABEL to NLABEL.  Treat null OLABEL or
+    NLABEL as a return.  Accrue modifications into the change group.  */
+ 
+@@ -1342,37 +1357,19 @@ redirect_exp_1 (rtx *loc, rtx olabel, rt
+   int i;
+   const char *fmt;
+ 
+-  if (code == LABEL_REF)
+-    {
+-      if (XEXP (x, 0) == olabel)
+-	{
+-	  rtx n;
+-	  if (nlabel)
+-	    n = gen_rtx_LABEL_REF (Pmode, nlabel);
+-	  else
+-	    n = gen_rtx_RETURN (VOIDmode);
+-
+-	  validate_change (insn, loc, n, 1);
+-	  return;
+-	}
+-    }
+-  else if (code == RETURN && olabel == 0)
++  if ((code == LABEL_REF && XEXP (x, 0) == olabel)
++      || x == olabel)
+     {
+-      if (nlabel)
+-	x = gen_rtx_LABEL_REF (Pmode, nlabel);
+-      else
+-	x = gen_rtx_RETURN (VOIDmode);
+-      if (loc == &PATTERN (insn))
+-	x = gen_rtx_SET (VOIDmode, pc_rtx, x);
+-      validate_change (insn, loc, x, 1);
++      validate_change (insn, loc, redirect_target (nlabel), 1);
+       return;
+     }
+ 
+-  if (code == SET && nlabel == 0 && SET_DEST (x) == pc_rtx
++  if (code == SET && SET_DEST (x) == pc_rtx
++      && ANY_RETURN_P (nlabel)
+       && GET_CODE (SET_SRC (x)) == LABEL_REF
+       && XEXP (SET_SRC (x), 0) == olabel)
+     {
+-      validate_change (insn, loc, gen_rtx_RETURN (VOIDmode), 1);
++      validate_change (insn, loc, nlabel, 1);
+       return;
+     }
+ 
+@@ -1409,6 +1406,7 @@ redirect_jump_1 (rtx jump, rtx nlabel)
+   int ochanges = num_validated_changes ();
+   rtx *loc, asmop;
+ 
++  gcc_assert (nlabel);
+   asmop = extract_asm_operands (PATTERN (jump));
+   if (asmop)
+     {
+@@ -1430,17 +1428,20 @@ redirect_jump_1 (rtx jump, rtx nlabel)
+    jump target label is unused as a result, it and the code following
+    it may be deleted.
+ 
+-   If NLABEL is zero, we are to turn the jump into a (possibly conditional)
+-   RETURN insn.
++   Normally, NLABEL will be a label, but it may also be a RETURN or
++   SIMPLE_RETURN rtx; in that case we are to turn the jump into a
++   (possibly conditional) return insn.
+ 
+    The return value will be 1 if the change was made, 0 if it wasn't
+-   (this can only occur for NLABEL == 0).  */
++   (this can only occur when trying to produce return insns).  */
+ 
+ int
+ redirect_jump (rtx jump, rtx nlabel, int delete_unused)
+ {
+   rtx olabel = JUMP_LABEL (jump);
+ 
++  gcc_assert (nlabel != NULL_RTX);
++
+   if (nlabel == olabel)
+     return 1;
+ 
+@@ -1452,7 +1453,7 @@ redirect_jump (rtx jump, rtx nlabel, int
+ }
+ 
+ /* Fix up JUMP_LABEL and label ref counts after OLABEL has been replaced with
+-   NLABEL in JUMP.
++   NEW_DEST in JUMP.
+    If DELETE_UNUSED is positive, delete related insn to OLABEL if its ref
+    count has dropped to zero.  */
+ void
+@@ -1468,13 +1469,14 @@ redirect_jump_2 (rtx jump, rtx olabel, r
+      about this.  */
+   gcc_assert (delete_unused >= 0);
+   JUMP_LABEL (jump) = nlabel;
+-  if (nlabel)
++  if (nlabel && !ANY_RETURN_P (nlabel))
+     ++LABEL_NUSES (nlabel);
+ 
+   /* Update labels in any REG_EQUAL note.  */
+   if ((note = find_reg_note (jump, REG_EQUAL, NULL_RTX)) != NULL_RTX)
+     {
+-      if (!nlabel || (invert && !invert_exp_1 (XEXP (note, 0), jump)))
++      if (ANY_RETURN_P (nlabel)
++	  || (invert && !invert_exp_1 (XEXP (note, 0), jump)))
+ 	remove_note (jump, note);
+       else
+ 	{
+@@ -1483,7 +1485,8 @@ redirect_jump_2 (rtx jump, rtx olabel, r
+ 	}
+     }
+ 
+-  if (olabel && --LABEL_NUSES (olabel) == 0 && delete_unused > 0
++  if (olabel && !ANY_RETURN_P (olabel)
++      && --LABEL_NUSES (olabel) == 0 && delete_unused > 0
+       /* Undefined labels will remain outside the insn stream.  */
+       && INSN_UID (olabel))
+     delete_related_insns (olabel);
+Index: gcc-4_5-branch/gcc/opts.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/opts.c
++++ gcc-4_5-branch/gcc/opts.c
+@@ -909,6 +909,7 @@ decode_options (unsigned int argc, const
+   flag_ipa_cp = opt2;
+   flag_ipa_sra = opt2;
+   flag_ee = opt2;
++  flag_shrink_wrap = opt2;
+ 
+   /* Track fields in field-sensitive alias analysis.  */
+   set_param_value ("max-fields-for-field-sensitive",
+Index: gcc-4_5-branch/gcc/print-rtl.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/print-rtl.c
++++ gcc-4_5-branch/gcc/print-rtl.c
+@@ -308,9 +308,16 @@ print_rtx (const_rtx in_rtx)
+ 	      }
+ 	  }
+ 	else if (i == 8 && JUMP_P (in_rtx) && JUMP_LABEL (in_rtx) != NULL)
+-	  /* Output the JUMP_LABEL reference.  */
+-	  fprintf (outfile, "\n%s%*s -> %d", print_rtx_head, indent * 2, "",
+-		   INSN_UID (JUMP_LABEL (in_rtx)));
++	  {
++	    /* Output the JUMP_LABEL reference.  */
++	    fprintf (outfile, "\n%s%*s -> ", print_rtx_head, indent * 2, "");
++	    if (GET_CODE (JUMP_LABEL (in_rtx)) == RETURN)
++	      fprintf (outfile, "return");
++	    else if (GET_CODE (JUMP_LABEL (in_rtx)) == SIMPLE_RETURN)
++	      fprintf (outfile, "simple_return");
++	    else
++	      fprintf (outfile, "%d", INSN_UID (JUMP_LABEL (in_rtx)));
++	  }
+ 	else if (i == 0 && GET_CODE (in_rtx) == VALUE)
+ 	  {
+ #ifndef GENERATOR_FILE
+Index: gcc-4_5-branch/gcc/reorg.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/reorg.c
++++ gcc-4_5-branch/gcc/reorg.c
+@@ -161,8 +161,11 @@ static rtx *unfilled_firstobj;
+ #define unfilled_slots_next	\
+   ((rtx *) obstack_next_free (&unfilled_slots_obstack))
+ 
+-/* Points to the label before the end of the function.  */
+-static rtx end_of_function_label;
++/* Points to the label before the end of the function, or before a
++   return insn.  */
++static rtx function_return_label;
++/* Likewise for a simple_return.  */
++static rtx function_simple_return_label;
+ 
+ /* Mapping between INSN_UID's and position in the code since INSN_UID's do
+    not always monotonically increase.  */
+@@ -175,7 +178,7 @@ static int stop_search_p (rtx, int);
+ static int resource_conflicts_p (struct resources *, struct resources *);
+ static int insn_references_resource_p (rtx, struct resources *, bool);
+ static int insn_sets_resource_p (rtx, struct resources *, bool);
+-static rtx find_end_label (void);
++static rtx find_end_label (rtx);
+ static rtx emit_delay_sequence (rtx, rtx, int);
+ static rtx add_to_delay_list (rtx, rtx);
+ static rtx delete_from_delay_slot (rtx);
+@@ -220,6 +223,15 @@ static void relax_delay_slots (rtx);
+ static void make_return_insns (rtx);
+ #endif
+ 
++/* Return true iff INSN is a simplejump, or any kind of return insn.  */
++
++static bool
++simplejump_or_return_p (rtx insn)
++{
++  return (JUMP_P (insn)
++	  && (simplejump_p (insn) || ANY_RETURN_P (PATTERN (insn))));
++}
++
+ /* Return TRUE if this insn should stop the search for insn to fill delay
+    slots.  LABELS_P indicates that labels should terminate the search.
+    In all cases, jumps terminate the search.  */
+@@ -335,23 +347,29 @@ insn_sets_resource_p (rtx insn, struct r
+ 
+    ??? There may be a problem with the current implementation.  Suppose
+    we start with a bare RETURN insn and call find_end_label.  It may set
+-   end_of_function_label just before the RETURN.  Suppose the machinery
++   function_return_label just before the RETURN.  Suppose the machinery
+    is able to fill the delay slot of the RETURN insn afterwards.  Then
+-   end_of_function_label is no longer valid according to the property
++   function_return_label is no longer valid according to the property
+    described above and find_end_label will still return it unmodified.
+    Note that this is probably mitigated by the following observation:
+-   once end_of_function_label is made, it is very likely the target of
++   once function_return_label is made, it is very likely the target of
+    a jump, so filling the delay slot of the RETURN will be much more
+    difficult.  */
+ 
+ static rtx
+-find_end_label (void)
++find_end_label (rtx kind)
+ {
+   rtx insn;
++  rtx *plabel;
++
++  if (kind == ret_rtx)
++    plabel = &function_return_label;
++  else
++    plabel = &function_simple_return_label;
+ 
+   /* If we found one previously, return it.  */
+-  if (end_of_function_label)
+-    return end_of_function_label;
++  if (*plabel)
++    return *plabel;
+ 
+   /* Otherwise, see if there is a label at the end of the function.  If there
+      is, it must be that RETURN insns aren't needed, so that is our return
+@@ -366,44 +384,44 @@ find_end_label (void)
+ 
+   /* When a target threads its epilogue we might already have a
+      suitable return insn.  If so put a label before it for the
+-     end_of_function_label.  */
++     function_return_label.  */
+   if (BARRIER_P (insn)
+       && JUMP_P (PREV_INSN (insn))
+-      && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN)
++      && PATTERN (PREV_INSN (insn)) == kind)
+     {
+       rtx temp = PREV_INSN (PREV_INSN (insn));
+-      end_of_function_label = gen_label_rtx ();
+-      LABEL_NUSES (end_of_function_label) = 0;
++      rtx label = gen_label_rtx ();
++      LABEL_NUSES (label) = 0;
+ 
+       /* Put the label before an USE insns that may precede the RETURN insn.  */
+       while (GET_CODE (temp) == USE)
+ 	temp = PREV_INSN (temp);
+ 
+-      emit_label_after (end_of_function_label, temp);
++      emit_label_after (label, temp);
++      *plabel = label;
+     }
+ 
+   else if (LABEL_P (insn))
+-    end_of_function_label = insn;
++    *plabel = insn;
+   else
+     {
+-      end_of_function_label = gen_label_rtx ();
+-      LABEL_NUSES (end_of_function_label) = 0;
++      rtx label = gen_label_rtx ();
++      LABEL_NUSES (label) = 0;
+       /* If the basic block reorder pass moves the return insn to
+ 	 some other place try to locate it again and put our
+-	 end_of_function_label there.  */
+-      while (insn && ! (JUMP_P (insn)
+-		        && (GET_CODE (PATTERN (insn)) == RETURN)))
++	 function_return_label there.  */
++      while (insn && ! (JUMP_P (insn) && (PATTERN (insn) == kind)))
+ 	insn = PREV_INSN (insn);
+       if (insn)
+ 	{
+ 	  insn = PREV_INSN (insn);
+ 
+-	  /* Put the label before an USE insns that may proceed the
++	  /* Put the label before an USE insns that may precede the
+ 	     RETURN insn.  */
+ 	  while (GET_CODE (insn) == USE)
+ 	    insn = PREV_INSN (insn);
+ 
+-	  emit_label_after (end_of_function_label, insn);
++	  emit_label_after (label, insn);
+ 	}
+       else
+ 	{
+@@ -413,19 +431,16 @@ find_end_label (void)
+ 	      && ! HAVE_return
+ #endif
+ 	      )
+-	    {
+-	      /* The RETURN insn has its delay slot filled so we cannot
+-		 emit the label just before it.  Since we already have
+-		 an epilogue and cannot emit a new RETURN, we cannot
+-		 emit the label at all.  */
+-	      end_of_function_label = NULL_RTX;
+-	      return end_of_function_label;
+-	    }
++	    /* The RETURN insn has its delay slot filled so we cannot
++	       emit the label just before it.  Since we already have
++	       an epilogue and cannot emit a new RETURN, we cannot
++	       emit the label at all.  */
++	    return NULL_RTX;
+ #endif /* HAVE_epilogue */
+ 
+ 	  /* Otherwise, make a new label and emit a RETURN and BARRIER,
+ 	     if needed.  */
+-	  emit_label (end_of_function_label);
++	  emit_label (label);
+ #ifdef HAVE_return
+ 	  /* We don't bother trying to create a return insn if the
+ 	     epilogue has filled delay-slots; we would have to try and
+@@ -437,19 +452,21 @@ find_end_label (void)
+ 	      /* The return we make may have delay slots too.  */
+ 	      rtx insn = gen_return ();
+ 	      insn = emit_jump_insn (insn);
++	      JUMP_LABEL (insn) = ret_rtx;
+ 	      emit_barrier ();
+ 	      if (num_delay_slots (insn) > 0)
+ 		obstack_ptr_grow (&unfilled_slots_obstack, insn);
+ 	    }
+ #endif
+ 	}
++      *plabel = label;
+     }
+ 
+   /* Show one additional use for this label so it won't go away until
+      we are done.  */
+-  ++LABEL_NUSES (end_of_function_label);
++  ++LABEL_NUSES (*plabel);
+ 
+-  return end_of_function_label;
++  return *plabel;
+ }
+ 
+ /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
+@@ -797,10 +814,8 @@ optimize_skip (rtx insn)
+   if ((next_trial == next_active_insn (JUMP_LABEL (insn))
+        && ! (next_trial == 0 && crtl->epilogue_delay_list != 0))
+       || (next_trial != 0
+-	  && JUMP_P (next_trial)
+-	  && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)
+-	  && (simplejump_p (next_trial)
+-	      || GET_CODE (PATTERN (next_trial)) == RETURN)))
++	  && simplejump_or_return_p (next_trial)
++	  && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)))
+     {
+       if (eligible_for_annul_false (insn, 0, trial, flags))
+ 	{
+@@ -819,13 +834,11 @@ optimize_skip (rtx insn)
+ 	 branch, thread our jump to the target of that branch.  Don't
+ 	 change this into a RETURN here, because it may not accept what
+ 	 we have in the delay slot.  We'll fix this up later.  */
+-      if (next_trial && JUMP_P (next_trial)
+-	  && (simplejump_p (next_trial)
+-	      || GET_CODE (PATTERN (next_trial)) == RETURN))
++      if (next_trial && simplejump_or_return_p (next_trial))
+ 	{
+ 	  rtx target_label = JUMP_LABEL (next_trial);
+-	  if (target_label == 0)
+-	    target_label = find_end_label ();
++	  if (ANY_RETURN_P (target_label))
++	    target_label = find_end_label (target_label);
+ 
+ 	  if (target_label)
+ 	    {
+@@ -866,7 +879,7 @@ get_jump_flags (rtx insn, rtx label)
+   if (JUMP_P (insn)
+       && (condjump_p (insn) || condjump_in_parallel_p (insn))
+       && INSN_UID (insn) <= max_uid
+-      && label != 0
++      && label != 0 && !ANY_RETURN_P (label)
+       && INSN_UID (label) <= max_uid)
+     flags
+       = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
+@@ -1038,7 +1051,7 @@ get_branch_condition (rtx insn, rtx targ
+     pat = XVECEXP (pat, 0, 0);
+ 
+   if (GET_CODE (pat) == RETURN)
+-    return target == 0 ? const_true_rtx : 0;
++    return ANY_RETURN_P (target) ? const_true_rtx : 0;
+ 
+   else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
+     return 0;
+@@ -1318,7 +1331,11 @@ steal_delay_list_from_target (rtx insn, 
+     }
+ 
+   /* Show the place to which we will be branching.  */
+-  *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
++  temp = JUMP_LABEL (XVECEXP (seq, 0, 0));
++  if (ANY_RETURN_P (temp))
++    *pnew_thread = temp;
++  else
++    *pnew_thread = next_active_insn (temp);
+ 
+   /* Add any new insns to the delay list and update the count of the
+      number of slots filled.  */
+@@ -1358,8 +1375,7 @@ steal_delay_list_from_fallthrough (rtx i
+   /* We can't do anything if SEQ's delay insn isn't an
+      unconditional branch.  */
+ 
+-  if (! simplejump_p (XVECEXP (seq, 0, 0))
+-      && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN)
++  if (! simplejump_or_return_p (XVECEXP (seq, 0, 0)))
+     return delay_list;
+ 
+   for (i = 1; i < XVECLEN (seq, 0); i++)
+@@ -1827,7 +1843,7 @@ own_thread_p (rtx thread, rtx label, int
+   rtx insn;
+ 
+   /* We don't own the function end.  */
+-  if (thread == 0)
++  if (ANY_RETURN_P (thread))
+     return 0;
+ 
+   /* Get the first active insn, or THREAD, if it is an active insn.  */
+@@ -2245,7 +2261,8 @@ fill_simple_delay_slots (int non_jumps_p
+ 	  && (!JUMP_P (insn)
+ 	      || ((condjump_p (insn) || condjump_in_parallel_p (insn))
+ 		  && ! simplejump_p (insn)
+-		  && JUMP_LABEL (insn) != 0)))
++		  && JUMP_LABEL (insn) != 0
++		  && !ANY_RETURN_P (JUMP_LABEL (insn)))))
+ 	{
+ 	  /* Invariant: If insn is a JUMP_INSN, the insn's jump
+ 	     label.  Otherwise, zero.  */
+@@ -2270,7 +2287,7 @@ fill_simple_delay_slots (int non_jumps_p
+ 		target = JUMP_LABEL (insn);
+ 	    }
+ 
+-	  if (target == 0)
++	  if (target == 0 || ANY_RETURN_P (target))
+ 	    for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
+ 	      {
+ 		next_trial = next_nonnote_insn (trial);
+@@ -2349,6 +2366,7 @@ fill_simple_delay_slots (int non_jumps_p
+ 	      && JUMP_P (trial)
+ 	      && simplejump_p (trial)
+ 	      && (target == 0 || JUMP_LABEL (trial) == target)
++	      && !ANY_RETURN_P (JUMP_LABEL (trial))
+ 	      && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
+ 	      && ! (NONJUMP_INSN_P (next_trial)
+ 		    && GET_CODE (PATTERN (next_trial)) == SEQUENCE)
+@@ -2371,7 +2389,7 @@ fill_simple_delay_slots (int non_jumps_p
+ 	      if (new_label != 0)
+ 		new_label = get_label_before (new_label);
+ 	      else
+-		new_label = find_end_label ();
++		new_label = find_end_label (simple_return_rtx);
+ 
+ 	      if (new_label)
+ 	        {
+@@ -2503,7 +2521,8 @@ fill_simple_delay_slots (int non_jumps_p
+ 
+ /* Follow any unconditional jump at LABEL;
+    return the ultimate label reached by any such chain of jumps.
+-   Return null if the chain ultimately leads to a return instruction.
++   Return a suitable return rtx if the chain ultimately leads to a
++   return instruction.
+    If LABEL is not followed by a jump, return LABEL.
+    If the chain loops or we can't find end, return LABEL,
+    since that tells caller to avoid changing the insn.  */
+@@ -2518,6 +2537,7 @@ follow_jumps (rtx label)
+ 
+   for (depth = 0;
+        (depth < 10
++	&& !ANY_RETURN_P (value)
+ 	&& (insn = next_active_insn (value)) != 0
+ 	&& JUMP_P (insn)
+ 	&& ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn)
+@@ -2527,18 +2547,22 @@ follow_jumps (rtx label)
+ 	&& BARRIER_P (next));
+        depth++)
+     {
+-      rtx tem;
++      rtx this_label = JUMP_LABEL (insn);
+ 
+       /* If we have found a cycle, make the insn jump to itself.  */
+-      if (JUMP_LABEL (insn) == label)
++      if (this_label == label)
+ 	return label;
+ 
+-      tem = next_active_insn (JUMP_LABEL (insn));
+-      if (tem && (GET_CODE (PATTERN (tem)) == ADDR_VEC
++      if (!ANY_RETURN_P (this_label))
++	{
++	  rtx tem = next_active_insn (this_label);
++	  if (tem
++	      && (GET_CODE (PATTERN (tem)) == ADDR_VEC
+ 		  || GET_CODE (PATTERN (tem)) == ADDR_DIFF_VEC))
+-	break;
++	    break;
++	}
+ 
+-      value = JUMP_LABEL (insn);
++      value = this_label;
+     }
+   if (depth == 10)
+     return label;
+@@ -2901,6 +2925,7 @@ fill_slots_from_thread (rtx insn, rtx co
+      arithmetic insn after the jump insn and put the arithmetic insn in the
+      delay slot.  If we can't do this, return.  */
+   if (delay_list == 0 && likely && new_thread
++      && !ANY_RETURN_P (new_thread)
+       && NONJUMP_INSN_P (new_thread)
+       && GET_CODE (PATTERN (new_thread)) != ASM_INPUT
+       && asm_noperands (PATTERN (new_thread)) < 0)
+@@ -2985,16 +3010,14 @@ fill_slots_from_thread (rtx insn, rtx co
+ 
+       gcc_assert (thread_if_true);
+ 
+-      if (new_thread && JUMP_P (new_thread)
+-	  && (simplejump_p (new_thread)
+-	      || GET_CODE (PATTERN (new_thread)) == RETURN)
++      if (new_thread && simplejump_or_return_p (new_thread)
+ 	  && redirect_with_delay_list_safe_p (insn,
+ 					      JUMP_LABEL (new_thread),
+ 					      delay_list))
+ 	new_thread = follow_jumps (JUMP_LABEL (new_thread));
+ 
+-      if (new_thread == 0)
+-	label = find_end_label ();
++      if (ANY_RETURN_P (new_thread))
++	label = find_end_label (new_thread);
+       else if (LABEL_P (new_thread))
+ 	label = new_thread;
+       else
+@@ -3340,11 +3363,12 @@ relax_delay_slots (rtx first)
+ 	 group of consecutive labels.  */
+       if (JUMP_P (insn)
+ 	  && (condjump_p (insn) || condjump_in_parallel_p (insn))
+-	  && (target_label = JUMP_LABEL (insn)) != 0)
++	  && (target_label = JUMP_LABEL (insn)) != 0
++	  && !ANY_RETURN_P (target_label))
+ 	{
+ 	  target_label = skip_consecutive_labels (follow_jumps (target_label));
+-	  if (target_label == 0)
+-	    target_label = find_end_label ();
++	  if (ANY_RETURN_P (target_label))
++	    target_label = find_end_label (target_label);
+ 
+ 	  if (target_label && next_active_insn (target_label) == next
+ 	      && ! condjump_in_parallel_p (insn))
+@@ -3359,9 +3383,8 @@ relax_delay_slots (rtx first)
+ 	  /* See if this jump conditionally branches around an unconditional
+ 	     jump.  If so, invert this jump and point it to the target of the
+ 	     second jump.  */
+-	  if (next && JUMP_P (next)
++	  if (next && simplejump_or_return_p (next)
+ 	      && any_condjump_p (insn)
+-	      && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
+ 	      && target_label
+ 	      && next_active_insn (target_label) == next_active_insn (next)
+ 	      && no_labels_between_p (insn, next))
+@@ -3403,8 +3426,7 @@ relax_delay_slots (rtx first)
+ 	 Don't do this if we expect the conditional branch to be true, because
+ 	 we would then be making the more common case longer.  */
+ 
+-      if (JUMP_P (insn)
+-	  && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
++      if (simplejump_or_return_p (insn)
+ 	  && (other = prev_active_insn (insn)) != 0
+ 	  && any_condjump_p (other)
+ 	  && no_labels_between_p (other, insn)
+@@ -3445,10 +3467,10 @@ relax_delay_slots (rtx first)
+ 	 Only do so if optimizing for size since this results in slower, but
+ 	 smaller code.  */
+       if (optimize_function_for_size_p (cfun)
+-	  && GET_CODE (PATTERN (delay_insn)) == RETURN
++	  && ANY_RETURN_P (PATTERN (delay_insn))
+ 	  && next
+ 	  && JUMP_P (next)
+-	  && GET_CODE (PATTERN (next)) == RETURN)
++	  && PATTERN (next) == PATTERN (delay_insn))
+ 	{
+ 	  rtx after;
+ 	  int i;
+@@ -3487,14 +3509,16 @@ relax_delay_slots (rtx first)
+ 	continue;
+ 
+       target_label = JUMP_LABEL (delay_insn);
++      if (target_label && ANY_RETURN_P (target_label))
++	continue;
+ 
+       if (target_label)
+ 	{
+ 	  /* If this jump goes to another unconditional jump, thread it, but
+ 	     don't convert a jump into a RETURN here.  */
+ 	  trial = skip_consecutive_labels (follow_jumps (target_label));
+-	  if (trial == 0)
+-	    trial = find_end_label ();
++	  if (ANY_RETURN_P (trial))
++	    trial = find_end_label (trial);
+ 
+ 	  if (trial && trial != target_label
+ 	      && redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
+@@ -3517,7 +3541,7 @@ relax_delay_slots (rtx first)
+ 		 later incorrectly compute register live/death info.  */
+ 	      rtx tmp = next_active_insn (trial);
+ 	      if (tmp == 0)
+-		tmp = find_end_label ();
++		tmp = find_end_label (simple_return_rtx);
+ 
+ 	      if (tmp)
+ 	        {
+@@ -3537,14 +3561,12 @@ relax_delay_slots (rtx first)
+ 	     delay list and that insn is redundant, thread the jump.  */
+ 	  if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
+ 	      && XVECLEN (PATTERN (trial), 0) == 2
+-	      && JUMP_P (XVECEXP (PATTERN (trial), 0, 0))
+-	      && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0))
+-		  || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN)
++	      && simplejump_or_return_p (XVECEXP (PATTERN (trial), 0, 0))
+ 	      && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0))
+ 	    {
+ 	      target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0));
+-	      if (target_label == 0)
+-		target_label = find_end_label ();
++	      if (ANY_RETURN_P (target_label))
++		target_label = find_end_label (target_label);
+ 
+ 	      if (target_label
+ 	          && redirect_with_delay_slots_safe_p (delay_insn, target_label,
+@@ -3622,16 +3644,15 @@ relax_delay_slots (rtx first)
+ 	 a RETURN here.  */
+       if (! INSN_ANNULLED_BRANCH_P (delay_insn)
+ 	  && any_condjump_p (delay_insn)
+-	  && next && JUMP_P (next)
+-	  && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
++	  && next && simplejump_or_return_p (next)
+ 	  && next_active_insn (target_label) == next_active_insn (next)
+ 	  && no_labels_between_p (insn, next))
+ 	{
+ 	  rtx label = JUMP_LABEL (next);
+ 	  rtx old_label = JUMP_LABEL (delay_insn);
+ 
+-	  if (label == 0)
+-	    label = find_end_label ();
++	  if (ANY_RETURN_P (label))
++	    label = find_end_label (label);
+ 
+ 	  /* find_end_label can generate a new label. Check this first.  */
+ 	  if (label
+@@ -3692,7 +3713,8 @@ static void
+ make_return_insns (rtx first)
+ {
+   rtx insn, jump_insn, pat;
+-  rtx real_return_label = end_of_function_label;
++  rtx real_return_label = function_return_label;
++  rtx real_simple_return_label = function_simple_return_label;
+   int slots, i;
+ 
+ #ifdef DELAY_SLOTS_FOR_EPILOGUE
+@@ -3707,18 +3729,25 @@ make_return_insns (rtx first)
+ #endif
+ 
+   /* See if there is a RETURN insn in the function other than the one we
+-     made for END_OF_FUNCTION_LABEL.  If so, set up anything we can't change
++     made for FUNCTION_RETURN_LABEL.  If so, set up anything we can't change
+      into a RETURN to jump to it.  */
+   for (insn = first; insn; insn = NEXT_INSN (insn))
+-    if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN)
++    if (JUMP_P (insn) && ANY_RETURN_P (PATTERN (insn)))
+       {
+-	real_return_label = get_label_before (insn);
++	rtx t = get_label_before (insn);
++	if (PATTERN (insn) == ret_rtx)
++	  real_return_label = t;
++	else
++	  real_simple_return_label = t;
+ 	break;
+       }
+ 
+   /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
+-     was equal to END_OF_FUNCTION_LABEL.  */
+-  LABEL_NUSES (real_return_label)++;
++     was equal to FUNCTION_RETURN_LABEL.  */
++  if (real_return_label)
++    LABEL_NUSES (real_return_label)++;
++  if (real_simple_return_label)
++    LABEL_NUSES (real_simple_return_label)++;
+ 
+   /* Clear the list of insns to fill so we can use it.  */
+   obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
+@@ -3726,13 +3755,27 @@ make_return_insns (rtx first)
+   for (insn = first; insn; insn = NEXT_INSN (insn))
+     {
+       int flags;
++      rtx kind, real_label;
+ 
+       /* Only look at filled JUMP_INSNs that go to the end of function
+ 	 label.  */
+       if (!NONJUMP_INSN_P (insn)
+ 	  || GET_CODE (PATTERN (insn)) != SEQUENCE
+-	  || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0))
+-	  || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label)
++	  || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0)))
++	continue;
++
++      if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) == function_return_label)
++	{
++	  kind = ret_rtx;
++	  real_label = real_return_label;
++	}
++      else if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0))
++	       == function_simple_return_label)
++	{
++	  kind = simple_return_rtx;
++	  real_label = real_simple_return_label;
++	}
++      else
+ 	continue;
+ 
+       pat = PATTERN (insn);
+@@ -3740,14 +3783,12 @@ make_return_insns (rtx first)
+ 
+       /* If we can't make the jump into a RETURN, try to redirect it to the best
+ 	 RETURN and go on to the next insn.  */
+-      if (! reorg_redirect_jump (jump_insn, NULL_RTX))
++      if (! reorg_redirect_jump (jump_insn, kind))
+ 	{
+ 	  /* Make sure redirecting the jump will not invalidate the delay
+ 	     slot insns.  */
+-	  if (redirect_with_delay_slots_safe_p (jump_insn,
+-						real_return_label,
+-						insn))
+-	    reorg_redirect_jump (jump_insn, real_return_label);
++	  if (redirect_with_delay_slots_safe_p (jump_insn, real_label, insn))
++	    reorg_redirect_jump (jump_insn, real_label);
+ 	  continue;
+ 	}
+ 
+@@ -3787,7 +3828,7 @@ make_return_insns (rtx first)
+ 	 RETURN, delete the SEQUENCE and output the individual insns,
+ 	 followed by the RETURN.  Then set things up so we try to find
+ 	 insns for its delay slots, if it needs some.  */
+-      if (GET_CODE (PATTERN (jump_insn)) == RETURN)
++      if (ANY_RETURN_P (PATTERN (jump_insn)))
+ 	{
+ 	  rtx prev = PREV_INSN (insn);
+ 
+@@ -3804,13 +3845,16 @@ make_return_insns (rtx first)
+       else
+ 	/* It is probably more efficient to keep this with its current
+ 	   delay slot as a branch to a RETURN.  */
+-	reorg_redirect_jump (jump_insn, real_return_label);
++	reorg_redirect_jump (jump_insn, real_label);
+     }
+ 
+   /* Now delete REAL_RETURN_LABEL if we never used it.  Then try to fill any
+      new delay slots we have created.  */
+-  if (--LABEL_NUSES (real_return_label) == 0)
++  if (real_return_label != NULL_RTX && --LABEL_NUSES (real_return_label) == 0)
+     delete_related_insns (real_return_label);
++  if (real_simple_return_label != NULL_RTX
++      && --LABEL_NUSES (real_simple_return_label) == 0)
++    delete_related_insns (real_simple_return_label);
+ 
+   fill_simple_delay_slots (1);
+   fill_simple_delay_slots (0);
+@@ -3878,7 +3922,7 @@ dbr_schedule (rtx first)
+   init_resource_info (epilogue_insn);
+ 
+   /* Show we haven't computed an end-of-function label yet.  */
+-  end_of_function_label = 0;
++  function_return_label = function_simple_return_label = NULL_RTX;
+ 
+   /* Initialize the statistics for this function.  */
+   memset (num_insns_needing_delays, 0, sizeof num_insns_needing_delays);
+@@ -3900,11 +3944,23 @@ dbr_schedule (rtx first)
+   /* If we made an end of function label, indicate that it is now
+      safe to delete it by undoing our prior adjustment to LABEL_NUSES.
+      If it is now unused, delete it.  */
+-  if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0)
+-    delete_related_insns (end_of_function_label);
++  if (function_return_label && --LABEL_NUSES (function_return_label) == 0)
++    delete_related_insns (function_return_label);
++  if (function_simple_return_label
++      && --LABEL_NUSES (function_simple_return_label) == 0)
++    delete_related_insns (function_simple_return_label);
+ 
++#if defined HAVE_return || defined HAVE_simple_return
++  if (
+ #ifdef HAVE_return
+-  if (HAVE_return && end_of_function_label != 0)
++      (HAVE_return && function_return_label != 0)
++#else
++      0
++#endif
++#ifdef HAVE_simple_return
++      || (HAVE_simple_return && function_simple_return_label != 0)
++#endif
++      )
+     make_return_insns (first);
+ #endif
+ 
+Index: gcc-4_5-branch/gcc/resource.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/resource.c
++++ gcc-4_5-branch/gcc/resource.c
+@@ -495,6 +495,8 @@ find_dead_or_set_registers (rtx target, 
+ 		  || GET_CODE (PATTERN (this_jump_insn)) == RETURN)
+ 		{
+ 		  next = JUMP_LABEL (this_jump_insn);
++		  if (next && ANY_RETURN_P (next))
++		    next = NULL_RTX;
+ 		  if (jump_insn == 0)
+ 		    {
+ 		      jump_insn = insn;
+@@ -562,9 +564,10 @@ find_dead_or_set_registers (rtx target, 
+ 		  AND_COMPL_HARD_REG_SET (scratch, needed.regs);
+ 		  AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch);
+ 
+-		  find_dead_or_set_registers (JUMP_LABEL (this_jump_insn),
+-					      &target_res, 0, jump_count,
+-					      target_set, needed);
++		  if (!ANY_RETURN_P (JUMP_LABEL (this_jump_insn)))
++		    find_dead_or_set_registers (JUMP_LABEL (this_jump_insn),
++						&target_res, 0, jump_count,
++						target_set, needed);
+ 		  find_dead_or_set_registers (next,
+ 					      &fallthrough_res, 0, jump_count,
+ 					      set, needed);
+@@ -1097,6 +1100,8 @@ mark_target_live_regs (rtx insns, rtx ta
+       struct resources new_resources;
+       rtx stop_insn = next_active_insn (jump_insn);
+ 
++      if (jump_target && ANY_RETURN_P (jump_target))
++	jump_target = NULL_RTX;
+       mark_target_live_regs (insns, next_active_insn (jump_target),
+ 			     &new_resources);
+       CLEAR_RESOURCE (&set);
+Index: gcc-4_5-branch/gcc/rtl.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/rtl.c
++++ gcc-4_5-branch/gcc/rtl.c
+@@ -256,6 +256,8 @@ copy_rtx (rtx orig)
+     case CODE_LABEL:
+     case PC:
+     case CC0:
++    case RETURN:
++    case SIMPLE_RETURN:
+     case SCRATCH:
+       /* SCRATCH must be shared because they represent distinct values.  */
+       return orig;
+Index: gcc-4_5-branch/gcc/rtl.def
+===================================================================
+--- gcc-4_5-branch.orig/gcc/rtl.def
++++ gcc-4_5-branch/gcc/rtl.def
+@@ -296,6 +296,10 @@ DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXT
+ 
+ DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
+ 
++/* A plain return, to be used on paths that are reached without going
++   through the function prologue.  */
++DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
++
+ /* Special for EH return from subroutine.  */
+ 
+ DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
+Index: gcc-4_5-branch/gcc/rtl.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/rtl.h
++++ gcc-4_5-branch/gcc/rtl.h
+@@ -411,6 +411,10 @@ struct GTY(()) rtvec_def {
+   (JUMP_P (INSN) && (GET_CODE (PATTERN (INSN)) == ADDR_VEC || \
+ 		     GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC))
+ 
++/* Predicate yielding nonzero iff X is a return or simple_preturn.  */
++#define ANY_RETURN_P(X) \
++  (GET_CODE (X) == RETURN || GET_CODE (X) == SIMPLE_RETURN)
++
+ /* 1 if X is a unary operator.  */
+ 
+ #define UNARY_P(X)   \
+@@ -1998,6 +2002,8 @@ enum global_rtl_index
+ {
+   GR_PC,
+   GR_CC0,
++  GR_RETURN,
++  GR_SIMPLE_RETURN,
+   GR_STACK_POINTER,
+   GR_FRAME_POINTER,
+ /* For register elimination to work properly these hard_frame_pointer_rtx,
+@@ -2032,6 +2038,8 @@ extern GTY(()) rtx global_rtl[GR_MAX];
+ 
+ /* Standard pieces of rtx, to be substituted directly into things.  */
+ #define pc_rtx                  (global_rtl[GR_PC])
++#define ret_rtx                 (global_rtl[GR_RETURN])
++#define simple_return_rtx       (global_rtl[GR_SIMPLE_RETURN])
+ #define cc0_rtx                 (global_rtl[GR_CC0])
+ 
+ /* All references to certain hard regs, except those created
+Index: gcc-4_5-branch/gcc/rtlanal.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/rtlanal.c
++++ gcc-4_5-branch/gcc/rtlanal.c
+@@ -2673,6 +2673,7 @@ tablejump_p (const_rtx insn, rtx *labelp
+ 
+   if (JUMP_P (insn)
+       && (label = JUMP_LABEL (insn)) != NULL_RTX
++      && !ANY_RETURN_P (label)
+       && (table = next_active_insn (label)) != NULL_RTX
+       && JUMP_TABLE_DATA_P (table))
+     {
+Index: gcc-4_5-branch/gcc/sched-int.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/sched-int.h
++++ gcc-4_5-branch/gcc/sched-int.h
+@@ -199,7 +199,7 @@ extern int max_issue (struct ready_list 
+ 
+ extern void ebb_compute_jump_reg_dependencies (rtx, regset, regset, regset);
+ 
+-extern edge find_fallthru_edge (basic_block);
++extern edge find_fallthru_edge_from (basic_block);
+ 
+ extern void (* sched_init_only_bb) (basic_block, basic_block);
+ extern basic_block (* sched_split_block) (basic_block, rtx);
+Index: gcc-4_5-branch/gcc/sched-vis.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/sched-vis.c
++++ gcc-4_5-branch/gcc/sched-vis.c
+@@ -549,6 +549,9 @@ print_pattern (char *buf, const_rtx x, i
+     case RETURN:
+       sprintf (buf, "return");
+       break;
++    case SIMPLE_RETURN:
++      sprintf (buf, "simple_return");
++      break;
+     case CALL:
+       print_exp (buf, x, verbose);
+       break;
+Index: gcc-4_5-branch/gcc/sel-sched-ir.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/sel-sched-ir.c
++++ gcc-4_5-branch/gcc/sel-sched-ir.c
+@@ -686,7 +686,7 @@ merge_fences (fence_t f, insn_t insn,
+ 
+       /* Find fallthrough edge.  */
+       gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb);
+-      candidate = find_fallthru_edge (BLOCK_FOR_INSN (insn)->prev_bb);
++      candidate = find_fallthru_edge_from (BLOCK_FOR_INSN (insn)->prev_bb);
+ 
+       if (!candidate
+           || (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn)
+Index: gcc-4_5-branch/gcc/sel-sched.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/sel-sched.c
++++ gcc-4_5-branch/gcc/sel-sched.c
+@@ -617,8 +617,8 @@ in_fallthru_bb_p (rtx insn, rtx succ)
+   if (bb == BLOCK_FOR_INSN (succ))
+     return true;
+ 
+-  if (find_fallthru_edge (bb))
+-    bb = find_fallthru_edge (bb)->dest;
++  if (find_fallthru_edge_from (bb))
++    bb = find_fallthru_edge_from (bb)->dest;
+   else
+     return false;
+ 
+@@ -4911,7 +4911,7 @@ move_cond_jump (rtx insn, bnd_t bnd)
+   next = PREV_INSN (insn);
+   BND_TO (bnd) = insn;
+ 
+-  ft_edge = find_fallthru_edge (block_from);
++  ft_edge = find_fallthru_edge_from (block_from);
+   block_next = ft_edge->dest;
+   /* There must be a fallthrough block (or where should go
+   control flow in case of false jump predicate otherwise?).  */
+Index: gcc-4_5-branch/gcc/vec.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/vec.h
++++ gcc-4_5-branch/gcc/vec.h
+@@ -188,6 +188,18 @@ along with GCC; see the file COPYING3.  
+ 
+ #define VEC_iterate(T,V,I,P)	(VEC_OP(T,base,iterate)(VEC_BASE(V),I,&(P)))
+ 
++/* Convenience macro for forward iteration.  */
++
++#define FOR_EACH_VEC_ELT(T, V, I, P)		\
++  for (I = 0; VEC_iterate (T, (V), (I), (P)); ++(I))
++
++/* Convenience macro for reverse iteration.  */
++
++#define FOR_EACH_VEC_ELT_REVERSE(T,V,I,P) \
++  for (I = VEC_length (T, (V)) - 1;           \
++       VEC_iterate (T, (V), (I), (P));	  \
++       (I)--)
++
+ /* Allocate new vector.
+    VEC(T,A) *VEC_T_A_alloc(int reserve);
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
new file mode 100644
index 0000000000..337b055805
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
@@ -0,0 +1,4075 @@
+2011-02-08  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2010-06-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/44721
+	* config/i386/i386.md (peephole2 for arithmetic ops with memory):
+	Fix last commit.
+
+	2010-06-30  Richard Guenther  <rguenther@suse.de>
+
+	PR target/44722
+	* config/i386/i386.md (peephole2 for fix:SSEMODEI24): Guard
+	against oscillation with reverse peephole2.
+
+	2010-07-01  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/44727
+	* config/i386/i386.md (peephole2 for arithmetic ops with memory):
+	Make sure operand 0 dies.
+
+2010-12-03  Yao Qi  <yao@codesourcery.com>
+
+	* config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix
+	regressions.
+	* config/arm/ldmstm.md: Regenreate.
+
+2010-12-03  Yao Qi  <yao@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2010-08-02  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR target/40457
+	* config/arm/arm.h (arm_regs_in_sequence): Declare.
+	* config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq,
+	load_multiple_sequence, store_multiple_sequence): Delete
+	declarations.
+	(arm_gen_load_multiple, arm_gen_store_multiple): Adjust
+	declarations.
+	* config/arm/ldmstm.md: New file.
+	* config/arm/arm.c (arm_regs_in_sequence): New array.
+	(load_multiple_sequence): Now static.  New args SAVED_ORDER,
+	CHECK_REGS.  All callers changed.
+	If SAVED_ORDER is nonnull, copy the computed order into it.
+	If CHECK_REGS is false, don't sort REGS.  Handle Thumb mode.
+	(store_multiple_sequence): Now static.  New args NOPS_TOTAL,
+	SAVED_ORDER, REG_RTXS and CHECK_REGS.  All callers changed.
+	If SAVED_ORDER is nonnull, copy the computed order into it.
+	If CHECK_REGS is false, don't sort REGS.  Set up REG_RTXS just
+	like REGS.  Handle Thumb mode.
+	(arm_gen_load_multiple_1): New function, broken out of
+	arm_gen_load_multiple.
+	(arm_gen_store_multiple_1): New function, broken out of
+	arm_gen_store_multiple.
+	(arm_gen_multiple_op): New function, with code from
+	arm_gen_load_multiple and arm_gen_store_multiple moved here.
+	(arm_gen_load_multiple, arm_gen_store_multiple): Now just
+	wrappers around arm_gen_multiple_op.  Remove argument UP, all callers
+	changed.
+	(gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions.
+	* config/arm/predicates.md (commutative_binary_operator): New.
+	(load_multiple_operation, store_multiple_operation): Handle more
+	variants of these patterns with different starting offsets.  Handle
+	Thumb-1.
+	* config/arm/arm.md: Include "ldmstm.md".
+	(ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2,
+	ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1,
+	stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related
+	peepholes): Delete.
+	* config/arm/ldmstm.md: New file.
+	* config/arm/arm-ldmstm.ml: New file.
+
+	* config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the
+	if statement which adds extra costs to frame-related expressions.
+
+	2010-05-06  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* config/arm/arm.h (MAX_LDM_STM_OPS): New macro.
+	* config/arm/arm.c (multiple_operation_profitable_p,
+	compute_offset_order): New static functions.
+	(load_multiple_sequence, store_multiple_sequence): Use them.
+	Replace constant 4 with MAX_LDM_STM_OPS.  Compute order[0] from
+	memory offsets, not register numbers.
+	(emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS.
+
+	2010-04-16  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* recog.h (struct recog_data): New field is_operator.
+	(struct insn_operand_data): New field is_operator.
+	* recog.c (extract_insn): Set recog_data.is_operator.
+	* genoutput.c (output_operand_data): Emit code to set the
+	is_operator field.
+	* reload.c (find_reloads): Use it rather than testing for an
+	empty constraint string.
+
+=== added file 'gcc/config/arm/arm-ldmstm.ml'
+Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml	2012-03-06 12:51:19.980547615 -0800
+@@ -0,0 +1,333 @@
++(* Auto-generate ARM ldm/stm patterns
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   Contributed by CodeSourcery.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it under
++   the terms of the GNU General Public License as published by the Free
++   Software Foundation; either version 3, or (at your option) any later
++   version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or
++   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++   for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.
++
++   This is an O'Caml program.  The O'Caml compiler is available from:
++
++     http://caml.inria.fr/
++
++   Or from your favourite OS's friendly packaging system. Tested with version
++   3.09.2, though other versions will probably work too.
++
++   Run with:
++     ocaml arm-ldmstm.ml >/path/to/gcc/config/arm/ldmstm.ml
++*)
++
++type amode = IA | IB | DA | DB
++
++type optype = IN | OUT | INOUT
++
++let rec string_of_addrmode addrmode =
++  match addrmode with
++    IA -> "ia" | IB -> "ib" | DA -> "da" | DB -> "db"
++
++let rec initial_offset addrmode nregs =
++  match addrmode with
++    IA -> 0
++  | IB -> 4
++  | DA -> -4 * nregs + 4
++  | DB -> -4 * nregs
++
++let rec final_offset addrmode nregs =
++  match addrmode with
++    IA -> nregs * 4
++  | IB -> nregs * 4
++  | DA -> -4 * nregs
++  | DB -> -4 * nregs
++
++let constr thumb =
++  if thumb then "l" else "rk"
++
++let inout_constr op_type =
++  match op_type with
++  OUT -> "="
++  | INOUT -> "+&"
++  | IN -> ""
++
++let destreg nregs first op_type thumb =
++  if not first then
++    Printf.sprintf "(match_dup %d)" (nregs)
++  else
++    Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")")
++    (nregs) (inout_constr op_type) (constr thumb)
++
++let write_ldm_set thumb nregs offset opnr first =
++  let indent = "     " in
++  Printf.printf "%s" (if first then "    [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr;
++  Printf.printf "%s     (mem:SI " indent;
++  begin if offset != 0 then Printf.printf "(plus:SI " end;
++  Printf.printf "%s" (destreg nregs first IN thumb);
++  begin if offset != 0 then Printf.printf "\n%s             (const_int %d))" indent offset end;
++  Printf.printf "))"
++
++let write_stm_set thumb nregs offset opnr first =
++  let indent = "     " in
++  Printf.printf "%s" (if first then "    [" else indent);
++  Printf.printf "(set (mem:SI ";
++  begin if offset != 0 then Printf.printf "(plus:SI " end;
++  Printf.printf "%s" (destreg nregs first IN thumb);
++  begin if offset != 0 then Printf.printf " (const_int %d))" offset end;
++  Printf.printf ")\n%s     (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr 
++
++let write_ldm_peep_set extra_indent nregs opnr first =
++  let indent = "   " ^ extra_indent in
++  Printf.printf "%s" (if first then extra_indent ^ "  [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr;
++  Printf.printf "%s     (match_operand:SI %d \"memory_operand\" \"\"))" indent (nregs + opnr)
++
++let write_stm_peep_set extra_indent nregs opnr first =
++  let indent = "   " ^ extra_indent in
++  Printf.printf "%s" (if first then extra_indent ^ "  [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"memory_operand\" \"\")\n" (nregs + opnr);
++  Printf.printf "%s     (match_operand:SI %d \"s_register_operand\" \"\"))" indent opnr
++
++let write_any_load optype nregs opnr first =
++  let indent = "   " in
++  Printf.printf "%s" (if first then "  [" else indent);
++  Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr;
++  Printf.printf "%s     (match_operand:SI %d \"%s\" \"\"))" indent (nregs * 2 + opnr) optype
++
++let write_const_store nregs opnr first =
++  let indent = "   " in
++  Printf.printf "%s(set (match_operand:SI %d \"memory_operand\" \"\")\n" indent (nregs + opnr);
++  Printf.printf "%s     (match_dup %d))" indent opnr
++
++let write_const_stm_peep_set nregs opnr first =
++  write_any_load "const_int_operand" nregs opnr first;
++  Printf.printf "\n";
++  write_const_store nregs opnr false
++
++  
++let rec write_pat_sets func opnr offset first n_left =
++  func offset opnr first;
++  begin
++    if n_left > 1 then begin
++      Printf.printf "\n";
++      write_pat_sets func (opnr + 1) (offset + 4) false (n_left - 1);
++    end else
++      Printf.printf "]"
++  end
++
++let rec write_peep_sets func opnr first n_left =
++  func opnr first;
++  begin
++    if n_left > 1 then begin
++      Printf.printf "\n";
++      write_peep_sets func (opnr + 1) false (n_left - 1);
++    end
++  end
++    
++let can_thumb addrmode update is_store =
++  match addrmode, update, is_store with
++    (* Thumb1 mode only supports IA with update.  However, for LDMIA,
++       if the address register also appears in the list of loaded
++       registers, the loaded value is stored, hence the RTL pattern
++       to describe such an insn does not have an update.  We check
++       in the match_parallel predicate that the condition described
++       above is met.  *)
++    IA, _, false -> true
++  | IA, true, true -> true
++  | _ -> false
++
++let target addrmode thumb =
++  match addrmode, thumb with
++    IA, true -> "TARGET_THUMB1"
++  | IA, false -> "TARGET_32BIT"
++  | DB, false -> "TARGET_32BIT"
++  | _, false -> "TARGET_ARM"
++
++let write_pattern_1 name ls addrmode nregs write_set_fn update thumb =
++  let astr = string_of_addrmode addrmode in
++  Printf.printf "(define_insn \"*%s%s%d_%s%s\"\n"
++    (if thumb then "thumb_" else "") name nregs astr
++    (if update then "_update" else "");
++  Printf.printf "  [(match_parallel 0 \"%s_multiple_operation\"\n" ls;
++  begin
++    if update then begin
++      Printf.printf "    [(set %s\n          (plus:SI "
++	(destreg 1 true OUT thumb); (*destreg 2 true IN thumb*)
++      Printf.printf "(match_operand:SI 2 \"s_register_operand\" \"1\")";
++      Printf.printf " (const_int %d)))\n"
++	(final_offset addrmode nregs)
++    end
++  end;
++  write_pat_sets
++    (write_set_fn thumb (if update then 2 else 1)) (if update then 3 else 2)
++    (initial_offset addrmode nregs)
++    (not update) nregs;
++  Printf.printf ")]\n  \"%s && XVECLEN (operands[0], 0) == %d\"\n"
++    (target addrmode thumb)
++    (if update then nregs + 1 else nregs);
++  Printf.printf "  \"%s%%(%s%%)\\t%%%d%s, {"
++    name astr (1) (if update then "!" else "");
++  for n = 1 to nregs; do
++    Printf.printf "%%%d%s" (n+(if update then 2 else 1)) (if n < nregs then ", " else "")
++  done;
++  Printf.printf "}\"\n";
++  Printf.printf "  [(set_attr \"type\" \"%s%d\")" ls nregs;
++  begin if not thumb then
++    Printf.printf "\n   (set_attr \"predicable\" \"yes\")";
++  end;
++  Printf.printf "])\n\n"
++
++let write_ldm_pattern addrmode nregs update =
++  write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update false;
++  begin if can_thumb addrmode update false then
++    write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update true;
++  end
++
++let write_stm_pattern addrmode nregs update =
++  write_pattern_1 "stm" "store" addrmode nregs write_stm_set update false;
++  begin if can_thumb addrmode update true then
++    write_pattern_1 "stm" "store" addrmode nregs write_stm_set update true;
++  end
++
++let write_ldm_commutative_peephole thumb =
++  let nregs = 2 in
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs;
++  let indent = "   " in
++  if thumb then begin
++    Printf.printf "\n%s(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2);
++    Printf.printf "%s     (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1);
++    Printf.printf "%s      [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2);
++    Printf.printf "%s       (match_operand:SI %d \"s_register_operand\" \"\")]))]\n" indent (nregs * 2 + 3)
++  end else begin
++    Printf.printf "\n%s(parallel\n" indent;
++    Printf.printf "%s  [(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2);
++    Printf.printf "%s        (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1);
++    Printf.printf "%s         [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2);
++    Printf.printf "%s          (match_operand:SI %d \"s_register_operand\" \"\")]))\n" indent (nregs * 2 + 3);
++    Printf.printf "%s   (clobber (reg:CC CC_REGNUM))])]\n" indent
++  end;
++  Printf.printf "  \"(((operands[%d] == operands[0] && operands[%d] == operands[1])\n" (nregs * 2 + 2) (nregs * 2 + 3);
++  Printf.printf "     || (operands[%d] == operands[0] && operands[%d] == operands[1]))\n" (nregs * 2 + 3) (nregs * 2 + 2);
++  Printf.printf "    && peep2_reg_dead_p (%d, operands[0]) && peep2_reg_dead_p (%d, operands[1]))\"\n" (nregs + 1) (nregs + 1);
++  begin
++    if thumb then
++      Printf.printf "  [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))]\n"
++	(nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3)
++    else begin
++      Printf.printf "  [(parallel\n";
++      Printf.printf "    [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))\n"
++	(nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3);
++      Printf.printf "     (clobber (reg:CC CC_REGNUM))])]\n"
++    end
++  end;
++  Printf.printf "{\n  if (!gen_ldm_seq (operands, %d, true))\n    FAIL;\n" nregs;
++  Printf.printf "})\n\n"
++
++let write_ldm_peephole nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_ldm_seq (operands, %d, false))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let write_ldm_peephole_b nregs =
++  if nregs > 2 then begin
++    Printf.printf "(define_peephole2\n";
++    write_ldm_peep_set "" nregs 0 true;
++    Printf.printf "\n   (parallel\n";
++    write_peep_sets (write_ldm_peep_set "  " nregs) 1 true (nregs - 1);
++    Printf.printf "])]\n  \"\"\n  [(const_int 0)]\n{\n";
++    Printf.printf "  if (gen_ldm_seq (operands, %d, false))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++  end
++
++let write_stm_peephole nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_stm_peep_set "" nregs) 0 true nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let write_stm_peephole_b nregs =
++  if nregs > 2 then begin
++    Printf.printf "(define_peephole2\n";
++    write_stm_peep_set "" nregs 0 true;
++    Printf.printf "\n   (parallel\n";
++    write_peep_sets (write_stm_peep_set "" nregs) 1 true (nregs - 1);
++    Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++    Printf.printf "  if (gen_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++  end
++
++let write_const_stm_peephole_a nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_const_stm_peep_set nregs) 0 true nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_const_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let write_const_stm_peephole_b nregs =
++  Printf.printf "(define_peephole2\n";
++  write_peep_sets (write_any_load "const_int_operand" nregs) 0 true nregs;
++  Printf.printf "\n";
++  write_peep_sets (write_const_store nregs) 0 false nregs;
++  Printf.printf "]\n  \"\"\n  [(const_int 0)]\n{\n";
++  Printf.printf "  if (gen_const_stm_seq (operands, %d))\n    DONE;\n  else\n    FAIL;\n})\n\n" nregs
++
++let patterns () =
++  let addrmodes = [ IA; IB; DA; DB ]  in
++  let sizes = [ 4; 3; 2] in
++  List.iter
++    (fun n ->
++      List.iter
++	(fun addrmode ->
++	  write_ldm_pattern addrmode n false;
++	  write_ldm_pattern addrmode n true;
++	  write_stm_pattern addrmode n false;
++	  write_stm_pattern addrmode n true)
++	addrmodes;
++      write_ldm_peephole n;
++      write_ldm_peephole_b n;
++      write_const_stm_peephole_a n;
++      write_const_stm_peephole_b n;
++      write_stm_peephole n;)
++    sizes;
++  write_ldm_commutative_peephole false;
++  write_ldm_commutative_peephole true
++
++let print_lines = List.iter (fun s -> Format.printf "%s@\n" s)
++
++(* Do it.  *)
++
++let _ = 
++  print_lines [
++"/* ARM ldm/stm instruction patterns.  This file was automatically generated";
++"   using arm-ldmstm.ml.  Please do not edit manually.";
++"";
++"   Copyright (C) 2010 Free Software Foundation, Inc.";
++"   Contributed by CodeSourcery.";
++"";
++"   This file is part of GCC.";
++"";
++"   GCC is free software; you can redistribute it and/or modify it";
++"   under the terms of the GNU General Public License as published";
++"   by the Free Software Foundation; either version 3, or (at your";
++"   option) any later version.";
++"";
++"   GCC is distributed in the hope that it will be useful, but WITHOUT";
++"   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY";
++"   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public";
++"   License for more details.";
++"";
++"   You should have received a copy of the GNU General Public License and";
++"   a copy of the GCC Runtime Library Exception along with this program;";
++"   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see";
++"   <http://www.gnu.org/licenses/>.  */";
++""];
++  patterns ();
+Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h	2012-03-06 12:47:54.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm-protos.h	2012-03-06 12:51:19.980547615 -0800
+@@ -99,14 +99,11 @@
+ extern int label_mentioned_p (rtx);
+ extern RTX_CODE minmax_code (rtx);
+ extern int adjacent_mem_locations (rtx, rtx);
+-extern int load_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *);
+-extern const char *emit_ldm_seq (rtx *, int);
+-extern int store_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *);
+-extern const char * emit_stm_seq (rtx *, int);
+-extern rtx arm_gen_load_multiple (int, int, rtx, int, int,
+-				  rtx, HOST_WIDE_INT *);
+-extern rtx arm_gen_store_multiple (int, int, rtx, int, int,
+-				   rtx, HOST_WIDE_INT *);
++extern bool gen_ldm_seq (rtx *, int, bool);
++extern bool gen_stm_seq (rtx *, int);
++extern bool gen_const_stm_seq (rtx *, int);
++extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
++extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
+ extern int arm_gen_movmemqi (rtx *);
+ extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
+ extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
+Index: gcc-4_5-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.c	2012-03-06 12:47:56.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm.c	2012-03-06 12:51:19.988547639 -0800
+@@ -753,6 +753,12 @@
+   "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
+ };
+ 
++/* The register numbers in sequence, for passing to arm_gen_load_multiple.  */
++int arm_regs_in_sequence[] =
++{
++  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
++};
++
+ #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
+ #define streq(string1, string2) (strcmp (string1, string2) == 0)
+ 
+@@ -9647,24 +9653,125 @@
+   return 0;
+ }
+ 
+-int
+-load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
+-			HOST_WIDE_INT *load_offset)
++
++/* Return true iff it would be profitable to turn a sequence of NOPS loads
++   or stores (depending on IS_STORE) into a load-multiple or store-multiple
++   instruction.  ADD_OFFSET is nonzero if the base address register needs
++   to be modified with an add instruction before we can use it.  */
++
++static bool
++multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED,
++				 int nops, HOST_WIDE_INT add_offset)
++ {
++  /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
++     if the offset isn't small enough.  The reason 2 ldrs are faster
++     is because these ARMs are able to do more than one cache access
++     in a single cycle.  The ARM9 and StrongARM have Harvard caches,
++     whilst the ARM8 has a double bandwidth cache.  This means that
++     these cores can do both an instruction fetch and a data fetch in
++     a single cycle, so the trick of calculating the address into a
++     scratch register (one of the result regs) and then doing a load
++     multiple actually becomes slower (and no smaller in code size).
++     That is the transformation
++
++ 	ldr	rd1, [rbase + offset]
++ 	ldr	rd2, [rbase + offset + 4]
++
++     to
++
++ 	add	rd1, rbase, offset
++ 	ldmia	rd1, {rd1, rd2}
++
++     produces worse code -- '3 cycles + any stalls on rd2' instead of
++     '2 cycles + any stalls on rd2'.  On ARMs with only one cache
++     access per cycle, the first sequence could never complete in less
++     than 6 cycles, whereas the ldm sequence would only take 5 and
++     would make better use of sequential accesses if not hitting the
++     cache.
++
++     We cheat here and test 'arm_ld_sched' which we currently know to
++     only be true for the ARM8, ARM9 and StrongARM.  If this ever
++     changes, then the test below needs to be reworked.  */
++  if (nops == 2 && arm_ld_sched && add_offset != 0)
++    return false;
++
++  return true;
++}
++
++/* Subroutine of load_multiple_sequence and store_multiple_sequence.
++   Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
++   an array ORDER which describes the sequence to use when accessing the
++   offsets that produces an ascending order.  In this sequence, each
++   offset must be larger by exactly 4 than the previous one.  ORDER[0]
++   must have been filled in with the lowest offset by the caller.
++   If UNSORTED_REGS is nonnull, it is an array of register numbers that
++   we use to verify that ORDER produces an ascending order of registers.
++   Return true if it was possible to construct such an order, false if
++   not.  */
++
++static bool
++compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order,
++		      int *unsorted_regs)
+ {
+-  int unsorted_regs[4];
+-  HOST_WIDE_INT unsorted_offsets[4];
+-  int order[4];
+-  int base_reg = -1;
+   int i;
++  for (i = 1; i < nops; i++)
++    {
++      int j;
++
++      order[i] = order[i - 1];
++      for (j = 0; j < nops; j++)
++	if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4)
++	  {
++	    /* We must find exactly one offset that is higher than the
++	       previous one by 4.  */
++	    if (order[i] != order[i - 1])
++	      return false;
++	    order[i] = j;
++	  }
++      if (order[i] == order[i - 1])
++	return false;
++      /* The register numbers must be ascending.  */
++      if (unsorted_regs != NULL
++	  && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]])
++	return false;
++    }
++  return true;
++}
++
++/* Used to determine in a peephole whether a sequence of load
++   instructions can be changed into a load-multiple instruction.
++   NOPS is the number of separate load instructions we are examining.  The
++   first NOPS entries in OPERANDS are the destination registers, the
++   next NOPS entries are memory operands.  If this function is
++   successful, *BASE is set to the common base register of the memory
++   accesses; *LOAD_OFFSET is set to the first memory location's offset
++   from that base register.
++   REGS is an array filled in with the destination register numbers.
++   SAVED_ORDER (if nonnull), is an array filled in with an order that maps
++   insn numbers to to an ascending order of stores.  If CHECK_REGS is true,
++   the sequence of registers in REGS matches the loads from ascending memory
++   locations, and the function verifies that the register numbers are
++   themselves ascending.  If CHECK_REGS is false, the register numbers
++   are stored in the order they are found in the operands.  */
++static int
++load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
++			int *base, HOST_WIDE_INT *load_offset, bool check_regs)
++{
++  int unsorted_regs[MAX_LDM_STM_OPS];
++  HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
++  int order[MAX_LDM_STM_OPS];
++  rtx base_reg_rtx = NULL;
++  int base_reg = -1;
++  int i, ldm_case;
+ 
+   if (low_irq_latency)
+     return 0;
+ 
+-  /* Can only handle 2, 3, or 4 insns at present,
+-     though could be easily extended if required.  */
+-  gcc_assert (nops >= 2 && nops <= 4);
++  /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
++     easily extended if required.  */
++  gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
+ 
+-  memset (order, 0, 4 * sizeof (int));
++  memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
+ 
+   /* Loop over the operands and check that the memory references are
+      suitable (i.e. immediate offsets from the same base register).  At
+@@ -9702,32 +9809,30 @@
+ 	  if (i == 0)
+ 	    {
+ 	      base_reg = REGNO (reg);
+-	      unsorted_regs[0] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      order[0] = 0;
+-	    }
+-	  else
+-	    {
+-	      if (base_reg != (int) REGNO (reg))
+-		/* Not addressed from the same base register.  */
++	      base_reg_rtx = reg;
++	      if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
+ 		return 0;
+-
+-	      unsorted_regs[i] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      if (unsorted_regs[i] < unsorted_regs[order[0]])
+-		order[0] = i;
+ 	    }
++	  else if (base_reg != (int) REGNO (reg))
++	    /* Not addressed from the same base register.  */
++	    return 0;
++
++	  unsorted_regs[i] = (GET_CODE (operands[i]) == REG
++			      ? REGNO (operands[i])
++			      : REGNO (SUBREG_REG (operands[i])));
+ 
+ 	  /* If it isn't an integer register, or if it overwrites the
+ 	     base register but isn't the last insn in the list, then
+ 	     we can't do this.  */
+-	  if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
++	  if (unsorted_regs[i] < 0
++	      || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
++	      || unsorted_regs[i] > 14
+ 	      || (i != nops - 1 && unsorted_regs[i] == base_reg))
+ 	    return 0;
+ 
+ 	  unsorted_offsets[i] = INTVAL (offset);
++	  if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
++	    order[0] = i;
+ 	}
+       else
+ 	/* Not a suitable memory address.  */
+@@ -9736,167 +9841,90 @@
+ 
+   /* All the useful information has now been extracted from the
+      operands into unsorted_regs and unsorted_offsets; additionally,
+-     order[0] has been set to the lowest numbered register in the
+-     list.  Sort the registers into order, and check that the memory
+-     offsets are ascending and adjacent.  */
+-
+-  for (i = 1; i < nops; i++)
+-    {
+-      int j;
+-
+-      order[i] = order[i - 1];
+-      for (j = 0; j < nops; j++)
+-	if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
+-	    && (order[i] == order[i - 1]
+-		|| unsorted_regs[j] < unsorted_regs[order[i]]))
+-	  order[i] = j;
+-
+-      /* Have we found a suitable register? if not, one must be used more
+-	 than once.  */
+-      if (order[i] == order[i - 1])
+-	return 0;
++     order[0] has been set to the lowest offset in the list.  Sort
++     the offsets into order, verifying that they are adjacent, and
++     check that the register numbers are ascending.  */
++  if (!compute_offset_order (nops, unsorted_offsets, order,
++			     check_regs ? unsorted_regs : NULL))
++    return 0;
+ 
+-      /* Is the memory address adjacent and ascending? */
+-      if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
+-	return 0;
+-    }
++  if (saved_order)
++    memcpy (saved_order, order, sizeof order);
+ 
+   if (base)
+     {
+       *base = base_reg;
+ 
+       for (i = 0; i < nops; i++)
+-	regs[i] = unsorted_regs[order[i]];
++	regs[i] = unsorted_regs[check_regs ? order[i] : i];
+ 
+       *load_offset = unsorted_offsets[order[0]];
+     }
+ 
+-  if (unsorted_offsets[order[0]] == 0)
+-    return 1; /* ldmia */
+-
+-  if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
+-    return 2; /* ldmib */
+-
+-  if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
+-    return 3; /* ldmda */
+-
+-  if (unsorted_offsets[order[nops - 1]] == -4)
+-    return 4; /* ldmdb */
+-
+-  /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
+-     if the offset isn't small enough.  The reason 2 ldrs are faster
+-     is because these ARMs are able to do more than one cache access
+-     in a single cycle.  The ARM9 and StrongARM have Harvard caches,
+-     whilst the ARM8 has a double bandwidth cache.  This means that
+-     these cores can do both an instruction fetch and a data fetch in
+-     a single cycle, so the trick of calculating the address into a
+-     scratch register (one of the result regs) and then doing a load
+-     multiple actually becomes slower (and no smaller in code size).
+-     That is the transformation
+-
+- 	ldr	rd1, [rbase + offset]
+- 	ldr	rd2, [rbase + offset + 4]
+-
+-     to
+-
+- 	add	rd1, rbase, offset
+- 	ldmia	rd1, {rd1, rd2}
+-
+-     produces worse code -- '3 cycles + any stalls on rd2' instead of
+-     '2 cycles + any stalls on rd2'.  On ARMs with only one cache
+-     access per cycle, the first sequence could never complete in less
+-     than 6 cycles, whereas the ldm sequence would only take 5 and
+-     would make better use of sequential accesses if not hitting the
+-     cache.
+-
+-     We cheat here and test 'arm_ld_sched' which we currently know to
+-     only be true for the ARM8, ARM9 and StrongARM.  If this ever
+-     changes, then the test below needs to be reworked.  */
+-  if (nops == 2 && arm_ld_sched)
++  if (TARGET_THUMB1
++      && !peep2_reg_dead_p (nops, base_reg_rtx))
+     return 0;
+ 
+-  /* Can't do it without setting up the offset, only do this if it takes
+-     no more than one insn.  */
+-  return (const_ok_for_arm (unsorted_offsets[order[0]])
+-	  || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
+-}
+-
+-const char *
+-emit_ldm_seq (rtx *operands, int nops)
+-{
+-  int regs[4];
+-  int base_reg;
+-  HOST_WIDE_INT offset;
+-  char buf[100];
+-  int i;
+-
+-  switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
+-    {
+-    case 1:
+-      strcpy (buf, "ldm%(ia%)\t");
+-      break;
+-
+-    case 2:
+-      strcpy (buf, "ldm%(ib%)\t");
+-      break;
+-
+-    case 3:
+-      strcpy (buf, "ldm%(da%)\t");
+-      break;
+-
+-    case 4:
+-      strcpy (buf, "ldm%(db%)\t");
+-      break;
+-
+-    case 5:
+-      if (offset >= 0)
+-	sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
+-		 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
+-		 (long) offset);
+-      else
+-	sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
+-		 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
+-		 (long) -offset);
+-      output_asm_insn (buf, operands);
+-      base_reg = regs[0];
+-      strcpy (buf, "ldm%(ia%)\t");
+-      break;
+-
+-    default:
+-      gcc_unreachable ();
+-    }
+-
+-  sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
+-	   reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
+-
+-  for (i = 1; i < nops; i++)
+-    sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
+-	     reg_names[regs[i]]);
++  if (unsorted_offsets[order[0]] == 0)
++    ldm_case = 1; /* ldmia */
++  else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
++    ldm_case = 2; /* ldmib */
++  else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
++    ldm_case = 3; /* ldmda */
++  else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
++    ldm_case = 4; /* ldmdb */
++  else if (const_ok_for_arm (unsorted_offsets[order[0]])
++	   || const_ok_for_arm (-unsorted_offsets[order[0]]))
++    ldm_case = 5;
++  else
++    return 0;
+ 
+-  strcat (buf, "}\t%@ phole ldm");
++  if (!multiple_operation_profitable_p (false, nops,
++					ldm_case == 5
++					? unsorted_offsets[order[0]] : 0))
++    return 0;
+ 
+-  output_asm_insn (buf, operands);
+-  return "";
++  return ldm_case;
+ }
+ 
+-int
+-store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
+-			 HOST_WIDE_INT * load_offset)
+-{
+-  int unsorted_regs[4];
+-  HOST_WIDE_INT unsorted_offsets[4];
+-  int order[4];
++/* Used to determine in a peephole whether a sequence of store instructions can
++   be changed into a store-multiple instruction.
++   NOPS is the number of separate store instructions we are examining.
++   NOPS_TOTAL is the total number of instructions recognized by the peephole
++   pattern.
++   The first NOPS entries in OPERANDS are the source registers, the next
++   NOPS entries are memory operands.  If this function is successful, *BASE is
++   set to the common base register of the memory accesses; *LOAD_OFFSET is set
++   to the first memory location's offset from that base register.  REGS is an
++   array filled in with the source register numbers, REG_RTXS (if nonnull) is
++   likewise filled with the corresponding rtx's.
++   SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
++   numbers to to an ascending order of stores.
++   If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
++   from ascending memory locations, and the function verifies that the register
++   numbers are themselves ascending.  If CHECK_REGS is false, the register
++   numbers are stored in the order they are found in the operands.  */
++static int
++store_multiple_sequence (rtx *operands, int nops, int nops_total,
++			 int *regs, rtx *reg_rtxs, int *saved_order, int *base,
++			 HOST_WIDE_INT *load_offset, bool check_regs)
++{
++  int unsorted_regs[MAX_LDM_STM_OPS];
++  rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS];
++  HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
++  int order[MAX_LDM_STM_OPS];
+   int base_reg = -1;
+-  int i;
++  rtx base_reg_rtx = NULL;
++  int i, stm_case;
+ 
+   if (low_irq_latency)
+     return 0;
+ 
+-  /* Can only handle 2, 3, or 4 insns at present, though could be easily
+-     extended if required.  */
+-  gcc_assert (nops >= 2 && nops <= 4);
++  /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
++     easily extended if required.  */
++  gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
+ 
+-  memset (order, 0, 4 * sizeof (int));
++  memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
+ 
+   /* Loop over the operands and check that the memory references are
+      suitable (i.e. immediate offsets from the same base register).  At
+@@ -9931,32 +9959,32 @@
+ 	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
+ 		  == CONST_INT)))
+ 	{
++	  unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG
++				  ? operands[i] : SUBREG_REG (operands[i]));
++	  unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]);
++
+ 	  if (i == 0)
+ 	    {
+ 	      base_reg = REGNO (reg);
+-	      unsorted_regs[0] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      order[0] = 0;
+-	    }
+-	  else
+-	    {
+-	      if (base_reg != (int) REGNO (reg))
+-		/* Not addressed from the same base register.  */
++	      base_reg_rtx = reg;
++	      if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
+ 		return 0;
+-
+-	      unsorted_regs[i] = (GET_CODE (operands[i]) == REG
+-				  ? REGNO (operands[i])
+-				  : REGNO (SUBREG_REG (operands[i])));
+-	      if (unsorted_regs[i] < unsorted_regs[order[0]])
+-		order[0] = i;
+ 	    }
++	  else if (base_reg != (int) REGNO (reg))
++	    /* Not addressed from the same base register.  */
++	    return 0;
+ 
+ 	  /* If it isn't an integer register, then we can't do this.  */
+-	  if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
++	  if (unsorted_regs[i] < 0
++	      || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
++	      || (TARGET_THUMB2 && unsorted_regs[i] == base_reg)
++	      || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM)
++	      || unsorted_regs[i] > 14)
+ 	    return 0;
+ 
+ 	  unsorted_offsets[i] = INTVAL (offset);
++	  if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
++	    order[0] = i;
+ 	}
+       else
+ 	/* Not a suitable memory address.  */
+@@ -9965,111 +9993,65 @@
+ 
+   /* All the useful information has now been extracted from the
+      operands into unsorted_regs and unsorted_offsets; additionally,
+-     order[0] has been set to the lowest numbered register in the
+-     list.  Sort the registers into order, and check that the memory
+-     offsets are ascending and adjacent.  */
+-
+-  for (i = 1; i < nops; i++)
+-    {
+-      int j;
+-
+-      order[i] = order[i - 1];
+-      for (j = 0; j < nops; j++)
+-	if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
+-	    && (order[i] == order[i - 1]
+-		|| unsorted_regs[j] < unsorted_regs[order[i]]))
+-	  order[i] = j;
+-
+-      /* Have we found a suitable register? if not, one must be used more
+-	 than once.  */
+-      if (order[i] == order[i - 1])
+-	return 0;
++     order[0] has been set to the lowest offset in the list.  Sort
++     the offsets into order, verifying that they are adjacent, and
++     check that the register numbers are ascending.  */
++  if (!compute_offset_order (nops, unsorted_offsets, order,
++			     check_regs ? unsorted_regs : NULL))
++    return 0;
+ 
+-      /* Is the memory address adjacent and ascending? */
+-      if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
+-	return 0;
+-    }
++  if (saved_order)
++    memcpy (saved_order, order, sizeof order);
+ 
+   if (base)
+     {
+       *base = base_reg;
+ 
+       for (i = 0; i < nops; i++)
+-	regs[i] = unsorted_regs[order[i]];
++	{
++	  regs[i] = unsorted_regs[check_regs ? order[i] : i];
++	  if (reg_rtxs)
++	    reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i];
++	}
+ 
+       *load_offset = unsorted_offsets[order[0]];
+     }
+ 
+-  if (unsorted_offsets[order[0]] == 0)
+-    return 1; /* stmia */
+-
+-  if (unsorted_offsets[order[0]] == 4)
+-    return 2; /* stmib */
+-
+-  if (unsorted_offsets[order[nops - 1]] == 0)
+-    return 3; /* stmda */
+-
+-  if (unsorted_offsets[order[nops - 1]] == -4)
+-    return 4; /* stmdb */
+-
+-  return 0;
+-}
+-
+-const char *
+-emit_stm_seq (rtx *operands, int nops)
+-{
+-  int regs[4];
+-  int base_reg;
+-  HOST_WIDE_INT offset;
+-  char buf[100];
+-  int i;
+-
+-  switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
+-    {
+-    case 1:
+-      strcpy (buf, "stm%(ia%)\t");
+-      break;
+-
+-    case 2:
+-      strcpy (buf, "stm%(ib%)\t");
+-      break;
+-
+-    case 3:
+-      strcpy (buf, "stm%(da%)\t");
+-      break;
+-
+-    case 4:
+-      strcpy (buf, "stm%(db%)\t");
+-      break;
+-
+-    default:
+-      gcc_unreachable ();
+-    }
+-
+-  sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
+-	   reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
++  if (TARGET_THUMB1
++      && !peep2_reg_dead_p (nops_total, base_reg_rtx))
++    return 0;
+ 
+-  for (i = 1; i < nops; i++)
+-    sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
+-	     reg_names[regs[i]]);
++  if (unsorted_offsets[order[0]] == 0)
++    stm_case = 1; /* stmia */
++  else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
++    stm_case = 2; /* stmib */
++  else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
++    stm_case = 3; /* stmda */
++  else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
++    stm_case = 4; /* stmdb */
++  else
++    return 0;
+ 
+-  strcat (buf, "}\t%@ phole stm");
++  if (!multiple_operation_profitable_p (false, nops, 0))
++    return 0;
+ 
+-  output_asm_insn (buf, operands);
+-  return "";
++  return stm_case;
+ }
+ 
+ /* Routines for use in generating RTL.  */
+ 
+-rtx
+-arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
+-		       int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
++/* Generate a load-multiple instruction.  COUNT is the number of loads in
++   the instruction; REGS and MEMS are arrays containing the operands.
++   BASEREG is the base register to be used in addressing the memory operands.
++   WBACK_OFFSET is nonzero if the instruction should update the base
++   register.  */
++
++static rtx
++arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
++			 HOST_WIDE_INT wback_offset)
+ {
+-  HOST_WIDE_INT offset = *offsetp;
+   int i = 0, j;
+   rtx result;
+-  int sign = up ? 1 : -1;
+-  rtx mem, addr;
+ 
+   /* XScale has load-store double instructions, but they have stricter
+      alignment requirements than load-store multiple, so we cannot
+@@ -10106,18 +10088,10 @@
+       start_sequence ();
+ 
+       for (i = 0; i < count; i++)
+-	{
+-	  addr = plus_constant (from, i * 4 * sign);
+-	  mem = adjust_automodify_address (basemem, SImode, addr, offset);
+-	  emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
+-	  offset += 4 * sign;
+-	}
++	emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]);
+ 
+-      if (write_back)
+-	{
+-	  emit_move_insn (from, plus_constant (from, count * 4 * sign));
+-	  *offsetp = offset;
+-	}
++      if (wback_offset != 0)
++	emit_move_insn (basereg, plus_constant (basereg, wback_offset));
+ 
+       seq = get_insns ();
+       end_sequence ();
+@@ -10126,41 +10100,40 @@
+     }
+ 
+   result = gen_rtx_PARALLEL (VOIDmode,
+-			     rtvec_alloc (count + (write_back ? 1 : 0)));
+-  if (write_back)
++			     rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
++  if (wback_offset != 0)
+     {
+       XVECEXP (result, 0, 0)
+-	= gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
++	= gen_rtx_SET (VOIDmode, basereg,
++		       plus_constant (basereg, wback_offset));
+       i = 1;
+       count++;
+     }
+ 
+   for (j = 0; i < count; i++, j++)
+-    {
+-      addr = plus_constant (from, j * 4 * sign);
+-      mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
+-      XVECEXP (result, 0, i)
+-	= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
+-      offset += 4 * sign;
+-    }
+-
+-  if (write_back)
+-    *offsetp = offset;
++    XVECEXP (result, 0, i)
++      = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]);
+ 
+   return result;
+ }
+ 
+-rtx
+-arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
+-			int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
++/* Generate a store-multiple instruction.  COUNT is the number of stores in
++   the instruction; REGS and MEMS are arrays containing the operands.
++   BASEREG is the base register to be used in addressing the memory operands.
++   WBACK_OFFSET is nonzero if the instruction should update the base
++   register.  */
++
++static rtx
++arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
++			  HOST_WIDE_INT wback_offset)
+ {
+-  HOST_WIDE_INT offset = *offsetp;
+   int i = 0, j;
+   rtx result;
+-  int sign = up ? 1 : -1;
+-  rtx mem, addr;
+ 
+-  /* See arm_gen_load_multiple for discussion of
++  if (GET_CODE (basereg) == PLUS)
++    basereg = XEXP (basereg, 0);
++
++  /* See arm_gen_load_multiple_1 for discussion of
+      the pros/cons of ldm/stm usage for XScale.  */
+   if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
+     {
+@@ -10169,18 +10142,10 @@
+       start_sequence ();
+ 
+       for (i = 0; i < count; i++)
+-	{
+-	  addr = plus_constant (to, i * 4 * sign);
+-	  mem = adjust_automodify_address (basemem, SImode, addr, offset);
+-	  emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
+-	  offset += 4 * sign;
+-	}
++	emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i]));
+ 
+-      if (write_back)
+-	{
+-	  emit_move_insn (to, plus_constant (to, count * 4 * sign));
+-	  *offsetp = offset;
+-	}
++      if (wback_offset != 0)
++	emit_move_insn (basereg, plus_constant (basereg, wback_offset));
+ 
+       seq = get_insns ();
+       end_sequence ();
+@@ -10189,29 +10154,319 @@
+     }
+ 
+   result = gen_rtx_PARALLEL (VOIDmode,
+-			     rtvec_alloc (count + (write_back ? 1 : 0)));
+-  if (write_back)
++			     rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
++  if (wback_offset != 0)
+     {
+       XVECEXP (result, 0, 0)
+-	= gen_rtx_SET (VOIDmode, to,
+-		       plus_constant (to, count * 4 * sign));
++	= gen_rtx_SET (VOIDmode, basereg,
++		       plus_constant (basereg, wback_offset));
+       i = 1;
+       count++;
+     }
+ 
+   for (j = 0; i < count; i++, j++)
++    XVECEXP (result, 0, i)
++      = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j]));
++
++  return result;
++}
++
++/* Generate either a load-multiple or a store-multiple instruction.  This
++   function can be used in situations where we can start with a single MEM
++   rtx and adjust its address upwards.
++   COUNT is the number of operations in the instruction, not counting a
++   possible update of the base register.  REGS is an array containing the
++   register operands.
++   BASEREG is the base register to be used in addressing the memory operands,
++   which are constructed from BASEMEM.
++   WRITE_BACK specifies whether the generated instruction should include an
++   update of the base register.
++   OFFSETP is used to pass an offset to and from this function; this offset
++   is not used when constructing the address (instead BASEMEM should have an
++   appropriate offset in its address), it is used only for setting
++   MEM_OFFSET.  It is updated only if WRITE_BACK is true.*/
++
++static rtx
++arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg,
++		     bool write_back, rtx basemem, HOST_WIDE_INT *offsetp)
++{
++  rtx mems[MAX_LDM_STM_OPS];
++  HOST_WIDE_INT offset = *offsetp;
++  int i;
++
++  gcc_assert (count <= MAX_LDM_STM_OPS);
++
++  if (GET_CODE (basereg) == PLUS)
++    basereg = XEXP (basereg, 0);
++
++  for (i = 0; i < count; i++)
+     {
+-      addr = plus_constant (to, j * 4 * sign);
+-      mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
+-      XVECEXP (result, 0, i)
+-	= gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
+-      offset += 4 * sign;
++      rtx addr = plus_constant (basereg, i * 4);
++      mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset);
++      offset += 4;
+     }
+ 
+   if (write_back)
+     *offsetp = offset;
+ 
+-  return result;
++  if (is_load)
++    return arm_gen_load_multiple_1 (count, regs, mems, basereg,
++				    write_back ? 4 * count : 0);
++  else
++    return arm_gen_store_multiple_1 (count, regs, mems, basereg,
++				     write_back ? 4 * count : 0);
++}
++
++rtx
++arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back,
++		       rtx basemem, HOST_WIDE_INT *offsetp)
++{
++  return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem,
++			      offsetp);
++}
++
++rtx
++arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back,
++			rtx basemem, HOST_WIDE_INT *offsetp)
++{
++  return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem,
++			      offsetp);
++}
++
++/* Called from a peephole2 expander to turn a sequence of loads into an
++   LDM instruction.  OPERANDS are the operands found by the peephole matcher;
++   NOPS indicates how many separate loads we are trying to combine.  SORT_REGS
++   is true if we can reorder the registers because they are used commutatively
++   subsequently.
++   Returns true iff we could generate a new instruction.  */
++
++bool
++gen_ldm_seq (rtx *operands, int nops, bool sort_regs)
++{
++  int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
++  rtx mems[MAX_LDM_STM_OPS];
++  int i, j, base_reg;
++  rtx base_reg_rtx;
++  HOST_WIDE_INT offset;
++  int write_back = FALSE;
++  int ldm_case;
++  rtx addr;
++
++  ldm_case = load_multiple_sequence (operands, nops, regs, mem_order,
++				     &base_reg, &offset, !sort_regs);
++
++  if (ldm_case == 0)
++    return false;
++
++  if (sort_regs)
++    for (i = 0; i < nops - 1; i++)
++      for (j = i + 1; j < nops; j++)
++	if (regs[i] > regs[j])
++	  {
++	    int t = regs[i];
++	    regs[i] = regs[j];
++	    regs[j] = t;
++	  }
++  base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
++
++  if (TARGET_THUMB1)
++    {
++      gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx));
++      gcc_assert (ldm_case == 1 || ldm_case == 5);
++      write_back = TRUE;
++    }
++
++  if (ldm_case == 5)
++    {
++      rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]);
++      emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset)));
++      offset = 0;
++      if (!TARGET_THUMB1)
++	{
++	  base_reg = regs[0];
++	  base_reg_rtx = newbase;
++	}
++    }
++
++  for (i = 0; i < nops; i++)
++    {
++      addr = plus_constant (base_reg_rtx, offset + i * 4);
++      mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
++					      SImode, addr, 0);
++    }
++  emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx,
++				      write_back ? offset + i * 4 : 0));
++  return true;
++}
++
++/* Called from a peephole2 expander to turn a sequence of stores into an
++   STM instruction.  OPERANDS are the operands found by the peephole matcher;
++   NOPS indicates how many separate stores we are trying to combine.
++   Returns true iff we could generate a new instruction.  */
++
++bool
++gen_stm_seq (rtx *operands, int nops)
++{
++  int i;
++  int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
++  rtx mems[MAX_LDM_STM_OPS];
++  int base_reg;
++  rtx base_reg_rtx;
++  HOST_WIDE_INT offset;
++  int write_back = FALSE;
++  int stm_case;
++  rtx addr;
++  bool base_reg_dies;
++
++  stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL,
++				      mem_order, &base_reg, &offset, true);
++
++  if (stm_case == 0)
++    return false;
++
++  base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
++
++  base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx);
++  if (TARGET_THUMB1)
++    {
++      gcc_assert (base_reg_dies);
++      write_back = TRUE;
++    }
++
++  if (stm_case == 5)
++    {
++      gcc_assert (base_reg_dies);
++      emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
++      offset = 0;
++    }
++
++  addr = plus_constant (base_reg_rtx, offset);
++
++  for (i = 0; i < nops; i++)
++    {
++      addr = plus_constant (base_reg_rtx, offset + i * 4);
++      mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
++					      SImode, addr, 0);
++    }
++  emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx,
++				       write_back ? offset + i * 4 : 0));
++  return true;
++}
++
++/* Called from a peephole2 expander to turn a sequence of stores that are
++   preceded by constant loads into an STM instruction.  OPERANDS are the
++   operands found by the peephole matcher; NOPS indicates how many
++   separate stores we are trying to combine; there are 2 * NOPS
++   instructions in the peephole.
++   Returns true iff we could generate a new instruction.  */
++
++bool
++gen_const_stm_seq (rtx *operands, int nops)
++{
++  int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS];
++  int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
++  rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS];
++  rtx mems[MAX_LDM_STM_OPS];
++  int base_reg;
++  rtx base_reg_rtx;
++  HOST_WIDE_INT offset;
++  int write_back = FALSE;
++  int stm_case;
++  rtx addr;
++  bool base_reg_dies;
++  int i, j;
++  HARD_REG_SET allocated;
++
++  stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs,
++				      mem_order, &base_reg, &offset, false);
++
++  if (stm_case == 0)
++    return false;
++
++  memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs);
++
++  /* If the same register is used more than once, try to find a free
++     register.  */
++  CLEAR_HARD_REG_SET (allocated);
++  for (i = 0; i < nops; i++)
++    {
++      for (j = i + 1; j < nops; j++)
++	if (regs[i] == regs[j])
++	  {
++	    rtx t = peep2_find_free_register (0, nops * 2,
++					      TARGET_THUMB1 ? "l" : "r",
++					      SImode, &allocated);
++	    if (t == NULL_RTX)
++	      return false;
++	    reg_rtxs[i] = t;
++	    regs[i] = REGNO (t);
++	  }
++    }
++
++  /* Compute an ordering that maps the register numbers to an ascending
++     sequence.  */
++  reg_order[0] = 0;
++  for (i = 0; i < nops; i++)
++    if (regs[i] < regs[reg_order[0]])
++      reg_order[0] = i;
++
++  for (i = 1; i < nops; i++)
++    {
++      int this_order = reg_order[i - 1];
++      for (j = 0; j < nops; j++)
++	if (regs[j] > regs[reg_order[i - 1]]
++	    && (this_order == reg_order[i - 1]
++		|| regs[j] < regs[this_order]))
++	  this_order = j;
++      reg_order[i] = this_order;
++    }
++
++  /* Ensure that registers that must be live after the instruction end
++     up with the correct value.  */
++  for (i = 0; i < nops; i++)
++    {
++      int this_order = reg_order[i];
++      if ((this_order != mem_order[i]
++	   || orig_reg_rtxs[this_order] != reg_rtxs[this_order])
++	  && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order]))
++	return false;
++    }
++
++  /* Load the constants.  */
++  for (i = 0; i < nops; i++)
++    {
++      rtx op = operands[2 * nops + mem_order[i]];
++      sorted_regs[i] = regs[reg_order[i]];
++      emit_move_insn (reg_rtxs[reg_order[i]], op);
++    }
++
++  base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
++
++  base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx);
++  if (TARGET_THUMB1)
++    {
++      gcc_assert (base_reg_dies);
++      write_back = TRUE;
++    }
++
++  if (stm_case == 5)
++    {
++      gcc_assert (base_reg_dies);
++      emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
++      offset = 0;
++    }
++
++  addr = plus_constant (base_reg_rtx, offset);
++
++  for (i = 0; i < nops; i++)
++    {
++      addr = plus_constant (base_reg_rtx, offset + i * 4);
++      mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
++					      SImode, addr, 0);
++    }
++  emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx,
++				       write_back ? offset + i * 4 : 0));
++  return true;
+ }
+ 
+ int
+@@ -10247,20 +10502,21 @@
+   for (i = 0; in_words_to_go >= 2; i+=4)
+     {
+       if (in_words_to_go > 4)
+-	emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
+-					  srcbase, &srcoffset));
++	emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src,
++					  TRUE, srcbase, &srcoffset));
+       else
+-	emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
+-					  FALSE, srcbase, &srcoffset));
++	emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go,
++					  src, FALSE, srcbase,
++					  &srcoffset));
+ 
+       if (out_words_to_go)
+ 	{
+ 	  if (out_words_to_go > 4)
+-	    emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
+-					       dstbase, &dstoffset));
++	    emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst,
++					       TRUE, dstbase, &dstoffset));
+ 	  else if (out_words_to_go != 1)
+-	    emit_insn (arm_gen_store_multiple (0, out_words_to_go,
+-					       dst, TRUE,
++	    emit_insn (arm_gen_store_multiple (arm_regs_in_sequence,
++					       out_words_to_go, dst,
+ 					       (last_bytes == 0
+ 						? FALSE : TRUE),
+ 					       dstbase, &dstoffset));
+Index: gcc-4_5-branch/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.h	2012-03-06 12:47:55.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm.h	2012-03-06 12:51:19.988547639 -0800
+@@ -1143,6 +1143,9 @@
+   ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
+    || (MODE) == CImode || (MODE) == XImode)
+ 
++/* The register numbers in sequence, for passing to arm_gen_load_multiple.  */
++extern int arm_regs_in_sequence[];
++
+ /* The order in which register should be allocated.  It is good to use ip
+    since no saving is required (though calls clobber it) and it never contains
+    function parameters.  It is quite good to use lr since other calls may
+@@ -2821,4 +2824,8 @@
+ #define NEED_INDICATE_EXEC_STACK	0
+ #endif
+ 
++/* The maximum number of parallel loads or stores we support in an ldm/stm
++   instruction.  */
++#define MAX_LDM_STM_OPS 4
++
+ #endif /* ! GCC_ARM_H */
+Index: gcc-4_5-branch/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/arm.md	2012-03-06 12:47:56.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/arm.md	2012-03-06 12:51:19.992547622 -0800
+@@ -6282,7 +6282,7 @@
+ 
+ ;; load- and store-multiple insns
+ ;; The arm can load/store any set of registers, provided that they are in
+-;; ascending order; but that is beyond GCC so stick with what it knows.
++;; ascending order, but these expanders assume a contiguous set.
+ 
+ (define_expand "load_multiple"
+   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+@@ -6303,126 +6303,12 @@
+     FAIL;
+ 
+   operands[3]
+-    = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]),
++    = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]),
++			     INTVAL (operands[2]),
+ 			     force_reg (SImode, XEXP (operands[1], 0)),
+-			     TRUE, FALSE, operands[1], &offset);
++			     FALSE, operands[1], &offset);
+ })
+ 
+-;; Load multiple with write-back
+-
+-(define_insn "*ldmsi_postinc4"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+-     (set (match_operand:SI 6 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
+-  "ldm%(ia%)\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi_postinc4_thumb1"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=l")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+-     (set (match_operand:SI 6 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))])]
+-  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
+-  "ldmia\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "type" "load4")]
+-)
+-
+-(define_insn "*ldmsi_postinc3"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 12)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "ldm%(ia%)\\t%1!, {%3, %4, %5}"
+-  [(set_attr "type" "load3")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi_postinc2"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 8)))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (match_dup 2)))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "ldm%(ia%)\\t%1!, {%3, %4}"
+-  [(set_attr "type" "load2")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-;; Ordinary load multiple
+-
+-(define_insn "*ldmsi4"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
+-	  (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+-     (set (match_operand:SI 5 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "ldm%(ia%)\\t%1, {%2, %3, %4, %5}"
+-  [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi3"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
+-	  (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+-     (set (match_operand:SI 4 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "ldm%(ia%)\\t%1, {%2, %3, %4}"
+-  [(set_attr "type" "load3")
+-   (set_attr "predicable" "yes")]
+-)
+-
+-(define_insn "*ldmsi2"
+-  [(match_parallel 0 "load_multiple_operation"
+-    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
+-	  (mem:SI (match_operand:SI 1 "s_register_operand" "r")))
+-     (set (match_operand:SI 3 "arm_hard_register_operand" "")
+-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
+-  "ldm%(ia%)\\t%1, {%2, %3}"
+-  [(set_attr "type" "load2")
+-   (set_attr "predicable" "yes")]
+-)
+-
+ (define_expand "store_multiple"
+   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+                           (match_operand:SI 1 "" ""))
+@@ -6442,125 +6328,12 @@
+     FAIL;
+ 
+   operands[3]
+-    = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]),
++    = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]),
++			      INTVAL (operands[2]),
+ 			      force_reg (SImode, XEXP (operands[0], 0)),
+-			      TRUE, FALSE, operands[0], &offset);
++			      FALSE, operands[0], &offset);
+ })
+ 
+-;; Store multiple with write-back
+-
+-(define_insn "*stmsi_postinc4"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+-	  (match_operand:SI 6 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
+-  "stm%(ia%)\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store4")]
+-)
+-
+-(define_insn "*stmsi_postinc4_thumb1"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=l")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 16)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+-	  (match_operand:SI 6 "arm_hard_register_operand" ""))])]
+-  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
+-  "stmia\\t%1!, {%3, %4, %5, %6}"
+-  [(set_attr "type" "store4")]
+-)
+-
+-(define_insn "*stmsi_postinc3"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 12)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "stm%(ia%)\\t%1!, {%3, %4, %5}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store3")]
+-)
+-
+-(define_insn "*stmsi_postinc2"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (match_operand:SI 1 "s_register_operand" "=r")
+-	  (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+-		   (const_int 8)))
+-     (set (mem:SI (match_dup 2))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "stm%(ia%)\\t%1!, {%3, %4}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store2")]
+-)
+-
+-;; Ordinary store multiple
+-
+-(define_insn "*stmsi4"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+-	  (match_operand:SI 2 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+-	  (match_operand:SI 5 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
+-  "stm%(ia%)\\t%1, {%2, %3, %4, %5}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store4")]
+-)
+-
+-(define_insn "*stmsi3"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+-	  (match_operand:SI 2 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+-	  (match_operand:SI 4 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
+-  "stm%(ia%)\\t%1, {%2, %3, %4}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store3")]
+-)
+-
+-(define_insn "*stmsi2"
+-  [(match_parallel 0 "store_multiple_operation"
+-    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+-	  (match_operand:SI 2 "arm_hard_register_operand" ""))
+-     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+-	  (match_operand:SI 3 "arm_hard_register_operand" ""))])]
+-  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
+-  "stm%(ia%)\\t%1, {%2, %3}"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "type" "store2")]
+-)
+ 
+ ;; Move a block of memory if it is word aligned and MORE than 2 words long.
+ ;; We could let this apply for blocks of less than this, but it clobbers so
+@@ -9025,8 +8798,8 @@
+ 	if (REGNO (reg) == R0_REGNUM)
+ 	  {
+ 	    /* On thumb we have to use a write-back instruction.  */
+-	    emit_insn (arm_gen_store_multiple (R0_REGNUM, 4, addr, TRUE,
+-			TARGET_THUMB ? TRUE : FALSE, mem, &offset));
++	    emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr,
++ 		       TARGET_THUMB ? TRUE : FALSE, mem, &offset));
+ 	    size = TARGET_ARM ? 16 : 0;
+ 	  }
+ 	else
+@@ -9072,8 +8845,8 @@
+ 	if (REGNO (reg) == R0_REGNUM)
+ 	  {
+ 	    /* On thumb we have to use a write-back instruction.  */
+-	    emit_insn (arm_gen_load_multiple (R0_REGNUM, 4, addr, TRUE,
+-			TARGET_THUMB ? TRUE : FALSE, mem, &offset));
++	    emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr,
++ 		       TARGET_THUMB ? TRUE : FALSE, mem, &offset));
+ 	    size = TARGET_ARM ? 16 : 0;
+ 	  }
+ 	else
+@@ -10666,87 +10439,6 @@
+   ""
+ )
+ 
+-; Peepholes to spot possible load- and store-multiples, if the ordering is
+-; reversed, check that the memory references aren't volatile.
+-
+-(define_peephole
+-  [(set (match_operand:SI 0 "s_register_operand" "=rk")
+-        (match_operand:SI 4 "memory_operand" "m"))
+-   (set (match_operand:SI 1 "s_register_operand" "=rk")
+-        (match_operand:SI 5 "memory_operand" "m"))
+-   (set (match_operand:SI 2 "s_register_operand" "=rk")
+-        (match_operand:SI 6 "memory_operand" "m"))
+-   (set (match_operand:SI 3 "s_register_operand" "=rk")
+-        (match_operand:SI 7 "memory_operand" "m"))]
+-  "TARGET_ARM && load_multiple_sequence (operands, 4, NULL, NULL, NULL)"
+-  "*
+-  return emit_ldm_seq (operands, 4);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 0 "s_register_operand" "=rk")
+-        (match_operand:SI 3 "memory_operand" "m"))
+-   (set (match_operand:SI 1 "s_register_operand" "=rk")
+-        (match_operand:SI 4 "memory_operand" "m"))
+-   (set (match_operand:SI 2 "s_register_operand" "=rk")
+-        (match_operand:SI 5 "memory_operand" "m"))]
+-  "TARGET_ARM && load_multiple_sequence (operands, 3, NULL, NULL, NULL)"
+-  "*
+-  return emit_ldm_seq (operands, 3);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 0 "s_register_operand" "=rk")
+-        (match_operand:SI 2 "memory_operand" "m"))
+-   (set (match_operand:SI 1 "s_register_operand" "=rk")
+-        (match_operand:SI 3 "memory_operand" "m"))]
+-  "TARGET_ARM && load_multiple_sequence (operands, 2, NULL, NULL, NULL)"
+-  "*
+-  return emit_ldm_seq (operands, 2);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 4 "memory_operand" "=m")
+-        (match_operand:SI 0 "s_register_operand" "rk"))
+-   (set (match_operand:SI 5 "memory_operand" "=m")
+-        (match_operand:SI 1 "s_register_operand" "rk"))
+-   (set (match_operand:SI 6 "memory_operand" "=m")
+-        (match_operand:SI 2 "s_register_operand" "rk"))
+-   (set (match_operand:SI 7 "memory_operand" "=m")
+-        (match_operand:SI 3 "s_register_operand" "rk"))]
+-  "TARGET_ARM && store_multiple_sequence (operands, 4, NULL, NULL, NULL)"
+-  "*
+-  return emit_stm_seq (operands, 4);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 3 "memory_operand" "=m")
+-        (match_operand:SI 0 "s_register_operand" "rk"))
+-   (set (match_operand:SI 4 "memory_operand" "=m")
+-        (match_operand:SI 1 "s_register_operand" "rk"))
+-   (set (match_operand:SI 5 "memory_operand" "=m")
+-        (match_operand:SI 2 "s_register_operand" "rk"))]
+-  "TARGET_ARM && store_multiple_sequence (operands, 3, NULL, NULL, NULL)"
+-  "*
+-  return emit_stm_seq (operands, 3);
+-  "
+-)
+-
+-(define_peephole
+-  [(set (match_operand:SI 2 "memory_operand" "=m")
+-        (match_operand:SI 0 "s_register_operand" "rk"))
+-   (set (match_operand:SI 3 "memory_operand" "=m")
+-        (match_operand:SI 1 "s_register_operand" "rk"))]
+-  "TARGET_ARM && store_multiple_sequence (operands, 2, NULL, NULL, NULL)"
+-  "*
+-  return emit_stm_seq (operands, 2);
+-  "
+-)
+-
+ (define_split
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
+@@ -11549,6 +11241,8 @@
+   "
+ )
+ 
++;; Load the load/store multiple patterns
++(include "ldmstm.md")
+ ;; Load the FPA co-processor patterns
+ (include "fpa.md")
+ ;; Load the Maverick co-processor patterns
+Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_5-branch/gcc/config/arm/ldmstm.md	2012-03-06 12:51:19.992547622 -0800
+@@ -0,0 +1,1191 @@
++/* ARM ldm/stm instruction patterns.  This file was automatically generated
++   using arm-ldmstm.ml.  Please do not edit manually.
++
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   Contributed by CodeSourcery.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++(define_insn "*ldm4_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm4_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "l")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")])
++
++(define_insn "*ldm4_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "ldm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm4_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
++  "ldm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")])
++
++(define_insn "*stm4_ia"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(ia%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "stm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_stm4_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
++  "stm%(ia%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")])
++
++(define_insn "*ldm4_ib"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int 4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 16))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ib%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_ib_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 16))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "ldm%(ib%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_ib"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(ib%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_ib_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "stm%(ib%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_da"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -12))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 1)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(da%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_da_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -12))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "ldm%(da%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_da"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 1))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(da%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_da_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -12)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
++  "stm%(da%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_db"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -16))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -12))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(db%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm4_db_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -16))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -12))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 6 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "ldm%(db%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "load4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_db"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -16)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -12)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(db%)\t%1, {%2, %3, %4, %5}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm4_db_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -16)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -12)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 6 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
++  "stm%(db%)\t%1!, {%3, %4, %5, %6}"
++  [(set_attr "type" "store4")
++   (set_attr "predicable" "yes")])
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 5 "memory_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 6 "memory_operand" ""))
++   (set (match_operand:SI 3 "s_register_operand" "")
++        (match_operand:SI 7 "memory_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 4, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "memory_operand" ""))
++   (parallel
++    [(set (match_operand:SI 1 "s_register_operand" "")
++          (match_operand:SI 5 "memory_operand" ""))
++     (set (match_operand:SI 2 "s_register_operand" "")
++          (match_operand:SI 6 "memory_operand" ""))
++     (set (match_operand:SI 3 "s_register_operand" "")
++          (match_operand:SI 7 "memory_operand" ""))])]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 4, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 9 "const_int_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 10 "const_int_operand" ""))
++   (set (match_operand:SI 6 "memory_operand" "")
++        (match_dup 2))
++   (set (match_operand:SI 3 "s_register_operand" "")
++        (match_operand:SI 11 "const_int_operand" ""))
++   (set (match_operand:SI 7 "memory_operand" "")
++        (match_dup 3))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 4))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 9 "const_int_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 10 "const_int_operand" ""))
++   (set (match_operand:SI 3 "s_register_operand" "")
++        (match_operand:SI 11 "const_int_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 6 "memory_operand" "")
++        (match_dup 2))
++   (set (match_operand:SI 7 "memory_operand" "")
++        (match_dup 3))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 4))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 4 "memory_operand" "")
++        (match_operand:SI 0 "s_register_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_operand:SI 1 "s_register_operand" ""))
++   (set (match_operand:SI 6 "memory_operand" "")
++        (match_operand:SI 2 "s_register_operand" ""))
++   (set (match_operand:SI 7 "memory_operand" "")
++        (match_operand:SI 3 "s_register_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_stm_seq (operands, 4))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_insn "*ldm3_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm3_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "l")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")])
++
++(define_insn "*ldm3_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm3_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")])
++
++(define_insn "*stm3_ia"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(ia%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_stm3_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
++  "stm%(ia%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")])
++
++(define_insn "*ldm3_ib"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int 4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 12))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ib%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_ib_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 12))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(ib%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_ib"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(ib%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_ib_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(ib%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_da"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -8))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 1)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(da%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_da_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "ldm%(da%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_da"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 1))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(da%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_da_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
++  "stm%(da%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_db"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -12))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(db%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm3_db_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -12))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 5 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "ldm%(db%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "load3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_db"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(db%)\t%1, {%2, %3, %4}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm3_db_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -12)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 5 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
++  "stm%(db%)\t%1!, {%3, %4, %5}"
++  [(set_attr "type" "store3")
++   (set_attr "predicable" "yes")])
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 4 "memory_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 5 "memory_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 3, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (parallel
++    [(set (match_operand:SI 1 "s_register_operand" "")
++          (match_operand:SI 4 "memory_operand" ""))
++     (set (match_operand:SI 2 "s_register_operand" "")
++          (match_operand:SI 5 "memory_operand" ""))])]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 3, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 6 "const_int_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 7 "const_int_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 2))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 3))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 6 "const_int_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 7 "const_int_operand" ""))
++   (set (match_operand:SI 2 "s_register_operand" "")
++        (match_operand:SI 8 "const_int_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_dup 1))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_dup 2))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 3))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 3 "memory_operand" "")
++        (match_operand:SI 0 "s_register_operand" ""))
++   (set (match_operand:SI 4 "memory_operand" "")
++        (match_operand:SI 1 "s_register_operand" ""))
++   (set (match_operand:SI 5 "memory_operand" "")
++        (match_operand:SI 2 "s_register_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_stm_seq (operands, 3))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_insn "*ldm2_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "ldm%(ia%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm2_ia"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (match_operand:SI 1 "s_register_operand" "l")))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 4))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
++  "ldm%(ia%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")])
++
++(define_insn "*ldm2_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_ldm2_ia_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")])
++
++(define_insn "*stm2_ia"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "stm%(ia%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*thumb_stm2_ia_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=l")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
++  "stm%(ia%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")])
++
++(define_insn "*ldm2_ib"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int 4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int 8))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "ldm%(ib%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_ib_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int 8))))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(ib%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_ib"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "stm%(ib%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_ib_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(ib%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_da"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -4))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 1)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "ldm%(da%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_da_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (match_dup 2)))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "ldm%(da%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_da"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -4)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 1))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
++  "stm%(da%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_da_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (match_dup 2))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
++  "stm%(da%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_db"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 2 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk")
++                  (const_int -8))))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 1)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "ldm%(db%)\t%1, {%2, %3}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*ldm2_db_update"
++  [(match_parallel 0 "load_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (match_operand:SI 3 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -8))))
++     (set (match_operand:SI 4 "arm_hard_register_operand" "")
++          (mem:SI (plus:SI (match_dup 2)
++                  (const_int -4))))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "ldm%(db%)\t%1!, {%3, %4}"
++  [(set_attr "type" "load2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_db"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8)))
++          (match_operand:SI 2 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 1) (const_int -4)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
++  "stm%(db%)\t%1, {%2, %3}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*stm2_db_update"
++  [(match_parallel 0 "store_multiple_operation"
++    [(set (match_operand:SI 1 "s_register_operand" "=rk")
++          (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8)))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -8)))
++          (match_operand:SI 3 "arm_hard_register_operand" ""))
++     (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
++          (match_operand:SI 4 "arm_hard_register_operand" ""))])]
++  "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
++  "stm%(db%)\t%1!, {%3, %4}"
++  [(set_attr "type" "store2")
++   (set_attr "predicable" "yes")])
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 2 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_ldm_seq (operands, 2, false))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "const_int_operand" ""))
++   (set (match_operand:SI 2 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 5 "const_int_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 1))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 2))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 4 "const_int_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 5 "const_int_operand" ""))
++   (set (match_operand:SI 2 "memory_operand" "")
++        (match_dup 0))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_dup 1))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_const_stm_seq (operands, 2))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 2 "memory_operand" "")
++        (match_operand:SI 0 "s_register_operand" ""))
++   (set (match_operand:SI 3 "memory_operand" "")
++        (match_operand:SI 1 "s_register_operand" ""))]
++  ""
++  [(const_int 0)]
++{
++  if (gen_stm_seq (operands, 2))
++    DONE;
++  else
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 2 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (parallel
++     [(set (match_operand:SI 4 "s_register_operand" "")
++           (match_operator:SI 5 "commutative_binary_operator"
++            [(match_operand:SI 6 "s_register_operand" "")
++             (match_operand:SI 7 "s_register_operand" "")]))
++      (clobber (reg:CC CC_REGNUM))])]
++  "(((operands[6] == operands[0] && operands[7] == operands[1])
++     || (operands[7] == operands[0] && operands[6] == operands[1]))
++    && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))"
++  [(parallel
++    [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))
++     (clobber (reg:CC CC_REGNUM))])]
++{
++  if (!gen_ldm_seq (operands, 2, true))
++    FAIL;
++})
++
++(define_peephole2
++  [(set (match_operand:SI 0 "s_register_operand" "")
++        (match_operand:SI 2 "memory_operand" ""))
++   (set (match_operand:SI 1 "s_register_operand" "")
++        (match_operand:SI 3 "memory_operand" ""))
++   (set (match_operand:SI 4 "s_register_operand" "")
++        (match_operator:SI 5 "commutative_binary_operator"
++         [(match_operand:SI 6 "s_register_operand" "")
++          (match_operand:SI 7 "s_register_operand" "")]))]
++  "(((operands[6] == operands[0] && operands[7] == operands[1])
++     || (operands[7] == operands[0] && operands[6] == operands[1]))
++    && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))"
++  [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))]
++{
++  if (!gen_ldm_seq (operands, 2, true))
++    FAIL;
++})
++
+Index: gcc-4_5-branch/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/arm/predicates.md	2012-03-06 12:47:54.000000000 -0800
++++ gcc-4_5-branch/gcc/config/arm/predicates.md	2012-03-06 12:51:19.992547622 -0800
+@@ -211,6 +211,11 @@
+   (and (match_code "ior,xor,and")
+        (match_test "mode == GET_MODE (op)")))
+ 
++;; True for commutative operators
++(define_special_predicate "commutative_binary_operator"
++  (and (match_code "ior,xor,and,plus")
++       (match_test "mode == GET_MODE (op)")))
++
+ ;; True for shift operators.
+ (define_special_predicate "shift_operator"
+   (and (ior (ior (and (match_code "mult")
+@@ -334,16 +339,20 @@
+   (match_code "parallel")
+ {
+   HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int dest_regno;
++  unsigned dest_regno;
+   rtx src_addr;
+   HOST_WIDE_INT i = 1, base = 0;
++  HOST_WIDE_INT offset = 0;
+   rtx elt;
++  bool addr_reg_loaded = false;
++  bool update = false;
+ 
+   if (low_irq_latency)
+     return false;
+ 
+   if (count <= 1
+-      || GET_CODE (XVECEXP (op, 0, 0)) != SET)
++      || GET_CODE (XVECEXP (op, 0, 0)) != SET
++      || !REG_P (SET_DEST (XVECEXP (op, 0, 0))))
+     return false;
+ 
+   /* Check to see if this might be a write-back.  */
+@@ -351,6 +360,7 @@
+     {
+       i++;
+       base = 1;
++      update = true;
+ 
+       /* Now check it more carefully.  */
+       if (GET_CODE (SET_DEST (elt)) != REG
+@@ -369,6 +379,15 @@
+ 
+   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
+   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
++  if (GET_CODE (src_addr) == PLUS)
++    {
++      if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT)
++	return false;
++      offset = INTVAL (XEXP (src_addr, 1));
++      src_addr = XEXP (src_addr, 0);
++    }
++  if (!REG_P (src_addr))
++    return false;
+ 
+   for (; i < count; i++)
+     {
+@@ -377,16 +396,28 @@
+       if (GET_CODE (elt) != SET
+           || GET_CODE (SET_DEST (elt)) != REG
+           || GET_MODE (SET_DEST (elt)) != SImode
+-          || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
++          || REGNO (SET_DEST (elt)) <= dest_regno
+           || GET_CODE (SET_SRC (elt)) != MEM
+           || GET_MODE (SET_SRC (elt)) != SImode
+-          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
+-          || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
+-          || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+-          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
++          || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
++	       || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
++	       || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
++	       || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4)
++	      && (!REG_P (XEXP (SET_SRC (elt), 0))
++		  || offset + (i - base) * 4 != 0)))
+         return false;
++      dest_regno = REGNO (SET_DEST (elt));
++      if (dest_regno == REGNO (src_addr))
++        addr_reg_loaded = true;
+     }
+-
++  /* For Thumb, we only have updating instructions.  If the pattern does
++     not describe an update, it must be because the address register is
++     in the list of loaded registers - on the hardware, this has the effect
++     of overriding the update.  */
++  if (update && addr_reg_loaded)
++    return false;
++  if (TARGET_THUMB1)
++    return update || addr_reg_loaded;
+   return true;
+ })
+ 
+@@ -394,9 +425,9 @@
+   (match_code "parallel")
+ {
+   HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int src_regno;
++  unsigned src_regno;
+   rtx dest_addr;
+-  HOST_WIDE_INT i = 1, base = 0;
++  HOST_WIDE_INT i = 1, base = 0, offset = 0;
+   rtx elt;
+ 
+   if (low_irq_latency)
+@@ -430,6 +461,16 @@
+   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
+   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
+ 
++  if (GET_CODE (dest_addr) == PLUS)
++    {
++      if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT)
++	return false;
++      offset = INTVAL (XEXP (dest_addr, 1));
++      dest_addr = XEXP (dest_addr, 0);
++    }
++  if (!REG_P (dest_addr))
++    return false;
++
+   for (; i < count; i++)
+     {
+       elt = XVECEXP (op, 0, i);
+@@ -437,14 +478,17 @@
+       if (GET_CODE (elt) != SET
+           || GET_CODE (SET_SRC (elt)) != REG
+           || GET_MODE (SET_SRC (elt)) != SImode
+-          || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
++          || REGNO (SET_SRC (elt)) <= src_regno
+           || GET_CODE (SET_DEST (elt)) != MEM
+           || GET_MODE (SET_DEST (elt)) != SImode
+-          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
+-          || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
+-          || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+-          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
++          || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
++	       || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
++	       || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
++               || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4)
++	      && (!REG_P (XEXP (SET_DEST (elt), 0))
++		  || offset + (i - base) * 4 != 0)))
+         return false;
++      src_regno = REGNO (SET_SRC (elt));
+     }
+ 
+   return true;
+Index: gcc-4_5-branch/gcc/config/i386/i386.md
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/i386/i386.md	2012-03-06 12:47:55.000000000 -0800
++++ gcc-4_5-branch/gcc/config/i386/i386.md	2012-03-06 12:51:19.996547605 -0800
+@@ -4960,6 +4960,7 @@
+    (set (match_operand:SSEMODEI24 2 "register_operand" "")
+ 	(fix:SSEMODEI24 (match_dup 0)))]
+   "TARGET_SHORTEN_X87_SSE
++   && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
+    && peep2_reg_dead_p (2, operands[0])"
+   [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
+   "")
+@@ -20089,15 +20090,14 @@
+ ;;  leal    (%edx,%eax,4), %eax
+ 
+ (define_peephole2
+-  [(parallel [(set (match_operand 0 "register_operand" "")
++  [(match_scratch:P 5 "r")
++   (parallel [(set (match_operand 0 "register_operand" "")
+ 		   (ashift (match_operand 1 "register_operand" "")
+ 			   (match_operand 2 "const_int_operand" "")))
+ 	       (clobber (reg:CC FLAGS_REG))])
+-   (set (match_operand 3 "register_operand")
+-        (match_operand 4 "x86_64_general_operand" ""))
+-   (parallel [(set (match_operand 5 "register_operand" "")
+-		   (plus (match_operand 6 "register_operand" "")
+-			 (match_operand 7 "register_operand" "")))
++   (parallel [(set (match_operand 3 "register_operand" "")
++		   (plus (match_dup 0)
++			 (match_operand 4 "x86_64_general_operand" "")))
+ 		   (clobber (reg:CC FLAGS_REG))])]
+   "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
+    /* Validate MODE for lea.  */
+@@ -20106,31 +20106,27 @@
+ 	    || GET_MODE (operands[0]) == HImode))
+        || GET_MODE (operands[0]) == SImode
+        || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
++   && (rtx_equal_p (operands[0], operands[3])
++       || peep2_reg_dead_p (2, operands[0]))
+    /* We reorder load and the shift.  */
+-   && !rtx_equal_p (operands[1], operands[3])
+-   && !reg_overlap_mentioned_p (operands[0], operands[4])
+-   /* Last PLUS must consist of operand 0 and 3.  */
+-   && !rtx_equal_p (operands[0], operands[3])
+-   && (rtx_equal_p (operands[3], operands[6])
+-       || rtx_equal_p (operands[3], operands[7]))
+-   && (rtx_equal_p (operands[0], operands[6])
+-       || rtx_equal_p (operands[0], operands[7]))
+-   /* The intermediate operand 0 must die or be same as output.  */
+-   && (rtx_equal_p (operands[0], operands[5])
+-       || peep2_reg_dead_p (3, operands[0]))"
+-  [(set (match_dup 3) (match_dup 4))
++   && !reg_overlap_mentioned_p (operands[0], operands[4])"
++  [(set (match_dup 5) (match_dup 4))
+    (set (match_dup 0) (match_dup 1))]
+ {
+-  enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode;
++  enum machine_mode mode = GET_MODE (operands[1]) == DImode ? DImode : SImode;
+   int scale = 1 << INTVAL (operands[2]);
+   rtx index = gen_lowpart (Pmode, operands[1]);
+-  rtx base = gen_lowpart (Pmode, operands[3]);
+-  rtx dest = gen_lowpart (mode, operands[5]);
++  rtx base = gen_lowpart (Pmode, operands[5]);
++  rtx dest = gen_lowpart (mode, operands[3]);
+ 
+   operands[1] = gen_rtx_PLUS (Pmode, base,
+   			      gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
++  operands[5] = base;
+   if (mode != Pmode)
+-    operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
++    {
++      operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
++      operands[5] = gen_rtx_SUBREG (mode, operands[5], 0);
++    }
+   operands[0] = dest;
+ })
+ 
+Index: gcc-4_5-branch/gcc/genoutput.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/genoutput.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/genoutput.c	2012-03-06 12:51:20.000547582 -0800
+@@ -266,6 +266,8 @@
+ 
+       printf ("    %d,\n", d->strict_low);
+ 
++      printf ("    %d,\n", d->constraint == NULL ? 1 : 0);
++
+       printf ("    %d\n", d->eliminable);
+ 
+       printf("  },\n");
+Index: gcc-4_5-branch/gcc/genrecog.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/genrecog.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/genrecog.c	2012-03-06 12:51:20.000547582 -0800
+@@ -1782,20 +1782,11 @@
+   int odepth = strlen (oldpos);
+   int ndepth = strlen (newpos);
+   int depth;
+-  int old_has_insn, new_has_insn;
+ 
+   /* Pop up as many levels as necessary.  */
+   for (depth = odepth; strncmp (oldpos, newpos, depth) != 0; --depth)
+     continue;
+ 
+-  /* Hunt for the last [A-Z] in both strings.  */
+-  for (old_has_insn = odepth - 1; old_has_insn >= 0; --old_has_insn)
+-    if (ISUPPER (oldpos[old_has_insn]))
+-      break;
+-  for (new_has_insn = ndepth - 1; new_has_insn >= 0; --new_has_insn)
+-    if (ISUPPER (newpos[new_has_insn]))
+-      break;
+-
+   /* Go down to desired level.  */
+   while (depth < ndepth)
+     {
+Index: gcc-4_5-branch/gcc/recog.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/recog.c	2012-03-06 12:47:48.000000000 -0800
++++ gcc-4_5-branch/gcc/recog.c	2012-03-06 13:04:05.780584592 -0800
+@@ -2082,6 +2082,7 @@
+ 			       recog_data.operand_loc,
+ 			       recog_data.constraints,
+ 			       recog_data.operand_mode, NULL);
++	  memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
+ 	  if (noperands > 0)
+ 	    {
+ 	      const char *p =  recog_data.constraints[0];
+@@ -2111,6 +2112,7 @@
+       for (i = 0; i < noperands; i++)
+ 	{
+ 	  recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
++	  recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
+ 	  recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
+ 	  /* VOIDmode match_operands gets mode from their real operand.  */
+ 	  if (recog_data.operand_mode[i] == VOIDmode)
+@@ -2909,6 +2911,10 @@
+ 
+ static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
+ static int peep2_current;
++
++static bool peep2_do_rebuild_jump_labels;
++static bool peep2_do_cleanup_cfg;
++
+ /* The number of instructions available to match a peep2.  */
+ int peep2_current_count;
+ 
+@@ -2917,6 +2923,16 @@
+    DF_LIVE_OUT for the block.  */
+ #define PEEP2_EOB	pc_rtx
+ 
++/* Wrap N to fit into the peep2_insn_data buffer.  */
++
++static int
++peep2_buf_position (int n)
++{
++  if (n >= MAX_INSNS_PER_PEEP2 + 1)
++    n -= MAX_INSNS_PER_PEEP2 + 1;
++  return n;
++}
++
+ /* Return the Nth non-note insn after `current', or return NULL_RTX if it
+    does not exist.  Used by the recognizer to find the next insn to match
+    in a multi-insn pattern.  */
+@@ -2926,9 +2942,7 @@
+ {
+   gcc_assert (n <= peep2_current_count);
+ 
+-  n += peep2_current;
+-  if (n >= MAX_INSNS_PER_PEEP2 + 1)
+-    n -= MAX_INSNS_PER_PEEP2 + 1;
++  n = peep2_buf_position (peep2_current + n);
+ 
+   return peep2_insn_data[n].insn;
+ }
+@@ -2941,9 +2955,7 @@
+ {
+   gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
+ 
+-  ofs += peep2_current;
+-  if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+-    ofs -= MAX_INSNS_PER_PEEP2 + 1;
++  ofs = peep2_buf_position (peep2_current + ofs);
+ 
+   gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
+ 
+@@ -2959,9 +2971,7 @@
+ 
+   gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
+ 
+-  ofs += peep2_current;
+-  if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
+-    ofs -= MAX_INSNS_PER_PEEP2 + 1;
++  ofs = peep2_buf_position (peep2_current + ofs);
+ 
+   gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
+ 
+@@ -2997,12 +3007,8 @@
+   gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
+   gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
+ 
+-  from += peep2_current;
+-  if (from >= MAX_INSNS_PER_PEEP2 + 1)
+-    from -= MAX_INSNS_PER_PEEP2 + 1;
+-  to += peep2_current;
+-  if (to >= MAX_INSNS_PER_PEEP2 + 1)
+-    to -= MAX_INSNS_PER_PEEP2 + 1;
++  from = peep2_buf_position (peep2_current + from);
++  to = peep2_buf_position (peep2_current + to);
+ 
+   gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
+   REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
+@@ -3016,8 +3022,7 @@
+ 	   *def_rec; def_rec++)
+ 	SET_HARD_REG_BIT (live, DF_REF_REGNO (*def_rec));
+ 
+-      if (++from >= MAX_INSNS_PER_PEEP2 + 1)
+-	from = 0;
++      from = peep2_buf_position (from + 1);
+     }
+ 
+   cl = (class_str[0] == 'r' ? GENERAL_REGS
+@@ -3107,19 +3112,234 @@
+   COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
+ }
+ 
++/* While scanning basic block BB, we found a match of length MATCH_LEN,
++   starting at INSN.  Perform the replacement, removing the old insns and
++   replacing them with ATTEMPT.  Returns the last insn emitted.  */
++
++static rtx
++peep2_attempt (basic_block bb, rtx insn, int match_len, rtx attempt)
++{
++  int i;
++  rtx last, note, before_try, x;
++  bool was_call = false;
++
++  /* If we are splitting a CALL_INSN, look for the CALL_INSN
++     in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
++     cfg-related call notes.  */
++  for (i = 0; i <= match_len; ++i)
++    {
++      int j;
++      rtx old_insn, new_insn, note;
++
++      j = peep2_buf_position (peep2_current + i);
++      old_insn = peep2_insn_data[j].insn;
++      if (!CALL_P (old_insn))
++	continue;
++      was_call = true;
++
++      new_insn = attempt;
++      while (new_insn != NULL_RTX)
++	{
++	  if (CALL_P (new_insn))
++	    break;
++	  new_insn = NEXT_INSN (new_insn);
++	}
++
++      gcc_assert (new_insn != NULL_RTX);
++
++      CALL_INSN_FUNCTION_USAGE (new_insn)
++	= CALL_INSN_FUNCTION_USAGE (old_insn);
++
++      for (note = REG_NOTES (old_insn);
++	   note;
++	   note = XEXP (note, 1))
++	switch (REG_NOTE_KIND (note))
++	  {
++	  case REG_NORETURN:
++	  case REG_SETJMP:
++	    add_reg_note (new_insn, REG_NOTE_KIND (note),
++			  XEXP (note, 0));
++	    break;
++	  default:
++	    /* Discard all other reg notes.  */
++	    break;
++	  }
++
++      /* Croak if there is another call in the sequence.  */
++      while (++i <= match_len)
++	{
++	  j = peep2_buf_position (peep2_current + i);
++	  old_insn = peep2_insn_data[j].insn;
++	  gcc_assert (!CALL_P (old_insn));
++	}
++      break;
++    }
++
++  i = peep2_buf_position (peep2_current + match_len);
++
++  note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
++
++  /* Replace the old sequence with the new.  */
++  last = emit_insn_after_setloc (attempt,
++				 peep2_insn_data[i].insn,
++				 INSN_LOCATOR (peep2_insn_data[i].insn));
++  before_try = PREV_INSN (insn);
++  delete_insn_chain (insn, peep2_insn_data[i].insn, false);
++
++  /* Re-insert the EH_REGION notes.  */
++  if (note || (was_call && nonlocal_goto_handler_labels))
++    {
++      edge eh_edge;
++      edge_iterator ei;
++
++      FOR_EACH_EDGE (eh_edge, ei, bb->succs)
++	if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
++	  break;
++
++      if (note)
++	copy_reg_eh_region_note_backward (note, last, before_try);
++
++      if (eh_edge)
++	for (x = last; x != before_try; x = PREV_INSN (x))
++	  if (x != BB_END (bb)
++	      && (can_throw_internal (x)
++		  || can_nonlocal_goto (x)))
++	    {
++	      edge nfte, nehe;
++	      int flags;
++
++	      nfte = split_block (bb, x);
++	      flags = (eh_edge->flags
++		       & (EDGE_EH | EDGE_ABNORMAL));
++	      if (CALL_P (x))
++		flags |= EDGE_ABNORMAL_CALL;
++	      nehe = make_edge (nfte->src, eh_edge->dest,
++				flags);
++
++	      nehe->probability = eh_edge->probability;
++	      nfte->probability
++		= REG_BR_PROB_BASE - nehe->probability;
++
++	      peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
++	      bb = nfte->src;
++	      eh_edge = nehe;
++	    }
++
++      /* Converting possibly trapping insn to non-trapping is
++	 possible.  Zap dummy outgoing edges.  */
++      peep2_do_cleanup_cfg |= purge_dead_edges (bb);
++    }
++
++  /* If we generated a jump instruction, it won't have
++     JUMP_LABEL set.  Recompute after we're done.  */
++  for (x = last; x != before_try; x = PREV_INSN (x))
++    if (JUMP_P (x))
++      {
++	peep2_do_rebuild_jump_labels = true;
++	break;
++      }
++
++  return last;
++}
++
++/* After performing a replacement in basic block BB, fix up the life
++   information in our buffer.  LAST is the last of the insns that we
++   emitted as a replacement.  PREV is the insn before the start of
++   the replacement.  MATCH_LEN is the number of instructions that were
++   matched, and which now need to be replaced in the buffer.  */
++
++static void
++peep2_update_life (basic_block bb, int match_len, rtx last, rtx prev)
++{
++  int i = peep2_buf_position (peep2_current + match_len + 1);
++  rtx x;
++  regset_head live;
++
++  INIT_REG_SET (&live);
++  COPY_REG_SET (&live, peep2_insn_data[i].live_before);
++
++  gcc_assert (peep2_current_count >= match_len + 1);
++  peep2_current_count -= match_len + 1;
++
++  x = last;
++  do
++    {
++      if (INSN_P (x))
++	{
++	  df_insn_rescan (x);
++	  if (peep2_current_count < MAX_INSNS_PER_PEEP2)
++	    {
++	      peep2_current_count++;
++	      if (--i < 0)
++		i = MAX_INSNS_PER_PEEP2;
++	      peep2_insn_data[i].insn = x;
++	      df_simulate_one_insn_backwards (bb, x, &live);
++	      COPY_REG_SET (peep2_insn_data[i].live_before, &live);
++	    }
++	}
++      x = PREV_INSN (x);
++    }
++  while (x != prev);
++  CLEAR_REG_SET (&live);
++
++  peep2_current = i;
++}
++
++/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
++   Return true if we added it, false otherwise.  The caller will try to match
++   peepholes against the buffer if we return false; otherwise it will try to
++   add more instructions to the buffer.  */
++
++static bool
++peep2_fill_buffer (basic_block bb, rtx insn, regset live)
++{
++  int pos;
++
++  /* Once we have filled the maximum number of insns the buffer can hold,
++     allow the caller to match the insns against peepholes.  We wait until
++     the buffer is full in case the target has similar peepholes of different
++     length; we always want to match the longest if possible.  */
++  if (peep2_current_count == MAX_INSNS_PER_PEEP2)
++    return false;
++
++  /* If an insn has RTX_FRAME_RELATED_P set, peephole substitution would lose
++     the REG_FRAME_RELATED_EXPR that is attached.  */
++  if (RTX_FRAME_RELATED_P (insn))
++    {
++      /* Let the buffer drain first.  */
++      if (peep2_current_count > 0)
++	return false;
++      /* Step over the insn then return true without adding the insn
++	 to the buffer; this will cause us to process the next
++	 insn.  */
++      df_simulate_one_insn_forwards (bb, insn, live);
++      return true;
++    }
++
++  pos = peep2_buf_position (peep2_current + peep2_current_count);
++  peep2_insn_data[pos].insn = insn;
++  COPY_REG_SET (peep2_insn_data[pos].live_before, live);
++  peep2_current_count++;
++
++  df_simulate_one_insn_forwards (bb, insn, live);
++  return true;
++}
++
+ /* Perform the peephole2 optimization pass.  */
+ 
+ static void
+ peephole2_optimize (void)
+ {
+-  rtx insn, prev;
++  rtx insn;
+   bitmap live;
+   int i;
+   basic_block bb;
+-  bool do_cleanup_cfg = false;
+-  bool do_rebuild_jump_labels = false;
++
++  peep2_do_cleanup_cfg = false;
++  peep2_do_rebuild_jump_labels = false;
+ 
+   df_set_flags (DF_LR_RUN_DCE);
++  df_note_add_problem ();
+   df_analyze ();
+ 
+   /* Initialize the regsets we're going to use.  */
+@@ -3129,214 +3349,59 @@
+ 
+   FOR_EACH_BB_REVERSE (bb)
+     {
++      bool past_end = false;
++      int pos;
++
+       rtl_profile_for_bb (bb);
+ 
+       /* Start up propagation.  */
+-      bitmap_copy (live, DF_LR_OUT (bb));
+-      df_simulate_initialize_backwards (bb, live);
++      bitmap_copy (live, DF_LR_IN (bb));
++      df_simulate_initialize_forwards (bb, live);
+       peep2_reinit_state (live);
+ 
+-      for (insn = BB_END (bb); ; insn = prev)
++      insn = BB_HEAD (bb);
++      for (;;)
+ 	{
+-	  prev = PREV_INSN (insn);
+-	  if (NONDEBUG_INSN_P (insn))
+-	    {
+-	      rtx attempt, before_try, x;
+-	      int match_len;
+-	      rtx note;
+-	      bool was_call = false;
+-
+-	      /* Record this insn.  */
+-	      if (--peep2_current < 0)
+-		peep2_current = MAX_INSNS_PER_PEEP2;
+-	      if (peep2_current_count < MAX_INSNS_PER_PEEP2
+-		  && peep2_insn_data[peep2_current].insn == NULL_RTX)
+-		peep2_current_count++;
+-	      peep2_insn_data[peep2_current].insn = insn;
+-	      df_simulate_one_insn_backwards (bb, insn, live);
+-	      COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
++	  rtx attempt, head;
++	  int match_len;
+ 
+-	      if (RTX_FRAME_RELATED_P (insn))
+-		{
+-		  /* If an insn has RTX_FRAME_RELATED_P set, peephole
+-		     substitution would lose the
+-		     REG_FRAME_RELATED_EXPR that is attached.  */
+-		  peep2_reinit_state (live);
+-		  attempt = NULL;
+-		}
+-	      else
+-		/* Match the peephole.  */
+-		attempt = peephole2_insns (PATTERN (insn), insn, &match_len);
+-
+-	      if (attempt != NULL)
+-		{
+-		  /* If we are splitting a CALL_INSN, look for the CALL_INSN
+-		     in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
+-		     cfg-related call notes.  */
+-		  for (i = 0; i <= match_len; ++i)
+-		    {
+-		      int j;
+-		      rtx old_insn, new_insn, note;
+-
+-		      j = i + peep2_current;
+-		      if (j >= MAX_INSNS_PER_PEEP2 + 1)
+-			j -= MAX_INSNS_PER_PEEP2 + 1;
+-		      old_insn = peep2_insn_data[j].insn;
+-		      if (!CALL_P (old_insn))
+-			continue;
+-		      was_call = true;
+-
+-		      new_insn = attempt;
+-		      while (new_insn != NULL_RTX)
+-			{
+-			  if (CALL_P (new_insn))
+-			    break;
+-			  new_insn = NEXT_INSN (new_insn);
+-			}
+-
+-		      gcc_assert (new_insn != NULL_RTX);
+-
+-		      CALL_INSN_FUNCTION_USAGE (new_insn)
+-			= CALL_INSN_FUNCTION_USAGE (old_insn);
+-
+-		      for (note = REG_NOTES (old_insn);
+-			   note;
+-			   note = XEXP (note, 1))
+-			switch (REG_NOTE_KIND (note))
+-			  {
+-			  case REG_NORETURN:
+-			  case REG_SETJMP:
+-			    add_reg_note (new_insn, REG_NOTE_KIND (note),
+-					  XEXP (note, 0));
+-			    break;
+-			  default:
+-			    /* Discard all other reg notes.  */
+-			    break;
+-			  }
+-
+-		      /* Croak if there is another call in the sequence.  */
+-		      while (++i <= match_len)
+-			{
+-			  j = i + peep2_current;
+-			  if (j >= MAX_INSNS_PER_PEEP2 + 1)
+-			    j -= MAX_INSNS_PER_PEEP2 + 1;
+-			  old_insn = peep2_insn_data[j].insn;
+-			  gcc_assert (!CALL_P (old_insn));
+-			}
+-		      break;
+-		    }
+-
+-		  i = match_len + peep2_current;
+-		  if (i >= MAX_INSNS_PER_PEEP2 + 1)
+-		    i -= MAX_INSNS_PER_PEEP2 + 1;
+-
+-		  note = find_reg_note (peep2_insn_data[i].insn,
+-					REG_EH_REGION, NULL_RTX);
+-
+-		  /* Replace the old sequence with the new.  */
+-		  attempt = emit_insn_after_setloc (attempt,
+-						    peep2_insn_data[i].insn,
+-				       INSN_LOCATOR (peep2_insn_data[i].insn));
+-		  before_try = PREV_INSN (insn);
+-		  delete_insn_chain (insn, peep2_insn_data[i].insn, false);
+-
+-		  /* Re-insert the EH_REGION notes.  */
+-		  if (note || (was_call && nonlocal_goto_handler_labels))
+-		    {
+-		      edge eh_edge;
+-		      edge_iterator ei;
+-
+-		      FOR_EACH_EDGE (eh_edge, ei, bb->succs)
+-			if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
+-			  break;
+-
+-		      if (note)
+-			copy_reg_eh_region_note_backward (note, attempt,
+-							  before_try);
+-
+-		      if (eh_edge)
+-			for (x = attempt ; x != before_try ; x = PREV_INSN (x))
+-			  if (x != BB_END (bb)
+-			      && (can_throw_internal (x)
+-				  || can_nonlocal_goto (x)))
+-			    {
+-			      edge nfte, nehe;
+-			      int flags;
+-
+-			      nfte = split_block (bb, x);
+-			      flags = (eh_edge->flags
+-				       & (EDGE_EH | EDGE_ABNORMAL));
+-			      if (CALL_P (x))
+-				flags |= EDGE_ABNORMAL_CALL;
+-			      nehe = make_edge (nfte->src, eh_edge->dest,
+-						flags);
+-
+-			      nehe->probability = eh_edge->probability;
+-			      nfte->probability
+-				= REG_BR_PROB_BASE - nehe->probability;
+-
+-			      do_cleanup_cfg |= purge_dead_edges (nfte->dest);
+-			      bb = nfte->src;
+-			      eh_edge = nehe;
+-			    }
+-
+-		      /* Converting possibly trapping insn to non-trapping is
+-			 possible.  Zap dummy outgoing edges.  */
+-		      do_cleanup_cfg |= purge_dead_edges (bb);
+-		    }
++	  if (!past_end && !NONDEBUG_INSN_P (insn))
++	    {
++	    next_insn:
++	      insn = NEXT_INSN (insn);
++	      if (insn == NEXT_INSN (BB_END (bb)))
++		past_end = true;
++	      continue;
++	    }
++	  if (!past_end && peep2_fill_buffer (bb, insn, live))
++	    goto next_insn;
+ 
+-		  if (targetm.have_conditional_execution ())
+-		    {
+-		      for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+-			peep2_insn_data[i].insn = NULL_RTX;
+-		      peep2_insn_data[peep2_current].insn = PEEP2_EOB;
+-		      peep2_current_count = 0;
+-		    }
+-		  else
+-		    {
+-		      /* Back up lifetime information past the end of the
+-			 newly created sequence.  */
+-		      if (++i >= MAX_INSNS_PER_PEEP2 + 1)
+-			i = 0;
+-		      bitmap_copy (live, peep2_insn_data[i].live_before);
+-
+-		      /* Update life information for the new sequence.  */
+-		      x = attempt;
+-		      do
+-			{
+-			  if (INSN_P (x))
+-			    {
+-			      if (--i < 0)
+-				i = MAX_INSNS_PER_PEEP2;
+-			      if (peep2_current_count < MAX_INSNS_PER_PEEP2
+-				  && peep2_insn_data[i].insn == NULL_RTX)
+-				peep2_current_count++;
+-			      peep2_insn_data[i].insn = x;
+-			      df_insn_rescan (x);
+-			      df_simulate_one_insn_backwards (bb, x, live);
+-			      bitmap_copy (peep2_insn_data[i].live_before,
+-					   live);
+-			    }
+-			  x = PREV_INSN (x);
+-			}
+-		      while (x != prev);
++	  /* If we did not fill an empty buffer, it signals the end of the
++	     block.  */
++	  if (peep2_current_count == 0)
++	    break;
+ 
+-		      peep2_current = i;
+-		    }
++	  /* The buffer filled to the current maximum, so try to match.  */
+ 
+-		  /* If we generated a jump instruction, it won't have
+-		     JUMP_LABEL set.  Recompute after we're done.  */
+-		  for (x = attempt; x != before_try; x = PREV_INSN (x))
+-		    if (JUMP_P (x))
+-		      {
+-		        do_rebuild_jump_labels = true;
+-			break;
+-		      }
+-		}
++	  pos = peep2_buf_position (peep2_current + peep2_current_count);
++	  peep2_insn_data[pos].insn = PEEP2_EOB;
++	  COPY_REG_SET (peep2_insn_data[pos].live_before, live);
++
++	  /* Match the peephole.  */
++	  head = peep2_insn_data[peep2_current].insn;
++	  attempt = peephole2_insns (PATTERN (head), head, &match_len);
++	  if (attempt != NULL)
++	    {
++	      rtx last;
++	      last = peep2_attempt (bb, head, match_len, attempt);
++	      peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
++	    }
++	  else
++	    {
++	      /* If no match, advance the buffer by one insn.  */
++	      peep2_current = peep2_buf_position (peep2_current + 1);
++	      peep2_current_count--;
+ 	    }
+-
+-	  if (insn == BB_HEAD (bb))
+-	    break;
+ 	}
+     }
+ 
+@@ -3344,7 +3409,7 @@
+   for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
+     BITMAP_FREE (peep2_insn_data[i].live_before);
+   BITMAP_FREE (live);
+-  if (do_rebuild_jump_labels)
++  if (peep2_do_rebuild_jump_labels)
+     rebuild_jump_labels (get_insns ());
+ }
+ #endif /* HAVE_peephole2 */
+Index: gcc-4_5-branch/gcc/recog.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/recog.h	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/recog.h	2012-03-06 12:51:20.000547582 -0800
+@@ -194,6 +194,9 @@
+   /* Gives the constraint string for operand N.  */
+   const char *constraints[MAX_RECOG_OPERANDS];
+ 
++  /* Nonzero if operand N is a match_operator or a match_parallel.  */
++  char is_operator[MAX_RECOG_OPERANDS];
++
+   /* Gives the mode of operand N.  */
+   enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
+ 
+@@ -260,6 +263,8 @@
+ 
+   const char strict_low;
+ 
++  const char is_operator;
++
+   const char eliminable;
+ };
+ 
+Index: gcc-4_5-branch/gcc/reload.c
+===================================================================
+--- gcc-4_5-branch.orig/gcc/reload.c	2012-03-06 11:53:32.000000000 -0800
++++ gcc-4_5-branch/gcc/reload.c	2012-03-06 12:51:20.004547561 -0800
+@@ -3631,7 +3631,7 @@
+ 		   || modified[j] != RELOAD_WRITE)
+ 		  && j != i
+ 		  /* Ignore things like match_operator operands.  */
+-		  && *recog_data.constraints[j] != 0
++		  && !recog_data.is_operator[j]
+ 		  /* Don't count an input operand that is constrained to match
+ 		     the early clobber operand.  */
+ 		  && ! (this_alternative_matches[j] == i
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99478.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99478.patch
new file mode 100644
index 0000000000..38463a9b40
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99478.patch
@@ -0,0 +1,74 @@
+2011-01-11  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/arm/t-arm: Fix up last commit.
+
+2011-01-11  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/arm/t-arm: Update MD_INCLUDES to include
+	all the files correctly.
+	* config/arm/arm.md: Update comments.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-02-22 11:38:56 +0000
++++ new/gcc/config/arm/arm.md	2011-03-01 14:32:39 +0000
+@@ -11246,6 +11246,7 @@
+   "
+ )
+ 
++;; Make sure that the includes are reflected in MD_INCLUDES.
+ ;; Load the load/store multiple patterns
+ (include "ldmstm.md")
+ ;; Load the FPA co-processor patterns
+
+=== modified file 'gcc/config/arm/t-arm'
+--- old/gcc/config/arm/t-arm	2010-08-16 09:41:58 +0000
++++ new/gcc/config/arm/t-arm	2011-01-11 21:01:30 +0000
+@@ -18,20 +18,33 @@
+ # along with GCC; see the file COPYING3.  If not see
+ # <http://www.gnu.org/licenses/>.
+ 
+-MD_INCLUDES= 	$(srcdir)/config/arm/arm-tune.md \
+-		$(srcdir)/config/arm/predicates.md \
+-		$(srcdir)/config/arm/arm-generic.md \
+-		$(srcdir)/config/arm/arm1020e.md \
+-		$(srcdir)/config/arm/arm1026ejs.md \
+-		$(srcdir)/config/arm/arm1136jfs.md \
+-		$(srcdir)/config/arm/arm926ejs.md \
+-		$(srcdir)/config/arm/cirrus.md \
+-		$(srcdir)/config/arm/fpa.md \
+-		$(srcdir)/config/arm/vec-common.md \
+-		$(srcdir)/config/arm/iwmmxt.md \
+-		$(srcdir)/config/arm/vfp.md \
+-		$(srcdir)/config/arm/neon.md \
+-		$(srcdir)/config/arm/thumb2.md
++MD_INCLUDES=	$(srcdir)/config/arm/arm-tune.md          	\
++		$(srcdir)/config/arm/predicates.md		\
++		$(srcdir)/config/arm/arm-generic.md       	\
++	 	$(srcdir)/config/arm/arm1020e.md          	\
++	 	$(srcdir)/config/arm/arm1026ejs.md        	\
++		$(srcdir)/config/arm/arm1136jfs.md        	\
++	 	$(srcdir)/config/arm/arm926ejs.md         	\
++		$(srcdir)/config/arm/cirrus.md            	\
++		$(srcdir)/config/arm/fpa.md               	\
++		$(srcdir)/config/arm/vec-common.md        	\
++		$(srcdir)/config/arm/iwmmxt.md            	\
++		$(srcdir)/config/arm/vfp.md               	\
++	 	$(srcdir)/config/arm/cortex-a5.md         	\
++		$(srcdir)/config/arm/cortex-a8.md         	\
++		$(srcdir)/config/arm/cortex-a9.md         	\
++		$(srcdir)/config/arm/cortex-a9-neon.md		\
++		$(srcdir)/config/arm/cortex-r4.md         	\
++		$(srcdir)/config/arm/cortex-r4f.md        	\
++		$(srcdir)/config/arm/cortex-m4.md         	\
++		$(srcdir)/config/arm/cortex-m4-fpu.md     	\
++		$(srcdir)/config/arm/vfp11.md             	\
++		$(srcdir)/config/arm/ldmstm.md            	\
++		$(srcdir)/config/arm/thumb2.md            	\
++		$(srcdir)/config/arm/neon.md              	\
++		$(srcdir)/config/arm/sync.md              	\
++		$(srcdir)/config/arm/cortex-a8-neon.md    	\
++		$(srcdir)/config/arm/constraints.md       	
+ 
+ LIB1ASMSRC = arm/lib1funcs.asm
+ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch
new file mode 100644
index 0000000000..2920466d8f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch
@@ -0,0 +1,101 @@
+2011-02-24  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2010-08-10  Bernd Schmidt  <bernds@codesourcery.com>
+
+	PR bootstrap/45177
+	* config/arm/arm.c (multiple_operation_profitable_p): Move xscale
+	test here from arm_gen_load_multiple_1.
+	(arm_gen_load_multiple_1, arm_gen_store_multiple_1): Use
+	multiple_operation_profitable_p.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-02-22 11:38:56 +0000
++++ new/gcc/config/arm/arm.c	2011-02-24 17:30:32 +0000
+@@ -9728,6 +9728,36 @@
+   if (nops == 2 && arm_ld_sched && add_offset != 0)
+     return false;
+ 
++  /* XScale has load-store double instructions, but they have stricter
++     alignment requirements than load-store multiple, so we cannot
++     use them.
++
++     For XScale ldm requires 2 + NREGS cycles to complete and blocks
++     the pipeline until completion.
++
++	NREGS		CYCLES
++	  1		  3
++	  2		  4
++	  3		  5
++	  4		  6
++
++     An ldr instruction takes 1-3 cycles, but does not block the
++     pipeline.
++
++	NREGS		CYCLES
++	  1		 1-3
++	  2		 2-6
++	  3		 3-9
++	  4		 4-12
++
++     Best case ldr will always win.  However, the more ldr instructions
++     we issue, the less likely we are to be able to schedule them well.
++     Using ldr instructions also increases code size.
++
++     As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
++     for counts of 3 or 4 regs.  */
++  if (nops <= 2 && arm_tune_xscale && !optimize_size)
++    return false;
+   return true;
+ }
+ 
+@@ -10086,35 +10116,7 @@
+   int i = 0, j;
+   rtx result;
+ 
+-  /* XScale has load-store double instructions, but they have stricter
+-     alignment requirements than load-store multiple, so we cannot
+-     use them.
+-
+-     For XScale ldm requires 2 + NREGS cycles to complete and blocks
+-     the pipeline until completion.
+-
+-	NREGS		CYCLES
+-	  1		  3
+-	  2		  4
+-	  3		  5
+-	  4		  6
+-
+-     An ldr instruction takes 1-3 cycles, but does not block the
+-     pipeline.
+-
+-	NREGS		CYCLES
+-	  1		 1-3
+-	  2		 2-6
+-	  3		 3-9
+-	  4		 4-12
+-
+-     Best case ldr will always win.  However, the more ldr instructions
+-     we issue, the less likely we are to be able to schedule them well.
+-     Using ldr instructions also increases code size.
+-
+-     As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
+-     for counts of 3 or 4 regs.  */
+-  if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
++  if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0))
+     {
+       rtx seq;
+ 
+@@ -10166,9 +10168,7 @@
+   if (GET_CODE (basereg) == PLUS)
+     basereg = XEXP (basereg, 0);
+ 
+-  /* See arm_gen_load_multiple_1 for discussion of
+-     the pros/cons of ldm/stm usage for XScale.  */
+-  if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
++  if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0))
+     {
+       rtx seq;
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99480.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99480.patch
new file mode 100644
index 0000000000..76d3c9565c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99480.patch
@@ -0,0 +1,64 @@
+2011-02-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+
+	gcc/
+	PR target/47551
+	* config/arm/arm.c (coproc_secondary_reload_class): Handle
+	structure modes.  Don't check neon_vector_mem_operand for
+	vector or structure modes.
+
+	gcc/testsuite/
+	PR target/47551
+	* gcc.target/arm/neon-modes-2.c: New test.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-02-24 17:30:32 +0000
++++ new/gcc/config/arm/arm.c	2011-03-02 11:29:06 +0000
+@@ -9303,11 +9303,14 @@
+       return GENERAL_REGS;
+     }
+ 
++  /* The neon move patterns handle all legitimate vector and struct
++     addresses.  */
+   if (TARGET_NEON
++      && MEM_P (x)
+       && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+-          || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+-      && neon_vector_mem_operand (x, 0))
+-     return NO_REGS;
++	  || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
++	  || VALID_NEON_STRUCT_MODE (mode)))
++    return NO_REGS;
+ 
+   if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
+     return NO_REGS;
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-2.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-modes-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-modes-2.c	2011-02-02 13:48:10 +0000
+@@ -0,0 +1,24 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O1" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20)
++#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1)
++#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A)
++
++#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5)
++
++void
++bar (uint32_t *ptr, int y)
++{
++  uint32x2x3_t MANY (SETUP);
++  int *x = __builtin_alloca (y);
++  int z[0x1000];
++  foo (x, z);
++  MANY (MODIFY);
++  foo (x, z);
++  MANY (STORE);
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99483.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99483.patch
new file mode 100644
index 0000000000..c0be4a03b1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99483.patch
@@ -0,0 +1,63 @@
+2011-02-11  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* cse.c (count_reg_usage): Check side_effects_p.  Remove the
+	separate check for volatile asms.
+
+	gcc/testsuite/
+	* gcc.dg/torture/volatile-pic-1.c: New test.
+
+=== modified file 'gcc/cse.c'
+--- old/gcc/cse.c	2010-11-26 12:03:32 +0000
++++ new/gcc/cse.c	2011-02-11 09:27:19 +0000
+@@ -6634,9 +6634,10 @@
+     case CALL_INSN:
+     case INSN:
+     case JUMP_INSN:
+-      /* We expect dest to be NULL_RTX here.  If the insn may trap, mark
+-         this fact by setting DEST to pc_rtx.  */
+-      if (insn_could_throw_p (x))
++      /* We expect dest to be NULL_RTX here.  If the insn may trap,
++	 or if it cannot be deleted due to side-effects, mark this fact
++	 by setting DEST to pc_rtx.  */
++      if (insn_could_throw_p (x) || side_effects_p (PATTERN (x)))
+ 	dest = pc_rtx;
+       if (code == CALL_INSN)
+ 	count_reg_usage (CALL_INSN_FUNCTION_USAGE (x), counts, dest, incr);
+@@ -6676,10 +6677,6 @@
+       return;
+ 
+     case ASM_OPERANDS:
+-      /* If the asm is volatile, then this insn cannot be deleted,
+-	 and so the inputs *must* be live.  */
+-      if (MEM_VOLATILE_P (x))
+-	dest = NULL_RTX;
+       /* Iterate over just the inputs, not the constraints as well.  */
+       for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
+ 	count_reg_usage (ASM_OPERANDS_INPUT (x, i), counts, dest, incr);
+
+=== added file 'gcc/testsuite/gcc.dg/torture/volatile-pic-1.c'
+--- old/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c	2011-02-11 09:27:19 +0000
+@@ -0,0 +1,20 @@
++/* { dg-do run } */
++/* { dg-require-visibility "" } */
++/* { dg-require-effective-target fpic } */
++/* { dg-options "-fPIC" } */
++
++volatile int x __attribute__((visibility("hidden")));
++
++void __attribute__((noinline)) bar (void)
++{
++#if defined (__arm__)
++  asm volatile ("mov r3,%0" :: "r" (0xdeadbeef) : "r3");
++#endif
++  (void) x;
++}
++
++int main (void)
++{
++  bar ();
++  return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99486.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99486.patch
new file mode 100644
index 0000000000..e6b58ac872
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99486.patch
@@ -0,0 +1,230 @@
+2011-03-09  Bernd Schmidt  <bernds@codesourcery.com>
+
+	Issue #10649
+	gcc/
+	* dwarf2out.c (dwarf2out_begin_epilogue): Accept simplejumps
+	as well as returnjumps.
+	* cfganal.c (set_edge_can_fallthru_flag): Revert previous change
+	that tried to keep epilogue blocks adjacent.
+
+2011-02-03  Bernd Schmidt  <bernds@codesourcery.com>
+
+	gcc/
+	* function.c (prepare_shrink_wrap): New function.
+	(thread_prologue_and_epilogue_insns): Call it.
+
+=== modified file 'gcc/cfganal.c'
+--- old/gcc/cfganal.c	2011-02-08 10:51:58 +0000
++++ new/gcc/cfganal.c	2011-03-10 14:55:10 +0000
+@@ -271,37 +271,6 @@
+       EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU;
+       EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU;
+     }
+-  /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired
+-     with a return or a sibcall.  Ensure that this remains the case if
+-     they are in different basic blocks.  */
+-  FOR_EACH_BB (bb)
+-    {
+-      edge e;
+-      edge_iterator ei;
+-      rtx insn, end;
+-
+-      end = BB_END (bb);
+-      FOR_BB_INSNS (bb, insn)
+-	if (GET_CODE (insn) == NOTE
+-	    && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG
+-	    && !(CALL_P (end) && SIBLING_CALL_P (end))
+-	    && !returnjump_p (end))
+-	  {
+-	    basic_block other_bb = NULL;
+-	    FOR_EACH_EDGE (e, ei, bb->succs)
+-	      {
+-		if (e->flags & EDGE_FALLTHRU)
+-		  other_bb = e->dest;
+-		else
+-		  e->flags &= ~EDGE_CAN_FALLTHRU;
+-	      }
+-	    FOR_EACH_EDGE (e, ei, other_bb->preds)
+-	      {
+-		if (!(e->flags & EDGE_FALLTHRU))
+-		  e->flags &= ~EDGE_CAN_FALLTHRU;
+-	      }	    
+-	  }
+-    }
+ }
+ 
+ /* Find unreachable blocks.  An unreachable block will have 0 in
+
+=== modified file 'gcc/dwarf2out.c'
+--- old/gcc/dwarf2out.c	2011-02-08 10:51:58 +0000
++++ new/gcc/dwarf2out.c	2011-03-10 14:55:10 +0000
+@@ -2782,10 +2782,10 @@
+   dwarf2out_frame_debug_expr (insn, label);
+ }
+ 
+-/* Determine if we need to save and restore CFI information around this
+-   epilogue.  If SIBCALL is true, then this is a sibcall epilogue.  If
+-   we do need to save/restore, then emit the save now, and insert a
+-   NOTE_INSN_CFA_RESTORE_STATE at the appropriate place in the stream.  */
++/* Determine if we need to save and restore CFI information around
++   this epilogue.  If we do need to save/restore, then emit the save
++   now, and insert a NOTE_INSN_CFA_RESTORE_STATE at the appropriate
++   place in the stream.  */
+ 
+ void
+ dwarf2out_begin_epilogue (rtx insn)
+@@ -2800,8 +2800,10 @@
+       if (!INSN_P (i))
+ 	continue;
+ 
+-      /* Look for both regular and sibcalls to end the block.  */
+-      if (returnjump_p (i))
++      /* Look for both regular and sibcalls to end the block.  Various
++	 optimization passes may cause us to jump to a common epilogue
++	 tail, so we also accept simplejumps.  */
++      if (returnjump_p (i) || simplejump_p (i))
+ 	break;
+       if (CALL_P (i) && SIBLING_CALL_P (i))
+ 	break;
+
+=== modified file 'gcc/function.c'
+--- old/gcc/function.c	2011-02-08 10:51:58 +0000
++++ new/gcc/function.c	2011-03-10 14:55:10 +0000
+@@ -5038,6 +5038,127 @@
+       return true;
+   return false;
+ }
++
++/* Look for sets of call-saved registers in the first block of the
++   function, and move them down into successor blocks if the register
++   is used only on one path.  This exposes more opportunities for
++   shrink-wrapping.
++   These kinds of sets often occur when incoming argument registers are
++   moved to call-saved registers because their values are live across
++   one or more calls during the function.  */
++
++static void
++prepare_shrink_wrap (basic_block entry_block)
++{
++  rtx insn, curr;
++  FOR_BB_INSNS_SAFE (entry_block, insn, curr)
++    {
++      basic_block next_bb;
++      edge e, live_edge;
++      edge_iterator ei;
++      rtx set, scan;
++      unsigned destreg, srcreg;
++
++      if (!NONDEBUG_INSN_P (insn))
++	continue;
++      set = single_set (insn);
++      if (!set)
++	continue;
++
++      if (!REG_P (SET_SRC (set)) || !REG_P (SET_DEST (set)))
++	continue;
++      srcreg = REGNO (SET_SRC (set));
++      destreg = REGNO (SET_DEST (set));
++      if (hard_regno_nregs[srcreg][GET_MODE (SET_SRC (set))] > 1
++	  || hard_regno_nregs[destreg][GET_MODE (SET_DEST (set))] > 1)
++	continue;
++
++      next_bb = entry_block;
++      scan = insn;
++
++      for (;;)
++	{
++	  live_edge = NULL;
++	  FOR_EACH_EDGE (e, ei, next_bb->succs)
++	    {
++	      if (REGNO_REG_SET_P (df_get_live_in (e->dest), destreg))
++		{
++		  if (live_edge)
++		    {
++		      live_edge = NULL;
++		      break;
++		    }
++		  live_edge = e;
++		}
++	    }
++	  if (!live_edge)
++	    break;
++	  /* We can sometimes encounter dead code.  Don't try to move it
++	     into the exit block.  */
++	  if (live_edge->dest == EXIT_BLOCK_PTR)
++	    break;
++	  if (EDGE_COUNT (live_edge->dest->preds) > 1)
++	    break;
++	  while (scan != BB_END (next_bb))
++	    {
++	      scan = NEXT_INSN (scan);
++	      if (NONDEBUG_INSN_P (scan))
++		{
++		  rtx link;
++		  HARD_REG_SET set_regs;
++
++		  CLEAR_HARD_REG_SET (set_regs);
++		  note_stores (PATTERN (scan), record_hard_reg_sets,
++			       &set_regs);
++		  if (CALL_P (scan))
++		    IOR_HARD_REG_SET (set_regs, call_used_reg_set);
++		  for (link = REG_NOTES (scan); link; link = XEXP (link, 1))
++		    if (REG_NOTE_KIND (link) == REG_INC)
++		      record_hard_reg_sets (XEXP (link, 0), NULL, &set_regs);
++
++		  if (TEST_HARD_REG_BIT (set_regs, srcreg)
++		      || reg_referenced_p (SET_DEST (set),
++					   PATTERN (scan)))
++		    {
++		      scan = NULL_RTX;
++		      break;
++		    }
++		  if (CALL_P (scan))
++		    {
++		      rtx link = CALL_INSN_FUNCTION_USAGE (scan);
++		      while (link)
++			{
++			  rtx tmp = XEXP (link, 0);
++			  if (GET_CODE (tmp) == USE
++			      && reg_referenced_p (SET_DEST (set), tmp))
++			    break;
++			  link = XEXP (link, 1);
++			}
++		      if (link)
++			{
++			  scan = NULL_RTX;
++			  break;
++			}
++		    }
++		}
++	    }
++	  if (!scan)
++	    break;
++	  next_bb = live_edge->dest;
++	}
++
++      if (next_bb != entry_block)
++	{
++	  rtx after = BB_HEAD (next_bb);
++	  while (!NOTE_P (after)
++		 || NOTE_KIND (after) != NOTE_INSN_BASIC_BLOCK)
++	    after = NEXT_INSN (after);
++	  emit_insn_after (PATTERN (insn), after);
++	  delete_insn (insn);
++	}
++    }
++}
++
+ #endif
+ 
+ #ifdef HAVE_return
+@@ -5215,6 +5336,8 @@
+       bitmap_head bb_antic_flags;
+       bitmap_head bb_on_list;
+ 
++      prepare_shrink_wrap (entry_edge->dest);
++
+       bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack);
+       bitmap_initialize (&bb_on_list, &bitmap_default_obstack);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99487.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99487.patch
new file mode 100644
index 0000000000..186c17717f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99487.patch
@@ -0,0 +1,42 @@
+2011-03-11  Andrew Stubbs  <ams@codesourcery.com>
+	    Michael Hope  <michael.hope@linaro.org>
+	    Matthias Klose  <doko@ubuntu.org>
+
+	gcc/
+	* function. (thread_prologue_and_epilogue_insns): Initialize
+	prologue_seq.
+	* opts.c (decode_options): Move flag_shrink_wrap to -O1.
+
+=== modified file 'gcc/function.c'
+--- old/gcc/function.c	2011-03-10 14:55:10 +0000
++++ new/gcc/function.c	2011-03-11 10:35:05 +0000
+@@ -5252,6 +5252,8 @@
+   edge_iterator ei;
+   bitmap_head bb_flags;
+ 
++  prologue_seq = NULL_RTX;
++
+   df_analyze ();
+ 
+   rtl_profile_for_bb (ENTRY_BLOCK_PTR);
+
+=== modified file 'gcc/opts.c'
+--- old/gcc/opts.c	2011-02-08 10:51:58 +0000
++++ new/gcc/opts.c	2011-03-11 10:35:05 +0000
+@@ -877,6 +877,7 @@
+   flag_tree_copy_prop = opt1;
+   flag_tree_sink = opt1;
+   flag_tree_ch = opt1;
++  flag_shrink_wrap = opt1;
+ 
+   /* -O2 optimizations.  */
+   opt2 = (optimize >= 2);
+@@ -909,7 +910,6 @@
+   flag_ipa_cp = opt2;
+   flag_ipa_sra = opt2;
+   flag_ee = opt2;
+-  flag_shrink_wrap = opt2;
+ 
+   /* Track fields in field-sensitive alias analysis.  */
+   set_param_value ("max-fields-for-field-sensitive",
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99488.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99488.patch
new file mode 100644
index 0000000000..2f41a0a73c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99488.patch
@@ -0,0 +1,22 @@
+2011-03-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* ee.c (reg_use_p): Handle subregs of promoted vars.
+
+=== modified file 'gcc/ee.c'
+--- old/gcc/ee.c	2010-12-10 15:33:37 +0000
++++ new/gcc/ee.c	2011-03-03 17:08:58 +0000
+@@ -209,7 +209,11 @@
+ 
+       *regno = REGNO (reg);
+ 
+-      if (paradoxical_subreg_p (use))
++      /* Non-paradoxical SUBREGs of promoted vars guarantee that the
++	 upper (elided) bits of the inner register have a particular value.
++	 For our purposes, such SUBREGs act as a full reference to the
++	 inner register.  */
++      if (paradoxical_subreg_p (use) || SUBREG_PROMOTED_VAR_P (use))
+         *size = GET_MODE_BITSIZE (GET_MODE (reg));
+       else
+         *size = subreg_lsb (use) + GET_MODE_BITSIZE (GET_MODE (use));
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99489.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99489.patch
new file mode 100644
index 0000000000..12fb56ad02
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99489.patch
@@ -0,0 +1,61 @@
+2011-03-10  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	LP:730440
+	PR target/47668
+	gcc/
+	* config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c'.
+	gcc/testsuite/
+	* gcc.target/arm/pr47688.c: New.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-03-01 14:32:39 +0000
++++ new/gcc/config/arm/arm.md	2011-03-11 14:26:34 +0000
+@@ -11133,13 +11133,15 @@
+   [(set_attr "conds" "clob")]
+ )
+ 
++;; We only care about the lower 16 bits of the constant 
++;; being inserted into the upper 16 bits of the register.
+ (define_insn "*arm_movtas_ze" 
+   [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
+                    (const_int 16)
+                    (const_int 16))
+         (match_operand:SI 1 "const_int_operand" ""))]
+   "arm_arch_thumb2"
+-  "movt%?\t%0, %c1"
++  "movt%?\t%0, %L1"
+  [(set_attr "predicable" "yes")
+    (set_attr "length" "4")]
+ )
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr47688.c'
+--- old/gcc/testsuite/gcc.target/arm/pr47688.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr47688.c	2011-03-11 14:26:34 +0000
+@@ -0,0 +1,26 @@
++/* { dg-options "-mthumb -O2" }  */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-final { scan-assembler-not "-32768" } } */
++
++typedef union
++{
++  unsigned long int u_32_value;
++  struct 
++  {
++    unsigned short int u_16_value_0;
++    unsigned short int u_16_value_1;
++  } u_16_values;
++} my_union;
++
++
++unsigned long int Test(const unsigned short int wXe)
++{
++  my_union dwCalcVal;
++  
++  dwCalcVal.u_16_values.u_16_value_0=wXe;
++  dwCalcVal.u_16_values.u_16_value_1=0x8000u;
++
++  dwCalcVal.u_32_value /=3;
++  
++  return (dwCalcVal.u_32_value);
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99494.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99494.patch
new file mode 100644
index 0000000000..56897e984b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99494.patch
@@ -0,0 +1,1272 @@
+2011-04-09  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+
+	Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	* config.sub: Recognize *-linux-android*.
+
+	2010-05-27 Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	Add support for Bionic C library
+	gcc/
+	* config.gcc (LIBC_GLIBC, LIBC_BIONIC, LIBC_UCLIBC): New tm_define
+	macro.
+	(DEFAULT_LIBC): New tm_define macro set to one of LIBC_*.
+	(bfin*-uclinux, moxie-*-uclinux*, m68k-*-uclinux*): Update.
+
+	* config/linux.h (OPTION_GLIBC, OPTION_UCLIBC, OPTION_BIONIC): Define.
+	(LINUX_TARGET_OS_CPP_BUILTINS): Define __gnu_linux__ only for GLIBC.
+	(CHOOSE_DYNAMIC_LINKER1, CHOOSE_DYNAMIC_LINKER): Make it easier
+	to support multiple C libraries.  Handle Bionic.
+	(BIONIC_DYNAMIC_LINKER, BIONIC_DYNAMIC_LINKER32,)
+	(BIONIC_DYNAMIC_LINKER64): Define.
+	(LINUX_DYNAMIC_LINKER, LINUX_DYNAMIC_LINKER32, LINUX_DYNAMIC_LINKER64):
+	Update.
+	(TARGET_HAS_SINCOS): Enable for Bionic.
+
+	* config/linux.opt: Rewrite to handle more than 2 C libraries.  Make
+	the last option specified on command line take effect.
+	(linux_uclibc): Rename to linux_libc, initialize using DEFAULT_LIBC.
+	(mbionic): New.
+	(mglibc, muclibc): Update.
+
+	* config/alpha/linux-elf.h, config/rs6000/linux64.h,
+	* config/rs6000/sysv4.h (CHOOSE_DYNAMIC_LINKER): Update to use
+	DEFAULT_LIBC.
+
+	* doc/invoke.texi (-mglibc, -muclibc): Update.
+	(-mbionic): Document.
+
+	gcc/testsuite/
+	* gcc.dg/glibc-uclibc-1.c, gcc.dg/glibc-uclibc-2.c: Remove, no longer
+	necessary.
+
+	2010-05-27 Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	Support compilation for Android platform.  Reimplement -mandroid.
+	gcc/
+	* config.gcc (*linux*): Include linux-android.h and linux-android.opt.
+	(*android*): Set ANDROID_DEFAULT.
+	(arm*-*-linux*): Include linux-android.h.
+	(arm*-*-eabi*): Don't include previous -mandroid implementation.
+	* config/arm/eabi.h: Remove, move Android-specific parts ...
+	* config/linux-android.h: ... here.  New file.
+	* config/arm/eabi.opt: Rename to ...
+	* config/linux-android.opt: ... this.
+	(mandroid): Allow -mno-android option.  Initialize based on
+	ANDROID_DEFAULT.
+	* config/linux.h (STARTFILE_SPEC, ENDFILE_SPEC, CC1_SPEC, LIB_SPEC):
+	Move logic to corresponding LINUX_TARGET_* macros.
+	(TARGET_OS_CPP_BUILTINS): Define __ANDROID__, when appropriate.
+	* config/linux-eabi.h (LINK_SPEC, CC1_SPEC, CC1PLUS_SPEC, LIB_SPEC,)
+	(STARTFILE_SPEC, ENDFILE_SPEC): Define to choose between Linux and
+	Android definitions.
+	(LINUX_TARGET_OS_CPP_BUILTINS): Define __ANDROID__ if TARGET_ANDROID.
+	* doc/invoke.texi (-mandroid, -tno-android-cc, -tno-android-ld):
+	Document.
+
+	2010-06-01 Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	gcc/
+	* config/arm/t-linux-androideabi: New.
+	* config.gcc (arm*-*-linux-androideabi): Include multilib configuration.
+
+	2010-05-27 Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	gcc/
+	* gthr-posix.h (pthread_cancel): Don't declare if compiling against
+	Bionic C library.
+	(__gthread_active_p): Check for pthread_create if compiling against
+	Bionic C library.
+
+	2010-06-01 Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	libstdc++-v3/
+	* acinclude.m4: Support Bionic C library.
+	Explicitly specify -fexceptions for exception check.
+	* configure.host: Support Bionic C library.
+	* configure: Regenerate.
+	* config/os/bionic/ctype_base.h, config/os/bionic/ctype_inline.h,
+	* config/os/bionic/ctype_noincline.h, config/os/bionic/os_defines.h:
+	New files, based on config/os/newlib/*.
+
+=== modified file 'config.sub'
+Index: gcc-4.5.3/config.sub
+===================================================================
+--- gcc-4.5.3.orig/config.sub
++++ gcc-4.5.3/config.sub
+@@ -4,7 +4,7 @@
+ #   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+ #   Free Software Foundation, Inc.
+ 
+-timestamp='2010-03-22'
++timestamp='2010-04-23'
+ 
+ # This file is (in principle) common to ALL GNU software.
+ # The presence of a machine in this file suggests that SOME GNU software
+@@ -124,8 +124,9 @@ esac
+ # Here we must recognize all the valid KERNEL-OS combinations.
+ maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
+ case $maybe_os in
+-  nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
+-  uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
++  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
++  linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
++  knetbsd*-gnu* | netbsd*-gnu* | \
+   kopensolaris*-gnu* | \
+   storm-chaos* | os2-emx* | rtmk-nova*)
+     os=-$maybe_os
+@@ -1307,7 +1308,8 @@ case $os in
+ 	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
+ 	      | -chorusos* | -chorusrdb* | -cegcc* \
+ 	      | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+-	      | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
++	      | -mingw32* | -linux-gnu* | -linux-android* \
++	      | -linux-newlib* | -linux-uclibc* \
+ 	      | -uxpv* | -beos* | -mpeix* | -udk* \
+ 	      | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
+ 	      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
+Index: gcc-4.5.3/gcc/config.gcc
+===================================================================
+--- gcc-4.5.3.orig/gcc/config.gcc
++++ gcc-4.5.3/gcc/config.gcc
+@@ -513,26 +513,48 @@ case ${target} in
+     *-*-gnu*)
+       tmake_file="$tmake_file t-gnu";;
+   esac
+-  # glibc / uclibc switch.  uclibc isn't usable for GNU/Hurd and neither for
+-  # GNU/k*BSD.
++  # Common C libraries.
++  tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3"
++  # glibc / uclibc / bionic switch.
++  # uclibc and bionic aren't usable for GNU/Hurd and neither for GNU/k*BSD.
+   case $target in
+     *linux*)
+       extra_options="$extra_options linux.opt";;
+     *)
+       tm_defines="$tm_defines OPTION_GLIBC=1";;
+   esac
+-  case ${target} in
++  case $target in
++    *-*-*android*)
++      tm_defines="$tm_defines DEFAULT_LIBC=LIBC_BIONIC"
++      ;;
+     *-*-*uclibc*)
+-      tm_defines="${tm_defines} UCLIBC_DEFAULT=1"
++      tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
+       ;;
+     *)
+-      tm_defines="${tm_defines} UCLIBC_DEFAULT=0"
++      tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC"
+       ;;
+   esac
+-  # Assume that glibc or uClibc are being used and so __cxa_atexit is provided.
++  # Assume that glibc or uClibc or Bionic are being used and so __cxa_atexit
++  # is provided.
+   default_use_cxa_atexit=yes
+   use_gcc_tgmath=no
+   use_gcc_stdint=wrap
++  # Add Android userspace support to Linux targets.
++  case $target in
++    *linux*)
++      tm_file="$tm_file linux-android.h"
++      extra_options="$extra_options linux-android.opt"
++      ;;
++  esac
++  # Enable compilation for Android by default for *android* targets.
++  case $target in
++    *-*-*android*)
++      tm_defines="$tm_defines ANDROID_DEFAULT=1"
++      ;;
++    *)
++      tm_defines="$tm_defines ANDROID_DEFAULT=0"
++      ;;
++  esac
+   ;;
+ *-*-netbsd*)
+   tmake_file="t-slibgcc-elf-ver t-libc-ok t-netbsd t-libgcc-pic"
+@@ -728,7 +750,7 @@ arm*-*-netbsd*)
+ 	use_collect2=yes
+ 	;;
+ arm*-*-linux*)			# ARM GNU/Linux with ELF
+-	tm_file="dbxelf.h elfos.h linux.h glibc-stdint.h arm/elf.h arm/linux-gas.h arm/linux-elf.h"
++	tm_file="dbxelf.h elfos.h linux.h linux-android.h glibc-stdint.h arm/elf.h arm/linux-gas.h arm/linux-elf.h"
+ 	case $target in
+ 	arm*b-*)
+ 		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+@@ -739,6 +761,12 @@ arm*-*-linux*)			# ARM GNU/Linux with EL
+ 	arm*-*-linux-*eabi)
+ 	    tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
+ 	    tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc"
++	    # Define multilib configuration for arm-linux-androideabi.
++	    case ${target} in
++	    *-androideabi)
++		tmake_file="$tmake_file arm/t-linux-androideabi"
++		;;
++	    esac
+   	    # The BPABI long long divmod functions return a 128-bit value in
+ 	    # registers r0-r3.  Correctly modeling that requires the use of
+ 	    # TImode.
+@@ -785,9 +813,8 @@ arm*-*-eabi* | arm*-*-symbianelf* )
+ 	tmake_file="arm/t-arm arm/t-arm-elf"
+ 	case ${target} in
+ 	arm*-*-eabi*)
+-	  tm_file="$tm_file arm/eabi.h newlib-stdint.h"
++	  tm_file="$tm_file newlib-stdint.h"
+ 	  tmake_file="${tmake_file} arm/t-bpabi"
+-	  extra_options="${extra_options} arm/eabi.opt"
+ 	  use_gcc_stdint=wrap
+ 	  ;;
+ 	arm*-*-symbianelf*)
+@@ -843,7 +870,7 @@ bfin*-elf*)
+ bfin*-uclinux*)
+ 	tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h linux.h glibc-stdint.h bfin/uclinux.h"
+ 	tmake_file=bfin/t-bfin-uclinux
+-	tm_defines="${tm_defines} UCLIBC_DEFAULT=1"
++	tm_defines="${tm_defines} DEFAULT_LIBC=LIBC_UCLIBC"
+ 	extra_options="${extra_options} linux.opt"
+ 	use_collect2=no
+ 	;;
+@@ -924,7 +951,7 @@ moxie-*-uclinux*)
+ 	tm_file="dbxelf.h elfos.h svr4.h ${tm_file} linux.h glibc-stdint.h moxie/uclinux.h"
+ 	extra_parts="crti.o crtn.o crtbegin.o crtend.o"
+ 	tmake_file="${tmake_file} moxie/t-moxie moxie/t-moxie-softfp soft-fp/t-softfp"
+-	tm_defines="${tm_defines} UCLIBC_DEFAULT=1"
++	tm_defines="${tm_defines} DEFAULT_LIBC=LIBC_UCLIBC"
+ 	extra_options="${extra_options} linux.opt"
+ 	;;
+ h8300-*-rtems*)
+@@ -1644,7 +1671,7 @@ m68k-*-uclinux*)		# Motorola m68k/ColdFi
+ 	default_m68k_cpu=68020
+ 	default_cf_cpu=5206
+ 	tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h flat.h m68k/linux.h m68k/uclinux.h ./sysroot-suffix.h"
+- 	tm_defines="${tm_defines} MOTOROLA=1 UCLIBC_DEFAULT=1"
++ 	tm_defines="${tm_defines} MOTOROLA=1 DEFAULT_LIBC=LIBC_UCLIBC"
+ 	extra_options="${extra_options} linux.opt"
+ 	tmake_file="m68k/t-floatlib m68k/t-uclinux m68k/t-mlibs"
+ 	;;
+Index: gcc-4.5.3/gcc/config/alpha/linux-elf.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/alpha/linux-elf.h
++++ gcc-4.5.3/gcc/config/alpha/linux-elf.h
+@@ -29,10 +29,12 @@ along with GCC; see the file COPYING3.
+ 
+ #define GLIBC_DYNAMIC_LINKER	"/lib/ld-linux.so.2"
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+-#if UCLIBC_DEFAULT
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}"
++#if DEFAULT_LIBC == LIBC_UCLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#elif DEFAULT_LIBC == LIBC_GLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
+ #else
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}"
++#error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define LINUX_DYNAMIC_LINKER \
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+Index: gcc-4.5.3/gcc/config/arm/eabi.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/eabi.h
++++ /dev/null
+@@ -1,125 +0,0 @@
+-/* Configuration file for ARM EABI targets.
+-   Copyright (C) 2008
+-   Free Software Foundation, Inc.
+-   Contributed by Doug Kwan (dougkwan@google.com)
+-
+-   This file is part of GCC.
+-
+-   GCC is free software; you can redistribute it and/or modify it
+-   under the terms of the GNU General Public License as published
+-   by the Free Software Foundation; either version 3, or (at your
+-   option) any later version.
+-
+-   GCC is distributed in the hope that it will be useful, but WITHOUT
+-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+-   License for more details.
+-
+-   You should have received a copy of the GNU General Public License
+-   along with GCC; see the file COPYING3.  If not see
+-   <http://www.gnu.org/licenses/>.  */
+-
+-/* This file contains macro overrides for EABI targets.  */
+-
+-#undef TARGET_OS_CPP_BUILTINS
+-#define TARGET_OS_CPP_BUILTINS()			\
+-  do							\
+-    {							\
+-      TARGET_BPABI_CPP_BUILTINS ();			\
+-      if (TARGET_ANDROID)				\
+-	builtin_define ("__ANDROID__");			\
+-    }							\
+-  while (false)
+-
+-#undef SUBSUBTARGET_EXTRA_SPECS
+-#define SUBSUBTARGET_EXTRA_SPECS \
+-  { "link_android",		ANDROID_LINK_SPEC },		\
+-  { "link_default",		BPABI_LINK_SPEC },		\
+-  { "cc1_android",		ANDROID_CC1_SPEC },		\
+-  { "cc1_default",		CC1_DEFAULT_SPEC },		\
+-  { "cc1plus_android",		ANDROID_CC1PLUS_SPEC },		\
+-  { "cc1plus_default",		CC1PLUS_DEFAULT_SPEC },		\
+-  { "lib_android",		ANDROID_LIB_SPEC },		\
+-  { "lib_default",		LIB_DEFAULT_SPEC },		\
+-  { "startfile_android",	ANDROID_STARTFILE_SPEC },	\
+-  { "startfile_default",	UNKNOWN_ELF_STARTFILE_SPEC },	\
+-  { "endfile_android",		ANDROID_ENDFILE_SPEC },		\
+-  { "endfile_default",		UNKNOWN_ELF_ENDFILE_SPEC },	\
+-
+-#undef ANDROID_LINK_SPEC
+-#define ANDROID_LINK_SPEC \
+-"%{mbig-endian:-EB} %{mlittle-endian:-EL} "		\
+-"%{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic} "	\
+-"%{!static:" \
+-   "%{shared: -Bsymbolic} " \
+-   "%{!shared:" \
+-      "%{rdynamic:-export-dynamic} " \
+-      "%{!dynamic-linker:-dynamic-linker /system/bin/linker}}} " \
+-"-X" SUBTARGET_EXTRA_LINK_SPEC
+-
+-/* Override LINK_SPEC in bpabi.h. */
+-#undef LINK_SPEC
+-#define LINK_SPEC \
+-"%{mandroid: %(link_android) ;" \
+-"          : %(link_default)}"
+-
+-/* Android uses -fno-exceptions by default. */
+-#undef ANDROID_CC1_SPEC
+-#define ANDROID_CC1_SPEC "%{!fexceptions:-fno-exceptions}"
+-
+-/* Default CC1_SPEC as in arm.h. */
+-#undef CC1_DEFAULT_SPEC
+-#define CC1_DEFAULT_SPEC ""
+-
+-#undef CC1_SPEC
+-#define CC1_SPEC \
+-"%{mandroid: %(cc1_android) ;" \
+-"          : %(cc1_default)}"
+-
+-/* Android uses -fno-rtti by default. */
+-#undef ANDROID_CC1PLUS_SPEC
+-#define ANDROID_CC1PLUS_SPEC "%{!frtti:-fno-rtti}"
+-
+-/* Default CC1PLUS_SPEC as in gcc.c. */
+-#undef CC1PLUS_DEFAULT_SPEC
+-#define CC1PLUS_DEFAULT_SPEC ""
+-
+-#undef CC1PLUS_SPEC
+-#define CC1PLUS_SPEC \
+-"%{mandroid: %(cc1plus_android) ;" \
+-"          : %(cc1plus_default)}"
+-
+-#undef ANDROID_LIB_SPEC
+-#define ANDROID_LIB_SPEC	"-lc %{!static:-ldl}"
+-
+-/* Default LIB_SPEC as in gcc.c. */
+-#undef LIB_DEFAULT_SPEC
+-#define LIB_DEFAULT_SPEC \
+-"%{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
+-
+-#undef LIB_SPEC
+-#define LIB_SPEC \
+-"%{mandroid: %(lib_android) ;" \
+-"          : %(lib_default)}"
+-
+-#undef ANDROID_STARTFILE_SPEC
+-#define ANDROID_STARTFILE_SPEC \
+-"%{!shared:" \
+-   "%{static: crtbegin_static%O%s ;" \
+-   "        : crtbegin_dynamic%O%s}}"
+-
+-/* Override STARTFILE_SPEC in unknown-elf.h. */
+-#undef STARTFILE_SPEC
+-#define STARTFILE_SPEC \
+-"%{mandroid: %(startfile_android) ;" \
+-"          : %(startfile_default)}"
+-
+-#undef ANDROID_ENDFILE_SPEC
+-#define ANDROID_ENDFILE_SPEC	"%{!shared:crtend_android%O%s}"
+-
+-/* Override ENDFILE_SPEC in unknown-elf.h. */
+-#undef ENDFILE_SPEC
+-#define ENDFILE_SPEC \
+-"%{mandroid: %(endfile_android) ;" \
+-"          : %(endfile_default)}"
+-
+Index: gcc-4.5.3/gcc/config/arm/eabi.opt
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/eabi.opt
++++ /dev/null
+@@ -1,23 +0,0 @@
+-; EABI specific options for ARM port of the compiler.
+-
+-; Copyright (C) 2008 Free Software Foundation, Inc.
+-;
+-; This file is part of GCC.
+-;
+-; GCC is free software; you can redistribute it and/or modify it under
+-; the terms of the GNU General Public License as published by the Free
+-; Software Foundation; either version 3, or (at your option) any later
+-; version.
+-;
+-; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+-; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-; for more details.
+-;
+-; You should have received a copy of the GNU General Public License
+-; along with GCC; see the file COPYING3.  If not see
+-; <http://www.gnu.org/licenses/>.
+-
+-mandroid
+-Target Report RejectNegative Mask(ANDROID)
+-Generate code for the Android operating system.
+Index: gcc-4.5.3/gcc/config/arm/linux-eabi.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/arm/linux-eabi.h
++++ gcc-4.5.3/gcc/config/arm/linux-eabi.h
+@@ -70,7 +70,30 @@
+ /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to
+    use the GNU/Linux version, not the generic BPABI version.  */
+ #undef  LINK_SPEC
+-#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC
++#define LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC                   \
++  LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC,                         \
++                      LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC)
++
++#undef  CC1_SPEC
++#define CC1_SPEC                                               \
++  LINUX_OR_ANDROID_CC (LINUX_TARGET_CC1_SPEC,                  \
++                      LINUX_TARGET_CC1_SPEC " " ANDROID_CC1_SPEC)
++
++#define CC1PLUS_SPEC \
++  LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC)
++
++#undef  LIB_SPEC
++#define LIB_SPEC                                               \
++  LINUX_OR_ANDROID_LD (LINUX_TARGET_LIB_SPEC,                  \
++                      LINUX_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC)
++
++#undef STARTFILE_SPEC
++#define STARTFILE_SPEC \
++  LINUX_OR_ANDROID_LD (LINUX_TARGET_STARTFILE_SPEC, ANDROID_STARTFILE_SPEC)
++
++#undef ENDFILE_SPEC
++#define ENDFILE_SPEC \
++  LINUX_OR_ANDROID_LD (LINUX_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
+ 
+ /* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+    do not use -lfloat.  */
+Index: gcc-4.5.3/gcc/config/arm/t-linux-androideabi
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/gcc/config/arm/t-linux-androideabi
+@@ -0,0 +1,10 @@
++MULTILIB_OPTIONS     = march=armv7-a mthumb
++MULTILIB_DIRNAMES    = armv7-a thumb
++MULTILIB_EXCEPTIONS  =
++MULTILIB_MATCHES     =
++MULTILIB_OSDIRNAMES  =
++
++# The "special" multilib can be used to build native applications for Android,
++# as opposed to native shared libraries that are then called via JNI.
++#MULTILIB_OPTIONS    += tno-android-cc
++#MULTILIB_DIRNAMES   += special
+Index: gcc-4.5.3/gcc/config/linux-android.h
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/gcc/config/linux-android.h
+@@ -0,0 +1,53 @@
++/* Configuration file for Linux Android targets.
++   Copyright (C) 2010
++   Free Software Foundation, Inc.
++   Contributed by CodeSourcery, Inc.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++#if ANDROID_DEFAULT
++# define NOANDROID "mno-android"
++#else
++# define NOANDROID "!mandroid"
++#endif
++
++#define LINUX_OR_ANDROID_CC(LINUX_SPEC, ANDROID_SPEC) \
++  "%{" NOANDROID "|tno-android-cc:" LINUX_SPEC ";:" ANDROID_SPEC "}"
++
++#define LINUX_OR_ANDROID_LD(LINUX_SPEC, ANDROID_SPEC) \
++  "%{" NOANDROID "|tno-android-ld:" LINUX_SPEC ";:" ANDROID_SPEC "}"
++
++#define ANDROID_LINK_SPEC \
++  "%{shared: -Bsymbolic}"
++
++#define ANDROID_CC1_SPEC						\
++  "%{!mglibc:%{!muclibc:%{!mbionic: -mbionic}}} "			\
++  "%{!fno-pic:%{!fno-PIC:%{!fpic:%{!fPIC: -fPIC}}}}"
++
++#define ANDROID_CC1PLUS_SPEC						\
++  "%{!fexceptions:%{!fno-exceptions: -fno-exceptions}} "		\
++  "%{!frtti:%{!fno-rtti: -fno-rtti}}"
++
++#define ANDROID_LIB_SPEC \
++  "%{!static: -ldl}"
++
++#define ANDROID_STARTFILE_SPEC						\
++  "%{!shared:"								\
++  "  %{static: crtbegin_static%O%s;: crtbegin_dynamic%O%s}}"
++
++#define ANDROID_ENDFILE_SPEC \
++  "%{!shared: crtend_android%O%s}"
+Index: gcc-4.5.3/gcc/config/linux-android.opt
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/gcc/config/linux-android.opt
+@@ -0,0 +1,23 @@
++; Android specific options.
++
++; Copyright (C) 2010 Free Software Foundation, Inc.
++;
++; This file is part of GCC.
++;
++; GCC is free software; you can redistribute it and/or modify it under
++; the terms of the GNU General Public License as published by the Free
++; Software Foundation; either version 3, or (at your option) any later
++; version.
++;
++; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++; WARRANTY; without even the implied warranty of MERCHANTABILITY or
++; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++; for more details.
++;
++; You should have received a copy of the GNU General Public License
++; along with GCC; see the file COPYING3.  If not see
++; <http://www.gnu.org/licenses/>.
++
++mandroid
++Target Report Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0)
++Generate code for the Android platform.
+Index: gcc-4.5.3/gcc/config/linux.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/linux.h
++++ gcc-4.5.3/gcc/config/linux.h
+@@ -1,6 +1,6 @@
+ /* Definitions for Linux-based GNU systems with ELF format
+    Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003, 2004, 2005, 2006,
+-   2007, 2009 Free Software Foundation, Inc.
++   2007, 2009, 2010 Free Software Foundation, Inc.
+    Contributed by Eric Youngdale.
+    Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org).
+ 
+@@ -42,16 +42,17 @@ see the files COPYING3 and COPYING.RUNTI
+    provides part of the support for getting C++ file-scope static
+    object constructed before entering `main'.  */
+    
+-#undef	STARTFILE_SPEC
+ #if defined HAVE_LD_PIE
+-#define STARTFILE_SPEC \
++#define LINUX_TARGET_STARTFILE_SPEC \
+   "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+    crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}"
+ #else
+-#define STARTFILE_SPEC \
++#define LINUX_TARGET_STARTFILE_SPEC \
+   "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+    crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}"
+ #endif
++#undef  STARTFILE_SPEC
++#define STARTFILE_SPEC LINUX_TARGET_STARTFILE_SPEC
+ 
+ /* Provide a ENDFILE_SPEC appropriate for GNU/Linux.  Here we tack on
+    the GNU/Linux magical crtend.o file (see crtstuff.c) which
+@@ -59,33 +60,44 @@ see the files COPYING3 and COPYING.RUNTI
+    object constructed before entering `main', followed by a normal
+    GNU/Linux "finalizer" file, `crtn.o'.  */
+ 
+-#undef	ENDFILE_SPEC
+-#define ENDFILE_SPEC \
++#define LINUX_TARGET_ENDFILE_SPEC \
+   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
++#undef  ENDFILE_SPEC
++#define ENDFILE_SPEC LINUX_TARGET_ENDFILE_SPEC
+ 
+ /* This is for -profile to use -lc_p instead of -lc.  */
++#define LINUX_TARGET_CC1_SPEC "%{profile:-p}"
+ #ifndef CC1_SPEC
+-#define CC1_SPEC "%{profile:-p}"
++#define CC1_SPEC LINUX_TARGET_CC1_SPEC
+ #endif
+ 
+ /* The GNU C++ standard library requires that these macros be defined.  */
+ #undef CPLUSPLUS_CPP_SPEC
+ #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
+ 
+-#undef	LIB_SPEC
+-#define LIB_SPEC \
++#define LINUX_TARGET_LIB_SPEC \
+   "%{pthread:-lpthread} \
+    %{shared:-lc} \
+    %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}"
++#undef  LIB_SPEC
++#define LIB_SPEC LINUX_TARGET_LIB_SPEC
++
++/* C libraries supported on Linux.  */
++#define OPTION_GLIBC  (linux_libc == LIBC_GLIBC)
++#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
++#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
+ 
+ #define LINUX_TARGET_OS_CPP_BUILTINS()				\
+     do {							\
+-	builtin_define ("__gnu_linux__");			\
++	if (OPTION_GLIBC)					\
++	  builtin_define ("__gnu_linux__");			\
+ 	builtin_define_std ("linux");				\
+ 	builtin_define_std ("unix");				\
+ 	builtin_assert ("system=linux");			\
+ 	builtin_assert ("system=unix");				\
+ 	builtin_assert ("system=posix");			\
++	if (OPTION_ANDROID)					\
++	  builtin_define ("__ANDROID__");			\
+     } while (0)
+ 
+ #if defined(HAVE_LD_EH_FRAME_HDR)
+@@ -105,13 +117,24 @@ see the files COPYING3 and COPYING.RUNTI
+ #endif
+ 
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+-   uClibc is the default C library and whether -muclibc or -mglibc has
+-   been passed to change the default.  */
+-#if UCLIBC_DEFAULT
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}"
++   uClibc or Bionic is the default C library and whether
++   -muclibc or -mglibc or -mbionic has been passed to change the default.  */
++
++#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3)	\
++  "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}"
++
++#if DEFAULT_LIBC == LIBC_GLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
++  CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B)
++#elif DEFAULT_LIBC == LIBC_UCLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
++  CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B)
++#elif DEFAULT_LIBC == LIBC_BIONIC
++#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
++  CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U)
+ #else
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}"
+-#endif
++#error "Unsupported DEFAULT_LIBC"
++#endif /* DEFAULT_LIBC */
+ 
+ /* For most targets the following definitions suffice;
+    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
+@@ -120,18 +143,25 @@ see the files COPYING3 and COPYING.RUNTI
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+-#define LINUX_DYNAMIC_LINKER \
+-  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+-#define LINUX_DYNAMIC_LINKER32 \
+-  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
+-#define LINUX_DYNAMIC_LINKER64 \
+-  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
++#define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
++#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
++#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
++
++#define LINUX_DYNAMIC_LINKER						\
++  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER,	\
++			 BIONIC_DYNAMIC_LINKER)
++#define LINUX_DYNAMIC_LINKER32						\
++  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \
++			 BIONIC_DYNAMIC_LINKER32)
++#define LINUX_DYNAMIC_LINKER64						\
++  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \
++			 BIONIC_DYNAMIC_LINKER64)
+ 
+ /* Determine whether the entire c99 runtime
+    is present in the runtime library.  */
+ #define TARGET_C99_FUNCTIONS (OPTION_GLIBC)
+ 
+ /* Whether we have sincos that follows the GNU extension.  */
+-#define TARGET_HAS_SINCOS (OPTION_GLIBC)
++#define TARGET_HAS_SINCOS (OPTION_GLIBC | OPTION_BIONIC)
+ 
+ #define TARGET_POSIX_IO
+Index: gcc-4.5.3/gcc/config/linux.opt
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/linux.opt
++++ gcc-4.5.3/gcc/config/linux.opt
+@@ -1,6 +1,6 @@
+ ; Processor-independent options for GNU/Linux.
+ ;
+-; Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc.
++; Copyright (C) 2006, 2007, 2009, 2010 Free Software Foundation, Inc.
+ ; Contributed by CodeSourcery.
+ ;
+ ; This file is part of GCC.
+@@ -19,10 +19,14 @@
+ ; along with GCC; see the file COPYING3.  If not see
+ ; <http://www.gnu.org/licenses/>.
+ 
++mbionic
++Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc)
++Use Bionic C library
++
+ mglibc
+-Target RejectNegative Report InverseMask(UCLIBC, GLIBC) Var(linux_uclibc) Init(UCLIBC_DEFAULT ? OPTION_MASK_UCLIBC : 0)
+-Use GNU libc instead of uClibc
++Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) VarExists Negative(muclibc)
++Use GNU C library
+ 
+ muclibc
+-Target RejectNegative Report Mask(UCLIBC) Var(linux_uclibc) VarExists
+-Use uClibc instead of GNU libc
++Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) VarExists Negative(mbionic)
++Use uClibc C library
+Index: gcc-4.5.3/gcc/config/rs6000/linux64.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/rs6000/linux64.h
++++ gcc-4.5.3/gcc/config/rs6000/linux64.h
+@@ -344,10 +344,12 @@ extern int dot_symbols;
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1"
+ #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+-#if UCLIBC_DEFAULT
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}"
++#if DEFAULT_LIBC == LIBC_UCLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#elif DEFAULT_LIBC == LIBC_GLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
+ #else
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}"
++#error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define LINUX_DYNAMIC_LINKER32 \
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
+Index: gcc-4.5.3/gcc/config/rs6000/sysv4.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/config/rs6000/sysv4.h
++++ gcc-4.5.3/gcc/config/rs6000/sysv4.h
+@@ -901,10 +901,12 @@ SVR4_ASM_SPEC \
+ 
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+-#if UCLIBC_DEFAULT
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}"
++#if DEFAULT_LIBC == LIBC_UCLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#elif DEFAULT_LIBC == LIBC_GLIBC
++#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
+ #else
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}"
++#error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define LINUX_DYNAMIC_LINKER \
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+Index: gcc-4.5.3/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4.5.3.orig/gcc/doc/invoke.texi
++++ gcc-4.5.3/gcc/doc/invoke.texi
+@@ -565,7 +565,8 @@ Objective-C and Objective-C++ Dialects}.
+ -mcpu=@var{cpu}}
+ 
+ @emph{GNU/Linux Options}
+-@gccoptlist{-muclibc}
++@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol
++-tno-android-cc -tno-android-ld}
+ 
+ @emph{H8/300 Options}
+ @gccoptlist{-mrelax  -mh  -ms  -mn  -mint32  -malign-300}
+@@ -11469,13 +11470,41 @@ These @samp{-m} options are defined for
+ @table @gcctabopt
+ @item -mglibc
+ @opindex mglibc
+-Use the GNU C library instead of uClibc.  This is the default except
+-on @samp{*-*-linux-*uclibc*} targets.
++Use the GNU C library.  This is the default except
++on @samp{*-*-linux-*uclibc*} and @samp{*-*-linux-*android*} targets.
+ 
+ @item -muclibc
+ @opindex muclibc
+-Use uClibc instead of the GNU C library.  This is the default on
++Use uClibc C library.  This is the default on
+ @samp{*-*-linux-*uclibc*} targets.
++
++@item -mbionic
++@opindex mbionic
++Use Bionic C library.  This is the default on
++@samp{*-*-linux-*android*} targets.
++
++@item -mandroid
++@opindex mandroid
++Compile code compatible with Android platform.  This is the default on
++@samp{*-*-linux-*android*} targets.
++
++When compiling, this option enables @option{-mbionic}, @option{-fPIC},
++@option{-fno-exceptions} and @option{-fno-rtti} by default.  When linking,
++this option makes the GCC driver pass Android-specific options to the linker.
++Finally, this option causes the preprocessor macro @code{__ANDROID__}
++to be defined.
++
++@item -tno-android-cc
++@opindex tno-android-cc
++Disable compilation effects of @option{-mandroid}, i.e., do not enable
++@option{-mbionic}, @option{-fPIC}, @option{-fno-exceptions} and
++@option{-fno-rtti} by default.
++
++@item -tno-android-ld
++@opindex tno-android-ld
++Disable linking effects of @option{-mandroid}, i.e., pass standard Linux
++linking options to the linker.
++
+ @end table
+ 
+ @node H8/300 Options
+Index: gcc-4.5.3/gcc/gthr-posix.h
+===================================================================
+--- gcc-4.5.3.orig/gcc/gthr-posix.h
++++ gcc-4.5.3/gcc/gthr-posix.h
+@@ -124,7 +124,9 @@ __gthrw(pthread_join)
+ __gthrw(pthread_equal)
+ __gthrw(pthread_self)
+ __gthrw(pthread_detach)
++#ifndef __BIONIC__
+ __gthrw(pthread_cancel)
++#endif
+ __gthrw(sched_yield)
+ 
+ __gthrw(pthread_mutex_lock)
+@@ -238,7 +240,15 @@ static inline int
+ __gthread_active_p (void)
+ {
+   static void *const __gthread_active_ptr
+-    = __extension__ (void *) &__gthrw_(pthread_cancel);
++    = __extension__ (void *) &__gthrw_(
++/* Android's C library does not provide pthread_cancel, check for
++   `pthread_create' instead.  */
++#ifndef __BIONIC__
++				       pthread_cancel
++#else
++				       pthread_create
++#endif
++				       );
+   return __gthread_active_ptr != 0;
+ }
+ 
+Index: gcc-4.5.3/gcc/testsuite/gcc.dg/glibc-uclibc-1.c
+===================================================================
+--- gcc-4.5.3.orig/gcc/testsuite/gcc.dg/glibc-uclibc-1.c
++++ /dev/null
+@@ -1,6 +0,0 @@
+-/* Test -mglibc and -muclibc not allowed together.  */
+-/* Origin: Joseph Myers <joseph@codesourcery.com> */
+-/* { dg-do link { target *-*-linux* } } */
+-/* { dg-options "-mglibc -muclibc" } */
+-
+-/* { dg-message "-mglibc and -muclibc used together" "" { target *-*-* } 0 } */
+Index: gcc-4.5.3/gcc/testsuite/gcc.dg/glibc-uclibc-2.c
+===================================================================
+--- gcc-4.5.3.orig/gcc/testsuite/gcc.dg/glibc-uclibc-2.c
++++ /dev/null
+@@ -1,6 +0,0 @@
+-/* Test -mglibc and -muclibc not allowed together.  */
+-/* Origin: Joseph Myers <joseph@codesourcery.com> */
+-/* { dg-do link { target *-*-linux* } } */
+-/* { dg-options "-muclibc -mglibc" } */
+-
+-/* { dg-message "-mglibc and -muclibc used together" "" { target *-*-* } 0 } */
+Index: gcc-4.5.3/libstdc++-v3/acinclude.m4
+===================================================================
+--- gcc-4.5.3.orig/libstdc++-v3/acinclude.m4
++++ gcc-4.5.3/libstdc++-v3/acinclude.m4
+@@ -95,7 +95,7 @@ AC_DEFUN([GLIBCXX_CONFIGURE], [
+   ## (Right now, this only matters for enable_wchar_t, but nothing prevents
+   ## other macros from doing the same.  This should be automated.)  -pme
+ 
+-  # Check for uClibc since Linux platforms use different configuration
++  # Check for C library flavor since Linux platforms use different configuration
+   # directories depending on the C library in use.
+   AC_EGREP_CPP([_using_uclibc], [
+   #include <stdio.h>
+@@ -104,6 +104,13 @@ AC_DEFUN([GLIBCXX_CONFIGURE], [
+   #endif
+   ], uclibc=yes, uclibc=no)
+ 
++  AC_EGREP_CPP([_using_bionic], [
++  #include <stdio.h>
++  #if __BIONIC__
++    _using_bionic
++  #endif
++  ], bionic=yes, bionic=no)
++
+   # Find platform-specific directories containing configuration info.
+   # Also possibly modify flags used elsewhere, as needed by the platform.
+   GLIBCXX_CHECK_HOST
+@@ -2722,7 +2729,7 @@ void foo()
+ }
+ EOF
+     old_CXXFLAGS="$CXXFLAGS"
+-    CXXFLAGS=-S
++    CXXFLAGS="-S -fexceptions"
+     if AC_TRY_EVAL(ac_compile); then
+       if grep _Unwind_SjLj_Resume conftest.s >/dev/null 2>&1 ; then
+         enable_sjlj_exceptions=yes
+Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_base.h
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_base.h
+@@ -0,0 +1,57 @@
++// Locale support -*- C++ -*-
++
++// Copyright (C) 2010 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++//
++// ISO C++ 14882: 22.1  Locales
++//
++
++// Information as gleaned from /usr/include/ctype.h, for solaris2.5.1
++
++// Support for Solaris 2.5.1
++
++_GLIBCXX_BEGIN_NAMESPACE(std)
++
++  /// @brief  Base class for ctype.
++  struct ctype_base
++  {
++    // Non-standard typedefs.
++    typedef const int* 		__to_type;
++
++    // NB: Offsets into ctype<char>::_M_table force a particular size
++    // on the mask type. Because of this, we don't use an enum.
++    typedef char 		mask;
++    static const mask upper    	= _U;
++    static const mask lower 	= _L;
++    static const mask alpha 	= _U | _L;
++    static const mask digit 	= _N;
++    static const mask xdigit 	= _X | _N;
++    static const mask space 	= _S;
++    static const mask print 	= _P | _U | _L | _N | _B;
++    static const mask graph 	= _P | _U | _L | _N;
++    static const mask cntrl 	= _C;
++    static const mask punct 	= _P;
++    static const mask alnum 	= _U | _L | _N;
++  };
++
++_GLIBCXX_END_NAMESPACE
+Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_inline.h
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_inline.h
+@@ -0,0 +1,71 @@
++// Locale support -*- C++ -*-
++
++// Copyright (C) 2010 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++/** @file ctype_inline.h
++ *  This is an internal header file, included by other library headers.
++ *  You should not attempt to use it directly.
++ */
++
++//
++// ISO C++ 14882: 22.1  Locales
++//
++
++// ctype bits to be inlined go here. Non-inlinable (ie virtual do_*)
++// functions go in ctype.cc
++
++_GLIBCXX_BEGIN_NAMESPACE(std)
++
++  bool
++  ctype<char>::
++  is(mask __m, char __c) const
++  { return _M_table[static_cast<unsigned char>(__c)] & __m; }
++
++  const char*
++  ctype<char>::
++  is(const char* __low, const char* __high, mask* __vec) const
++  {
++    while (__low < __high)
++      *__vec++ = _M_table[static_cast<unsigned char>(*__low++)];
++    return __high;
++  }
++
++  const char*
++  ctype<char>::
++  scan_is(mask __m, const char* __low, const char* __high) const
++  {
++    while (__low < __high && !this->is(__m, *__low))
++      ++__low;
++    return __low;
++  }
++
++  const char*
++  ctype<char>::
++  scan_not(mask __m, const char* __low, const char* __high) const
++  {
++    while (__low < __high && this->is(__m, *__low) != 0)
++      ++__low;
++    return __low;
++  }
++
++_GLIBCXX_END_NAMESPACE
+Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_noninline.h
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_noninline.h
+@@ -0,0 +1,98 @@
++// Locale support -*- C++ -*-
++
++// Copyright (C) 2010 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++/** @file ctype_noninline.h
++ *  This is an internal header file, included by other library headers.
++ *  You should not attempt to use it directly.
++ */
++
++//
++// ISO C++ 14882: 22.1  Locales
++//
++
++// Information as gleaned from /usr/include/ctype.h
++
++  const ctype_base::mask*
++  ctype<char>::classic_table() throw()
++  { return _ctype_ + 1; }
++
++  ctype<char>::ctype(__c_locale, const mask* __table, bool __del,
++		     size_t __refs)
++  : facet(__refs), _M_del(__table != 0 && __del),
++  _M_toupper(NULL), _M_tolower(NULL),
++  _M_table(__table ? __table : classic_table())
++  {
++    memset(_M_widen, 0, sizeof(_M_widen));
++    _M_widen_ok = 0;
++    memset(_M_narrow, 0, sizeof(_M_narrow));
++    _M_narrow_ok = 0;
++  }
++
++  ctype<char>::ctype(const mask* __table, bool __del, size_t __refs)
++  : facet(__refs), _M_del(__table != 0 && __del),
++  _M_toupper(NULL), _M_tolower(NULL),
++  _M_table(__table ? __table : classic_table())
++  {
++    memset(_M_widen, 0, sizeof(_M_widen));
++    _M_widen_ok = 0;
++    memset(_M_narrow, 0, sizeof(_M_narrow));
++    _M_narrow_ok = 0;
++  }
++
++  char
++  ctype<char>::do_toupper(char __c) const
++  {
++    int __x = __c;
++    return (this->is(ctype_base::lower, __c) ? (__x - 'a' + 'A') : __x);
++  }
++
++  const char*
++  ctype<char>::do_toupper(char* __low, const char* __high) const
++  {
++    while (__low < __high)
++      {
++	*__low = this->do_toupper(*__low);
++	++__low;
++      }
++    return __high;
++  }
++
++  char
++  ctype<char>::do_tolower(char __c) const
++  {
++    int __x = __c;
++    return (this->is(ctype_base::upper, __c) ? (__x - 'A' + 'a') : __x);
++  }
++
++  const char*
++  ctype<char>::do_tolower(char* __low, const char* __high) const
++  {
++    while (__low < __high)
++      {
++	*__low = this->do_tolower(*__low);
++	++__low;
++      }
++    return __high;
++  }
++
+Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/os_defines.h
+===================================================================
+--- /dev/null
++++ gcc-4.5.3/libstdc++-v3/config/os/bionic/os_defines.h
+@@ -0,0 +1,36 @@
++// Specific definitions for Bionic  -*- C++ -*-
++
++// Copyright (C) 2010 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++/** @file os_defines.h
++ *  This is an internal header file, included by other library headers.
++ *  You should not attempt to use it directly.
++ */
++
++#ifndef _GLIBCXX_OS_DEFINES
++#define _GLIBCXX_OS_DEFINES 1
++
++// System-specific #define, typedefs, corrections, etc, go here.  This
++// file will come before all others.
++
++#endif
+Index: gcc-4.5.3/libstdc++-v3/configure
+===================================================================
+--- gcc-4.5.3.orig/libstdc++-v3/configure
++++ gcc-4.5.3/libstdc++-v3/configure
+@@ -5185,7 +5185,7 @@ fi
+   ## (Right now, this only matters for enable_wchar_t, but nothing prevents
+   ## other macros from doing the same.  This should be automated.)  -pme
+ 
+-  # Check for uClibc since Linux platforms use different configuration
++  # Check for C library flavor since Linux platforms use different configuration
+   # directories depending on the C library in use.
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+@@ -5205,6 +5205,24 @@ fi
+ rm -f conftest*
+ 
+ 
++  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++
++  #include <stdio.h>
++  #if __BIONIC__
++    _using_bionic
++  #endif
++
++_ACEOF
++if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
++  $EGREP "_using_bionic" >/dev/null 2>&1; then :
++  bionic=yes
++else
++  bionic=no
++fi
++rm -f conftest*
++
++
+   # Find platform-specific directories containing configuration info.
+   # Also possibly modify flags used elsewhere, as needed by the platform.
+ 
+@@ -14897,7 +14915,7 @@ void foo()
+ }
+ EOF
+     old_CXXFLAGS="$CXXFLAGS"
+-    CXXFLAGS=-S
++    CXXFLAGS="-S -fexceptions"
+     if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
+   (eval $ac_compile) 2>&5
+   ac_status=$?
+Index: gcc-4.5.3/libstdc++-v3/configure.host
+===================================================================
+--- gcc-4.5.3.orig/libstdc++-v3/configure.host
++++ gcc-4.5.3/libstdc++-v3/configure.host
+@@ -238,6 +238,8 @@ case "${host_os}" in
+   gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu)
+     if [ "$uclibc" = "yes" ]; then
+       os_include_dir="os/uclibc"
++    elif [ "$bionic" = "yes" ]; then
++      os_include_dir="os/bionic"
+     else
+       os_include_dir="os/gnu-linux"
+     fi
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99495.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99495.patch
new file mode 100644
index 0000000000..bb866ce8d9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99495.patch
@@ -0,0 +1,784 @@
+2011-03-24  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	* loop-doloop.c (doloop_condition_get): Support new form of
+	doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
+	* config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
+	(doloop_end): New.
+	* config/arm/arm.md (*addsi3_compare0): Remove "*".
+	* ddg.c (check_closing_branch_deps, get_node_of_insn_uid):
+	New functions.
+	(create_ddg): Pass sbitmap containing do-loop related
+	instructions instead of closing_branch_deps parameter and call
+	check_closing_branch_deps function.
+	* ddg.h (create_ddg): Adjust the function declaration.
+	* modulo-sched.c (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT
+	and redefine.
+	(doloop_register_get): Handle NONDEBUG_INSN_P.
+	(stage_count): New field in struct partial_schedule.
+	(mark_doloop_insns, calculate_stage_count): New functions.
+	(normalize_sched_times): Rename to reset_sched_times and handle
+	incrementing the sched time of the nodes by a constant value
+	passed as parameter.
+	(duplicate_insns_of_cycles): Skip closing branch.
+	(sms_schedule_by_order): Schedule closing branch when
+	closing_branch_deps is true.
+	(ps_insn_find_column): Handle closing branch.
+	(sms_schedule): Call reset_sched_times and handle case where
+	do-loop pattern is not decoupled from the other loop instructions.
+	Support new form of doloop pattern.
+	(ps_insert_empty_row): Update calls to normalize_sched_times
+	and rotate_partial_schedule functions.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-03-11 14:26:34 +0000
++++ new/gcc/config/arm/arm.md	2011-03-24 07:45:38 +0000
+@@ -734,7 +734,7 @@
+   ""
+ )
+ 
+-(define_insn "*addsi3_compare0"
++(define_insn "addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+ 	 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r")
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2011-02-08 10:51:58 +0000
++++ new/gcc/config/arm/thumb2.md	2011-03-24 07:45:38 +0000
+@@ -1194,7 +1194,7 @@
+    (set_attr "length" "2")]
+ )
+ 
+-(define_insn "*thumb2_addsi3_compare0"
++(define_insn "thumb2_addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+ 	  (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
+@@ -1445,3 +1445,56 @@
+   [(set_attr "length" "4,4,16")
+    (set_attr "predicable" "yes")]
+ )
++
++
++;; Define the subtract-one-and-jump insns so loop.c
++;; knows what to generate.
++(define_expand "doloop_end"
++  [(use (match_operand 0 "" ""))      ; loop pseudo
++   (use (match_operand 1 "" ""))      ; iterations; zero if unknown
++   (use (match_operand 2 "" ""))      ; max iterations
++   (use (match_operand 3 "" ""))      ; loop level
++   (use (match_operand 4 "" ""))]     ; label
++  "TARGET_32BIT"
++  "
++ {
++   /* Currently SMS relies on the do-loop pattern to recognize loops
++      where (1) the control part consists of all insns defining and/or
++      using a certain 'count' register and (2) the loop count can be
++      adjusted by modifying this register prior to the loop.
++     ??? The possible introduction of a new block to initialize the
++      new IV can potentially affect branch optimizations.  */
++   if (optimize > 0 && flag_modulo_sched)
++   {
++     rtx s0;
++     rtx bcomp;
++     rtx loc_ref;
++     rtx cc_reg;
++     rtx insn;
++     rtx cmp;
++
++     /* Only use this on innermost loops.  */
++     if (INTVAL (operands[3]) > 1)
++       FAIL;
++
++     if (GET_MODE (operands[0]) != SImode)
++       FAIL;
++
++     s0 = operands [0];
++     if (TARGET_THUMB2)
++       insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
++     else
++       insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
++
++     cmp = XVECEXP (PATTERN (insn), 0, 0);
++     cc_reg = SET_DEST (cmp);
++     bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
++     loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
++     emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
++                                  gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
++                                                        loc_ref, pc_rtx)));
++     DONE;
++   }else
++      FAIL;
++ }")
++
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2010-07-19 08:58:53 +0000
++++ new/gcc/ddg.c	2011-03-24 07:45:38 +0000
+@@ -60,6 +60,8 @@
+ static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type,
+ 				     dep_data_type, int, int);
+ static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr);
++static ddg_node_ptr get_node_of_insn_uid (ddg_ptr, int);
++
+ 
+ /* Auxiliary variable for mem_read_insn_p/mem_write_insn_p.  */
+ static bool mem_ref_p;
+@@ -450,12 +452,65 @@
+   sched_free_deps (head, tail, false);
+ }
+ 
++/* Given DOLOOP_INSNS which holds the instructions that
++   belong to the do-loop part; mark closing_branch_deps field in ddg G
++   as TRUE if the do-loop part's instructions are dependent on the other
++   loop instructions.  Otherwise mark it as FALSE.  */
++static void
++check_closing_branch_deps (ddg_ptr g, sbitmap doloop_insns)
++{
++  sbitmap_iterator sbi;
++  unsigned int u = 0;
++
++  EXECUTE_IF_SET_IN_SBITMAP (doloop_insns, 0, u, sbi)
++  {
++    ddg_edge_ptr e;
++    ddg_node_ptr u_node = get_node_of_insn_uid (g, u);
++
++    gcc_assert (u_node);
++
++    for (e = u_node->in; e != 0; e = e->next_in)
++      {
++	ddg_node_ptr v_node = e->src;
++
++	if (((unsigned int) INSN_UID (v_node->insn) == u)
++	    || DEBUG_INSN_P (v_node->insn))
++	  continue;
++	
++	/* Ignore dependencies between memory writes and the
++	   jump.  */
++	if (JUMP_P (u_node->insn)
++	    && e->type == OUTPUT_DEP 
++            && mem_write_insn_p (v_node->insn))
++	  continue;
++	if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
++	  {
++	    g->closing_branch_deps = 1;
++	    return;
++	  }
++      }
++    for (e = u_node->out; e != 0; e = e->next_out)
++      {
++	ddg_node_ptr v_node = e->dest;
++
++	if (((unsigned int) INSN_UID (v_node->insn) == u)
++            || DEBUG_INSN_P (v_node->insn))
++	  continue;
++	if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
++	  {
++	    g->closing_branch_deps = 1;
++	    return;
++	  }
++      }
++  }
++  g->closing_branch_deps = 0;
++}
+ 
+ /* Given a basic block, create its DDG and return a pointer to a variable
+    of ddg type that represents it.
+    Initialize the ddg structure fields to the appropriate values.  */
+ ddg_ptr
+-create_ddg (basic_block bb, int closing_branch_deps)
++create_ddg (basic_block bb, sbitmap doloop_insns)
+ {
+   ddg_ptr g;
+   rtx insn, first_note;
+@@ -465,7 +520,6 @@
+   g = (ddg_ptr) xcalloc (1, sizeof (struct ddg));
+ 
+   g->bb = bb;
+-  g->closing_branch_deps = closing_branch_deps;
+ 
+   /* Count the number of insns in the BB.  */
+   for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
+@@ -538,6 +592,11 @@
+   /* Build the data dependency graph.  */
+   build_intra_loop_deps (g);
+   build_inter_loop_deps (g);
++
++  /* Check whether the do-loop part is decoupled from the other loop
++     instructions.  */
++  check_closing_branch_deps (g, doloop_insns);
++
+   return g;
+ }
+ 
+@@ -831,6 +890,18 @@
+   return NULL;
+ }
+ 
++/* Given the uid of an instruction UID return the node that represents it.  */
++static ddg_node_ptr
++get_node_of_insn_uid (ddg_ptr g, int uid)
++{
++  int i;
++
++  for (i = 0; i < g->num_nodes; i++)
++    if (uid == INSN_UID (g->nodes[i].insn))
++      return &g->nodes[i];
++  return NULL;
++}
++
+ /* Given a set OPS of nodes in the DDG, find the set of their successors
+    which are not in OPS, and set their bits in SUCC.  Bits corresponding to
+    OPS are cleared from SUCC.  Leaves the other bits in SUCC unchanged.  */
+
+=== modified file 'gcc/ddg.h'
+--- old/gcc/ddg.h	2009-11-25 10:55:54 +0000
++++ new/gcc/ddg.h	2011-03-24 07:45:38 +0000
+@@ -167,7 +167,7 @@
+ };
+ 
+ 
+-ddg_ptr create_ddg (basic_block, int closing_branch_deps);
++ddg_ptr create_ddg (basic_block, sbitmap);
+ void free_ddg (ddg_ptr);
+ 
+ void print_ddg (FILE *, ddg_ptr);
+
+=== modified file 'gcc/loop-doloop.c'
+--- old/gcc/loop-doloop.c	2010-07-19 08:58:53 +0000
++++ new/gcc/loop-doloop.c	2011-03-24 07:45:38 +0000
+@@ -78,6 +78,8 @@
+   rtx inc_src;
+   rtx condition;
+   rtx pattern;
++  rtx cc_reg = NULL_RTX;
++  rtx reg_orig = NULL_RTX;
+ 
+   /* The canonical doloop pattern we expect has one of the following
+      forms:
+@@ -96,7 +98,16 @@
+      2)  (set (reg) (plus (reg) (const_int -1))
+          (set (pc) (if_then_else (reg != 0)
+ 	                         (label_ref (label))
+-			         (pc))).  */
++			         (pc))).  
++
++     Some targets (ARM) do the comparison before the branch, as in the
++     following form:
++
++     3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0)))
++                   (set (reg) (plus (reg) (const_int -1)))])
++        (set (pc) (if_then_else (cc == NE)
++                                (label_ref (label))
++                                (pc))) */
+ 
+   pattern = PATTERN (doloop_pat);
+ 
+@@ -104,19 +115,47 @@
+     {
+       rtx cond;
+       rtx prev_insn = prev_nondebug_insn (doloop_pat);
++      rtx cmp_arg1, cmp_arg2;
++      rtx cmp_orig;
+ 
+-      /* We expect the decrement to immediately precede the branch.  */
++      /* In case the pattern is not PARALLEL we expect two forms
++	 of doloop which are cases 2) and 3) above: in case 2) the
++	 decrement immediately precedes the branch, while in case 3)
++	 the compare and decrement instructions immediately precede
++	 the branch.  */
+ 
+       if (prev_insn == NULL_RTX || !INSN_P (prev_insn))
+         return 0;
+ 
+       cmp = pattern;
+-      inc = PATTERN (PREV_INSN (doloop_pat));
++      if (GET_CODE (PATTERN (prev_insn)) == PARALLEL)
++        {
++	  /* The third case: the compare and decrement instructions
++	     immediately precede the branch.  */
++	  cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0);
++	  if (GET_CODE (cmp_orig) != SET)
++	    return 0;
++	  if (GET_CODE (SET_SRC (cmp_orig)) != COMPARE)
++	    return 0;
++	  cmp_arg1 = XEXP (SET_SRC (cmp_orig), 0);
++          cmp_arg2 = XEXP (SET_SRC (cmp_orig), 1);
++	  if (cmp_arg2 != const0_rtx 
++	      || GET_CODE (cmp_arg1) != PLUS)
++	    return 0;
++	  reg_orig = XEXP (cmp_arg1, 0);
++	  if (XEXP (cmp_arg1, 1) != GEN_INT (-1) 
++	      || !REG_P (reg_orig))
++	    return 0;
++	  cc_reg = SET_DEST (cmp_orig);
++	  
++	  inc = XVECEXP (PATTERN (prev_insn), 0, 1);
++	}
++      else
++        inc = PATTERN (prev_insn);
+       /* We expect the condition to be of the form (reg != 0)  */
+       cond = XEXP (SET_SRC (cmp), 0);
+       if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx)
+         return 0;
+-
+     }
+   else
+     {
+@@ -162,11 +201,15 @@
+     return 0;
+ 
+   if ((XEXP (condition, 0) == reg)
++      /* For the third case:  */  
++      || ((cc_reg != NULL_RTX)
++	  && (XEXP (condition, 0) == cc_reg)
++	  && (reg_orig == reg))
+       || (GET_CODE (XEXP (condition, 0)) == PLUS
+-		   && XEXP (XEXP (condition, 0), 0) == reg))
++	  && XEXP (XEXP (condition, 0), 0) == reg))
+    {
+      if (GET_CODE (pattern) != PARALLEL)
+-     /*  The second form we expect:
++     /*  For the second form we expect:
+ 
+          (set (reg) (plus (reg) (const_int -1))
+          (set (pc) (if_then_else (reg != 0)
+@@ -181,7 +224,24 @@
+                      (set (reg) (plus (reg) (const_int -1)))
+                      (additional clobbers and uses)])
+ 
+-         So we return that form instead.
++        For the third form we expect:
++
++        (parallel [(set (cc) (compare ((plus (reg) (const_int -1)), 0))
++                   (set (reg) (plus (reg) (const_int -1)))])
++        (set (pc) (if_then_else (cc == NE)
++                                (label_ref (label))
++                                (pc))) 
++
++        which is equivalent to the following:
++
++        (parallel [(set (cc) (compare (reg,  1))
++                   (set (reg) (plus (reg) (const_int -1)))
++                   (set (pc) (if_then_else (NE == cc)
++                                           (label_ref (label))
++                                           (pc))))])
++
++        So we return the second form instead for the two cases.
++
+      */
+         condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx);
+ 
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2009-11-25 10:55:54 +0000
++++ new/gcc/modulo-sched.c	2011-03-24 07:45:38 +0000
+@@ -116,8 +116,10 @@
+ 
+ /* The number of different iterations the nodes in ps span, assuming
+    the stage boundaries are placed efficiently.  */
+-#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
+-			     + 1 + (ps)->ii - 1) / (ps)->ii)
++#define CALC_STAGE_COUNT(min_cycle,max_cycle,ii) ((max_cycle - min_cycle \
++                         + 1 + ii - 1) / ii)
++/* The stage count of ps.  */
++#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
+ 
+ /* A single instruction in the partial schedule.  */
+ struct ps_insn
+@@ -155,6 +157,8 @@
+   int max_cycle;
+ 
+   ddg_ptr g;	/* The DDG of the insns in the partial schedule.  */
++
++  int stage_count;  /* The stage count of the partial schedule.  */
+ };
+ 
+ /* We use this to record all the register replacements we do in
+@@ -195,6 +199,7 @@
+                                     rtx, rtx);
+ static void duplicate_insns_of_cycles (partial_schedule_ptr,
+ 				       int, int, int, rtx);
++static int calculate_stage_count (partial_schedule_ptr ps);
+ 
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+@@ -310,10 +315,10 @@
+      either a single (parallel) branch-on-count or a (non-parallel)
+      branch immediately preceded by a single (decrement) insn.  */
+   first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
+-                             : PREV_INSN (tail));
++                             : prev_nondebug_insn (tail));
+ 
+   for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
+-    if (reg_mentioned_p (reg, insn))
++    if (reg_mentioned_p (reg, insn) && NONDEBUG_INSN_P (insn))
+       {
+         if (dump_file)
+         {
+@@ -332,6 +337,24 @@
+ #endif
+ }
+ 
++/* Mark in DOLOOP_INSNS the instructions that belong to the do-loop part.
++  Use TAIL to recognize that part.  */
++static void
++mark_doloop_insns (sbitmap doloop_insns, rtx tail)
++{
++  rtx first_insn_not_to_check, insn;
++
++  /* This is the first instruction which belongs the doloop part.  */
++  first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
++			     : prev_nondebug_insn (tail));
++
++  sbitmap_zero (doloop_insns);
++  for (insn = first_insn_not_to_check; insn != NEXT_INSN (tail);
++       insn = NEXT_INSN (insn))
++    if (NONDEBUG_INSN_P (insn))
++      SET_BIT (doloop_insns, INSN_UID (insn));
++}
++
+ /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
+    that the number of iterations is a compile-time constant.  If so,
+    return the rtx that sets COUNT_REG to a constant, and set COUNT to
+@@ -569,13 +592,12 @@
+     }
+ }
+ 
+-/* Bump the SCHED_TIMEs of all nodes to start from zero.  Set the values
+-   of SCHED_ROW and SCHED_STAGE.  */
++/* Bump the SCHED_TIMEs of all nodes by AMOUNT.  Set the values of
++   SCHED_ROW and SCHED_STAGE.  */
+ static void
+-normalize_sched_times (partial_schedule_ptr ps)
++reset_sched_times (partial_schedule_ptr ps, int amount)
+ {
+   int row;
+-  int amount = PS_MIN_CYCLE (ps);
+   int ii = ps->ii;
+   ps_insn_ptr crr_insn;
+ 
+@@ -584,6 +606,10 @@
+       {
+ 	ddg_node_ptr u = crr_insn->node;
+ 	int normalized_time = SCHED_TIME (u) - amount;
++	int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
++        /* The first cycle in row zero after the rotation.  */
++	int new_first_cycle_in_row_zero = 
++	  new_min_cycle + ii - SMODULO (new_min_cycle, ii);
+ 
+ 	if (dump_file)
+ 	  fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
+@@ -592,8 +618,30 @@
+ 	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+ 	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+ 	SCHED_TIME (u) = normalized_time;
+-	SCHED_ROW (u) = normalized_time % ii;
+-	SCHED_STAGE (u) = normalized_time / ii;
++	crr_insn->cycle = normalized_time;
++	SCHED_ROW (u) = SMODULO (normalized_time, ii);
++
++	/* If min_cycle is in row zero after the rotation then
++	   the stage count can be calculated by dividing the cycle
++	   with ii.  Otherwise, the calculation is done by dividing the
++	   SMSed kernel into two intervals:
++
++	   1) min_cycle	              <= interval 0 < first_cycle_in_row_zero
++	   2) first_cycle_in_row_zero <= interval 1 < max_cycle
++	   
++	   Cycles in interval 0 are in stage 0. The stage of cycles
++	   in interval 1 should be added by 1 to take interval 0 into
++	   account.  */
++	if (SMODULO (new_min_cycle, ii) == 0)
++          SCHED_STAGE (u) = normalized_time / ii;
++        else
++	  {
++            if (crr_insn->cycle < new_first_cycle_in_row_zero)
++	      SCHED_STAGE (u) = 0;
++	    else
++              SCHED_STAGE (u) = 
++		((SCHED_TIME (u) - new_first_cycle_in_row_zero) / ii) + 1;
++	  }
+       }
+ }
+ 
+@@ -646,9 +694,12 @@
+ 
+         /* Do not duplicate any insn which refers to count_reg as it
+            belongs to the control part.
++           If closing_branch_deps is true the closing branch is scheduled
++           as well and thus should be ignored.
+            TODO: This should be done by analyzing the control part of
+            the loop.  */
+-        if (reg_mentioned_p (count_reg, u_node->insn))
++        if (reg_mentioned_p (count_reg, u_node->insn)
++            || JUMP_P (ps_ij->node->insn))
+           continue;
+ 
+ 	if (for_prolog)
+@@ -894,7 +945,8 @@
+   basic_block condition_bb = NULL;
+   edge latch_edge;
+   gcov_type trip_count = 0;
+-
++  sbitmap doloop_insns;
++  
+   loop_optimizer_init (LOOPS_HAVE_PREHEADERS
+ 		       | LOOPS_HAVE_RECORDED_EXITS);
+   if (number_of_loops () <= 1)
+@@ -919,6 +971,7 @@
+   setup_sched_infos ();
+   haifa_sched_init ();
+ 
++  doloop_insns = sbitmap_alloc (get_max_uid () + 1);
+   /* Allocate memory to hold the DDG array one entry for each loop.
+      We use loop->num as index into this array.  */
+   g_arr = XCNEWVEC (ddg_ptr, number_of_loops ());
+@@ -1009,9 +1062,11 @@
+ 	continue;
+       }
+ 
+-      /* Don't handle BBs with calls or barriers, or !single_set insns,
+-         or auto-increment insns (to avoid creating invalid reg-moves
+-         for the auto-increment insns).
++      /* Don't handle BBs with calls or barriers or auto-increment insns 
++	 (to avoid creating invalid reg-moves for the auto-increment insns),
++	 or !single_set with the exception of instructions that include
++	 count_reg---these instructions are part of the control part
++	 that do-loop recognizes.
+          ??? Should handle auto-increment insns.
+          ??? Should handle insns defining subregs.  */
+      for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
+@@ -1021,7 +1076,8 @@
+         if (CALL_P (insn)
+             || BARRIER_P (insn)
+             || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
+-                && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
++                && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
++                && !reg_mentioned_p (count_reg, insn))
+             || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
+             || (INSN_P (insn) && (set = single_set (insn))
+                 && GET_CODE (SET_DEST (set)) == SUBREG))
+@@ -1048,14 +1104,16 @@
+ 
+ 	  continue;
+ 	}
+-
+-      if (! (g = create_ddg (bb, 0)))
++      mark_doloop_insns (doloop_insns, tail);
++      if (! (g = create_ddg (bb, doloop_insns)))
+         {
+           if (dump_file)
+ 	    fprintf (dump_file, "SMS create_ddg failed\n");
+ 	  continue;
+         }
+-
++      if (dump_file)
++        fprintf (dump_file, "SMS closing_branch_deps: %d\n", 
++                 g->closing_branch_deps); 
+       g_arr[loop->num] = g;
+       if (dump_file)
+         fprintf (dump_file, "...OK\n");
+@@ -1157,11 +1215,13 @@
+ 
+       ps = sms_schedule_by_order (g, mii, maxii, node_order);
+ 
+-      if (ps){
+-	stage_count = PS_STAGE_COUNT (ps);
+-        gcc_assert(stage_count >= 1);
+-      }
+-
++      if (ps)
++	{
++	  stage_count = calculate_stage_count (ps);
++	  gcc_assert(stage_count >= 1);
++	  PS_STAGE_COUNT(ps) = stage_count;
++	}
++      
+       /* Stage count of 1 means that there is no interleaving between
+          iterations, let the scheduling passes do the job.  */
+       if (stage_count <= 1
+@@ -1182,17 +1242,7 @@
+       else
+ 	{
+ 	  struct undo_replace_buff_elem *reg_move_replaces;
+-
+-	  if (dump_file)
+-	    {
+-	      fprintf (dump_file,
+-		       "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
+-		       stage_count);
+-	      print_partial_schedule (ps, dump_file);
+-	      fprintf (dump_file,
+-		       "SMS Branch (%d) will later be scheduled at cycle %d.\n",
+-		       g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
+-	    }
++	  int amount;
+ 
+ 	  /* Set the stage boundaries.  If the DDG is built with closing_branch_deps,
+ 	     the closing_branch was scheduled and should appear in the last (ii-1)
+@@ -1202,12 +1252,28 @@
+              TODO: Revisit the issue of scheduling the insns of the
+              control part relative to the branch when the control part
+              has more than one insn.  */
+-	  normalize_sched_times (ps);
+-	  rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
++	  amount = (g->closing_branch_deps)? SCHED_TIME (g->closing_branch) + 1: 
++	    PS_MIN_CYCLE (ps);
++	  reset_sched_times (ps, amount);
++	  rotate_partial_schedule (ps, amount);
++	  
+ 	  set_columns_for_ps (ps);
+ 
+ 	  canon_loop (loop);
+ 
++          if (dump_file)
++            {
++	      fprintf (dump_file,
++		       "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
++		       stage_count);
++	      print_partial_schedule (ps, dump_file);
++	      if (!g->closing_branch_deps)
++		fprintf (dump_file,
++			 "SMS Branch (%d) will later be scheduled at \
++			 cycle %d.\n",
++			 g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
++            }
++
+           /* case the BCT count is not known , Do loop-versioning */
+ 	  if (count_reg && ! count_init)
+             {
+@@ -1252,6 +1318,7 @@
+     }
+ 
+   free (g_arr);
++  sbitmap_free (doloop_insns);
+ 
+   /* Release scheduler data, needed until now because of DFA.  */
+   haifa_sched_finish ();
+@@ -1759,8 +1826,9 @@
+ 	      RESET_BIT (tobe_scheduled, u);
+ 	      continue;
+ 	    }
+-
+-	  if (JUMP_P (insn)) /* Closing branch handled later.  */
++	  /* Closing branch handled later unless closing_branch_deps
++	     is true.  */
++	  if (JUMP_P (insn) && !g->closing_branch_deps) 
+ 	    {
+ 	      RESET_BIT (tobe_scheduled, u);
+ 	      continue;
+@@ -1893,8 +1961,8 @@
+   if (dump_file)
+     fprintf (dump_file, "split_row=%d\n", split_row);
+ 
+-  normalize_sched_times (ps);
+-  rotate_partial_schedule (ps, ps->min_cycle);
++  reset_sched_times (ps, PS_MIN_CYCLE (ps));
++  rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
+ 
+   rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
+   for (row = 0; row < split_row; row++)
+@@ -2571,6 +2639,7 @@
+   ps_insn_ptr next_ps_i;
+   ps_insn_ptr first_must_follow = NULL;
+   ps_insn_ptr last_must_precede = NULL;
++  ps_insn_ptr last_in_row = NULL;
+   int row;
+ 
+   if (! ps_i)
+@@ -2597,8 +2666,37 @@
+ 	  else
+             last_must_precede = next_ps_i;
+         }
++      /* The closing branch must be the last in the row.  */
++      if (must_precede 
++	  && TEST_BIT (must_precede, next_ps_i->node->cuid) 
++	  && JUMP_P (next_ps_i->node->insn))     
++	return false;
++             
++       last_in_row = next_ps_i;
+     }
+ 
++  /* If closing_branch_deps is true we are scheduling the closing
++     branch as well.  Make sure there is no dependent instruction after
++     it as the branch should be the last instruction.  */
++  if (JUMP_P (ps_i->node->insn)) 
++    {
++      if (first_must_follow)
++	return false;
++      if (last_in_row)
++	{
++	  /* Make the branch the last in the row.  New instructions
++	     will be inserted at the beginning of the row or after the
++	     last must_precede instruction thus the branch is guaranteed
++	     to remain the last instruction in the row.  */
++	  last_in_row->next_in_row = ps_i;
++	  ps_i->prev_in_row = last_in_row;
++	  ps_i->next_in_row = NULL;
++	}
++      else
++	ps->rows[row] = ps_i;
++      return true;
++    }
++  
+   /* Now insert the node after INSERT_AFTER_PSI.  */
+ 
+   if (! last_must_precede)
+@@ -2820,6 +2918,54 @@
+   return ps_i;
+ }
+ 
++/* Calculate the stage count of the partial schedule PS.  */
++int
++calculate_stage_count (partial_schedule_ptr ps)
++{
++  int stage_count;
++
++  /* If closing_branch_deps is false then the stage
++     boundaries are placed efficiently, meaning that min_cycle will be
++     placed at row 0. Otherwise, the closing branch will be placed in
++     row ii-1. For the later case we assume the final SMSed kernel can
++     be divided into two intervals. This assumption is used for the
++     stage count calculation:
++
++     1) min_cycle               <= interval 0 < first_cycle_in_row_zero
++     2) first_cycle_in_row_zero <= interval 1 < max_cycle
++   */
++  stage_count =
++    CALC_STAGE_COUNT (PS_MIN_CYCLE (ps), PS_MAX_CYCLE (ps), ps->ii);
++  if (ps->g->closing_branch_deps)
++    {
++      int new_min_cycle;
++      int new_min_cycle_row;
++      int rotation_amount = SCHED_TIME (ps->g->closing_branch) + 1;
++
++      /* This is the new value of min_cycle after the final rotation to
++         bring closing branch into row ii-1.  */
++      new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
++      /* This is the row which the the new min_cycle will be placed in.  */
++      new_min_cycle_row = SMODULO (new_min_cycle, ps->ii);
++      /* If the row of min_cycle is zero then interval 0 is empty.
++         Otherwise, we need to calculate interval 1 and add it by one
++         to take interval 0 into account.  */
++      if (new_min_cycle_row != 0)
++	{
++	  int new_max_cycle, first_cycle_in_row_zero;
++
++	  new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
++	  first_cycle_in_row_zero =
++	    new_min_cycle + ps->ii - new_min_cycle_row;
++
++	  stage_count =
++	    CALC_STAGE_COUNT (first_cycle_in_row_zero, new_max_cycle,
++			      ps->ii) + 1;
++	}
++    }
++  return stage_count;
++}
++
+ /* Rotate the rows of PS such that insns scheduled at time
+    START_CYCLE will appear in row 0.  Updates max/min_cycles.  */
+ void
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99498.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99498.patch
new file mode 100644
index 0000000000..9c305cc651
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99498.patch
@@ -0,0 +1,186 @@
+2011-02-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Issue #10439
+	gcc/
+	* config/arm/unwind-arm.c (enum __cxa_type_match_result): New.
+	(cxa_type_match): Correct declaration.
+	(__gnu_unwind_pr_common): Reconstruct
+	additional indirection when __cxa_type_match returns
+	succeeded_with_ptr_to_base.
+
+	libstdc++/
+	* libsupc++/eh_arm.c (__cxa_type_match): Construct address of
+	thrown object here.  Return succeded_with_ptr_to_base for all
+	pointer cases.
+
+=== modified file 'gcc/config/arm/unwind-arm.c'
+--- old/gcc/config/arm/unwind-arm.c	2010-08-12 12:39:35 +0000
++++ new/gcc/config/arm/unwind-arm.c	2011-04-08 10:41:46 +0000
+@@ -32,13 +32,18 @@
+ typedef unsigned char bool;
+ 
+ typedef struct _ZSt9type_info type_info; /* This names C++ type_info type */
++enum __cxa_type_match_result
++  {
++    ctm_failed = 0,
++    ctm_succeeded = 1,
++    ctm_succeeded_with_ptr_to_base = 2
++  };
+ 
+ void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp);
+ bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp);
+-bool __attribute__((weak)) __cxa_type_match(_Unwind_Control_Block *ucbp,
+-					    const type_info *rttip,
+-					    bool is_reference,
+-					    void **matched_object);
++enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match
++  (_Unwind_Control_Block *ucbp, const type_info *rttip,
++   bool is_reference, void **matched_object);
+ 
+ _Unwind_Ptr __attribute__((weak))
+ __gnu_Unwind_Find_exidx (_Unwind_Ptr, int *);
+@@ -1107,6 +1112,7 @@
+ 		      _uw rtti;
+ 		      bool is_reference = (data[0] & uint32_highbit) != 0;
+ 		      void *matched;
++		      enum __cxa_type_match_result match_type;
+ 
+ 		      /* Check for no-throw areas.  */
+ 		      if (data[1] == (_uw) -2)
+@@ -1118,17 +1124,31 @@
+ 			{
+ 			  /* Match a catch specification.  */
+ 			  rtti = _Unwind_decode_target2 ((_uw) &data[1]);
+-			  if (!__cxa_type_match (ucbp, (type_info *) rtti,
+-						 is_reference,
+-						 &matched))
+-			    matched = (void *)0;
++			  match_type = __cxa_type_match (ucbp,
++							 (type_info *) rtti,
++							 is_reference,
++							 &matched);
+ 			}
++		      else
++			match_type = ctm_succeeded;
+ 
+-		      if (matched)
++		      if (match_type)
+ 			{
+ 			  ucbp->barrier_cache.sp =
+ 			    _Unwind_GetGR (context, R_SP);
+-			  ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
++			  // ctm_succeeded_with_ptr_to_base really
++			  // means _c_t_m indirected the pointer
++			  // object.  We have to reconstruct the
++			  // additional pointer layer by using a temporary.
++			  if (match_type == ctm_succeeded_with_ptr_to_base)
++			    {
++			      ucbp->barrier_cache.bitpattern[2]
++				= (_uw) matched;
++			      ucbp->barrier_cache.bitpattern[0]
++				= (_uw) &ucbp->barrier_cache.bitpattern[2];
++			    }
++			  else
++			    ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
+ 			  ucbp->barrier_cache.bitpattern[1] = (_uw) data;
+ 			  return _URC_HANDLER_FOUND;
+ 			}
+
+=== modified file 'libstdc++-v3/libsupc++/eh_arm.cc'
+--- old/libstdc++-v3/libsupc++/eh_arm.cc	2009-04-09 14:00:19 +0000
++++ new/libstdc++-v3/libsupc++/eh_arm.cc	2011-04-08 10:41:46 +0000
+@@ -30,10 +30,11 @@
+ using namespace __cxxabiv1;
+ 
+ 
+-// Given the thrown type THROW_TYPE, pointer to a variable containing a
+-// pointer to the exception object THROWN_PTR_P and a type CATCH_TYPE to
+-// compare against, return whether or not there is a match and if so,
+-// update *THROWN_PTR_P.
++// Given the thrown type THROW_TYPE, exception object UE_HEADER and a
++// type CATCH_TYPE to compare against, return whether or not there is
++// a match and if so, update *THROWN_PTR_P to point to either the
++// type-matched object, or in the case of a pointer type, the object
++// pointed to by the pointer.
+ 
+ extern "C" __cxa_type_match_result
+ __cxa_type_match(_Unwind_Exception* ue_header,
+@@ -41,51 +42,51 @@
+ 		 bool is_reference __attribute__((__unused__)),
+ 		 void** thrown_ptr_p)
+ {
+-  bool forced_unwind = __is_gxx_forced_unwind_class(ue_header->exception_class);
+-  bool foreign_exception = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
+-  bool dependent_exception =
+-    __is_dependent_exception(ue_header->exception_class);
++  bool forced_unwind
++    = __is_gxx_forced_unwind_class(ue_header->exception_class);
++  bool foreign_exception
++    = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
++  bool dependent_exception
++    = __is_dependent_exception(ue_header->exception_class);
+   __cxa_exception* xh = __get_exception_header_from_ue(ue_header);
+   __cxa_dependent_exception *dx = __get_dependent_exception_from_ue(ue_header);
+   const std::type_info* throw_type;
++  void *thrown_ptr = 0;
+ 
+   if (forced_unwind)
+     throw_type = &typeid(abi::__forced_unwind);
+   else if (foreign_exception)
+     throw_type = &typeid(abi::__foreign_exception);
+-  else if (dependent_exception)
+-    throw_type = __get_exception_header_from_obj
+-      (dx->primaryException)->exceptionType;
+   else
+-    throw_type = xh->exceptionType;
+-
+-  void* thrown_ptr = *thrown_ptr_p;
++    {
++      if (dependent_exception)
++	xh = __get_exception_header_from_obj (dx->primaryException);
++      throw_type = xh->exceptionType;
++      // We used to require the caller set the target of thrown_ptr_p,
++      // but that's incorrect -- the EHABI makes no such requirement
++      // -- and not all callers will set it.  Fortunately callers that
++      // do initialize will always pass us the value we calculate
++      // here, so there's no backwards compatibility problem.
++      thrown_ptr = __get_object_from_ue (ue_header);
++    }
++  
++  __cxa_type_match_result result = ctm_succeeded;
+ 
+   // Pointer types need to adjust the actual pointer, not
+   // the pointer to pointer that is the exception object.
+   // This also has the effect of passing pointer types
+   // "by value" through the __cxa_begin_catch return value.
+   if (throw_type->__is_pointer_p())
+-    thrown_ptr = *(void**) thrown_ptr;
++    {
++      thrown_ptr = *(void**) thrown_ptr;
++      // We need to indicate the indirection to our caller.
++      result = ctm_succeeded_with_ptr_to_base;
++    }
+ 
+   if (catch_type->__do_catch(throw_type, &thrown_ptr, 1))
+     {
+       *thrown_ptr_p = thrown_ptr;
+-
+-      if (typeid(*catch_type) == typeid (typeid(void*)))
+-	{
+-	  const __pointer_type_info *catch_pointer_type =
+-	    static_cast<const __pointer_type_info *> (catch_type);
+-	  const __pointer_type_info *throw_pointer_type =
+-	    static_cast<const __pointer_type_info *> (throw_type);
+-
+-	  if (typeid (*catch_pointer_type->__pointee) != typeid (void)
+-	      && (*catch_pointer_type->__pointee != 
+-		  *throw_pointer_type->__pointee))
+-	    return ctm_succeeded_with_ptr_to_base;
+-	}
+-
+-      return ctm_succeeded;
++      return result;
+     }
+ 
+   return ctm_failed;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99502.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99502.patch
new file mode 100644
index 0000000000..59bf01cc56
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99502.patch
@@ -0,0 +1,134 @@
+2011-04-26  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2011-03-21  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* simplify-rtx.c (simplify_binary_operation_1): Handle
+	(xor (and A B) C) case when B and C are both constants.
+
+	gcc/testsuite/
+	* gcc.target/arm/xor-and.c: New.
+
+	2011-03-18  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* combine.c (try_combine): Do simplification only call of
+	subst() on i2 even when i1 is present. Update comments.
+
+	gcc/testsuite/
+	* gcc.target/arm/unsigned-extend-1.c: New.
+
+=== modified file 'gcc/combine.c'
+--- old/gcc/combine.c	2011-01-06 11:02:44 +0000
++++ new/gcc/combine.c	2011-04-14 13:58:12 +0000
+@@ -2939,7 +2939,7 @@
+       /* It is possible that the source of I2 or I1 may be performing
+ 	 an unneeded operation, such as a ZERO_EXTEND of something
+ 	 that is known to have the high part zero.  Handle that case
+-	 by letting subst look at the innermost one of them.
++	 by letting subst look at the inner insns.
+ 
+ 	 Another way to do this would be to have a function that tries
+ 	 to simplify a single insn instead of merging two or more
+@@ -2964,11 +2964,9 @@
+ 	      subst_low_luid = DF_INSN_LUID (i1);
+ 	      i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	    }
+-	  else
+-	    {
+-	      subst_low_luid = DF_INSN_LUID (i2);
+-	      i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
+-	    }
++
++	  subst_low_luid = DF_INSN_LUID (i2);
++	  i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	}
+ 
+       n_occurrences = 0;		/* `subst' counts here */
+
+=== modified file 'gcc/simplify-rtx.c'
+--- old/gcc/simplify-rtx.c	2010-06-25 20:11:56 +0000
++++ new/gcc/simplify-rtx.c	2011-04-14 13:58:12 +0000
+@@ -2413,6 +2413,46 @@
+ 							XEXP (op0, 1), mode),
+ 				    op1);
+ 
++      /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
++	 we can transform like this:
++            (A&B)^C == ~(A&B)&C | ~C&(A&B)
++                    == (~A|~B)&C | ~C&(A&B)    * DeMorgan's Law
++                    == ~A&C | ~B&C | A&(~C&B)  * Distribute and re-order
++	 Attempt a few simplifications when B and C are both constants.  */
++      if (GET_CODE (op0) == AND
++	  && CONST_INT_P (op1)
++	  && CONST_INT_P (XEXP (op0, 1)))
++	{
++	  rtx a = XEXP (op0, 0);
++	  rtx b = XEXP (op0, 1);
++	  rtx c = op1;
++	  HOST_WIDE_INT bval = INTVAL (b);
++	  HOST_WIDE_INT cval = INTVAL (c);
++
++	  rtx na_c
++	    = simplify_binary_operation (AND, mode,
++					 simplify_gen_unary (NOT, mode, a, mode),
++					 c);
++	  if ((~cval & bval) == 0)
++	    {
++	      /* Try to simplify ~A&C | ~B&C.  */
++	      if (na_c != NULL_RTX)
++		return simplify_gen_binary (IOR, mode, na_c,
++					    GEN_INT (~bval & cval));
++	    }
++	  else
++	    {
++	      /* If ~A&C is zero, simplify A&(~C&B) | ~B&C.  */
++	      if (na_c == const0_rtx)
++		{
++		  rtx a_nc_b = simplify_gen_binary (AND, mode, a,
++						    GEN_INT (~cval & bval));
++		  return simplify_gen_binary (IOR, mode, a_nc_b,
++					      GEN_INT (~bval & cval));
++		}
++	    }
++	}
++
+       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
+ 	 comparison if STORE_FLAG_VALUE is 1.  */
+       if (STORE_FLAG_VALUE == 1
+
+=== added file 'gcc/testsuite/gcc.target/arm/unsigned-extend-1.c'
+--- old/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c	2011-04-14 13:58:12 +0000
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv6" } */
++
++unsigned char foo (unsigned char c)
++{
++  return (c >= '0') && (c <= '9');
++}
++
++/* { dg-final { scan-assembler-not "uxtb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/xor-and.c'
+--- old/gcc/testsuite/gcc.target/arm/xor-and.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/xor-and.c	2011-04-14 13:58:12 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O -march=armv6" } */
++
++unsigned short foo (unsigned short x)
++{
++  x ^= 0x4002;
++  x >>= 1;
++  x |= 0x8000;
++  return x;
++}
++
++/* { dg-final { scan-assembler "orr" } } */
++/* { dg-final { scan-assembler-not "mvn" } } */
++/* { dg-final { scan-assembler-not "uxth" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99503.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99503.patch
new file mode 100644
index 0000000000..abbd95b4db
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99503.patch
@@ -0,0 +1,6070 @@
+2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	From  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/46329
+	* gcc.target/arm/pr46329.c: New test.
+
+	gcc/
+	PR target/46329
+	* config/arm/arm.c (arm_legitimate_constant_p_1): Return false
+	for all Neon struct constants.
+
+2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* doc/tm.texi (LEGITIMATE_CONSTANT_P): Replace with...
+	(TARGET_LEGITIMATE_CONSTANT_P): ...this.
+	* target.h (gcc_target): Add legitimate_constant_p.
+	* target-def.h (TARGET_LEGITIMATE_CONSTANT_P): Define.
+	(TARGET_INITIALIZER): Include it.
+	* calls.c (precompute_register_parameters): Replace uses of
+	LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p.
+	(emit_library_call_value_1): Likewise.
+	* expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn)
+	(compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise.
+	* recog.c (general_operand, immediate_operand): Likewise.
+	* reload.c (find_reloads_toplev, find_reloads_address_part): Likewise.
+	* reload1.c (init_eliminable_invariants): Likewise.
+	* targhooks.h (default_legitimate_constant_p); Declare.
+	* targhooks.c (default_legitimate_constant_p): New function.
+
+	* config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete.
+	* config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise.
+	(THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise.
+	* config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define.
+	(arm_legitimate_constant_p_1, thumb_legitimate_constant_p)
+	(arm_legitimate_constant_p): New functions.
+	(arm_cannot_force_const_mem): Make static.
+
+2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* hooks.h (hook_bool_mode_uhwi_false): Declare.
+	* hooks.c (hook_bool_mode_uhwi_false): New function.
+	* doc/tm.texi (TARGET_ARRAY_MODE_SUPPORTED_P): Document.
+	* target.h (array_mode_supported_p): New hook.
+	* target-def.h (TARGET_ARRAY_MODE_SUPPORTED_P): Define if undefined.
+	(TARGET_INITIALIZER): Include it.
+	* stor-layout.c (mode_for_array): New function.
+	(layout_type): Use it.
+	* config/arm/arm.c (arm_array_mode_supported_p): New function.
+	(TARGET_ARRAY_MODE_SUPPORTED_P): Define.
+
+2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-04-12  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/arm/neon-vld3-1.c: New test.
+	* gcc.target/arm/neon-vst3-1.c: New test.
+	* gcc.target/arm/neon/v*.c: Regenerate.
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-12  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
+	size of a '%A' memory reference.
+	(T_DREG, T_QREG): New neon_builtin_type_bits.
+	(arm_init_neon_builtins): Assert that the load and store operands
+	are neon_struct_operands.
+	(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
+	(NEON_ARG_MEMORY): New builtin_arg.
+	(neon_dereference_pointer): New function.
+	(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
+	Handle NEON_ARG_MEMORY.
+	(arm_expand_neon_builtin): Update after above interface changes.
+	Use NEON_ARG_MEMORY for loads and stores.
+	* config/arm/predicates.md (neon_struct_operand): New predicate.
+	* config/arm/neon.md (V_two_elem): Tweak formatting.
+	(V_three_elem): Use BLKmode for accesses that have no associated mode.
+	(neon_vld1<mode>, neon_vld1_dup<mode>)
+	(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
+	(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
+	(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
+	(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
+	(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
+	(neon_vst4<mode>): Replace pointer operand with a memory operand.
+	Use %A in the output template.
+	(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
+	(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
+	(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
+	the width of the memory access.  Remove post-increment.
+	* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
+
+2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-03-30  Richard Sandiford  <richard.sandiford@linaro.org>
+		    Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/43590
+	* config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove
+	operand 1 and reshuffle the operands to match.
+	(neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
+
+=== modified file 'gcc/calls.c'
+--- old/gcc/calls.c	2010-11-04 12:43:52 +0000
++++ new/gcc/calls.c	2011-04-20 10:07:36 +0000
+@@ -674,7 +674,7 @@
+ 	/* If the value is a non-legitimate constant, force it into a
+ 	   pseudo now.  TLS symbols sometimes need a call to resolve.  */
+ 	if (CONSTANT_P (args[i].value)
+-	    && !LEGITIMATE_CONSTANT_P (args[i].value))
++	    && !targetm.legitimate_constant_p (args[i].mode, args[i].value))
+ 	  args[i].value = force_reg (args[i].mode, args[i].value);
+ 
+ 	/* If we are to promote the function arg to a wider mode,
+@@ -3413,7 +3413,8 @@
+ 
+       /* Make sure it is a reasonable operand for a move or push insn.  */
+       if (!REG_P (addr) && !MEM_P (addr)
+-	  && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
++	  && !(CONSTANT_P (addr)
++	       && targetm.legitimate_constant_p (Pmode, addr)))
+ 	addr = force_operand (addr, NULL_RTX);
+ 
+       argvec[count].value = addr;
+@@ -3453,7 +3454,7 @@
+ 
+       /* Make sure it is a reasonable operand for a move or push insn.  */
+       if (!REG_P (val) && !MEM_P (val)
+-	  && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
++	  && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val)))
+ 	val = force_operand (val, NULL_RTX);
+ 
+       if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-02-08 12:07:29 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-04-20 10:07:36 +0000
+@@ -81,7 +81,6 @@
+ extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
+ 						     bool);
+ extern bool arm_tls_referenced_p (rtx);
+-extern bool arm_cannot_force_const_mem (rtx);
+ 
+ extern int cirrus_memory_offset (rtx);
+ extern int arm_coproc_mem_operand (rtx, bool);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-03-02 11:29:06 +0000
++++ new/gcc/config/arm/arm.c	2011-04-20 10:10:50 +0000
+@@ -140,6 +140,8 @@
+ static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
+ 				 tree);
+ static bool arm_have_conditional_execution (void);
++static bool arm_cannot_force_const_mem (rtx);
++static bool arm_legitimate_constant_p (enum machine_mode, rtx);
+ static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
+ static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+ static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+@@ -222,6 +224,8 @@
+ static tree arm_promoted_type (const_tree t);
+ static tree arm_convert_to_type (tree type, tree expr);
+ static bool arm_scalar_mode_supported_p (enum machine_mode);
++static bool arm_array_mode_supported_p (enum machine_mode,
++					unsigned HOST_WIDE_INT);
+ static bool arm_frame_pointer_required (void);
+ static bool arm_can_eliminate (const int, const int);
+ static void arm_asm_trampoline_template (FILE *);
+@@ -355,6 +359,8 @@
+ #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
+ #undef TARGET_VECTOR_MODE_SUPPORTED_P
+ #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
++#undef TARGET_ARRAY_MODE_SUPPORTED_P
++#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
+ 
+ #undef  TARGET_MACHINE_DEPENDENT_REORG
+ #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
+@@ -467,6 +473,9 @@
+ #undef TARGET_HAVE_CONDITIONAL_EXECUTION
+ #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
+ 
++#undef TARGET_LEGITIMATE_CONSTANT_P
++#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
++
+ #undef TARGET_CANNOT_FORCE_CONST_MEM
+ #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
+ 
+@@ -6447,9 +6456,47 @@
+   return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
+ }
+ 
++/* Implement TARGET_LEGITIMATE_CONSTANT_P.
++
++   On the ARM, allow any integer (invalid ones are removed later by insn
++   patterns), nice doubles and symbol_refs which refer to the function's
++   constant pool XXX.
++
++   When generating pic allow anything.  */
++
++static bool
++arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
++{
++  /* At present, we have no support for Neon structure constants, so forbid
++     them here.  It might be possible to handle simple cases like 0 and -1
++     in future.  */
++  if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
++    return false;
++
++  return flag_pic || !label_mentioned_p (x);
++}
++
++static bool
++thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
++{
++  return (GET_CODE (x) == CONST_INT
++	  || GET_CODE (x) == CONST_DOUBLE
++	  || CONSTANT_ADDRESS_P (x)
++	  || flag_pic);
++}
++
++static bool
++arm_legitimate_constant_p (enum machine_mode mode, rtx x)
++{
++  return (!arm_cannot_force_const_mem (x)
++	  && (TARGET_32BIT
++	      ? arm_legitimate_constant_p_1 (mode, x)
++	      : thumb_legitimate_constant_p (mode, x)));
++}
++
+ /* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */
+ 
+-bool
++static bool
+ arm_cannot_force_const_mem (rtx x)
+ {
+   rtx base, offset;
+@@ -16847,7 +16894,7 @@
+       {
+ 	rtx addr;
+ 	bool postinc = FALSE;
+-	unsigned align, modesize, align_bits;
++	unsigned align, memsize, align_bits;
+ 
+ 	gcc_assert (GET_CODE (x) == MEM);
+ 	addr = XEXP (x, 0);
+@@ -16862,12 +16909,12 @@
+ 	   instruction (for some alignments) as an aid to the memory subsystem
+ 	   of the target.  */
+ 	align = MEM_ALIGN (x) >> 3;
+-	modesize = GET_MODE_SIZE (GET_MODE (x));
++	memsize = INTVAL (MEM_SIZE (x));
+ 	
+ 	/* Only certain alignment specifiers are supported by the hardware.  */
+-	if (modesize == 16 && (align % 32) == 0)
++	if (memsize == 16 && (align % 32) == 0)
+ 	  align_bits = 256;
+-	else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
++	else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
+ 	  align_bits = 128;
+ 	else if ((align % 8) == 0)
+ 	  align_bits = 64;
+@@ -16875,7 +16922,7 @@
+ 	  align_bits = 0;
+ 	
+ 	if (align_bits != 0)
+-	  asm_fprintf (stream, ", :%d", align_bits);
++	  asm_fprintf (stream, ":%d", align_bits);
+ 
+ 	asm_fprintf (stream, "]");
+ 
+@@ -18398,12 +18445,14 @@
+   T_V2SI  = 0x0004,
+   T_V2SF  = 0x0008,
+   T_DI    = 0x0010,
++  T_DREG  = 0x001F,
+   T_V16QI = 0x0020,
+   T_V8HI  = 0x0040,
+   T_V4SI  = 0x0080,
+   T_V4SF  = 0x0100,
+   T_V2DI  = 0x0200,
+   T_TI	  = 0x0400,
++  T_QREG  = 0x07E0,
+   T_EI	  = 0x0800,
+   T_OI	  = 0x1000
+ };
+@@ -19049,10 +19098,9 @@
+ 		    if (is_load && k == 1)
+ 		      {
+ 		        /* Neon load patterns always have the memory operand
+-			   (a SImode pointer) in the operand 1 position.  We
+-			   want a const pointer to the element type in that
+-			   position.  */
+-		        gcc_assert (insn_data[icode].operand[k].mode == SImode);
++			   in the operand 1 position.  */
++			gcc_assert (insn_data[icode].operand[k].predicate
++				    == neon_struct_operand);
+ 
+ 			switch (1 << j)
+ 			  {
+@@ -19087,10 +19135,9 @@
+ 		    else if (is_store && k == 0)
+ 		      {
+ 		        /* Similarly, Neon store patterns use operand 0 as
+-			   the memory location to store to (a SImode pointer).
+-			   Use a pointer to the element type of the store in
+-			   that position.  */
+-			gcc_assert (insn_data[icode].operand[k].mode == SImode);
++			   the memory location to store to.  */
++			gcc_assert (insn_data[icode].operand[k].predicate
++				    == neon_struct_operand);
+ 
+ 			switch (1 << j)
+ 			  {
+@@ -19410,10 +19457,11 @@
+ }
+ 
+ static enum insn_code
+-locate_neon_builtin_icode (int fcode, neon_itype *itype)
++locate_neon_builtin_icode (int fcode, neon_itype *itype,
++			   enum neon_builtin_type_bits *type_bit)
+ {
+   neon_builtin_datum key, *found;
+-  int idx;
++  int idx, type, ntypes;
+ 
+   key.base_fcode = fcode;
+   found = (neon_builtin_datum *)
+@@ -19426,20 +19474,83 @@
+   if (itype)
+     *itype = found->itype;
+ 
++  if (type_bit)
++    {
++      ntypes = 0;
++      for (type = 0; type < T_MAX; type++)
++	if (found->bits & (1 << type))
++	  {
++	    if (ntypes == idx)
++	      break;
++	    ntypes++;
++	  }
++      gcc_assert (type < T_MAX);
++      *type_bit = (enum neon_builtin_type_bits) (1 << type);
++    }
+   return found->codes[idx];
+ }
+ 
+ typedef enum {
+   NEON_ARG_COPY_TO_REG,
+   NEON_ARG_CONSTANT,
++  NEON_ARG_MEMORY,
+   NEON_ARG_STOP
+ } builtin_arg;
+ 
+ #define NEON_MAX_BUILTIN_ARGS 5
+ 
++/* EXP is a pointer argument to a Neon load or store intrinsic.  Derive
++   and return an expression for the accessed memory.
++
++   The intrinsic function operates on a block of registers that has
++   mode REG_MODE.  This block contains vectors of type TYPE_BIT.
++   The function references the memory at EXP in mode MEM_MODE;
++   this mode may be BLKmode if no more suitable mode is available.  */
++
++static tree
++neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
++			  enum machine_mode reg_mode,
++			  enum neon_builtin_type_bits type_bit)
++{
++  HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
++  tree elem_type, upper_bound, array_type;
++
++  /* Work out the size of the register block in bytes.  */
++  reg_size = GET_MODE_SIZE (reg_mode);
++
++  /* Work out the size of each vector in bytes.  */
++  gcc_assert (type_bit & (T_DREG | T_QREG));
++  vector_size = (type_bit & T_QREG ? 16 : 8);
++
++  /* Work out how many vectors there are.  */
++  gcc_assert (reg_size % vector_size == 0);
++  nvectors = reg_size / vector_size;
++
++  /* Work out how many elements are being loaded or stored.
++     MEM_MODE == REG_MODE implies a one-to-one mapping between register
++     and memory elements; anything else implies a lane load or store.  */
++  if (mem_mode == reg_mode)
++    nelems = vector_size * nvectors;
++  else
++    nelems = nvectors;
++
++  /* Work out the type of each element.  */
++  gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
++  elem_type = TREE_TYPE (TREE_TYPE (exp));
++
++  /* Create a type that describes the full access.  */
++  upper_bound = build_int_cst (size_type_node, nelems - 1);
++  array_type = build_array_type (elem_type, build_index_type (upper_bound));
++
++  /* Dereference EXP using that type.  */
++  exp = convert (build_pointer_type (array_type), exp);
++  return fold_build1 (INDIRECT_REF, array_type, exp);
++}
++
+ /* Expand a Neon builtin.  */
+ static rtx
+ arm_expand_neon_args (rtx target, int icode, int have_retval,
++		      enum neon_builtin_type_bits type_bit,
+ 		      tree exp, ...)
+ {
+   va_list ap;
+@@ -19448,7 +19559,9 @@
+   rtx op[NEON_MAX_BUILTIN_ARGS];
+   enum machine_mode tmode = insn_data[icode].operand[0].mode;
+   enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
++  enum machine_mode other_mode;
+   int argc = 0;
++  int opno;
+ 
+   if (have_retval
+       && (!target
+@@ -19466,26 +19579,46 @@
+         break;
+       else
+         {
++          opno = argc + have_retval;
++          mode[argc] = insn_data[icode].operand[opno].mode;
+           arg[argc] = CALL_EXPR_ARG (exp, argc);
++          if (thisarg == NEON_ARG_MEMORY)
++            {
++              other_mode = insn_data[icode].operand[1 - opno].mode;
++              arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
++                                                    other_mode, type_bit);
++            }
+           op[argc] = expand_normal (arg[argc]);
+-          mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
+ 
+           switch (thisarg)
+             {
+             case NEON_ARG_COPY_TO_REG:
+               /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
+-              if (!(*insn_data[icode].operand[argc + have_retval].predicate)
++              if (!(*insn_data[icode].operand[opno].predicate)
+                      (op[argc], mode[argc]))
+                 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
+               break;
+ 
+             case NEON_ARG_CONSTANT:
+               /* FIXME: This error message is somewhat unhelpful.  */
+-              if (!(*insn_data[icode].operand[argc + have_retval].predicate)
++              if (!(*insn_data[icode].operand[opno].predicate)
+                     (op[argc], mode[argc]))
+ 		error ("argument must be a constant");
+               break;
+ 
++            case NEON_ARG_MEMORY:
++	      gcc_assert (MEM_P (op[argc]));
++	      PUT_MODE (op[argc], mode[argc]);
++	      /* ??? arm_neon.h uses the same built-in functions for signed
++		 and unsigned accesses, casting where necessary.  This isn't
++		 alias safe.  */
++	      set_mem_alias_set (op[argc], 0);
++	      if (!(*insn_data[icode].operand[opno].predicate)
++                    (op[argc], mode[argc]))
++		op[argc] = (replace_equiv_address
++			    (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
++              break;
++
+             case NEON_ARG_STOP:
+               gcc_unreachable ();
+             }
+@@ -19564,14 +19697,15 @@
+ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+ {
+   neon_itype itype;
+-  enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
++  enum neon_builtin_type_bits type_bit;
++  enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
+ 
+   switch (itype)
+     {
+     case NEON_UNOP:
+     case NEON_CONVERT:
+     case NEON_DUPLANE:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_BINOP:
+@@ -19581,90 +19715,90 @@
+     case NEON_SCALARMULH:
+     case NEON_SHIFTINSERT:
+     case NEON_LOGICBINOP:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_STOP);
+ 
+     case NEON_TERNOP:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_GETLANE:
+     case NEON_FIXCONV:
+     case NEON_SHIFTIMM:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
+         NEON_ARG_STOP);
+ 
+     case NEON_CREATE:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_DUP:
+     case NEON_SPLIT:
+     case NEON_REINTERP:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_COMBINE:
+     case NEON_VTBL:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_RESULTPAIR:
+-      return arm_expand_neon_args (target, icode, 0, exp,
++      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_STOP);
+ 
+     case NEON_LANEMUL:
+     case NEON_LANEMULL:
+     case NEON_LANEMULH:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_LANEMAC:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SHIFTACC:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SCALARMAC:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SELECT:
+     case NEON_VTBX:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_STOP);
+ 
+     case NEON_LOAD1:
+     case NEON_LOADSTRUCT:
+-      return arm_expand_neon_args (target, icode, 1, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_STOP);
+ 
+     case NEON_LOAD1LANE:
+     case NEON_LOADSTRUCTLANE:
+-      return arm_expand_neon_args (target, icode, 1, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ 	NEON_ARG_STOP);
+ 
+     case NEON_STORE1:
+     case NEON_STORESTRUCT:
+-      return arm_expand_neon_args (target, icode, 0, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
++      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_STORE1LANE:
+     case NEON_STORESTRUCTLANE:
+-      return arm_expand_neon_args (target, icode, 0, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
++      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ 	NEON_ARG_STOP);
+     }
+ 
+@@ -22349,6 +22483,20 @@
+   return false;
+ }
+ 
++/* Implements target hook array_mode_supported_p.  */
++
++static bool
++arm_array_mode_supported_p (enum machine_mode mode,
++			    unsigned HOST_WIDE_INT nelems)
++{
++  if (TARGET_NEON
++      && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
++      && (nelems >= 2 && nelems <= 4))
++    return true;
++
++  return false;
++}
++
+ /* Implement TARGET_SHIFT_TRUNCATION_MASK.  SImode shifts use normal
+    ARM insns and therefore guarantee that the shift count is modulo 256.
+    DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-02-08 12:07:29 +0000
++++ new/gcc/config/arm/arm.h	2011-04-20 10:07:36 +0000
+@@ -1996,27 +1996,6 @@
+ #define TARGET_DEFAULT_WORD_RELOCATIONS 0
+ #endif
+ 
+-/* Nonzero if the constant value X is a legitimate general operand.
+-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+-
+-   On the ARM, allow any integer (invalid ones are removed later by insn
+-   patterns), nice doubles and symbol_refs which refer to the function's
+-   constant pool XXX.
+-
+-   When generating pic allow anything.  */
+-#define ARM_LEGITIMATE_CONSTANT_P(X)	(flag_pic || ! label_mentioned_p (X))
+-
+-#define THUMB_LEGITIMATE_CONSTANT_P(X)	\
+- (   GET_CODE (X) == CONST_INT		\
+-  || GET_CODE (X) == CONST_DOUBLE	\
+-  || CONSTANT_ADDRESS_P (X)		\
+-  || flag_pic)
+-
+-#define LEGITIMATE_CONSTANT_P(X)			\
+-  (!arm_cannot_force_const_mem (X)			\
+-   && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X)	\
+-		    : THUMB_LEGITIMATE_CONSTANT_P (X)))
+-
+ #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
+ #define SUBTARGET_NAME_ENCODING_LENGTHS
+ #endif
+
+=== modified file 'gcc/config/arm/neon-testgen.ml'
+--- old/gcc/config/arm/neon-testgen.ml	2010-08-20 13:27:11 +0000
++++ new/gcc/config/arm/neon-testgen.ml	2011-04-20 10:00:39 +0000
+@@ -177,7 +177,7 @@
+       let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
+         "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
+     | (PtrTo elt | CstPtrTo elt) ->
+-      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]"
++      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
+     | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+     | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+     | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2010-11-04 11:47:50 +0000
++++ new/gcc/config/arm/neon.md	2011-04-20 10:00:39 +0000
+@@ -259,20 +259,18 @@
+ 
+ ;; Mode of pair of elements for each vector mode, to define transfer
+ ;; size for structure lane/dup loads and stores.
+-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
+-			      (V4HI "SI") (V8HI "SI")
++(define_mode_attr V_two_elem [(V8QI "HI")   (V16QI "HI")
++                              (V4HI "SI")   (V8HI "SI")
+                               (V2SI "V2SI") (V4SI "V2SI")
+                               (V2SF "V2SF") (V4SF "V2SF")
+                               (DI "V2DI")   (V2DI "V2DI")])
+ 
+ ;; Similar, for three elements.
+-;; ??? Should we define extra modes so that sizes of all three-element
+-;; accesses can be accurately represented?
+-(define_mode_attr V_three_elem [(V8QI "SI")   (V16QI "SI")
+-			        (V4HI "V4HI") (V8HI "V4HI")
+-                                (V2SI "V4SI") (V4SI "V4SI")
+-                                (V2SF "V4SF") (V4SF "V4SF")
+-                                (DI "EI")     (V2DI "EI")])
++(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
++                                (V4HI "BLK") (V8HI "BLK")
++                                (V2SI "BLK") (V4SI "BLK")
++                                (V2SF "BLK") (V4SF "BLK")
++                                (DI "EI")    (V2DI "EI")])
+ 
+ ;; Similar, for four elements.
+ (define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
+@@ -4567,16 +4565,16 @@
+ 
+ (define_insn "neon_vld1<mode>"
+   [(set (match_operand:VDQX 0 "s_register_operand" "=w")
+-        (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
++        (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
+                     UNSPEC_VLD1))]
+   "TARGET_NEON"
+-  "vld1.<V_sz_elem>\t%h0, [%1]"
++  "vld1.<V_sz_elem>\t%h0, %A1"
+   [(set_attr "neon_type" "neon_vld1_1_2_regs")]
+ )
+ 
+ (define_insn "neon_vld1_lane<mode>"
+   [(set (match_operand:VDX 0 "s_register_operand" "=w")
+-        (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
+                      (match_operand:VDX 2 "s_register_operand" "0")
+                      (match_operand:SI 3 "immediate_operand" "i")]
+                     UNSPEC_VLD1_LANE))]
+@@ -4587,9 +4585,9 @@
+   if (lane < 0 || lane >= max)
+     error ("lane out of range");
+   if (max == 1)
+-    return "vld1.<V_sz_elem>\t%P0, [%1]";
++    return "vld1.<V_sz_elem>\t%P0, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
+@@ -4599,7 +4597,7 @@
+ 
+ (define_insn "neon_vld1_lane<mode>"
+   [(set (match_operand:VQX 0 "s_register_operand" "=w")
+-        (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
+                      (match_operand:VQX 2 "s_register_operand" "0")
+                      (match_operand:SI 3 "immediate_operand" "i")]
+                     UNSPEC_VLD1_LANE))]
+@@ -4618,9 +4616,9 @@
+     }
+   operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
+   if (max == 2)
+-    return "vld1.<V_sz_elem>\t%P0, [%1]";
++    return "vld1.<V_sz_elem>\t%P0, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
+@@ -4630,14 +4628,14 @@
+ 
+ (define_insn "neon_vld1_dup<mode>"
+   [(set (match_operand:VDX 0 "s_register_operand" "=w")
+-        (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
++        (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
+                     UNSPEC_VLD1_DUP))]
+   "TARGET_NEON"
+ {
+   if (GET_MODE_NUNITS (<MODE>mode) > 1)
+-    return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4647,14 +4645,14 @@
+ 
+ (define_insn "neon_vld1_dup<mode>"
+   [(set (match_operand:VQX 0 "s_register_operand" "=w")
+-        (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
++        (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
+                     UNSPEC_VLD1_DUP))]
+   "TARGET_NEON"
+ {
+   if (GET_MODE_NUNITS (<MODE>mode) > 2)
+-    return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4663,15 +4661,15 @@
+ )
+ 
+ (define_insn "neon_vst1<mode>"
+-  [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
+ 	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
+ 		     UNSPEC_VST1))]
+   "TARGET_NEON"
+-  "vst1.<V_sz_elem>\t%h1, [%0]"
++  "vst1.<V_sz_elem>\t%h1, %A0"
+   [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
+ 
+ (define_insn "neon_vst1_lane<mode>"
+-  [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
+ 	(vec_select:<V_elem>
+ 	  (match_operand:VDX 1 "s_register_operand" "w")
+ 	  (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
+@@ -4682,9 +4680,9 @@
+   if (lane < 0 || lane >= max)
+     error ("lane out of range");
+   if (max == 1)
+-    return "vst1.<V_sz_elem>\t{%P1}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1}, %A0";
+   else
+-    return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
+@@ -4692,7 +4690,7 @@
+                     (const_string "neon_vst1_vst2_lane")))])
+ 
+ (define_insn "neon_vst1_lane<mode>"
+-  [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
+         (vec_select:<V_elem>
+            (match_operand:VQX 1 "s_register_operand" "w")
+            (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
+@@ -4711,24 +4709,24 @@
+     }
+   operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
+   if (max == 2)
+-    return "vst1.<V_sz_elem>\t{%P1}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1}, %A0";
+   else
+-    return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
+ }
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+ 
+ (define_insn "neon_vld2<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+-        (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD2))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vld1.64\t%h0, [%1]";
++    return "vld1.64\t%h0, %A1";
+   else
+-    return "vld2.<V_sz_elem>\t%h0, [%1]";
++    return "vld2.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4738,16 +4736,16 @@
+ 
+ (define_insn "neon_vld2<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD2))]
+   "TARGET_NEON"
+-  "vld2.<V_sz_elem>\t%h0, [%1]"
++  "vld2.<V_sz_elem>\t%h0, %A1"
+   [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
+ 
+ (define_insn "neon_vld2_lane<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+-        (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:TI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4764,7 +4762,7 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 2);
+   ops[2] = operands[1];
+   ops[3] = operands[3];
+-  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
++  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+@@ -4772,7 +4770,7 @@
+ 
+ (define_insn "neon_vld2_lane<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:OI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4794,7 +4792,7 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 4);
+   ops[2] = operands[1];
+   ops[3] = GEN_INT (lane);
+-  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
++  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+@@ -4802,15 +4800,15 @@
+ 
+ (define_insn "neon_vld2_dup<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+-        (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD2_DUP))]
+   "TARGET_NEON"
+ {
+   if (GET_MODE_NUNITS (<MODE>mode) > 1)
+-    return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
++    return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4819,16 +4817,16 @@
+ )
+ 
+ (define_insn "neon_vst2<mode>"
+-  [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
+         (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VST2))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vst1.64\t%h1, [%0]";
++    return "vst1.64\t%h1, %A0";
+   else
+-    return "vst2.<V_sz_elem>\t%h1, [%0]";
++    return "vst2.<V_sz_elem>\t%h1, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4837,17 +4835,17 @@
+ )
+ 
+ (define_insn "neon_vst2<mode>"
+-  [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ 	(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+ 		    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ 		   UNSPEC_VST2))]
+   "TARGET_NEON"
+-  "vst2.<V_sz_elem>\t%h1, [%0]"
++  "vst2.<V_sz_elem>\t%h1, %A0"
+   [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
+ )
+ 
+ (define_insn "neon_vst2_lane<mode>"
+-  [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
+ 	(unspec:<V_two_elem>
+ 	  [(match_operand:TI 1 "s_register_operand" "w")
+ 	   (match_operand:SI 2 "immediate_operand" "i")
+@@ -4865,14 +4863,14 @@
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 2);
+   ops[3] = operands[2];
+-  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
++  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+ 
+ (define_insn "neon_vst2_lane<mode>"
+-  [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_two_elem>
+            [(match_operand:OI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -4895,7 +4893,7 @@
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = GEN_INT (lane);
+-  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
++  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+@@ -4903,15 +4901,15 @@
+ 
+ (define_insn "neon_vld3<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+-        (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD3))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vld1.64\t%h0, [%1]";
++    return "vld1.64\t%h0, %A1";
+   else
+-    return "vld3.<V_sz_elem>\t%h0, [%1]";
++    return "vld3.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4920,27 +4918,25 @@
+ )
+ 
+ (define_expand "neon_vld3<mode>"
+-  [(match_operand:CI 0 "s_register_operand" "=w")
+-   (match_operand:SI 1 "s_register_operand" "+r")
++  [(match_operand:CI 0 "s_register_operand")
++   (match_operand:CI 1 "neon_struct_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
+-  emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[1], EImode, 0);
++  emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
++  mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
++  emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vld3qa<mode>"
+   [(set (match_operand:CI 0 "s_register_operand" "=w")
+-        (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:CI 1 "s_register_operand" "0")
++        (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD3A))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 24)))]
++                   UNSPEC_VLD3A))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -4948,8 +4944,8 @@
+   ops[0] = gen_rtx_REG (DImode, regno);
+   ops[1] = gen_rtx_REG (DImode, regno + 4);
+   ops[2] = gen_rtx_REG (DImode, regno + 8);
+-  ops[3] = operands[2];
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
++  ops[3] = operands[1];
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4957,13 +4953,10 @@
+ 
+ (define_insn "neon_vld3qb<mode>"
+   [(set (match_operand:CI 0 "s_register_operand" "=w")
+-        (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:CI 1 "s_register_operand" "0")
++        (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
++                    (match_operand:CI 2 "s_register_operand" "0")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD3B))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 24)))]
++                   UNSPEC_VLD3B))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -4971,8 +4964,8 @@
+   ops[0] = gen_rtx_REG (DImode, regno + 2);
+   ops[1] = gen_rtx_REG (DImode, regno + 6);
+   ops[2] = gen_rtx_REG (DImode, regno + 10);
+-  ops[3] = operands[2];
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
++  ops[3] = operands[1];
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4980,7 +4973,7 @@
+ 
+ (define_insn "neon_vld3_lane<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+-        (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:EI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4998,7 +4991,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = operands[1];
+   ops[4] = operands[3];
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+                    ops);
+   return "";
+ }
+@@ -5007,7 +5000,7 @@
+ 
+ (define_insn "neon_vld3_lane<mode>"
+   [(set (match_operand:CI 0 "s_register_operand" "=w")
+-        (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:CI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -5030,7 +5023,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 8);
+   ops[3] = operands[1];
+   ops[4] = GEN_INT (lane);
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+                    ops);
+   return "";
+ }
+@@ -5039,7 +5032,7 @@
+ 
+ (define_insn "neon_vld3_dup<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+-        (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD3_DUP))]
+   "TARGET_NEON"
+@@ -5052,11 +5045,11 @@
+       ops[1] = gen_rtx_REG (DImode, regno + 2);
+       ops[2] = gen_rtx_REG (DImode, regno + 4);
+       ops[3] = operands[1];
+-      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
++      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
+       return "";
+     }
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -5064,16 +5057,16 @@
+                     (const_string "neon_vld1_1_2_regs")))])
+ 
+ (define_insn "neon_vst3<mode>"
+-  [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+         (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VST3))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vst1.64\t%h1, [%0]";
++    return "vst1.64\t%h1, %A0";
+   else
+-    return "vst3.<V_sz_elem>\t%h1, [%0]";
++    return "vst3.<V_sz_elem>\t%h1, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -5081,62 +5074,60 @@
+                     (const_string "neon_vst2_4_regs_vst3_vst4")))])
+ 
+ (define_expand "neon_vst3<mode>"
+-  [(match_operand:SI 0 "s_register_operand" "+r")
+-   (match_operand:CI 1 "s_register_operand" "w")
++  [(match_operand:CI 0 "neon_struct_operand")
++   (match_operand:CI 1 "s_register_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
+-  emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[0], EImode, 0);
++  emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
++  mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
++  emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vst3qa<mode>"
+-  [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
++  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
++        (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST3A))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 24)))]
++                   UNSPEC_VST3A))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst3qb<mode>"
+-  [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
++  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
++        (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST3B))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 24)))]
++                   UNSPEC_VST3B))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno + 2);
+   ops[2] = gen_rtx_REG (DImode, regno + 6);
+   ops[3] = gen_rtx_REG (DImode, regno + 10);
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst3_lane<mode>"
+-  [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_three_elem>
+            [(match_operand:EI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -5155,7 +5146,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 2);
+   ops[3] = gen_rtx_REG (DImode, regno + 4);
+   ops[4] = operands[2];
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+                    ops);
+   return "";
+ }
+@@ -5163,7 +5154,7 @@
+ )
+ 
+ (define_insn "neon_vst3_lane<mode>"
+-  [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_three_elem>
+            [(match_operand:CI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -5187,7 +5178,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+   ops[4] = GEN_INT (lane);
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+                    ops);
+   return "";
+ }
+@@ -5195,15 +5186,15 @@
+ 
+ (define_insn "neon_vld4<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD4))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vld1.64\t%h0, [%1]";
++    return "vld1.64\t%h0, %A1";
+   else
+-    return "vld4.<V_sz_elem>\t%h0, [%1]";
++    return "vld4.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -5212,27 +5203,25 @@
+ )
+ 
+ (define_expand "neon_vld4<mode>"
+-  [(match_operand:XI 0 "s_register_operand" "=w")
+-   (match_operand:SI 1 "s_register_operand" "+r")
++  [(match_operand:XI 0 "s_register_operand")
++   (match_operand:XI 1 "neon_struct_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
+-  emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[1], OImode, 0);
++  emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
++  mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
++  emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vld4qa<mode>"
+   [(set (match_operand:XI 0 "s_register_operand" "=w")
+-        (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:XI 1 "s_register_operand" "0")
++        (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD4A))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 32)))]
++                   UNSPEC_VLD4A))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -5241,8 +5230,8 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 4);
+   ops[2] = gen_rtx_REG (DImode, regno + 8);
+   ops[3] = gen_rtx_REG (DImode, regno + 12);
+-  ops[4] = operands[2];
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
++  ops[4] = operands[1];
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -5250,13 +5239,10 @@
+ 
+ (define_insn "neon_vld4qb<mode>"
+   [(set (match_operand:XI 0 "s_register_operand" "=w")
+-        (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:XI 1 "s_register_operand" "0")
++        (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
++                    (match_operand:XI 2 "s_register_operand" "0")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD4B))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 32)))]
++                   UNSPEC_VLD4B))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -5265,8 +5251,8 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 6);
+   ops[2] = gen_rtx_REG (DImode, regno + 10);
+   ops[3] = gen_rtx_REG (DImode, regno + 14);
+-  ops[4] = operands[2];
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
++  ops[4] = operands[1];
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -5274,7 +5260,7 @@
+ 
+ (define_insn "neon_vld4_lane<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:OI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -5293,7 +5279,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 6);
+   ops[4] = operands[1];
+   ops[5] = operands[3];
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
+                    ops);
+   return "";
+ }
+@@ -5302,7 +5288,7 @@
+ 
+ (define_insn "neon_vld4_lane<mode>"
+   [(set (match_operand:XI 0 "s_register_operand" "=w")
+-        (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:XI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -5326,7 +5312,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 12);
+   ops[4] = operands[1];
+   ops[5] = GEN_INT (lane);
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
+                    ops);
+   return "";
+ }
+@@ -5335,7 +5321,7 @@
+ 
+ (define_insn "neon_vld4_dup<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD4_DUP))]
+   "TARGET_NEON"
+@@ -5349,12 +5335,12 @@
+       ops[2] = gen_rtx_REG (DImode, regno + 4);
+       ops[3] = gen_rtx_REG (DImode, regno + 6);
+       ops[4] = operands[1];
+-      output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
++      output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
+                        ops);
+       return "";
+     }
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -5363,16 +5349,16 @@
+ )
+ 
+ (define_insn "neon_vst4<mode>"
+-  [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+         (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VST4))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vst1.64\t%h1, [%0]";
++    return "vst1.64\t%h1, %A0";
+   else
+-    return "vst4.<V_sz_elem>\t%h1, [%0]";
++    return "vst4.<V_sz_elem>\t%h1, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -5381,64 +5367,62 @@
+ )
+ 
+ (define_expand "neon_vst4<mode>"
+-  [(match_operand:SI 0 "s_register_operand" "+r")
+-   (match_operand:XI 1 "s_register_operand" "w")
++  [(match_operand:XI 0 "neon_struct_operand")
++   (match_operand:XI 1 "s_register_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
+-  emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[0], OImode, 0);
++  emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
++  mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
++  emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vst4qa<mode>"
+-  [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
++        (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST4A))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 32)))]
++                   UNSPEC_VST4A))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[5];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+   ops[4] = gen_rtx_REG (DImode, regno + 12);
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst4qb<mode>"
+-  [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
++        (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST4B))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 32)))]
++                   UNSPEC_VST4B))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[5];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno + 2);
+   ops[2] = gen_rtx_REG (DImode, regno + 6);
+   ops[3] = gen_rtx_REG (DImode, regno + 10);
+   ops[4] = gen_rtx_REG (DImode, regno + 14);
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst4_lane<mode>"
+-  [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_four_elem>
+            [(match_operand:OI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -5458,7 +5442,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 4);
+   ops[4] = gen_rtx_REG (DImode, regno + 6);
+   ops[5] = operands[2];
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
+                    ops);
+   return "";
+ }
+@@ -5466,7 +5450,7 @@
+ )
+ 
+ (define_insn "neon_vst4_lane<mode>"
+-  [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_four_elem>
+            [(match_operand:XI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -5491,7 +5475,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+   ops[4] = gen_rtx_REG (DImode, regno + 12);
+   ops[5] = GEN_INT (lane);
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
+                    ops);
+   return "";
+ }
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-04-06 12:29:08 +0000
++++ new/gcc/config/arm/predicates.md	2011-04-20 10:00:39 +0000
+@@ -681,3 +681,7 @@
+    } 
+   return true; 
+ })
++
++(define_special_predicate "neon_struct_operand"
++  (and (match_code "mem")
++       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
+
+=== modified file 'gcc/doc/tm.texi'
+--- old/gcc/doc/tm.texi	2011-02-08 10:51:58 +0000
++++ new/gcc/doc/tm.texi	2011-04-20 10:07:36 +0000
+@@ -2642,8 +2642,8 @@
+ register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant.  If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+-of using @code{PREFERRED_RELOAD_CLASS}.
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+ 
+ If an insn has pseudos in it after register allocation, reload will go
+ through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
+@@ -4367,6 +4367,34 @@
+ must have move patterns for this mode.
+ @end deftypefn
+ 
++@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems})
++Return true if GCC should try to use a scalar mode to store an array
++of @var{nelems} elements, given that each element has mode @var{mode}.
++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit
++and allows GCC to use any defined integer mode.
++
++One use of this hook is to support vector load and store operations
++that operate on several homogeneous vectors.  For example, ARM Neon
++has operations like:
++
++@smallexample
++int8x8x3_t vld3_s8 (const int8_t *)
++@end smallexample
++
++where the return type is defined as:
++
++@smallexample
++typedef struct int8x8x3_t
++@{
++  int8x8_t val[3];
++@} int8x8x3_t;
++@end smallexample
++
++If this hook allows @code{val} to have a scalar mode, then
++@code{int8x8x3_t} can have the same mode.  GCC can then store
++@code{int8x8x3_t}s in registers rather than forcing them onto the stack.
++@end deftypefn
++
+ @node Scalar Return
+ @subsection How Scalar Function Values Are Returned
+ @cindex return values in registers
+@@ -5600,13 +5628,13 @@
+ You may assume that @var{addr} is a valid address for the machine.
+ @end defmac
+ 
+-@defmac LEGITIMATE_CONSTANT_P (@var{x})
+-A C expression that is nonzero if @var{x} is a legitimate constant for
+-an immediate operand on the target machine.  You can assume that
+-@var{x} satisfies @code{CONSTANT_P}, so you need not check this.  In fact,
+-@samp{1} is a suitable definition for this macro on machines where
+-anything @code{CONSTANT_P} is valid.
+-@end defmac
++@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x})
++This hook returns true if @var{x} is a legitimate constant for a
++@var{mode}-mode immediate operand on the target machine.  You can assume that
++@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
++
++The default definition returns true.
++@end deftypefn
+ 
+ @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x})
+ This hook is used to undo the possibly obfuscating effects of the
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2011-03-23 12:22:13 +0000
++++ new/gcc/expr.c	2011-04-20 10:07:36 +0000
+@@ -1537,7 +1537,7 @@
+   if (nregs == 0)
+     return;
+ 
+-  if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
++  if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
+     x = validize_mem (force_const_mem (mode, x));
+ 
+   /* See if the machine can do this with a load multiple insn.  */
+@@ -2366,7 +2366,7 @@
+ 		    offset -= size;
+ 
+ 		  cst = (*constfun) (constfundata, offset, mode);
+-		  if (!LEGITIMATE_CONSTANT_P (cst))
++		  if (!targetm.legitimate_constant_p (mode, cst))
+ 		    return 0;
+ 
+ 		  if (!reverse)
+@@ -3440,7 +3440,7 @@
+ 
+       y_cst = y;
+ 
+-      if (!LEGITIMATE_CONSTANT_P (y))
++      if (!targetm.legitimate_constant_p (mode, y))
+ 	{
+ 	  y = force_const_mem (mode, y);
+ 
+@@ -3496,7 +3496,7 @@
+ 
+   REAL_VALUE_FROM_CONST_DOUBLE (r, y);
+ 
+-  if (LEGITIMATE_CONSTANT_P (y))
++  if (targetm.legitimate_constant_p (dstmode, y))
+     oldcost = rtx_cost (y, SET, speed);
+   else
+     oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed);
+@@ -3519,7 +3519,7 @@
+ 
+       trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode);
+ 
+-      if (LEGITIMATE_CONSTANT_P (trunc_y))
++      if (targetm.legitimate_constant_p (srcmode, trunc_y))
+ 	{
+ 	  /* Skip if the target needs extra instructions to perform
+ 	     the extension.  */
+@@ -3932,7 +3932,7 @@
+ 	 by setting SKIP to 0.  */
+       skip = (reg_parm_stack_space == 0) ? 0 : not_stack;
+ 
+-      if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
++      if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
+ 	x = validize_mem (force_const_mem (mode, x));
+ 
+       /* If X is a hard register in a non-integer mode, copy it into a pseudo;
+@@ -8951,7 +8951,7 @@
+ 	   constant and we don't need a memory reference.  */
+ 	if (CONSTANT_P (op0)
+ 	    && mode2 != BLKmode
+-	    && LEGITIMATE_CONSTANT_P (op0)
++	    && targetm.legitimate_constant_p (mode2, op0)
+ 	    && !must_force_mem)
+ 	  op0 = force_reg (mode2, op0);
+ 
+
+=== modified file 'gcc/hooks.c'
+--- old/gcc/hooks.c	2009-11-26 01:52:19 +0000
++++ new/gcc/hooks.c	2011-04-20 10:06:58 +0000
+@@ -86,6 +86,15 @@
+   return true;
+ }
+ 
++/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT)
++   and returns false.  */
++bool
++hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED,
++			   unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED)
++{
++  return false;
++}
++
+ /* Generic hook that takes (FILE *, const char *) and does nothing.  */
+ void
+ hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
+
+=== modified file 'gcc/hooks.h'
+--- old/gcc/hooks.h	2009-11-26 01:52:19 +0000
++++ new/gcc/hooks.h	2011-04-20 10:06:58 +0000
+@@ -32,6 +32,8 @@
+ extern bool hook_bool_mode_false (enum machine_mode);
+ extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
+ extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx);
++extern bool hook_bool_mode_uhwi_false (enum machine_mode,
++				       unsigned HOST_WIDE_INT);
+ extern bool hook_bool_tree_false (tree);
+ extern bool hook_bool_const_tree_false (const_tree);
+ extern bool hook_bool_tree_true (tree);
+
+=== modified file 'gcc/recog.c'
+--- old/gcc/recog.c	2011-02-08 12:07:29 +0000
++++ new/gcc/recog.c	2011-04-20 10:07:36 +0000
+@@ -932,7 +932,9 @@
+     return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
+ 	     || mode == VOIDmode)
+ 	    && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+-	    && LEGITIMATE_CONSTANT_P (op));
++	    && targetm.legitimate_constant_p (mode == VOIDmode
++					      ? GET_MODE (op)
++					      : mode, op));
+ 
+   /* Except for certain constants with VOIDmode, already checked for,
+      OP's mode must match MODE if MODE specifies a mode.  */
+@@ -1109,7 +1111,9 @@
+ 	  && (GET_MODE (op) == mode || mode == VOIDmode
+ 	      || GET_MODE (op) == VOIDmode)
+ 	  && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+-	  && LEGITIMATE_CONSTANT_P (op));
++	  && targetm.legitimate_constant_p (mode == VOIDmode
++					    ? GET_MODE (op)
++					    : mode, op));
+ }
+ 
+ /* Returns 1 if OP is an operand that is a CONST_INT.  */
+@@ -1175,7 +1179,9 @@
+       return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
+ 	       || mode == VOIDmode)
+ 	      && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+-	      && LEGITIMATE_CONSTANT_P (op));
++	      && targetm.legitimate_constant_p (mode == VOIDmode
++						? GET_MODE (op)
++						: mode, op));
+     }
+ 
+   if (GET_MODE (op) != mode && mode != VOIDmode)
+
+=== modified file 'gcc/reload.c'
+--- old/gcc/reload.c	2011-02-08 12:07:29 +0000
++++ new/gcc/reload.c	2011-04-20 10:07:36 +0000
+@@ -4739,7 +4739,8 @@
+ 	    simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
+ 				 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
+ 	  gcc_assert (tem);
+-	  if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
++	  if (CONSTANT_P (tem)
++	      && !targetm.legitimate_constant_p (GET_MODE (x), tem))
+ 	    {
+ 	      tem = force_const_mem (GET_MODE (x), tem);
+ 	      i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
+@@ -6061,7 +6062,7 @@
+ 			   enum reload_type type, int ind_levels)
+ {
+   if (CONSTANT_P (x)
+-      && (! LEGITIMATE_CONSTANT_P (x)
++      && (!targetm.legitimate_constant_p (mode, x)
+ 	  || PREFERRED_RELOAD_CLASS (x, rclass) == NO_REGS))
+     {
+       x = force_const_mem (mode, x);
+@@ -6071,7 +6072,7 @@
+ 
+   else if (GET_CODE (x) == PLUS
+ 	   && CONSTANT_P (XEXP (x, 1))
+-	   && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
++	   && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
+ 	       || PREFERRED_RELOAD_CLASS (XEXP (x, 1), rclass) == NO_REGS))
+     {
+       rtx tem;
+
+=== modified file 'gcc/reload1.c'
+--- old/gcc/reload1.c	2011-03-02 13:30:06 +0000
++++ new/gcc/reload1.c	2011-04-20 10:07:36 +0000
+@@ -4164,6 +4164,9 @@
+ 		}
+ 	      else if (function_invariant_p (x))
+ 		{
++		  enum machine_mode mode;
++
++		  mode = GET_MODE (SET_DEST (set));
+ 		  if (GET_CODE (x) == PLUS)
+ 		    {
+ 		      /* This is PLUS of frame pointer and a constant,
+@@ -4176,12 +4179,11 @@
+ 		      reg_equiv_invariant[i] = x;
+ 		      num_eliminable_invariants++;
+ 		    }
+-		  else if (LEGITIMATE_CONSTANT_P (x))
++		  else if (targetm.legitimate_constant_p (mode, x))
+ 		    reg_equiv_constant[i] = x;
+ 		  else
+ 		    {
+-		      reg_equiv_memory_loc[i]
+-			= force_const_mem (GET_MODE (SET_DEST (set)), x);
++		      reg_equiv_memory_loc[i] = force_const_mem (mode, x);
+ 		      if (! reg_equiv_memory_loc[i])
+ 			reg_equiv_init[i] = NULL_RTX;
+ 		    }
+
+=== modified file 'gcc/stor-layout.c'
+--- old/gcc/stor-layout.c	2011-04-06 12:29:08 +0000
++++ new/gcc/stor-layout.c	2011-04-20 10:06:58 +0000
+@@ -507,6 +507,34 @@
+   return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
+ }
+ 
++/* Return the natural mode of an array, given that it is SIZE bytes in
++   total and has elements of type ELEM_TYPE.  */
++
++static enum machine_mode
++mode_for_array (tree elem_type, tree size)
++{
++  tree elem_size;
++  unsigned HOST_WIDE_INT int_size, int_elem_size;
++  bool limit_p;
++
++  /* One-element arrays get the component type's mode.  */
++  elem_size = TYPE_SIZE (elem_type);
++  if (simple_cst_equal (size, elem_size))
++    return TYPE_MODE (elem_type);
++
++  limit_p = true;
++  if (host_integerp (size, 1) && host_integerp (elem_size, 1))
++    {
++      int_size = tree_low_cst (size, 1);
++      int_elem_size = tree_low_cst (elem_size, 1);
++      if (int_elem_size > 0
++	  && int_size % int_elem_size == 0
++	  && targetm.array_mode_supported_p (TYPE_MODE (elem_type),
++					     int_size / int_elem_size))
++	limit_p = false;
++    }
++  return mode_for_size_tree (size, MODE_INT, limit_p);
++}
+ 
+ /* Subroutine of layout_decl: Force alignment required for the data type.
+    But if the decl itself wants greater alignment, don't override that.  */
+@@ -2044,14 +2072,8 @@
+ 	    && (TYPE_MODE (TREE_TYPE (type)) != BLKmode
+ 		|| TYPE_NO_FORCE_BLK (TREE_TYPE (type))))
+ 	  {
+-	    /* One-element arrays get the component type's mode.  */
+-	    if (simple_cst_equal (TYPE_SIZE (type),
+-				  TYPE_SIZE (TREE_TYPE (type))))
+-	      SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type)));
+-	    else
+-	      SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type),
+-						       MODE_INT, 1));
+-
++	    SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type),
++						 TYPE_SIZE (type)));
+ 	    if (TYPE_MODE (type) != BLKmode
+ 		&& STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
+ 		&& TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
+
+=== modified file 'gcc/target-def.h'
+--- old/gcc/target-def.h	2010-08-10 13:31:21 +0000
++++ new/gcc/target-def.h	2011-04-20 10:07:36 +0000
+@@ -553,12 +553,17 @@
+ #define TARGET_VECTOR_MODE_SUPPORTED_P hook_bool_mode_false
+ #endif
+ 
++#ifndef TARGET_ARRAY_MODE_SUPPORTED_P
++#define TARGET_ARRAY_MODE_SUPPORTED_P hook_bool_mode_uhwi_false
++#endif
++
+ /* In hooks.c.  */
+ #define TARGET_CANNOT_MODIFY_JUMPS_P hook_bool_void_false
+ #define TARGET_BRANCH_TARGET_REGISTER_CLASS \
+   default_branch_target_register_class
+ #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED hook_bool_bool_false
+ #define TARGET_HAVE_CONDITIONAL_EXECUTION default_have_conditional_execution
++#define TARGET_LEGITIMATE_CONSTANT_P default_legitimate_constant_p
+ #define TARGET_CANNOT_FORCE_CONST_MEM hook_bool_rtx_false
+ #define TARGET_CANNOT_COPY_INSN_P NULL
+ #define TARGET_COMMUTATIVE_P hook_bool_const_rtx_commutative_p
+@@ -961,6 +966,7 @@
+   TARGET_BRANCH_TARGET_REGISTER_CLASS,		\
+   TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED,	\
+   TARGET_HAVE_CONDITIONAL_EXECUTION,		\
++  TARGET_LEGITIMATE_CONSTANT_P,			\
+   TARGET_CANNOT_FORCE_CONST_MEM,		\
+   TARGET_CANNOT_COPY_INSN_P,			\
+   TARGET_COMMUTATIVE_P,				\
+@@ -985,6 +991,7 @@
+   TARGET_ADDR_SPACE_HOOKS,			\
+   TARGET_SCALAR_MODE_SUPPORTED_P,		\
+   TARGET_VECTOR_MODE_SUPPORTED_P,               \
++  TARGET_ARRAY_MODE_SUPPORTED_P,		\
+   TARGET_RTX_COSTS,				\
+   TARGET_ADDRESS_COST,				\
+   TARGET_ALLOCATE_INITIAL_VALUE,		\
+
+=== modified file 'gcc/target.h'
+--- old/gcc/target.h	2010-08-10 13:31:21 +0000
++++ new/gcc/target.h	2011-04-20 10:07:36 +0000
+@@ -645,7 +645,10 @@
+   /* Return true if the target supports conditional execution.  */
+   bool (* have_conditional_execution) (void);
+ 
+-  /* True if the constant X cannot be placed in the constant pool.  */
++  /* See tm.texi.  */
++  bool (* legitimate_constant_p) (enum machine_mode, rtx);
++
++    /* True if the constant X cannot be placed in the constant pool.  */
+   bool (* cannot_force_const_mem) (rtx);
+ 
+   /* True if the insn X cannot be duplicated.  */
+@@ -764,6 +767,9 @@
+      for further details.  */
+   bool (* vector_mode_supported_p) (enum machine_mode mode);
+ 
++  /* See tm.texi.  */
++  bool (* array_mode_supported_p) (enum machine_mode, unsigned HOST_WIDE_INT);
++
+   /* Compute a (partial) cost for rtx X.  Return true if the complete
+      cost has been computed, and false if subexpressions should be
+      scanned.  In either case, *TOTAL contains the cost result.  */
+
+=== modified file 'gcc/targhooks.c'
+--- old/gcc/targhooks.c	2010-03-27 10:27:39 +0000
++++ new/gcc/targhooks.c	2011-04-20 10:07:36 +0000
+@@ -1008,4 +1008,15 @@
+ #endif
+ }
+ 
++bool
++default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
++			       rtx x ATTRIBUTE_UNUSED)
++{
++#ifdef LEGITIMATE_CONSTANT_P
++  return LEGITIMATE_CONSTANT_P (x);
++#else
++  return true;
++#endif
++}
++
+ #include "gt-targhooks.h"
+
+=== modified file 'gcc/targhooks.h'
+--- old/gcc/targhooks.h	2010-03-27 10:27:39 +0000
++++ new/gcc/targhooks.h	2011-04-20 10:07:36 +0000
+@@ -132,3 +132,4 @@
+ extern rtx default_addr_space_convert (rtx, tree, tree);
+ extern unsigned int default_case_values_threshold (void);
+ extern bool default_have_conditional_execution (void);
++extern bool default_legitimate_constant_p (enum machine_mode, rtx);
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vld3-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vld3-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vld3-1.c	2011-04-20 10:00:39 +0000
+@@ -0,0 +1,27 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++uint32_t buffer[12];
++
++void __attribute__((noinline))
++foo (uint32_t *a)
++{
++  uint32x4x3_t x;
++
++  x = vld3q_u32 (a);
++  x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
++  vst3q_u32 (a, x);
++}
++
++int
++main (void)
++{
++  buffer[0] = 1;
++  buffer[1] = 2;
++  foo (buffer);
++  return buffer[0] != 3;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vst3-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vst3-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vst3-1.c	2011-04-20 10:00:39 +0000
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++uint32_t buffer[64];
++
++void __attribute__((noinline))
++foo (uint32_t *a)
++{
++  uint32x4x3_t x;
++
++  x = vld3q_u32 (a);
++  a[35] = 1;
++  vst3q_lane_u32 (a + 32, x, 1);
++}
++
++int
++main (void)
++{
++  foo (buffer);
++  return buffer[35] != 1;
++}
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x4_t = vld1q_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x8_t = vld1q_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x16_t = vld1q_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x8_t = vld1q_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x4_t = vld1q_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x2_t = vld1q_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x16_t = vld1q_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x8_t = vld1q_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x4_t = vld1q_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x2_t = vld1q_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x16_t = vld1q_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x4_t = vld1q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x8_t = vld1q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x16_t = vld1q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x8_t = vld1q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x4_t = vld1q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x2_t = vld1q_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x16_t = vld1q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x8_t = vld1q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x4_t = vld1q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x2_t = vld1q_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x16_t = vld1q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2_t = vld1_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4_t = vld1_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8_t = vld1_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4_t = vld1_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2_t = vld1_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1_t = vld1_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8_t = vld1_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4_t = vld1_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2_t = vld1_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1_t = vld1_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8_t = vld1_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2_t = vld1_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4_t = vld1_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8_t = vld1_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4_t = vld1_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2_t = vld1_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1_t = vld1_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8_t = vld1_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4_t = vld1_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2_t = vld1_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1_t = vld1_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8_t = vld1_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_float32x4x2_t = vld2q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_poly16x8x2_t = vld2q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_poly8x16x2_t = vld2q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int16x8x2_t = vld2q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int32x4x2_t = vld2q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int8x16x2_t = vld2q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint16x8x2_t = vld2q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint32x4x2_t = vld2q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint8x16x2_t = vld2q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x2_t = vld2_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x2_t = vld2_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x2_t = vld2_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x2_t = vld2_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x2_t = vld2_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x2_t = vld2_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x2_t = vld2_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x2_t = vld2_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x2_t = vld2_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x2_t = vld2_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x2_t = vld2_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x2_t = vld2_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x2_t = vld2_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x2_t = vld2_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x2_t = vld2_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x2_t = vld2_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x2_t = vld2_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x2_t = vld2_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x2_t = vld2_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x2_t = vld2_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x2_t = vld2_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x2_t = vld2_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_float32x4x3_t = vld3q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_poly16x8x3_t = vld3q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_poly8x16x3_t = vld3q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int16x8x3_t = vld3q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int32x4x3_t = vld3q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int8x16x3_t = vld3q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint16x8x3_t = vld3q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint32x4x3_t = vld3q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint8x16x3_t = vld3q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x3_t = vld3_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x3_t = vld3_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x3_t = vld3_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x3_t = vld3_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x3_t = vld3_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x3_t = vld3_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x3_t = vld3_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x3_t = vld3_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x3_t = vld3_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x3_t = vld3_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x3_t = vld3_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x3_t = vld3_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x3_t = vld3_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x3_t = vld3_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x3_t = vld3_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x3_t = vld3_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x3_t = vld3_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x3_t = vld3_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x3_t = vld3_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x3_t = vld3_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x3_t = vld3_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x3_t = vld3_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_float32x4x4_t = vld4q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_poly16x8x4_t = vld4q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_poly8x16x4_t = vld4q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int16x8x4_t = vld4q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int32x4x4_t = vld4q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_int8x16x4_t = vld4q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint16x8x4_t = vld4q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint32x4x4_t = vld4q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c	2011-04-20 10:00:39 +0000
+@@ -15,6 +15,6 @@
+   out_uint8x16x4_t = vld4q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x4_t = vld4_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x4_t = vld4_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x4_t = vld4_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x4_t = vld4_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x4_t = vld4_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x4_t = vld4_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x4_t = vld4_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x4_t = vld4_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x4_t = vld4_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x4_t = vld4_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x4_t = vld4_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_float32x2x4_t = vld4_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly16x4x4_t = vld4_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_poly8x8x4_t = vld4_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int16x4x4_t = vld4_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int32x2x4_t = vld4_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int64x1x4_t = vld4_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_int8x8x4_t = vld4_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint16x4x4_t = vld4_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint32x2x4_t = vld4_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint64x1x4_t = vld4_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c	2011-04-20 10:00:39 +0000
+@@ -15,5 +15,5 @@
+   out_uint8x8x4_t = vld4_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c	2011-04-20 10:00:39 +0000
+@@ -16,6 +16,6 @@
+   vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c'
+--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c	2010-08-20 13:27:11 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c	2011-04-20 10:00:39 +0000
+@@ -16,5 +16,5 @@
+   vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@.*\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@.*\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr46329.c'
+--- old/gcc/testsuite/gcc.target/arm/pr46329.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr46329.c	2011-05-03 12:49:58 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++int __attribute__ ((vector_size (32))) x;
++void
++foo (void)
++{
++  x <<= x;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99504.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99504.patch
new file mode 100644
index 0000000000..b287c4da31
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99504.patch
@@ -0,0 +1,26 @@
+Remove the following
+
+ 2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+ 
+	gcc/testsuite/
+	From  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/46329
+	* gcc.target/arm/pr46329.c: New test.
+
+=== removed file 'gcc/testsuite/gcc.target/arm/pr46329.c'
+--- old/gcc/testsuite/gcc.target/arm/pr46329.c	2011-05-03 12:49:58 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr46329.c	1970-01-01 00:00:00 +0000
+@@ -1,11 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-int __attribute__ ((vector_size (32))) x;
+-void
+-foo (void)
+-{
+-  x <<= x;
+-}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99506.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99506.patch
new file mode 100644
index 0000000000..9432f4c0a5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99506.patch
@@ -0,0 +1,21 @@
+2011-05-06  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	From Sergey Grechanik  <mouseentity@ispras.ru>, approved for mainline
+
+	* config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS
+	for constant vectors.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-04-20 10:10:50 +0000
++++ new/gcc/config/arm/arm.c	2011-05-04 15:13:02 +0000
+@@ -9353,7 +9353,7 @@
+   /* The neon move patterns handle all legitimate vector and struct
+      addresses.  */
+   if (TARGET_NEON
+-      && MEM_P (x)
++      && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
+       && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+ 	  || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
+ 	  || VALID_NEON_STRUCT_MODE (mode)))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99507.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99507.patch
new file mode 100644
index 0000000000..f3d5eee6e7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99507.patch
@@ -0,0 +1,20 @@
+2011-05-03  Tom de Vries  <tom@codesourcery.com>
+
+	gcc/
+	* stmt.c (set_jump_prob): Make robust against *inv_scale == 0.
+
+=== modified file 'gcc/stmt.c'
+--- old/gcc/stmt.c	2011-02-07 13:23:30 +0000
++++ new/gcc/stmt.c	2011-05-06 19:17:34 +0000
+@@ -2312,7 +2312,9 @@
+ set_jump_prob (rtx jump, int prob, int *inv_scale)
+ {
+   /* j[i] = p[i] * scale / REG_BR_PROB_BASE.  */
+-  int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale;
++  int jump_prob = (*inv_scale > 0
++                   ? prob * REG_BR_PROB_BASE / *inv_scale
++                   : REG_BR_PROB_BASE / 2);
+   /* f[i] = REG_BR_PROB_BASE - j[i].  */
+   int fallthrough_prob = REG_BR_PROB_BASE - jump_prob;
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99510.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99510.patch
new file mode 100644
index 0000000000..b4e4e883ac
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99510.patch
@@ -0,0 +1,24 @@
+2011-05-13  Michael Hope  <michael.hope@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-05-05  Michael Hope  <michael.hope@linaro.org>
+
+	PR pch/45979
+	* config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for
+	__ARM_EABI__ hosts.
+
+=== modified file 'gcc/config/host-linux.c'
+--- old/gcc/config/host-linux.c	2009-02-20 15:20:38 +0000
++++ new/gcc/config/host-linux.c	2011-05-06 20:16:10 +0000
+@@ -86,6 +86,8 @@
+ # define TRY_EMPTY_VM_SPACE	0x60000000
+ #elif defined(__mc68000__)
+ # define TRY_EMPTY_VM_SPACE	0x40000000
++#elif defined(__ARM_EABI__)
++# define TRY_EMPTY_VM_SPACE     0x60000000
+ #else
+ # define TRY_EMPTY_VM_SPACE	0
+ #endif
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99511.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99511.patch
new file mode 100644
index 0000000000..8d096c25d0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99511.patch
@@ -0,0 +1,582 @@
+2011-05-13 Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	* loop-doloop.c (doloop_condition_get): Support new form of
+	doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
+	* config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
+	(doloop_end): New.
+	* config/arm/arm.md (*addsi3_compare0): Remove "*".
+	* params.def (sms-min-sc): New param flag.
+	* doc/invoke.texi (sms-min-sc): Document it.
+	* ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge
+	enters the branch create an anti edge in the opposite direction
+	to prevent the creation of reg-moves.
+	(get_node_of_insn_uid, check_closing_branch_deps): Delete
+	functions.
+	(create_ddg): Restore previous definition and implementation.
+	* ddg.h (create_ddg): Restore previous definition.
+	* modulo-sched.c: Adjust comment to reflect the fact we are
+	scheduling closing branch.
+	(PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine.
+	(stage_count): New field in struct partial_schedule.
+	(calculate_stage_count): New function.
+	(normalize_sched_times): Rename to reset_sched_times and handle
+	incrementing the sched time of the nodes by a constant value
+	passed as parameter.
+	(duplicate_insns_of_cycles): Skip closing branch.
+	(sms_schedule_by_order): Schedule closing branch.
+	(ps_insn_find_column): Handle closing branch.
+	(sms_schedule): Call reset_sched_times and adjust the code to
+	support scheduling of the closing branch. Use sms-min-sc.
+	Support new form of doloop pattern.
+	(ps_insert_empty_row): Update calls to normalize_sched_times
+	and rotate_partial_schedule functions.	
+	(mark_doloop_insns): Remove.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-03-24 07:45:38 +0000
++++ new/gcc/ddg.c	2011-05-11 08:00:14 +0000
+@@ -60,8 +60,6 @@
+ static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type,
+ 				     dep_data_type, int, int);
+ static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr);
+-static ddg_node_ptr get_node_of_insn_uid (ddg_ptr, int);
+-
+ 
+ /* Auxiliary variable for mem_read_insn_p/mem_write_insn_p.  */
+ static bool mem_ref_p;
+@@ -199,6 +197,11 @@
+         }
+     }
+ 
++  /* If a true dep edge enters the branch create an anti edge in the
++     opposite direction to prevent the creation of reg-moves.  */
++  if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
++    create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
++
+    latency = dep_cost (link);
+    e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
+    add_edge_to_ddg (g, e);
+@@ -452,65 +455,12 @@
+   sched_free_deps (head, tail, false);
+ }
+ 
+-/* Given DOLOOP_INSNS which holds the instructions that
+-   belong to the do-loop part; mark closing_branch_deps field in ddg G
+-   as TRUE if the do-loop part's instructions are dependent on the other
+-   loop instructions.  Otherwise mark it as FALSE.  */
+-static void
+-check_closing_branch_deps (ddg_ptr g, sbitmap doloop_insns)
+-{
+-  sbitmap_iterator sbi;
+-  unsigned int u = 0;
+-
+-  EXECUTE_IF_SET_IN_SBITMAP (doloop_insns, 0, u, sbi)
+-  {
+-    ddg_edge_ptr e;
+-    ddg_node_ptr u_node = get_node_of_insn_uid (g, u);
+-
+-    gcc_assert (u_node);
+-
+-    for (e = u_node->in; e != 0; e = e->next_in)
+-      {
+-	ddg_node_ptr v_node = e->src;
+-
+-	if (((unsigned int) INSN_UID (v_node->insn) == u)
+-	    || DEBUG_INSN_P (v_node->insn))
+-	  continue;
+-	
+-	/* Ignore dependencies between memory writes and the
+-	   jump.  */
+-	if (JUMP_P (u_node->insn)
+-	    && e->type == OUTPUT_DEP 
+-            && mem_write_insn_p (v_node->insn))
+-	  continue;
+-	if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
+-	  {
+-	    g->closing_branch_deps = 1;
+-	    return;
+-	  }
+-      }
+-    for (e = u_node->out; e != 0; e = e->next_out)
+-      {
+-	ddg_node_ptr v_node = e->dest;
+-
+-	if (((unsigned int) INSN_UID (v_node->insn) == u)
+-            || DEBUG_INSN_P (v_node->insn))
+-	  continue;
+-	if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
+-	  {
+-	    g->closing_branch_deps = 1;
+-	    return;
+-	  }
+-      }
+-  }
+-  g->closing_branch_deps = 0;
+-}
+ 
+ /* Given a basic block, create its DDG and return a pointer to a variable
+    of ddg type that represents it.
+    Initialize the ddg structure fields to the appropriate values.  */
+ ddg_ptr
+-create_ddg (basic_block bb, sbitmap doloop_insns)
++create_ddg (basic_block bb, int closing_branch_deps)
+ {
+   ddg_ptr g;
+   rtx insn, first_note;
+@@ -520,6 +470,7 @@
+   g = (ddg_ptr) xcalloc (1, sizeof (struct ddg));
+ 
+   g->bb = bb;
++  g->closing_branch_deps = closing_branch_deps;
+ 
+   /* Count the number of insns in the BB.  */
+   for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
+@@ -592,11 +543,6 @@
+   /* Build the data dependency graph.  */
+   build_intra_loop_deps (g);
+   build_inter_loop_deps (g);
+-
+-  /* Check whether the do-loop part is decoupled from the other loop
+-     instructions.  */
+-  check_closing_branch_deps (g, doloop_insns);
+-
+   return g;
+ }
+ 
+@@ -890,18 +836,6 @@
+   return NULL;
+ }
+ 
+-/* Given the uid of an instruction UID return the node that represents it.  */
+-static ddg_node_ptr
+-get_node_of_insn_uid (ddg_ptr g, int uid)
+-{
+-  int i;
+-
+-  for (i = 0; i < g->num_nodes; i++)
+-    if (uid == INSN_UID (g->nodes[i].insn))
+-      return &g->nodes[i];
+-  return NULL;
+-}
+-
+ /* Given a set OPS of nodes in the DDG, find the set of their successors
+    which are not in OPS, and set their bits in SUCC.  Bits corresponding to
+    OPS are cleared from SUCC.  Leaves the other bits in SUCC unchanged.  */
+
+=== modified file 'gcc/ddg.h'
+--- old/gcc/ddg.h	2011-03-24 07:45:38 +0000
++++ new/gcc/ddg.h	2011-05-11 08:00:14 +0000
+@@ -167,7 +167,7 @@
+ };
+ 
+ 
+-ddg_ptr create_ddg (basic_block, sbitmap);
++ddg_ptr create_ddg (basic_block, int closing_branch_deps);
+ void free_ddg (ddg_ptr);
+ 
+ void print_ddg (FILE *, ddg_ptr);
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2011-04-17 23:04:58 +0000
++++ new/gcc/doc/invoke.texi	2011-05-11 08:00:14 +0000
+@@ -8430,6 +8430,10 @@
+ The maximum number of best instructions in the ready list that are considered
+ for renaming in the selective scheduler.  The default value is 2.
+ 
++@item sms-min-sc
++The minimum value of stage count that swing modulo scheduler will
++generate.  The default value is 2.
++
+ @item max-last-value-rtl
+ The maximum size measured as number of RTLs that can be recorded in an expression
+ in combiner for a pseudo register as last known value of that register.  The default
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-03-24 07:45:38 +0000
++++ new/gcc/modulo-sched.c	2011-05-11 08:00:14 +0000
+@@ -84,14 +84,13 @@
+       II cycles (i.e. use register copies to prevent a def from overwriting
+       itself before reaching the use).
+ 
+-    SMS works with countable loops (1) whose control part can be easily
+-    decoupled from the rest of the loop and (2) whose loop count can
+-    be easily adjusted.  This is because we peel a constant number of
+-    iterations into a prologue and epilogue for which we want to avoid
+-    emitting the control part, and a kernel which is to iterate that
+-    constant number of iterations less than the original loop.  So the
+-    control part should be a set of insns clearly identified and having
+-    its own iv, not otherwise used in the loop (at-least for now), which
++    SMS works with countable loops whose loop count can be easily
++    adjusted.  This is because we peel a constant number of iterations
++    into a prologue and epilogue for which we want to avoid emitting
++    the control part, and a kernel which is to iterate that constant
++    number of iterations less than the original loop.  So the control
++    part should be a set of insns clearly identified and having its
++    own iv, not otherwise used in the loop (at-least for now), which
+     initializes a register before the loop to the number of iterations.
+     Currently SMS relies on the do-loop pattern to recognize such loops,
+     where (1) the control part comprises of all insns defining and/or
+@@ -116,7 +115,7 @@
+ 
+ /* The number of different iterations the nodes in ps span, assuming
+    the stage boundaries are placed efficiently.  */
+-#define CALC_STAGE_COUNT(min_cycle,max_cycle,ii) ((max_cycle - min_cycle \
++#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \
+                          + 1 + ii - 1) / ii)
+ /* The stage count of ps.  */
+ #define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
+@@ -200,7 +199,6 @@
+ static void duplicate_insns_of_cycles (partial_schedule_ptr,
+ 				       int, int, int, rtx);
+ static int calculate_stage_count (partial_schedule_ptr ps);
+-
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+ #define SCHED_FIRST_REG_MOVE(x) \
+@@ -318,7 +316,7 @@
+                              : prev_nondebug_insn (tail));
+ 
+   for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
+-    if (reg_mentioned_p (reg, insn) && NONDEBUG_INSN_P (insn))
++    if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn))
+       {
+         if (dump_file)
+         {
+@@ -337,24 +335,6 @@
+ #endif
+ }
+ 
+-/* Mark in DOLOOP_INSNS the instructions that belong to the do-loop part.
+-  Use TAIL to recognize that part.  */
+-static void
+-mark_doloop_insns (sbitmap doloop_insns, rtx tail)
+-{
+-  rtx first_insn_not_to_check, insn;
+-
+-  /* This is the first instruction which belongs the doloop part.  */
+-  first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
+-			     : prev_nondebug_insn (tail));
+-
+-  sbitmap_zero (doloop_insns);
+-  for (insn = first_insn_not_to_check; insn != NEXT_INSN (tail);
+-       insn = NEXT_INSN (insn))
+-    if (NONDEBUG_INSN_P (insn))
+-      SET_BIT (doloop_insns, INSN_UID (insn));
+-}
+-
+ /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
+    that the number of iterations is a compile-time constant.  If so,
+    return the rtx that sets COUNT_REG to a constant, and set COUNT to
+@@ -607,44 +587,42 @@
+ 	ddg_node_ptr u = crr_insn->node;
+ 	int normalized_time = SCHED_TIME (u) - amount;
+ 	int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
+-        /* The first cycle in row zero after the rotation.  */
+-	int new_first_cycle_in_row_zero = 
+-	  new_min_cycle + ii - SMODULO (new_min_cycle, ii);
++        int sc_until_cycle_zero, stage;
+ 
+-	if (dump_file)
+-	  fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
+-		   min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME
+-		   (u), ps->min_cycle);
++        if (dump_file)
++          {
++            /* Print the scheduling times after the rotation.  */
++            fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
++                     "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
++                     INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
++                     normalized_time);
++            if (JUMP_P (crr_insn->node->insn))
++              fprintf (dump_file, " (branch)");
++            fprintf (dump_file, "\n");
++          }
++	
+ 	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+ 	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+ 	SCHED_TIME (u) = normalized_time;
+-	crr_insn->cycle = normalized_time;
+ 	SCHED_ROW (u) = SMODULO (normalized_time, ii);
+-
+-	/* If min_cycle is in row zero after the rotation then
+-	   the stage count can be calculated by dividing the cycle
+-	   with ii.  Otherwise, the calculation is done by dividing the
+-	   SMSed kernel into two intervals:
+-
+-	   1) min_cycle	              <= interval 0 < first_cycle_in_row_zero
+-	   2) first_cycle_in_row_zero <= interval 1 < max_cycle
+-	   
+-	   Cycles in interval 0 are in stage 0. The stage of cycles
+-	   in interval 1 should be added by 1 to take interval 0 into
+-	   account.  */
+-	if (SMODULO (new_min_cycle, ii) == 0)
+-          SCHED_STAGE (u) = normalized_time / ii;
+-        else
+-	  {
+-            if (crr_insn->cycle < new_first_cycle_in_row_zero)
+-	      SCHED_STAGE (u) = 0;
+-	    else
+-              SCHED_STAGE (u) = 
+-		((SCHED_TIME (u) - new_first_cycle_in_row_zero) / ii) + 1;
++      
++        /* The calculation of stage count is done adding the number
++           of stages before cycle zero and after cycle zero.  */
++	sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
++	
++	if (SCHED_TIME (u) < 0)
++	  {
++	    stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
++	    SCHED_STAGE (u) = sc_until_cycle_zero - stage;
++	  }
++	else
++	  {
++	    stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
++	    SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
+ 	  }
+       }
+ }
+-
++ 
+ /* Set SCHED_COLUMN of each node according to its position in PS.  */
+ static void
+ set_columns_for_ps (partial_schedule_ptr ps)
+@@ -694,8 +672,8 @@
+ 
+         /* Do not duplicate any insn which refers to count_reg as it
+            belongs to the control part.
+-           If closing_branch_deps is true the closing branch is scheduled
+-           as well and thus should be ignored.
++           The closing branch is scheduled as well and thus should
++           be ignored.
+            TODO: This should be done by analyzing the control part of
+            the loop.  */
+         if (reg_mentioned_p (count_reg, u_node->insn)
+@@ -945,8 +923,7 @@
+   basic_block condition_bb = NULL;
+   edge latch_edge;
+   gcov_type trip_count = 0;
+-  sbitmap doloop_insns;
+-  
++
+   loop_optimizer_init (LOOPS_HAVE_PREHEADERS
+ 		       | LOOPS_HAVE_RECORDED_EXITS);
+   if (number_of_loops () <= 1)
+@@ -971,7 +948,6 @@
+   setup_sched_infos ();
+   haifa_sched_init ();
+ 
+-  doloop_insns = sbitmap_alloc (get_max_uid () + 1);
+   /* Allocate memory to hold the DDG array one entry for each loop.
+      We use loop->num as index into this array.  */
+   g_arr = XCNEWVEC (ddg_ptr, number_of_loops ());
+@@ -1104,16 +1080,18 @@
+ 
+ 	  continue;
+ 	}
+-      mark_doloop_insns (doloop_insns, tail);
+-      if (! (g = create_ddg (bb, doloop_insns)))
++
++      /* Always schedule the closing branch with the rest of the
++         instructions. The branch is rotated to be in row ii-1 at the
++         end of the scheduling procedure to make sure it's the last
++         instruction in the iteration.  */
++      if (! (g = create_ddg (bb, 1)))
+         {
+           if (dump_file)
+ 	    fprintf (dump_file, "SMS create_ddg failed\n");
+ 	  continue;
+         }
+-      if (dump_file)
+-        fprintf (dump_file, "SMS closing_branch_deps: %d\n", 
+-                 g->closing_branch_deps); 
++
+       g_arr[loop->num] = g;
+       if (dump_file)
+         fprintf (dump_file, "...OK\n");
+@@ -1215,16 +1193,17 @@
+ 
+       ps = sms_schedule_by_order (g, mii, maxii, node_order);
+ 
+-      if (ps)
+-	{
+-	  stage_count = calculate_stage_count (ps);
+-	  gcc_assert(stage_count >= 1);
+-	  PS_STAGE_COUNT(ps) = stage_count;
+-	}
+-      
+-      /* Stage count of 1 means that there is no interleaving between
+-         iterations, let the scheduling passes do the job.  */
+-      if (stage_count <= 1
++       if (ps)
++       {
++         stage_count = calculate_stage_count (ps);
++         gcc_assert(stage_count >= 1);
++         PS_STAGE_COUNT(ps) = stage_count;
++       }
++
++      /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
++         1 means that there is no interleaving between iterations thus
++         we let the scheduling passes do the job in this case.  */
++      if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
+ 	  || (count_init && (loop_count <= stage_count))
+ 	  || (flag_branch_probabilities && (trip_count <= stage_count)))
+ 	{
+@@ -1242,21 +1221,12 @@
+       else
+ 	{
+ 	  struct undo_replace_buff_elem *reg_move_replaces;
+-	  int amount;
+-
+-	  /* Set the stage boundaries.  If the DDG is built with closing_branch_deps,
+-	     the closing_branch was scheduled and should appear in the last (ii-1)
+-	     row.  Otherwise, we are free to schedule the branch, and we let nodes
+-	     that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
+-	     row; this should reduce stage_count to minimum.
+-             TODO: Revisit the issue of scheduling the insns of the
+-             control part relative to the branch when the control part
+-             has more than one insn.  */
+-	  amount = (g->closing_branch_deps)? SCHED_TIME (g->closing_branch) + 1: 
+-	    PS_MIN_CYCLE (ps);
++          int amount = SCHED_TIME (g->closing_branch) + 1;
++	  
++	  /* Set the stage boundaries.	The closing_branch was scheduled
++	     and should appear in the last (ii-1) row.  */
+ 	  reset_sched_times (ps, amount);
+ 	  rotate_partial_schedule (ps, amount);
+-	  
+ 	  set_columns_for_ps (ps);
+ 
+ 	  canon_loop (loop);
+@@ -1267,13 +1237,8 @@
+ 		       "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
+ 		       stage_count);
+ 	      print_partial_schedule (ps, dump_file);
+-	      if (!g->closing_branch_deps)
+-		fprintf (dump_file,
+-			 "SMS Branch (%d) will later be scheduled at \
+-			 cycle %d.\n",
+-			 g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
+-            }
+-
++	    }
++ 
+           /* case the BCT count is not known , Do loop-versioning */
+ 	  if (count_reg && ! count_init)
+             {
+@@ -1318,7 +1283,6 @@
+     }
+ 
+   free (g_arr);
+-  sbitmap_free (doloop_insns);
+ 
+   /* Release scheduler data, needed until now because of DFA.  */
+   haifa_sched_finish ();
+@@ -1826,13 +1790,6 @@
+ 	      RESET_BIT (tobe_scheduled, u);
+ 	      continue;
+ 	    }
+-	  /* Closing branch handled later unless closing_branch_deps
+-	     is true.  */
+-	  if (JUMP_P (insn) && !g->closing_branch_deps) 
+-	    {
+-	      RESET_BIT (tobe_scheduled, u);
+-	      continue;
+-	    }
+ 
+ 	  if (TEST_BIT (sched_nodes, u))
+ 	    continue;
+@@ -2675,9 +2632,9 @@
+        last_in_row = next_ps_i;
+     }
+ 
+-  /* If closing_branch_deps is true we are scheduling the closing
+-     branch as well.  Make sure there is no dependent instruction after
+-     it as the branch should be the last instruction.  */
++  /* The closing branch is scheduled as well.  Make sure there is no
++     dependent instruction after it as the branch should be the last
++     instruction in the row.  */
+   if (JUMP_P (ps_i->node->insn)) 
+     {
+       if (first_must_follow)
+@@ -2918,51 +2875,21 @@
+   return ps_i;
+ }
+ 
+-/* Calculate the stage count of the partial schedule PS.  */
++/* Calculate the stage count of the partial schedule PS.  The calculation
++   takes into account the rotation to bring the closing branch to row
++   ii-1.  */
+ int
+ calculate_stage_count (partial_schedule_ptr ps)
+ {
+-  int stage_count;
+-
+-  /* If closing_branch_deps is false then the stage
+-     boundaries are placed efficiently, meaning that min_cycle will be
+-     placed at row 0. Otherwise, the closing branch will be placed in
+-     row ii-1. For the later case we assume the final SMSed kernel can
+-     be divided into two intervals. This assumption is used for the
+-     stage count calculation:
+-
+-     1) min_cycle               <= interval 0 < first_cycle_in_row_zero
+-     2) first_cycle_in_row_zero <= interval 1 < max_cycle
+-   */
+-  stage_count =
+-    CALC_STAGE_COUNT (PS_MIN_CYCLE (ps), PS_MAX_CYCLE (ps), ps->ii);
+-  if (ps->g->closing_branch_deps)
+-    {
+-      int new_min_cycle;
+-      int new_min_cycle_row;
+-      int rotation_amount = SCHED_TIME (ps->g->closing_branch) + 1;
+-
+-      /* This is the new value of min_cycle after the final rotation to
+-         bring closing branch into row ii-1.  */
+-      new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
+-      /* This is the row which the the new min_cycle will be placed in.  */
+-      new_min_cycle_row = SMODULO (new_min_cycle, ps->ii);
+-      /* If the row of min_cycle is zero then interval 0 is empty.
+-         Otherwise, we need to calculate interval 1 and add it by one
+-         to take interval 0 into account.  */
+-      if (new_min_cycle_row != 0)
+-	{
+-	  int new_max_cycle, first_cycle_in_row_zero;
+-
+-	  new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
+-	  first_cycle_in_row_zero =
+-	    new_min_cycle + ps->ii - new_min_cycle_row;
+-
+-	  stage_count =
+-	    CALC_STAGE_COUNT (first_cycle_in_row_zero, new_max_cycle,
+-			      ps->ii) + 1;
+-	}
+-    }
++  int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
++  int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
++  int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
++  int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
++
++  /* The calculation of stage count is done adding the number of stages
++     before cycle zero and after cycle zero.  */ 
++  stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii);
++
+   return stage_count;
+ }
+ 
+
+=== modified file 'gcc/params.def'
+--- old/gcc/params.def	2011-02-01 14:20:13 +0000
++++ new/gcc/params.def	2011-05-11 08:00:14 +0000
+@@ -324,6 +324,11 @@
+ 	 "sms-max-ii-factor",
+ 	 "A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop",
+ 	 100, 0, 0)
++/* The minimum value of stage count that swing modulo scheduler will generate.  */
++DEFPARAM(PARAM_SMS_MIN_SC,
++        "sms-min-sc",
++        "The minimum value of stage count that swing modulo scheduler will generate.",
++        2, 1, 1)
+ DEFPARAM(PARAM_SMS_DFA_HISTORY,
+ 	 "sms-dfa-history",
+ 	 "The number of cycles the swing modulo scheduler considers when checking conflicts using DFA",
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch
new file mode 100644
index 0000000000..3fe9bbca52
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch
@@ -0,0 +1,32 @@
+2011-05-19  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	* ddg.c (free_ddg_all_sccs): Free sccs field in struct
+	ddg_all_sccs.
+	* modulo-sched.c (sms_schedule): Avoid unfreed
+	memory when SMS fails.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-05-11 08:00:14 +0000
++++ new/gcc/ddg.c	2011-05-13 16:16:22 +0000
+@@ -978,6 +978,7 @@
+   for (i = 0; i < all_sccs->num_sccs; i++)
+     free_scc (all_sccs->sccs[i]);
+ 
++  free (all_sccs->sccs);
+   free (all_sccs);
+ }
+ 
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-05-11 08:00:14 +0000
++++ new/gcc/modulo-sched.c	2011-05-13 16:16:22 +0000
+@@ -1216,7 +1216,6 @@
+ 	      fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
+ 	      fprintf (dump_file, ")\n");
+ 	    }
+-	  continue;
+ 	}
+       else
+ 	{
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch
new file mode 100644
index 0000000000..e058eb15e0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch
@@ -0,0 +1,45 @@
+2011-06-09  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	LP:748138
+
+	gcc/
+	* cfgrtl.c (try_redirect_by_replacing_jump): Treat EXIT_BLOCK_PTR case
+	separately before call to redirect_jump(). Add assertion.
+	(patch_jump_insn): Same.
+
+=== modified file 'gcc/cfgrtl.c'
+--- old/gcc/cfgrtl.c	2011-02-08 10:51:58 +0000
++++ new/gcc/cfgrtl.c	2011-05-12 08:56:07 +0000
+@@ -835,11 +835,10 @@
+       if (dump_file)
+ 	fprintf (dump_file, "Redirecting jump %i from %i to %i.\n",
+ 		 INSN_UID (insn), e->dest->index, target->index);
+-      if (!redirect_jump (insn, block_label (target), 0))
+-	{
+-	  gcc_assert (target == EXIT_BLOCK_PTR);
+-	  return NULL;
+-	}
++      if (target == EXIT_BLOCK_PTR)
++	return NULL;
++      if (! redirect_jump (insn, block_label (target), 0))
++	gcc_unreachable ();
+     }
+ 
+   /* Cannot do anything for target exit block.  */
+@@ -1019,11 +1018,10 @@
+ 	  /* If the substitution doesn't succeed, die.  This can happen
+ 	     if the back end emitted unrecognizable instructions or if
+ 	     target is exit block on some arches.  */
+-	  if (!redirect_jump (insn, block_label (new_bb), 0))
+-	    {
+-	      gcc_assert (new_bb == EXIT_BLOCK_PTR);
+-	      return false;
+-	    }
++	  if (new_bb == EXIT_BLOCK_PTR)
++	    return false;
++	  if (! redirect_jump (insn, block_label (new_bb), 0))
++	    gcc_unreachable ();
+ 	}
+     }
+   return true;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99519.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99519.patch
new file mode 100644
index 0000000000..5337070afd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99519.patch
@@ -0,0 +1,25 @@
+2011-07-01  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+	LP 744754
+        2011-04-17  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* config/arm/arm.c (neon_struct_mem_operand):
+	Support POST_INC/PRE_DEC memory operands.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-05-11 14:47:14 +0000
++++ new/gcc/config/arm/arm.c	2011-06-29 10:46:39 +0000
+@@ -9322,6 +9322,11 @@
+   if (GET_CODE (ind) == REG)
+     return arm_address_register_rtx_p (ind, 0);
+ 
++  /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db).  */
++  if (GET_CODE (ind) == POST_INC
++      || GET_CODE (ind) == PRE_DEC)
++    return arm_address_register_rtx_p (XEXP (ind, 0), 0);
++
+   return FALSE;
+ }
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99521.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99521.patch
new file mode 100644
index 0000000000..6d2d75bf91
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99521.patch
@@ -0,0 +1,166 @@
+2011-07-08  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	gcc/
+	* builtins.c (get_object_alignment): Fix comment.
+	* fold-const.c (get_pointer_modulus_and_residue): Remove
+	allow_func_align.  Use get_object_alignment.
+	(fold_binary_loc): Update caller.
+
+2011-07-08  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	gcc/
+	Backport from mainline:
+
+	2011-06-29  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR tree-optimization/49545
+	* builtins.c (get_object_alignment_1): Update function comment.
+	Do not use DECL_ALIGN for functions, but test
+	TARGET_PTRMEMFUNC_VBIT_LOCATION instead.
+	* fold-const.c (get_pointer_modulus_and_residue): Don't check
+	for functions here.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-06-29  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.dg/torture/pr49169.c: Restrict to ARM and MIPS targets.
+
+2011-07-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-07-27  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/49169
+	* fold-const.c (get_pointer_modulus_and_residue): Don't rely on
+	the alignment of function decls.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-07-27  Michael Hope  <michael.hope@linaro.org>
+		    Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR tree-optimization/49169
+	* gcc.dg/torture/pr49169.c: New test.
+
+=== modified file 'gcc/builtins.c'
+--- old/gcc/builtins.c	2011-01-06 11:02:44 +0000
++++ new/gcc/builtins.c	2011-06-29 09:59:48 +0000
+@@ -263,7 +263,14 @@
+ 
+ /* Return the alignment in bits of EXP, an object.
+    Don't return more than MAX_ALIGN no matter what, ALIGN is the inital
+-   guessed alignment e.g. from type alignment.  */
++   guessed alignment e.g. from type alignment.
++
++   Note that the address (and thus the alignment) computed here is based
++   on the address to which a symbol resolves, whereas DECL_ALIGN is based
++   on the address at which an object is actually located.  These two
++   addresses are not always the same.  For example, on ARM targets,
++   the address &foo of a Thumb function foo() has the lowest bit set,
++   whereas foo() itself starts on an even address.  */
+ 
+ int
+ get_object_alignment (tree exp, unsigned int align, unsigned int max_align)
+@@ -327,7 +334,21 @@
+     exp = DECL_INITIAL (exp);
+   if (DECL_P (exp)
+       && TREE_CODE (exp) != LABEL_DECL)
+-    align = MIN (inner, DECL_ALIGN (exp));
++    {
++      if (TREE_CODE (exp) == FUNCTION_DECL)
++	{
++	  /* Function addresses can encode extra information besides their
++	     alignment.  However, if TARGET_PTRMEMFUNC_VBIT_LOCATION
++	     allows the low bit to be used as a virtual bit, we know
++	     that the address itself must be 2-byte aligned.  */
++	  if (TARGET_PTRMEMFUNC_VBIT_LOCATION == ptrmemfunc_vbit_in_pfn)
++	    align = 2 * BITS_PER_UNIT;
++	  else
++	    align = BITS_PER_UNIT;
++	}
++      else
++	align = MIN (inner, DECL_ALIGN (exp));
++    }
+ #ifdef CONSTANT_ALIGNMENT
+   else if (CONSTANT_CLASS_P (exp))
+     align = MIN (inner, (unsigned)CONSTANT_ALIGNMENT (exp, align));
+
+=== modified file 'gcc/fold-const.c'
+--- old/gcc/fold-const.c	2011-05-05 14:28:53 +0000
++++ new/gcc/fold-const.c	2011-07-08 12:54:44 +0000
+@@ -10030,15 +10030,10 @@
+    0 <= N < M as is common.  In general, the precise value of P is unknown.
+    M is chosen as large as possible such that constant N can be determined.
+ 
+-   Returns M and sets *RESIDUE to N.
+-
+-   If ALLOW_FUNC_ALIGN is true, do take functions' DECL_ALIGN_UNIT into
+-   account.  This is not always possible due to PR 35705.
+- */
++   Returns M and sets *RESIDUE to N.  */
+ 
+ static unsigned HOST_WIDE_INT
+-get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue,
+-				 bool allow_func_align)
++get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue)
+ {
+   enum tree_code code;
+ 
+@@ -10068,9 +10063,8 @@
+ 	    }
+ 	}
+ 
+-      if (DECL_P (expr)
+-	  && (allow_func_align || TREE_CODE (expr) != FUNCTION_DECL))
+-	return DECL_ALIGN_UNIT (expr);
++      if (DECL_P (expr))
++	return get_object_alignment (expr, BITS_PER_UNIT, ~0U) / BITS_PER_UNIT;
+     }
+   else if (code == POINTER_PLUS_EXPR)
+     {
+@@ -10080,8 +10074,7 @@
+ 
+       op0 = TREE_OPERAND (expr, 0);
+       STRIP_NOPS (op0);
+-      modulus = get_pointer_modulus_and_residue (op0, residue,
+-						 allow_func_align);
++      modulus = get_pointer_modulus_and_residue (op0, residue);
+ 
+       op1 = TREE_OPERAND (expr, 1);
+       STRIP_NOPS (op1);
+@@ -11801,8 +11794,7 @@
+ 	  unsigned HOST_WIDE_INT modulus, residue;
+ 	  unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg1);
+ 
+-	  modulus = get_pointer_modulus_and_residue (arg0, &residue,
+-						     integer_onep (arg1));
++	  modulus = get_pointer_modulus_and_residue (arg0, &residue);
+ 
+ 	  /* This works because modulus is a power of 2.  If this weren't the
+ 	     case, we'd have to replace it by its greatest power-of-2
+
+=== added file 'gcc/testsuite/gcc.dg/torture/pr49169.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49169.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49169.c	2011-06-29 09:59:48 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile { target { arm*-*-* || mips*-*-* } } } */
++
++#include <stdlib.h>
++#include <stdint.h>
++
++int
++main (void)
++{
++  void *p = main;
++  if ((intptr_t) p & 1)
++    abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "abort" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99522.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99522.patch
new file mode 100644
index 0000000000..cdf44b1184
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99522.patch
@@ -0,0 +1,210 @@
+2011-07-11  Revital Eres  <revital.eres@linaro.org>
+
+	Backport from mainline -r175091
+	gcc/
+	* modulo-sched.c (struct ps_insn): Remove row_rest_count field.
+	(struct partial_schedule): Add rows_length field.
+	(verify_partial_schedule): Check rows_length.
+	(ps_insert_empty_row): Handle rows_length.
+	(create_partial_schedule): Likewise.
+	(free_partial_schedule): Likewise.
+	(reset_partial_schedule): Likewise.
+	(create_ps_insn): Remove rest_count argument.
+	(remove_node_from_ps): Update rows_length.
+	(add_node_to_ps): Update rows_length and call create_ps_insn
+	without passing row_rest_count.
+	(rotate_partial_schedule): Update rows_length.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-05-13 16:16:22 +0000
++++ new/gcc/modulo-sched.c	2011-07-04 11:39:09 +0000
+@@ -134,8 +134,6 @@
+   ps_insn_ptr next_in_row,
+ 	      prev_in_row;
+ 
+-  /* The number of nodes in the same row that come after this node.  */
+-  int row_rest_count;
+ };
+ 
+ /* Holds the partial schedule as an array of II rows.  Each entry of the
+@@ -149,6 +147,12 @@
+   /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii).  */
+   ps_insn_ptr *rows;
+ 
++  /*  rows_length[i] holds the number of instructions in the row.
++      It is used only (as an optimization) to back off quickly from
++      trying to schedule a node in a full row; that is, to avoid running
++      through futile DFA state transitions.  */
++  int *rows_length;
++  
+   /* The earliest absolute cycle of an insn in the partial schedule.  */
+   int min_cycle;
+ 
+@@ -1907,6 +1911,7 @@
+   int ii = ps->ii;
+   int new_ii = ii + 1;
+   int row;
++  int *rows_length_new;
+ 
+   verify_partial_schedule (ps, sched_nodes);
+ 
+@@ -1921,9 +1926,11 @@
+   rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
+ 
+   rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
++  rows_length_new = (int *) xcalloc (new_ii, sizeof (int));
+   for (row = 0; row < split_row; row++)
+     {
+       rows_new[row] = ps->rows[row];
++      rows_length_new[row] = ps->rows_length[row];
+       ps->rows[row] = NULL;
+       for (crr_insn = rows_new[row];
+ 	   crr_insn; crr_insn = crr_insn->next_in_row)
+@@ -1944,6 +1951,7 @@
+   for (row = split_row; row < ii; row++)
+     {
+       rows_new[row + 1] = ps->rows[row];
++      rows_length_new[row + 1] = ps->rows_length[row];
+       ps->rows[row] = NULL;
+       for (crr_insn = rows_new[row + 1];
+ 	   crr_insn; crr_insn = crr_insn->next_in_row)
+@@ -1965,6 +1973,8 @@
+     + (SMODULO (ps->max_cycle, ii) >= split_row ? 1 : 0);
+   free (ps->rows);
+   ps->rows = rows_new;
++  free (ps->rows_length);
++  ps->rows_length = rows_length_new;
+   ps->ii = new_ii;
+   gcc_assert (ps->min_cycle >= 0);
+ 
+@@ -2040,16 +2050,23 @@
+   ps_insn_ptr crr_insn;
+ 
+   for (row = 0; row < ps->ii; row++)
+-    for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
+-      {
+-	ddg_node_ptr u = crr_insn->node;
+-
+-	gcc_assert (TEST_BIT (sched_nodes, u->cuid));
+-	/* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
+-	   popcount (sched_nodes) == number of insns in ps.  */
+-	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+-	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+-      }
++    {
++      int length = 0;
++      
++      for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
++	{
++	  ddg_node_ptr u = crr_insn->node;
++	  
++	  length++;
++	  gcc_assert (TEST_BIT (sched_nodes, u->cuid));
++	  /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
++	     popcount (sched_nodes) == number of insns in ps.  */
++	  gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
++	  gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
++	}
++      
++      gcc_assert (ps->rows_length[row] == length);
++    }
+ }
+ 
+ 
+@@ -2455,6 +2472,7 @@
+ {
+   partial_schedule_ptr ps = XNEW (struct partial_schedule);
+   ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
++  ps->rows_length = (int *) xcalloc (ii, sizeof (int));
+   ps->ii = ii;
+   ps->history = history;
+   ps->min_cycle = INT_MAX;
+@@ -2493,6 +2511,7 @@
+     return;
+   free_ps_insns (ps);
+   free (ps->rows);
++  free (ps->rows_length);
+   free (ps);
+ }
+ 
+@@ -2510,6 +2529,8 @@
+   ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii
+ 						 * sizeof (ps_insn_ptr));
+   memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr));
++  ps->rows_length = (int *) xrealloc (ps->rows_length, new_ii * sizeof (int));
++  memset (ps->rows_length, 0, new_ii * sizeof (int));
+   ps->ii = new_ii;
+   ps->min_cycle = INT_MAX;
+   ps->max_cycle = INT_MIN;
+@@ -2538,14 +2559,13 @@
+ 
+ /* Creates an object of PS_INSN and initializes it to the given parameters.  */
+ static ps_insn_ptr
+-create_ps_insn (ddg_node_ptr node, int rest_count, int cycle)
++create_ps_insn (ddg_node_ptr node, int cycle)
+ {
+   ps_insn_ptr ps_i = XNEW (struct ps_insn);
+ 
+   ps_i->node = node;
+   ps_i->next_in_row = NULL;
+   ps_i->prev_in_row = NULL;
+-  ps_i->row_rest_count = rest_count;
+   ps_i->cycle = cycle;
+ 
+   return ps_i;
+@@ -2578,6 +2598,8 @@
+       if (ps_i->next_in_row)
+ 	ps_i->next_in_row->prev_in_row = ps_i->prev_in_row;
+     }
++   
++  ps->rows_length[row] -= 1; 
+   free (ps_i);
+   return true;
+ }
+@@ -2734,17 +2756,12 @@
+ 		sbitmap must_precede, sbitmap must_follow)
+ {
+   ps_insn_ptr ps_i;
+-  int rest_count = 1;
+   int row = SMODULO (cycle, ps->ii);
+ 
+-  if (ps->rows[row]
+-      && ps->rows[row]->row_rest_count >= issue_rate)
++  if (ps->rows_length[row] >= issue_rate)
+     return NULL;
+ 
+-  if (ps->rows[row])
+-    rest_count += ps->rows[row]->row_rest_count;
+-
+-  ps_i = create_ps_insn (node, rest_count, cycle);
++  ps_i = create_ps_insn (node, cycle);
+ 
+   /* Finds and inserts PS_I according to MUST_FOLLOW and
+      MUST_PRECEDE.  */
+@@ -2754,6 +2771,7 @@
+       return NULL;
+     }
+ 
++  ps->rows_length[row] += 1;
+   return ps_i;
+ }
+ 
+@@ -2909,11 +2927,16 @@
+   for (i = 0; i < backward_rotates; i++)
+     {
+       ps_insn_ptr first_row = ps->rows[0];
++      int first_row_length = ps->rows_length[0];
+ 
+       for (row = 0; row < last_row; row++)
+-	ps->rows[row] = ps->rows[row+1];
++	{
++	  ps->rows[row] = ps->rows[row + 1];
++	  ps->rows_length[row] = ps->rows_length[row + 1]; 
++	}
+ 
+       ps->rows[last_row] = first_row;
++      ps->rows_length[last_row] = first_row_length;
+     }
+ 
+   ps->max_cycle -= start_cycle;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99523.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99523.patch
new file mode 100644
index 0000000000..64eb23777d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99523.patch
@@ -0,0 +1,119 @@
+2011-07-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	Backport from mainline:
+	gcc/
+	2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* reload1.c (choose_reload_regs): Use mode sizes to check whether
+	an old reload register completely defines the required value.
+
+	gcc/testsuite/
+	2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/arm/neon-modes-3.c: New test.
+
+=== modified file 'gcc/reload1.c'
+--- old/gcc/reload1.c	2011-07-01 09:27:50 +0000
++++ new/gcc/reload1.c	2011-07-11 10:05:08 +0000
+@@ -6449,6 +6449,8 @@
+ 
+ 	      if (regno >= 0
+ 		  && reg_last_reload_reg[regno] != 0
++		  && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
++		      >= GET_MODE_SIZE (mode) + byte)
+ #ifdef CANNOT_CHANGE_MODE_CLASS
+ 		  /* Verify that the register it's in can be used in
+ 		     mode MODE.  */
+@@ -6460,24 +6462,12 @@
+ 		{
+ 		  enum reg_class rclass = rld[r].rclass, last_class;
+ 		  rtx last_reg = reg_last_reload_reg[regno];
+-		  enum machine_mode need_mode;
+ 
+ 		  i = REGNO (last_reg);
+ 		  i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
+ 		  last_class = REGNO_REG_CLASS (i);
+ 
+-		  if (byte == 0)
+-		    need_mode = mode;
+-		  else
+-		    need_mode
+-		      = smallest_mode_for_size
+-		        (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
+-			 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
+-			 ? MODE_INT : GET_MODE_CLASS (mode));
+-
+-		  if ((GET_MODE_SIZE (GET_MODE (last_reg))
+-		       >= GET_MODE_SIZE (need_mode))
+-		      && reg_reloaded_contents[i] == regno
++		  if (reg_reloaded_contents[i] == regno
+ 		      && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
+ 		      && HARD_REGNO_MODE_OK (i, rld[r].mode)
+ 		      && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-3.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-modes-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-modes-3.c	2011-07-11 10:05:08 +0000
+@@ -0,0 +1,61 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n)
++{
++  float32x4x4_t a5, a6, a7, a8, a9;
++  int i;
++
++  a5 = *src;
++  a6 = *src;
++  a7 = *src;
++  a8 = *src;
++  a9 = *src;
++  while (n--)
++    {
++      for (i = 0; i < 8; i++)
++	{
++	  float32x4x4_t a0, a1, a2, a3, a4;
++
++	  a0 = *src;
++	  a1 = *src;
++	  a2 = *src;
++	  a3 = *src;
++	  a4 = *src;
++	  *src = a0;
++	  *dest = a0.val[0];
++	  *dest = a0.val[3];
++	  *src = a1;
++	  *dest = a1.val[0];
++	  *dest = a1.val[3];
++	  *src = a2;
++	  *dest = a2.val[0];
++	  *dest = a2.val[3];
++	  *src = a3;
++	  *dest = a3.val[0];
++	  *dest = a3.val[3];
++	  *src = a4;
++	  *dest = a4.val[0];
++	  *dest = a4.val[3];
++	}
++      *src = a5;
++      *dest = a5.val[0];
++      *dest = a5.val[3];
++      *src = a6;
++      *dest = a6.val[0];
++      *dest = a6.val[3];
++      *src = a7;
++      *dest = a7.val[0];
++      *dest = a7.val[3];
++      *src = a8;
++      *dest = a8.val[0];
++      *dest = a8.val[3];
++      *src = a9;
++      *dest = a9.val[0];
++      *dest = a9.val[3];
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch
new file mode 100644
index 0000000000..2e8e12d2a5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch
@@ -0,0 +1,209 @@
+ 2011-07-14  Richard Sandiford  <richard.sandiford@linaro.org>
+ 
+	gcc/
+	* config/arm/arm.h (ARM_LEGITIMIZE_RELOAD_ADDRESS): Apply the
+	arm_legitimize_reload_address changes marked [*] below.
+
+	Backport from mainline:
+
+	2011-04-20  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	[*] config/arm/arm.c (arm_legitimize_reload_address): For NEON
+	quad-word modes, reduce to 9-bit index range when above 1016
+	limit.
+
+	2011-04-11  Chung-Lin Tang  <cltang@codesourcery.com>
+		    Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/48250
+	[*] config/arm/arm.c (arm_legitimize_reload_address): Update cases
+	to use sign-magnitude offsets. Reject unsupported unaligned
+	cases. Add detailed description in comments.
+	* config/arm/arm.md (reload_outdf): Disable for ARM mode; change
+	condition from TARGET_32BIT to TARGET_ARM.
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-04-20 10:07:36 +0000
++++ new/gcc/config/arm/arm.h	2011-07-12 16:35:20 +0000
+@@ -1399,6 +1399,11 @@
+     ? GENERAL_REGS : NO_REGS)					\
+    : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
+ 
++#define SIGN_MAG_LOW_ADDR_BITS(VAL, N)					\
++      (((VAL) & ((1 << (N)) - 1))					\
++       ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N))	\
++       : 0)
++
+ /* Try a machine-dependent way of reloading an illegitimate address
+    operand.  If we find one, push the reload and jump to WIN.  This
+    macro is used in only one place: `find_reloads_address' in reload.c.
+@@ -1418,26 +1423,135 @@
+ 	  HOST_WIDE_INT val = INTVAL (XEXP (X, 1));			   \
+ 	  HOST_WIDE_INT low, high;					   \
+ 									   \
+-	  if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT))	   \
+-	    low = ((val & 0xf) ^ 0x8) - 0x8;				   \
+-	  else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)		   \
+-	    /* Need to be careful, -256 is not a valid offset.  */	   \
+-	    low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);		   \
+-	  else if (TARGET_REALLY_IWMMXT && MODE == SImode)		   \
+-	    /* Need to be careful, -1024 is not a valid offset.  */	   \
+-	    low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);		   \
+-	  else if (MODE == SImode					   \
+-		   || (MODE == SFmode && TARGET_SOFT_FLOAT)		   \
+-		   || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
+-	    /* Need to be careful, -4096 is not a valid offset.  */	   \
+-	    low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);		   \
+-	  else if ((MODE == HImode || MODE == QImode) && arm_arch4)	   \
+-	    /* Need to be careful, -256 is not a valid offset.  */	   \
+-	    low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);		   \
+-	  else if (GET_MODE_CLASS (MODE) == MODE_FLOAT			   \
+-		   && TARGET_HARD_FLOAT && TARGET_FPA)			   \
+-	    /* Need to be careful, -1024 is not a valid offset.  */	   \
+-	    low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);		   \
++	  /* Detect coprocessor load/stores.  */			   \
++	  bool coproc_p = ((TARGET_HARD_FLOAT				   \
++			    && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK) \
++			    && (mode == SFmode || mode == DFmode	   \
++				|| (mode == DImode && TARGET_MAVERICK)))   \
++			   || (TARGET_REALLY_IWMMXT			   \
++			       && VALID_IWMMXT_REG_MODE (mode))		   \
++			   || (TARGET_NEON				   \
++			       && (VALID_NEON_DREG_MODE (mode)		   \
++				   || VALID_NEON_QREG_MODE (mode))));	   \
++									   \
++	  /* For some conditions, bail out when lower two bits are	   \
++	     unaligned.  */						   \
++	  if ((val & 0x3) != 0						   \
++	      /* Coprocessor load/store indexes are 8-bits + '00'	   \
++		 appended.  */						   \
++	      && (coproc_p 						   \
++		  /* For DI, and DF under soft-float: */		   \
++		  || ((mode == DImode || mode == DFmode)		   \
++		      /* Without ldrd, we use stm/ldm, which does not	   \
++			 fair well with unaligned bits.  */		   \
++		      && (! TARGET_LDRD					   \
++			  /* Thumb-2 ldrd/strd is [-1020,+1020] in	   \
++			     steps of 4.  */				   \
++			  || TARGET_THUMB2))))				   \
++	    break;						   	   \
++									   \
++	  /* When breaking down a [reg+index] reload address into	   \
++	     [(reg+high)+low], of which the (reg+high) gets turned into	   \
++	     a reload add insn, we try to decompose the index into	   \
++	     high/low values that can often also lead to better reload	   \
++	     CSE.  For example:						   \
++		     ldr r0, [r2, #4100]  // Offset too large		   \
++		     ldr r1, [r2, #4104]  // Offset too large		   \
++									   \
++	     is best reloaded as:					   \
++		     add t1, r2, #4096					   \
++		     ldr r0, [t1, #4]					   \
++		     add t2, r2, #4096					   \
++		     ldr r1, [t2, #8]					   \
++									   \
++	     which post-reload CSE can simplify in most cases to eliminate \
++	     the second add instruction:				   \
++		     add t1, r2, #4096					   \
++		     ldr r0, [t1, #4]					   \
++		     ldr r1, [t1, #8]					   \
++									   \
++	     The idea here is that we want to split out the bits of the	   \
++	     constant as a mask, rather than as subtracting the maximum	   \
++	     offset that the respective type of load/store used can	   \
++	     handle.							   \
++									   \
++	     When encountering negative offsets, we can still utilize it   \
++	     even if the overall offset is positive; sometimes this may	   \
++	     lead to an immediate that can be constructed with fewer	   \
++	     instructions.  For example:				   \
++		     ldr r0, [r2, #0x3FFFFC]				   \
++									   \
++	     This is best reloaded as:					   \
++		     add t1, r2, #0x400000				   \
++		     ldr r0, [t1, #-4]					   \
++									   \
++	     The trick for spotting this for a load insn with N bits of	   \
++	     offset (i.e. bits N-1:0) is to look at bit N; if it is set,   \
++	     then chose a negative offset that is going to make bit N and  \
++	     all the bits below it become zero in the remainder part.	   \
++									   \
++	     The SIGN_MAG_LOW_ADDR_BITS macro below implements this,	   \
++	     with respect to sign-magnitude addressing (i.e. separate	   \
++	     +- bit, or 1's complement), used in most cases of ARM	   \
++	     load/store instructions.  */				   \
++									   \
++	  if (coproc_p)							   \
++	    {								   \
++	      low = SIGN_MAG_LOW_ADDR_BITS (val, 10);			   \
++									   \
++	      /* NEON quad-word load/stores are made of two double-word	   \
++		 accesses, so the valid index range is reduced by 8.	   \
++		 Treat as 9-bit range if we go over it.  */		   \
++	      if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016) \
++		low = SIGN_MAG_LOW_ADDR_BITS (val, 9);			   \
++	    }								   \
++	  else if (GET_MODE_SIZE (mode) == 8)				   \
++	    {								   \
++	      if (TARGET_LDRD)						   \
++		low = (TARGET_THUMB2					   \
++		       ? SIGN_MAG_LOW_ADDR_BITS (val, 10)		   \
++		       : SIGN_MAG_LOW_ADDR_BITS (val, 8));		   \
++	      else							   \
++		/* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib) \
++		   to access doublewords. The supported load/store offsets \
++		   are -8, -4, and 4, which we try to produce here.  */	   \
++		low = ((val & 0xf) ^ 0x8) - 0x8;			   \
++	    }								   \
++	  else if (GET_MODE_SIZE (mode) < 8)				   \
++	    {								   \
++	      /* NEON element load/stores do not have an offset.  */	   \
++	      if (TARGET_NEON_FP16 && mode == HFmode)			   \
++		break;							   \
++									   \
++	      if (TARGET_THUMB2)					   \
++		{							   \
++		  /* Thumb-2 has an asymmetrical index range of (-256,4096). \
++		     Try the wider 12-bit range first, and re-try if the   \
++		     result is out of range.  */			   \
++		  low = SIGN_MAG_LOW_ADDR_BITS (val, 12);		   \
++		  if (low < -255)					   \
++		    low = SIGN_MAG_LOW_ADDR_BITS (val, 8);		   \
++		}							   \
++	      else							   \
++		{							   \
++		  if (mode == HImode || mode == HFmode)			   \
++		    {							   \
++		      if (arm_arch4)					   \
++			low = SIGN_MAG_LOW_ADDR_BITS (val, 8);		   \
++		      else						   \
++			{						   \
++			  /* The storehi/movhi_bytes fallbacks can use	   \
++			     only [-4094,+4094] of the full ldrb/strb	   \
++			     index range.  */				   \
++			  low = SIGN_MAG_LOW_ADDR_BITS (val, 12);	   \
++			  if (low == 4095 || low == -4095)		   \
++			    break;					   \
++			}						   \
++		    }							   \
++		  else							   \
++		    low = SIGN_MAG_LOW_ADDR_BITS (val, 12);		   \
++		}							   \
++	    }								   \
+ 	  else								   \
+ 	    break;							   \
+ 									   \
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-04-28 16:13:24 +0000
++++ new/gcc/config/arm/arm.md	2011-07-12 16:35:20 +0000
+@@ -6167,7 +6167,7 @@
+   [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
+    (match_operand:DF 1 "s_register_operand" "r")
+    (match_operand:SI 2 "s_register_operand" "=&r")]
+-  "TARGET_32BIT"
++  "TARGET_THUMB2"
+   "
+   {
+     enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99525.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99525.patch
new file mode 100644
index 0000000000..560a830bfe
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99525.patch
@@ -0,0 +1,67 @@
+2011-07-15  Michael Hope  <michael.hope@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-05  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* ifcvt.c (cond_exec_process_insns): Disallow converting a block
+	that contains the prologue.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-04-01  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* gcc.c-torture/compile/20110401-1.c: New test.
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c	2011-05-05 14:28:53 +0000
++++ new/gcc/ifcvt.c	2011-07-11 04:08:33 +0000
+@@ -1,5 +1,6 @@
+ /* If-conversion support.
+-   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
++   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010,
++   2011
+    Free Software Foundation, Inc.
+ 
+    This file is part of GCC.
+@@ -311,6 +312,10 @@
+ 
+   for (insn = start; ; insn = NEXT_INSN (insn))
+     {
++      /* dwarf2out can't cope with conditional prologues.  */
++      if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
++	return FALSE;
++
+       if (NOTE_P (insn) || DEBUG_INSN_P (insn))
+ 	goto insn_done;
+ 
+
+=== added file 'gcc/testsuite/gcc.c-torture/compile/20110401-1.c'
+--- old/gcc/testsuite/gcc.c-torture/compile/20110401-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/compile/20110401-1.c	2011-07-11 04:08:33 +0000
+@@ -0,0 +1,22 @@
++void asn1_length_der (unsigned long int len, unsigned char *ans, int *ans_len)
++{
++    int k;
++    unsigned char temp[4];
++    if (len < 128) {
++	if (ans != ((void *) 0))
++	    ans[0] = (unsigned char) len;
++	*ans_len = 1;
++    } else {
++	k = 0;
++	while (len) {
++	    temp[k++] = len & 0xFF;
++	    len = len >> 8;
++	}
++	*ans_len = k + 1;
++	if (ans != ((void *) 0)) {
++	    ans[0] = ((unsigned char) k & 0x7F) + 128;
++	    while (k--)
++		ans[*ans_len - 1 - k] = temp[k];
++	}
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99528.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99528.patch
new file mode 100644
index 0000000000..8743583065
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99528.patch
@@ -0,0 +1,138 @@
+2011-07-19  Revital Eres  <revital.eres@linaro.org>
+
+	Backport from mainline -r175090
+	gcc/
+	* ddg.c (add_intra_loop_mem_dep): New function.
+	(build_intra_loop_deps): Call it.
+
+	gcc/testsuite
+	* gcc.dg/sms-9.c: New file.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-05-13 16:16:22 +0000
++++ new/gcc/ddg.c	2011-07-05 09:02:18 +0000
+@@ -352,6 +352,33 @@
+ }
+ 
+ 
++/* Given two nodes, analyze their RTL insns and add intra-loop mem deps
++   to ddg G.  */
++static void
++add_intra_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
++{
++
++  if ((from->cuid == to->cuid)
++      || !insn_alias_sets_conflict_p (from->insn, to->insn))
++    /* Do not create edge if memory references have disjoint alias sets
++       or 'to' and 'from' are the same instruction.  */
++    return;
++
++  if (mem_write_insn_p (from->insn))
++    {
++      if (mem_read_insn_p (to->insn))
++	create_ddg_dep_no_link (g, from, to,
++				DEBUG_INSN_P (to->insn)
++				? ANTI_DEP : TRUE_DEP, MEM_DEP, 0);
++      else
++	create_ddg_dep_no_link (g, from, to,
++				DEBUG_INSN_P (to->insn)
++				? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 0);
++    }
++  else if (!mem_read_insn_p (to->insn))
++    create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 0);
++}
++
+ /* Given two nodes, analyze their RTL insns and add inter-loop mem deps
+    to ddg G.  */
+ static void
+@@ -439,10 +466,22 @@
+ 	      if (DEBUG_INSN_P (j_node->insn))
+ 		continue;
+ 	      if (mem_access_insn_p (j_node->insn))
+- 		/* Don't bother calculating inter-loop dep if an intra-loop dep
+-		   already exists.  */
++		{
++		  /* Don't bother calculating inter-loop dep if an intra-loop dep
++		     already exists.  */
+ 	      	  if (! TEST_BIT (dest_node->successors, j))
+ 		    add_inter_loop_mem_dep (g, dest_node, j_node);
++		  /* If -fmodulo-sched-allow-regmoves
++		     is set certain anti-dep edges are not created.
++		     It might be that these anti-dep edges are on the
++		     path from one memory instruction to another such that
++		     removing these edges could cause a violation of the
++		     memory dependencies.  Thus we add intra edges between
++		     every two memory instructions in this case.  */
++		  if (flag_modulo_sched_allow_regmoves
++		      && !TEST_BIT (dest_node->predecessors, j))
++		    add_intra_loop_mem_dep (g, j_node, dest_node);
++		}
+             }
+         }
+     }
+
+=== added file 'gcc/testsuite/gcc.dg/sms-9.c'
+--- old/gcc/testsuite/gcc.dg/sms-9.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/sms-9.c	2011-07-04 11:13:26 +0000
+@@ -0,0 +1,60 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fmodulo-sched -fno-auto-inc-dec -O2 -fmodulo-sched-allow-regmoves" } */
++
++#include <stdlib.h>
++#include <stdarg.h>
++
++struct df_ref_info
++{
++  unsigned int *begin;
++  unsigned int *count;
++};
++
++extern void *memset (void *s, int c, __SIZE_TYPE__ n);
++
++
++__attribute__ ((noinline))
++     int
++     df_reorganize_refs_by_reg_by_insn (struct df_ref_info *ref_info,
++					int num, unsigned int start)
++{
++  unsigned int m = num;
++  unsigned int offset = 77;
++  unsigned int r;
++
++  for (r = start; r < m; r++)
++    {
++      ref_info->begin[r] = offset;
++      offset += ref_info->count[r];
++      ref_info->count[r] = 0;
++    }
++
++  return offset;
++}
++
++int
++main ()
++{
++  struct df_ref_info temp;
++  int num = 100;
++  unsigned int start = 5;
++  int i, offset;
++
++  temp.begin = malloc (100 * sizeof (unsigned int));
++  temp.count = malloc (100 * sizeof (unsigned int));
++
++  memset (temp.begin, 0, sizeof (unsigned int) * num);
++  memset (temp.count, 0, sizeof (unsigned int) * num);
++
++  for (i = 0; i < num; i++)
++    temp.count[i] = i + 1;
++
++  offset = df_reorganize_refs_by_reg_by_insn (&temp, num, start);
++
++  if (offset != 5112)
++    abort ();
++
++  free (temp.begin);
++  free (temp.count);
++  return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99529.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99529.patch
new file mode 100644
index 0000000000..f0f6a94324
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99529.patch
@@ -0,0 +1,741 @@
+2011-07-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	PR middle-end/49736
+	* expr.c (all_zeros_p): Undo bogus part of last change.
+
+2011-07-21  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	Backport from mainline:
+	gcc/cp/
+	2011-07-13  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* typeck2.c (split_nonconstant_init_1): Pass the initializer directly,
+	rather than a pointer to it.  Return true if the whole of the value
+	was initialized by the generated statements.  Use
+	complete_ctor_at_level_p instead of count_type_elements.
+
+	gcc/
+	2011-07-13  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree.h (categorize_ctor_elements): Remove comment.  Fix long line.
+	(count_type_elements): Delete.
+	(complete_ctor_at_level_p): Declare.
+	* expr.c (flexible_array_member_p): New function, split out from...
+	(count_type_elements): ...here.  Make static.  Replace allow_flexarr
+	parameter with for_ctor_p.  When for_ctor_p is true, return the
+	number of elements that should appear in the top-level constructor,
+	otherwise return an estimate of the number of scalars.
+	(categorize_ctor_elements): Replace p_must_clear with p_complete.
+	(categorize_ctor_elements_1): Likewise.  Use complete_ctor_at_level_p.
+	(complete_ctor_at_level_p): New function, borrowing union logic
+	from old categorize_ctor_elements_1.
+	(mostly_zeros_p): Return true if the constructor is not complete.
+	(all_zeros_p): Update call to categorize_ctor_elements.
+	* gimplify.c (gimplify_init_constructor): Update call to
+	categorize_ctor_elements.  Don't call count_type_elements.
+	Unconditionally prevent clearing for variable-sized types,
+	otherwise rely on categorize_ctor_elements to detect
+	incomplete initializers.
+
+	gcc/testsuite/
+	2011-07-13  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* gcc.target/arm/pr48183.c: New test.
+
+=== modified file 'gcc/cp/typeck2.c'
+--- old/gcc/cp/typeck2.c	2010-07-30 14:05:57 +0000
++++ new/gcc/cp/typeck2.c	2011-07-13 13:36:36 +0000
+@@ -546,18 +546,20 @@
+ 
+ 
+ /* The recursive part of split_nonconstant_init.  DEST is an lvalue
+-   expression to which INIT should be assigned.  INIT is a CONSTRUCTOR.  */
++   expression to which INIT should be assigned.  INIT is a CONSTRUCTOR.
++   Return true if the whole of the value was initialized by the
++   generated statements.  */
+ 
+-static void
+-split_nonconstant_init_1 (tree dest, tree *initp)
++static bool
++split_nonconstant_init_1 (tree dest, tree init)
+ {
+   unsigned HOST_WIDE_INT idx;
+-  tree init = *initp;
+   tree field_index, value;
+   tree type = TREE_TYPE (dest);
+   tree inner_type = NULL;
+   bool array_type_p = false;
+-  HOST_WIDE_INT num_type_elements, num_initialized_elements;
++  bool complete_p = true;
++  HOST_WIDE_INT num_split_elts = 0;
+ 
+   switch (TREE_CODE (type))
+     {
+@@ -569,7 +571,6 @@
+     case RECORD_TYPE:
+     case UNION_TYPE:
+     case QUAL_UNION_TYPE:
+-      num_initialized_elements = 0;
+       FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx,
+ 				field_index, value)
+ 	{
+@@ -592,13 +593,14 @@
+ 		sub = build3 (COMPONENT_REF, inner_type, dest, field_index,
+ 			      NULL_TREE);
+ 
+-	      split_nonconstant_init_1 (sub, &value);
++	      if (!split_nonconstant_init_1 (sub, value))
++		complete_p = false;
++	      num_split_elts++;
+ 	    }
+ 	  else if (!initializer_constant_valid_p (value, inner_type))
+ 	    {
+ 	      tree code;
+ 	      tree sub;
+-	      HOST_WIDE_INT inner_elements;
+ 
+ 	      /* FIXME: Ordered removal is O(1) so the whole function is
+ 		 worst-case quadratic. This could be fixed using an aside
+@@ -622,21 +624,9 @@
+ 	      code = build_stmt (input_location, EXPR_STMT, code);
+ 	      add_stmt (code);
+ 
+-	      inner_elements = count_type_elements (inner_type, true);
+-	      if (inner_elements < 0)
+-		num_initialized_elements = -1;
+-	      else if (num_initialized_elements >= 0)
+-		num_initialized_elements += inner_elements;
+-	      continue;
++	      num_split_elts++;
+ 	    }
+ 	}
+-
+-      num_type_elements = count_type_elements (type, true);
+-      /* If all elements of the initializer are non-constant and
+-	 have been split out, we don't need the empty CONSTRUCTOR.  */
+-      if (num_type_elements > 0
+-	  && num_type_elements == num_initialized_elements)
+-	*initp = NULL;
+       break;
+ 
+     case VECTOR_TYPE:
+@@ -648,6 +638,7 @@
+ 	  code = build2 (MODIFY_EXPR, type, dest, cons);
+ 	  code = build_stmt (input_location, EXPR_STMT, code);
+ 	  add_stmt (code);
++	  num_split_elts += CONSTRUCTOR_NELTS (init);
+ 	}
+       break;
+ 
+@@ -657,6 +648,8 @@
+ 
+   /* The rest of the initializer is now a constant. */
+   TREE_CONSTANT (init) = 1;
++  return complete_p && complete_ctor_at_level_p (TREE_TYPE (init),
++						 num_split_elts, inner_type);
+ }
+ 
+ /* A subroutine of store_init_value.  Splits non-constant static
+@@ -672,7 +665,8 @@
+   if (TREE_CODE (init) == CONSTRUCTOR)
+     {
+       code = push_stmt_list ();
+-      split_nonconstant_init_1 (dest, &init);
++      if (split_nonconstant_init_1 (dest, init))
++	init = NULL_TREE;
+       code = pop_stmt_list (code);
+       DECL_INITIAL (dest) = init;
+       TREE_READONLY (dest) = 0;
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2011-04-20 10:07:36 +0000
++++ new/gcc/expr.c	2011-07-14 11:52:06 +0000
+@@ -4860,16 +4860,136 @@
+   return NULL_RTX;
+ }
+ 
++/* Return true if field F of structure TYPE is a flexible array.  */
++
++static bool
++flexible_array_member_p (const_tree f, const_tree type)
++{
++  const_tree tf;
++
++  tf = TREE_TYPE (f);
++  return (TREE_CHAIN (f) == NULL
++	  && TREE_CODE (tf) == ARRAY_TYPE
++	  && TYPE_DOMAIN (tf)
++	  && TYPE_MIN_VALUE (TYPE_DOMAIN (tf))
++	  && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf)))
++	  && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf))
++	  && int_size_in_bytes (type) >= 0);
++}
++
++/* If FOR_CTOR_P, return the number of top-level elements that a constructor
++   must have in order for it to completely initialize a value of type TYPE.
++   Return -1 if the number isn't known.
++
++   If !FOR_CTOR_P, return an estimate of the number of scalars in TYPE.  */
++
++static HOST_WIDE_INT
++count_type_elements (const_tree type, bool for_ctor_p)
++{
++  switch (TREE_CODE (type))
++    {
++    case ARRAY_TYPE:
++      {
++	tree nelts;
++
++	nelts = array_type_nelts (type);
++	if (nelts && host_integerp (nelts, 1))
++	  {
++	    unsigned HOST_WIDE_INT n;
++
++	    n = tree_low_cst (nelts, 1) + 1;
++	    if (n == 0 || for_ctor_p)
++	      return n;
++	    else
++	      return n * count_type_elements (TREE_TYPE (type), false);
++	  }
++	return for_ctor_p ? -1 : 1;
++      }
++
++    case RECORD_TYPE:
++      {
++	unsigned HOST_WIDE_INT n;
++	tree f;
++
++	n = 0;
++	for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
++	  if (TREE_CODE (f) == FIELD_DECL)
++	    {
++	      if (!for_ctor_p)
++		n += count_type_elements (TREE_TYPE (f), false);
++	      else if (!flexible_array_member_p (f, type))
++		/* Don't count flexible arrays, which are not supposed
++		   to be initialized.  */
++		n += 1;
++	    }
++
++	return n;
++      }
++
++    case UNION_TYPE:
++    case QUAL_UNION_TYPE:
++      {
++	tree f;
++	HOST_WIDE_INT n, m;
++
++	gcc_assert (!for_ctor_p);
++	/* Estimate the number of scalars in each field and pick the
++	   maximum.  Other estimates would do instead; the idea is simply
++	   to make sure that the estimate is not sensitive to the ordering
++	   of the fields.  */
++	n = 1;
++	for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
++	  if (TREE_CODE (f) == FIELD_DECL)
++	    {
++	      m = count_type_elements (TREE_TYPE (f), false);
++	      /* If the field doesn't span the whole union, add an extra
++		 scalar for the rest.  */
++	      if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (f)),
++				    TYPE_SIZE (type)) != 1)
++		m++;
++	      if (n < m)
++		n = m;
++	    }
++	return n;
++      }
++
++    case COMPLEX_TYPE:
++      return 2;
++
++    case VECTOR_TYPE:
++      return TYPE_VECTOR_SUBPARTS (type);
++
++    case INTEGER_TYPE:
++    case REAL_TYPE:
++    case FIXED_POINT_TYPE:
++    case ENUMERAL_TYPE:
++    case BOOLEAN_TYPE:
++    case POINTER_TYPE:
++    case OFFSET_TYPE:
++    case REFERENCE_TYPE:
++      return 1;
++
++    case ERROR_MARK:
++      return 0;
++
++    case VOID_TYPE:
++    case METHOD_TYPE:
++    case FUNCTION_TYPE:
++    case LANG_TYPE:
++    default:
++      gcc_unreachable ();
++    }
++}
++
+ /* Helper for categorize_ctor_elements.  Identical interface.  */
+ 
+ static bool
+ categorize_ctor_elements_1 (const_tree ctor, HOST_WIDE_INT *p_nz_elts,
+-			    HOST_WIDE_INT *p_elt_count,
+-			    bool *p_must_clear)
++			    HOST_WIDE_INT *p_init_elts, bool *p_complete)
+ {
+   unsigned HOST_WIDE_INT idx;
+-  HOST_WIDE_INT nz_elts, elt_count;
+-  tree value, purpose;
++  HOST_WIDE_INT nz_elts, init_elts, num_fields;
++  tree value, purpose, elt_type;
+ 
+   /* Whether CTOR is a valid constant initializer, in accordance with what
+      initializer_constant_valid_p does.  If inferred from the constructor
+@@ -4878,7 +4998,9 @@
+   bool const_p = const_from_elts_p ? true : TREE_STATIC (ctor);
+ 
+   nz_elts = 0;
+-  elt_count = 0;
++  init_elts = 0;
++  num_fields = 0;
++  elt_type = NULL_TREE;
+ 
+   FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), idx, purpose, value)
+     {
+@@ -4894,6 +5016,8 @@
+ 	    mult = (tree_low_cst (hi_index, 1)
+ 		    - tree_low_cst (lo_index, 1) + 1);
+ 	}
++      num_fields += mult;
++      elt_type = TREE_TYPE (value);
+ 
+       switch (TREE_CODE (value))
+ 	{
+@@ -4901,11 +5025,11 @@
+ 	  {
+ 	    HOST_WIDE_INT nz = 0, ic = 0;
+ 
+-	    bool const_elt_p
+-	      = categorize_ctor_elements_1 (value, &nz, &ic, p_must_clear);
++	    bool const_elt_p = categorize_ctor_elements_1 (value, &nz, &ic,
++							   p_complete);
+ 
+ 	    nz_elts += mult * nz;
+- 	    elt_count += mult * ic;
++ 	    init_elts += mult * ic;
+ 
+ 	    if (const_from_elts_p && const_p)
+ 	      const_p = const_elt_p;
+@@ -4917,12 +5041,12 @@
+ 	case FIXED_CST:
+ 	  if (!initializer_zerop (value))
+ 	    nz_elts += mult;
+-	  elt_count += mult;
++	  init_elts += mult;
+ 	  break;
+ 
+ 	case STRING_CST:
+ 	  nz_elts += mult * TREE_STRING_LENGTH (value);
+-	  elt_count += mult * TREE_STRING_LENGTH (value);
++	  init_elts += mult * TREE_STRING_LENGTH (value);
+ 	  break;
+ 
+ 	case COMPLEX_CST:
+@@ -4930,7 +5054,7 @@
+ 	    nz_elts += mult;
+ 	  if (!initializer_zerop (TREE_IMAGPART (value)))
+ 	    nz_elts += mult;
+-	  elt_count += mult;
++	  init_elts += mult;
+ 	  break;
+ 
+ 	case VECTOR_CST:
+@@ -4940,60 +5064,31 @@
+ 	      {
+ 		if (!initializer_zerop (TREE_VALUE (v)))
+ 		  nz_elts += mult;
+-		elt_count += mult;
++		init_elts += mult;
+ 	      }
+ 	  }
+ 	  break;
+ 
+ 	default:
+-	  nz_elts += mult;
+-	  elt_count += mult;
++	  {
++	    HOST_WIDE_INT tc = count_type_elements (elt_type, false);
++	    nz_elts += mult * tc;
++	    init_elts += mult * tc;
+ 
+-	  if (const_from_elts_p && const_p)
+-	    const_p = initializer_constant_valid_p (value, TREE_TYPE (value))
+-		      != NULL_TREE;
++	    if (const_from_elts_p && const_p)
++	      const_p = initializer_constant_valid_p (value, elt_type)
++			!= NULL_TREE;
++	  }
+ 	  break;
+ 	}
+     }
+ 
+-  if (!*p_must_clear
+-      && (TREE_CODE (TREE_TYPE (ctor)) == UNION_TYPE
+-	  || TREE_CODE (TREE_TYPE (ctor)) == QUAL_UNION_TYPE))
+-    {
+-      tree init_sub_type;
+-      bool clear_this = true;
+-
+-      if (!VEC_empty (constructor_elt, CONSTRUCTOR_ELTS (ctor)))
+-	{
+-	  /* We don't expect more than one element of the union to be
+-	     initialized.  Not sure what we should do otherwise... */
+-          gcc_assert (VEC_length (constructor_elt, CONSTRUCTOR_ELTS (ctor))
+-		      == 1);
+-
+-          init_sub_type = TREE_TYPE (VEC_index (constructor_elt,
+-						CONSTRUCTOR_ELTS (ctor),
+-						0)->value);
+-
+-	  /* ??? We could look at each element of the union, and find the
+-	     largest element.  Which would avoid comparing the size of the
+-	     initialized element against any tail padding in the union.
+-	     Doesn't seem worth the effort...  */
+-	  if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (ctor)),
+-				TYPE_SIZE (init_sub_type)) == 1)
+-	    {
+-	      /* And now we have to find out if the element itself is fully
+-		 constructed.  E.g. for union { struct { int a, b; } s; } u
+-		 = { .s = { .a = 1 } }.  */
+-	      if (elt_count == count_type_elements (init_sub_type, false))
+-		clear_this = false;
+-	    }
+-	}
+-
+-      *p_must_clear = clear_this;
+-    }
++  if (*p_complete && !complete_ctor_at_level_p (TREE_TYPE (ctor),
++						num_fields, elt_type))
++    *p_complete = false;
+ 
+   *p_nz_elts += nz_elts;
+-  *p_elt_count += elt_count;
++  *p_init_elts += init_elts;
+ 
+   return const_p;
+ }
+@@ -5003,111 +5098,50 @@
+      and place it in *P_NZ_ELTS;
+    * how many scalar fields in total are in CTOR,
+      and place it in *P_ELT_COUNT.
+-   * if a type is a union, and the initializer from the constructor
+-     is not the largest element in the union, then set *p_must_clear.
++   * whether the constructor is complete -- in the sense that every
++     meaningful byte is explicitly given a value --
++     and place it in *P_COMPLETE.
+ 
+    Return whether or not CTOR is a valid static constant initializer, the same
+    as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0".  */
+ 
+ bool
+ categorize_ctor_elements (const_tree ctor, HOST_WIDE_INT *p_nz_elts,
+-			  HOST_WIDE_INT *p_elt_count,
+-			  bool *p_must_clear)
++			  HOST_WIDE_INT *p_init_elts, bool *p_complete)
+ {
+   *p_nz_elts = 0;
+-  *p_elt_count = 0;
+-  *p_must_clear = false;
++  *p_init_elts = 0;
++  *p_complete = true;
+ 
+-  return
+-    categorize_ctor_elements_1 (ctor, p_nz_elts, p_elt_count, p_must_clear);
++  return categorize_ctor_elements_1 (ctor, p_nz_elts, p_init_elts, p_complete);
+ }
+ 
+-/* Count the number of scalars in TYPE.  Return -1 on overflow or
+-   variable-sized.  If ALLOW_FLEXARR is true, don't count flexible
+-   array member at the end of the structure.  */
++/* TYPE is initialized by a constructor with NUM_ELTS elements, the last
++   of which had type LAST_TYPE.  Each element was itself a complete
++   initializer, in the sense that every meaningful byte was explicitly
++   given a value.  Return true if the same is true for the constructor
++   as a whole.  */
+ 
+-HOST_WIDE_INT
+-count_type_elements (const_tree type, bool allow_flexarr)
++bool
++complete_ctor_at_level_p (const_tree type, HOST_WIDE_INT num_elts,
++			  const_tree last_type)
+ {
+-  const HOST_WIDE_INT max = ~((HOST_WIDE_INT)1 << (HOST_BITS_PER_WIDE_INT-1));
+-  switch (TREE_CODE (type))
++  if (TREE_CODE (type) == UNION_TYPE
++      || TREE_CODE (type) == QUAL_UNION_TYPE)
+     {
+-    case ARRAY_TYPE:
+-      {
+-	tree telts = array_type_nelts (type);
+-	if (telts && host_integerp (telts, 1))
+-	  {
+-	    HOST_WIDE_INT n = tree_low_cst (telts, 1) + 1;
+-	    HOST_WIDE_INT m = count_type_elements (TREE_TYPE (type), false);
+-	    if (n == 0)
+-	      return 0;
+-	    else if (max / n > m)
+-	      return n * m;
+-	  }
+-	return -1;
+-      }
+-
+-    case RECORD_TYPE:
+-      {
+-	HOST_WIDE_INT n = 0, t;
+-	tree f;
+-
+-	for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
+-	  if (TREE_CODE (f) == FIELD_DECL)
+-	    {
+-	      t = count_type_elements (TREE_TYPE (f), false);
+-	      if (t < 0)
+-		{
+-		  /* Check for structures with flexible array member.  */
+-		  tree tf = TREE_TYPE (f);
+-		  if (allow_flexarr
+-		      && TREE_CHAIN (f) == NULL
+-		      && TREE_CODE (tf) == ARRAY_TYPE
+-		      && TYPE_DOMAIN (tf)
+-		      && TYPE_MIN_VALUE (TYPE_DOMAIN (tf))
+-		      && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf)))
+-		      && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf))
+-		      && int_size_in_bytes (type) >= 0)
+-		    break;
+-
+-		  return -1;
+-		}
+-	      n += t;
+-	    }
+-
+-	return n;
+-      }
+-
+-    case UNION_TYPE:
+-    case QUAL_UNION_TYPE:
+-      return -1;
+-
+-    case COMPLEX_TYPE:
+-      return 2;
+-
+-    case VECTOR_TYPE:
+-      return TYPE_VECTOR_SUBPARTS (type);
+-
+-    case INTEGER_TYPE:
+-    case REAL_TYPE:
+-    case FIXED_POINT_TYPE:
+-    case ENUMERAL_TYPE:
+-    case BOOLEAN_TYPE:
+-    case POINTER_TYPE:
+-    case OFFSET_TYPE:
+-    case REFERENCE_TYPE:
+-      return 1;
+-
+-    case ERROR_MARK:
+-      return 0;
+-
+-    case VOID_TYPE:
+-    case METHOD_TYPE:
+-    case FUNCTION_TYPE:
+-    case LANG_TYPE:
+-    default:
+-      gcc_unreachable ();
++      if (num_elts == 0)
++	return false;
++
++      gcc_assert (num_elts == 1 && last_type);
++
++      /* ??? We could look at each element of the union, and find the
++	 largest element.  Which would avoid comparing the size of the
++	 initialized element against any tail padding in the union.
++	 Doesn't seem worth the effort...  */
++      return simple_cst_equal (TYPE_SIZE (type), TYPE_SIZE (last_type)) == 1;
+     }
++
++  return count_type_elements (type, true) == num_elts;
+ }
+ 
+ /* Return 1 if EXP contains mostly (3/4)  zeros.  */
+@@ -5116,18 +5150,12 @@
+ mostly_zeros_p (const_tree exp)
+ {
+   if (TREE_CODE (exp) == CONSTRUCTOR)
+-
+     {
+-      HOST_WIDE_INT nz_elts, count, elts;
+-      bool must_clear;
+-
+-      categorize_ctor_elements (exp, &nz_elts, &count, &must_clear);
+-      if (must_clear)
+-	return 1;
+-
+-      elts = count_type_elements (TREE_TYPE (exp), false);
+-
+-      return nz_elts < elts / 4;
++      HOST_WIDE_INT nz_elts, init_elts;
++      bool complete_p;
++
++      categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p);
++      return !complete_p || nz_elts < init_elts / 4;
+     }
+ 
+   return initializer_zerop (exp);
+@@ -5139,12 +5167,11 @@
+ all_zeros_p (const_tree exp)
+ {
+   if (TREE_CODE (exp) == CONSTRUCTOR)
+-
+     {
+-      HOST_WIDE_INT nz_elts, count;
+-      bool must_clear;
++      HOST_WIDE_INT nz_elts, init_elts;
++      bool complete_p;
+ 
+-      categorize_ctor_elements (exp, &nz_elts, &count, &must_clear);
++      categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p);
+       return nz_elts == 0;
+     }
+ 
+
+=== modified file 'gcc/gimplify.c'
+--- old/gcc/gimplify.c	2011-04-07 18:27:20 +0000
++++ new/gcc/gimplify.c	2011-07-13 13:36:36 +0000
+@@ -3634,9 +3634,8 @@
+     case ARRAY_TYPE:
+       {
+ 	struct gimplify_init_ctor_preeval_data preeval_data;
+-	HOST_WIDE_INT num_type_elements, num_ctor_elements;
+-	HOST_WIDE_INT num_nonzero_elements;
+-	bool cleared, valid_const_initializer;
++	HOST_WIDE_INT num_ctor_elements, num_nonzero_elements;
++	bool cleared, complete_p, valid_const_initializer;
+ 
+ 	/* Aggregate types must lower constructors to initialization of
+ 	   individual elements.  The exception is that a CONSTRUCTOR node
+@@ -3653,7 +3652,7 @@
+ 	   can only do so if it known to be a valid constant initializer.  */
+ 	valid_const_initializer
+ 	  = categorize_ctor_elements (ctor, &num_nonzero_elements,
+-				      &num_ctor_elements, &cleared);
++				      &num_ctor_elements, &complete_p);
+ 
+ 	/* If a const aggregate variable is being initialized, then it
+ 	   should never be a lose to promote the variable to be static.  */
+@@ -3691,26 +3690,29 @@
+ 	   parts in, then generate code for the non-constant parts.  */
+ 	/* TODO.  There's code in cp/typeck.c to do this.  */
+ 
+-	num_type_elements = count_type_elements (type, true);
++	if (int_size_in_bytes (TREE_TYPE (ctor)) < 0)
++	  /* store_constructor will ignore the clearing of variable-sized
++	     objects.  Initializers for such objects must explicitly set
++	     every field that needs to be set.  */
++	  cleared = false;
++	else if (!complete_p)
++	  /* If the constructor isn't complete, clear the whole object
++	     beforehand.
+ 
+-	/* If count_type_elements could not determine number of type elements
+-	   for a constant-sized object, assume clearing is needed.
+-	   Don't do this for variable-sized objects, as store_constructor
+-	   will ignore the clearing of variable-sized objects.  */
+-	if (num_type_elements < 0 && int_size_in_bytes (type) >= 0)
++	     ??? This ought not to be needed.  For any element not present
++	     in the initializer, we should simply set them to zero.  Except
++	     we'd need to *find* the elements that are not present, and that
++	     requires trickery to avoid quadratic compile-time behavior in
++	     large cases or excessive memory use in small cases.  */
+ 	  cleared = true;
+-	/* If there are "lots" of zeros, then block clear the object first.  */
+-	else if (num_type_elements - num_nonzero_elements
++	else if (num_ctor_elements - num_nonzero_elements
+ 		 > CLEAR_RATIO (optimize_function_for_speed_p (cfun))
+-		 && num_nonzero_elements < num_type_elements/4)
+-	  cleared = true;
+-	/* ??? This bit ought not be needed.  For any element not present
+-	   in the initializer, we should simply set them to zero.  Except
+-	   we'd need to *find* the elements that are not present, and that
+-	   requires trickery to avoid quadratic compile-time behavior in
+-	   large cases or excessive memory use in small cases.  */
+-	else if (num_ctor_elements < num_type_elements)
+-	  cleared = true;
++		 && num_nonzero_elements < num_ctor_elements / 4)
++	  /* If there are "lots" of zeros, it's more efficient to clear
++	     the memory and then set the nonzero elements.  */
++	  cleared = true;
++	else
++	  cleared = false;
+ 
+ 	/* If there are "lots" of initialized elements, and all of them
+ 	   are valid address constants, then the entire initializer can
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr48183.c'
+--- old/gcc/testsuite/gcc.target/arm/pr48183.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr48183.c	2011-07-13 13:36:36 +0000
+@@ -0,0 +1,25 @@
++/* testsuite/gcc.target/arm/pr48183.c */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O -g" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n)
++{
++    unsigned i;
++    int16x4x2_t input;
++    int32x4x2_t mid;
++    int32x4x2_t output;
++
++    for (i = 0; i < n/2; i += 8) {
++        input = vld2_s16(src + i);
++        mid.val[0] = vmovl_s16(input.val[0]);
++        mid.val[1] = vmovl_s16(input.val[1]);
++        output.val[0] = vshlq_n_s32(mid.val[0], 8);
++        output.val[1] = vshlq_n_s32(mid.val[1], 8);
++        vst2q_s32((int32_t *)dst + i, output);
++    }
++}
+
+=== modified file 'gcc/tree.h'
+--- old/gcc/tree.h	2011-04-06 12:29:08 +0000
++++ new/gcc/tree.h	2011-07-13 13:36:36 +0000
+@@ -4361,21 +4361,10 @@
+ 
+ extern VEC(tree,gc) *ctor_to_vec (tree);
+ 
+-/* Examine CTOR to discover:
+-   * how many scalar fields are set to nonzero values,
+-     and place it in *P_NZ_ELTS;
+-   * how many scalar fields in total are in CTOR,
+-     and place it in *P_ELT_COUNT.
+-   * if a type is a union, and the initializer from the constructor
+-     is not the largest element in the union, then set *p_must_clear.
+-
+-   Return whether or not CTOR is a valid static constant initializer, the same
+-   as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0".  */
+-
+-extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, HOST_WIDE_INT *,
+-				      bool *);
+-
+-extern HOST_WIDE_INT count_type_elements (const_tree, bool);
++extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *,
++				      HOST_WIDE_INT *, bool *);
++
++extern bool complete_ctor_at_level_p (const_tree, HOST_WIDE_INT, const_tree);
+ 
+ /* integer_zerop (tree x) is nonzero if X is an integer constant of value 0.  */
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99530.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99530.patch
new file mode 100644
index 0000000000..64d6262d60
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99530.patch
@@ -0,0 +1,27 @@
+2011-07-21  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	gcc/
+	Backport from mainline:
+
+	2011-07-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* regcprop.c (maybe_mode_change): Check HARD_REGNO_MODE_OK.
+
+=== modified file 'gcc/regcprop.c'
+--- old/gcc/regcprop.c	2010-08-05 15:28:47 +0000
++++ new/gcc/regcprop.c	2011-07-21 12:40:44 +0000
+@@ -418,10 +418,9 @@
+ 
+       offset = ((WORDS_BIG_ENDIAN ? wordoffset : 0)
+ 		+ (BYTES_BIG_ENDIAN ? byteoffset : 0));
+-      return gen_rtx_raw_REG (new_mode,
+-			      regno + subreg_regno_offset (regno, orig_mode,
+-							   offset,
+-							   new_mode));
++      regno += subreg_regno_offset (regno, orig_mode, offset, new_mode);
++      if (HARD_REGNO_MODE_OK (regno, new_mode))
++	return gen_rtx_raw_REG (new_mode, regno);
+     }
+   return NULL_RTX;
+ }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99531.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99531.patch
new file mode 100644
index 0000000000..5559dfeda4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99531.patch
@@ -0,0 +1,25 @@
+2011-07-29  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+	Backport only bits marked as [*] from mainline:
+        2010-12-19  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* config/arm/arm.c ([*]arm_legitimate_index_p): Add VFP load/store
+	index range case. Change to SF/DFmode tests to avoid capturing HFmode.
+	(thumb2_legitimate_index_p): Same.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-06-29 10:46:39 +0000
++++ new/gcc/config/arm/arm.c	2011-07-29 15:01:53 +0000
+@@ -5643,8 +5643,8 @@
+ 
+   /* Standard coprocessor addressing modes.  */
+   if (TARGET_HARD_FLOAT
+-      && (TARGET_FPA || TARGET_MAVERICK)
+-      && (GET_MODE_CLASS (mode) == MODE_FLOAT
++      && (TARGET_FPA || TARGET_MAVERICK || TARGET_VFP)
++      && ((mode == SFmode || mode == DFmode)
+ 	  || (TARGET_MAVERICK && mode == DImode)))
+     return (code == CONST_INT && INTVAL (index) < 1024
+ 	    && INTVAL (index) > -1024
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99532.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99532.patch
new file mode 100644
index 0000000000..0c2c02b6fb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99532.patch
@@ -0,0 +1,456 @@
+2011-08-03  Revital Eres  <revital.eres@linaro.org>
+
+	* modulo-sched.c (calculate_stage_count,
+	calculate_must_precede_follow, get_sched_window,
+	try_scheduling_node_in_cycle, remove_node_from_ps): Add
+	declaration.
+	(update_node_sched_params, set_must_precede_follow, optimize_sc):
+	New functions.
+	(reset_sched_times): Call update_node_sched_params.
+	(sms_schedule): Call optimize_sc.
+	(get_sched_window): Change function arguments.
+	(sms_schedule_by_order): Update call to get_sched_window.
+	Call set_must_precede_follow.
+	(calculate_stage_count): Add function argument.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-07-04 11:39:09 +0000
++++ new/gcc/modulo-sched.c	2011-08-03 12:20:38 +0000
+@@ -202,7 +202,16 @@
+                                     rtx, rtx);
+ static void duplicate_insns_of_cycles (partial_schedule_ptr,
+ 				       int, int, int, rtx);
+-static int calculate_stage_count (partial_schedule_ptr ps);
++static int calculate_stage_count (partial_schedule_ptr, int);
++static void calculate_must_precede_follow (ddg_node_ptr, int, int,
++					   int, int, sbitmap, sbitmap, sbitmap);
++static int get_sched_window (partial_schedule_ptr, ddg_node_ptr, 
++			     sbitmap, int, int *, int *, int *);
++static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
++					  int, int, sbitmap, int *, sbitmap,
++					  sbitmap);
++static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
++
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+ #define SCHED_FIRST_REG_MOVE(x) \
+@@ -576,6 +585,36 @@
+     }
+ }
+ 
++/* Update the sched_params (time, row and stage) for node U using the II,
++   the CYCLE of U and MIN_CYCLE.  
++   We're not simply taking the following
++   SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
++   because the stages may not be aligned on cycle 0.  */
++static void
++update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle)
++{
++  int sc_until_cycle_zero;
++  int stage;
++
++  SCHED_TIME (u) = cycle;
++  SCHED_ROW (u) = SMODULO (cycle, ii);
++
++  /* The calculation of stage count is done adding the number
++     of stages before cycle zero and after cycle zero.  */
++  sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
++
++  if (SCHED_TIME (u) < 0)
++    {
++      stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
++      SCHED_STAGE (u) = sc_until_cycle_zero - stage;
++    }
++  else
++    {
++      stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
++      SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
++    }
++}
++
+ /* Bump the SCHED_TIMEs of all nodes by AMOUNT.  Set the values of
+    SCHED_ROW and SCHED_STAGE.  */
+ static void
+@@ -591,7 +630,6 @@
+ 	ddg_node_ptr u = crr_insn->node;
+ 	int normalized_time = SCHED_TIME (u) - amount;
+ 	int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
+-        int sc_until_cycle_zero, stage;
+ 
+         if (dump_file)
+           {
+@@ -607,23 +645,9 @@
+ 	
+ 	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+ 	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+-	SCHED_TIME (u) = normalized_time;
+-	SCHED_ROW (u) = SMODULO (normalized_time, ii);
+-      
+-        /* The calculation of stage count is done adding the number
+-           of stages before cycle zero and after cycle zero.  */
+-	sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
+-	
+-	if (SCHED_TIME (u) < 0)
+-	  {
+-	    stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
+-	    SCHED_STAGE (u) = sc_until_cycle_zero - stage;
+-	  }
+-	else
+-	  {
+-	    stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
+-	    SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
+-	  }
++
++	crr_insn->cycle = normalized_time;
++	update_node_sched_params (u, ii, normalized_time, new_min_cycle);
+       }
+ }
+  
+@@ -660,6 +684,206 @@
+ 			    PREV_INSN (last));
+ }
+ 
++/* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE
++   respectively only if cycle C falls on the border of the scheduling
++   window boundaries marked by START and END cycles.  STEP is the
++   direction of the window.  */
++static inline void
++set_must_precede_follow (sbitmap *tmp_follow, sbitmap must_follow,
++			 sbitmap *tmp_precede, sbitmap must_precede, int c,
++			 int start, int end, int step)
++{
++  *tmp_precede = NULL;
++  *tmp_follow = NULL;
++
++  if (c == start)
++    {
++      if (step == 1)
++	*tmp_precede = must_precede;
++      else			/* step == -1.  */
++	*tmp_follow = must_follow;
++    }
++  if (c == end - step)
++    {
++      if (step == 1)
++	*tmp_follow = must_follow;
++      else			/* step == -1.  */
++	*tmp_precede = must_precede;
++    }
++
++}
++
++/* Return True if the branch can be moved to row ii-1 while
++   normalizing the partial schedule PS to start from cycle zero and thus
++   optimize the SC.  Otherwise return False.  */
++static bool
++optimize_sc (partial_schedule_ptr ps, ddg_ptr g)
++{
++  int amount = PS_MIN_CYCLE (ps);
++  sbitmap sched_nodes = sbitmap_alloc (g->num_nodes);
++  int start, end, step;
++  int ii = ps->ii;
++  bool ok = false;
++  int stage_count, stage_count_curr;
++
++  /* Compare the SC after normalization and SC after bringing the branch
++     to row ii-1.  If they are equal just bail out.  */
++  stage_count = calculate_stage_count (ps, amount);
++  stage_count_curr =
++    calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1));
++
++  if (stage_count == stage_count_curr)
++    {
++      if (dump_file)
++	fprintf (dump_file, "SMS SC already optimized.\n");
++
++      ok = false;
++      goto clear;
++    }
++
++  if (dump_file)
++    {
++      fprintf (dump_file, "SMS Trying to optimize branch location\n");
++      fprintf (dump_file, "SMS partial schedule before trial:\n");
++      print_partial_schedule (ps, dump_file);
++    }
++
++  /* First, normalize the partial scheduling.  */
++  reset_sched_times (ps, amount);
++  rotate_partial_schedule (ps, amount);
++  if (dump_file)
++    {
++      fprintf (dump_file,
++	       "SMS partial schedule after normalization (ii, %d, SC %d):\n",
++	       ii, stage_count);
++      print_partial_schedule (ps, dump_file);
++    }
++
++  if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1)
++    {
++      ok = true;
++      goto clear;
++    }
++
++  sbitmap_ones (sched_nodes);
++
++  /* Calculate the new placement of the branch.  It should be in row
++     ii-1 and fall into it's scheduling window.  */
++  if (get_sched_window (ps, g->closing_branch, sched_nodes, ii, &start,
++			&step, &end) == 0)
++    {
++      bool success;
++      ps_insn_ptr next_ps_i;
++      int branch_cycle = SCHED_TIME (g->closing_branch);
++      int row = SMODULO (branch_cycle, ps->ii);
++      int num_splits = 0;
++      sbitmap must_precede, must_follow, tmp_precede, tmp_follow;
++      int c;
++
++      if (dump_file)
++	fprintf (dump_file, "\nTrying to schedule node %d "
++		 "INSN = %d  in (%d .. %d) step %d\n",
++		 g->closing_branch->cuid,
++		 (INSN_UID (g->closing_branch->insn)), start, end, step);
++
++      gcc_assert ((step > 0 && start < end) || (step < 0 && start > end));
++      if (step == 1)
++	{
++	  c = start + ii - SMODULO (start, ii) - 1;
++	  gcc_assert (c >= start);
++	  if (c >= end)
++	    {
++	      ok = false;
++	      if (dump_file)
++		fprintf (dump_file,
++			 "SMS failed to schedule branch at cycle: %d\n", c);
++	      goto clear;
++	    }
++	}
++      else
++	{
++	  c = start - SMODULO (start, ii) - 1;
++	  gcc_assert (c <= start);
++
++	  if (c <= end)
++	    {
++	      if (dump_file)
++		fprintf (dump_file,
++			 "SMS failed to schedule branch at cycle: %d\n", c);
++	      ok = false;
++	      goto clear;
++	    }
++	}
++
++      must_precede = sbitmap_alloc (g->num_nodes);
++      must_follow = sbitmap_alloc (g->num_nodes);
++
++      /* Try to schedule the branch is it's new cycle.  */
++      calculate_must_precede_follow (g->closing_branch, start, end,
++				     step, ii, sched_nodes,
++				     must_precede, must_follow);
++
++      set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
++			       must_precede, c, start, end, step);
++
++      /* Find the element in the partial schedule related to the closing
++         branch so we can remove it from it's current cycle.  */
++      for (next_ps_i = ps->rows[row];
++	   next_ps_i; next_ps_i = next_ps_i->next_in_row)
++	if (next_ps_i->node->cuid == g->closing_branch->cuid)
++	  break;
++
++      gcc_assert (next_ps_i);
++      gcc_assert (remove_node_from_ps (ps, next_ps_i));
++      success =
++	try_scheduling_node_in_cycle (ps, g->closing_branch,
++				      g->closing_branch->cuid, c,
++				      sched_nodes, &num_splits,
++				      tmp_precede, tmp_follow);
++      gcc_assert (num_splits == 0);
++      if (!success)
++	{
++	  if (dump_file)
++	    fprintf (dump_file,
++		     "SMS failed to schedule branch at cycle: %d, "
++		     "bringing it back to cycle %d\n", c, branch_cycle);
++
++	  /* The branch was failed to be placed in row ii - 1.
++	     Put it back in it's original place in the partial
++	     schedualing.  */
++	  set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
++				   must_precede, branch_cycle, start, end,
++				   step);
++	  success =
++	    try_scheduling_node_in_cycle (ps, g->closing_branch,
++					  g->closing_branch->cuid,
++					  branch_cycle, sched_nodes,
++					  &num_splits, tmp_precede,
++					  tmp_follow);
++	  gcc_assert (success && (num_splits == 0));
++	  ok = false;
++	}
++      else
++	{
++	  /* The branch is placed in row ii - 1.  */
++	  if (dump_file)
++	    fprintf (dump_file,
++		     "SMS success in moving branch to cycle %d\n", c);
++
++	  update_node_sched_params (g->closing_branch, ii, c,
++				    PS_MIN_CYCLE (ps));
++	  ok = true;
++	}
++
++      free (must_precede);
++      free (must_follow);
++    }
++
++clear:
++  free (sched_nodes);
++  return ok;
++}
++
+ static void
+ duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
+ 			   int to_stage, int for_prolog, rtx count_reg)
+@@ -1115,6 +1339,7 @@
+       int mii, rec_mii;
+       unsigned stage_count = 0;
+       HOST_WIDEST_INT loop_count = 0;
++      bool opt_sc_p = false;
+ 
+       if (! (g = g_arr[loop->num]))
+         continue;
+@@ -1196,14 +1421,32 @@
+       set_node_sched_params (g);
+ 
+       ps = sms_schedule_by_order (g, mii, maxii, node_order);
+-
+-       if (ps)
+-       {
+-         stage_count = calculate_stage_count (ps);
+-         gcc_assert(stage_count >= 1);
+-         PS_STAGE_COUNT(ps) = stage_count;
+-       }
+-
++      
++      if (ps)
++	{
++	  /* Try to achieve optimized SC by normalizing the partial
++	     schedule (having the cycles start from cycle zero).
++	     The branch location must be placed in row ii-1 in the
++	     final scheduling.	If failed, shift all instructions to
++	     position the branch in row ii-1.  */
++	  opt_sc_p = optimize_sc (ps, g);
++	  if (opt_sc_p)
++	    stage_count = calculate_stage_count (ps, 0);
++	  else
++	    {
++	      /* Bring the branch to cycle ii-1.  */
++	      int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
++	      
++	      if (dump_file)
++		fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
++	      
++	      stage_count = calculate_stage_count (ps, amount);
++	    }
++	  
++	  gcc_assert (stage_count >= 1);
++	  PS_STAGE_COUNT (ps) = stage_count;
++	}
++      
+       /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
+          1 means that there is no interleaving between iterations thus
+          we let the scheduling passes do the job in this case.  */
+@@ -1224,12 +1467,16 @@
+       else
+ 	{
+ 	  struct undo_replace_buff_elem *reg_move_replaces;
+-          int amount = SCHED_TIME (g->closing_branch) + 1;
++
++          if (!opt_sc_p)
++            {
++	      /* Rotate the partial schedule to have the branch in row ii-1.  */
++              int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
++	      
++              reset_sched_times (ps, amount);
++              rotate_partial_schedule (ps, amount);
++            }
+ 	  
+-	  /* Set the stage boundaries.	The closing_branch was scheduled
+-	     and should appear in the last (ii-1) row.  */
+-	  reset_sched_times (ps, amount);
+-	  rotate_partial_schedule (ps, amount);
+ 	  set_columns_for_ps (ps);
+ 
+ 	  canon_loop (loop);
+@@ -1381,13 +1628,11 @@
+    scheduling window is empty and zero otherwise.  */
+ 
+ static int
+-get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
++get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node,
+ 		  sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
+ {
+   int start, step, end;
+   ddg_edge_ptr e;
+-  int u = nodes_order [i];
+-  ddg_node_ptr u_node = &ps->g->nodes[u];
+   sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
+   sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
+   sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
+@@ -1799,7 +2044,7 @@
+ 
+ 	  /* Try to get non-empty scheduling window.  */
+ 	 success = 0;
+-         if (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start,
++         if (get_sched_window (ps, u_node, sched_nodes, ii, &start,
+                                 &step, &end) == 0)
+             {
+               if (dump_file)
+@@ -1816,24 +2061,11 @@
+ 
+               for (c = start; c != end; c += step)
+                 {
+-                  sbitmap tmp_precede = NULL;
+-                  sbitmap tmp_follow = NULL;
+-
+-                  if (c == start)
+-                    {
+-                      if (step == 1)
+-                        tmp_precede = must_precede;
+-                      else      /* step == -1.  */
+-                        tmp_follow = must_follow;
+-                    }
+-                  if (c == end - step)
+-                    {
+-                      if (step == 1)
+-                        tmp_follow = must_follow;
+-                      else      /* step == -1.  */
+-                        tmp_precede = must_precede;
+-                    }
+-
++		  sbitmap tmp_precede, tmp_follow;
++
++                  set_must_precede_follow (&tmp_follow, must_follow, 
++		                           &tmp_precede, must_precede, 
++                                           c, start, end, step);
+                   success =
+                     try_scheduling_node_in_cycle (ps, u_node, u, c,
+                                                   sched_nodes,
+@@ -2893,12 +3125,10 @@
+ }
+ 
+ /* Calculate the stage count of the partial schedule PS.  The calculation
+-   takes into account the rotation to bring the closing branch to row
+-   ii-1.  */
++   takes into account the rotation amount passed in ROTATION_AMOUNT.  */
+ int
+-calculate_stage_count (partial_schedule_ptr ps)
++calculate_stage_count (partial_schedule_ptr ps, int rotation_amount)
+ {
+-  int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
+   int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
+   int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
+   int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99533.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99533.patch
new file mode 100644
index 0000000000..196da9d9d8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99533.patch
@@ -0,0 +1,63 @@
+2011-08-09  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	Backport from trunk -r176970:
+
+	* modulo-sched.c: Change comment.
+	(reset_sched_times): Fix print message.
+	(print_partial_schedule): Add print
+	info.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-08-03 12:20:38 +0000
++++ new/gcc/modulo-sched.c	2011-08-09 04:31:10 +0000
+@@ -84,13 +84,14 @@
+       II cycles (i.e. use register copies to prevent a def from overwriting
+       itself before reaching the use).
+ 
+-    SMS works with countable loops whose loop count can be easily
+-    adjusted.  This is because we peel a constant number of iterations
+-    into a prologue and epilogue for which we want to avoid emitting
+-    the control part, and a kernel which is to iterate that constant
+-    number of iterations less than the original loop.  So the control
+-    part should be a set of insns clearly identified and having its
+-    own iv, not otherwise used in the loop (at-least for now), which
++    SMS works with countable loops (1) whose control part can be easily
++    decoupled from the rest of the loop and (2) whose loop count can
++    be easily adjusted.  This is because we peel a constant number of
++    iterations into a prologue and epilogue for which we want to avoid
++    emitting the control part, and a kernel which is to iterate that
++    constant number of iterations less than the original loop.  So the
++    control part should be a set of insns clearly identified and having
++    its own iv, not otherwise used in the loop (at-least for now), which
+     initializes a register before the loop to the number of iterations.
+     Currently SMS relies on the do-loop pattern to recognize such loops,
+     where (1) the control part comprises of all insns defining and/or
+@@ -636,8 +637,8 @@
+             /* Print the scheduling times after the rotation.  */
+             fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
+                      "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
+-                     INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
+-                     normalized_time);
++                     INSN_UID (crr_insn->node->insn), normalized_time,
++                     new_min_cycle);
+             if (JUMP_P (crr_insn->node->insn))
+               fprintf (dump_file, " (branch)");
+             fprintf (dump_file, "\n");
+@@ -2782,8 +2783,13 @@
+       fprintf (dump, "\n[ROW %d ]: ", i);
+       while (ps_i)
+ 	{
+-	  fprintf (dump, "%d, ",
+-		   INSN_UID (ps_i->node->insn));
++	  if (JUMP_P (ps_i->node->insn))
++	    fprintf (dump, "%d (branch), ",
++		     INSN_UID (ps_i->node->insn));
++	  else
++	    fprintf (dump, "%d, ",
++		     INSN_UID (ps_i->node->insn));
++	
+ 	  ps_i = ps_i->next_in_row;
+ 	}
+     }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99534.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99534.patch
new file mode 100644
index 0000000000..9fa6cf261c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99534.patch
@@ -0,0 +1,39 @@
+2011-08-09  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	Backport from trunk -r176972:
+
+	* ddg.c (create_ddg_dep_from_intra_loop_link): Remove
+	the creation of anti-dep edge from a branch.
+	add_cross_iteration_register_deps):
+	Create anti-dep edge from a branch.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-07-05 09:02:18 +0000
++++ new/gcc/ddg.c	2011-07-31 13:13:38 +0000
+@@ -197,11 +197,6 @@
+         }
+     }
+ 
+-  /* If a true dep edge enters the branch create an anti edge in the
+-     opposite direction to prevent the creation of reg-moves.  */
+-  if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
+-    create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
+-
+    latency = dep_cost (link);
+    e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
+    add_edge_to_ddg (g, e);
+@@ -305,8 +300,11 @@
+ 
+ 	  gcc_assert (first_def_node);
+ 
++         /* Always create the edge if the use node is a branch in
++            order to prevent the creation of reg-moves.  */
+           if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
+-              || !flag_modulo_sched_allow_regmoves)
++              || !flag_modulo_sched_allow_regmoves
++	      || JUMP_P (use_node->insn))
+             create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
+                                     REG_DEP, 1);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99536.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99536.patch
new file mode 100644
index 0000000000..76798ec1cc
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99536.patch
@@ -0,0 +1,33 @@
+2011-08-15  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* config/rs6000/rs6000.c (paired_expand_vector_init): Don't create
+	CONST_VECTORs with symbolic elements.
+	(rs6000_expand_vector_init): Likewise.
+
+=== modified file 'gcc/config/rs6000/rs6000.c'
+--- old/gcc/config/rs6000/rs6000.c	2011-08-11 11:09:07 +0000
++++ new/gcc/config/rs6000/rs6000.c	2011-08-16 12:42:39 +0000
+@@ -4129,7 +4129,9 @@
+   for (i = 0; i < n_elts; ++i)
+     {
+       x = XVECEXP (vals, 0, i);
+-      if (!CONSTANT_P (x))
++      if (!(CONST_INT_P (x)
++	    || GET_CODE (x) == CONST_DOUBLE
++	    || GET_CODE (x) == CONST_FIXED))
+ 	++n_var;
+     }
+   if (n_var == 0)
+@@ -4281,7 +4283,9 @@
+   for (i = 0; i < n_elts; ++i)
+     {
+       x = XVECEXP (vals, 0, i);
+-      if (!CONSTANT_P (x))
++      if (!(CONST_INT_P (x)
++	    || GET_CODE (x) == CONST_DOUBLE
++	    || GET_CODE (x) == CONST_FIXED))
+ 	++n_var, one_var = i;
+       else if (x != CONST0_RTX (inner_mode))
+ 	all_const_zero = false;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99537.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99537.patch
new file mode 100644
index 0000000000..b8584334cf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99537.patch
@@ -0,0 +1,105 @@
+2011-08-16  Matthias Klose  <doko@ubuntu.com>
+
+	Backport from FSF:
+
+	2010-12-20  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/rs6000/freebsd.h (SVR4_ASM_SPEC): Don't define.
+	(DBX_REGISTER_NUMBER): Define.
+	* config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Define.
+	* config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Define.
+	* config/rs6000/sysv4.h (SIZE_TYPE): Define.
+	(ASM_SPEC): Define without using SVR4_ASM_SPEC.
+	(DBX_REGISTER_NUMBER): Undefine.
+	* config.gcc (powerpc-*-eabispe*, powerpc-*-eabisimaltivec*,
+	powerpc-*-eabisim*, powerpc-*-elf*, powerpc-*-eabialtivec*,
+	powerpc-xilinx-eabi*, powerpc-*-eabi*, powerpc-*-rtems*,
+	powerpc-*-linux* | powerpc64-*-linux*, powerpc64-*-gnu*,
+	powerpc-*-gnu-gnualtivec*, powerpc-*-gnu*,
+	powerpc-wrs-vxworks|powerpc-wrs-vxworksae, powerpcle-*-elf*,
+	powerpcle-*-eabisim*, powerpcle-*-eabi*): Don't use svr4.h.
+
+=== modified file 'gcc/config.gcc'
+Index: gcc-4_5-branch/gcc/config.gcc
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config.gcc	2011-09-16 23:01:43.000000000 -0700
++++ gcc-4_5-branch/gcc/config.gcc	2011-09-17 10:54:32.763299018 -0700
+@@ -2028,7 +2028,7 @@ powerpc-*-rtems*)
+ 	tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm"
+ 	;;
+ powerpc-*-linux* | powerpc64-*-linux*)
+-	tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h"
++	tm_file="${tm_file} dbxelf.h elfos.h linux.h freebsd-spec.h rs6000/sysv4.h"
+ 	extra_options="${extra_options} rs6000/sysv4.opt"
+ 	tmake_file="t-dfprules rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"
+ 	maybe_biarch=yes
+Index: gcc-4_5-branch/gcc/config/freebsd-spec.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/freebsd-spec.h	2011-06-16 17:59:03.000000000 -0700
++++ gcc-4_5-branch/gcc/config/freebsd-spec.h	2011-09-17 10:54:32.763299018 -0700
+@@ -154,6 +154,7 @@ is built with the --enable-threads confi
+ #endif
+ 
+ #if defined(HAVE_LD_EH_FRAME_HDR)
++#undef LINK_EH_SPEC
+ #define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+ #endif
+ 
+Index: gcc-4_5-branch/gcc/config/rs6000/linux64.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/linux64.h	2011-09-16 23:01:43.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/linux64.h	2011-09-17 10:56:01.043298999 -0700
+@@ -339,6 +339,9 @@ extern int dot_symbols;
+ 
+ #undef	LINK_OS_DEFAULT_SPEC
+ #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
++#undef LINUX_DYNAMIC_LINKER32
++#undef LINUX_DYNAMIC_LINKER64
++#undef CHOOSE_DYNAMIC_LINKER
+ 
+ #define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld.so.1"
+ #define GLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld64.so.1"
+Index: gcc-4_5-branch/gcc/config/rs6000/sysv4.h
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config/rs6000/sysv4.h	2011-09-16 23:01:44.000000000 -0700
++++ gcc-4_5-branch/gcc/config/rs6000/sysv4.h	2011-09-17 10:54:32.773299018 -0700
+@@ -617,6 +617,7 @@ SVR4_ASM_SPEC \
+ #define CC1_SECURE_PLT_DEFAULT_SPEC ""
+ #endif
+ 
++#undef CC1_SPEC
+ /* Pass -G xxx to the compiler and set correct endian mode.  */
+ #define	CC1_SPEC "%{G*} %(cc1_cpu) \
+ %{mlittle|mlittle-endian: %(cc1_endian_little);           \
+@@ -900,22 +901,13 @@ SVR4_ASM_SPEC \
+ #define LINK_START_LINUX_SPEC ""
+ 
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+-#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+-#if DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
+-#elif DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
+-#else
+-#error "Unsupported DEFAULT_LIBC"
+-#endif
+-#define LINUX_DYNAMIC_LINKER \
+-  CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+ 
+ #define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   %{!dynamic-linker:-dynamic-linker " LINUX_DYNAMIC_LINKER "}}}"
+ 
+ #if defined(HAVE_LD_EH_FRAME_HDR)
++# undef LINK_EH_SPEC
+ # define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+ #endif
+ 
+@@ -1110,6 +1102,7 @@ ncrtn.o%s"
+    be stacked, so that invocations of #pragma pack(pop)' will return
+    to the previous value.  */
+ 
++#undef HANDLE_PRAGMA_PACK_PUSH_POP
+ #define HANDLE_PRAGMA_PACK_PUSH_POP 1
+ 
+ /* Select a format to encode pointers in exception handling data.  CODE
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99540.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99540.patch
new file mode 100644
index 0000000000..b71f6cc5b4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99540.patch
@@ -0,0 +1,23 @@
+2011-08-26  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-08-26  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* df-problems.c (df_note_bb_compute): Pass uses rather than defs
+	to df_set_dead_notes_for_mw.
+
+=== modified file 'gcc/df-problems.c'
+--- old/gcc/df-problems.c	2011-05-05 14:28:53 +0000
++++ new/gcc/df-problems.c	2011-08-26 14:39:38 +0000
+@@ -3562,7 +3562,7 @@
+       while (*mws_rec)
+ 	{
+ 	  struct df_mw_hardreg *mws = *mws_rec;
+-	  if ((DF_MWS_REG_DEF_P (mws))
++	  if (DF_MWS_REG_USE_P (mws)
+ 	      && !df_ignore_stack_reg (mws->start_regno))
+ 	    {
+ 	      bool really_add_notes = debug_insn != 0;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99548.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99548.patch
new file mode 100644
index 0000000000..b78319e8fa
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99548.patch
@@ -0,0 +1,80 @@
+2011-09-22  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	Backport from trunk -r178804:
+	modulo-sched.c (remove_node_from_ps): Return void
+	instead of bool.
+	(optimize_sc): Adjust call to remove_node_from_ps.
+	(sms_schedule): Add print info.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-08-09 04:31:10 +0000
++++ new/gcc/modulo-sched.c	2011-09-22 13:58:43 +0000
+@@ -211,7 +211,7 @@
+ static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
+ 					  int, int, sbitmap, int *, sbitmap,
+ 					  sbitmap);
+-static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
++static void remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
+ 
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+@@ -834,8 +834,7 @@
+ 	if (next_ps_i->node->cuid == g->closing_branch->cuid)
+ 	  break;
+ 
+-      gcc_assert (next_ps_i);
+-      gcc_assert (remove_node_from_ps (ps, next_ps_i));
++      remove_node_from_ps (ps, next_ps_i);
+       success =
+ 	try_scheduling_node_in_cycle (ps, g->closing_branch,
+ 				      g->closing_branch->cuid, c,
+@@ -1485,8 +1484,8 @@
+           if (dump_file)
+             {
+ 	      fprintf (dump_file,
+-		       "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
+-		       stage_count);
++		       "%s:%d SMS succeeded %d %d (with ii, sc)\n",
++		       insn_file (tail), insn_line (tail), ps->ii, stage_count);
+ 	      print_partial_schedule (ps, dump_file);
+ 	    }
+  
+@@ -2810,22 +2809,18 @@
+ }
+ 
+ 
+-/* Removes the given PS_INSN from the partial schedule.  Returns false if the
+-   node is not found in the partial schedule, else returns true.  */
+-static bool
++/* Removes the given PS_INSN from the partial schedule.  */  
++static void 
+ remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i)
+ {
+   int row;
+ 
+-  if (!ps || !ps_i)
+-    return false;
+-
++  gcc_assert (ps && ps_i);
++  
+   row = SMODULO (ps_i->cycle, ps->ii);
+   if (! ps_i->prev_in_row)
+     {
+-      if (ps_i != ps->rows[row])
+-	return false;
+-
++      gcc_assert (ps_i == ps->rows[row]);
+       ps->rows[row] = ps_i->next_in_row;
+       if (ps->rows[row])
+ 	ps->rows[row]->prev_in_row = NULL;
+@@ -2839,7 +2834,7 @@
+    
+   ps->rows_length[row] -= 1; 
+   free (ps_i);
+-  return true;
++  return;
+ }
+ 
+ /* Unlike what literature describes for modulo scheduling (which focuses
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
new file mode 100644
index 0000000000..43617024a1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
@@ -0,0 +1,460 @@
+2011-10-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2010-12-06  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/46771
+	* reginfo.c (init_subregs_of_mode): Don't call find_subregs_of_mode
+	on DEBUG_INSNs.
+
+2011-10-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-22  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/predicates.md (expandable_comparison_operator): New
+	predicate, extracted from...
+	(arm_comparison_operator): ...here.
+	* config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
+	(cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
+	(movdfcc): Use expandable_comparison_operator.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-09-22  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/arm/cmp-1.c: New test.
+	* gcc.target/arm/cmp-2.c: Likewise.
+
+2011-10-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR target/49030
+	* config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
+	* config/arm/arm.c (maybe_get_arm_condition_code): New function,
+	reusing the old code from get_arm_condition_code.  Return ARM_NV
+	for invalid comparison codes.
+	(get_arm_condition_code): Redefine in terms of
+	maybe_get_arm_condition_code.
+	* config/arm/predicates.md (arm_comparison_operator): Use
+	maybe_get_arm_condition_code.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-09-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR target/49030
+	* gcc.dg/torture/pr49030.c: New test.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-09-15 10:06:35 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-10-03 10:09:06 +0000
+@@ -182,6 +182,7 @@
+ #endif
+ extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
+ #ifdef RTX_CODE
++extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
+ extern void thumb1_final_prescan_insn (rtx);
+ extern void thumb2_final_prescan_insn (rtx);
+ extern const char *thumb_load_double_from_address (rtx *);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-09-15 10:06:35 +0000
++++ new/gcc/config/arm/arm.c	2011-10-03 10:09:06 +0000
+@@ -17196,10 +17196,10 @@
+    decremented/zeroed by arm_asm_output_opcode as the insns are output.  */
+ 
+ /* Returns the index of the ARM condition code string in
+-   `arm_condition_codes'.  COMPARISON should be an rtx like
+-   `(eq (...) (...))'.  */
+-static enum arm_cond_code
+-get_arm_condition_code (rtx comparison)
++   `arm_condition_codes', or ARM_NV if the comparison is invalid.
++   COMPARISON should be an rtx like `(eq (...) (...))'.  */
++enum arm_cond_code
++maybe_get_arm_condition_code (rtx comparison)
+ {
+   enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
+   enum arm_cond_code code;
+@@ -17223,11 +17223,11 @@
+     case CC_DLTUmode: code = ARM_CC;
+ 
+     dominance:
+-      gcc_assert (comp_code == EQ || comp_code == NE);
+-
+       if (comp_code == EQ)
+ 	return ARM_INVERSE_CONDITION_CODE (code);
+-      return code;
++      if (comp_code == NE)
++	return code;
++      return ARM_NV;
+ 
+     case CC_NOOVmode:
+       switch (comp_code)
+@@ -17236,7 +17236,7 @@
+ 	case EQ: return ARM_EQ;
+ 	case GE: return ARM_PL;
+ 	case LT: return ARM_MI;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Zmode:
+@@ -17244,7 +17244,7 @@
+ 	{
+ 	case NE: return ARM_NE;
+ 	case EQ: return ARM_EQ;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Nmode:
+@@ -17252,7 +17252,7 @@
+ 	{
+ 	case NE: return ARM_MI;
+ 	case EQ: return ARM_PL;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CCFPEmode:
+@@ -17277,7 +17277,7 @@
+ 	  /* UNEQ and LTGT do not have a representation.  */
+ 	case UNEQ: /* Fall through.  */
+ 	case LTGT: /* Fall through.  */
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_SWPmode:
+@@ -17293,7 +17293,7 @@
+ 	case GTU: return ARM_CC;
+ 	case LEU: return ARM_CS;
+ 	case LTU: return ARM_HI;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Cmode:
+@@ -17301,7 +17301,7 @@
+ 	{
+ 	case LTU: return ARM_CS;
+ 	case GEU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_CZmode:
+@@ -17313,7 +17313,7 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_NCVmode:
+@@ -17323,7 +17323,7 @@
+ 	case LT: return ARM_LT;
+ 	case GEU: return ARM_CS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CCmode:
+@@ -17339,13 +17339,22 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     default: gcc_unreachable ();
+     }
+ }
+ 
++/* Like maybe_get_arm_condition_code, but never return ARM_NV.  */
++static enum arm_cond_code
++get_arm_condition_code (rtx comparison)
++{
++  enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
++  gcc_assert (code != ARM_NV);
++  return code;
++}
++
+ /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
+    instructions.  */
+ void
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-07-12 16:35:20 +0000
++++ new/gcc/config/arm/arm.md	2011-10-03 10:09:55 +0000
+@@ -6428,7 +6428,7 @@
+ 
+ (define_expand "cbranchsi4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:SI 1 "s_register_operand" "")
+ 	        (match_operand:SI 2 "nonmemory_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -6479,7 +6479,7 @@
+ 
+ (define_expand "cbranchsf4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:SF 1 "s_register_operand" "")
+ 	        (match_operand:SF 2 "arm_float_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -6491,7 +6491,7 @@
+ 
+ (define_expand "cbranchdf4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:DF 1 "s_register_operand" "")
+ 	        (match_operand:DF 2 "arm_float_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -6503,7 +6503,7 @@
+ 
+ (define_expand "cbranchdi4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:DI 1 "cmpdi_operand" "")
+ 	        (match_operand:DI 2 "cmpdi_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -7898,7 +7898,7 @@
+ 
+ (define_expand "cstoresi4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:SI 2 "s_register_operand" "")
+ 	  (match_operand:SI 3 "reg_or_int_operand" "")]))]
+   "TARGET_32BIT || TARGET_THUMB1"
+@@ -8034,7 +8034,7 @@
+ 
+ (define_expand "cstoresf4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:SF 2 "s_register_operand" "")
+ 	  (match_operand:SF 3 "arm_float_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -8044,7 +8044,7 @@
+ 
+ (define_expand "cstoredf4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:DF 2 "s_register_operand" "")
+ 	  (match_operand:DF 3 "arm_float_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+@@ -8054,7 +8054,7 @@
+ 
+ (define_expand "cstoredi4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:DI 2 "cmpdi_operand" "")
+ 	  (match_operand:DI 3 "cmpdi_operand" "")]))]
+   "TARGET_32BIT"
+@@ -8174,7 +8174,7 @@
+ 
+ (define_expand "movsicc"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
++	(if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
+ 			 (match_operand:SI 2 "arm_not_operand" "")
+ 			 (match_operand:SI 3 "arm_not_operand" "")))]
+   "TARGET_32BIT"
+@@ -8194,7 +8194,7 @@
+ 
+ (define_expand "movsfcc"
+   [(set (match_operand:SF 0 "s_register_operand" "")
+-	(if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
++	(if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
+ 			 (match_operand:SF 2 "s_register_operand" "")
+ 			 (match_operand:SF 3 "nonmemory_operand" "")))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -8220,7 +8220,7 @@
+ 
+ (define_expand "movdfcc"
+   [(set (match_operand:DF 0 "s_register_operand" "")
+-	(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
++	(if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
+ 			 (match_operand:DF 2 "s_register_operand" "")
+ 			 (match_operand:DF 3 "arm_float_add_operand" "")))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-09-15 10:06:35 +0000
++++ new/gcc/config/arm/predicates.md	2011-10-03 10:09:55 +0000
+@@ -236,11 +236,15 @@
+ 
+ ;; True for integer comparisons and, if FP is active, for comparisons
+ ;; other than LTGT or UNEQ.
++(define_special_predicate "expandable_comparison_operator"
++  (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
++	       unordered,ordered,unlt,unle,unge,ungt"))
++
++;; Likewise, but only accept comparisons that are directly supported
++;; by ARM condition codes.
+ (define_special_predicate "arm_comparison_operator"
+-  (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
+-       (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
+-			 && (TARGET_FPA || TARGET_VFP)")
+-            (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
++  (and (match_operand 0 "expandable_comparison_operator")
++       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
+ 
+ (define_special_predicate "lt_ge_comparison_operator"
+   (match_code "lt,ge"))
+
+=== modified file 'gcc/reginfo.c'
+--- old/gcc/reginfo.c	2011-09-15 10:06:35 +0000
++++ new/gcc/reginfo.c	2011-10-03 10:10:17 +0000
+@@ -1350,7 +1350,7 @@
+ 
+   FOR_EACH_BB (bb)
+     FOR_BB_INSNS (bb, insn)
+-    if (INSN_P (insn))
++    if (NONDEBUG_INSN_P (insn))
+       find_subregs_of_mode (PATTERN (insn));
+ }
+ 
+
+=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49030.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49030.c	2011-10-03 10:09:06 +0000
+@@ -0,0 +1,19 @@
++void
++sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
++		       unsigned long dst_skip)
++{
++  long long y;
++  while (nsamples--)
++    {
++      y = (long long) (*src * 8388608.0f) << 8;
++      if (y > 2147483647) {
++	*(int *) dst = 2147483647;
++      } else if (y < -2147483647 - 1) {
++	*(int *) dst = -2147483647 - 1;
++      } else {
++	*(int *) dst = (int) y;
++      }
++      dst += dst_skip;
++      src++;
++    }
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/cmp-1.c'
+--- old/gcc/testsuite/gcc.target/arm/cmp-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/cmp-1.c	2011-10-03 10:09:55 +0000
+@@ -0,0 +1,37 @@
++/* { dg-do compile } */
++/* { dg-options "-O" } */
++/* { dg-final { scan-assembler-not "\tbl\t" } } */
++/* { dg-final { scan-assembler-not "__aeabi" } } */
++int x, y;
++
++#define TEST_EXPR(NAME, ARGS, EXPR)			\
++  int NAME##1 ARGS { return (EXPR); }			\
++  int NAME##2 ARGS { return !(EXPR); }			\
++  int NAME##3 ARGS { return (EXPR) ? x : y; }		\
++  void NAME##4 ARGS { if (EXPR) x++; }			\
++  void NAME##5 ARGS { if (!(EXPR)) x++; }
++
++#define TEST(NAME, TYPE, OPERATOR) \
++  TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2)	\
++  TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2)	\
++  TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2)	\
++  TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
++  TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100)		\
++  TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
++
++#define TEST_OP(NAME, OPERATOR) \
++  TEST (sc_##NAME, signed char, OPERATOR)		\
++  TEST (uc_##NAME, unsigned char, OPERATOR)		\
++  TEST (ss_##NAME, short, OPERATOR)			\
++  TEST (us_##NAME, unsigned short, OPERATOR)		\
++  TEST (si_##NAME, int, OPERATOR)			\
++  TEST (ui_##NAME, unsigned int, OPERATOR)		\
++  TEST (sll_##NAME, long long, OPERATOR)		\
++  TEST (ull_##NAME, unsigned long long, OPERATOR)
++
++TEST_OP (eq, ==)
++TEST_OP (ne, !=)
++TEST_OP (lt, <)
++TEST_OP (gt, >)
++TEST_OP (le, <=)
++TEST_OP (ge, >=)
+
+=== added file 'gcc/testsuite/gcc.target/arm/cmp-2.c'
+--- old/gcc/testsuite/gcc.target/arm/cmp-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/cmp-2.c	2011-10-03 10:09:55 +0000
+@@ -0,0 +1,49 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
++/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
++/* { dg-final { scan-assembler-not "\tbl\t" } } */
++/* { dg-final { scan-assembler-not "__aeabi" } } */
++int x, y;
++
++#define EQ(X, Y) ((X) == (Y))
++#define NE(X, Y) ((X) != (Y))
++#define LT(X, Y) ((X) < (Y))
++#define GT(X, Y) ((X) > (Y))
++#define LE(X, Y) ((X) <= (Y))
++#define GE(X, Y) ((X) >= (Y))
++
++#define TEST_EXPR(NAME, ARGS, EXPR)			\
++  int NAME##1 ARGS { return (EXPR); }			\
++  int NAME##2 ARGS { return !(EXPR); }			\
++  int NAME##3 ARGS { return (EXPR) ? x : y; }		\
++  void NAME##4 ARGS { if (EXPR) x++; }			\
++  void NAME##5 ARGS { if (!(EXPR)) x++; }
++
++#define TEST(NAME, TYPE, OPERATOR) \
++  TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2))		\
++  TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2))	\
++  TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2))	\
++  TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2))	\
++  TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100))			\
++  TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
++
++#define TEST_OP(NAME, OPERATOR) \
++  TEST (f_##NAME, float, OPERATOR)		\
++  TEST (d_##NAME, double, OPERATOR)		\
++  TEST (ld_##NAME, long double, OPERATOR)
++
++TEST_OP (eq, EQ)
++TEST_OP (ne, NE)
++TEST_OP (lt, LT)
++TEST_OP (gt, GT)
++TEST_OP (le, LE)
++TEST_OP (ge, GE)
++TEST_OP (blt, __builtin_isless)
++TEST_OP (bgt, __builtin_isgreater)
++TEST_OP (ble, __builtin_islessequal)
++TEST_OP (bge, __builtin_isgreaterequal)
++/* This one should be expanded into separate ordered and equality
++   comparisons.  */
++TEST_OP (blg, __builtin_islessgreater)
++TEST_OP (bun, __builtin_isunordered)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/mips64-nomultilib.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/mips64-nomultilib.patch
new file mode 100644
index 0000000000..1ef69f899d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/mips64-nomultilib.patch
@@ -0,0 +1,52 @@
+Index: gcc-4.5/gcc/config/mips/linux64.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/mips/linux64.h	2010-09-25 02:05:05.484423095 -0700
++++ gcc-4.5/gcc/config/mips/linux64.h	2010-09-25 02:31:18.524931014 -0700
+@@ -26,7 +26,7 @@
+   BASE_DRIVER_SELF_SPECS, \
+   LINUX_DRIVER_SELF_SPECS \
+   " %{!EB:%{!EL:%(endian_spec)}}" \
+-  " %{!mabi=*: -mabi=n32}"
++  " %{!mabi=*: -mabi=64}"
+ 
+ #undef LIB_SPEC
+ #define LIB_SPEC "\
+@@ -35,9 +35,9 @@
+ %{!shared: \
+   %{profile:-lc_p} %{!profile:-lc}}"
+ 
+-#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+-#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld.so.1"
+-#define GLIBC_DYNAMIC_LINKERN32 "/lib32/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
++#define GLIBC_DYNAMIC_LINKERN32 "/lib64/ld.so.1"
+ #define UCLIBC_DYNAMIC_LINKERN32 "/lib32/ld-uClibc.so.0"
+ #define LINUX_DYNAMIC_LINKERN32 \
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32)
+Index: gcc-4.5/gcc/config.gcc
+===================================================================
+--- gcc-4.5.orig/gcc/config.gcc	2010-07-22 16:37:17.000000000 -0700
++++ gcc-4.5/gcc/config.gcc	2010-09-25 02:25:41.412414136 -0700
+@@ -1707,7 +1707,7 @@
+ 	*-*-irix6*)
+ 		tm_file="${tm_file} mips/iris6.h"
+ 		tmake_file="${tmake_file} mips/t-iris6"
+-		tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_N32"
++		tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_64"
+ 		case ${target} in
+ 		*-*-irix6.[0-4]*)
+ 			use_gcc_stdint=provide
+Index: gcc-4.5/gcc/config/mips/t-linux64
+===================================================================
+--- gcc-4.5.orig/gcc/config/mips/t-linux64	2010-07-11 16:14:42.000000000 -0700
++++ gcc-4.5/gcc/config/mips/t-linux64	2010-09-25 02:29:52.758708250 -0700
+@@ -18,7 +18,7 @@
+ 
+ MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
+ MULTILIB_DIRNAMES = n32 32 64
+-MULTILIB_OSDIRNAMES = ../lib32 ../lib ../lib64
++MULTILIB_OSDIRNAMES = ../lib64 ../lib32 ../lib
+ 
+ EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/more-epilogues.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/more-epilogues.patch
new file mode 100644
index 0000000000..64f1cf3751
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/more-epilogues.patch
@@ -0,0 +1,83 @@
+Index: a/gcc/cfgcleanup.c
+===================================================================
+--- a/gcc/cfgcleanup.c	(revision 315947)
++++ b/gcc/cfgcleanup.c	(working copy)
+@@ -1179,13 +1179,19 @@ flow_find_head_matching_sequence (basic_
+ 
+   while (true)
+     {
+-
+-      /* Ignore notes.  */
++      /* Ignore notes, except NOTE_INSN_EPILOGUE_BEG.  */
+       while (!NONDEBUG_INSN_P (i1) && i1 != BB_END (bb1))
+-	i1 = NEXT_INSN (i1);
+-
++	{
++	  if (NOTE_P (i1) && NOTE_KIND (i1) == NOTE_INSN_EPILOGUE_BEG)
++	    break;
++	  i1 = NEXT_INSN (i1);
++	}
+       while (!NONDEBUG_INSN_P (i2) && i2 != BB_END (bb2))
+-	i2 = NEXT_INSN (i2);
++	{
++	  if (NOTE_P (i2) && NOTE_KIND (i2) == NOTE_INSN_EPILOGUE_BEG)
++	    break;
++	  i2 = NEXT_INSN (i2);
++	}
+ 
+       if (NOTE_P (i1) || NOTE_P (i2)
+ 	  || JUMP_P (i1) || JUMP_P (i2))
+Index: a/gcc/cfglayout.c
+===================================================================
+--- a/gcc/cfglayout.c	(revision 315947)
++++ b/gcc/cfglayout.c	(working copy)
+@@ -1295,6 +1295,16 @@ cfg_layout_initialize (unsigned int flag
+       bb->flags |= BB_NON_LOCAL_GOTO_TARGET;
+     }
+ 
++  FOR_EACH_BB (bb)
++    {
++      rtx insn;
++      FOR_BB_INSNS (bb, insn)
++	if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG)
++	  {
++	    bb->flags |= BB_EPILOGUE_BEGIN;
++	    break;
++	  }
++    }
+   cleanup_cfg (CLEANUP_CFGLAYOUT | flags);
+ }
+ 
+Index: a/gcc/basic-block.h
+===================================================================
+--- a/gcc/basic-block.h	(revision 315947)
++++ b/gcc/basic-block.h	(working copy)
+@@ -332,7 +332,11 @@ enum bb_flags
+ 
+   /* Set on blocks that cannot be threaded through.
+      Only used in cfgcleanup.c.  */
+-  BB_NONTHREADABLE_BLOCK = 1 << 11
++  BB_NONTHREADABLE_BLOCK = 1 << 11,
++
++  /* Set on blocks that have a NOTE_INSN_EPILOGUE_BEGIN.
++     Only used in cfglayout mode.  */
++  BB_EPILOGUE_BEGIN = 1 << 12
+ };
+ 
+ /* Dummy flag for convenience in the hot/cold partitioning code.  */
+Index: a/gcc/cfgrtl.c
+===================================================================
+--- a/gcc/cfgrtl.c	(revision 315947)
++++ b/gcc/cfgrtl.c	(working copy)
+@@ -2707,7 +2707,10 @@ cfg_layout_can_merge_blocks_p (basic_blo
+ 	     not allow us to redirect an edge by replacing a table jump.  */
+ 	  && (!JUMP_P (BB_END (a))
+ 	      || ((!optimize || reload_completed)
+-		  ? simplejump_p (BB_END (a)) : onlyjump_p (BB_END (a)))));
++		  ? simplejump_p (BB_END (a)) : onlyjump_p (BB_END (a))))
++	  /* Don't separate a NOTE_INSN_EPILOGUE_BEG from its returnjump.  */
++	  && (!(b->flags & BB_EPILOGUE_BEGIN)
++	      || returnjump_p (BB_END (b))));
+ }
+ 
+ /* Merge block A and B.  The blocks must be mergeable.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/optional_libstdc.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/optional_libstdc.patch
new file mode 100644
index 0000000000..0f74353a1f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/optional_libstdc.patch
@@ -0,0 +1,23 @@
+gcc-runtime builds libstdc++ separately from gcc-cross-*. Its configure tests using g++ 
+will not run correctly since my default the linker will try and link against libstdc++
+which shouldn't exist yet. We need an option to disable the automatically added -lstdc++
+option whilst leaving -lc, -lgcc and other automatic library dependencies. This patch 
+adds such an option which only disables the -lstdc++ linkage.
+
+A "standard" gcc build uses xgcc and hence avoids this. We should ask upstream how to 
+do this officially, the likely answer is don't build libstdc++ separately.
+
+RP 29/6/10
+
+Index: gcc-4.3.3/gcc/cp/g++spec.c
+===================================================================
+--- gcc-4.3.3.orig/gcc/cp/g++spec.c	2010-06-29 00:06:03.901695025 +0100
++++ gcc-4.3.3/gcc/cp/g++spec.c	2010-06-29 00:06:58.800325439 +0100
+@@ -131,6 +131,7 @@
+       if (argv[i][0] == '-')
+ 	{
+ 	  if (strcmp (argv[i], "-nostdlib") == 0
++	      || strcmp (argv[i], "-nostdlib++") == 0
+ 	      || strcmp (argv[i], "-nodefaultlibs") == 0)
+ 	    {
+ 	      library = -1;
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr30961.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr30961.dpatch
new file mode 100644
index 0000000000..b20fdf5bf5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr30961.dpatch
@@ -0,0 +1,179 @@
+#! /bin/sh -e
+
+# DP: <your description>
+
+dir=
+if [ $# -eq 3 -a "$2" = '-d' ]; then
+    pdir="-d $3"
+    dir="$3/"
+elif [ $# -ne 1 ]; then
+    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+    exit 1
+fi
+case "$1" in
+    -patch)
+        patch $pdir -f --no-backup-if-mismatch -p0 < $0
+        ;;
+    -unpatch)
+        patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
+        ;;
+    *)
+        echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+        exit 1
+esac
+exit 0
+
+From: "H.J. Lu" <hjl@lucon.org>
+Sender: gcc-patches-owner@gcc.gnu.org
+To: gcc-patches@gcc.gnu.org
+Subject: PATCH: PR target/30961: [4.1/4.2/4.3 regression] redundant reg/mem 	stores/moves
+Date: Mon, 27 Aug 2007 11:34:12 -0700
+
+We start with
+
+(note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG)
+
+(insn:HI 6 3 10 2 c.c:3 (set (reg:DF 58 [ <result> ])
+        (subreg:DF (reg/v:DI 59 [ in ]) 0)) 102 {*movdf_integer_rex64} (expr_list:REG_DEAD (reg/v:DI 59 [ in ])
+        (nil)))
+
+(insn:HI 10 6 16 2 c.c:7 (set (reg/i:DF 21 xmm0 [ <result> ])
+        (reg:DF 58 [ <result> ])) 102 {*movdf_integer_rex64} (expr_list:REG_DEAD (reg:DF 58 [ <result> ])
+        (nil)))
+
+(insn:HI 16 10 0 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil))
+
+we are trying to allocate registers for insn 6 and we allocate
+xmm0 for the return value. Reload doesn't check if xmm0 can be used for
+DF 59, it allocates xmm1 for DF 59 and generates:
+
+Reloads for insn # 6
+Reload 0: reload_in (DF) = (reg:DF 5 di)
+        SSE_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
+        reload_in_reg: (subreg:DF (reg/v:DI 5 di [orig:59 in ] [59]) 0)
+        reload_reg_rtx: (reg:DF 22 xmm1)
+...
+
+(note:HI 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
+
+(note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG)
+
+(insn 22 3 23 2 c.c:3 (set (mem/c:DF (plus:DI (reg/f:DI 7 sp)
+                (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])
+        (reg:DF 5 di)) 102 {*movdf_integer_rex64} (nil))
+
+(insn 23 22 6 2 c.c:3 (set (reg:DF 22 xmm1)
+        (mem/c:DF (plus:DI (reg/f:DI 7 sp)
+                (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])) 102 {*movdf_integer_rex64} (nil))
+
+(insn:HI 6 23 16 2 c.c:3 (set (reg:DF 21 xmm0 [orig:58 <result> ] [58])
+        (reg:DF 22 xmm1)) 102 {*movdf_integer_rex64} (nil))
+
+(insn 16 6 21 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil))
+
+This patch tries to use the destination register when reloading for input. It
+generates
+
+Reloads for insn # 6
+Reload 0: reload_in (DF) = (reg:DF 5 di)
+        SSE_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
+        reload_in_reg: (subreg:DF (reg/v:DI 5 di [orig:59 in ] [59]) 0)
+        reload_reg_rtx: (reg:DF 21 xmm0)
+...
+(note:HI 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
+
+(note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG)
+
+(insn 22 3 23 2 c.c:3 (set (mem/c:DF (plus:DI (reg/f:DI 7 sp)
+                (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])
+        (reg:DF 5 di)) 102 {*movdf_integer_rex64} (nil))
+
+(insn 23 22 6 2 c.c:3 (set (reg:DF 21 xmm0)
+        (mem/c:DF (plus:DI (reg/f:DI 7 sp)
+                (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])) 102 {*movdf_integer_rex64} (nil))
+
+(insn:HI 6 23 10 2 c.c:3 (set (reg:DF 22 xmm1 [orig:58 <result> ] [58])
+        (reg:DF 21 xmm0)) 102 {*movdf_integer_rex64} (nil))
+
+(insn:HI 10 6 16 2 c.c:7 (set (reg/i:DF 21 xmm0 [ <result> ])
+        (reg:DF 22 xmm1 [orig:58 <result> ] [58])) 102 {*movdf_integer_rex64} (nil))
+
+(insn 16 10 21 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil))
+
+
+H.J.
+----
+gcc/
+
+2007-08-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/30961
+	* reload1.c (find_reg): Favor the hard register in destination
+	if it is usable and a memory location is needed for reload
+	input.
+
+gcc/testsuite/
+
+2007-08-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/30961
+	* gcc.target/i386/pr30961-1.c: New.
+
+--- gcc/reload1.c.second	2007-08-27 09:35:08.000000000 -0700
++++ gcc/reload1.c	2007-08-27 09:36:33.000000000 -0700
+@@ -1781,6 +1781,20 @@ find_reg (struct insn_chain *chain, int 
+   HARD_REG_SET not_usable;
+   HARD_REG_SET used_by_other_reload;
+   reg_set_iterator rsi;
++#ifdef SECONDARY_MEMORY_NEEDED
++  rtx body = PATTERN (chain->insn);
++  unsigned int dest_reg = FIRST_PSEUDO_REGISTER;
++
++  if (GET_CODE (body) == SET)
++    {
++      rtx dest = SET_DEST (body);
++
++      if ((REG_P (dest)
++	   || (GET_CODE (dest) == SUBREG
++	       && REG_P (SUBREG_REG (dest)))))
++	dest_reg = reg_or_subregno (dest);
++    }
++#endif
+ 
+   COPY_HARD_REG_SET (not_usable, bad_spill_regs);
+   IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
+@@ -1821,6 +1835,18 @@ find_reg (struct insn_chain *chain, int 
+ 	    this_cost--;
+ 	  if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
+ 	    this_cost--;
++#ifdef SECONDARY_MEMORY_NEEDED
++	  /* If a memory location is needed for rl->in and dest_reg
++	     is usable, we will favor it.  */
++	  else if (dest_reg == regno
++		   && rl->in
++		   && REG_P (rl->in)
++		   && REGNO (rl->in) < FIRST_PSEUDO_REGISTER
++		   && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (rl->in)),
++					       rl->class,
++					       rl->mode))
++	    this_cost = 0;
++#endif
+ 	  if (this_cost < best_cost
+ 	      /* Among registers with equal cost, prefer caller-saved ones, or
+ 		 use REG_ALLOC_ORDER if it is defined.  */
+--- gcc/testsuite/gcc.target/i386/pr30961-1.c.second	2007-08-27 11:01:59.000000000 -0700
++++ gcc/testsuite/gcc.target/i386/pr30961-1.c	2007-08-27 11:02:51.000000000 -0700
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target lp64 } */
++/* { dg-options "-O2" } */
++
++double
++convert (long long in)
++{
++  double f;
++  __builtin_memcpy( &f, &in, sizeof( in ) );
++  return f;
++}
++
++/* { dg-final { scan-assembler-not "movapd" } } */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr35942.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr35942.patch
new file mode 100644
index 0000000000..da610f5189
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr35942.patch
@@ -0,0 +1,38 @@
+Fix PR 35942: remove -lstdc++ from libtool postdeps for CXX.
+
+libstdc++-v3/ChangeLog:
+2010-01-04  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
+
+	PR libstdc++/35942
+	* configure.ac: Remove -lstdc++ from libtool's postdeps_CXX.
+	* configure: Regenerate.
+
+
+Index: gcc-4.3.3/libstdc++-v3/configure
+===================================================================
+--- gcc-4.3.3.orig/libstdc++-v3/configure	2010-03-26 17:57:51.000000000 +0000
++++ gcc-4.3.3/libstdc++-v3/configure	2010-03-26 17:57:58.000000000 +0000
+@@ -13759,6 +13759,9 @@
+ 
+ 
+ 
++# Eliminate -lstdc++ addition to postdeps for cross compiles.
++postdeps_CXX=`echo " $postdeps_CXX " | sed 's, -lstdc++ ,,g'`
++
+ # Possibly disable most of the library.
+ ## TODO: Consider skipping unncessary tests altogether in this case, rather
+ ## than just ignoring the results.  Faster /and/ more correct, win win.
+Index: gcc-4.3.3/libstdc++-v3/configure.ac
+===================================================================
+--- gcc-4.3.3.orig/libstdc++-v3/configure.ac	2010-03-26 17:57:54.000000000 +0000
++++ gcc-4.3.3/libstdc++-v3/configure.ac	2010-03-26 17:57:58.000000000 +0000
+@@ -89,6 +89,9 @@
+ AC_SUBST(enable_shared)
+ AC_SUBST(enable_static)
+ 
++# Eliminate -lstdc++ addition to postdeps for cross compiles.
++postdeps_CXX=`echo " $postdeps_CXX " | sed 's, -lstdc++ ,,g'`
++
+ # Possibly disable most of the library.
+ ## TODO: Consider skipping unncessary tests altogether in this case, rather
+ ## than just ignoring the results.  Faster /and/ more correct, win win.
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/sh4-multilib.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/sh4-multilib.patch
new file mode 100644
index 0000000000..c895c95e12
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/sh4-multilib.patch
@@ -0,0 +1,25 @@
+# DP: Fix multilib (m4/m4-nofpu) for sh4-linux
+
+---
+ a/gcc/config.gcc |    5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+Index: gcc-4_5-branch/gcc/config.gcc
+===================================================================
+--- gcc-4_5-branch.orig/gcc/config.gcc	2010-12-23 00:33:39.000000000 -0800
++++ gcc-4_5-branch/gcc/config.gcc	2011-01-09 02:57:36.608656002 -0800
+@@ -2321,11 +2321,12 @@
+ 	if test "$sh_multilibs" = "default" ; then
+ 		case ${target} in
+ 		sh64-superh-linux* | \
+-		sh[1234]*)	sh_multilibs=${sh_cpu_target} ;;
+ 		sh64* | sh5*)	sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
+-		sh-superh-*)	sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
++		sh-superh-* | \
++		sh4-*-linux*)	sh_multilibs=m4,m4-nofpu ;;
+ 		sh*-*-linux*)	sh_multilibs=m1,m3e,m4 ;;
+ 		sh*-*-netbsd*)	sh_multilibs=m3,m3e,m4 ;;
++		sh-superh-*)	sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
+ 		*) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ 		esac
+ 		if test x$with_fp = xno; then
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/use-defaults.h-and-t-oe-in-B.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/use-defaults.h-and-t-oe-in-B.patch
new file mode 100644
index 0000000000..c93e6caa06
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/use-defaults.h-and-t-oe-in-B.patch
@@ -0,0 +1,57 @@
+Upstream-Status: Pending
+
+Use the defaults.h in ${B} instead of ${S}, and t-oe in ${B}, so that
+the source can be shared between gcc-cross-initial,
+gcc-cross-intermediate, gcc-cross, gcc-runtime, and also the sdk build.
+---
+ gcc/Makefile.in  |    2 +-
+ gcc/configure    |    4 ++--
+ gcc/configure.ac |    4 ++--
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/Makefile.in b/gcc/Makefile.in
+index d91f93a..03ee2bd 100644
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -461,7 +461,7 @@ LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h ]
+ TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@
+ 
+ xmake_file=@xmake_file@
+-tmake_file=@tmake_file@
++tmake_file=@tmake_file@ ./t-oe
+ TM_ENDIAN_CONFIG=@TM_ENDIAN_CONFIG@
+ TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@
+ TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@
+diff --git a/gcc/configure b/gcc/configure
+index f440fa2..dafb0c1 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -10838,8 +10838,8 @@ for f in $tm_file; do
+        tm_include_list="${tm_include_list} $f"
+        ;;
+     defaults.h )
+-       tm_file_list="${tm_file_list} \$(srcdir)/$f"
+-       tm_include_list="${tm_include_list} $f"
++       tm_file_list="${tm_file_list} ./$f"
++       tm_include_list="${tm_include_list} ./$f"
+        ;;
+     * )
+        tm_file_list="${tm_file_list} \$(srcdir)/config/$f"
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index d003091..ba422e6 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -1652,8 +1652,8 @@ for f in $tm_file; do
+        tm_include_list="${tm_include_list} $f"
+        ;;
+     defaults.h )
+-       tm_file_list="${tm_file_list} \$(srcdir)/$f"
+-       tm_include_list="${tm_include_list} $f"
++       tm_file_list="${tm_file_list} ./$f"
++       tm_include_list="${tm_include_list} ./$f"
+        ;;
+     * )
+        tm_file_list="${tm_file_list} \$(srcdir)/config/$f"
+-- 
+1.7.1
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-no-host-includes.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-no-host-includes.patch
new file mode 100644
index 0000000000..4ccf35f627
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-no-host-includes.patch
@@ -0,0 +1,31 @@
+Index: gcc-4.4+svnr145550/gcc/incpath.c
+===================================================================
+--- gcc-4.4+svnr145550.orig/gcc/incpath.c	2009-04-04 13:48:31.000000000 -0700
++++ gcc-4.4+svnr145550/gcc/incpath.c	2009-04-04 14:49:29.000000000 -0700
+@@ -417,6 +417,26 @@
+   p->construct = 0;
+   p->user_supplied_p = user_supplied_p;
+ 
++#ifdef CROSS_COMPILE
++    /* A common error when cross compiling is including
++    host headers. This code below will try to fail fast
++    for cross compiling. Currently we consider /usr/include,
++    /opt/include and /sw/include as harmful.  */
++	{
++		/* printf("Adding Path: %s\n", p->name ); */
++		if( strstr(p->name, "/usr/include" ) == p->name ) {
++			fprintf(stderr, _("CROSS COMPILE Badness: /usr/include in INCLUDEPATH: %s\n"), p->name);
++			abort();
++		} else if( strstr(p->name, "/sw/include") == p->name ) {
++			fprintf(stderr, _("CROSS COMPILE Badness: /sw/include in INCLUDEPATH: %s\n"), p->name);
++			abort();
++		} else if( strstr(p->name, "/opt/include") == p->name ) {
++			fprintf(stderr, _("CROSS COMPILE Badness: /opt/include in INCLUDEPATH: %s\n"), p->name);
++			abort();
++		 }
++	}
++#endif
++
+   add_cpp_dir_path (p, chain);
+ }
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-xgcc-cpp.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-xgcc-cpp.patch
new file mode 100644
index 0000000000..a7722cbfc4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-xgcc-cpp.patch
@@ -0,0 +1,28 @@
+upstream: n/a
+comment: Use the preprocessor we have just compiled instead the one of
+the system. There might be incompabilities between us and them.
+
+Index: gcc-4.3.1/Makefile.in
+===================================================================
+--- gcc-4.3.1.orig/Makefile.in	2008-08-19 01:09:56.000000000 -0700
++++ gcc-4.3.1/Makefile.in	2008-08-19 01:13:27.000000000 -0700
+@@ -204,6 +204,7 @@
+ 	AR="$(AR_FOR_TARGET)"; export AR; \
+ 	AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \
+ 	CC="$(CC_FOR_TARGET)"; export CC; \
++	CPP="$(CC_FOR_TARGET) -E"; export CPP; \
+ 	CFLAGS="$(CFLAGS_FOR_TARGET) $(SYSROOT_CFLAGS_FOR_TARGET) $(DEBUG_PREFIX_CFLAGS_FOR_TARGET)"; export CFLAGS; \
+ 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
+ 	CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \
+Index: gcc-4.3.1/Makefile.tpl
+===================================================================
+--- gcc-4.3.1.orig/Makefile.tpl	2008-08-21 00:07:58.000000000 -0700
++++ gcc-4.3.1/Makefile.tpl	2008-08-21 00:09:52.000000000 -0700
+@@ -223,6 +223,7 @@
+ 	AR="$(AR_FOR_TARGET)"; export AR; \
+ 	AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \
+ 	CC="$(CC_FOR_TARGET)"; export CC; \
++	CPP="$(CC_FOR_TARGET) -E"; export CPP; \
+ 	CFLAGS="$(CFLAGS_FOR_TARGET) $(SYSROOT_CFLAGS_FOR_TARGET) $(DEBUG_PREFIX_CFLAGS_FOR_TARGET)"; export CFLAGS; \
+ 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
+ 	CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch
new file mode 100644
index 0000000000..ef33afff70
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch
@@ -0,0 +1,45 @@
+Index: gcc-4_6-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.c	2012-03-05 17:14:09.901129286 -0800
++++ gcc-4_6-branch/gcc/config/arm/arm.c	2012-03-05 17:18:23.061141606 -0800
+@@ -17525,6 +17525,13 @@
+       }
+       return;
+ 
++    case 'v':
++      {
++        gcc_assert (GET_CODE (x) == CONST_DOUBLE);
++        fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
++        return;
++      }
++
+     /* Register specifier for vld1.16/vst1.16.  Translate the S register
+        number into a D register number and element index.  */
+     case 'z':
+@@ -24925,4 +24932,26 @@
+   return 4;
+ }
+ 
++int
++vfp3_const_double_for_fract_bits (rtx operand)
++{
++  REAL_VALUE_TYPE r0;
++  
++  if (GET_CODE (operand) != CONST_DOUBLE)
++    return 0;
++  
++  REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
++  if (exact_real_inverse (DFmode, &r0))
++    {
++      if (exact_real_truncate (DFmode, &r0))
++       {
++	 HOST_WIDE_INT value = real_to_integer (&r0);
++	 value = value & 0xffffffff;
++	 if ((value != 0) && ( (value & (value - 1)) == 0))
++	   return int_log2 (value);
++       }
++    }
++  return 0;
++}
++
+ #include "gt-arm.h"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch
new file mode 100644
index 0000000000..4c573f401e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch
@@ -0,0 +1,51 @@
+2011-02-21  Andrew Stubbs  <ams@codesourcery.com>
+	    Julian Brown  <julian@codesourcery.com>
+	    Mark Shinwell  <shinwell@codesourcery.com>
+
+	Forward-ported from Linaro GCC 4.5 (bzr99324).
+
+	gcc/
+	* config/arm/arm.h (arm_class_likely_spilled_p): Check against
+	LO_REGS only for Thumb-1.
+	(MODE_BASE_REG_CLASS): Restrict base registers to those which can
+	be used in short instructions when optimising for size on Thumb-2.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-01-29 03:20:57 +0000
++++ new/gcc/config/arm/arm.c	2011-02-21 14:04:51 +0000
+@@ -22304,14 +22304,16 @@
+ 
+ /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
+  
+-   We need to define this for LO_REGS on thumb.  Otherwise we can end up
+-   using r0-r4 for function arguments, r7 for the stack frame and don't
+-   have enough left over to do doubleword arithmetic.  */
+-
++   We need to define this for LO_REGS on Thumb-1.  Otherwise we can end up
++   using r0-r4 for function arguments, r7 for the stack frame and don't have
++   enough left over to do doubleword arithmetic.  For Thumb-2 all the
++   potentially problematic instructions accept high registers so this is not
++   necessary.  Care needs to be taken to avoid adding new Thumb-2 patterns
++   that require many low registers.  */
+ static bool
+ arm_class_likely_spilled_p (reg_class_t rclass)
+ {
+-  if ((TARGET_THUMB && rclass == LO_REGS)
++  if ((TARGET_THUMB1 && rclass == LO_REGS)
+       || rclass  == CC_REG)
+     return true;
+ 
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-01-29 03:20:57 +0000
++++ new/gcc/config/arm/arm.h	2011-02-21 14:04:51 +0000
+@@ -1185,7 +1185,7 @@
+    when addressing quantities in QI or HI mode; if we don't know the
+    mode, then we must be conservative.  */
+ #define MODE_BASE_REG_CLASS(MODE)					\
+-    (TARGET_32BIT ? CORE_REGS :					\
++    (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS :      \
+      (((MODE) == SImode) ? BASE_REGS : LO_REGS))
+ 
+ /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch
new file mode 100644
index 0000000000..4b0079e1dc
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch
@@ -0,0 +1,653 @@
+2011-03-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* doc/invoke.texi (max-stores-to-sink): Document.
+	* params.h (MAX_STORES_TO_SINK): Define.
+	* opts.c (finish_options): Set MAX_STORES_TO_SINK to 0
+	if either vectorization or if-conversion is disabled.
+	* tree-data-ref.c (dr_equal_offsets_p1): Moved and renamed from
+	tree-vect-data-refs.c vect_equal_offsets.
+	(dr_equal_offsets_p): New function.
+	(find_data_references_in_bb): Remove static.
+	* tree-data-ref.h (find_data_references_in_bb): Declare.
+	(dr_equal_offsets_p): Likewise.
+	* tree-vect-data-refs.c (vect_equal_offsets): Move to tree-data-ref.c.
+	(vect_drs_dependent_in_basic_block): Update calls to
+	vect_equal_offsets.
+	(vect_check_interleaving): Likewise.
+	* tree-ssa-phiopt.c: Include cfgloop.h and tree-data-ref.h.
+	(cond_if_else_store_replacement): Rename to...
+	(cond_if_else_store_replacement_1): ... this.  Change arguments and
+	documentation.
+	(cond_if_else_store_replacement): New function.
+	* Makefile.in (tree-ssa-phiopt.o): Adjust dependencies.
+	* params.def (PARAM_MAX_STORES_TO_SINK): Define.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-cselim-1.c: New test.
+	* gcc.dg/vect/vect-cselim-2.c: New test.
+
+=== modified file 'gcc/Makefile.in'
+--- old/gcc/Makefile.in	2011-03-26 09:20:34 +0000
++++ new/gcc/Makefile.in	2011-04-18 11:31:29 +0000
+@@ -2422,7 +2422,8 @@
+ tree-ssa-phiopt.o : tree-ssa-phiopt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
+    $(TM_H) $(GGC_H) $(TREE_H) $(TM_P_H) $(BASIC_BLOCK_H) \
+    $(TREE_FLOW_H) $(TREE_PASS_H) $(TREE_DUMP_H) langhooks.h $(FLAGS_H) \
+-   $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h
++   $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h $(CFGLOOP_H) \
++   $(TREE_DATA_REF_H)
+ tree-nrv.o : tree-nrv.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
+    $(TM_H) $(TREE_H) $(FUNCTION_H) $(BASIC_BLOCK_H) $(FLAGS_H) \
+    $(DIAGNOSTIC_H) $(TREE_FLOW_H) $(TIMEVAR_H) $(TREE_DUMP_H) $(TREE_PASS_H) \
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2011-03-29 14:24:42 +0000
++++ new/gcc/doc/invoke.texi	2011-04-18 11:31:29 +0000
+@@ -8909,6 +8909,11 @@
+ The maximum number of namespaces to consult for suggestions when C++
+ name lookup fails for an identifier.  The default is 1000.
+ 
++@item max-stores-to-sink
++The maximum number of conditional stores paires that can be sunk.  Set to 0
++if either vectorization (@option{-ftree-vectorize}) or if-conversion
++(@option{-ftree-loop-if-convert}) is disabled.  The default is 2.
++
+ @end table
+ @end table
+ 
+
+=== modified file 'gcc/opts.c'
+--- old/gcc/opts.c	2011-02-17 22:51:57 +0000
++++ new/gcc/opts.c	2011-03-27 09:38:18 +0000
+@@ -823,6 +823,12 @@
+ 	  opts->x_flag_split_stack = 0;
+ 	}
+     }
++
++  /* Set PARAM_MAX_STORES_TO_SINK to 0 if either vectorization or if-conversion
++     is disabled.  */
++  if (!opts->x_flag_tree_vectorize || !opts->x_flag_tree_loop_if_convert)
++    maybe_set_param_value (PARAM_MAX_STORES_TO_SINK, 0,
++                           opts->x_param_values, opts_set->x_param_values);
+ }
+ 
+ #define LEFT_COLUMN	27
+
+=== modified file 'gcc/params.def'
+--- old/gcc/params.def	2011-03-26 09:20:34 +0000
++++ new/gcc/params.def	2011-04-18 11:31:29 +0000
+@@ -883,6 +883,13 @@
+ 	  "name lookup fails",
+ 	  1000, 0, 0)
+ 
++/* Maximum number of conditional store pairs that can be sunk.  */
++DEFPARAM (PARAM_MAX_STORES_TO_SINK,
++          "max-stores-to-sink",
++          "Maximum number of conditional store pairs that can be sunk",
++          2, 0, 0)
++
++
+ /*
+ Local variables:
+ mode:c
+
+=== modified file 'gcc/params.h'
+--- old/gcc/params.h	2011-01-13 13:41:03 +0000
++++ new/gcc/params.h	2011-03-27 09:38:18 +0000
+@@ -206,4 +206,6 @@
+   PARAM_VALUE (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO)
+ #define MIN_NONDEBUG_INSN_UID \
+   PARAM_VALUE (PARAM_MIN_NONDEBUG_INSN_UID)
++#define MAX_STORES_TO_SINK \
++  PARAM_VALUE (PARAM_MAX_STORES_TO_SINK)
+ #endif /* ! GCC_PARAMS_H */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c	2011-03-27 09:38:18 +0000
+@@ -0,0 +1,86 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 50
++
++typedef struct {
++  short a;
++  short b;
++} data;
++
++data in1[N], in2[N], out[N];
++short result[N*2] = {7,-7,9,-6,11,-5,13,-4,15,-3,17,-2,19,-1,21,0,23,1,25,2,27,3,29,4,31,5,33,6,35,7,37,8,39,9,41,10,43,11,45,12,47,13,49,14,51,15,53,16,55,17,57,18,59,19,61,20,63,21,65,22,67,23,69,24,71,25,73,26,75,27,77,28,79,29,81,30,83,31,85,32,87,33,89,34,91,35,93,36,95,37,97,38,99,39,101,40,103,41,105,42};
++short out1[N], out2[N];
++
++__attribute__ ((noinline)) void
++foo ()
++{
++  int i;
++  short c, d;
++
++  /* Vectorizable with conditional store sinking.  */
++  for (i = 0; i < N; i++)
++    {
++      c = in1[i].b;
++      d = in2[i].b;
++
++      if (c >= d)
++        {
++          out[i].b = c;
++          out[i].a = d + 5;
++        }
++      else
++        {
++          out[i].b = d - 12;
++          out[i].a = c + d;
++        }
++    }
++
++  /* Not vectorizable.  */
++  for (i = 0; i < N; i++)
++    {
++      c = in1[i].b;
++      d = in2[i].b;
++
++      if (c >= d)
++        {
++          out1[i] = c;
++        }
++      else
++        {
++          out2[i] = c + d;
++        }
++    }
++}
++
++int
++main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in1[i].a = i;
++      in1[i].b = i + 2;
++      in2[i].a = 5;
++      in2[i].b = i + 5;
++      __asm__ volatile ("");
++    }
++
++  foo ();
++
++  for (i = 0; i < N; i++)
++    {
++      if (out[i].a != result[2*i] || out[i].b != result[2*i+1])
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { vect_no_align || {! vect_strided } } } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c	2011-03-27 09:38:18 +0000
+@@ -0,0 +1,65 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 50
++
++int a[N], b[N], in1[N], in2[N];
++int result[2*N] = {5,-7,7,-6,9,-5,11,-4,13,-3,15,-2,17,-1,19,0,21,1,23,2,25,3,27,4,29,5,31,6,33,7,35,8,37,9,39,10,41,11,43,12,45,13,47,14,49,15,51,16,53,17,55,18,57,19,59,20,61,21,63,22,65,23,67,24,69,25,71,26,73,27,75,28,77,29,79,30,81,31,83,32,85,33,87,34,89,35,91,36,93,37,95,38,97,39,99,40,101,41,103,42};
++
++__attribute__ ((noinline)) void
++foo (int *pa, int *pb)
++{
++  int i;
++  int c, d;
++
++  /* Store sinking should not work here since the pointers may alias.  */
++  for (i = 0; i < N; i++)
++    {
++      c = in1[i];
++      d = in2[i];
++
++      if (c >= d)
++        {
++          *pa = c;
++          *pb = d + 5;
++        }
++      else
++        {
++          *pb = d - 12;
++          *pa = c + d;
++        }
++
++      pa++;
++      pb++;
++    }
++}
++
++int
++main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in1[i] = i;
++      in2[i] = i + 5;
++      __asm__ volatile ("");
++    }
++
++  foo (a, b);
++
++  for (i = 0; i < N; i++)
++    {
++      if (a[i] != result[2*i] || b[i] != result[2*i+1])
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect"  } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/tree-data-ref.c'
+--- old/gcc/tree-data-ref.c	2011-02-05 01:39:20 +0000
++++ new/gcc/tree-data-ref.c	2011-03-27 09:38:18 +0000
+@@ -991,6 +991,48 @@
+   return dr;
+ }
+ 
++/* Check if OFFSET1 and OFFSET2 (DR_OFFSETs of some data-refs) are identical
++   expressions.  */
++static bool
++dr_equal_offsets_p1 (tree offset1, tree offset2)
++{
++  bool res;
++
++  STRIP_NOPS (offset1);
++  STRIP_NOPS (offset2);
++
++  if (offset1 == offset2)
++    return true;
++
++  if (TREE_CODE (offset1) != TREE_CODE (offset2)
++      || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1)))
++    return false;
++
++  res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 0),
++                             TREE_OPERAND (offset2, 0));
++
++  if (!res || !BINARY_CLASS_P (offset1))
++    return res;
++
++  res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 1),
++                             TREE_OPERAND (offset2, 1));
++
++  return res;
++}
++
++/* Check if DRA and DRB have equal offsets.  */
++bool
++dr_equal_offsets_p (struct data_reference *dra,
++                    struct data_reference *drb)
++{
++  tree offset1, offset2;
++
++  offset1 = DR_OFFSET (dra);
++  offset2 = DR_OFFSET (drb);
++
++  return dr_equal_offsets_p1 (offset1, offset2);
++}
++
+ /* Returns true if FNA == FNB.  */
+ 
+ static bool
+@@ -4294,7 +4336,7 @@
+    DATAREFS.  Returns chrec_dont_know when failing to analyze a
+    difficult case, returns NULL_TREE otherwise.  */
+ 
+-static tree
++tree
+ find_data_references_in_bb (struct loop *loop, basic_block bb,
+                             VEC (data_reference_p, heap) **datarefs)
+ {
+
+=== modified file 'gcc/tree-data-ref.h'
+--- old/gcc/tree-data-ref.h	2011-01-25 21:24:23 +0000
++++ new/gcc/tree-data-ref.h	2011-03-27 09:38:18 +0000
+@@ -426,10 +426,14 @@
+ extern void compute_all_dependences (VEC (data_reference_p, heap) *,
+ 				     VEC (ddr_p, heap) **, VEC (loop_p, heap) *,
+ 				     bool);
++extern tree find_data_references_in_bb (struct loop *, basic_block,
++                                        VEC (data_reference_p, heap) **);
+ 
+ extern void create_rdg_vertices (struct graph *, VEC (gimple, heap) *);
+ extern bool dr_may_alias_p (const struct data_reference *,
+ 			    const struct data_reference *);
++extern bool dr_equal_offsets_p (struct data_reference *,
++                                struct data_reference *);
+ 
+ 
+ /* Return true when the base objects of data references A and B are
+
+=== modified file 'gcc/tree-ssa-phiopt.c'
+--- old/gcc/tree-ssa-phiopt.c	2010-11-03 15:18:50 +0000
++++ new/gcc/tree-ssa-phiopt.c	2011-03-27 09:38:18 +0000
+@@ -34,6 +34,8 @@
+ #include "langhooks.h"
+ #include "pointer-set.h"
+ #include "domwalk.h"
++#include "cfgloop.h"
++#include "tree-data-ref.h"
+ 
+ static unsigned int tree_ssa_phiopt (void);
+ static unsigned int tree_ssa_phiopt_worker (bool);
+@@ -1292,35 +1294,18 @@
+   return true;
+ }
+ 
+-/* Do the main work of conditional store replacement.  We already know
+-   that the recognized pattern looks like so:
+-
+-   split:
+-     if (cond) goto THEN_BB; else goto ELSE_BB (edge E1)
+-   THEN_BB:
+-     X = Y;
+-     goto JOIN_BB;
+-   ELSE_BB:
+-     X = Z;
+-     fallthrough (edge E0)
+-   JOIN_BB:
+-     some more
+-
+-   We check that THEN_BB and ELSE_BB contain only one store
+-   that the stores have a "simple" RHS.  */
++/* Do the main work of conditional store replacement.  */
+ 
+ static bool
+-cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb,
+-				basic_block join_bb)
++cond_if_else_store_replacement_1 (basic_block then_bb, basic_block else_bb,
++				  basic_block join_bb, gimple then_assign,
++				  gimple else_assign)
+ {
+-  gimple then_assign = last_and_only_stmt (then_bb);
+-  gimple else_assign = last_and_only_stmt (else_bb);
+   tree lhs_base, lhs, then_rhs, else_rhs;
+   source_location then_locus, else_locus;
+   gimple_stmt_iterator gsi;
+   gimple newphi, new_stmt;
+ 
+-  /* Check if then_bb and else_bb contain only one store each.  */
+   if (then_assign == NULL
+       || !gimple_assign_single_p (then_assign)
+       || else_assign == NULL
+@@ -1385,6 +1370,190 @@
+   return true;
+ }
+ 
++/* Conditional store replacement.  We already know
++   that the recognized pattern looks like so:
++
++   split:
++     if (cond) goto THEN_BB; else goto ELSE_BB (edge E1)
++   THEN_BB:
++     ...
++     X = Y;
++     ...
++     goto JOIN_BB;
++   ELSE_BB:
++     ...
++     X = Z;
++     ...
++     fallthrough (edge E0)
++   JOIN_BB:
++     some more
++
++   We check that it is safe to sink the store to JOIN_BB by verifying that
++   there are no read-after-write or write-after-write dependencies in
++   THEN_BB and ELSE_BB.  */
++
++static bool
++cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb,
++                                basic_block join_bb)
++{
++  gimple then_assign = last_and_only_stmt (then_bb);
++  gimple else_assign = last_and_only_stmt (else_bb);
++  VEC (data_reference_p, heap) *then_datarefs, *else_datarefs;
++  VEC (ddr_p, heap) *then_ddrs, *else_ddrs;
++  gimple then_store, else_store;
++  bool found, ok = false, res;
++  struct data_dependence_relation *ddr;
++  data_reference_p then_dr, else_dr;
++  int i, j;
++  tree then_lhs, else_lhs;
++  VEC (gimple, heap) *then_stores, *else_stores;
++  basic_block blocks[3];
++
++  if (MAX_STORES_TO_SINK == 0)
++    return false;
++
++  /* Handle the case with single statement in THEN_BB and ELSE_BB.  */
++  if (then_assign && else_assign)
++    return cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
++                                             then_assign, else_assign);
++
++  /* Find data references.  */
++  then_datarefs = VEC_alloc (data_reference_p, heap, 1);
++  else_datarefs = VEC_alloc (data_reference_p, heap, 1);
++  if ((find_data_references_in_bb (NULL, then_bb, &then_datarefs)
++        == chrec_dont_know)
++      || !VEC_length (data_reference_p, then_datarefs)
++      || (find_data_references_in_bb (NULL, else_bb, &else_datarefs)
++        == chrec_dont_know)
++      || !VEC_length (data_reference_p, else_datarefs))
++    {
++      free_data_refs (then_datarefs);
++      free_data_refs (else_datarefs);
++      return false;
++    }
++
++  /* Find pairs of stores with equal LHS.  */
++  then_stores = VEC_alloc (gimple, heap, 1);
++  else_stores = VEC_alloc (gimple, heap, 1);
++  FOR_EACH_VEC_ELT (data_reference_p, then_datarefs, i, then_dr)
++    {
++      if (DR_IS_READ (then_dr))
++        continue;
++
++      then_store = DR_STMT (then_dr);
++      then_lhs = gimple_assign_lhs (then_store);
++      found = false;
++
++      FOR_EACH_VEC_ELT (data_reference_p, else_datarefs, j, else_dr)
++        {
++          if (DR_IS_READ (else_dr))
++            continue;
++
++          else_store = DR_STMT (else_dr);
++          else_lhs = gimple_assign_lhs (else_store);
++
++          if (operand_equal_p (then_lhs, else_lhs, 0))
++            {
++              found = true;
++              break;
++            }
++        }
++
++      if (!found)
++        continue;
++
++      VEC_safe_push (gimple, heap, then_stores, then_store);
++      VEC_safe_push (gimple, heap, else_stores, else_store);
++    }
++
++  /* No pairs of stores found.  */
++  if (!VEC_length (gimple, then_stores)
++      || VEC_length (gimple, then_stores) > (unsigned) MAX_STORES_TO_SINK)
++    {
++      free_data_refs (then_datarefs);
++      free_data_refs (else_datarefs);
++      VEC_free (gimple, heap, then_stores);
++      VEC_free (gimple, heap, else_stores);
++      return false;
++    }
++
++  /* Compute and check data dependencies in both basic blocks.  */
++  then_ddrs = VEC_alloc (ddr_p, heap, 1);
++  else_ddrs = VEC_alloc (ddr_p, heap, 1);
++  compute_all_dependences (then_datarefs, &then_ddrs, NULL, false);
++  compute_all_dependences (else_datarefs, &else_ddrs, NULL, false);
++  blocks[0] = then_bb;
++  blocks[1] = else_bb;
++  blocks[2] = join_bb;
++  renumber_gimple_stmt_uids_in_blocks (blocks, 3);
++
++  /* Check that there are no read-after-write or write-after-write dependencies
++     in THEN_BB.  */
++  FOR_EACH_VEC_ELT (ddr_p, then_ddrs, i, ddr)
++    {
++      struct data_reference *dra = DDR_A (ddr);
++      struct data_reference *drb = DDR_B (ddr);
++
++      if (DDR_ARE_DEPENDENT (ddr) != chrec_known
++          && ((DR_IS_READ (dra) && DR_IS_WRITE (drb)
++               && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb)))
++              || (DR_IS_READ (drb) && DR_IS_WRITE (dra)
++                  && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra)))
++              || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb))))
++        {
++          free_dependence_relations (then_ddrs);
++          free_dependence_relations (else_ddrs);
++          free_data_refs (then_datarefs);
++          free_data_refs (else_datarefs);
++          VEC_free (gimple, heap, then_stores);
++          VEC_free (gimple, heap, else_stores);
++          return false;
++        }
++    }
++
++  /* Check that there are no read-after-write or write-after-write dependencies
++     in ELSE_BB.  */
++  FOR_EACH_VEC_ELT (ddr_p, else_ddrs, i, ddr)
++    {
++      struct data_reference *dra = DDR_A (ddr);
++      struct data_reference *drb = DDR_B (ddr);
++
++      if (DDR_ARE_DEPENDENT (ddr) != chrec_known
++          && ((DR_IS_READ (dra) && DR_IS_WRITE (drb)
++               && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb)))
++              || (DR_IS_READ (drb) && DR_IS_WRITE (dra)
++                  && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra)))
++              || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb))))
++        {
++          free_dependence_relations (then_ddrs);
++          free_dependence_relations (else_ddrs);
++          free_data_refs (then_datarefs);
++          free_data_refs (else_datarefs);
++          VEC_free (gimple, heap, then_stores);
++          VEC_free (gimple, heap, else_stores);
++          return false;
++        }
++    }
++
++  /* Sink stores with same LHS.  */
++  FOR_EACH_VEC_ELT (gimple, then_stores, i, then_store)
++    {
++      else_store = VEC_index (gimple, else_stores, i);
++      res = cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
++                                              then_store, else_store);
++      ok = ok || res;
++    }
++
++  free_dependence_relations (then_ddrs);
++  free_dependence_relations (else_ddrs);
++  free_data_refs (then_datarefs);
++  free_data_refs (else_datarefs);
++  VEC_free (gimple, heap, then_stores);
++  VEC_free (gimple, heap, else_stores);
++
++  return ok;
++}
++
+ /* Always do these optimizations if we have SSA
+    trees to work on.  */
+ static bool
+
+=== modified file 'gcc/tree-vect-data-refs.c'
+--- old/gcc/tree-vect-data-refs.c	2011-02-25 11:18:14 +0000
++++ new/gcc/tree-vect-data-refs.c	2011-03-27 09:38:18 +0000
+@@ -289,39 +289,6 @@
+     }
+ }
+ 
+-
+-/* Function vect_equal_offsets.
+-
+-   Check if OFFSET1 and OFFSET2 are identical expressions.  */
+-
+-static bool
+-vect_equal_offsets (tree offset1, tree offset2)
+-{
+-  bool res;
+-
+-  STRIP_NOPS (offset1);
+-  STRIP_NOPS (offset2);
+-
+-  if (offset1 == offset2)
+-    return true;
+-
+-  if (TREE_CODE (offset1) != TREE_CODE (offset2)
+-      || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1)))
+-    return false;
+-
+-  res = vect_equal_offsets (TREE_OPERAND (offset1, 0),
+-			    TREE_OPERAND (offset2, 0));
+-
+-  if (!res || !BINARY_CLASS_P (offset1))
+-    return res;
+-
+-  res = vect_equal_offsets (TREE_OPERAND (offset1, 1),
+-			    TREE_OPERAND (offset2, 1));
+-
+-  return res;
+-}
+-
+-
+ /* Check dependence between DRA and DRB for basic block vectorization.
+    If the accesses share same bases and offsets, we can compare their initial
+    constant offsets to decide whether they differ or not.  In case of a read-
+@@ -352,7 +319,7 @@
+            || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
+            || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
+            != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
+-      || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb)))
++      || !dr_equal_offsets_p (dra, drb))
+     return true;
+ 
+   /* Check the types.  */
+@@ -402,7 +369,7 @@
+ 	   || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
+ 	   || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
+ 	   != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
+-      || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb))
++      || !dr_equal_offsets_p (dra, drb)
+       || !tree_int_cst_compare (DR_INIT (dra), DR_INIT (drb))
+       || DR_IS_READ (dra) != DR_IS_READ (drb))
+     return false;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch
new file mode 100644
index 0000000000..017b1df7e3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch
@@ -0,0 +1,126 @@
+2011-04-21  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2008-12-03  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-shift-3.c, gcc.dg/vect/vect-shift-4.c: New.
+	* lib/target-supports.exp (check_effective_target_vect_shift_char): New
+	function.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c	2011-04-21 13:51:06 +0000
+@@ -0,0 +1,37 @@
++/* { dg-require-effective-target vect_shift } */
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++
++#define N 32
++
++unsigned short dst[N] __attribute__((aligned(N)));
++unsigned short src[N] __attribute__((aligned(N)));
++
++__attribute__ ((noinline))
++void array_shift(void)
++{
++  int i;
++  for (i = 0; i < N; i++)
++    dst[i] = src[i] >> 3;
++}
++
++int main()
++{
++  volatile int i;
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    src[i] = i << 3;
++
++  array_shift ();
++
++  for (i = 0; i < N; i++)
++    if (dst[i] != i)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c	2011-04-21 13:51:06 +0000
+@@ -0,0 +1,37 @@
++/* { dg-require-effective-target vect_shift_char } */
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++
++#define N 32
++
++unsigned char dst[N] __attribute__((aligned(N)));
++unsigned char src[N] __attribute__((aligned(N)));
++
++__attribute__ ((noinline))
++void array_shift(void)
++{
++  int i;
++  for (i = 0; i < N; i++)
++    dst[i] = src[i] >> 3;
++}
++
++int main()
++{
++  volatile int i;
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    src[i] = i << 3;
++
++  array_shift ();
++
++  for (i = 0; i < N; i++)
++    if (dst[i] != i)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-02-19 15:31:15 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-04-21 13:51:06 +0000
+@@ -2308,6 +2308,26 @@
+ }
+ 
+ 
++# Return 1 if the target supports hardware vector shift operation for char.
++
++proc check_effective_target_vect_shift_char { } {
++    global et_vect_shift_char_saved
++
++    if [info exists et_vect_shift_char_saved] {
++	verbose "check_effective_target_vect_shift_char: using cached result" 2
++    } else {
++	set et_vect_shift_char_saved 0
++	if { ([istarget powerpc*-*-*]
++             && ![istarget powerpc-*-linux*paired*])
++	     || [check_effective_target_arm32] } {
++	   set et_vect_shift_char_saved 1
++	}
++    }
++
++    verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2
++    return $et_vect_shift_char_saved
++}
++
+ # Return 1 if the target supports hardware vectors of long, 0 otherwise.
+ #
+ # This can change for different subtargets so do not cache the result.
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch
new file mode 100644
index 0000000000..3dde3b29a1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch
@@ -0,0 +1,177 @@
+2011-04-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from FSF:
+
+	2011-04-03  Richard Guenther  <rguenther@suse.de>
+		    Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-if-conv.c (memrefs_read_or_written_unconditionally): Strip all
+	non-variable offsets and compare the remaining bases of the two
+	accesses instead of looking for exact same data-ref.
+
+	gcc/testsuite/
+	* gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: New test.
+	* gcc.dg/vect/vect.exp: Run if-cvt-stores-vect* tests with
+	-ftree-loop-if-convert-stores.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c'
+--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c	2011-04-24 07:45:49 +0000
+@@ -0,0 +1,69 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 50
++
++typedef struct {
++  short a;
++  short b;
++} data;
++
++data in1[N], in2[N], out[N];
++short result[N*2] = {10,-7,11,-6,12,-5,13,-4,14,-3,15,-2,16,-1,17,0,18,1,19,2,20,3,21,4,22,5,23,6,24,7,25,8,26,9,27,10,28,11,29,12,30,13,31,14,32,15,33,16,34,17,35,18,36,19,37,20,38,21,39,22,40,23,41,24,42,25,43,26,44,27,45,28,46,29,47,30,48,31,49,32,50,33,51,34,52,35,53,36,54,37,55,38,56,39,57,40,58,41,59,42};
++short out1[N], out2[N];
++
++__attribute__ ((noinline)) void
++foo ()
++{
++  int i;
++  short c, d;
++
++  for (i = 0; i < N; i++)
++    {
++      c = in1[i].b;
++      d = in2[i].b;
++
++      if (c >= d)
++        {
++          out[i].b = in1[i].a;
++          out[i].a = d + 5;
++        }
++      else
++        {
++          out[i].b = d - 12;
++          out[i].a = in2[i].a + d;
++        }
++    }
++}
++
++int
++main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in1[i].a = i;
++      in1[i].b = i + 2;
++      in2[i].a = 5;
++      in2[i].b = i + 5;
++      __asm__ volatile ("");
++    }
++
++  foo ();
++
++  for (i = 0; i < N; i++)
++    {
++      if (out[i].a != result[2*i] || out[i].b != result[2*i+1])
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { vect_no_align || {! vect_strided } } } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
+--- old/gcc/testsuite/gcc.dg/vect/vect.exp	2010-11-22 21:49:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect.exp	2011-04-24 07:45:49 +0000
+@@ -210,6 +210,12 @@
+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/ggc-*.\[cS\]]]  \
+         "" $DEFAULT_VECTCFLAGS
+ 
++# -ftree-loop-if-convert-stores
++set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
++lappend DEFAULT_VECTCFLAGS "-ftree-loop-if-convert-stores"
++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/if-cvt-stores-vect-*.\[cS\]]]  \
++        "" $DEFAULT_VECTCFLAGS
++
+ # With -O3.
+ # Don't allow IPA cloning, because it throws our counts out of whack.
+ set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
+
+=== modified file 'gcc/tree-if-conv.c'
+--- old/gcc/tree-if-conv.c	2011-02-23 16:49:52 +0000
++++ new/gcc/tree-if-conv.c	2011-04-24 07:45:49 +0000
+@@ -464,8 +464,8 @@
+ /* Returns true when the memory references of STMT are read or written
+    unconditionally.  In other words, this function returns true when
+    for every data reference A in STMT there exist other accesses to
+-   the same data reference with predicates that add up (OR-up) to the
+-   true predicate: this ensures that the data reference A is touched
++   a data reference with the same base with predicates that add up (OR-up) to
++   the true predicate: this ensures that the data reference A is touched
+    (read or written) on every iteration of the if-converted loop.  */
+ 
+ static bool
+@@ -489,21 +489,38 @@
+ 	  continue;
+ 
+ 	for (j = 0; VEC_iterate (data_reference_p, drs, j, b); j++)
+-	  if (DR_STMT (b) != stmt
+-	      && same_data_refs (a, b))
+-	    {
+-	      tree cb = bb_predicate (gimple_bb (DR_STMT (b)));
+-
+-	      if (DR_RW_UNCONDITIONALLY (b) == 1
+-		  || is_true_predicate (cb)
+-		  || is_true_predicate (ca = fold_or_predicates (EXPR_LOCATION (cb),
+-								 ca, cb)))
+-		{
+-		  DR_RW_UNCONDITIONALLY (a) = 1;
+-		  DR_RW_UNCONDITIONALLY (b) = 1;
+-		  found = true;
+-		  break;
+-		}
++          {
++            tree ref_base_a = DR_REF (a);
++            tree ref_base_b = DR_REF (b);
++
++            if (DR_STMT (b) == stmt)
++              continue;
++
++            while (TREE_CODE (ref_base_a) == COMPONENT_REF
++                   || TREE_CODE (ref_base_a) == IMAGPART_EXPR
++                   || TREE_CODE (ref_base_a) == REALPART_EXPR)
++              ref_base_a = TREE_OPERAND (ref_base_a, 0);
++
++            while (TREE_CODE (ref_base_b) == COMPONENT_REF
++                   || TREE_CODE (ref_base_b) == IMAGPART_EXPR
++                   || TREE_CODE (ref_base_b) == REALPART_EXPR)
++              ref_base_b = TREE_OPERAND (ref_base_b, 0);
++
++  	    if (!operand_equal_p (ref_base_a, ref_base_b, 0))
++	      {
++	        tree cb = bb_predicate (gimple_bb (DR_STMT (b)));
++
++	        if (DR_RW_UNCONDITIONALLY (b) == 1
++		    || is_true_predicate (cb)
++		    || is_true_predicate (ca
++                        = fold_or_predicates (EXPR_LOCATION (cb), ca, cb)))
++		  {
++		    DR_RW_UNCONDITIONALLY (a) = 1;
++  		    DR_RW_UNCONDITIONALLY (b) = 1;
++		    found = true;
++		    break;
++		  }
++               }
+ 	    }
+ 
+ 	if (!found)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch
new file mode 100644
index 0000000000..2c14ceb8cb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch
@@ -0,0 +1,140 @@
+2011-05-02  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from FSF:
+
+	2011-03-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (arm_autovectorize_vector_sizes): New function.
+	(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-outer-5.c: Reduce the distance between data
+	accesses to preserve the meaning of the test for doubleword vectors.
+	* gcc.dg/vect/no-vfa-pr29145.c: Likewise.
+	* gcc.dg/vect/slp-3.c: Reduce the loop bound for the same reason.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-03-02 11:38:43 +0000
++++ new/gcc/config/arm/arm.c	2011-04-28 11:46:58 +0000
+@@ -250,6 +250,7 @@
+ 						     bool is_packed);
+ static void arm_conditional_register_usage (void);
+ static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
++static unsigned int arm_autovectorize_vector_sizes (void);
+ 
+ 
+ /* Table of machine attributes.  */
+@@ -395,6 +396,9 @@
+ #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
+ #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
+ #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
++#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
++#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
++  arm_autovectorize_vector_sizes
+ 
+ #undef  TARGET_MACHINE_DEPENDENT_REORG
+ #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
+@@ -23511,6 +23515,12 @@
+     }
+ }
+ 
++static unsigned int
++arm_autovectorize_vector_sizes (void)
++{
++  return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
++}
++
+ static bool
+ arm_vector_alignment_reachable (const_tree type, bool is_packed)
+ {
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c	2011-04-28 11:46:58 +0000
+@@ -8,7 +8,7 @@
+ void with_restrict(int * __restrict p)
+ {
+   int i;
+-  int *q = p - 2;
++  int *q = p - 1;
+ 
+   for (i = 0; i < 1000; ++i) {
+     p[i] = q[i];
+@@ -19,7 +19,7 @@
+ void without_restrict(int * p)
+ {
+   int i;
+-  int *q = p - 2;
++  int *q = p - 1;
+ 
+   for (i = 0; i < 1000; ++i) {
+     p[i] = q[i];
+@@ -38,8 +38,8 @@
+     a[i] = b[i] = i;
+   }
+ 
+-  with_restrict(a + 2);
+-  without_restrict(b + 2);
++  with_restrict(a + 1);
++  without_restrict(b + 1);
+ 
+   for (i = 0; i < 1002; ++i) {
+     if (a[i] != b[i])
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-3.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-3.c	2011-04-28 11:46:58 +0000
+@@ -4,9 +4,9 @@
+ #include <stdarg.h>
+ #include "tree-vect.h"
+ 
+-#define N 8 
++#define N 12 
+ 
+-unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
+ 
+ int
+ main1 ()
+@@ -101,7 +101,7 @@
+     }
+ 
+   /* SLP with unrolling by 8.  */
+-  for (i = 0; i < N/2; i++)
++  for (i = 0; i < N/4; i++)
+     {
+       out[i*9] = in[i*9];
+       out[i*9 + 1] = in[i*9 + 1];
+@@ -115,7 +115,7 @@
+     }
+ 
+   /* check results:  */
+-  for (i = 0; i < N/2; i++)
++  for (i = 0; i < N/4; i++)
+     {
+       if (out[i*9] !=  in[i*9]
+          || out[i*9 + 1] != in[i*9 + 1]
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c	2011-04-28 11:46:58 +0000
+@@ -17,7 +17,7 @@
+   float B[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+   float C[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+   float D[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+-  float E[4] = {0,1,2,480};
++  float E[4] = {0,480,960,1440};
+   float s;
+ 
+   int i, j;
+@@ -55,7 +55,7 @@
+       s = 0;
+       for (j=0; j<N; j+=4)
+ 	s += C[j];
+-      B[i+3] = B[i] + s;
++      B[i+1] = B[i] + s;
+     }
+ 
+   /* check results:  */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
new file mode 100644
index 0000000000..6e76c21272
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
@@ -0,0 +1,255 @@
+2011-04-26  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2011-04-15  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	gcc/
+	* combine.c (subst, combine_simlify_rtx): Add new argument, use it
+	to track processing of conditionals.  Update all callers.
+	(try_combine, simplify_if_then_else): Update.
+
+	2011-04-25  Maxim Kuvyrkov  <maxim@codesourcery.com>
+		    Eric Botcazou <ebotcazou@adacore.com>
+
+	gcc/
+	* combine.c (combine_simplify_rtx): Avoid mis-simplifying conditionals
+	for STORE_FLAG_VALUE==-1 case.
+
+=== modified file 'gcc/combine.c'
+Index: gcc-4_6-branch/gcc/combine.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/combine.c	2012-03-05 00:16:20.000000000 -0800
++++ gcc-4_6-branch/gcc/combine.c	2012-03-05 16:05:01.212928507 -0800
+@@ -391,8 +391,8 @@
+ static void undo_all (void);
+ static void undo_commit (void);
+ static rtx *find_split_point (rtx *, rtx, bool);
+-static rtx subst (rtx, rtx, rtx, int, int);
+-static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
++static rtx subst (rtx, rtx, rtx, int, int, int);
++static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
+ static rtx simplify_if_then_else (rtx);
+ static rtx simplify_set (rtx);
+ static rtx simplify_logical (rtx);
+@@ -3119,12 +3119,12 @@
+ 	  if (i1)
+ 	    {
+ 	      subst_low_luid = DF_INSN_LUID (i1);
+-	      i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
++	      i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	    }
+ 	  else
+ 	    {
+ 	      subst_low_luid = DF_INSN_LUID (i2);
+-	      i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
++	      i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	    }
+ 	}
+ 
+@@ -3136,7 +3136,7 @@
+ 	 self-referential RTL when we will be substituting I1SRC for I1DEST
+ 	 later.  Likewise if I0 feeds into I2, either directly or indirectly
+ 	 through I1, and I0DEST is in I0SRC.  */
+-      newpat = subst (PATTERN (i3), i2dest, i2src, 0,
++      newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
+ 		      (i1_feeds_i2_n && i1dest_in_i1src)
+ 		      || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
+ 			  && i0dest_in_i0src));
+@@ -3180,7 +3180,7 @@
+ 	 copy of I1SRC each time we substitute it, in order to avoid creating
+ 	 self-referential RTL when we will be substituting I0SRC for I0DEST
+ 	 later.  */
+-      newpat = subst (newpat, i1dest, i1src, 0,
++      newpat = subst (newpat, i1dest, i1src, 0, 0,
+ 		      i0_feeds_i1_n && i0dest_in_i0src);
+       substed_i1 = 1;
+ 
+@@ -3214,7 +3214,7 @@
+ 
+       n_occurrences = 0;
+       subst_low_luid = DF_INSN_LUID (i0);
+-      newpat = subst (newpat, i0dest, i0src, 0, 0);
++      newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
+       substed_i0 = 1;
+     }
+ 
+@@ -3276,7 +3276,7 @@
+ 	{
+ 	  rtx t = i1pat;
+ 	  if (i0_feeds_i1_n)
+-	    t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0);
++	    t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
+ 
+ 	  XVECEXP (newpat, 0, --total_sets) = t;
+ 	}
+@@ -3284,10 +3284,10 @@
+ 	{
+ 	  rtx t = i2pat;
+ 	  if (i1_feeds_i2_n)
+-	    t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
++	    t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
+ 		       i0_feeds_i1_n && i0dest_in_i0src);
+ 	  if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
+-	    t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0);
++	    t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
+ 
+ 	  XVECEXP (newpat, 0, --total_sets) = t;
+ 	}
+@@ -4959,11 +4959,13 @@
+ 
+    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
+ 
++   IN_COND is nonzero if we are on top level of the condition.
++
+    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
+    by copying if `n_occurrences' is nonzero.  */
+ 
+ static rtx
+-subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
++subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
+ {
+   enum rtx_code code = GET_CODE (x);
+   enum machine_mode op0_mode = VOIDmode;
+@@ -5024,7 +5026,7 @@
+       && GET_CODE (XVECEXP (x, 0, 0)) == SET
+       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
+     {
+-      new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
++      new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
+ 
+       /* If this substitution failed, this whole thing fails.  */
+       if (GET_CODE (new_rtx) == CLOBBER
+@@ -5041,7 +5043,7 @@
+ 	      && GET_CODE (dest) != CC0
+ 	      && GET_CODE (dest) != PC)
+ 	    {
+-	      new_rtx = subst (dest, from, to, 0, unique_copy);
++	      new_rtx = subst (dest, from, to, 0, 0, unique_copy);
+ 
+ 	      /* If this substitution failed, this whole thing fails.  */
+ 	      if (GET_CODE (new_rtx) == CLOBBER
+@@ -5087,8 +5089,8 @@
+ 		    }
+ 		  else
+ 		    {
+-		      new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
+-				   unique_copy);
++		      new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
++				       unique_copy);
+ 
+ 		      /* If this substitution failed, this whole thing
+ 			 fails.  */
+@@ -5165,7 +5167,9 @@
+ 				&& (code == SUBREG || code == STRICT_LOW_PART
+ 				    || code == ZERO_EXTRACT))
+ 			       || code == SET)
+-			      && i == 0), unique_copy);
++			      && i == 0),
++				 code == IF_THEN_ELSE && i == 0,
++				 unique_copy);
+ 
+ 	      /* If we found that we will have to reject this combination,
+ 		 indicate that by returning the CLOBBER ourselves, rather than
+@@ -5222,7 +5226,7 @@
+       /* If X is sufficiently simple, don't bother trying to do anything
+ 	 with it.  */
+       if (code != CONST_INT && code != REG && code != CLOBBER)
+-	x = combine_simplify_rtx (x, op0_mode, in_dest);
++	x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
+ 
+       if (GET_CODE (x) == code)
+ 	break;
+@@ -5242,10 +5246,12 @@
+    expression.
+ 
+    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
+-   if we are inside a SET_DEST.  */
++   if we are inside a SET_DEST.  IN_COND is nonzero if we are on the top level
++   of a condition.  */
+ 
+ static rtx
+-combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
++combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
++		      int in_cond)
+ {
+   enum rtx_code code = GET_CODE (x);
+   enum machine_mode mode = GET_MODE (x);
+@@ -5300,8 +5306,8 @@
+ 	     false arms to store-flag values.  Be careful to use copy_rtx
+ 	     here since true_rtx or false_rtx might share RTL with x as a
+ 	     result of the if_then_else_cond call above.  */
+-	  true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
+-	  false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
++	  true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
++	  false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
+ 
+ 	  /* If true_rtx and false_rtx are not general_operands, an if_then_else
+ 	     is unlikely to be simpler.  */
+@@ -5645,7 +5651,7 @@
+ 	{
+ 	  /* Try to simplify the expression further.  */
+ 	  rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
+-	  temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
++	  temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
+ 
+ 	  /* If we could, great.  If not, do not go ahead with the IOR
+ 	     replacement, since PLUS appears in many special purpose
+@@ -5738,7 +5744,16 @@
+ 	     ZERO_EXTRACT is indeed appropriate, it will be placed back by
+ 	     the call to make_compound_operation in the SET case.  */
+ 
+-	  if (STORE_FLAG_VALUE == 1
++	  if (in_cond)
++	    /* Don't apply below optimizations if the caller would
++	       prefer a comparison rather than a value.
++	       E.g., for the condition in an IF_THEN_ELSE most targets need
++	       an explicit comparison.  */
++	    {
++	      ;
++	    }
++
++	  else if (STORE_FLAG_VALUE == 1
+ 	      && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
+ 	      && op1 == const0_rtx
+ 	      && mode == GET_MODE (op0)
+@@ -5784,7 +5799,10 @@
+ 
+ 	  /* If STORE_FLAG_VALUE is -1, we have cases similar to
+ 	     those above.  */
+-	  if (STORE_FLAG_VALUE == -1
++	  if (in_cond)
++	    ;
++
++	  else if (STORE_FLAG_VALUE == -1
+ 	      && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
+ 	      && op1 == const0_rtx
+ 	      && (num_sign_bit_copies (op0, mode)
+@@ -5982,11 +6000,11 @@
+       if (reg_mentioned_p (from, true_rtx))
+ 	true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
+ 				      from, true_val),
+-		      pc_rtx, pc_rtx, 0, 0);
++			  pc_rtx, pc_rtx, 0, 0, 0);
+       if (reg_mentioned_p (from, false_rtx))
+ 	false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
+ 				   from, false_val),
+-		       pc_rtx, pc_rtx, 0, 0);
++			   pc_rtx, pc_rtx, 0, 0, 0);
+ 
+       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
+       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
+@@ -6203,11 +6221,11 @@
+ 	{
+ 	  temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
+ 						 cond_op0, cond_op1),
+-			pc_rtx, pc_rtx, 0, 0);
++			pc_rtx, pc_rtx, 0, 0, 0);
+ 	  temp = simplify_gen_binary (MULT, m, temp,
+ 				      simplify_gen_binary (MULT, m, c1,
+ 							   const_true_rtx));
+-	  temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
++	  temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
+ 	  temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
+ 
+ 	  if (extend_op != UNKNOWN)
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
new file mode 100644
index 0000000000..395c08cab7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
@@ -0,0 +1,6125 @@
+2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	From  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/46329
+	* gcc.target/arm/pr46329.c: New test.
+
+	gcc/
+	PR target/46329
+	* config/arm/arm.c (arm_legitimate_constant_p_1): Return false
+	for all Neon struct constants.
+
+2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* targhooks.h (default_legitimate_constant_p); Declare.
+	* targhooks.c (default_legitimate_constant_p): New function.
+
+	Backport from mainline:
+	2011-04-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* target.def (legitimate_constant_p): New hook.
+	* doc/tm.texi.in (LEGITIMATE_CONSTANT_P): Replace with...
+	(TARGET_LEGITIMATE_CONSTANT_P): ...this.
+	* doc/tm.texi: Regenerate.
+	* calls.c (precompute_register_parameters): Replace uses of
+	LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p.
+	(emit_library_call_value_1): Likewise.
+	* expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn)
+	(compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise.
+	* recog.c (general_operand, immediate_operand): Likewise.
+	* reload.c (find_reloads_toplev, find_reloads_address_part): Likewise.
+	* reload1.c (init_eliminable_invariants): Likewise.
+
+	* config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete.
+	* config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise.
+	(THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise.
+	* config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define.
+	(arm_legitimate_constant_p_1, thumb_legitimate_constant_p)
+	(arm_legitimate_constant_p): New functions.
+	(arm_cannot_force_const_mem): Make static.
+
+2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* hooks.h (hook_bool_mode_uhwi_false): Declare.
+	* hooks.c (hook_bool_mode_uhwi_false): New function.
+	* target.def (array_mode_supported_p): New hook.
+	* doc/tm.texi.in (TARGET_ARRAY_MODE_SUPPORTED_P): Add @hook.
+	* doc/tm.texi: Regenerate.
+	* stor-layout.c (mode_for_array): New function.
+	(layout_type): Use it.
+	* config/arm/arm.c (arm_array_mode_supported_p): New function.
+	(TARGET_ARRAY_MODE_SUPPORTED_P): Define.
+
+2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-12  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
+	size of a '%A' memory reference.
+	(T_DREG, T_QREG): New neon_builtin_type_bits.
+	(arm_init_neon_builtins): Assert that the load and store operands
+	are neon_struct_operands.
+	(locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
+	(NEON_ARG_MEMORY): New builtin_arg.
+	(neon_dereference_pointer): New function.
+	(arm_expand_neon_args): Add a neon_builtin_type_bits argument.
+	Handle NEON_ARG_MEMORY.
+	(arm_expand_neon_builtin): Update after above interface changes.
+	Use NEON_ARG_MEMORY for loads and stores.
+	* config/arm/predicates.md (neon_struct_operand): New predicate.
+	* config/arm/iterators.md (V_two_elem): Tweak formatting.
+	(V_three_elem): Use BLKmode for accesses that have no associated mode.
+	(V_four_elem): Tweak formatting.
+	* config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
+	(neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
+	(neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
+	(neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
+	(neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
+	(neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
+	(neon_vst4<mode>): Replace pointer operand with a memory operand.
+	Use %A in the output template.
+	(neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
+	(neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
+	(neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
+	the width of the memory access.  Remove post-increment.
+	* config/arm/neon-testgen.ml: Allow addresses to have an alignment.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-04-12  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/arm/neon-vld3-1.c: New test.
+	* gcc.target/arm/neon-vst3-1.c: New test.
+	* gcc.target/arm/neon/v*.c: Regenerate.
+
+2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-03-30  Richard Sandiford  <richard.sandiford@linaro.org>
+		    Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/43590
+	* config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove
+	operand 1 and reshuffle the operands to match.
+	(neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
+
+=== modified file 'gcc/calls.c'
+Index: gcc-4_6-branch/gcc/calls.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/calls.c	2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/calls.c	2011-09-16 20:16:00.217564705 -0700
+@@ -686,7 +686,7 @@
+ 	/* If the value is a non-legitimate constant, force it into a
+ 	   pseudo now.  TLS symbols sometimes need a call to resolve.  */
+ 	if (CONSTANT_P (args[i].value)
+-	    && !LEGITIMATE_CONSTANT_P (args[i].value))
++	    && !targetm.legitimate_constant_p (args[i].mode, args[i].value))
+ 	  args[i].value = force_reg (args[i].mode, args[i].value);
+ 
+ 	/* If we are to promote the function arg to a wider mode,
+@@ -3449,7 +3449,8 @@
+ 
+       /* Make sure it is a reasonable operand for a move or push insn.  */
+       if (!REG_P (addr) && !MEM_P (addr)
+-	  && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
++	  && !(CONSTANT_P (addr)
++	       && targetm.legitimate_constant_p (Pmode, addr)))
+ 	addr = force_operand (addr, NULL_RTX);
+ 
+       argvec[count].value = addr;
+@@ -3490,7 +3491,7 @@
+ 
+       /* Make sure it is a reasonable operand for a move or push insn.  */
+       if (!REG_P (val) && !MEM_P (val)
+-	  && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
++	  && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val)))
+ 	val = force_operand (val, NULL_RTX);
+ 
+       if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
+Index: gcc-4_6-branch/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm-protos.h	2011-06-24 08:33:37.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/arm-protos.h	2011-09-16 20:16:00.217564705 -0700
+@@ -81,7 +81,6 @@
+ extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
+ 						     bool);
+ extern bool arm_tls_referenced_p (rtx);
+-extern bool arm_cannot_force_const_mem (rtx);
+ 
+ extern int cirrus_memory_offset (rtx);
+ extern int arm_coproc_mem_operand (rtx, bool);
+Index: gcc-4_6-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.c	2011-09-16 20:14:34.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/arm.c	2011-09-16 20:16:00.237564275 -0700
+@@ -143,6 +143,8 @@
+ static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
+ 				 tree);
+ static bool arm_have_conditional_execution (void);
++static bool arm_cannot_force_const_mem (rtx);
++static bool arm_legitimate_constant_p (enum machine_mode, rtx);
+ static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
+ static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+ static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+@@ -241,6 +243,8 @@
+ static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
+ static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
+ static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *);
++static bool arm_array_mode_supported_p (enum machine_mode,
++					unsigned HOST_WIDE_INT);
+ static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
+ static bool arm_class_likely_spilled_p (reg_class_t);
+ static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
+@@ -394,6 +398,8 @@
+ #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
+ #undef TARGET_VECTOR_MODE_SUPPORTED_P
+ #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
++#undef TARGET_ARRAY_MODE_SUPPORTED_P
++#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
+ #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
+ #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
+ #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
+@@ -523,6 +529,9 @@
+ #undef TARGET_HAVE_CONDITIONAL_EXECUTION
+ #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
+ 
++#undef TARGET_LEGITIMATE_CONSTANT_P
++#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
++
+ #undef TARGET_CANNOT_FORCE_CONST_MEM
+ #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
+ 
+@@ -6539,9 +6548,47 @@
+   return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
+ }
+ 
++/* Implement TARGET_LEGITIMATE_CONSTANT_P.
++
++   On the ARM, allow any integer (invalid ones are removed later by insn
++   patterns), nice doubles and symbol_refs which refer to the function's
++   constant pool XXX.
++
++   When generating pic allow anything.  */
++
++static bool
++arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
++{
++  /* At present, we have no support for Neon structure constants, so forbid
++     them here.  It might be possible to handle simple cases like 0 and -1
++     in future.  */
++  if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
++    return false;
++
++  return flag_pic || !label_mentioned_p (x);
++}
++
++static bool
++thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
++{
++  return (GET_CODE (x) == CONST_INT
++	  || GET_CODE (x) == CONST_DOUBLE
++	  || CONSTANT_ADDRESS_P (x)
++	  || flag_pic);
++}
++
++static bool
++arm_legitimate_constant_p (enum machine_mode mode, rtx x)
++{
++  return (!arm_cannot_force_const_mem (x)
++	  && (TARGET_32BIT
++	      ? arm_legitimate_constant_p_1 (mode, x)
++	      : thumb_legitimate_constant_p (mode, x)));
++}
++
+ /* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */
+ 
+-bool
++static bool
+ arm_cannot_force_const_mem (rtx x)
+ {
+   rtx base, offset;
+@@ -16598,7 +16645,7 @@
+       {
+ 	rtx addr;
+ 	bool postinc = FALSE;
+-	unsigned align, modesize, align_bits;
++	unsigned align, memsize, align_bits;
+ 
+ 	gcc_assert (GET_CODE (x) == MEM);
+ 	addr = XEXP (x, 0);
+@@ -16613,12 +16660,12 @@
+ 	   instruction (for some alignments) as an aid to the memory subsystem
+ 	   of the target.  */
+ 	align = MEM_ALIGN (x) >> 3;
+-	modesize = GET_MODE_SIZE (GET_MODE (x));
++	memsize = INTVAL (MEM_SIZE (x));
+ 	
+ 	/* Only certain alignment specifiers are supported by the hardware.  */
+-	if (modesize == 16 && (align % 32) == 0)
++	if (memsize == 16 && (align % 32) == 0)
+ 	  align_bits = 256;
+-	else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
++	else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
+ 	  align_bits = 128;
+ 	else if ((align % 8) == 0)
+ 	  align_bits = 64;
+@@ -18278,12 +18325,14 @@
+   T_V2SI  = 0x0004,
+   T_V2SF  = 0x0008,
+   T_DI    = 0x0010,
++  T_DREG  = 0x001F,
+   T_V16QI = 0x0020,
+   T_V8HI  = 0x0040,
+   T_V4SI  = 0x0080,
+   T_V4SF  = 0x0100,
+   T_V2DI  = 0x0200,
+   T_TI	  = 0x0400,
++  T_QREG  = 0x07E0,
+   T_EI	  = 0x0800,
+   T_OI	  = 0x1000
+ };
+@@ -18929,10 +18978,9 @@
+ 		    if (is_load && k == 1)
+ 		      {
+ 		        /* Neon load patterns always have the memory operand
+-			   (a SImode pointer) in the operand 1 position.  We
+-			   want a const pointer to the element type in that
+-			   position.  */
+-		        gcc_assert (insn_data[icode].operand[k].mode == SImode);
++			   in the operand 1 position.  */
++			gcc_assert (insn_data[icode].operand[k].predicate
++				    == neon_struct_operand);
+ 
+ 			switch (1 << j)
+ 			  {
+@@ -18967,10 +19015,9 @@
+ 		    else if (is_store && k == 0)
+ 		      {
+ 		        /* Similarly, Neon store patterns use operand 0 as
+-			   the memory location to store to (a SImode pointer).
+-			   Use a pointer to the element type of the store in
+-			   that position.  */
+-			gcc_assert (insn_data[icode].operand[k].mode == SImode);
++			   the memory location to store to.  */
++			gcc_assert (insn_data[icode].operand[k].predicate
++				    == neon_struct_operand);
+ 
+ 			switch (1 << j)
+ 			  {
+@@ -19290,12 +19337,13 @@
+ }
+ 
+ static enum insn_code
+-locate_neon_builtin_icode (int fcode, neon_itype *itype)
++locate_neon_builtin_icode (int fcode, neon_itype *itype,
++			   enum neon_builtin_type_bits *type_bit)
+ {
+   neon_builtin_datum key
+     = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
+   neon_builtin_datum *found;
+-  int idx;
++  int idx, type, ntypes;
+ 
+   key.base_fcode = fcode;
+   found = (neon_builtin_datum *)
+@@ -19308,20 +19356,84 @@
+   if (itype)
+     *itype = found->itype;
+ 
++  if (type_bit)
++    {
++      ntypes = 0;
++      for (type = 0; type < T_MAX; type++)
++	if (found->bits & (1 << type))
++	  {
++	    if (ntypes == idx)
++	      break;
++	    ntypes++;
++	  }
++      gcc_assert (type < T_MAX);
++      *type_bit = (enum neon_builtin_type_bits) (1 << type);
++    }
+   return found->codes[idx];
+ }
+ 
+ typedef enum {
+   NEON_ARG_COPY_TO_REG,
+   NEON_ARG_CONSTANT,
++  NEON_ARG_MEMORY,
+   NEON_ARG_STOP
+ } builtin_arg;
+ 
+ #define NEON_MAX_BUILTIN_ARGS 5
+ 
++/* EXP is a pointer argument to a Neon load or store intrinsic.  Derive
++   and return an expression for the accessed memory.
++
++   The intrinsic function operates on a block of registers that has
++   mode REG_MODE.  This block contains vectors of type TYPE_BIT.
++   The function references the memory at EXP in mode MEM_MODE;
++   this mode may be BLKmode if no more suitable mode is available.  */
++
++static tree
++neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
++			  enum machine_mode reg_mode,
++			  enum neon_builtin_type_bits type_bit)
++{
++  HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
++  tree elem_type, upper_bound, array_type;
++
++  /* Work out the size of the register block in bytes.  */
++  reg_size = GET_MODE_SIZE (reg_mode);
++
++  /* Work out the size of each vector in bytes.  */
++  gcc_assert (type_bit & (T_DREG | T_QREG));
++  vector_size = (type_bit & T_QREG ? 16 : 8);
++
++  /* Work out how many vectors there are.  */
++  gcc_assert (reg_size % vector_size == 0);
++  nvectors = reg_size / vector_size;
++
++  /* Work out how many elements are being loaded or stored.
++     MEM_MODE == REG_MODE implies a one-to-one mapping between register
++     and memory elements; anything else implies a lane load or store.  */
++  if (mem_mode == reg_mode)
++    nelems = vector_size * nvectors;
++  else
++    nelems = nvectors;
++
++  /* Work out the type of each element.  */
++  gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
++  elem_type = TREE_TYPE (TREE_TYPE (exp));
++
++  /* Create a type that describes the full access.  */
++  upper_bound = build_int_cst (size_type_node, nelems - 1);
++  array_type = build_array_type (elem_type, build_index_type (upper_bound));
++
++  /* Dereference EXP using that type.  */
++  exp = convert (build_pointer_type (array_type), exp);
++  return fold_build2 (MEM_REF, array_type, exp,
++		      build_int_cst (TREE_TYPE (exp), 0));
++}
++
+ /* Expand a Neon builtin.  */
+ static rtx
+ arm_expand_neon_args (rtx target, int icode, int have_retval,
++		      enum neon_builtin_type_bits type_bit,
+ 		      tree exp, ...)
+ {
+   va_list ap;
+@@ -19330,7 +19442,9 @@
+   rtx op[NEON_MAX_BUILTIN_ARGS];
+   enum machine_mode tmode = insn_data[icode].operand[0].mode;
+   enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
++  enum machine_mode other_mode;
+   int argc = 0;
++  int opno;
+ 
+   if (have_retval
+       && (!target
+@@ -19348,26 +19462,46 @@
+         break;
+       else
+         {
++          opno = argc + have_retval;
++          mode[argc] = insn_data[icode].operand[opno].mode;
+           arg[argc] = CALL_EXPR_ARG (exp, argc);
++          if (thisarg == NEON_ARG_MEMORY)
++            {
++              other_mode = insn_data[icode].operand[1 - opno].mode;
++              arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
++                                                    other_mode, type_bit);
++            }
+           op[argc] = expand_normal (arg[argc]);
+-          mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
+ 
+           switch (thisarg)
+             {
+             case NEON_ARG_COPY_TO_REG:
+               /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
+-              if (!(*insn_data[icode].operand[argc + have_retval].predicate)
++              if (!(*insn_data[icode].operand[opno].predicate)
+                      (op[argc], mode[argc]))
+                 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
+               break;
+ 
+             case NEON_ARG_CONSTANT:
+               /* FIXME: This error message is somewhat unhelpful.  */
+-              if (!(*insn_data[icode].operand[argc + have_retval].predicate)
++              if (!(*insn_data[icode].operand[opno].predicate)
+                     (op[argc], mode[argc]))
+ 		error ("argument must be a constant");
+               break;
+ 
++            case NEON_ARG_MEMORY:
++	      gcc_assert (MEM_P (op[argc]));
++	      PUT_MODE (op[argc], mode[argc]);
++	      /* ??? arm_neon.h uses the same built-in functions for signed
++		 and unsigned accesses, casting where necessary.  This isn't
++		 alias safe.  */
++	      set_mem_alias_set (op[argc], 0);
++	      if (!(*insn_data[icode].operand[opno].predicate)
++                    (op[argc], mode[argc]))
++		op[argc] = (replace_equiv_address
++			    (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
++              break;
++
+             case NEON_ARG_STOP:
+               gcc_unreachable ();
+             }
+@@ -19446,14 +19580,15 @@
+ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+ {
+   neon_itype itype;
+-  enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
++  enum neon_builtin_type_bits type_bit;
++  enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
+ 
+   switch (itype)
+     {
+     case NEON_UNOP:
+     case NEON_CONVERT:
+     case NEON_DUPLANE:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_BINOP:
+@@ -19463,90 +19598,90 @@
+     case NEON_SCALARMULH:
+     case NEON_SHIFTINSERT:
+     case NEON_LOGICBINOP:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_STOP);
+ 
+     case NEON_TERNOP:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_GETLANE:
+     case NEON_FIXCONV:
+     case NEON_SHIFTIMM:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
+         NEON_ARG_STOP);
+ 
+     case NEON_CREATE:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_DUP:
+     case NEON_SPLIT:
+     case NEON_REINTERP:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_COMBINE:
+     case NEON_VTBL:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_RESULTPAIR:
+-      return arm_expand_neon_args (target, icode, 0, exp,
++      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_STOP);
+ 
+     case NEON_LANEMUL:
+     case NEON_LANEMULL:
+     case NEON_LANEMULH:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_LANEMAC:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SHIFTACC:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SCALARMAC:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SELECT:
+     case NEON_VTBX:
+-      return arm_expand_neon_args (target, icode, 1, exp,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_STOP);
+ 
+     case NEON_LOAD1:
+     case NEON_LOADSTRUCT:
+-      return arm_expand_neon_args (target, icode, 1, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_STOP);
+ 
+     case NEON_LOAD1LANE:
+     case NEON_LOADSTRUCTLANE:
+-      return arm_expand_neon_args (target, icode, 1, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
++      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ 	NEON_ARG_STOP);
+ 
+     case NEON_STORE1:
+     case NEON_STORESTRUCT:
+-      return arm_expand_neon_args (target, icode, 0, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
++      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_STORE1LANE:
+     case NEON_STORESTRUCTLANE:
+-      return arm_expand_neon_args (target, icode, 0, exp,
+-	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
++      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ 	NEON_ARG_STOP);
+     }
+ 
+@@ -22265,6 +22400,20 @@
+     return true;
+ 
+   return false;
++}
++
++/* Implements target hook array_mode_supported_p.  */
++
++static bool
++arm_array_mode_supported_p (enum machine_mode mode,
++			    unsigned HOST_WIDE_INT nelems)
++{
++  if (TARGET_NEON
++      && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
++      && (nelems >= 2 && nelems <= 4))
++    return true;
++
++  return false;
+ }
+ 
+ /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
+Index: gcc-4_6-branch/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.h	2011-09-16 20:14:33.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/arm.h	2011-09-16 20:16:00.237564275 -0700
+@@ -1777,27 +1777,6 @@
+ #define TARGET_DEFAULT_WORD_RELOCATIONS 0
+ #endif
+ 
+-/* Nonzero if the constant value X is a legitimate general operand.
+-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+-
+-   On the ARM, allow any integer (invalid ones are removed later by insn
+-   patterns), nice doubles and symbol_refs which refer to the function's
+-   constant pool XXX.
+-
+-   When generating pic allow anything.  */
+-#define ARM_LEGITIMATE_CONSTANT_P(X)	(flag_pic || ! label_mentioned_p (X))
+-
+-#define THUMB_LEGITIMATE_CONSTANT_P(X)	\
+- (   GET_CODE (X) == CONST_INT		\
+-  || GET_CODE (X) == CONST_DOUBLE	\
+-  || CONSTANT_ADDRESS_P (X)		\
+-  || flag_pic)
+-
+-#define LEGITIMATE_CONSTANT_P(X)			\
+-  (!arm_cannot_force_const_mem (X)			\
+-   && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X)	\
+-		    : THUMB_LEGITIMATE_CONSTANT_P (X)))
+-
+ #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
+ #define SUBTARGET_NAME_ENCODING_LENGTHS
+ #endif
+Index: gcc-4_6-branch/gcc/config/arm/iterators.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/iterators.md	2011-06-24 08:33:37.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/iterators.md	2011-09-16 20:16:00.237564275 -0700
+@@ -194,24 +194,22 @@
+ 
+ ;; Mode of pair of elements for each vector mode, to define transfer
+ ;; size for structure lane/dup loads and stores.
+-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
+-                  (V4HI "SI") (V8HI "SI")
++(define_mode_attr V_two_elem [(V8QI "HI")   (V16QI "HI")
++                              (V4HI "SI")   (V8HI "SI")
+                               (V2SI "V2SI") (V4SI "V2SI")
+                               (V2SF "V2SF") (V4SF "V2SF")
+                               (DI "V2DI")   (V2DI "V2DI")])
+ 
+ ;; Similar, for three elements.
+-;; ??? Should we define extra modes so that sizes of all three-element
+-;; accesses can be accurately represented?
+-(define_mode_attr V_three_elem [(V8QI "SI")   (V16QI "SI")
+-                    (V4HI "V4HI") (V8HI "V4HI")
+-                                (V2SI "V4SI") (V4SI "V4SI")
+-                                (V2SF "V4SF") (V4SF "V4SF")
+-                                (DI "EI")     (V2DI "EI")])
++(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
++                                (V4HI "BLK") (V8HI "BLK")
++                                (V2SI "BLK") (V4SI "BLK")
++                                (V2SF "BLK") (V4SF "BLK")
++                                (DI "EI")    (V2DI "EI")])
+ 
+ ;; Similar, for four elements.
+ (define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
+-                   (V4HI "V4HI") (V8HI "V4HI")
++                               (V4HI "V4HI") (V8HI "V4HI")
+                                (V2SI "V4SI") (V4SI "V4SI")
+                                (V2SF "V4SF") (V4SF "V4SF")
+                                (DI "OI")     (V2DI "OI")])
+Index: gcc-4_6-branch/gcc/config/arm/neon-testgen.ml
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/neon-testgen.ml	2011-06-24 08:33:37.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/neon-testgen.ml	2011-09-16 20:16:00.237564275 -0700
+@@ -177,7 +177,7 @@
+       let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
+         "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
+     | (PtrTo elt | CstPtrTo elt) ->
+-      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]"
++      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
+     | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+     | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+     | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
+Index: gcc-4_6-branch/gcc/config/arm/neon.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/neon.md	2011-07-19 21:50:44.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/neon.md	2011-09-16 20:16:00.247564269 -0700
+@@ -4250,16 +4250,16 @@
+ 
+ (define_insn "neon_vld1<mode>"
+   [(set (match_operand:VDQX 0 "s_register_operand" "=w")
+-        (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
++        (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
+                     UNSPEC_VLD1))]
+   "TARGET_NEON"
+-  "vld1.<V_sz_elem>\t%h0, [%1]"
++  "vld1.<V_sz_elem>\t%h0, %A1"
+   [(set_attr "neon_type" "neon_vld1_1_2_regs")]
+ )
+ 
+ (define_insn "neon_vld1_lane<mode>"
+   [(set (match_operand:VDX 0 "s_register_operand" "=w")
+-        (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
+                      (match_operand:VDX 2 "s_register_operand" "0")
+                      (match_operand:SI 3 "immediate_operand" "i")]
+                     UNSPEC_VLD1_LANE))]
+@@ -4270,9 +4270,9 @@
+   if (lane < 0 || lane >= max)
+     error ("lane out of range");
+   if (max == 1)
+-    return "vld1.<V_sz_elem>\t%P0, [%1]";
++    return "vld1.<V_sz_elem>\t%P0, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
+@@ -4282,7 +4282,7 @@
+ 
+ (define_insn "neon_vld1_lane<mode>"
+   [(set (match_operand:VQX 0 "s_register_operand" "=w")
+-        (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
+                      (match_operand:VQX 2 "s_register_operand" "0")
+                      (match_operand:SI 3 "immediate_operand" "i")]
+                     UNSPEC_VLD1_LANE))]
+@@ -4301,9 +4301,9 @@
+     }
+   operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
+   if (max == 2)
+-    return "vld1.<V_sz_elem>\t%P0, [%1]";
++    return "vld1.<V_sz_elem>\t%P0, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
+@@ -4313,14 +4313,14 @@
+ 
+ (define_insn "neon_vld1_dup<mode>"
+   [(set (match_operand:VDX 0 "s_register_operand" "=w")
+-        (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
++        (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
+                     UNSPEC_VLD1_DUP))]
+   "TARGET_NEON"
+ {
+   if (GET_MODE_NUNITS (<MODE>mode) > 1)
+-    return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4330,14 +4330,14 @@
+ 
+ (define_insn "neon_vld1_dup<mode>"
+   [(set (match_operand:VQX 0 "s_register_operand" "=w")
+-        (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
++        (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
+                     UNSPEC_VLD1_DUP))]
+   "TARGET_NEON"
+ {
+   if (GET_MODE_NUNITS (<MODE>mode) > 2)
+-    return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
++    return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4346,15 +4346,15 @@
+ )
+ 
+ (define_insn "neon_vst1<mode>"
+-  [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
+ 	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
+ 		     UNSPEC_VST1))]
+   "TARGET_NEON"
+-  "vst1.<V_sz_elem>\t%h1, [%0]"
++  "vst1.<V_sz_elem>\t%h1, %A0"
+   [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
+ 
+ (define_insn "neon_vst1_lane<mode>"
+-  [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
+ 	(vec_select:<V_elem>
+ 	  (match_operand:VDX 1 "s_register_operand" "w")
+ 	  (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
+@@ -4365,9 +4365,9 @@
+   if (lane < 0 || lane >= max)
+     error ("lane out of range");
+   if (max == 1)
+-    return "vst1.<V_sz_elem>\t{%P1}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1}, %A0";
+   else
+-    return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
+@@ -4375,7 +4375,7 @@
+                     (const_string "neon_vst1_vst2_lane")))])
+ 
+ (define_insn "neon_vst1_lane<mode>"
+-  [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
+         (vec_select:<V_elem>
+            (match_operand:VQX 1 "s_register_operand" "w")
+            (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
+@@ -4394,24 +4394,24 @@
+     }
+   operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
+   if (max == 2)
+-    return "vst1.<V_sz_elem>\t{%P1}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1}, %A0";
+   else
+-    return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
++    return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
+ }
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+ 
+ (define_insn "neon_vld2<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+-        (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD2))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vld1.64\t%h0, [%1]";
++    return "vld1.64\t%h0, %A1";
+   else
+-    return "vld2.<V_sz_elem>\t%h0, [%1]";
++    return "vld2.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4421,16 +4421,16 @@
+ 
+ (define_insn "neon_vld2<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD2))]
+   "TARGET_NEON"
+-  "vld2.<V_sz_elem>\t%h0, [%1]"
++  "vld2.<V_sz_elem>\t%h0, %A1"
+   [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
+ 
+ (define_insn "neon_vld2_lane<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+-        (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:TI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4447,7 +4447,7 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 2);
+   ops[2] = operands[1];
+   ops[3] = operands[3];
+-  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
++  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+@@ -4455,7 +4455,7 @@
+ 
+ (define_insn "neon_vld2_lane<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:OI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4477,7 +4477,7 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 4);
+   ops[2] = operands[1];
+   ops[3] = GEN_INT (lane);
+-  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
++  output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+@@ -4485,15 +4485,15 @@
+ 
+ (define_insn "neon_vld2_dup<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+-        (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD2_DUP))]
+   "TARGET_NEON"
+ {
+   if (GET_MODE_NUNITS (<MODE>mode) > 1)
+-    return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
++    return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4502,16 +4502,16 @@
+ )
+ 
+ (define_insn "neon_vst2<mode>"
+-  [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
+         (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VST2))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vst1.64\t%h1, [%0]";
++    return "vst1.64\t%h1, %A0";
+   else
+-    return "vst2.<V_sz_elem>\t%h1, [%0]";
++    return "vst2.<V_sz_elem>\t%h1, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4520,17 +4520,17 @@
+ )
+ 
+ (define_insn "neon_vst2<mode>"
+-  [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ 	(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+ 		    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ 		   UNSPEC_VST2))]
+   "TARGET_NEON"
+-  "vst2.<V_sz_elem>\t%h1, [%0]"
++  "vst2.<V_sz_elem>\t%h1, %A0"
+   [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
+ )
+ 
+ (define_insn "neon_vst2_lane<mode>"
+-  [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
+ 	(unspec:<V_two_elem>
+ 	  [(match_operand:TI 1 "s_register_operand" "w")
+ 	   (match_operand:SI 2 "immediate_operand" "i")
+@@ -4548,14 +4548,14 @@
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 2);
+   ops[3] = operands[2];
+-  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
++  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+ 
+ (define_insn "neon_vst2_lane<mode>"
+-  [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_two_elem>
+            [(match_operand:OI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -4578,7 +4578,7 @@
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = GEN_INT (lane);
+-  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
++  output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+@@ -4586,15 +4586,15 @@
+ 
+ (define_insn "neon_vld3<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+-        (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD3))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vld1.64\t%h0, [%1]";
++    return "vld1.64\t%h0, %A1";
+   else
+-    return "vld3.<V_sz_elem>\t%h0, [%1]";
++    return "vld3.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4603,27 +4603,25 @@
+ )
+ 
+ (define_expand "neon_vld3<mode>"
+-  [(match_operand:CI 0 "s_register_operand" "=w")
+-   (match_operand:SI 1 "s_register_operand" "+r")
++  [(match_operand:CI 0 "s_register_operand")
++   (match_operand:CI 1 "neon_struct_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
+-  emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[1], EImode, 0);
++  emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
++  mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
++  emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vld3qa<mode>"
+   [(set (match_operand:CI 0 "s_register_operand" "=w")
+-        (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:CI 1 "s_register_operand" "0")
++        (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD3A))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 24)))]
++                   UNSPEC_VLD3A))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -4631,8 +4629,8 @@
+   ops[0] = gen_rtx_REG (DImode, regno);
+   ops[1] = gen_rtx_REG (DImode, regno + 4);
+   ops[2] = gen_rtx_REG (DImode, regno + 8);
+-  ops[3] = operands[2];
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
++  ops[3] = operands[1];
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4640,13 +4638,10 @@
+ 
+ (define_insn "neon_vld3qb<mode>"
+   [(set (match_operand:CI 0 "s_register_operand" "=w")
+-        (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:CI 1 "s_register_operand" "0")
++        (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
++                    (match_operand:CI 2 "s_register_operand" "0")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD3B))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 24)))]
++                   UNSPEC_VLD3B))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -4654,8 +4649,8 @@
+   ops[0] = gen_rtx_REG (DImode, regno + 2);
+   ops[1] = gen_rtx_REG (DImode, regno + 6);
+   ops[2] = gen_rtx_REG (DImode, regno + 10);
+-  ops[3] = operands[2];
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
++  ops[3] = operands[1];
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4663,7 +4658,7 @@
+ 
+ (define_insn "neon_vld3_lane<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+-        (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:EI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4681,7 +4676,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = operands[1];
+   ops[4] = operands[3];
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+                    ops);
+   return "";
+ }
+@@ -4690,7 +4685,7 @@
+ 
+ (define_insn "neon_vld3_lane<mode>"
+   [(set (match_operand:CI 0 "s_register_operand" "=w")
+-        (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:CI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4713,7 +4708,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 8);
+   ops[3] = operands[1];
+   ops[4] = GEN_INT (lane);
+-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
++  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+                    ops);
+   return "";
+ }
+@@ -4722,7 +4717,7 @@
+ 
+ (define_insn "neon_vld3_dup<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+-        (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD3_DUP))]
+   "TARGET_NEON"
+@@ -4735,11 +4730,11 @@
+       ops[1] = gen_rtx_REG (DImode, regno + 2);
+       ops[2] = gen_rtx_REG (DImode, regno + 4);
+       ops[3] = operands[1];
+-      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
++      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
+       return "";
+     }
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4747,16 +4742,16 @@
+                     (const_string "neon_vld1_1_2_regs")))])
+ 
+ (define_insn "neon_vst3<mode>"
+-  [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+         (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VST3))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vst1.64\t%h1, [%0]";
++    return "vst1.64\t%h1, %A0";
+   else
+-    return "vst3.<V_sz_elem>\t%h1, [%0]";
++    return "vst3.<V_sz_elem>\t%h1, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4764,62 +4759,60 @@
+                     (const_string "neon_vst2_4_regs_vst3_vst4")))])
+ 
+ (define_expand "neon_vst3<mode>"
+-  [(match_operand:SI 0 "s_register_operand" "+r")
+-   (match_operand:CI 1 "s_register_operand" "w")
++  [(match_operand:CI 0 "neon_struct_operand")
++   (match_operand:CI 1 "s_register_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
+-  emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[0], EImode, 0);
++  emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
++  mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
++  emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vst3qa<mode>"
+-  [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
++  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
++        (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST3A))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 24)))]
++                   UNSPEC_VST3A))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst3qb<mode>"
+-  [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
++  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
++        (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST3B))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 24)))]
++                   UNSPEC_VST3B))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno + 2);
+   ops[2] = gen_rtx_REG (DImode, regno + 6);
+   ops[3] = gen_rtx_REG (DImode, regno + 10);
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst3_lane<mode>"
+-  [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_three_elem>
+            [(match_operand:EI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -4838,7 +4831,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 2);
+   ops[3] = gen_rtx_REG (DImode, regno + 4);
+   ops[4] = operands[2];
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+                    ops);
+   return "";
+ }
+@@ -4846,7 +4839,7 @@
+ )
+ 
+ (define_insn "neon_vst3_lane<mode>"
+-  [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_three_elem>
+            [(match_operand:CI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -4870,7 +4863,7 @@
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+   ops[4] = GEN_INT (lane);
+-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
++  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+                    ops);
+   return "";
+ }
+@@ -4878,15 +4871,15 @@
+ 
+ (define_insn "neon_vld4<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD4))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vld1.64\t%h0, [%1]";
++    return "vld1.64\t%h0, %A1";
+   else
+-    return "vld4.<V_sz_elem>\t%h0, [%1]";
++    return "vld4.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4895,27 +4888,25 @@
+ )
+ 
+ (define_expand "neon_vld4<mode>"
+-  [(match_operand:XI 0 "s_register_operand" "=w")
+-   (match_operand:SI 1 "s_register_operand" "+r")
++  [(match_operand:XI 0 "s_register_operand")
++   (match_operand:XI 1 "neon_struct_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
+-  emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
+-                                    operands[1], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[1], OImode, 0);
++  emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
++  mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
++  emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vld4qa<mode>"
+   [(set (match_operand:XI 0 "s_register_operand" "=w")
+-        (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:XI 1 "s_register_operand" "0")
++        (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD4A))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 32)))]
++                   UNSPEC_VLD4A))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -4924,8 +4915,8 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 4);
+   ops[2] = gen_rtx_REG (DImode, regno + 8);
+   ops[3] = gen_rtx_REG (DImode, regno + 12);
+-  ops[4] = operands[2];
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
++  ops[4] = operands[1];
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4933,13 +4924,10 @@
+ 
+ (define_insn "neon_vld4qb<mode>"
+   [(set (match_operand:XI 0 "s_register_operand" "=w")
+-        (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
+-                    (match_operand:XI 1 "s_register_operand" "0")
++        (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
++                    (match_operand:XI 2 "s_register_operand" "0")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VLD4B))
+-   (set (match_operand:SI 2 "s_register_operand" "=r")
+-        (plus:SI (match_dup 3)
+-		 (const_int 32)))]
++                   UNSPEC_VLD4B))]
+   "TARGET_NEON"
+ {
+   int regno = REGNO (operands[0]);
+@@ -4948,8 +4936,8 @@
+   ops[1] = gen_rtx_REG (DImode, regno + 6);
+   ops[2] = gen_rtx_REG (DImode, regno + 10);
+   ops[3] = gen_rtx_REG (DImode, regno + 14);
+-  ops[4] = operands[2];
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
++  ops[4] = operands[1];
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4957,7 +4945,7 @@
+ 
+ (define_insn "neon_vld4_lane<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:OI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4976,7 +4964,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 6);
+   ops[4] = operands[1];
+   ops[5] = operands[3];
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
+                    ops);
+   return "";
+ }
+@@ -4985,7 +4973,7 @@
+ 
+ (define_insn "neon_vld4_lane<mode>"
+   [(set (match_operand:XI 0 "s_register_operand" "=w")
+-        (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+                     (match_operand:XI 2 "s_register_operand" "0")
+                     (match_operand:SI 3 "immediate_operand" "i")
+                     (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -5009,7 +4997,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 12);
+   ops[4] = operands[1];
+   ops[5] = GEN_INT (lane);
+-  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
++  output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
+                    ops);
+   return "";
+ }
+@@ -5018,7 +5006,7 @@
+ 
+ (define_insn "neon_vld4_dup<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+-        (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++        (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VLD4_DUP))]
+   "TARGET_NEON"
+@@ -5032,12 +5020,12 @@
+       ops[2] = gen_rtx_REG (DImode, regno + 4);
+       ops[3] = gen_rtx_REG (DImode, regno + 6);
+       ops[4] = operands[1];
+-      output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
++      output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
+                        ops);
+       return "";
+     }
+   else
+-    return "vld1.<V_sz_elem>\t%h0, [%1]";
++    return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -5046,16 +5034,16 @@
+ )
+ 
+ (define_insn "neon_vst4<mode>"
+-  [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+         (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+                     (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                    UNSPEC_VST4))]
+   "TARGET_NEON"
+ {
+   if (<V_sz_elem> == 64)
+-    return "vst1.64\t%h1, [%0]";
++    return "vst1.64\t%h1, %A0";
+   else
+-    return "vst4.<V_sz_elem>\t%h1, [%0]";
++    return "vst4.<V_sz_elem>\t%h1, %A0";
+ }
+   [(set (attr "neon_type")
+       (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -5064,64 +5052,62 @@
+ )
+ 
+ (define_expand "neon_vst4<mode>"
+-  [(match_operand:SI 0 "s_register_operand" "+r")
+-   (match_operand:XI 1 "s_register_operand" "w")
++  [(match_operand:XI 0 "neon_struct_operand")
++   (match_operand:XI 1 "s_register_operand")
+    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+   "TARGET_NEON"
+ {
+-  emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
+-  emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
++  rtx mem;
++
++  mem = adjust_address (operands[0], OImode, 0);
++  emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
++  mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
++  emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
+   DONE;
+ })
+ 
+ (define_insn "neon_vst4qa<mode>"
+-  [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
++        (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST4A))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 32)))]
++                   UNSPEC_VST4A))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[5];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno);
+   ops[2] = gen_rtx_REG (DImode, regno + 4);
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+   ops[4] = gen_rtx_REG (DImode, regno + 12);
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst4qb<mode>"
+-  [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
+-        (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
++  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
++        (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+                     (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+-                   UNSPEC_VST4B))
+-   (set (match_operand:SI 0 "s_register_operand" "=r")
+-        (plus:SI (match_dup 1)
+-		 (const_int 32)))]
++                   UNSPEC_VST4B))]
+   "TARGET_NEON"
+ {
+-  int regno = REGNO (operands[2]);
++  int regno = REGNO (operands[1]);
+   rtx ops[5];
+   ops[0] = operands[0];
+   ops[1] = gen_rtx_REG (DImode, regno + 2);
+   ops[2] = gen_rtx_REG (DImode, regno + 6);
+   ops[3] = gen_rtx_REG (DImode, regno + 10);
+   ops[4] = gen_rtx_REG (DImode, regno + 14);
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+   return "";
+ }
+   [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+ 
+ (define_insn "neon_vst4_lane<mode>"
+-  [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_four_elem>
+            [(match_operand:OI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -5141,7 +5127,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 4);
+   ops[4] = gen_rtx_REG (DImode, regno + 6);
+   ops[5] = operands[2];
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
+                    ops);
+   return "";
+ }
+@@ -5149,7 +5135,7 @@
+ )
+ 
+ (define_insn "neon_vst4_lane<mode>"
+-  [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
++  [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
+         (unspec:<V_four_elem>
+            [(match_operand:XI 1 "s_register_operand" "w")
+             (match_operand:SI 2 "immediate_operand" "i")
+@@ -5174,7 +5160,7 @@
+   ops[3] = gen_rtx_REG (DImode, regno + 8);
+   ops[4] = gen_rtx_REG (DImode, regno + 12);
+   ops[5] = GEN_INT (lane);
+-  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
++  output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
+                    ops);
+   return "";
+ }
+Index: gcc-4_6-branch/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/predicates.md	2011-09-16 19:58:21.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/predicates.md	2011-09-16 20:19:03.967834108 -0700
+@@ -686,3 +686,8 @@
+ 
+ (define_special_predicate "add_operator"
+ 			 (match_code "plus"))
++
++(define_special_predicate "neon_struct_operand"
++  (and (match_code "mem")
++       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
++
+Index: gcc-4_6-branch/gcc/doc/tm.texi
+===================================================================
+--- gcc-4_6-branch.orig/gcc/doc/tm.texi	2011-06-24 08:13:00.000000000 -0700
++++ gcc-4_6-branch/gcc/doc/tm.texi	2011-09-16 20:16:00.257564628 -0700
+@@ -2533,7 +2533,7 @@
+ register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant.  If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+ of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+ 
+ If an insn has pseudos in it after register allocation, reload will go
+@@ -2570,8 +2570,8 @@
+ register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant.  If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+-of using @code{PREFERRED_RELOAD_CLASS}.
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+ 
+ If an insn has pseudos in it after register allocation, reload will go
+ through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
+@@ -4319,6 +4319,34 @@
+ must have move patterns for this mode.
+ @end deftypefn
+ 
++@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems})
++Return true if GCC should try to use a scalar mode to store an array
++of @var{nelems} elements, given that each element has mode @var{mode}.
++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit
++and allows GCC to use any defined integer mode.
++
++One use of this hook is to support vector load and store operations
++that operate on several homogeneous vectors.  For example, ARM NEON
++has operations like:
++
++@smallexample
++int8x8x3_t vld3_s8 (const int8_t *)
++@end smallexample
++
++where the return type is defined as:
++
++@smallexample
++typedef struct int8x8x3_t
++@{
++  int8x8_t val[3];
++@} int8x8x3_t;
++@end smallexample
++
++If this hook allows @code{val} to have a scalar mode, then
++@code{int8x8x3_t} can have the same mode.  GCC can then store
++@code{int8x8x3_t}s in registers rather than forcing them onto the stack.
++@end deftypefn
++
+ @deftypefn {Target Hook} bool TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P (enum machine_mode @var{mode})
+ Define this to return nonzero for machine modes for which the port has
+ small register classes.  If this target hook returns nonzero for a given
+@@ -5577,13 +5605,13 @@
+ @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
+ @end defmac
+ 
+-@defmac LEGITIMATE_CONSTANT_P (@var{x})
+-A C expression that is nonzero if @var{x} is a legitimate constant for
+-an immediate operand on the target machine.  You can assume that
+-@var{x} satisfies @code{CONSTANT_P}, so you need not check this.  In fact,
+-@samp{1} is a suitable definition for this macro on machines where
+-anything @code{CONSTANT_P} is valid.
+-@end defmac
++@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x})
++This hook returns true if @var{x} is a legitimate constant for a
++@var{mode}-mode immediate operand on the target machine.  You can assume that
++@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
++
++The default definition returns true.
++@end deftypefn
+ 
+ @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x})
+ This hook is used to undo the possibly obfuscating effects of the
+Index: gcc-4_6-branch/gcc/doc/tm.texi.in
+===================================================================
+--- gcc-4_6-branch.orig/gcc/doc/tm.texi.in	2011-06-24 08:13:00.000000000 -0700
++++ gcc-4_6-branch/gcc/doc/tm.texi.in	2011-09-16 20:16:00.257564628 -0700
+@@ -2521,7 +2521,7 @@
+ register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant.  If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+ of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+ 
+ If an insn has pseudos in it after register allocation, reload will go
+@@ -2558,8 +2558,8 @@
+ register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant.  If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+-of using @code{PREFERRED_RELOAD_CLASS}.
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+ 
+ If an insn has pseudos in it after register allocation, reload will go
+ through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
+@@ -4305,6 +4305,8 @@
+ must have move patterns for this mode.
+ @end deftypefn
+ 
++@hook TARGET_ARRAY_MODE_SUPPORTED_P
++
+ @hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
+ Define this to return nonzero for machine modes for which the port has
+ small register classes.  If this target hook returns nonzero for a given
+@@ -5555,13 +5557,13 @@
+ @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
+ @end defmac
+ 
+-@defmac LEGITIMATE_CONSTANT_P (@var{x})
+-A C expression that is nonzero if @var{x} is a legitimate constant for
+-an immediate operand on the target machine.  You can assume that
+-@var{x} satisfies @code{CONSTANT_P}, so you need not check this.  In fact,
+-@samp{1} is a suitable definition for this macro on machines where
+-anything @code{CONSTANT_P} is valid.
+-@end defmac
++@hook TARGET_LEGITIMATE_CONSTANT_P
++This hook returns true if @var{x} is a legitimate constant for a
++@var{mode}-mode immediate operand on the target machine.  You can assume that
++@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
++
++The default definition returns true.
++@end deftypefn
+ 
+ @hook TARGET_DELEGITIMIZE_ADDRESS
+ This hook is used to undo the possibly obfuscating effects of the
+Index: gcc-4_6-branch/gcc/expr.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/expr.c	2011-09-16 20:14:32.000000000 -0700
++++ gcc-4_6-branch/gcc/expr.c	2011-09-16 20:16:00.267564792 -0700
+@@ -1497,7 +1497,7 @@
+   if (nregs == 0)
+     return;
+ 
+-  if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
++  if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
+     x = validize_mem (force_const_mem (mode, x));
+ 
+   /* See if the machine can do this with a load multiple insn.  */
+@@ -2308,7 +2308,7 @@
+ 		    offset -= size;
+ 
+ 		  cst = (*constfun) (constfundata, offset, mode);
+-		  if (!LEGITIMATE_CONSTANT_P (cst))
++		  if (!targetm.legitimate_constant_p (mode, cst))
+ 		    return 0;
+ 
+ 		  if (!reverse)
+@@ -3363,7 +3363,7 @@
+ 
+       y_cst = y;
+ 
+-      if (!LEGITIMATE_CONSTANT_P (y))
++      if (!targetm.legitimate_constant_p (mode, y))
+ 	{
+ 	  y = force_const_mem (mode, y);
+ 
+@@ -3419,7 +3419,7 @@
+ 
+   REAL_VALUE_FROM_CONST_DOUBLE (r, y);
+ 
+-  if (LEGITIMATE_CONSTANT_P (y))
++  if (targetm.legitimate_constant_p (dstmode, y))
+     oldcost = rtx_cost (y, SET, speed);
+   else
+     oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed);
+@@ -3442,7 +3442,7 @@
+ 
+       trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode);
+ 
+-      if (LEGITIMATE_CONSTANT_P (trunc_y))
++      if (targetm.legitimate_constant_p (srcmode, trunc_y))
+ 	{
+ 	  /* Skip if the target needs extra instructions to perform
+ 	     the extension.  */
+@@ -3855,7 +3855,7 @@
+ 	 by setting SKIP to 0.  */
+       skip = (reg_parm_stack_space == 0) ? 0 : not_stack;
+ 
+-      if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
++      if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
+ 	x = validize_mem (force_const_mem (mode, x));
+ 
+       /* If X is a hard register in a non-integer mode, copy it into a pseudo;
+@@ -9108,7 +9108,7 @@
+ 	   constant and we don't need a memory reference.  */
+ 	if (CONSTANT_P (op0)
+ 	    && mode2 != BLKmode
+-	    && LEGITIMATE_CONSTANT_P (op0)
++	    && targetm.legitimate_constant_p (mode2, op0)
+ 	    && !must_force_mem)
+ 	  op0 = force_reg (mode2, op0);
+ 
+Index: gcc-4_6-branch/gcc/hooks.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/hooks.c	2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/hooks.c	2011-09-16 20:16:00.267564792 -0700
+@@ -101,6 +101,15 @@
+   return true;
+ }
+ 
++/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT)
++   and returns false.  */
++bool
++hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED,
++			   unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED)
++{
++  return false;
++}
++
+ /* Generic hook that takes (FILE *, const char *) and does nothing.  */
+ void
+ hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
+Index: gcc-4_6-branch/gcc/hooks.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/hooks.h	2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/hooks.h	2011-09-16 20:16:00.267564792 -0700
+@@ -34,6 +34,8 @@
+ extern bool hook_bool_mode_true (enum machine_mode);
+ extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
+ extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx);
++extern bool hook_bool_mode_uhwi_false (enum machine_mode,
++				       unsigned HOST_WIDE_INT);
+ extern bool hook_bool_tree_false (tree);
+ extern bool hook_bool_const_tree_false (const_tree);
+ extern bool hook_bool_tree_true (tree);
+Index: gcc-4_6-branch/gcc/recog.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/recog.c	2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/recog.c	2011-09-16 20:16:00.277564886 -0700
+@@ -930,7 +930,9 @@
+     return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
+ 	     || mode == VOIDmode)
+ 	    && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+-	    && LEGITIMATE_CONSTANT_P (op));
++	    && targetm.legitimate_constant_p (mode == VOIDmode
++					      ? GET_MODE (op)
++					      : mode, op));
+ 
+   /* Except for certain constants with VOIDmode, already checked for,
+      OP's mode must match MODE if MODE specifies a mode.  */
+@@ -1107,7 +1109,9 @@
+ 	  && (GET_MODE (op) == mode || mode == VOIDmode
+ 	      || GET_MODE (op) == VOIDmode)
+ 	  && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+-	  && LEGITIMATE_CONSTANT_P (op));
++	  && targetm.legitimate_constant_p (mode == VOIDmode
++					    ? GET_MODE (op)
++					    : mode, op));
+ }
+ 
+ /* Returns 1 if OP is an operand that is a CONST_INT.  */
+Index: gcc-4_6-branch/gcc/reload.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/reload.c	2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/reload.c	2011-09-16 20:16:00.277564886 -0700
+@@ -4721,7 +4721,8 @@
+ 	    simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
+ 				 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
+ 	  gcc_assert (tem);
+-	  if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
++	  if (CONSTANT_P (tem)
++	      && !targetm.legitimate_constant_p (GET_MODE (x), tem))
+ 	    {
+ 	      tem = force_const_mem (GET_MODE (x), tem);
+ 	      i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
+@@ -6049,7 +6050,7 @@
+ 			   enum reload_type type, int ind_levels)
+ {
+   if (CONSTANT_P (x)
+-      && (! LEGITIMATE_CONSTANT_P (x)
++      && (!targetm.legitimate_constant_p (mode, x)
+ 	  || targetm.preferred_reload_class (x, rclass) == NO_REGS))
+     {
+       x = force_const_mem (mode, x);
+@@ -6059,7 +6060,7 @@
+ 
+   else if (GET_CODE (x) == PLUS
+ 	   && CONSTANT_P (XEXP (x, 1))
+-	   && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
++	   && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
+ 	       || targetm.preferred_reload_class (XEXP (x, 1), rclass)
+ 		   == NO_REGS))
+     {
+Index: gcc-4_6-branch/gcc/reload1.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/reload1.c	2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/reload1.c	2011-09-16 20:16:00.277564886 -0700
+@@ -4155,6 +4155,9 @@
+ 		}
+ 	      else if (function_invariant_p (x))
+ 		{
++		  enum machine_mode mode;
++
++		  mode = GET_MODE (SET_DEST (set));
+ 		  if (GET_CODE (x) == PLUS)
+ 		    {
+ 		      /* This is PLUS of frame pointer and a constant,
+@@ -4167,12 +4170,11 @@
+ 		      reg_equiv_invariant[i] = x;
+ 		      num_eliminable_invariants++;
+ 		    }
+-		  else if (LEGITIMATE_CONSTANT_P (x))
++		  else if (targetm.legitimate_constant_p (mode, x))
+ 		    reg_equiv_constant[i] = x;
+ 		  else
+ 		    {
+-		      reg_equiv_memory_loc[i]
+-			= force_const_mem (GET_MODE (SET_DEST (set)), x);
++		      reg_equiv_memory_loc[i] = force_const_mem (mode, x);
+ 		      if (! reg_equiv_memory_loc[i])
+ 			reg_equiv_init[i] = NULL_RTX;
+ 		    }
+Index: gcc-4_6-branch/gcc/stor-layout.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/stor-layout.c	2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/stor-layout.c	2011-09-16 20:16:00.287564867 -0700
+@@ -546,6 +546,34 @@
+   return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
+ }
+ 
++/* Return the natural mode of an array, given that it is SIZE bytes in
++   total and has elements of type ELEM_TYPE.  */
++
++static enum machine_mode
++mode_for_array (tree elem_type, tree size)
++{
++  tree elem_size;
++  unsigned HOST_WIDE_INT int_size, int_elem_size;
++  bool limit_p;
++
++  /* One-element arrays get the component type's mode.  */
++  elem_size = TYPE_SIZE (elem_type);
++  if (simple_cst_equal (size, elem_size))
++    return TYPE_MODE (elem_type);
++
++  limit_p = true;
++  if (host_integerp (size, 1) && host_integerp (elem_size, 1))
++    {
++      int_size = tree_low_cst (size, 1);
++      int_elem_size = tree_low_cst (elem_size, 1);
++      if (int_elem_size > 0
++	  && int_size % int_elem_size == 0
++	  && targetm.array_mode_supported_p (TYPE_MODE (elem_type),
++					     int_size / int_elem_size))
++	limit_p = false;
++    }
++  return mode_for_size_tree (size, MODE_INT, limit_p);
++}
+ 
+ /* Subroutine of layout_decl: Force alignment required for the data type.
+    But if the decl itself wants greater alignment, don't override that.  */
+@@ -2039,14 +2067,8 @@
+ 	    && (TYPE_MODE (TREE_TYPE (type)) != BLKmode
+ 		|| TYPE_NO_FORCE_BLK (TREE_TYPE (type))))
+ 	  {
+-	    /* One-element arrays get the component type's mode.  */
+-	    if (simple_cst_equal (TYPE_SIZE (type),
+-				  TYPE_SIZE (TREE_TYPE (type))))
+-	      SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type)));
+-	    else
+-	      SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type),
+-						       MODE_INT, 1));
+-
++	    SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type),
++						 TYPE_SIZE (type)));
+ 	    if (TYPE_MODE (type) != BLKmode
+ 		&& STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
+ 		&& TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
+Index: gcc-4_6-branch/gcc/target.def
+===================================================================
+--- gcc-4_6-branch.orig/gcc/target.def	2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/target.def	2011-09-16 20:16:00.287564867 -0700
+@@ -1344,6 +1344,13 @@
+  unsigned, (unsigned nunroll, struct loop *loop),
+  NULL)
+ 
++/* True if X is a legitimate MODE-mode immediate operand.  */
++DEFHOOK
++(legitimate_constant_p,
++ "",
++ bool, (enum machine_mode mode, rtx x),
++ default_legitimate_constant_p)
++
+ /* True if the constant X cannot be placed in the constant pool.  */
+ DEFHOOK
+ (cannot_force_const_mem,
+@@ -1611,6 +1618,38 @@
+  bool, (enum machine_mode mode),
+  hook_bool_mode_false)
+ 
++/* True if we should try to use a scalar mode to represent an array,
++   overriding the usual MAX_FIXED_MODE limit.  */
++DEFHOOK
++(array_mode_supported_p,
++ "Return true if GCC should try to use a scalar mode to store an array\n\
++of @var{nelems} elements, given that each element has mode @var{mode}.\n\
++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit\n\
++and allows GCC to use any defined integer mode.\n\
++\n\
++One use of this hook is to support vector load and store operations\n\
++that operate on several homogeneous vectors.  For example, ARM NEON\n\
++has operations like:\n\
++\n\
++@smallexample\n\
++int8x8x3_t vld3_s8 (const int8_t *)\n\
++@end smallexample\n\
++\n\
++where the return type is defined as:\n\
++\n\
++@smallexample\n\
++typedef struct int8x8x3_t\n\
++@{\n\
++  int8x8_t val[3];\n\
++@} int8x8x3_t;\n\
++@end smallexample\n\
++\n\
++If this hook allows @code{val} to have a scalar mode, then\n\
++@code{int8x8x3_t} can have the same mode.  GCC can then store\n\
++@code{int8x8x3_t}s in registers rather than forcing them onto the stack.",
++ bool, (enum machine_mode mode, unsigned HOST_WIDE_INT nelems),
++ hook_bool_mode_uhwi_false)
++
+ /* Compute cost of moving data from a register of class FROM to one of
+    TO, using MODE.  */
+ DEFHOOK
+Index: gcc-4_6-branch/gcc/targhooks.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/targhooks.c	2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/targhooks.c	2011-09-16 20:16:00.287564867 -0700
+@@ -1519,4 +1519,15 @@
+     { OPT_LEVELS_NONE, 0, NULL, 0 }
+   };
+ 
++bool
++default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
++			       rtx x ATTRIBUTE_UNUSED)
++{
++#ifdef LEGITIMATE_CONSTANT_P
++  return LEGITIMATE_CONSTANT_P (x);
++#else
++  return true;
++#endif
++}
++
+ #include "gt-targhooks.h"
+Index: gcc-4_6-branch/gcc/targhooks.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/targhooks.h	2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/targhooks.h	2011-09-16 20:16:00.287564867 -0700
+@@ -183,3 +183,4 @@
+ 
+ extern void *default_get_pch_validity (size_t *);
+ extern const char *default_pch_valid_p (const void *, size_t);
++extern bool default_legitimate_constant_p (enum machine_mode, rtx);
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c	2011-09-16 20:16:00.287564867 -0700
+@@ -0,0 +1,27 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++uint32_t buffer[12];
++
++void __attribute__((noinline))
++foo (uint32_t *a)
++{
++  uint32x4x3_t x;
++
++  x = vld3q_u32 (a);
++  x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
++  vst3q_u32 (a, x);
++}
++
++int
++main (void)
++{
++  buffer[0] = 1;
++  buffer[1] = 2;
++  foo (buffer);
++  return buffer[0] != 3;
++}
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c	2011-09-16 20:16:00.287564867 -0700
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++uint32_t buffer[64];
++
++void __attribute__((noinline))
++foo (uint32_t *a)
++{
++  uint32x4x3_t x;
++
++  x = vld3q_u32 (a);
++  a[35] = 1;
++  vst3q_lane_u32 (a + 32, x, 1);
++}
++
++int
++main (void)
++{
++  foo (buffer);
++  return buffer[35] != 1;
++}
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c	2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+   out_float32x4_t = vld1q_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c	2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x8_t = vld1q_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c	2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x16_t = vld1q_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c	2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+   out_int16x8_t = vld1q_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c	2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+   out_int32x4_t = vld1q_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c	2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+   out_int64x2_t = vld1q_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c	2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+   out_int8x16_t = vld1q_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c	2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x8_t = vld1q_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c	2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x4_t = vld1q_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c	2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x2_t = vld1q_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c	2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x16_t = vld1q_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c	2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+   out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_float32x4_t = vld1q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x8_t = vld1q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x16_t = vld1q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int16x8_t = vld1q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int32x4_t = vld1q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int64x2_t = vld1q_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int8x16_t = vld1q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x8_t = vld1q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x4_t = vld1q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x2_t = vld1q_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x16_t = vld1q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2_t = vld1_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4_t = vld1_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8_t = vld1_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4_t = vld1_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2_t = vld1_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1_t = vld1_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8_t = vld1_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4_t = vld1_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c	2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2_t = vld1_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c	2011-09-16 20:16:00.367564848 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1_t = vld1_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c	2011-09-16 20:16:00.367564848 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8_t = vld1_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c	2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+   out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c	2011-09-16 20:16:00.367564848 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2_t = vld1_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4_t = vld1_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8_t = vld1_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4_t = vld1_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2_t = vld1_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1_t = vld1_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8_t = vld1_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4_t = vld1_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2_t = vld1_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c	2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1_t = vld1_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c	2011-09-16 20:16:00.387564830 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8_t = vld1_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c	2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+   out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c	2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c	2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+   out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c	2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+   out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c	2011-09-16 20:16:00.397564843 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c	2011-09-16 20:16:00.397564843 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_float32x4x2_t = vld2q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_poly16x8x2_t = vld2q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_poly8x16x2_t = vld2q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_int16x8x2_t = vld2q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_int32x4x2_t = vld2q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_int8x16x2_t = vld2q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c	2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+   out_uint16x8x2_t = vld2q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,6 +15,6 @@
+   out_uint32x4x2_t = vld2q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,6 +15,6 @@
+   out_uint8x16x2_t = vld2q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2x2_t = vld2_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4x2_t = vld2_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8x2_t = vld2_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4x2_t = vld2_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2x2_t = vld2_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c	2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1x2_t = vld2_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c	2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8x2_t = vld2_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c	2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4x2_t = vld2_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c	2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2x2_t = vld2_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c	2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1x2_t = vld2_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c	2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8x2_t = vld2_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c	2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+   out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c	2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2x2_t = vld2_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c	2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4x2_t = vld2_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c	2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8x2_t = vld2_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c	2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4x2_t = vld2_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c	2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2x2_t = vld2_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c	2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1x2_t = vld2_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c	2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8x2_t = vld2_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c	2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4x2_t = vld2_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c	2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2x2_t = vld2_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c	2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1x2_t = vld2_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c	2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8x2_t = vld2_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c	2011-09-16 20:16:00.437564924 -0700
+@@ -16,5 +16,5 @@
+   out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c	2011-09-16 20:16:00.437564924 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c	2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+   out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c	2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+   out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c	2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c	2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_float32x4x3_t = vld3q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_poly16x8x3_t = vld3q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_poly8x16x3_t = vld3q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_int16x8x3_t = vld3q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_int32x4x3_t = vld3q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_int8x16x3_t = vld3q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_uint16x8x3_t = vld3q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c	2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+   out_uint32x4x3_t = vld3q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,6 +15,6 @@
+   out_uint8x16x3_t = vld3q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2x3_t = vld3_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4x3_t = vld3_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8x3_t = vld3_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4x3_t = vld3_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2x3_t = vld3_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1x3_t = vld3_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8x3_t = vld3_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4x3_t = vld3_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2x3_t = vld3_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1x3_t = vld3_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8x3_t = vld3_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+   out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2x3_t = vld3_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4x3_t = vld3_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8x3_t = vld3_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4x3_t = vld3_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2x3_t = vld3_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c	2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1x3_t = vld3_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8x3_t = vld3_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4x3_t = vld3_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2x3_t = vld3_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1x3_t = vld3_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8x3_t = vld3_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c	2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+   out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c	2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c	2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+   out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c	2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+   out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c	2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c	2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,6 +15,6 @@
+   out_float32x4x4_t = vld4q_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,6 +15,6 @@
+   out_poly16x8x4_t = vld4q_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c	2011-09-16 20:16:00.467564964 -0700
+@@ -15,6 +15,6 @@
+   out_poly8x16x4_t = vld4q_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+   out_int16x8x4_t = vld4q_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+   out_int32x4x4_t = vld4q_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+   out_int8x16x4_t = vld4q_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+   out_uint16x8x4_t = vld4q_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+   out_uint32x4x4_t = vld4q_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+   out_uint8x16x4_t = vld4q_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2x4_t = vld4_dup_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4x4_t = vld4_dup_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8x4_t = vld4_dup_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4x4_t = vld4_dup_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c	2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2x4_t = vld4_dup_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c	2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1x4_t = vld4_dup_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c	2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8x4_t = vld4_dup_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c	2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4x4_t = vld4_dup_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c	2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2x4_t = vld4_dup_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c	2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1x4_t = vld4_dup_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c	2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8x4_t = vld4_dup_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c	2011-09-16 20:16:00.487565006 -0700
+@@ -16,5 +16,5 @@
+   out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c	2011-09-16 20:16:00.487565006 -0700
+@@ -16,5 +16,5 @@
+   out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c	2011-09-16 20:16:00.487565006 -0700
+@@ -16,5 +16,5 @@
+   out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c	2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+   out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c	2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+   out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c	2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+   out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c	2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+   out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c	2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+   out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c	2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+   out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_float32x2x4_t = vld4_f32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_poly16x4x4_t = vld4_p16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_poly8x8x4_t = vld4_p8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_int16x4x4_t = vld4_s16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_int32x2x4_t = vld4_s32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_int64x1x4_t = vld4_s64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_int8x8x4_t = vld4_s8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c	2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+   out_uint16x4x4_t = vld4_u16 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c	2011-09-16 20:16:00.507565013 -0700
+@@ -15,5 +15,5 @@
+   out_uint32x2x4_t = vld4_u32 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c	2011-09-16 20:16:00.507565013 -0700
+@@ -15,5 +15,5 @@
+   out_uint64x1x4_t = vld4_u64 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c	2011-09-16 20:16:00.507565013 -0700
+@@ -15,5 +15,5 @@
+   out_uint8x8x4_t = vld4_u8 (0);
+ }
+ 
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c	2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+   vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c	2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+   vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+   vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c	2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+   vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,6 +16,6 @@
+   vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c	2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+   vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c	2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+   vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+   vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c	2011-09-16 20:16:00.557565092 -0700
+@@ -16,6 +16,6 @@
+   vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+   vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c	2011-09-16 20:16:00.567565108 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c	2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c	2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+   vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+   vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+   vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+   vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+   vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+   vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+   vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+   vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+   vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+   vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+   vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c	2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+   vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+   vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+   vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+   vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+   vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4f32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u16.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u32.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u64.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u8.c	2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c	2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+   vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+ }
+ 
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c	2011-09-16 20:16:00.617565191 -0700
+@@ -0,0 +1,9 @@
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++int __attribute__ ((vector_size (32))) x;
++void
++foo (void)
++{
++  x <<= x;
++}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch
new file mode 100644
index 0000000000..004f0131cf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch
@@ -0,0 +1,21 @@
+2011-05-06  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	From Sergey Grechanik  <mouseentity@ispras.ru>, approved for mainline
+
+	* config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS
+	for constant vectors.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-05-03 15:18:07 +0000
++++ new/gcc/config/arm/arm.c	2011-05-06 11:33:02 +0000
+@@ -9193,7 +9193,7 @@
+   /* The neon move patterns handle all legitimate vector and struct
+      addresses.  */
+   if (TARGET_NEON
+-      && MEM_P (x)
++      && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
+       && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+ 	  || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
+ 	  || VALID_NEON_STRUCT_MODE (mode)))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch
new file mode 100644
index 0000000000..ce0272431d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch
@@ -0,0 +1,24 @@
+2011-05-12  Michael Hope  <michael.hope@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-05-05  Michael Hope  <michael.hope@linaro.org>
+
+	PR pch/45979
+	* config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for
+	__ARM_EABI__ hosts.
+
+=== modified file 'gcc/config/host-linux.c'
+--- old/gcc/config/host-linux.c	2010-11-29 14:09:41 +0000
++++ new/gcc/config/host-linux.c	2011-05-06 20:19:30 +0000
+@@ -84,6 +84,8 @@
+ # define TRY_EMPTY_VM_SPACE	0x60000000
+ #elif defined(__mc68000__)
+ # define TRY_EMPTY_VM_SPACE	0x40000000
++#elif defined(__ARM_EABI__)
++# define TRY_EMPTY_VM_SPACE	0x60000000
+ #else
+ # define TRY_EMPTY_VM_SPACE	0
+ #endif
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch
new file mode 100644
index 0000000000..7885b7af49
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch
@@ -0,0 +1,640 @@
+2011-05-13  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	* loop-doloop.c (doloop_condition_get): Support new form of
+	doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
+	* config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
+	(doloop_end): New.
+	* config/arm/arm.md (*addsi3_compare0): Remove "*".
+	* params.def (sms-min-sc): New param flag.
+	* doc/invoke.texi (sms-min-sc): Document it.
+	* ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge
+	enters the branch create an anti edge in the opposite direction
+	to prevent the creation of reg-moves.
+	* modulo-sched.c: Adjust comment to reflect the fact we are
+	scheduling closing branch.
+	(PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine.
+	(stage_count): New field in struct partial_schedule.
+	(calculate_stage_count): New function.
+	(normalize_sched_times): Rename to reset_sched_times and handle
+	incrementing the sched time of the nodes by a constant value
+	passed as parameter.
+	(duplicate_insns_of_cycles): Skip closing branch.
+	(sms_schedule_by_order): Schedule closing branch.
+	(ps_insn_find_column): Handle closing branch.
+	(sms_schedule): Call reset_sched_times and adjust the code to
+	support scheduling of the closing branch. Use sms-min-sc.
+	Support new form of doloop pattern.
+	(ps_insert_empty_row): Update calls to normalize_sched_times
+	and rotate_partial_schedule functions.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-05-06 11:28:27 +0000
++++ new/gcc/config/arm/arm.md	2011-05-13 13:42:39 +0000
+@@ -791,7 +791,7 @@
+   ""
+ )
+ 
+-(define_insn "*addsi3_compare0"
++(define_insn "addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+ 	 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r")
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2011-01-03 20:52:22 +0000
++++ new/gcc/config/arm/thumb2.md	2011-05-11 07:15:47 +0000
+@@ -836,7 +836,7 @@
+   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
+ )
+ 
+-(define_insn "*thumb2_addsi3_compare0"
++(define_insn "thumb2_addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+ 	  (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
+@@ -1118,3 +1118,54 @@
+   "
+   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
+   ")
++
++;; Define the subtract-one-and-jump insns so loop.c
++;; knows what to generate.
++(define_expand "doloop_end"
++  [(use (match_operand 0 "" ""))      ; loop pseudo
++   (use (match_operand 1 "" ""))      ; iterations; zero if unknown
++   (use (match_operand 2 "" ""))      ; max iterations
++   (use (match_operand 3 "" ""))      ; loop level
++   (use (match_operand 4 "" ""))]     ; label
++  "TARGET_32BIT"
++  "
++ {
++   /* Currently SMS relies on the do-loop pattern to recognize loops
++      where (1) the control part consists of all insns defining and/or
++      using a certain 'count' register and (2) the loop count can be
++      adjusted by modifying this register prior to the loop.
++      ??? The possible introduction of a new block to initialize the
++      new IV can potentially affect branch optimizations.  */
++   if (optimize > 0 && flag_modulo_sched)
++   {
++     rtx s0;
++     rtx bcomp;
++     rtx loc_ref;
++     rtx cc_reg;
++     rtx insn;
++     rtx cmp;
++
++    /* Only use this on innermost loops.  */
++     if (INTVAL (operands[3]) > 1)
++       FAIL;
++     if (GET_MODE (operands[0]) != SImode)
++       FAIL;
++
++     s0 = operands [0];
++     if (TARGET_THUMB2)
++       insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
++     else
++       insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
++
++     cmp = XVECEXP (PATTERN (insn), 0, 0);
++     cc_reg = SET_DEST (cmp);
++     bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
++     loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
++     emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
++                                  gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
++                                                        loc_ref, pc_rtx)));
++     DONE;
++   }else
++      FAIL;
++}")
++
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2010-11-30 11:41:24 +0000
++++ new/gcc/ddg.c	2011-05-11 07:15:47 +0000
+@@ -197,6 +197,11 @@
+         }
+     }
+ 
++  /* If a true dep edge enters the branch create an anti edge in the
++     opposite direction to prevent the creation of reg-moves.  */
++  if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
++    create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
++
+    latency = dep_cost (link);
+    e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
+    add_edge_to_ddg (g, e);
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2011-04-18 11:31:29 +0000
++++ new/gcc/doc/invoke.texi	2011-05-11 07:15:47 +0000
+@@ -8730,6 +8730,10 @@
+ The maximum number of best instructions in the ready list that are considered
+ for renaming in the selective scheduler.  The default value is 2.
+ 
++@item sms-min-sc
++The minimum value of stage count that swing modulo scheduler will
++generate.  The default value is 2.
++
+ @item max-last-value-rtl
+ The maximum size measured as number of RTLs that can be recorded in an expression
+ in combiner for a pseudo register as last known value of that register.  The default
+
+=== modified file 'gcc/loop-doloop.c'
+--- old/gcc/loop-doloop.c	2010-11-30 11:41:24 +0000
++++ new/gcc/loop-doloop.c	2011-05-11 07:15:47 +0000
+@@ -78,6 +78,8 @@
+   rtx inc_src;
+   rtx condition;
+   rtx pattern;
++  rtx cc_reg = NULL_RTX;
++  rtx reg_orig = NULL_RTX;
+ 
+   /* The canonical doloop pattern we expect has one of the following
+      forms:
+@@ -96,7 +98,16 @@
+      2)  (set (reg) (plus (reg) (const_int -1))
+          (set (pc) (if_then_else (reg != 0)
+ 	                         (label_ref (label))
+-			         (pc))).  */
++			         (pc))).  
++
++     Some targets (ARM) do the comparison before the branch, as in the
++     following form:
++
++     3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0)))
++                   (set (reg) (plus (reg) (const_int -1)))])
++        (set (pc) (if_then_else (cc == NE)
++                                (label_ref (label))
++                                (pc))) */
+ 
+   pattern = PATTERN (doloop_pat);
+ 
+@@ -104,19 +115,47 @@
+     {
+       rtx cond;
+       rtx prev_insn = prev_nondebug_insn (doloop_pat);
++      rtx cmp_arg1, cmp_arg2;
++      rtx cmp_orig;
+ 
+-      /* We expect the decrement to immediately precede the branch.  */
++      /* In case the pattern is not PARALLEL we expect two forms
++	 of doloop which are cases 2) and 3) above: in case 2) the
++	 decrement immediately precedes the branch, while in case 3)
++	 the compare and decrement instructions immediately precede
++	 the branch.  */
+ 
+       if (prev_insn == NULL_RTX || !INSN_P (prev_insn))
+         return 0;
+ 
+       cmp = pattern;
+-      inc = PATTERN (PREV_INSN (doloop_pat));
++      if (GET_CODE (PATTERN (prev_insn)) == PARALLEL)
++        {
++	  /* The third case: the compare and decrement instructions
++	     immediately precede the branch.  */
++	  cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0);
++	  if (GET_CODE (cmp_orig) != SET)
++	    return 0;
++	  if (GET_CODE (SET_SRC (cmp_orig)) != COMPARE)
++	    return 0;
++	  cmp_arg1 = XEXP (SET_SRC (cmp_orig), 0);
++          cmp_arg2 = XEXP (SET_SRC (cmp_orig), 1);
++	  if (cmp_arg2 != const0_rtx 
++	      || GET_CODE (cmp_arg1) != PLUS)
++	    return 0;
++	  reg_orig = XEXP (cmp_arg1, 0);
++	  if (XEXP (cmp_arg1, 1) != GEN_INT (-1) 
++	      || !REG_P (reg_orig))
++	    return 0;
++	  cc_reg = SET_DEST (cmp_orig);
++	  
++	  inc = XVECEXP (PATTERN (prev_insn), 0, 1);
++	}
++      else
++        inc = PATTERN (prev_insn);
+       /* We expect the condition to be of the form (reg != 0)  */
+       cond = XEXP (SET_SRC (cmp), 0);
+       if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx)
+         return 0;
+-
+     }
+   else
+     {
+@@ -162,11 +201,15 @@
+     return 0;
+ 
+   if ((XEXP (condition, 0) == reg)
++      /* For the third case:  */  
++      || ((cc_reg != NULL_RTX)
++	  && (XEXP (condition, 0) == cc_reg)
++	  && (reg_orig == reg))
+       || (GET_CODE (XEXP (condition, 0)) == PLUS
+-		   && XEXP (XEXP (condition, 0), 0) == reg))
++	  && XEXP (XEXP (condition, 0), 0) == reg))
+    {
+      if (GET_CODE (pattern) != PARALLEL)
+-     /*  The second form we expect:
++     /*  For the second form we expect:
+ 
+          (set (reg) (plus (reg) (const_int -1))
+          (set (pc) (if_then_else (reg != 0)
+@@ -181,7 +224,24 @@
+                      (set (reg) (plus (reg) (const_int -1)))
+                      (additional clobbers and uses)])
+ 
+-         So we return that form instead.
++        For the third form we expect:
++
++        (parallel [(set (cc) (compare ((plus (reg) (const_int -1)), 0))
++                   (set (reg) (plus (reg) (const_int -1)))])
++        (set (pc) (if_then_else (cc == NE)
++                                (label_ref (label))
++                                (pc))) 
++
++        which is equivalent to the following:
++
++        (parallel [(set (cc) (compare (reg,  1))
++                   (set (reg) (plus (reg) (const_int -1)))
++                   (set (pc) (if_then_else (NE == cc)
++                                           (label_ref (label))
++                                           (pc))))])
++
++        So we return the second form instead for the two cases.
++
+      */
+         condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx);
+ 
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-02-14 17:59:10 +0000
++++ new/gcc/modulo-sched.c	2011-05-11 07:15:47 +0000
+@@ -84,14 +84,13 @@
+       II cycles (i.e. use register copies to prevent a def from overwriting
+       itself before reaching the use).
+ 
+-    SMS works with countable loops (1) whose control part can be easily
+-    decoupled from the rest of the loop and (2) whose loop count can
+-    be easily adjusted.  This is because we peel a constant number of
+-    iterations into a prologue and epilogue for which we want to avoid
+-    emitting the control part, and a kernel which is to iterate that
+-    constant number of iterations less than the original loop.  So the
+-    control part should be a set of insns clearly identified and having
+-    its own iv, not otherwise used in the loop (at-least for now), which
++    SMS works with countable loops whose loop count can be easily
++    adjusted.  This is because we peel a constant number of iterations
++    into a prologue and epilogue for which we want to avoid emitting
++    the control part, and a kernel which is to iterate that constant
++    number of iterations less than the original loop.  So the control
++    part should be a set of insns clearly identified and having its
++    own iv, not otherwise used in the loop (at-least for now), which
+     initializes a register before the loop to the number of iterations.
+     Currently SMS relies on the do-loop pattern to recognize such loops,
+     where (1) the control part comprises of all insns defining and/or
+@@ -116,8 +115,10 @@
+ 
+ /* The number of different iterations the nodes in ps span, assuming
+    the stage boundaries are placed efficiently.  */
+-#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
+-			     + 1 + (ps)->ii - 1) / (ps)->ii)
++#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \
++                         + 1 + ii - 1) / ii)
++/* The stage count of ps.  */
++#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
+ 
+ /* A single instruction in the partial schedule.  */
+ struct ps_insn
+@@ -155,6 +156,8 @@
+   int max_cycle;
+ 
+   ddg_ptr g;	/* The DDG of the insns in the partial schedule.  */
++
++  int stage_count;  /* The stage count of the partial schedule.  */
+ };
+ 
+ /* We use this to record all the register replacements we do in
+@@ -195,7 +198,7 @@
+                                     rtx, rtx);
+ static void duplicate_insns_of_cycles (partial_schedule_ptr,
+ 				       int, int, int, rtx);
+-
++static int calculate_stage_count (partial_schedule_ptr ps);
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+ #define SCHED_FIRST_REG_MOVE(x) \
+@@ -310,10 +313,10 @@
+      either a single (parallel) branch-on-count or a (non-parallel)
+      branch immediately preceded by a single (decrement) insn.  */
+   first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
+-                             : PREV_INSN (tail));
++                             : prev_nondebug_insn (tail));
+ 
+   for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
+-    if (reg_mentioned_p (reg, insn))
++    if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn))
+       {
+         if (dump_file)
+         {
+@@ -569,13 +572,12 @@
+     }
+ }
+ 
+-/* Bump the SCHED_TIMEs of all nodes to start from zero.  Set the values
+-   of SCHED_ROW and SCHED_STAGE.  */
++/* Bump the SCHED_TIMEs of all nodes by AMOUNT.  Set the values of
++   SCHED_ROW and SCHED_STAGE.  */
+ static void
+-normalize_sched_times (partial_schedule_ptr ps)
++reset_sched_times (partial_schedule_ptr ps, int amount)
+ {
+   int row;
+-  int amount = PS_MIN_CYCLE (ps);
+   int ii = ps->ii;
+   ps_insn_ptr crr_insn;
+ 
+@@ -584,19 +586,43 @@
+       {
+ 	ddg_node_ptr u = crr_insn->node;
+ 	int normalized_time = SCHED_TIME (u) - amount;
++	int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
++        int sc_until_cycle_zero, stage;
+ 
+-	if (dump_file)
+-	  fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
+-		   min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME
+-		   (u), ps->min_cycle);
++        if (dump_file)
++          {
++            /* Print the scheduling times after the rotation.  */
++            fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
++                     "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
++                     INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
++                     normalized_time);
++            if (JUMP_P (crr_insn->node->insn))
++              fprintf (dump_file, " (branch)");
++            fprintf (dump_file, "\n");
++          }
++	
+ 	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+ 	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+ 	SCHED_TIME (u) = normalized_time;
+-	SCHED_ROW (u) = normalized_time % ii;
+-	SCHED_STAGE (u) = normalized_time / ii;
++	SCHED_ROW (u) = SMODULO (normalized_time, ii);
++      
++        /* The calculation of stage count is done adding the number
++           of stages before cycle zero and after cycle zero.  */
++	sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
++	
++	if (SCHED_TIME (u) < 0)
++	  {
++	    stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
++	    SCHED_STAGE (u) = sc_until_cycle_zero - stage;
++	  }
++	else
++	  {
++	    stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
++	    SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
++	  }
+       }
+ }
+-
++ 
+ /* Set SCHED_COLUMN of each node according to its position in PS.  */
+ static void
+ set_columns_for_ps (partial_schedule_ptr ps)
+@@ -646,9 +672,12 @@
+ 
+         /* Do not duplicate any insn which refers to count_reg as it
+            belongs to the control part.
++           The closing branch is scheduled as well and thus should
++           be ignored.
+            TODO: This should be done by analyzing the control part of
+            the loop.  */
+-        if (reg_mentioned_p (count_reg, u_node->insn))
++        if (reg_mentioned_p (count_reg, u_node->insn)
++            || JUMP_P (ps_ij->node->insn))
+           continue;
+ 
+ 	if (for_prolog)
+@@ -1009,9 +1038,11 @@
+ 	continue;
+       }
+ 
+-      /* Don't handle BBs with calls or barriers, or !single_set insns,
+-         or auto-increment insns (to avoid creating invalid reg-moves
+-         for the auto-increment insns).
++      /* Don't handle BBs with calls or barriers or auto-increment insns 
++	 (to avoid creating invalid reg-moves for the auto-increment insns),
++	 or !single_set with the exception of instructions that include
++	 count_reg---these instructions are part of the control part
++	 that do-loop recognizes.
+          ??? Should handle auto-increment insns.
+          ??? Should handle insns defining subregs.  */
+      for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
+@@ -1021,7 +1052,8 @@
+         if (CALL_P (insn)
+             || BARRIER_P (insn)
+             || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
+-                && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
++                && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
++                && !reg_mentioned_p (count_reg, insn))
+             || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
+             || (INSN_P (insn) && (set = single_set (insn))
+                 && GET_CODE (SET_DEST (set)) == SUBREG))
+@@ -1049,7 +1081,11 @@
+ 	  continue;
+ 	}
+ 
+-      if (! (g = create_ddg (bb, 0)))
++      /* Always schedule the closing branch with the rest of the
++         instructions. The branch is rotated to be in row ii-1 at the
++         end of the scheduling procedure to make sure it's the last
++         instruction in the iteration.  */
++      if (! (g = create_ddg (bb, 1)))
+         {
+           if (dump_file)
+ 	    fprintf (dump_file, "SMS create_ddg failed\n");
+@@ -1157,14 +1193,17 @@
+ 
+       ps = sms_schedule_by_order (g, mii, maxii, node_order);
+ 
+-      if (ps){
+-	stage_count = PS_STAGE_COUNT (ps);
+-        gcc_assert(stage_count >= 1);
+-      }
++       if (ps)
++       {
++         stage_count = calculate_stage_count (ps);
++         gcc_assert(stage_count >= 1);
++         PS_STAGE_COUNT(ps) = stage_count;
++       }
+ 
+-      /* Stage count of 1 means that there is no interleaving between
+-         iterations, let the scheduling passes do the job.  */
+-      if (stage_count <= 1
++      /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
++         1 means that there is no interleaving between iterations thus
++         we let the scheduling passes do the job in this case.  */
++      if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
+ 	  || (count_init && (loop_count <= stage_count))
+ 	  || (flag_branch_probabilities && (trip_count <= stage_count)))
+ 	{
+@@ -1182,32 +1221,24 @@
+       else
+ 	{
+ 	  struct undo_replace_buff_elem *reg_move_replaces;
+-
+-	  if (dump_file)
+-	    {
++          int amount = SCHED_TIME (g->closing_branch) + 1;
++	  
++	  /* Set the stage boundaries.	The closing_branch was scheduled
++	     and should appear in the last (ii-1) row.  */
++	  reset_sched_times (ps, amount);
++	  rotate_partial_schedule (ps, amount);
++	  set_columns_for_ps (ps);
++
++	  canon_loop (loop);
++
++          if (dump_file)
++            {
+ 	      fprintf (dump_file,
+ 		       "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
+ 		       stage_count);
+ 	      print_partial_schedule (ps, dump_file);
+-	      fprintf (dump_file,
+-		       "SMS Branch (%d) will later be scheduled at cycle %d.\n",
+-		       g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
+ 	    }
+-
+-	  /* Set the stage boundaries.  If the DDG is built with closing_branch_deps,
+-	     the closing_branch was scheduled and should appear in the last (ii-1)
+-	     row.  Otherwise, we are free to schedule the branch, and we let nodes
+-	     that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
+-	     row; this should reduce stage_count to minimum.
+-             TODO: Revisit the issue of scheduling the insns of the
+-             control part relative to the branch when the control part
+-             has more than one insn.  */
+-	  normalize_sched_times (ps);
+-	  rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
+-	  set_columns_for_ps (ps);
+-
+-	  canon_loop (loop);
+-
++ 
+           /* case the BCT count is not known , Do loop-versioning */
+ 	  if (count_reg && ! count_init)
+             {
+@@ -1760,12 +1791,6 @@
+ 	      continue;
+ 	    }
+ 
+-	  if (JUMP_P (insn)) /* Closing branch handled later.  */
+-	    {
+-	      RESET_BIT (tobe_scheduled, u);
+-	      continue;
+-	    }
+-
+ 	  if (TEST_BIT (sched_nodes, u))
+ 	    continue;
+ 
+@@ -1893,8 +1918,8 @@
+   if (dump_file)
+     fprintf (dump_file, "split_row=%d\n", split_row);
+ 
+-  normalize_sched_times (ps);
+-  rotate_partial_schedule (ps, ps->min_cycle);
++  reset_sched_times (ps, PS_MIN_CYCLE (ps));
++  rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
+ 
+   rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
+   for (row = 0; row < split_row; row++)
+@@ -2571,6 +2596,7 @@
+   ps_insn_ptr next_ps_i;
+   ps_insn_ptr first_must_follow = NULL;
+   ps_insn_ptr last_must_precede = NULL;
++  ps_insn_ptr last_in_row = NULL;
+   int row;
+ 
+   if (! ps_i)
+@@ -2597,8 +2623,37 @@
+ 	  else
+             last_must_precede = next_ps_i;
+         }
++      /* The closing branch must be the last in the row.  */
++      if (must_precede 
++	  && TEST_BIT (must_precede, next_ps_i->node->cuid) 
++	  && JUMP_P (next_ps_i->node->insn))     
++	return false;
++             
++       last_in_row = next_ps_i;
+     }
+ 
++  /* The closing branch is scheduled as well.  Make sure there is no
++     dependent instruction after it as the branch should be the last
++     instruction in the row.  */
++  if (JUMP_P (ps_i->node->insn)) 
++    {
++      if (first_must_follow)
++	return false;
++      if (last_in_row)
++	{
++	  /* Make the branch the last in the row.  New instructions
++	     will be inserted at the beginning of the row or after the
++	     last must_precede instruction thus the branch is guaranteed
++	     to remain the last instruction in the row.  */
++	  last_in_row->next_in_row = ps_i;
++	  ps_i->prev_in_row = last_in_row;
++	  ps_i->next_in_row = NULL;
++	}
++      else
++	ps->rows[row] = ps_i;
++      return true;
++    }
++  
+   /* Now insert the node after INSERT_AFTER_PSI.  */
+ 
+   if (! last_must_precede)
+@@ -2820,6 +2875,24 @@
+   return ps_i;
+ }
+ 
++/* Calculate the stage count of the partial schedule PS.  The calculation
++   takes into account the rotation to bring the closing branch to row
++   ii-1.  */
++int
++calculate_stage_count (partial_schedule_ptr ps)
++{
++  int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
++  int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
++  int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
++  int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
++
++  /* The calculation of stage count is done adding the number of stages
++     before cycle zero and after cycle zero.  */ 
++  stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii);
++
++  return stage_count;
++}
++
+ /* Rotate the rows of PS such that insns scheduled at time
+    START_CYCLE will appear in row 0.  Updates max/min_cycles.  */
+ void
+
+=== modified file 'gcc/params.def'
+--- old/gcc/params.def	2011-04-18 11:31:29 +0000
++++ new/gcc/params.def	2011-05-11 07:15:47 +0000
+@@ -344,6 +344,11 @@
+ 	 "sms-max-ii-factor",
+ 	 "A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop",
+ 	 100, 0, 0)
++/* The minimum value of stage count that swing modulo scheduler will generate.  */
++DEFPARAM(PARAM_SMS_MIN_SC,
++        "sms-min-sc",
++        "The minimum value of stage count that swing modulo scheduler will generate.",
++        2, 1, 1)
+ DEFPARAM(PARAM_SMS_DFA_HISTORY,
+ 	 "sms-dfa-history",
+ 	 "The number of cycles the swing modulo scheduler considers when checking conflicts using DFA",
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch
new file mode 100644
index 0000000000..9c62102db5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch
@@ -0,0 +1,30 @@
+ 2011-05-13  Revital Eres  <revital.eres@linaro.org>
+ 
+ 	gcc/
+	* ddg.c (free_ddg_all_sccs): Free sccs field in struct ddg_all_sccs.
+	* modulo-sched.c (sms_schedule): Avoid unfreed memory when SMS fails.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-05-11 07:15:47 +0000
++++ new/gcc/ddg.c	2011-05-13 16:03:40 +0000
+@@ -1016,6 +1016,7 @@
+   for (i = 0; i < all_sccs->num_sccs; i++)
+     free_scc (all_sccs->sccs[i]);
+ 
++  free (all_sccs->sccs);
+   free (all_sccs);
+ }
+ 
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-05-11 07:15:47 +0000
++++ new/gcc/modulo-sched.c	2011-05-13 16:03:40 +0000
+@@ -1216,7 +1216,6 @@
+ 	      fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
+ 	      fprintf (dump_file, ")\n");
+ 	    }
+-	  continue;
+ 	}
+       else
+ 	{
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch
new file mode 100644
index 0000000000..c26ee5bde4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch
@@ -0,0 +1,134 @@
+2011-06-02  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	Backport from mainline:
+
+	2011-03-21  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* simplify-rtx.c (simplify_binary_operation_1): Handle
+	(xor (and A B) C) case when B and C are both constants.
+
+	gcc/testsuite/
+	* gcc.target/arm/xor-and.c: New.
+
+	2011-03-18  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	gcc/
+	* combine.c (try_combine): Do simplification only call of
+	subst() on i2 even when i1 is present. Update comments.
+
+	gcc/testsuite/
+	* gcc.target/arm/unsigned-extend-1.c: New.
+
+=== modified file 'gcc/combine.c'
+--- old/gcc/combine.c	2011-05-06 11:28:27 +0000
++++ new/gcc/combine.c	2011-05-27 14:31:18 +0000
+@@ -3089,7 +3089,7 @@
+       /* It is possible that the source of I2 or I1 may be performing
+ 	 an unneeded operation, such as a ZERO_EXTEND of something
+ 	 that is known to have the high part zero.  Handle that case
+-	 by letting subst look at the innermost one of them.
++	 by letting subst look at the inner insns.
+ 
+ 	 Another way to do this would be to have a function that tries
+ 	 to simplify a single insn instead of merging two or more
+@@ -3114,11 +3114,9 @@
+ 	      subst_low_luid = DF_INSN_LUID (i1);
+ 	      i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	    }
+-	  else
+-	    {
+-	      subst_low_luid = DF_INSN_LUID (i2);
+-	      i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
+-	    }
++
++	  subst_low_luid = DF_INSN_LUID (i2);
++	  i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
+ 	}
+ 
+       n_occurrences = 0;		/* `subst' counts here */
+
+=== modified file 'gcc/simplify-rtx.c'
+--- old/gcc/simplify-rtx.c	2011-03-26 09:24:06 +0000
++++ new/gcc/simplify-rtx.c	2011-05-27 14:31:18 +0000
+@@ -2484,6 +2484,46 @@
+ 							XEXP (op0, 1), mode),
+ 				    op1);
+ 
++      /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
++	 we can transform like this:
++            (A&B)^C == ~(A&B)&C | ~C&(A&B)
++                    == (~A|~B)&C | ~C&(A&B)    * DeMorgan's Law
++                    == ~A&C | ~B&C | A&(~C&B)  * Distribute and re-order
++	 Attempt a few simplifications when B and C are both constants.  */
++      if (GET_CODE (op0) == AND
++	  && CONST_INT_P (op1)
++	  && CONST_INT_P (XEXP (op0, 1)))
++	{
++	  rtx a = XEXP (op0, 0);
++	  rtx b = XEXP (op0, 1);
++	  rtx c = op1;
++	  HOST_WIDE_INT bval = INTVAL (b);
++	  HOST_WIDE_INT cval = INTVAL (c);
++
++	  rtx na_c
++	    = simplify_binary_operation (AND, mode,
++					 simplify_gen_unary (NOT, mode, a, mode),
++					 c);
++	  if ((~cval & bval) == 0)
++	    {
++	      /* Try to simplify ~A&C | ~B&C.  */
++	      if (na_c != NULL_RTX)
++		return simplify_gen_binary (IOR, mode, na_c,
++					    GEN_INT (~bval & cval));
++	    }
++	  else
++	    {
++	      /* If ~A&C is zero, simplify A&(~C&B) | ~B&C.  */
++	      if (na_c == const0_rtx)
++		{
++		  rtx a_nc_b = simplify_gen_binary (AND, mode, a,
++						    GEN_INT (~cval & bval));
++		  return simplify_gen_binary (IOR, mode, a_nc_b,
++					      GEN_INT (~bval & cval));
++		}
++	    }
++	}
++
+       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
+ 	 comparison if STORE_FLAG_VALUE is 1.  */
+       if (STORE_FLAG_VALUE == 1
+
+=== added file 'gcc/testsuite/gcc.target/arm/unsigned-extend-1.c'
+--- old/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c	2011-05-27 14:31:18 +0000
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv6" } */
++
++unsigned char foo (unsigned char c)
++{
++  return (c >= '0') && (c <= '9');
++}
++
++/* { dg-final { scan-assembler-not "uxtb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/xor-and.c'
+--- old/gcc/testsuite/gcc.target/arm/xor-and.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/xor-and.c	2011-05-27 14:31:18 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O -march=armv6" } */
++
++unsigned short foo (unsigned short x)
++{
++  x ^= 0x4002;
++  x >>= 1;
++  x |= 0x8000;
++  return x;
++}
++
++/* { dg-final { scan-assembler "orr" } } */
++/* { dg-final { scan-assembler-not "mvn" } } */
++/* { dg-final { scan-assembler-not "uxth" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch
new file mode 100644
index 0000000000..bda39e8faa
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch
@@ -0,0 +1,5027 @@
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* gimple.c (gimple_build_call_internal_1): Add missing call to
+	gimple_call_reset_alias_info.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.dg/vect/vect-strided-u16-i3.c: New test.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* lib/target-supports.exp (check_effective_target_vect_strided):
+	Replace with...
+	(check_effective_target_vect_strided2)
+	(check_effective_target_vect_strided3)
+	(check_effective_target_vect_strided4)
+	(check_effective_target_vect_strided8): ...these new functions.
+
+	* gcc.dg/vect/O3-pr39675-2.c: Update accordingly.
+	* gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c: Likewise.
+	* gcc.dg/vect/fast-math-slp-27.c: Likewise.
+	* gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: Likewise.
+	* gcc.dg/vect/pr37539.c: Likewise.
+	* gcc.dg/vect/slp-11a.c: Likewise.
+	* gcc.dg/vect/slp-11b.c: Likewise.
+	* gcc.dg/vect/slp-11c.c: Likewise.
+	* gcc.dg/vect/slp-12a.c: Likewise.
+	* gcc.dg/vect/slp-12b.c: Likewise.
+	* gcc.dg/vect/slp-18.c: Likewise.
+	* gcc.dg/vect/slp-19a.c: Likewise.
+	* gcc.dg/vect/slp-19b.c: Likewise.
+	* gcc.dg/vect/slp-21.c: Likewise.
+	* gcc.dg/vect/slp-23.c: Likewise.
+	* gcc.dg/vect/vect-cselim-1.c: Likewise.
+
+	* gcc.dg/vect/fast-math-vect-complex-3.c: Use vect_stridedN
+	instead of vect_interleave && vect_extract_even_odd.
+	* gcc.dg/vect/no-scevccp-outer-10a.c: Likewise.
+	* gcc.dg/vect/no-scevccp-outer-10b.c: Likewise.
+	* gcc.dg/vect/no-scevccp-outer-20.c: Likewise.
+	* gcc.dg/vect/vect-1.c: Likewise.
+	* gcc.dg/vect/vect-10.c: Likewise.
+	* gcc.dg/vect/vect-98.c: Likewise.
+	* gcc.dg/vect/vect-107.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-mult.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u16-i2.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u16-i4.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u16-mult.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u32-mult.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u8-i2-gap.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u8-i8-gap2.c: Likewise.
+	* gcc.dg/vect/vect-strided-a-u8-i8-gap7.c: Likewise.
+	* gcc.dg/vect/vect-strided-float.c: Likewise.
+	* gcc.dg/vect/vect-strided-mult-char-ls.c: Likewise.
+	* gcc.dg/vect/vect-strided-mult.c: Likewise.
+	* gcc.dg/vect/vect-strided-same-dr.c: Likewise.
+	* gcc.dg/vect/vect-strided-u16-i2.c: Likewise.
+	* gcc.dg/vect/vect-strided-u16-i4.c: Likewise.
+	* gcc.dg/vect/vect-strided-u32-i4.c: Likewise.
+	* gcc.dg/vect/vect-strided-u32-i8.c: Likewise.
+	* gcc.dg/vect/vect-strided-u32-mult.c: Likewise.
+	* gcc.dg/vect/vect-strided-u8-i2-gap.c: Likewise.
+	* gcc.dg/vect/vect-strided-u8-i2.c: Likewise.
+	* gcc.dg/vect/vect-strided-u8-i8-gap2.c: Likewise.
+	* gcc.dg/vect/vect-strided-u8-i8-gap4.c: Likewise.
+	* gcc.dg/vect/vect-strided-u8-i8-gap7.c: Likewise.
+	* gcc.dg/vect/vect-strided-u8-i8.c: Likewise.
+	* gcc.dg/vect/vect-vfa-03.c: Likewise.
+
+	* gcc.dg/vect/no-scevccp-outer-18.c: Add vect_stridedN to the
+	target condition.
+	* gcc.dg/vect/pr30843.c: Likewise.
+	* gcc.dg/vect/pr33866.c: Likewise.
+	* gcc.dg/vect/slp-reduc-6.c: Likewise.
+	* gcc.dg/vect/vect-strided-store-a-u8-i2.c: Likewise.
+	* gcc.dg/vect/vect-strided-store-u16-i4.c: Likewise.
+	* gcc.dg/vect/vect-strided-store-u32-i2.c: Likewise.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.dg/vect/slp-11.c: Split into...
+	* gcc.dg/vect/slp-11a.c, gcc.dg/vect/slp-11b.c,
+	gcc.dg/vect/slp-11c.c: ...these tests.
+	* gcc.dg/vect/slp-12a.c: Split 4-stride loop into...
+	* gcc.dg/vect/slp-12c.c: ...this new test.
+	* gcc.dg/vect/slp-19.c: Split into...
+	* gcc.dg/vect/slp-19a.c, gcc.dg/vect/slp-19b.c,
+	gcc.dg/vect/slp-19c.c: ...these new tests.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* lib/target-supports.exp
+	(check_effective_target_vect_extract_even_odd_wide): Delete.
+	(check_effective_target_vect_strided_wide): Likewise.
+	* gcc.dg/vect/O3-pr39675-2.c: Use the non-wide versions instead.
+	* gcc.dg/vect/fast-math-pr35982.c: Likewise.
+	* gcc.dg/vect/fast-math-vect-complex-3.c: Likewise.
+	* gcc.dg/vect/pr37539.c: Likewise.
+	* gcc.dg/vect/slp-11.c: Likewise.
+	* gcc.dg/vect/slp-12a.c: Likewise.
+	* gcc.dg/vect/slp-12b.c: Likewise.
+	* gcc.dg/vect/slp-19.c: Likewise.
+	* gcc.dg/vect/slp-23.c: Likewise.
+	* gcc.dg/vect/vect-1.c: Likewise.
+	* gcc.dg/vect/vect-98.c: Likewise.
+	* gcc.dg/vect/vect-107.c: Likewise.
+	* gcc.dg/vect/vect-strided-float.c: Likewise.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-04-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.dg/vect/vect.exp: Run the main tests twice, one with -flto
+	and once without.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainlie:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/neon.md (vec_load_lanes<mode><mode>): New expanders,
+	(vec_store_lanes<mode><mode>): Likewise.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-05-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* doc/md.texi (vec_load_lanes, vec_store_lanes): Document.
+	* optabs.h (COI_vec_load_lanes, COI_vec_store_lanes): New
+	convert_optab_index values.
+	(vec_load_lanes_optab, vec_store_lanes_optab): New convert optabs.
+	* genopinit.c (optabs): Initialize the new optabs.
+	* internal-fn.def (LOAD_LANES, STORE_LANES): New internal functions.
+	* internal-fn.c (get_multi_vector_move, expand_LOAD_LANES)
+	(expand_STORE_LANES): New functions.
+	* tree.h (build_array_type_nelts): Declare.
+	* tree.c (build_array_type_nelts): New function.
+	* tree-vectorizer.h (vect_model_store_cost): Add a bool argument.
+	(vect_model_load_cost): Likewise.
+	(vect_store_lanes_supported, vect_load_lanes_supported)
+	(vect_record_strided_load_vectors): Declare.
+	* tree-vect-data-refs.c (vect_lanes_optab_supported_p)
+	(vect_store_lanes_supported, vect_load_lanes_supported): New functions.
+	(vect_transform_strided_load): Split out statement recording into...
+	(vect_record_strided_load_vectors): ...this new function.
+	* tree-vect-stmts.c (create_vector_array, read_vector_array)
+	(write_vector_array, create_array_ref): New functions.
+	(vect_model_store_cost): Add store_lanes_p argument.
+	(vect_model_load_cost): Add load_lanes_p argument.
+	(vectorizable_store): Try to use store-lanes functions for
+	interleaved stores.
+	(vectorizable_load): Likewise load-lanes and loads.
+	* tree-vect-slp.c (vect_get_and_check_slp_defs): Update call
+	to vect_model_store_cost.
+	(vect_build_slp_tree): Likewise vect_model_load_cost.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree-vect-stmts.c (vectorizable_store): Only chain one related
+	statement per copy.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* tree-inline.c (estimate_num_insns): Likewise.
+
+	Backport from mainline:
+
+	2011-04-20  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* Makefile.in (INTERNAL_FN_DEF, INTERNAL_FN_H): Define.
+	(GIMPLE_H): Include $(INTERNAL_FN_H).
+	(OBJS-common): Add internal-fn.o.
+	(internal-fn.o): New rule.
+	* internal-fn.def: New file.
+	* internal-fn.h: Likewise.
+	* internal-fn.c: Likewise.
+	* gimple.h: Include internal-fn.h.
+	(GF_CALL_INTERNAL): New gf_mask.
+	(gimple_statement_call): Put fntype into a union with a new
+	internal_fn field.
+	(gimple_build_call_internal): Declare.
+	(gimple_build_call_internal_vec): Likewise.
+	(gimple_call_same_target_p): Likewise.
+	(gimple_call_internal_p): New function.
+	(gimple_call_internal_fn): Likewise.
+	(gimple_call_set_fn): Assert that the function is not internal.
+	(gimple_call_set_fndecl): Likewise.
+	(gimple_call_set_internal_fn): New function.
+	(gimple_call_addr_fndecl): Handle null functions.
+	(gimple_call_return_type): Likewise.
+	[---- Plus backport adjustments:
+	(GF_CALL_INTERNAL_FN_SHIFT): New macro.
+	(GF_CALL_INTERNAL_FN): New gf_mask.
+	----]
+	* gimple.c (gimple_build_call_internal_1): New function.
+	(gimple_build_call_internal): Likewise.
+	(gimple_build_call_internal_vec): Likewise.
+	(gimple_call_same_target_p): Likewise.
+	(gimple_call_flags): Handle calls to internal functions.
+	(gimple_call_fnspec): New function.
+	(gimple_call_arg_flags, gimple_call_return_flags): Use it.
+	(gimple_has_side_effects): Handle null functions.
+	(gimple_rhs_has_side_effects): Likewise.
+	(gimple_call_copy_skip_args): Handle calls to internal functions.
+	* cfgexpand.c (expand_call_stmt): Likewise.
+	* expr.c (expand_expr_real_1): Assert that the call isn't internal.
+	* gimple-low.c (gimple_check_call_args): Handle calls to internal
+	functions.
+	* gimple-pretty-print.c (dump_gimple_call): Likewise.
+	* ipa-prop.c (ipa_analyze_call_uses): Handle null functions.
+	* tree-cfg.c (verify_gimple_call): Handle calls to internal functions.
+	(do_warn_unused_result): Likewise.
+	[---- Plus backport adjustments:
+	(verify_stmt): Likewise.
+	----]
+	* tree-eh.c (same_handler_p): Use gimple_call_same_target_p.
+	* tree-ssa-ccp.c (ccp_fold_stmt): Handle calls to internal functions.
+	[---- Plus backport adjustments:
+	(fold_gimple_call): Likewise.
+	----]
+	* tree-ssa-dom.c (hashable_expr): Use the gimple statement to record
+	the target of a call.
+	(initialize_hash_element): Update accordingly.
+	(hashable_expr_equal_p): Use gimple_call_same_target_p.
+	(iterative_hash_hashable_expr): Handle calls to internal functions.
+	(print_expr_hash_elt): Likewise.
+	* tree-ssa-pre.c (can_value_number_call): Likewise.
+	(eliminate): Handle null functions.
+	* tree-ssa-sccvn.c (visit_use): Handle calls to internal functions.
+	* tree-ssa-structalias.c (find_func_aliases): Likewise.
+	* value-prof.c (gimple_ic_transform): Likewise.
+	(gimple_indirect_call_to_profile): Likewise.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree-vectorizer.h (vect_strided_store_supported): Add a
+	HOST_WIDE_INT argument.
+	(vect_strided_load_supported): Likewise.
+	(vect_permute_store_chain): Return void.
+	(vect_transform_strided_load): Likewise.
+	(vect_permute_load_chain): Delete.
+	* tree-vect-data-refs.c (vect_strided_store_supported): Take a
+	count argument.  Check that the count is a power of two.
+	(vect_strided_load_supported): Likewise.
+	(vect_permute_store_chain): Return void.  Update after above changes.
+	Assert that the access is supported.
+	(vect_permute_load_chain): Likewise.
+	(vect_transform_strided_load): Return void.
+	* tree-vect-stmts.c (vectorizable_store): Update calls after
+	above interface changes.
+	(vectorizable_load): Likewise.
+	(vect_analyze_stmt): Don't check for strided powers of two here.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree-vectorizer.h (vect_create_data_ref_ptr): Add an extra
+	type parameter.
+	* tree-vect-data-refs.c (vect_create_data_ref_ptr): Add an aggr_type
+	parameter.  Generalise code to handle arrays as well as vectors.
+	(vect_setup_realignment): Update accordingly.
+	* tree-vect-stmts.c (vectorizable_store): Likewise.
+	(vectorizable_load): Likewise.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree-vect-stmts.c (vectorizable_load): Allocate and free dr_chain
+	within the per-copy loop.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree-vect-stmts.c (vectorizable_load): Print the number of copies
+	in the dump file.
+
+2001-06-02  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-03-25  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS
+	case to VFPv1.
+
+=== modified file 'gcc/Makefile.in'
+--- old/gcc/Makefile.in	2011-05-26 14:27:33 +0000
++++ new/gcc/Makefile.in	2011-06-02 12:12:00 +0000
+@@ -888,6 +888,8 @@
+ READ_MD_H = $(OBSTACK_H) $(HASHTAB_H) read-md.h
+ PARAMS_H = params.h params.def
+ BUILTINS_DEF = builtins.def sync-builtins.def omp-builtins.def
++INTERNAL_FN_DEF = internal-fn.def
++INTERNAL_FN_H = internal-fn.h $(INTERNAL_FN_DEF)
+ TREE_H = tree.h all-tree.def tree.def c-family/c-common.def \
+ 	$(lang_tree_files) $(MACHMODE_H) tree-check.h $(BUILTINS_DEF) \
+ 	$(INPUT_H) statistics.h $(VEC_H) treestruct.def $(HASHTAB_H) \
+@@ -897,7 +899,7 @@
+ BASIC_BLOCK_H = basic-block.h $(PREDICT_H) $(VEC_H) $(FUNCTION_H) cfghooks.h
+ GIMPLE_H = gimple.h gimple.def gsstruct.def pointer-set.h $(VEC_H) \
+ 	$(GGC_H) $(BASIC_BLOCK_H) $(TARGET_H) tree-ssa-operands.h \
+-	tree-ssa-alias.h vecir.h
++	tree-ssa-alias.h vecir.h $(INTERNAL_FN_H)
+ GCOV_IO_H = gcov-io.h gcov-iov.h auto-host.h
+ COVERAGE_H = coverage.h $(GCOV_IO_H)
+ DEMANGLE_H = $(srcdir)/../include/demangle.h
+@@ -1269,6 +1271,7 @@
+ 	init-regs.o \
+ 	input.o \
+ 	integrate.o \
++	internal-fn.o \
+ 	intl.o \
+ 	ira.o \
+ 	ira-build.o \
+@@ -2751,6 +2754,8 @@
+    $(TM_H) $(TREE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) $(TREE_FLOW_H) \
+    $(TREE_PASS_H) tree-ssa-propagate.h tree-pretty-print.h \
+    gimple-pretty-print.h
++internal-fn.o : internal-fn.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
++   $(GIMPLE_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H)
+ gimple.o : gimple.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \
+    $(GGC_H) $(GIMPLE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) gt-gimple.h \
+    $(TREE_FLOW_H) value-prof.h $(FLAGS_H) $(DEMANGLE_H) \
+
+=== modified file 'gcc/cfgexpand.c'
+--- old/gcc/cfgexpand.c	2011-04-20 11:18:50 +0000
++++ new/gcc/cfgexpand.c	2011-06-02 12:12:00 +0000
+@@ -1839,12 +1839,17 @@
+ static void
+ expand_call_stmt (gimple stmt)
+ {
+-  tree exp;
+-  tree lhs = gimple_call_lhs (stmt);
++  tree exp, lhs;
+   size_t i;
+   bool builtin_p;
+   tree decl;
+ 
++  if (gimple_call_internal_p (stmt))
++    {
++      expand_internal_call (stmt);
++      return;
++    }
++
+   exp = build_vl_exp (CALL_EXPR, gimple_call_num_args (stmt) + 3);
+ 
+   CALL_EXPR_FN (exp) = gimple_call_fn (stmt);
+@@ -1882,6 +1887,7 @@
+   SET_EXPR_LOCATION (exp, gimple_location (stmt));
+   TREE_BLOCK (exp) = gimple_block (stmt);
+ 
++  lhs = gimple_call_lhs (stmt);
+   if (lhs)
+     expand_assignment (lhs, exp, false);
+   else
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-04-26 14:42:21 +0000
++++ new/gcc/config/arm/arm.h	2011-06-02 12:12:00 +0000
+@@ -1169,12 +1169,12 @@
+ }
+ 
+ /* FPA registers can't do subreg as all values are reformatted to internal
+-   precision.  VFP registers may only be accessed in the mode they
+-   were set.  */
+-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)	\
+-  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)		\
+-   ? reg_classes_intersect_p (FPA_REGS, (CLASS))	\
+-     || reg_classes_intersect_p (VFP_REGS, (CLASS))	\
++   precision.  In VFPv1, VFP registers could only be accessed in the mode
++   they were set, so subregs would be invalid there too.  However, we don't
++   support VFPv1 at the moment, and the restriction was lifted in VFPv2.  */
++#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)		\
++  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)			\
++   ? reg_classes_intersect_p (FPA_REGS, (CLASS))		\
+    : 0)
+ 
+ /* The class value for index registers, and the one for base regs.  */
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2011-05-06 11:28:27 +0000
++++ new/gcc/config/arm/neon.md	2011-06-02 12:12:00 +0000
+@@ -4248,6 +4248,12 @@
+   DONE;
+ })
+ 
++(define_expand "vec_load_lanes<mode><mode>"
++  [(set (match_operand:VDQX 0 "s_register_operand")
++        (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand")]
++                     UNSPEC_VLD1))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vld1<mode>"
+   [(set (match_operand:VDQX 0 "s_register_operand" "=w")
+         (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
+@@ -4345,6 +4351,12 @@
+                     (const_string "neon_vld1_1_2_regs")))]
+ )
+ 
++(define_expand "vec_store_lanes<mode><mode>"
++  [(set (match_operand:VDQX 0 "neon_struct_operand")
++	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand")]
++		     UNSPEC_VST1))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vst1<mode>"
+   [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
+ 	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
+@@ -4401,6 +4413,13 @@
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+ 
++(define_expand "vec_load_lanesti<mode>"
++  [(set (match_operand:TI 0 "s_register_operand")
++        (unspec:TI [(match_operand:TI 1 "neon_struct_operand")
++                    (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++		   UNSPEC_VLD2))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vld2<mode>"
+   [(set (match_operand:TI 0 "s_register_operand" "=w")
+         (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
+@@ -4419,6 +4438,13 @@
+                     (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))]
+ )
+ 
++(define_expand "vec_load_lanesoi<mode>"
++  [(set (match_operand:OI 0 "s_register_operand")
++        (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
++                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++		   UNSPEC_VLD2))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vld2<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+         (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+@@ -4501,6 +4527,13 @@
+                     (const_string "neon_vld1_1_2_regs")))]
+ )
+ 
++(define_expand "vec_store_lanesti<mode>"
++  [(set (match_operand:TI 0 "neon_struct_operand")
++	(unspec:TI [(match_operand:TI 1 "s_register_operand")
++                    (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++                   UNSPEC_VST2))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vst2<mode>"
+   [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
+         (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+@@ -4519,6 +4552,13 @@
+                     (const_string "neon_vst1_1_2_regs_vst2_2_regs")))]
+ )
+ 
++(define_expand "vec_store_lanesoi<mode>"
++  [(set (match_operand:OI 0 "neon_struct_operand")
++	(unspec:OI [(match_operand:OI 1 "s_register_operand")
++                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++                   UNSPEC_VST2))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vst2<mode>"
+   [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ 	(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+@@ -4584,6 +4624,13 @@
+   [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+ 
++(define_expand "vec_load_lanesei<mode>"
++  [(set (match_operand:EI 0 "s_register_operand")
++        (unspec:EI [(match_operand:EI 1 "neon_struct_operand")
++                    (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++		   UNSPEC_VLD3))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vld3<mode>"
+   [(set (match_operand:EI 0 "s_register_operand" "=w")
+         (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
+@@ -4602,6 +4649,16 @@
+                     (const_string "neon_vld3_vld4")))]
+ )
+ 
++(define_expand "vec_load_lanesci<mode>"
++  [(match_operand:CI 0 "s_register_operand")
++   (match_operand:CI 1 "neon_struct_operand")
++   (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++  "TARGET_NEON"
++{
++  emit_insn (gen_neon_vld3<mode> (operands[0], operands[1]));
++  DONE;
++})
++
+ (define_expand "neon_vld3<mode>"
+   [(match_operand:CI 0 "s_register_operand")
+    (match_operand:CI 1 "neon_struct_operand")
+@@ -4741,6 +4798,13 @@
+                     (const_string "neon_vld3_vld4_all_lanes")
+                     (const_string "neon_vld1_1_2_regs")))])
+ 
++(define_expand "vec_store_lanesei<mode>"
++  [(set (match_operand:EI 0 "neon_struct_operand")
++	(unspec:EI [(match_operand:EI 1 "s_register_operand")
++                    (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++                   UNSPEC_VST3))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vst3<mode>"
+   [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+         (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
+@@ -4758,6 +4822,16 @@
+                     (const_string "neon_vst1_1_2_regs_vst2_2_regs")
+                     (const_string "neon_vst2_4_regs_vst3_vst4")))])
+ 
++(define_expand "vec_store_lanesci<mode>"
++  [(match_operand:CI 0 "neon_struct_operand")
++   (match_operand:CI 1 "s_register_operand")
++   (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++  "TARGET_NEON"
++{
++  emit_insn (gen_neon_vst3<mode> (operands[0], operands[1]));
++  DONE;
++})
++
+ (define_expand "neon_vst3<mode>"
+   [(match_operand:CI 0 "neon_struct_operand")
+    (match_operand:CI 1 "s_register_operand")
+@@ -4869,6 +4943,13 @@
+ }
+ [(set_attr "neon_type" "neon_vst3_vst4_lane")])
+ 
++(define_expand "vec_load_lanesoi<mode>"
++  [(set (match_operand:OI 0 "s_register_operand")
++        (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
++                    (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++		   UNSPEC_VLD4))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vld4<mode>"
+   [(set (match_operand:OI 0 "s_register_operand" "=w")
+         (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+@@ -4887,6 +4968,16 @@
+                     (const_string "neon_vld3_vld4")))]
+ )
+ 
++(define_expand "vec_load_lanesxi<mode>"
++  [(match_operand:XI 0 "s_register_operand")
++   (match_operand:XI 1 "neon_struct_operand")
++   (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++  "TARGET_NEON"
++{
++  emit_insn (gen_neon_vld4<mode> (operands[0], operands[1]));
++  DONE;
++})
++
+ (define_expand "neon_vld4<mode>"
+   [(match_operand:XI 0 "s_register_operand")
+    (match_operand:XI 1 "neon_struct_operand")
+@@ -5033,6 +5124,13 @@
+                     (const_string "neon_vld1_1_2_regs")))]
+ )
+ 
++(define_expand "vec_store_lanesoi<mode>"
++  [(set (match_operand:OI 0 "neon_struct_operand")
++	(unspec:OI [(match_operand:OI 1 "s_register_operand")
++                    (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++                   UNSPEC_VST4))]
++  "TARGET_NEON")
++
+ (define_insn "neon_vst4<mode>"
+   [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+         (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+@@ -5051,6 +5149,16 @@
+                     (const_string "neon_vst2_4_regs_vst3_vst4")))]
+ )
+ 
++(define_expand "vec_store_lanesxi<mode>"
++  [(match_operand:XI 0 "neon_struct_operand")
++   (match_operand:XI 1 "s_register_operand")
++   (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
++  "TARGET_NEON"
++{
++  emit_insn (gen_neon_vst4<mode> (operands[0], operands[1]));
++  DONE;
++})
++
+ (define_expand "neon_vst4<mode>"
+   [(match_operand:XI 0 "neon_struct_operand")
+    (match_operand:XI 1 "s_register_operand")
+
+=== modified file 'gcc/doc/md.texi'
+--- old/gcc/doc/md.texi	2011-01-03 20:52:22 +0000
++++ new/gcc/doc/md.texi	2011-05-05 15:43:06 +0000
+@@ -3935,6 +3935,48 @@
+ consecutive memory locations, operand 1 is the first register, and
+ operand 2 is a constant: the number of consecutive registers.
+ 
++@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
++@item @samp{vec_load_lanes@var{m}@var{n}}
++Perform an interleaved load of several vectors from memory operand 1
++into register operand 0.  Both operands have mode @var{m}.  The register
++operand is viewed as holding consecutive vectors of mode @var{n},
++while the memory operand is a flat array that contains the same number
++of elements.  The operation is equivalent to:
++
++@smallexample
++int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
++for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
++  for (i = 0; i < c; i++)
++    operand0[i][j] = operand1[j * c + i];
++@end smallexample
++
++For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
++from memory into a register of mode @samp{TI}@.  The register
++contains two consecutive vectors of mode @samp{V4HI}@.
++
++This pattern can only be used if:
++@smallexample
++TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
++@end smallexample
++is true.  GCC assumes that, if a target supports this kind of
++instruction for some mode @var{n}, it also supports unaligned
++loads for vectors of mode @var{n}.
++
++@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
++@item @samp{vec_store_lanes@var{m}@var{n}}
++Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
++and register operands reversed.  That is, the instruction is
++equivalent to:
++
++@smallexample
++int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
++for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
++  for (i = 0; i < c; i++)
++    operand0[j * c + i] = operand1[i][j];
++@end smallexample
++
++for a memory operand 0 and register operand 1.
++
+ @cindex @code{vec_set@var{m}} instruction pattern
+ @item @samp{vec_set@var{m}}
+ Set given field in the vector value.  Operand 0 is the vector to modify,
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2011-05-26 14:27:33 +0000
++++ new/gcc/expr.c	2011-06-02 12:12:00 +0000
+@@ -8537,10 +8537,13 @@
+ 	  if (code == SSA_NAME
+ 	      && (g = SSA_NAME_DEF_STMT (ssa_name))
+ 	      && gimple_code (g) == GIMPLE_CALL)
+-	    pmode = promote_function_mode (type, mode, &unsignedp,
+-					   TREE_TYPE
+-					   (TREE_TYPE (gimple_call_fn (g))),
+-					   2);
++	    {
++	      gcc_assert (!gimple_call_internal_p (g));
++	      pmode = promote_function_mode (type, mode, &unsignedp,
++					     TREE_TYPE
++					     (TREE_TYPE (gimple_call_fn (g))),
++					     2);
++	    }
+ 	  else
+ 	    pmode = promote_decl_mode (exp, &unsignedp);
+ 	  gcc_assert (GET_MODE (decl_rtl) == pmode);
+
+=== modified file 'gcc/genopinit.c'
+--- old/gcc/genopinit.c	2011-01-03 20:52:22 +0000
++++ new/gcc/genopinit.c	2011-05-05 15:43:06 +0000
+@@ -74,6 +74,8 @@
+   "set_convert_optab_handler (fractuns_optab, $B, $A, CODE_FOR_$(fractuns$Q$a$I$b2$))",
+   "set_convert_optab_handler (satfract_optab, $B, $A, CODE_FOR_$(satfract$a$Q$b2$))",
+   "set_convert_optab_handler (satfractuns_optab, $B, $A, CODE_FOR_$(satfractuns$I$a$Q$b2$))",
++  "set_convert_optab_handler (vec_load_lanes_optab, $A, $B, CODE_FOR_$(vec_load_lanes$a$b$))",
++  "set_convert_optab_handler (vec_store_lanes_optab, $A, $B, CODE_FOR_$(vec_store_lanes$a$b$))",
+   "set_optab_handler (add_optab, $A, CODE_FOR_$(add$P$a3$))",
+   "set_optab_handler (addv_optab, $A, CODE_FOR_$(add$F$a3$)),\n\
+     set_optab_handler (add_optab, $A, CODE_FOR_$(add$F$a3$))",
+
+=== modified file 'gcc/gimple-low.c'
+--- old/gcc/gimple-low.c	2011-02-08 11:15:53 +0000
++++ new/gcc/gimple-low.c	2011-05-05 15:42:22 +0000
+@@ -218,6 +218,10 @@
+   tree fndecl, parms, p;
+   unsigned int i, nargs;
+ 
++  /* Calls to internal functions always match their signature.  */
++  if (gimple_call_internal_p (stmt))
++    return true;
++
+   nargs = gimple_call_num_args (stmt);
+ 
+   /* Get argument types for verification.  */
+
+=== modified file 'gcc/gimple-pretty-print.c'
+--- old/gcc/gimple-pretty-print.c	2011-02-15 18:36:16 +0000
++++ new/gcc/gimple-pretty-print.c	2011-05-05 15:42:22 +0000
+@@ -596,8 +596,12 @@
+ 
+   if (flags & TDF_RAW)
+     {
+-      dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T",
+-                     gs, gimple_call_fn (gs), lhs);
++      if (gimple_call_internal_p (gs))
++	dump_gimple_fmt (buffer, spc, flags, "%G <%s, %T", gs,
++			 internal_fn_name (gimple_call_internal_fn (gs)), lhs);
++      else
++	dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T",
++			 gs, gimple_call_fn (gs), lhs);
+       if (gimple_call_num_args (gs) > 0)
+         {
+           pp_string (buffer, ", ");
+@@ -617,7 +621,10 @@
+ 
+ 	  pp_space (buffer);
+         }
+-      print_call_name (buffer, gimple_call_fn (gs), flags);
++      if (gimple_call_internal_p (gs))
++	pp_string (buffer, internal_fn_name (gimple_call_internal_fn (gs)));
++      else
++	print_call_name (buffer, gimple_call_fn (gs), flags);
+       pp_string (buffer, " (");
+       dump_gimple_call_args (buffer, gs, flags);
+       pp_character (buffer, ')');
+
+=== modified file 'gcc/gimple.c'
+--- old/gcc/gimple.c	2011-05-18 13:33:53 +0000
++++ new/gcc/gimple.c	2011-06-02 12:12:00 +0000
+@@ -276,6 +276,59 @@
+ }
+ 
+ 
++/* Helper for gimple_build_call_internal and gimple_build_call_internal_vec.
++   Build the basic components of a GIMPLE_CALL statement to internal
++   function FN with NARGS arguments.  */
++
++static inline gimple
++gimple_build_call_internal_1 (enum internal_fn fn, unsigned nargs)
++{
++  gimple s = gimple_build_with_ops (GIMPLE_CALL, ERROR_MARK, nargs + 3);
++  s->gsbase.subcode |= GF_CALL_INTERNAL;
++  gimple_call_set_internal_fn (s, fn);
++  gimple_call_reset_alias_info (s);
++  return s;
++}
++
++
++/* Build a GIMPLE_CALL statement to internal function FN.  NARGS is
++   the number of arguments.  The ... are the arguments.  */
++
++gimple
++gimple_build_call_internal (enum internal_fn fn, unsigned nargs, ...)
++{
++  va_list ap;
++  gimple call;
++  unsigned i;
++
++  call = gimple_build_call_internal_1 (fn, nargs);
++  va_start (ap, nargs);
++  for (i = 0; i < nargs; i++)
++    gimple_call_set_arg (call, i, va_arg (ap, tree));
++  va_end (ap);
++
++  return call;
++}
++
++
++/* Build a GIMPLE_CALL statement to internal function FN with the arguments
++   specified in vector ARGS.  */
++
++gimple
++gimple_build_call_internal_vec (enum internal_fn fn, VEC(tree, heap) *args)
++{
++  unsigned i, nargs;
++  gimple call;
++
++  nargs = VEC_length (tree, args);
++  call = gimple_build_call_internal_1 (fn, nargs);
++  for (i = 0; i < nargs; i++)
++    gimple_call_set_arg (call, i, VEC_index (tree, args, i));
++
++  return call;
++}
++
++
+ /* Build a GIMPLE_CALL statement from CALL_EXPR T.  Note that T is
+    assumed to be in GIMPLE form already.  Minimal checking is done of
+    this fact.  */
+@@ -1774,6 +1827,20 @@
+   return (gimple_body (fndecl) || (fn && fn->cfg));
+ }
+ 
++/* Return true if calls C1 and C2 are known to go to the same function.  */
++
++bool
++gimple_call_same_target_p (const_gimple c1, const_gimple c2)
++{
++  if (gimple_call_internal_p (c1))
++    return (gimple_call_internal_p (c2)
++	    && gimple_call_internal_fn (c1) == gimple_call_internal_fn (c2));
++  else
++    return (gimple_call_fn (c1) == gimple_call_fn (c2)
++	    || (gimple_call_fndecl (c1)
++		&& gimple_call_fndecl (c1) == gimple_call_fndecl (c2)));
++}
++
+ /* Detect flags from a GIMPLE_CALL.  This is just like
+    call_expr_flags, but for gimple tuples.  */
+ 
+@@ -1786,6 +1853,8 @@
+ 
+   if (decl)
+     flags = flags_from_decl_or_type (decl);
++  else if (gimple_call_internal_p (stmt))
++    flags = internal_fn_flags (gimple_call_internal_fn (stmt));
+   else
+     {
+       t = TREE_TYPE (gimple_call_fn (stmt));
+@@ -1801,18 +1870,35 @@
+   return flags;
+ }
+ 
++/* Return the "fn spec" string for call STMT.  */
++
++static tree
++gimple_call_fnspec (const_gimple stmt)
++{
++  tree fn, type, attr;
++
++  fn = gimple_call_fn (stmt);
++  if (!fn)
++    return NULL_TREE;
++
++  type = TREE_TYPE (TREE_TYPE (fn));
++  if (!type)
++    return NULL_TREE;
++
++  attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
++  if (!attr)
++    return NULL_TREE;
++
++  return TREE_VALUE (TREE_VALUE (attr));
++}
++
+ /* Detects argument flags for argument number ARG on call STMT.  */
+ 
+ int
+ gimple_call_arg_flags (const_gimple stmt, unsigned arg)
+ {
+-  tree type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt)));
+-  tree attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
+-  if (!attr)
+-    return 0;
+-
+-  attr = TREE_VALUE (TREE_VALUE (attr));
+-  if (1 + arg >= (unsigned) TREE_STRING_LENGTH (attr))
++  tree attr = gimple_call_fnspec (stmt);
++  if (!attr || 1 + arg >= (unsigned) TREE_STRING_LENGTH (attr))
+     return 0;
+ 
+   switch (TREE_STRING_POINTER (attr)[1 + arg])
+@@ -1850,13 +1936,8 @@
+   if (gimple_call_flags (stmt) & ECF_MALLOC)
+     return ERF_NOALIAS;
+ 
+-  type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt)));
+-  attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
+-  if (!attr)
+-    return 0;
+-
+-  attr = TREE_VALUE (TREE_VALUE (attr));
+-  if (TREE_STRING_LENGTH (attr) < 1)
++  attr = gimple_call_fnspec (stmt);
++  if (!attr || TREE_STRING_LENGTH (attr) < 1)
+     return 0;
+ 
+   switch (TREE_STRING_POINTER (attr)[0])
+@@ -2293,6 +2374,7 @@
+   if (is_gimple_call (s))
+     {
+       unsigned nargs = gimple_call_num_args (s);
++      tree fn;
+ 
+       if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE)))
+         return true;
+@@ -2307,7 +2389,8 @@
+ 	  return true;
+ 	}
+ 
+-      if (TREE_SIDE_EFFECTS (gimple_call_fn (s)))
++      fn = gimple_call_fn (s);
++      if (fn && TREE_SIDE_EFFECTS (fn))
+         return true;
+ 
+       for (i = 0; i < nargs; i++)
+@@ -2349,14 +2432,15 @@
+   if (is_gimple_call (s))
+     {
+       unsigned nargs = gimple_call_num_args (s);
++      tree fn;
+ 
+       if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE)))
+         return true;
+ 
+       /* We cannot use gimple_has_volatile_ops here,
+          because we must ignore a volatile LHS.  */
+-      if (TREE_SIDE_EFFECTS (gimple_call_fn (s))
+-          || TREE_THIS_VOLATILE (gimple_call_fn (s)))
++      fn = gimple_call_fn (s);
++      if (fn && (TREE_SIDE_EFFECTS (fn) || TREE_THIS_VOLATILE (fn)))
+ 	{
+ 	  gcc_assert (gimple_has_volatile_ops (s));
+ 	  return true;
+@@ -3113,7 +3197,6 @@
+ gimple_call_copy_skip_args (gimple stmt, bitmap args_to_skip)
+ {
+   int i;
+-  tree fn = gimple_call_fn (stmt);
+   int nargs = gimple_call_num_args (stmt);
+   VEC(tree, heap) *vargs = VEC_alloc (tree, heap, nargs);
+   gimple new_stmt;
+@@ -3122,7 +3205,11 @@
+     if (!bitmap_bit_p (args_to_skip, i))
+       VEC_quick_push (tree, vargs, gimple_call_arg (stmt, i));
+ 
+-  new_stmt = gimple_build_call_vec (fn, vargs);
++  if (gimple_call_internal_p (stmt))
++    new_stmt = gimple_build_call_internal_vec (gimple_call_internal_fn (stmt),
++					       vargs);
++  else
++    new_stmt = gimple_build_call_vec (gimple_call_fn (stmt), vargs);
+   VEC_free (tree, heap, vargs);
+   if (gimple_call_lhs (stmt))
+     gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
+
+=== modified file 'gcc/gimple.h'
+--- old/gcc/gimple.h	2011-04-18 21:58:03 +0000
++++ new/gcc/gimple.h	2011-06-02 12:12:00 +0000
+@@ -30,6 +30,7 @@
+ #include "basic-block.h"
+ #include "tree-ssa-operands.h"
+ #include "tree-ssa-alias.h"
++#include "internal-fn.h"
+ 
+ struct gimple_seq_node_d;
+ typedef struct gimple_seq_node_d *gimple_seq_node;
+@@ -82,6 +83,8 @@
+ 			   name, a _DECL, a _REF, etc.  */
+ };
+ 
++#define GF_CALL_INTERNAL_FN_SHIFT 8
++
+ /* Specific flags for individual GIMPLE statements.  These flags are
+    always stored in gimple_statement_base.subcode and they may only be
+    defined for statement codes that do not use sub-codes.
+@@ -102,6 +105,8 @@
+     GF_CALL_TAILCALL		= 1 << 3,
+     GF_CALL_VA_ARG_PACK		= 1 << 4,
+     GF_CALL_NOTHROW		= 1 << 5,
++    GF_CALL_INTERNAL		= 1 << 6,
++    GF_CALL_INTERNAL_FN		= 0xff << GF_CALL_INTERNAL_FN_SHIFT,
+     GF_OMP_PARALLEL_COMBINED	= 1 << 0,
+ 
+     /* True on an GIMPLE_OMP_RETURN statement if the return does not require
+@@ -817,6 +822,8 @@
+ 
+ gimple gimple_build_call_vec (tree, VEC(tree, heap) *);
+ gimple gimple_build_call (tree, unsigned, ...);
++gimple gimple_build_call_internal (enum internal_fn, unsigned, ...);
++gimple gimple_build_call_internal_vec (enum internal_fn, VEC(tree, heap) *);
+ gimple gimple_build_call_from_tree (tree);
+ gimple gimplify_assign (tree, tree, gimple_seq *);
+ gimple gimple_build_cond (enum tree_code, tree, tree, tree, tree);
+@@ -861,6 +868,7 @@
+ void gimple_seq_free (gimple_seq);
+ void gimple_seq_add_seq (gimple_seq *, gimple_seq);
+ gimple_seq gimple_seq_copy (gimple_seq);
++bool gimple_call_same_target_p (const_gimple, const_gimple);
+ int gimple_call_flags (const_gimple);
+ int gimple_call_return_flags (const_gimple);
+ int gimple_call_arg_flags (const_gimple, unsigned);
+@@ -2012,6 +2020,27 @@
+ }
+ 
+ 
++/* Return true if call GS calls an internal-only function, as enumerated
++   by internal_fn.  */
++
++static inline bool
++gimple_call_internal_p (const_gimple gs)
++{
++  GIMPLE_CHECK (gs, GIMPLE_CALL);
++  return (gs->gsbase.subcode & GF_CALL_INTERNAL) != 0;
++}
++
++
++/* Return the target of internal call GS.  */
++
++static inline enum internal_fn
++gimple_call_internal_fn (const_gimple gs)
++{
++  gcc_assert (gimple_call_internal_p (gs));
++  return (enum internal_fn) (gs->gsbase.subcode >> GF_CALL_INTERNAL_FN_SHIFT);
++}
++
++
+ /* Return a pointer to the tree node representing the function called by call
+    statement GS.  */
+ 
+@@ -2029,6 +2058,7 @@
+ gimple_call_set_fn (gimple gs, tree fn)
+ {
+   GIMPLE_CHECK (gs, GIMPLE_CALL);
++  gcc_assert (!gimple_call_internal_p (gs));
+   gimple_set_op (gs, 1, fn);
+ }
+ 
+@@ -2039,10 +2069,23 @@
+ gimple_call_set_fndecl (gimple gs, tree decl)
+ {
+   GIMPLE_CHECK (gs, GIMPLE_CALL);
++  gcc_assert (!gimple_call_internal_p (gs));
+   gimple_set_op (gs, 1, build_fold_addr_expr_loc (gimple_location (gs), decl));
+ }
+ 
+ 
++/* Set internal function FN to be the function called by call statement GS.  */
++
++static inline void
++gimple_call_set_internal_fn (gimple gs, enum internal_fn fn)
++{
++  GIMPLE_CHECK (gs, GIMPLE_CALL);
++  gcc_assert (gimple_call_internal_p (gs));
++  gs->gsbase.subcode &= ~GF_CALL_INTERNAL_FN;
++  gs->gsbase.subcode |= (int) fn << GF_CALL_INTERNAL_FN_SHIFT;
++}
++
++
+ /* If a given GIMPLE_CALL's callee is a FUNCTION_DECL, return it.
+    Otherwise return NULL.  This function is analogous to
+    get_callee_fndecl in tree land.  */
+@@ -2051,7 +2094,7 @@
+ gimple_call_fndecl (const_gimple gs)
+ {
+   tree addr = gimple_call_fn (gs);
+-  if (TREE_CODE (addr) == ADDR_EXPR)
++  if (addr && TREE_CODE (addr) == ADDR_EXPR)
+     {
+       tree fndecl = TREE_OPERAND (addr, 0);
+       if (TREE_CODE (fndecl) == MEM_REF)
+@@ -2073,8 +2116,13 @@
+ static inline tree
+ gimple_call_return_type (const_gimple gs)
+ {
+-  tree fn = gimple_call_fn (gs);
+-  tree type = TREE_TYPE (fn);
++  tree fn, type;
++
++  fn = gimple_call_fn (gs);
++  if (fn == NULL_TREE)
++    return TREE_TYPE (gimple_call_lhs (gs));
++
++  type = TREE_TYPE (fn);
+ 
+   /* See through the pointer.  */
+   type = TREE_TYPE (type);
+
+=== added file 'gcc/internal-fn.c'
+--- old/gcc/internal-fn.c	1970-01-01 00:00:00 +0000
++++ new/gcc/internal-fn.c	2011-05-05 15:43:06 +0000
+@@ -0,0 +1,147 @@
++/* Internal functions.
++   Copyright (C) 2011 Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#include "config.h"
++#include "system.h"
++#include "coretypes.h"
++#include "gimple.h"
++#include "tree.h"
++#include "expr.h"
++#include "optabs.h"
++#include "recog.h"
++
++/* The names of each internal function, indexed by function number.  */
++const char *const internal_fn_name_array[] = {
++#define DEF_INTERNAL_FN(CODE, FLAGS) #CODE,
++#include "internal-fn.def"
++#undef DEF_INTERNAL_FN
++  "<invalid-fn>"
++};
++
++/* The ECF_* flags of each internal function, indexed by function number.  */
++const int internal_fn_flags_array[] = {
++#define DEF_INTERNAL_FN(CODE, FLAGS) FLAGS,
++#include "internal-fn.def"
++#undef DEF_INTERNAL_FN
++  0
++};
++
++/* ARRAY_TYPE is an array of vector modes.  Return the associated insn
++   for load-lanes-style optab OPTAB.  The insn must exist.  */
++
++static enum insn_code
++get_multi_vector_move (tree array_type, convert_optab optab)
++{
++  enum insn_code icode;
++  enum machine_mode imode;
++  enum machine_mode vmode;
++
++  gcc_assert (TREE_CODE (array_type) == ARRAY_TYPE);
++  imode = TYPE_MODE (array_type);
++  vmode = TYPE_MODE (TREE_TYPE (array_type));
++
++  icode = convert_optab_handler (optab, imode, vmode);
++  gcc_assert (icode != CODE_FOR_nothing);
++  return icode;
++}
++
++/* Expand LOAD_LANES call STMT.  */
++
++static void
++expand_LOAD_LANES (gimple stmt)
++{
++  tree type, lhs, rhs;
++  rtx target, mem;
++  enum insn_code icode;
++  const struct insn_operand_data *operand;
++
++  lhs = gimple_call_lhs (stmt);
++  rhs = gimple_call_arg (stmt, 0);
++  type = TREE_TYPE (lhs);
++
++  target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
++  mem = expand_normal (rhs);
++
++  gcc_assert (REG_P (target));
++  gcc_assert (MEM_P (mem));
++  PUT_MODE (mem, TYPE_MODE (type));
++
++  icode = get_multi_vector_move (type, vec_load_lanes_optab);
++
++  operand = &insn_data[(int) icode].operand[1];
++  if (operand->predicate && !operand->predicate (mem, operand->mode))
++    mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
++
++  emit_insn (GEN_FCN (icode) (target, mem));
++}
++
++/* Expand STORE_LANES call STMT.  */
++
++static void
++expand_STORE_LANES (gimple stmt)
++{
++  tree type, lhs, rhs;
++  rtx target, reg;
++  enum insn_code icode;
++  const struct insn_operand_data *operand;
++
++  lhs = gimple_call_lhs (stmt);
++  rhs = gimple_call_arg (stmt, 0);
++  type = TREE_TYPE (rhs);
++
++  target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
++  reg = expand_normal (rhs);
++
++  gcc_assert (MEM_P (target));
++  PUT_MODE (target, TYPE_MODE (type));
++
++  icode = get_multi_vector_move (type, vec_store_lanes_optab);
++
++  operand = &insn_data[(int) icode].operand[0];
++  if (operand->predicate && !operand->predicate (target, operand->mode))
++    target = replace_equiv_address (target,
++				    force_reg (Pmode, XEXP (target, 0)));
++
++  operand = &insn_data[(int) icode].operand[1];
++  if (operand->predicate && !operand->predicate (reg, operand->mode))
++    reg = force_reg (TYPE_MODE (type), reg);
++
++  emit_insn (GEN_FCN (icode) (target, reg));
++}
++
++/* Routines to expand each internal function, indexed by function number.
++   Each routine has the prototype:
++
++       expand_<NAME> (gimple stmt)
++
++   where STMT is the statement that performs the call. */
++static void (*const internal_fn_expanders[]) (gimple) = {
++#define DEF_INTERNAL_FN(CODE, FLAGS) expand_##CODE,
++#include "internal-fn.def"
++#undef DEF_INTERNAL_FN
++  0
++};
++
++/* Expand STMT, which is a call to internal function FN.  */
++
++void
++expand_internal_call (gimple stmt)
++{
++  internal_fn_expanders[(int) gimple_call_internal_fn (stmt)] (stmt);
++}
+
+=== added file 'gcc/internal-fn.def'
+--- old/gcc/internal-fn.def	1970-01-01 00:00:00 +0000
++++ new/gcc/internal-fn.def	2011-05-05 15:43:06 +0000
+@@ -0,0 +1,42 @@
++/* Internal functions.
++   Copyright (C) 2011 Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++/* This file specifies a list of internal "functions".  These functions
++   differ from built-in functions in that they have no linkage and cannot
++   be called directly by the user.  They represent operations that are only
++   synthesised by GCC itself.
++
++   Internal functions are used instead of tree codes if the operation
++   and its operands are more naturally represented as a GIMPLE_CALL
++   than a GIMPLE_ASSIGN.
++
++   Each entry in this file has the form:
++
++     DEF_INTERNAL_FN (NAME, FLAGS)
++
++   where NAME is the name of the function and FLAGS is a set of
++   ECF_* flags.  Each entry must have a corresponding expander
++   of the form:
++
++     void expand_NAME (gimple stmt)
++
++   where STMT is the statement that performs the call.  */
++
++DEF_INTERNAL_FN (LOAD_LANES, ECF_CONST | ECF_LEAF)
++DEF_INTERNAL_FN (STORE_LANES, ECF_CONST | ECF_LEAF)
+
+=== added file 'gcc/internal-fn.h'
+--- old/gcc/internal-fn.h	1970-01-01 00:00:00 +0000
++++ new/gcc/internal-fn.h	2011-05-05 15:42:22 +0000
+@@ -0,0 +1,52 @@
++/* Internal functions.
++   Copyright (C) 2011 Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_INTERNAL_FN_H
++#define GCC_INTERNAL_FN_H
++
++enum internal_fn {
++#define DEF_INTERNAL_FN(CODE, FLAGS) IFN_##CODE,
++#include "internal-fn.def"
++#undef DEF_INTERNAL_FN
++  IFN_LAST
++};
++
++extern const char *const internal_fn_name_array[];
++extern const int internal_fn_flags_array[];
++
++/* Return the name of internal function FN.  The name is only meaningful
++   for dumps; it has no linkage.  */
++
++static inline const char *
++internal_fn_name (enum internal_fn fn)
++{
++  return internal_fn_name_array[(int) fn];
++}
++
++/* Return the ECF_* flags for function FN.  */
++
++static inline int
++internal_fn_flags (enum internal_fn fn)
++{
++  return internal_fn_flags_array[(int) fn];
++}
++
++extern void expand_internal_call (gimple);
++
++#endif
+
+=== modified file 'gcc/ipa-prop.c'
+--- old/gcc/ipa-prop.c	2011-04-18 21:58:03 +0000
++++ new/gcc/ipa-prop.c	2011-06-02 12:12:00 +0000
+@@ -1418,6 +1418,8 @@
+ {
+   tree target = gimple_call_fn (call);
+ 
++  if (!target)
++    return;
+   if (TREE_CODE (target) == SSA_NAME)
+     ipa_analyze_indirect_call_uses (node, info, parms_info, call, target);
+   else if (TREE_CODE (target) == OBJ_TYPE_REF)
+
+=== modified file 'gcc/optabs.h'
+--- old/gcc/optabs.h	2011-01-03 20:52:22 +0000
++++ new/gcc/optabs.h	2011-05-05 15:43:06 +0000
+@@ -578,6 +578,9 @@
+   COI_satfract,
+   COI_satfractuns,
+ 
++  COI_vec_load_lanes,
++  COI_vec_store_lanes,
++
+   COI_MAX
+ };
+ 
+@@ -598,6 +601,8 @@
+ #define fractuns_optab (&convert_optab_table[COI_fractuns])
+ #define satfract_optab (&convert_optab_table[COI_satfract])
+ #define satfractuns_optab (&convert_optab_table[COI_satfractuns])
++#define vec_load_lanes_optab (&convert_optab_table[COI_vec_load_lanes])
++#define vec_store_lanes_optab (&convert_optab_table[COI_vec_store_lanes])
+ 
+ /* Contains the optab used for each rtx code.  */
+ extern optab code_to_optab[NUM_RTX_CODE + 1];
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c'
+--- old/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c	2009-04-20 10:26:18 +0000
++++ new/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c	2011-05-05 15:46:10 +0000
+@@ -26,7 +26,7 @@
+     }
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided_wide } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided_wide } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided4 } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c'
+--- old/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c	2011-05-05 15:46:10 +0000
+@@ -113,7 +113,7 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect"  {target { vect_strided && vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect"  {target { vect_strided8 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided8 && vect_int_mult } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c'
+--- old/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c	2008-08-26 08:14:37 +0000
++++ new/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c	2011-05-05 15:44:00 +0000
+@@ -20,7 +20,7 @@
+   return avg;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide  } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide  } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd  } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd  } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c'
+--- old/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c	2010-08-26 11:13:58 +0000
++++ new/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c	2011-05-05 15:46:10 +0000
+@@ -13,5 +13,5 @@
+    }
+ }
+ 
+-/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided } } } */
++/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c	2011-05-05 15:46:10 +0000
+@@ -56,5 +56,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave  && vect_extract_even_odd_wide } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c'
+--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c	2011-04-24 07:45:49 +0000
++++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c	2011-05-05 15:46:10 +0000
+@@ -65,5 +65,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { vect_no_align || {! vect_strided } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { vect_no_align || { ! vect_strided2 } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c	2011-05-05 15:46:10 +0000
+@@ -54,5 +54,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c	2011-05-05 15:46:10 +0000
+@@ -53,5 +53,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c	2007-10-21 09:01:16 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c	2011-05-05 15:46:10 +0000
+@@ -47,5 +47,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_interleave } } } */
++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c	2011-05-05 15:46:10 +0000
+@@ -50,5 +50,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/pr30843.c'
+--- old/gcc/testsuite/gcc.dg/vect/pr30843.c	2007-02-22 12:30:12 +0000
++++ new/gcc/testsuite/gcc.dg/vect/pr30843.c	2011-05-05 15:46:10 +0000
+@@ -20,6 +20,6 @@
+     }
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided4 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/pr33866.c'
+--- old/gcc/testsuite/gcc.dg/vect/pr33866.c	2007-10-30 08:26:14 +0000
++++ new/gcc/testsuite/gcc.dg/vect/pr33866.c	2011-05-05 15:46:10 +0000
+@@ -27,6 +27,6 @@
+ }
+ 
+ /* Needs interleaving support.  */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/pr37539.c'
+--- old/gcc/testsuite/gcc.dg/vect/pr37539.c	2009-11-26 02:03:50 +0000
++++ new/gcc/testsuite/gcc.dg/vect/pr37539.c	2011-05-05 15:46:10 +0000
+@@ -40,7 +40,7 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_strided_wide } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_strided4 && vect_strided2 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+ 
+
+=== removed file 'gcc/testsuite/gcc.dg/vect/slp-11.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-11.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-11.c	1970-01-01 00:00:00 +0000
+@@ -1,113 +0,0 @@
+-/* { dg-require-effective-target vect_int } */
+-
+-#include <stdarg.h>
+-#include "tree-vect.h"
+-
+-#define N 8 
+-
+-int
+-main1 ()
+-{
+-  int i;
+-  unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
+-  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
+-  float out2[N*8];
+-
+-  /* Different operations - not SLPable.  */
+-  for (i = 0; i < N; i++)
+-    {
+-      a0 = in[i*8] + 5;
+-      a1 = in[i*8 + 1] * 6;
+-      a2 = in[i*8 + 2] + 7;
+-      a3 = in[i*8 + 3] + 8;
+-      a4 = in[i*8 + 4] + 9;
+-      a5 = in[i*8 + 5] + 10;
+-      a6 = in[i*8 + 6] + 11;
+-      a7 = in[i*8 + 7] + 12;
+-
+-      b0 = a0 * 3;
+-      b1 = a1 * 2;
+-      b2 = a2 * 12;
+-      b3 = a3 * 5;
+-      b4 = a4 * 8;
+-      b5 = a5 * 4;
+-      b6 = a6 * 3;
+-      b7 = a7 * 2;
+-
+-      out[i*8] = b0 - 2;
+-      out[i*8 + 1] = b1 - 3; 
+-      out[i*8 + 2] = b2 - 2;
+-      out[i*8 + 3] = b3 - 1;
+-      out[i*8 + 4] = b4 - 8;
+-      out[i*8 + 5] = b5 - 7;
+-      out[i*8 + 6] = b6 - 3;
+-      out[i*8 + 7] = b7 - 7;
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N; i++)
+-    {
+-      if (out[i*8] !=  (in[i*8] + 5) * 3 - 2
+-         || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3
+-         || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2
+-         || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1
+-         || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8
+-         || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7
+-         || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3
+-         || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7)
+-	abort ();
+-    }
+-
+-  /* Requires permutation - not SLPable.  */
+-  for (i = 0; i < N*2; i++)
+-    {
+-      out[i*4] = (in[i*4] + 2) * 3;
+-      out[i*4 + 1] = (in[i*4 + 2] + 2) * 7;
+-      out[i*4 + 2] = (in[i*4 + 1] + 7) * 3;
+-      out[i*4 + 3] = (in[i*4 + 3] + 3) * 4;
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N*2; i++)
+-    {
+-      if (out[i*4] !=  (in[i*4] + 2) * 3
+-         || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7
+-         || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3
+-         || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4)
+-        abort ();
+-    }
+-
+-  /* Different operations - not SLPable.  */
+-  for (i = 0; i < N*4; i++)
+-    {
+-      out2[i*2] = ((float) in[i*2] * 2 + 6) ;
+-      out2[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7);
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N*4; i++)
+-    {
+-      if (out2[i*2] !=  ((float) in[i*2] * 2 + 6)
+-         || out2[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7))
+-        abort ();
+-    }
+-
+-
+-  return 0;
+-}
+-
+-int main (void)
+-{
+-  check_vect ();
+-
+-  main1 ();
+-
+-  return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect"  { target { { vect_uintfloat_cvt && vect_strided_wide } &&  vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect"  { target { { { ! vect_uintfloat_cvt } && vect_strided_wide } &&  vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect"  {target  { ! { vect_int_mult && vect_strided_wide } } } } }  */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0  "vect"  } } */
+-/* { dg-final { cleanup-tree-dump "vect" } } */
+-  
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-11a.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-11a.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-11a.c	2011-05-05 15:46:10 +0000
+@@ -0,0 +1,75 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 8
++
++int
++main1 ()
++{
++  int i;
++  unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++
++  /* Different operations - not SLPable.  */
++  for (i = 0; i < N; i++)
++    {
++      a0 = in[i*8] + 5;
++      a1 = in[i*8 + 1] * 6;
++      a2 = in[i*8 + 2] + 7;
++      a3 = in[i*8 + 3] + 8;
++      a4 = in[i*8 + 4] + 9;
++      a5 = in[i*8 + 5] + 10;
++      a6 = in[i*8 + 6] + 11;
++      a7 = in[i*8 + 7] + 12;
++
++      b0 = a0 * 3;
++      b1 = a1 * 2;
++      b2 = a2 * 12;
++      b3 = a3 * 5;
++      b4 = a4 * 8;
++      b5 = a5 * 4;
++      b6 = a6 * 3;
++      b7 = a7 * 2;
++
++      out[i*8] = b0 - 2;
++      out[i*8 + 1] = b1 - 3;
++      out[i*8 + 2] = b2 - 2;
++      out[i*8 + 3] = b3 - 1;
++      out[i*8 + 4] = b4 - 8;
++      out[i*8 + 5] = b5 - 7;
++      out[i*8 + 6] = b6 - 3;
++      out[i*8 + 7] = b7 - 7;
++    }
++
++  /* check results:  */
++  for (i = 0; i < N; i++)
++    {
++      if (out[i*8] !=  (in[i*8] + 5) * 3 - 2
++         || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3
++         || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2
++         || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1
++         || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8
++         || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7
++         || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3
++         || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7)
++	abort ();
++    }
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-11b.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-11b.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-11b.c	2011-05-05 15:46:10 +0000
+@@ -0,0 +1,49 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 8
++
++int
++main1 ()
++{
++  int i;
++  unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++
++  /* Requires permutation - not SLPable.  */
++  for (i = 0; i < N*2; i++)
++    {
++      out[i*4] = (in[i*4] + 2) * 3;
++      out[i*4 + 1] = (in[i*4 + 2] + 2) * 7;
++      out[i*4 + 2] = (in[i*4 + 1] + 7) * 3;
++      out[i*4 + 3] = (in[i*4 + 3] + 3) * 4;
++    }
++
++  /* check results:  */
++  for (i = 0; i < N*2; i++)
++    {
++      if (out[i*4] !=  (in[i*4] + 2) * 3
++         || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7
++         || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3
++         || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4)
++        abort ();
++    }
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided4 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided4 && vect_int_mult } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-11c.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-11c.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-11c.c	2011-05-05 15:46:10 +0000
+@@ -0,0 +1,46 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 8
++
++int
++main1 ()
++{
++  int i;
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++  float out[N*8];
++
++  /* Different operations - not SLPable.  */
++  for (i = 0; i < N*4; i++)
++    {
++      out[i*2] = ((float) in[i*2] * 2 + 6) ;
++      out[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7);
++    }
++
++  /* check results:  */
++  for (i = 0; i < N*4; i++)
++    {
++      if (out[i*2] !=  ((float) in[i*2] * 2 + 6)
++         || out[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7))
++        abort ();
++    }
++
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0  "vect"  } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12a.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-12a.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-12a.c	2011-05-05 15:46:10 +0000
+@@ -11,7 +11,7 @@
+   int i;
+   unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
+   unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
+-  unsigned int ia[N], ib[N*2];
++  unsigned int ia[N];
+ 
+   for (i = 0; i < N; i++)
+     {
+@@ -61,27 +61,6 @@
+ 	abort ();
+     }
+ 
+-  for (i = 0; i < N*2; i++)
+-    {
+-      out[i*4] = (in[i*4] + 2) * 3;
+-      out[i*4 + 1] = (in[i*4 + 1] + 2) * 7;
+-      out[i*4 + 2] = (in[i*4 + 2] + 7) * 3;
+-      out[i*4 + 3] = (in[i*4 + 3] + 7) * 7;
+-
+-      ib[i] = 7;
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N*2; i++)
+-    {
+-      if (out[i*4] !=  (in[i*4] + 2) * 3
+-         || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7
+-         || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3
+-         || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7 
+-         || ib[i] != 7)
+-        abort ();
+-    }
+-
+   return 0;
+ }
+ 
+@@ -94,11 +73,8 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect"  {target { vect_strided_wide && vect_int_mult} } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect"  {target  { ! vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target  { ! vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+-  
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12b.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-12b.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-12b.c	2011-05-05 15:46:10 +0000
+@@ -43,9 +43,9 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  {target { vect_strided_wide && vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect"  {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect"  {target { vect_strided_wide && vect_int_mult } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect"  {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_strided2 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect"  { target { ! { vect_strided2 && vect_int_mult } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect"  { target { vect_strided2 && vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect"  { target { ! { vect_strided2 && vect_int_mult } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-12c.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-12c.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-12c.c	2011-05-05 15:44:41 +0000
+@@ -0,0 +1,53 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 8
++
++int
++main1 ()
++{
++  int i;
++  unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++  unsigned int ia[N*2];
++
++  for (i = 0; i < N*2; i++)
++    {
++      out[i*4] = (in[i*4] + 2) * 3;
++      out[i*4 + 1] = (in[i*4 + 1] + 2) * 7;
++      out[i*4 + 2] = (in[i*4 + 2] + 7) * 3;
++      out[i*4 + 3] = (in[i*4 + 3] + 7) * 7;
++
++      ia[i] = 7;
++    }
++
++  /* check results:  */
++  for (i = 0; i < N*2; i++)
++    {
++      if (out[i*4] !=  (in[i*4] + 2) * 3
++         || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7
++         || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3
++         || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7
++         || ia[i] != 7)
++        abort ();
++    }
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect"  { target { ! vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_int_mult } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_int_mult } } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-18.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-18.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-18.c	2011-05-05 15:46:10 +0000
+@@ -91,7 +91,7 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_strided } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== removed file 'gcc/testsuite/gcc.dg/vect/slp-19.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-19.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-19.c	1970-01-01 00:00:00 +0000
+@@ -1,154 +0,0 @@
+-/* { dg-require-effective-target vect_int } */
+-
+-#include <stdarg.h>
+-#include "tree-vect.h"
+-
+-#define N 16 
+-
+-int
+-main1 ()
+-{
+-  unsigned int i;
+-  unsigned int out[N*8];
+-  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
+-  unsigned int ia[N*2], a0, a1, a2, a3;
+-
+-  for (i = 0; i < N; i++)
+-    {
+-      out[i*8] = in[i*8];
+-      out[i*8 + 1] = in[i*8 + 1];
+-      out[i*8 + 2] = in[i*8 + 2];
+-      out[i*8 + 3] = in[i*8 + 3];
+-      out[i*8 + 4] = in[i*8 + 4];
+-      out[i*8 + 5] = in[i*8 + 5];
+-      out[i*8 + 6] = in[i*8 + 6];
+-      out[i*8 + 7] = in[i*8 + 7];
+-    
+-      ia[i] = in[i*8 + 2];
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N; i++)
+-    {
+-      if (out[i*8] !=  in[i*8]
+-         || out[i*8 + 1] != in[i*8 + 1]
+-         || out[i*8 + 2] != in[i*8 + 2]
+-         || out[i*8 + 3] != in[i*8 + 3]
+-         || out[i*8 + 4] != in[i*8 + 4]
+-         || out[i*8 + 5] != in[i*8 + 5]
+-         || out[i*8 + 6] != in[i*8 + 6]
+-         || out[i*8 + 7] != in[i*8 + 7]
+-         || ia[i] != in[i*8 + 2])
+-	abort ();
+-    }
+-
+-  for (i = 0; i < N*2; i++)
+-    {
+-      a0 = in[i*4] + 1;
+-      a1 = in[i*4 + 1] + 2;
+-      a2 = in[i*4 + 2] + 3;
+-      a3 = in[i*4 + 3] + 4;
+-
+-      out[i*4] = a0;
+-      out[i*4 + 1] = a1;
+-      out[i*4 + 2] = a2;
+-      out[i*4 + 3] = a3;
+-
+-      ia[i] = a2;
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N*2; i++)
+-    {
+-      if (out[i*4] !=  in[i*4] + 1
+-         || out[i*4 + 1] != in[i*4 + 1] + 2
+-         || out[i*4 + 2] != in[i*4 + 2] + 3
+-         || out[i*4 + 3] != in[i*4 + 3] + 4
+-         || ia[i] != in[i*4 + 2] + 3)
+-        abort ();
+-    }
+-
+-  /* The last stmt requires interleaving of not power of 2 size - not 
+-     vectorizable.  */
+-  for (i = 0; i < N/2; i++)
+-    {
+-      out[i*12] = in[i*12];
+-      out[i*12 + 1] = in[i*12 + 1];
+-      out[i*12 + 2] = in[i*12 + 2];
+-      out[i*12 + 3] = in[i*12 + 3];
+-      out[i*12 + 4] = in[i*12 + 4];
+-      out[i*12 + 5] = in[i*12 + 5];
+-      out[i*12 + 6] = in[i*12 + 6];
+-      out[i*12 + 7] = in[i*12 + 7];
+-      out[i*12 + 8] = in[i*12 + 8];
+-      out[i*12 + 9] = in[i*12 + 9];
+-      out[i*12 + 10] = in[i*12 + 10];
+-      out[i*12 + 11] = in[i*12 + 11];
+-
+-      ia[i] = in[i*12 + 7];
+-    }
+-
+-  /* check results:  */
+-  for (i = 0; i < N/2; i++)
+-    {
+-      if (out[i*12] !=  in[i*12]
+-         || out[i*12 + 1] != in[i*12 + 1]
+-         || out[i*12 + 2] != in[i*12 + 2]
+-         || out[i*12 + 3] != in[i*12 + 3]
+-         || out[i*12 + 4] != in[i*12 + 4]
+-         || out[i*12 + 5] != in[i*12 + 5]
+-         || out[i*12 + 6] != in[i*12 + 6]
+-         || out[i*12 + 7] != in[i*12 + 7]
+-         || out[i*12 + 8] != in[i*12 + 8]
+-         || out[i*12 + 9] != in[i*12 + 9]
+-         || out[i*12 + 10] != in[i*12 + 10]
+-         || out[i*12 + 11] != in[i*12 + 11]
+-         || ia[i] != in[i*12 + 7])
+-        abort ();
+-    }
+-
+-  /* Hybrid SLP with unrolling by 2.  */
+-  for (i = 0; i < N; i++)
+-    {
+-      out[i*6] = in[i*6];
+-      out[i*6 + 1] = in[i*6 + 1];
+-      out[i*6 + 2] = in[i*6 + 2];
+-      out[i*6 + 3] = in[i*6 + 3];
+-      out[i*6 + 4] = in[i*6 + 4];
+-      out[i*6 + 5] = in[i*6 + 5];
+-    
+-      ia[i] = i;
+-    } 
+-    
+-  /* check results:  */
+-  for (i = 0; i < N/2; i++)
+-    {
+-      if (out[i*6] !=  in[i*6]
+-         || out[i*6 + 1] != in[i*6 + 1]
+-         || out[i*6 + 2] != in[i*6 + 2]
+-         || out[i*6 + 3] != in[i*6 + 3]
+-         || out[i*6 + 4] != in[i*6 + 4]
+-         || out[i*6 + 5] != in[i*6 + 5]
+-         || ia[i] != i)
+-        abort ();
+-    }
+-
+-
+-  return 0;
+-}
+-
+-int main (void)
+-{
+-  check_vect ();
+-
+-  main1 ();
+-
+-  return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target  vect_strided_wide  } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target  { ! { vect_strided_wide } } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect"  { target  vect_strided_wide  } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect"  { target { ! { vect_strided_wide } } } } } */
+-/* { dg-final { cleanup-tree-dump "vect" } } */
+-  
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-19a.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-19a.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-19a.c	2011-05-05 15:46:10 +0000
+@@ -0,0 +1,61 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 16
++
++int
++main1 ()
++{
++  unsigned int i;
++  unsigned int out[N*8];
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++  unsigned int ia[N*2];
++
++  for (i = 0; i < N; i++)
++    {
++      out[i*8] = in[i*8];
++      out[i*8 + 1] = in[i*8 + 1];
++      out[i*8 + 2] = in[i*8 + 2];
++      out[i*8 + 3] = in[i*8 + 3];
++      out[i*8 + 4] = in[i*8 + 4];
++      out[i*8 + 5] = in[i*8 + 5];
++      out[i*8 + 6] = in[i*8 + 6];
++      out[i*8 + 7] = in[i*8 + 7];
++
++      ia[i] = in[i*8 + 2];
++    }
++
++  /* check results:  */
++  for (i = 0; i < N; i++)
++    {
++      if (out[i*8] !=  in[i*8]
++         || out[i*8 + 1] != in[i*8 + 1]
++         || out[i*8 + 2] != in[i*8 + 2]
++         || out[i*8 + 3] != in[i*8 + 3]
++         || out[i*8 + 4] != in[i*8 + 4]
++         || out[i*8 + 5] != in[i*8 + 5]
++         || out[i*8 + 6] != in[i*8 + 6]
++         || out[i*8 + 7] != in[i*8 + 7]
++         || ia[i] != in[i*8 + 2])
++	abort ();
++    }
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided8 } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided8 } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided8} } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-19b.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-19b.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-19b.c	2011-05-05 15:46:10 +0000
+@@ -0,0 +1,58 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 16
++
++int
++main1 ()
++{
++  unsigned int i;
++  unsigned int out[N*8];
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++  unsigned int ia[N*2], a0, a1, a2, a3;
++
++  for (i = 0; i < N*2; i++)
++    {
++      a0 = in[i*4] + 1;
++      a1 = in[i*4 + 1] + 2;
++      a2 = in[i*4 + 2] + 3;
++      a3 = in[i*4 + 3] + 4;
++
++      out[i*4] = a0;
++      out[i*4 + 1] = a1;
++      out[i*4 + 2] = a2;
++      out[i*4 + 3] = a3;
++
++      ia[i] = a2;
++    }
++
++  /* check results:  */
++  for (i = 0; i < N*2; i++)
++    {
++      if (out[i*4] !=  in[i*4] + 1
++         || out[i*4 + 1] != in[i*4 + 1] + 2
++         || out[i*4 + 2] != in[i*4 + 2] + 3
++         || out[i*4 + 3] != in[i*4 + 3] + 4
++         || ia[i] != in[i*4 + 2] + 3)
++        abort ();
++    }
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided4 } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided4 } } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-19c.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-19c.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-19c.c	2011-05-05 15:44:41 +0000
+@@ -0,0 +1,95 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 16
++
++int
++main1 ()
++{
++  unsigned int i;
++  unsigned int out[N*8];
++  unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
++  unsigned int ia[N*2], a0, a1, a2, a3;
++
++  /* The last stmt requires interleaving of not power of 2 size - not
++     vectorizable.  */
++  for (i = 0; i < N/2; i++)
++    {
++      out[i*12] = in[i*12];
++      out[i*12 + 1] = in[i*12 + 1];
++      out[i*12 + 2] = in[i*12 + 2];
++      out[i*12 + 3] = in[i*12 + 3];
++      out[i*12 + 4] = in[i*12 + 4];
++      out[i*12 + 5] = in[i*12 + 5];
++      out[i*12 + 6] = in[i*12 + 6];
++      out[i*12 + 7] = in[i*12 + 7];
++      out[i*12 + 8] = in[i*12 + 8];
++      out[i*12 + 9] = in[i*12 + 9];
++      out[i*12 + 10] = in[i*12 + 10];
++      out[i*12 + 11] = in[i*12 + 11];
++
++      ia[i] = in[i*12 + 7];
++    }
++
++  /* check results:  */
++  for (i = 0; i < N/2; i++)
++    {
++      if (out[i*12] !=  in[i*12]
++         || out[i*12 + 1] != in[i*12 + 1]
++         || out[i*12 + 2] != in[i*12 + 2]
++         || out[i*12 + 3] != in[i*12 + 3]
++         || out[i*12 + 4] != in[i*12 + 4]
++         || out[i*12 + 5] != in[i*12 + 5]
++         || out[i*12 + 6] != in[i*12 + 6]
++         || out[i*12 + 7] != in[i*12 + 7]
++         || out[i*12 + 8] != in[i*12 + 8]
++         || out[i*12 + 9] != in[i*12 + 9]
++         || out[i*12 + 10] != in[i*12 + 10]
++         || out[i*12 + 11] != in[i*12 + 11]
++         || ia[i] != in[i*12 + 7])
++        abort ();
++    }
++
++  /* Hybrid SLP with unrolling by 2.  */
++  for (i = 0; i < N; i++)
++    {
++      out[i*6] = in[i*6];
++      out[i*6 + 1] = in[i*6 + 1];
++      out[i*6 + 2] = in[i*6 + 2];
++      out[i*6 + 3] = in[i*6 + 3];
++      out[i*6 + 4] = in[i*6 + 4];
++      out[i*6 + 5] = in[i*6 + 5];
++
++      ia[i] = i;
++    }
++
++  /* check results:  */
++  for (i = 0; i < N/2; i++)
++    {
++      if (out[i*6] !=  in[i*6]
++         || out[i*6 + 1] != in[i*6 + 1]
++         || out[i*6 + 2] != in[i*6 + 2]
++         || out[i*6 + 3] != in[i*6 + 3]
++         || out[i*6 + 4] != in[i*6 + 4]
++         || out[i*6 + 5] != in[i*6 + 5]
++         || ia[i] != i)
++        abort ();
++    }
++
++  return 0;
++}
++
++int main (void)
++{
++  check_vect ();
++
++  main1 ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-21.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-21.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-21.c	2011-05-05 15:46:10 +0000
+@@ -199,9 +199,9 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect"  { target { vect_strided || vect_extract_even_odd } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target  { ! { vect_strided || vect_extract_even_odd } } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided }  } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect"  { target { ! { vect_strided } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect"  { target { vect_strided4 || vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target  { ! { vect_strided4 || vect_extract_even_odd } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided4 }  } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect"  { target { ! { vect_strided4 } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-23.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-23.c	2011-01-10 12:51:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-23.c	2011-05-05 15:46:10 +0000
+@@ -106,8 +106,8 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided_wide } && {! { vect_no_align} } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide || vect_no_align} } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */
+ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-reduc-6.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c	2011-05-05 15:46:10 +0000
+@@ -42,7 +42,7 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! vect_unpack } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! { vect_unpack || vect_strided2 } } } } } } */
+ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
+ /* { dg-final { scan-tree-dump-times "different interleaving chains in one node" 1 "vect" { target { ! vect_no_int_add } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-1.c	2010-08-19 10:23:50 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-1.c	2011-05-05 15:46:10 +0000
+@@ -85,6 +85,6 @@
+   fbar (a);
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_strided2 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-10.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-10.c	2010-05-27 12:23:45 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-10.c	2011-05-05 15:46:10 +0000
+@@ -22,5 +22,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_strided2 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-107.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-107.c	2008-08-19 08:06:54 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-107.c	2011-05-05 15:46:10 +0000
+@@ -40,6 +40,6 @@
+   return main1 ();
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-98.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-98.c	2008-08-02 11:05:47 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-98.c	2011-05-05 15:46:10 +0000
+@@ -38,6 +38,6 @@
+ }
+ 
+ /* Needs interleaving support.  */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail  { vect_interleave && vect_extract_even_odd_wide } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail  vect_strided4 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c	2011-03-27 09:38:18 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c	2011-05-05 15:46:10 +0000
+@@ -82,5 +82,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { vect_no_align || {! vect_strided } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { vect_no_align || { ! vect_strided2 } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c	2011-05-05 15:46:10 +0000
+@@ -71,6 +71,6 @@
+   return 0;
+ }   
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c	2011-05-05 15:46:10 +0000
+@@ -55,6 +55,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c	2011-05-05 15:46:10 +0000
+@@ -68,6 +68,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided4 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c	2011-05-05 15:46:10 +0000
+@@ -62,6 +62,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c	2010-05-27 12:23:45 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c	2011-05-05 15:46:10 +0000
+@@ -61,6 +61,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c	2011-05-05 15:46:10 +0000
+@@ -69,6 +69,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c	2011-05-05 15:46:10 +0000
+@@ -76,6 +76,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c	2011-05-05 15:46:10 +0000
+@@ -81,6 +81,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-float.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-float.c	2008-08-19 08:06:54 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-float.c	2011-05-05 15:46:10 +0000
+@@ -39,7 +39,7 @@
+ }
+ 
+ /* Needs interleaving support.  */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c	2011-05-05 15:46:10 +0000
+@@ -71,6 +71,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c	2011-05-05 15:46:10 +0000
+@@ -71,6 +71,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c	2011-05-05 15:46:10 +0000
+@@ -72,5 +72,5 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c	2008-08-12 05:31:57 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c	2011-05-05 15:46:10 +0000
+@@ -55,6 +55,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave || vect_strided2 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c	2007-10-21 09:01:16 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c	2011-05-05 15:46:10 +0000
+@@ -65,8 +65,8 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect"  { target { vect_interleave && vect_pack_trunc  } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { { ! { vect_interleave } } && { vect_pack_trunc } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect"  { target { { vect_interleave || vect_strided4 } && vect_pack_trunc } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { { ! { vect_interleave || vect_strided4 } } && { vect_pack_trunc } } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c	2011-05-05 15:46:10 +0000
+@@ -39,7 +39,7 @@
+ }
+ 
+ /* Needs interleaving support.  */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave || vect_strided2 } } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c	2011-05-05 15:46:10 +0000
+@@ -55,6 +55,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c	2011-05-05 15:46:25 +0000
+@@ -0,0 +1,112 @@
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 128
++
++typedef struct {
++   unsigned short a;
++   unsigned short b;
++   unsigned short c;
++} s;
++
++#define A(I) (I)
++#define B(I) ((I) * 2)
++#define C(I) ((unsigned short) ~((I) ^ 0x18))
++
++void __attribute__ ((noinline))
++check1 (s *res)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    if (res[i].a != C (i)
++	|| res[i].b != A (i)
++	|| res[i].c != B (i))
++      abort ();
++}
++
++void __attribute__ ((noinline))
++check2 (unsigned short *res)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    if (res[i] != (unsigned short) (A (i) + B (i) + C (i)))
++      abort ();
++}
++
++void __attribute__ ((noinline))
++check3 (s *res)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    if (res[i].a != i
++	|| res[i].b != i
++	|| res[i].c != i)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++check4 (unsigned short *res)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    if (res[i] != (unsigned short) (A (i) + B (i)))
++      abort ();
++}
++
++void __attribute__ ((noinline))
++main1 (s *arr)
++{
++  int i;
++  s *ptr = arr;
++  s res1[N];
++  unsigned short res2[N];
++
++  for (i = 0; i < N; i++)
++    {
++      res1[i].a = arr[i].c;
++      res1[i].b = arr[i].a;
++      res1[i].c = arr[i].b;
++    }
++  check1 (res1);
++
++  for (i = 0; i < N; i++)
++    res2[i] = arr[i].a + arr[i].b + arr[i].c;
++  check2 (res2);
++
++  for (i = 0; i < N; i++)
++    {
++      res1[i].a = i;
++      res1[i].b = i;
++      res1[i].c = i;
++    }
++  check3 (res1);
++
++  for (i = 0; i < N; i++)
++    res2[i] = arr[i].a + arr[i].b;
++  check4 (res2);
++}
++
++int main (void)
++{
++  int i;
++  s arr[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      arr[i].a = A (i);
++      arr[i].b = B (i);
++      arr[i].c = C (i);
++    }
++  main1 (arr);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect"  { target vect_strided3 } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c	2011-05-05 15:46:10 +0000
+@@ -68,6 +68,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided4 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c	2011-05-05 15:46:10 +0000
+@@ -63,6 +63,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided4 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c	2011-05-05 15:46:10 +0000
+@@ -77,6 +77,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c	2010-05-27 12:23:45 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c	2011-05-05 15:46:10 +0000
+@@ -60,6 +60,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c	2011-05-05 15:46:10 +0000
+@@ -71,6 +71,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c	2011-05-05 15:46:10 +0000
+@@ -54,6 +54,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+    
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c	2011-05-05 15:46:10 +0000
+@@ -78,6 +78,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c	2011-05-05 15:46:10 +0000
+@@ -98,6 +98,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c	2011-05-05 15:46:10 +0000
+@@ -83,6 +83,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c	2011-05-05 15:46:10 +0000
+@@ -85,6 +85,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+   
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-vfa-03.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c	2007-09-09 07:46:12 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c	2011-05-05 15:46:10 +0000
+@@ -53,6 +53,6 @@
+ } 
+ 
+ /* Needs interleaving support.  */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail  { vect_interleave && vect_extract_even_odd } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail  vect_strided2 } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
+--- old/gcc/testsuite/gcc.dg/vect/vect.exp	2011-04-24 07:45:49 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect.exp	2011-05-05 15:43:31 +0000
+@@ -75,15 +75,20 @@
+ lappend VECT_SLP_CFLAGS "-fdump-tree-slp-details"
+ 
+ # Main loop.
+-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]]  \
+-	"" $DEFAULT_VECTCFLAGS
+-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]]  \
+-	"" $DEFAULT_VECTCFLAGS
+-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]]  \
+-        "" $DEFAULT_VECTCFLAGS
+-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]]  \
+-        "" $VECT_SLP_CFLAGS
+-
++set VECT_ADDITIONAL_FLAGS [list ""]
++if { [check_effective_target_lto] } {
++    lappend VECT_ADDITIONAL_FLAGS "-flto"
++}
++foreach flags $VECT_ADDITIONAL_FLAGS {
++    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]]  \
++	$flags $DEFAULT_VECTCFLAGS
++    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]]  \
++	$flags $DEFAULT_VECTCFLAGS
++    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]]  \
++        $flags $DEFAULT_VECTCFLAGS
++    dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]]  \
++        $flags $VECT_SLP_CFLAGS
++}
+ 
+ #### Tests with special options
+ global SAVED_DEFAULT_VECTCFLAGS
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-05-06 11:28:27 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-06-02 12:12:00 +0000
+@@ -3139,29 +3139,6 @@
+     return $et_vect_extract_even_odd_saved
+ }
+ 
+-# Return 1 if the target supports vector even/odd elements extraction of
+-# vectors with SImode elements or larger, 0 otherwise.
+-
+-proc check_effective_target_vect_extract_even_odd_wide { } {
+-    global et_vect_extract_even_odd_wide_saved
+-    
+-    if [info exists et_vect_extract_even_odd_wide_saved] {
+-        verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2
+-    } else {
+-        set et_vect_extract_even_odd_wide_saved 0 
+-        if { [istarget powerpc*-*-*] 
+-             || [istarget i?86-*-*]
+-             || [istarget x86_64-*-*]
+-             || [istarget ia64-*-*]
+-             || [istarget spu-*-*] } {
+-           set et_vect_extract_even_odd_wide_saved 1
+-        }
+-    }
+-
+-    verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2
+-    return $et_vect_extract_even_odd_wide_saved
+-}
+-
+ # Return 1 if the target supports vector interleaving, 0 otherwise.
+ 
+ proc check_effective_target_vect_interleave { } {
+@@ -3184,41 +3161,30 @@
+     return $et_vect_interleave_saved
+ }
+ 
+-# Return 1 if the target supports vector interleaving and extract even/odd, 0 otherwise.
+-proc check_effective_target_vect_strided { } {
+-    global et_vect_strided_saved
+-
+-    if [info exists et_vect_strided_saved] {
+-        verbose "check_effective_target_vect_strided: using cached result" 2
+-    } else {
+-        set et_vect_strided_saved 0
+-        if { [check_effective_target_vect_interleave]
+-             && [check_effective_target_vect_extract_even_odd] } {
+-           set et_vect_strided_saved 1
+-        }
+-    }
+-
+-    verbose "check_effective_target_vect_strided: returning $et_vect_strided_saved" 2
+-    return $et_vect_strided_saved
+-}
+-
+-# Return 1 if the target supports vector interleaving and extract even/odd
+-# for wide element types, 0 otherwise.
+-proc check_effective_target_vect_strided_wide { } {
+-    global et_vect_strided_wide_saved
+-
+-    if [info exists et_vect_strided_wide_saved] {
+-        verbose "check_effective_target_vect_strided_wide: using cached result" 2
+-    } else {
+-        set et_vect_strided_wide_saved 0
+-        if { [check_effective_target_vect_interleave]
+-             && [check_effective_target_vect_extract_even_odd_wide] } {
+-           set et_vect_strided_wide_saved 1
+-        }
+-    }
+-
+-    verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2
+-    return $et_vect_strided_wide_saved
++foreach N {2 3 4 8} {
++    eval [string map [list N $N] {
++	# Return 1 if the target supports 2-vector interleaving
++	proc check_effective_target_vect_stridedN { } {
++	    global et_vect_stridedN_saved
++
++	    if [info exists et_vect_stridedN_saved] {
++		verbose "check_effective_target_vect_stridedN: using cached result" 2
++	    } else {
++		set et_vect_stridedN_saved 0
++		if { (N & -N) == N
++		     && [check_effective_target_vect_interleave]
++		     && [check_effective_target_vect_extract_even_odd] } {
++		    set et_vect_stridedN_saved 1
++		}
++		if { [istarget arm*-*-*] && N >= 2 && N <= 4 } {
++		    set et_vect_stridedN_saved 1
++		}
++	    }
++
++	    verbose "check_effective_target_vect_stridedN: returning $et_vect_stridedN_saved" 2
++	    return $et_vect_stridedN_saved
++	}
++    }]
+ }
+ 
+ # Return 1 if the target supports section-anchors
+
+=== modified file 'gcc/tree-cfg.c'
+--- old/gcc/tree-cfg.c	2011-02-12 21:11:33 +0000
++++ new/gcc/tree-cfg.c	2011-05-05 15:42:22 +0000
+@@ -3046,7 +3046,26 @@
+   tree fntype;
+   unsigned i;
+ 
+-  if (TREE_CODE (fn) != OBJ_TYPE_REF
++  if (gimple_call_internal_p (stmt))
++    {
++      if (fn)
++	{
++	  error ("gimple call has two targets");
++	  debug_generic_stmt (fn);
++	  return true;
++	}
++    }
++  else
++    {
++      if (!fn)
++	{
++	  error ("gimple call has no target");
++	  return true;
++	}
++    }
++
++  if (fn
++      && TREE_CODE (fn) != OBJ_TYPE_REF
+       && !is_gimple_val (fn))
+     {
+       error ("invalid function in gimple call");
+@@ -3054,9 +3073,10 @@
+       return true;
+     }
+ 
+-  if (!POINTER_TYPE_P (TREE_TYPE  (fn))
+-      || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE
+-	  && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE))
++  if (fn
++      && (!POINTER_TYPE_P (TREE_TYPE  (fn))
++	  || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE
++	      && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE)))
+     {
+       error ("non-function in gimple call");
+       return true;
+@@ -3076,8 +3096,12 @@
+       return true;
+     }
+ 
+-  fntype = TREE_TYPE (TREE_TYPE (fn));
+-  if (gimple_call_lhs (stmt)
++  if (fn)
++    fntype = TREE_TYPE (TREE_TYPE (fn));
++  else
++    fntype = NULL_TREE;
++  if (fntype
++      && gimple_call_lhs (stmt)
+       && !useless_type_conversion_p (TREE_TYPE (gimple_call_lhs (stmt)),
+ 				     TREE_TYPE (fntype))
+       /* ???  At least C++ misses conversions at assignments from
+@@ -4130,9 +4154,10 @@
+      didn't see a function declaration before the call.  */
+   if (is_gimple_call (stmt))
+     {
+-      tree decl;
++      tree fn, decl;
+ 
+-      if (!is_gimple_call_addr (gimple_call_fn (stmt)))
++      fn = gimple_call_fn (stmt);
++      if (fn && !is_gimple_call_addr (fn))
+ 	{
+ 	  error ("invalid function in call statement");
+ 	  return true;
+@@ -7484,6 +7509,8 @@
+ 	case GIMPLE_CALL:
+ 	  if (gimple_call_lhs (g))
+ 	    break;
++	  if (gimple_call_internal_p (g))
++	    break;
+ 
+ 	  /* This is a naked call, as opposed to a GIMPLE_CALL with an
+ 	     LHS.  All calls whose value is ignored should be
+
+=== modified file 'gcc/tree-eh.c'
+--- old/gcc/tree-eh.c	2011-05-10 06:31:59 +0000
++++ new/gcc/tree-eh.c	2011-06-02 12:12:00 +0000
+@@ -2745,7 +2745,7 @@
+       || gimple_call_lhs (twos)
+       || gimple_call_chain (ones)
+       || gimple_call_chain (twos)
+-      || !operand_equal_p (gimple_call_fn (ones), gimple_call_fn (twos), 0)
++      || !gimple_call_same_target_p (ones, twos)
+       || gimple_call_num_args (ones) != gimple_call_num_args (twos))
+     return false;
+ 
+
+=== modified file 'gcc/tree-inline.c'
+--- old/gcc/tree-inline.c	2011-05-05 21:02:06 +0000
++++ new/gcc/tree-inline.c	2011-06-02 12:12:00 +0000
+@@ -3471,10 +3471,13 @@
+       {
+ 	tree decl = gimple_call_fndecl (stmt);
+ 	tree addr = gimple_call_fn (stmt);
+-	tree funtype = TREE_TYPE (addr);
++	tree funtype = NULL_TREE;
+ 	bool stdarg = false;
+ 
+-	if (POINTER_TYPE_P (funtype))
++	if (addr)
++	  funtype = TREE_TYPE (addr);
++
++	if (funtype && POINTER_TYPE_P (funtype))
+ 	  funtype = TREE_TYPE (funtype);
+ 
+ 	/* Do not special case builtins where we see the body.
+@@ -3514,7 +3517,7 @@
+ 	if (decl)
+ 	  funtype = TREE_TYPE (decl);
+ 
+-	if (!VOID_TYPE_P (TREE_TYPE (funtype)))
++	if (funtype && !VOID_TYPE_P (TREE_TYPE (funtype)))
+ 	  cost += estimate_move_cost (TREE_TYPE (funtype));
+ 
+ 	if (funtype)
+
+=== modified file 'gcc/tree-ssa-ccp.c'
+--- old/gcc/tree-ssa-ccp.c	2011-01-31 16:52:22 +0000
++++ new/gcc/tree-ssa-ccp.c	2011-05-05 15:42:22 +0000
+@@ -1279,7 +1279,10 @@
+ 
+     case GIMPLE_CALL:
+       {
+-	tree fn = valueize_op (gimple_call_fn (stmt));
++	tree fn = gimple_call_fn (stmt);
++	if (!fn)
++	  return NULL_TREE;
++	fn = valueize_op (fn);
+ 	if (TREE_CODE (fn) == ADDR_EXPR
+ 	    && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL
+ 	    && DECL_BUILT_IN (TREE_OPERAND (fn, 0)))
+@@ -2310,6 +2313,11 @@
+ 	    return true;
+ 	  }
+ 
++	/* Internal calls provide no argument types, so the extra laxity
++	   for normal calls does not apply.  */
++	if (gimple_call_internal_p (stmt))
++	  return false;
++
+ 	/* Propagate into the call arguments.  Compared to replace_uses_in
+ 	   this can use the argument slot types for type verification
+ 	   instead of the current argument type.  We also can safely
+
+=== modified file 'gcc/tree-ssa-dom.c'
+--- old/gcc/tree-ssa-dom.c	2011-02-14 17:59:10 +0000
++++ new/gcc/tree-ssa-dom.c	2011-05-05 15:42:22 +0000
+@@ -64,7 +64,7 @@
+     struct { enum tree_code op;  tree opnd; } unary;
+     struct { enum tree_code op;  tree opnd0, opnd1; } binary;
+     struct { enum tree_code op;  tree opnd0, opnd1, opnd2; } ternary;
+-    struct { tree fn; bool pure; size_t nargs; tree *args; } call;
++    struct { gimple fn_from; bool pure; size_t nargs; tree *args; } call;
+   } ops;
+ };
+ 
+@@ -258,7 +258,7 @@
+ 
+       expr->type = TREE_TYPE (gimple_call_lhs (stmt));
+       expr->kind = EXPR_CALL;
+-      expr->ops.call.fn = gimple_call_fn (stmt);
++      expr->ops.call.fn_from = stmt;
+ 
+       if (gimple_call_flags (stmt) & (ECF_CONST | ECF_PURE))
+         expr->ops.call.pure = true;
+@@ -422,8 +422,8 @@
+ 
+         /* If the calls are to different functions, then they
+            clearly cannot be equal.  */
+-        if (! operand_equal_p (expr0->ops.call.fn,
+-                               expr1->ops.call.fn, 0))
++        if (!gimple_call_same_target_p (expr0->ops.call.fn_from,
++                                        expr1->ops.call.fn_from))
+           return false;
+ 
+         if (! expr0->ops.call.pure)
+@@ -503,9 +503,15 @@
+       {
+         size_t i;
+         enum tree_code code = CALL_EXPR;
++        gimple fn_from;
+ 
+         val = iterative_hash_object (code, val);
+-        val = iterative_hash_expr (expr->ops.call.fn, val);
++        fn_from = expr->ops.call.fn_from;
++        if (gimple_call_internal_p (fn_from))
++          val = iterative_hash_hashval_t
++            ((hashval_t) gimple_call_internal_fn (fn_from), val);
++        else
++          val = iterative_hash_expr (gimple_call_fn (fn_from), val);
+         for (i = 0; i < expr->ops.call.nargs; i++)
+           val = iterative_hash_expr (expr->ops.call.args[i], val);
+       }
+@@ -565,8 +571,14 @@
+         {
+           size_t i;
+           size_t nargs = element->expr.ops.call.nargs;
++          gimple fn_from;
+ 
+-          print_generic_expr (stream, element->expr.ops.call.fn, 0);
++          fn_from = element->expr.ops.call.fn_from;
++          if (gimple_call_internal_p (fn_from))
++            fputs (internal_fn_name (gimple_call_internal_fn (fn_from)),
++                   stream);
++          else
++            print_generic_expr (stream, gimple_call_fn (fn_from), 0);
+           fprintf (stream, " (");
+           for (i = 0; i < nargs; i++)
+             {
+
+=== modified file 'gcc/tree-ssa-pre.c'
+--- old/gcc/tree-ssa-pre.c	2011-02-15 13:04:47 +0000
++++ new/gcc/tree-ssa-pre.c	2011-05-05 15:42:22 +0000
+@@ -2657,11 +2657,13 @@
+ }
+ 
+ /* Return true if we can value number the call in STMT.  This is true
+-   if we have a pure or constant call.  */
++   if we have a pure or constant call to a real function.  */
+ 
+ static bool
+ can_value_number_call (gimple stmt)
+ {
++  if (gimple_call_internal_p (stmt))
++    return false;
+   if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
+     return true;
+   return false;
+@@ -4187,6 +4189,7 @@
+   gimple_stmt_iterator gsi;
+   gimple stmt;
+   unsigned i;
++  tree fn;
+ 
+   FOR_EACH_BB (b)
+     {
+@@ -4378,9 +4381,10 @@
+ 	  /* Visit indirect calls and turn them into direct calls if
+ 	     possible.  */
+ 	  if (is_gimple_call (stmt)
+-	      && TREE_CODE (gimple_call_fn (stmt)) == SSA_NAME)
++	      && (fn = gimple_call_fn (stmt))
++	      && TREE_CODE (fn) == SSA_NAME)
+ 	    {
+-	      tree fn = VN_INFO (gimple_call_fn (stmt))->valnum;
++	      fn = VN_INFO (fn)->valnum;
+ 	      if (TREE_CODE (fn) == ADDR_EXPR
+ 		  && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL)
+ 		{
+
+=== modified file 'gcc/tree-ssa-sccvn.c'
+--- old/gcc/tree-ssa-sccvn.c	2011-05-12 14:08:00 +0000
++++ new/gcc/tree-ssa-sccvn.c	2011-06-02 12:12:00 +0000
+@@ -2982,7 +2982,8 @@
+ 	  /* ???  We should handle stores from calls.  */
+ 	  else if (TREE_CODE (lhs) == SSA_NAME)
+ 	    {
+-	      if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
++	      if (!gimple_call_internal_p (stmt)
++		  && gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
+ 		changed = visit_reference_op_call (lhs, stmt);
+ 	      else
+ 		changed = defs_to_varying (stmt);
+
+=== modified file 'gcc/tree-ssa-structalias.c'
+--- old/gcc/tree-ssa-structalias.c	2011-02-10 15:29:52 +0000
++++ new/gcc/tree-ssa-structalias.c	2011-05-05 15:42:22 +0000
+@@ -4319,6 +4319,7 @@
+ 	    /* Fallthru to general call handling.  */;
+ 	  }
+       if (!in_ipa_mode
++	  || gimple_call_internal_p (t)
+ 	  || (fndecl
+ 	      && (!(fi = lookup_vi_for_tree (fndecl))
+ 		  || !fi->is_fn_info)))
+
+=== modified file 'gcc/tree-vect-data-refs.c'
+--- old/gcc/tree-vect-data-refs.c	2011-05-06 11:28:27 +0000
++++ new/gcc/tree-vect-data-refs.c	2011-06-02 12:12:00 +0000
+@@ -43,6 +43,45 @@
+ #include "expr.h"
+ #include "optabs.h"
+ 
++/* Return true if load- or store-lanes optab OPTAB is implemented for
++   COUNT vectors of type VECTYPE.  NAME is the name of OPTAB.  */
++
++static bool
++vect_lanes_optab_supported_p (const char *name, convert_optab optab,
++			      tree vectype, unsigned HOST_WIDE_INT count)
++{
++  enum machine_mode mode, array_mode;
++  bool limit_p;
++
++  mode = TYPE_MODE (vectype);
++  limit_p = !targetm.array_mode_supported_p (mode, count);
++  array_mode = mode_for_size (count * GET_MODE_BITSIZE (mode),
++			      MODE_INT, limit_p);
++
++  if (array_mode == BLKmode)
++    {
++      if (vect_print_dump_info (REPORT_DETAILS))
++	fprintf (vect_dump, "no array mode for %s[" HOST_WIDE_INT_PRINT_DEC "]",
++		 GET_MODE_NAME (mode), count);
++      return false;
++    }
++
++  if (convert_optab_handler (optab, array_mode, mode) == CODE_FOR_nothing)
++    {
++      if (vect_print_dump_info (REPORT_DETAILS))
++	fprintf (vect_dump, "cannot use %s<%s><%s>",
++		 name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode));
++      return false;
++    }
++
++  if (vect_print_dump_info (REPORT_DETAILS))
++    fprintf (vect_dump, "can use %s<%s><%s>",
++	     name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode));
++
++  return true;
++}
++
++
+ /* Return the smallest scalar part of STMT.
+    This is used to determine the vectype of the stmt.  We generally set the
+    vectype according to the type of the result (lhs).  For stmts whose
+@@ -2196,19 +2235,6 @@
+           return false;
+         }
+ 
+-      /* FORNOW: we handle only interleaving that is a power of 2.
+-         We don't fail here if it may be still possible to vectorize the
+-         group using SLP.  If not, the size of the group will be checked in
+-         vect_analyze_operations, and the vectorization will fail.  */
+-      if (exact_log2 (stride) == -1)
+-	{
+-	  if (vect_print_dump_info (REPORT_DETAILS))
+-	    fprintf (vect_dump, "interleaving is not a power of 2");
+-
+-	  if (slp_impossible)
+-	    return false;
+-	}
+-
+       if (stride == 0)
+         stride = count;
+ 
+@@ -2911,31 +2937,33 @@
+ 
+ /* Function vect_create_data_ref_ptr.
+ 
+-   Create a new pointer to vector type (vp), that points to the first location
+-   accessed in the loop by STMT, along with the def-use update chain to
+-   appropriately advance the pointer through the loop iterations. Also set
+-   aliasing information for the pointer.  This vector pointer is used by the
+-   callers to this function to create a memory reference expression for vector
+-   load/store access.
++   Create a new pointer-to-AGGR_TYPE variable (ap), that points to the first
++   location accessed in the loop by STMT, along with the def-use update
++   chain to appropriately advance the pointer through the loop iterations.
++   Also set aliasing information for the pointer.  This pointer is used by
++   the callers to this function to create a memory reference expression for
++   vector load/store access.
+ 
+    Input:
+    1. STMT: a stmt that references memory. Expected to be of the form
+          GIMPLE_ASSIGN <name, data-ref> or
+ 	 GIMPLE_ASSIGN <data-ref, name>.
+-   2. AT_LOOP: the loop where the vector memref is to be created.
+-   3. OFFSET (optional): an offset to be added to the initial address accessed
++   2. AGGR_TYPE: the type of the reference, which should be either a vector
++        or an array.
++   3. AT_LOOP: the loop where the vector memref is to be created.
++   4. OFFSET (optional): an offset to be added to the initial address accessed
+         by the data-ref in STMT.
+-   4. ONLY_INIT: indicate if vp is to be updated in the loop, or remain
++   5. ONLY_INIT: indicate if vp is to be updated in the loop, or remain
+         pointing to the initial address.
+-   5. TYPE: if not NULL indicates the required type of the data-ref.
++   6. TYPE: if not NULL indicates the required type of the data-ref.
+ 
+    Output:
+    1. Declare a new ptr to vector_type, and have it point to the base of the
+       data reference (initial addressed accessed by the data reference).
+       For example, for vector of type V8HI, the following code is generated:
+ 
+-      v8hi *vp;
+-      vp = (v8hi *)initial_address;
++      v8hi *ap;
++      ap = (v8hi *)initial_address;
+ 
+       if OFFSET is not supplied:
+          initial_address = &a[init];
+@@ -2955,7 +2983,7 @@
+    4. Return the pointer.  */
+ 
+ tree
+-vect_create_data_ref_ptr (gimple stmt, struct loop *at_loop,
++vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop,
+ 			  tree offset, tree *initial_address, gimple *ptr_incr,
+ 			  bool only_init, bool *inv_p)
+ {
+@@ -2965,17 +2993,16 @@
+   struct loop *loop = NULL;
+   bool nested_in_vect_loop = false;
+   struct loop *containing_loop = NULL;
+-  tree vectype = STMT_VINFO_VECTYPE (stmt_info);
+-  tree vect_ptr_type;
+-  tree vect_ptr;
++  tree aggr_ptr_type;
++  tree aggr_ptr;
+   tree new_temp;
+   gimple vec_stmt;
+   gimple_seq new_stmt_list = NULL;
+   edge pe = NULL;
+   basic_block new_bb;
+-  tree vect_ptr_init;
++  tree aggr_ptr_init;
+   struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info);
+-  tree vptr;
++  tree aptr;
+   gimple_stmt_iterator incr_gsi;
+   bool insert_after;
+   bool negative;
+@@ -2986,6 +3013,9 @@
+   gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
+   tree base;
+ 
++  gcc_assert (TREE_CODE (aggr_type) == ARRAY_TYPE
++	      || TREE_CODE (aggr_type) == VECTOR_TYPE);
++
+   if (loop_vinfo)
+     {
+       loop = LOOP_VINFO_LOOP (loop_vinfo);
+@@ -3020,8 +3050,9 @@
+   if (vect_print_dump_info (REPORT_DETAILS))
+     {
+       tree data_ref_base = base_name;
+-      fprintf (vect_dump, "create vector-pointer variable to type: ");
+-      print_generic_expr (vect_dump, vectype, TDF_SLIM);
++      fprintf (vect_dump, "create %s-pointer variable to type: ",
++	       tree_code_name[(int) TREE_CODE (aggr_type)]);
++      print_generic_expr (vect_dump, aggr_type, TDF_SLIM);
+       if (TREE_CODE (data_ref_base) == VAR_DECL
+           || TREE_CODE (data_ref_base) == ARRAY_REF)
+         fprintf (vect_dump, "  vectorizing an array ref: ");
+@@ -3032,27 +3063,28 @@
+       print_generic_expr (vect_dump, base_name, TDF_SLIM);
+     }
+ 
+-  /* (1) Create the new vector-pointer variable.  */
+-  vect_ptr_type = build_pointer_type (vectype);
++  /* (1) Create the new aggregate-pointer variable.  */
++  aggr_ptr_type = build_pointer_type (aggr_type);
+   base = get_base_address (DR_REF (dr));
+   if (base
+       && TREE_CODE (base) == MEM_REF)
+-    vect_ptr_type
+-      = build_qualified_type (vect_ptr_type,
++    aggr_ptr_type
++      = build_qualified_type (aggr_ptr_type,
+ 			      TYPE_QUALS (TREE_TYPE (TREE_OPERAND (base, 0))));
+-  vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
++  aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
+                                     get_name (base_name));
+ 
+-  /* Vector types inherit the alias set of their component type by default so
+-     we need to use a ref-all pointer if the data reference does not conflict
+-     with the created vector data reference because it is not addressable.  */
+-  if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr),
++  /* Vector and array types inherit the alias set of their component
++     type by default so we need to use a ref-all pointer if the data
++     reference does not conflict with the created aggregated data
++     reference because it is not addressable.  */
++  if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr),
+ 			      get_alias_set (DR_REF (dr))))
+     {
+-      vect_ptr_type
+-	= build_pointer_type_for_mode (vectype,
+-				       TYPE_MODE (vect_ptr_type), true);
+-      vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
++      aggr_ptr_type
++	= build_pointer_type_for_mode (aggr_type,
++				       TYPE_MODE (aggr_ptr_type), true);
++      aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
+ 					get_name (base_name));
+     }
+ 
+@@ -3063,14 +3095,14 @@
+       do
+ 	{
+ 	  tree lhs = gimple_assign_lhs (orig_stmt);
+-	  if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr),
++	  if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr),
+ 				      get_alias_set (lhs)))
+ 	    {
+-	      vect_ptr_type
+-		= build_pointer_type_for_mode (vectype,
+-					       TYPE_MODE (vect_ptr_type), true);
+-	      vect_ptr
+-		= vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
++	      aggr_ptr_type
++		= build_pointer_type_for_mode (aggr_type,
++					       TYPE_MODE (aggr_ptr_type), true);
++	      aggr_ptr
++		= vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
+ 					 get_name (base_name));
+ 	      break;
+ 	    }
+@@ -3080,7 +3112,7 @@
+       while (orig_stmt);
+     }
+ 
+-  add_referenced_var (vect_ptr);
++  add_referenced_var (aggr_ptr);
+ 
+   /* Note: If the dataref is in an inner-loop nested in LOOP, and we are
+      vectorizing LOOP (i.e., outer-loop vectorization), we need to create two
+@@ -3113,8 +3145,8 @@
+ 		vp2 = vp1 + step
+ 		if () goto LOOP   */
+ 
+-  /* (2) Calculate the initial address the vector-pointer, and set
+-         the vector-pointer to point to it before the loop.  */
++  /* (2) Calculate the initial address of the aggregate-pointer, and set
++     the aggregate-pointer to point to it before the loop.  */
+ 
+   /* Create: (&(base[init_val+offset]) in the loop preheader.  */
+ 
+@@ -3133,17 +3165,17 @@
+ 
+   *initial_address = new_temp;
+ 
+-  /* Create: p = (vectype *) initial_base  */
++  /* Create: p = (aggr_type *) initial_base  */
+   if (TREE_CODE (new_temp) != SSA_NAME
+-      || !useless_type_conversion_p (vect_ptr_type, TREE_TYPE (new_temp)))
++      || !useless_type_conversion_p (aggr_ptr_type, TREE_TYPE (new_temp)))
+     {
+-      vec_stmt = gimple_build_assign (vect_ptr,
+-				      fold_convert (vect_ptr_type, new_temp));
+-      vect_ptr_init = make_ssa_name (vect_ptr, vec_stmt);
++      vec_stmt = gimple_build_assign (aggr_ptr,
++				      fold_convert (aggr_ptr_type, new_temp));
++      aggr_ptr_init = make_ssa_name (aggr_ptr, vec_stmt);
+       /* Copy the points-to information if it exists. */
+       if (DR_PTR_INFO (dr))
+-	duplicate_ssa_name_ptr_info (vect_ptr_init, DR_PTR_INFO (dr));
+-      gimple_assign_set_lhs (vec_stmt, vect_ptr_init);
++	duplicate_ssa_name_ptr_info (aggr_ptr_init, DR_PTR_INFO (dr));
++      gimple_assign_set_lhs (vec_stmt, aggr_ptr_init);
+       if (pe)
+ 	{
+ 	  new_bb = gsi_insert_on_edge_immediate (pe, vec_stmt);
+@@ -3153,19 +3185,19 @@
+ 	gsi_insert_before (&gsi, vec_stmt, GSI_SAME_STMT);
+     }
+   else
+-    vect_ptr_init = new_temp;
++    aggr_ptr_init = new_temp;
+ 
+-  /* (3) Handle the updating of the vector-pointer inside the loop.
++  /* (3) Handle the updating of the aggregate-pointer inside the loop.
+      This is needed when ONLY_INIT is false, and also when AT_LOOP is the
+      inner-loop nested in LOOP (during outer-loop vectorization).  */
+ 
+   /* No update in loop is required.  */
+   if (only_init && (!loop_vinfo || at_loop == loop))
+-    vptr = vect_ptr_init;
++    aptr = aggr_ptr_init;
+   else
+     {
+-      /* The step of the vector pointer is the Vector Size.  */
+-      tree step = TYPE_SIZE_UNIT (vectype);
++      /* The step of the aggregate pointer is the type size.  */
++      tree step = TYPE_SIZE_UNIT (aggr_type);
+       /* One exception to the above is when the scalar step of the load in
+ 	 LOOP is zero. In this case the step here is also zero.  */
+       if (*inv_p)
+@@ -3175,9 +3207,9 @@
+ 
+       standard_iv_increment_position (loop, &incr_gsi, &insert_after);
+ 
+-      create_iv (vect_ptr_init,
+-		 fold_convert (vect_ptr_type, step),
+-		 vect_ptr, loop, &incr_gsi, insert_after,
++      create_iv (aggr_ptr_init,
++		 fold_convert (aggr_ptr_type, step),
++		 aggr_ptr, loop, &incr_gsi, insert_after,
+ 		 &indx_before_incr, &indx_after_incr);
+       incr = gsi_stmt (incr_gsi);
+       set_vinfo_for_stmt (incr, new_stmt_vec_info (incr, loop_vinfo, NULL));
+@@ -3191,14 +3223,14 @@
+       if (ptr_incr)
+ 	*ptr_incr = incr;
+ 
+-      vptr = indx_before_incr;
++      aptr = indx_before_incr;
+     }
+ 
+   if (!nested_in_vect_loop || only_init)
+-    return vptr;
+-
+-
+-  /* (4) Handle the updating of the vector-pointer inside the inner-loop
++    return aptr;
++
++
++  /* (4) Handle the updating of the aggregate-pointer inside the inner-loop
+      nested in LOOP, if exists.  */
+ 
+   gcc_assert (nested_in_vect_loop);
+@@ -3206,7 +3238,7 @@
+     {
+       standard_iv_increment_position (containing_loop, &incr_gsi,
+ 				      &insert_after);
+-      create_iv (vptr, fold_convert (vect_ptr_type, DR_STEP (dr)), vect_ptr,
++      create_iv (aptr, fold_convert (aggr_ptr_type, DR_STEP (dr)), aggr_ptr,
+ 		 containing_loop, &incr_gsi, insert_after, &indx_before_incr,
+ 		 &indx_after_incr);
+       incr = gsi_stmt (incr_gsi);
+@@ -3343,13 +3375,22 @@
+    and FALSE otherwise.  */
+ 
+ bool
+-vect_strided_store_supported (tree vectype)
++vect_strided_store_supported (tree vectype, unsigned HOST_WIDE_INT count)
+ {
+   optab interleave_high_optab, interleave_low_optab;
+   enum machine_mode mode;
+ 
+   mode = TYPE_MODE (vectype);
+ 
++  /* vect_permute_store_chain requires the group size to be a power of two.  */
++  if (exact_log2 (count) == -1)
++    {
++      if (vect_print_dump_info (REPORT_DETAILS))
++	fprintf (vect_dump, "the size of the group of strided accesses"
++		 " is not a power of 2");
++      return false;
++    }
++
+   /* Check that the operation is supported.  */
+   interleave_high_optab = optab_for_tree_code (VEC_INTERLEAVE_HIGH_EXPR,
+ 					       vectype, optab_default);
+@@ -3374,6 +3415,18 @@
+ }
+ 
+ 
++/* Return TRUE if vec_store_lanes is available for COUNT vectors of
++   type VECTYPE.  */
++
++bool
++vect_store_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count)
++{
++  return vect_lanes_optab_supported_p ("vec_store_lanes",
++				       vec_store_lanes_optab,
++				       vectype, count);
++}
++
++
+ /* Function vect_permute_store_chain.
+ 
+    Given a chain of interleaved stores in DR_CHAIN of LENGTH that must be
+@@ -3435,7 +3488,7 @@
+    I3:  4 12 20 28  5 13 21 30
+    I4:  6 14 22 30  7 15 23 31.  */
+ 
+-bool
++void
+ vect_permute_store_chain (VEC(tree,heap) *dr_chain,
+ 			  unsigned int length,
+ 			  gimple stmt,
+@@ -3449,9 +3502,7 @@
+   unsigned int j;
+   enum tree_code high_code, low_code;
+ 
+-  /* Check that the operation is supported.  */
+-  if (!vect_strided_store_supported (vectype))
+-    return false;
++  gcc_assert (vect_strided_store_supported (vectype, length));
+ 
+   *result_chain = VEC_copy (tree, heap, dr_chain);
+ 
+@@ -3504,7 +3555,6 @@
+ 	}
+       dr_chain = VEC_copy (tree, heap, *result_chain);
+     }
+-  return true;
+ }
+ 
+ /* Function vect_setup_realignment
+@@ -3674,8 +3724,9 @@
+ 
+       gcc_assert (!compute_in_loop);
+       vec_dest = vect_create_destination_var (scalar_dest, vectype);
+-      ptr = vect_create_data_ref_ptr (stmt, loop_for_initial_load, NULL_TREE,
+-				      &init_addr, &inc, true, &inv_p);
++      ptr = vect_create_data_ref_ptr (stmt, vectype, loop_for_initial_load,
++				      NULL_TREE, &init_addr, &inc,
++				      true, &inv_p);
+       new_stmt = gimple_build_assign_with_ops
+ 		   (BIT_AND_EXPR, NULL_TREE, ptr,
+ 		    build_int_cst (TREE_TYPE (ptr),
+@@ -3780,13 +3831,22 @@
+    and FALSE otherwise.  */
+ 
+ bool
+-vect_strided_load_supported (tree vectype)
++vect_strided_load_supported (tree vectype, unsigned HOST_WIDE_INT count)
+ {
+   optab perm_even_optab, perm_odd_optab;
+   enum machine_mode mode;
+ 
+   mode = TYPE_MODE (vectype);
+ 
++  /* vect_permute_load_chain requires the group size to be a power of two.  */
++  if (exact_log2 (count) == -1)
++    {
++      if (vect_print_dump_info (REPORT_DETAILS))
++	fprintf (vect_dump, "the size of the group of strided accesses"
++		 " is not a power of 2");
++      return false;
++    }
++
+   perm_even_optab = optab_for_tree_code (VEC_EXTRACT_EVEN_EXPR, vectype,
+ 					 optab_default);
+   if (!perm_even_optab)
+@@ -3821,6 +3881,16 @@
+   return true;
+ }
+ 
++/* Return TRUE if vec_load_lanes is available for COUNT vectors of
++   type VECTYPE.  */
++
++bool
++vect_load_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count)
++{
++  return vect_lanes_optab_supported_p ("vec_load_lanes",
++				       vec_load_lanes_optab,
++				       vectype, count);
++}
+ 
+ /* Function vect_permute_load_chain.
+ 
+@@ -3898,7 +3968,7 @@
+    3rd vec (E2):  2 6 10 14 18 22 26 30
+    4th vec (E4):  3 7 11 15 19 23 27 31.  */
+ 
+-bool
++static void
+ vect_permute_load_chain (VEC(tree,heap) *dr_chain,
+ 			 unsigned int length,
+ 			 gimple stmt,
+@@ -3911,9 +3981,7 @@
+   int i;
+   unsigned int j;
+ 
+-  /* Check that the operation is supported.  */
+-  if (!vect_strided_load_supported (vectype))
+-    return false;
++  gcc_assert (vect_strided_load_supported (vectype, length));
+ 
+   *result_chain = VEC_copy (tree, heap, dr_chain);
+   for (i = 0; i < exact_log2 (length); i++)
+@@ -3956,7 +4024,6 @@
+ 	}
+       dr_chain = VEC_copy (tree, heap, *result_chain);
+     }
+-  return true;
+ }
+ 
+ 
+@@ -3967,24 +4034,32 @@
+    the scalar statements.
+ */
+ 
+-bool
++void
+ vect_transform_strided_load (gimple stmt, VEC(tree,heap) *dr_chain, int size,
+ 			     gimple_stmt_iterator *gsi)
+ {
+-  stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
+-  gimple first_stmt = DR_GROUP_FIRST_DR (stmt_info);
+-  gimple next_stmt, new_stmt;
+   VEC(tree,heap) *result_chain = NULL;
+-  unsigned int i, gap_count;
+-  tree tmp_data_ref;
+ 
+   /* DR_CHAIN contains input data-refs that are a part of the interleaving.
+      RESULT_CHAIN is the output of vect_permute_load_chain, it contains permuted
+      vectors, that are ready for vector computation.  */
+   result_chain = VEC_alloc (tree, heap, size);
+-  /* Permute.  */
+-  if (!vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain))
+-    return false;
++  vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain);
++  vect_record_strided_load_vectors (stmt, result_chain);
++  VEC_free (tree, heap, result_chain);
++}
++
++/* RESULT_CHAIN contains the output of a group of strided loads that were
++   generated as part of the vectorization of STMT.  Assign the statement
++   for each vector to the associated scalar statement.  */
++
++void
++vect_record_strided_load_vectors (gimple stmt, VEC(tree,heap) *result_chain)
++{
++  gimple first_stmt = DR_GROUP_FIRST_DR (vinfo_for_stmt (stmt));
++  gimple next_stmt, new_stmt;
++  unsigned int i, gap_count;
++  tree tmp_data_ref;
+ 
+   /* Put a permuted data-ref in the VECTORIZED_STMT field.
+      Since we scan the chain starting from it's first node, their order
+@@ -4046,9 +4121,6 @@
+ 	    break;
+         }
+     }
+-
+-  VEC_free (tree, heap, result_chain);
+-  return true;
+ }
+ 
+ /* Function vect_force_dr_alignment_p.
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2010-12-23 16:25:52 +0000
++++ new/gcc/tree-vect-slp.c	2011-05-05 15:43:06 +0000
+@@ -215,7 +215,8 @@
+ 	    vect_model_simple_cost (stmt_info, ncopies_for_cost, dt, slp_node);
+ 	  else
+ 	    /* Store.  */
+-	    vect_model_store_cost (stmt_info, ncopies_for_cost, dt[0], slp_node);
++	    vect_model_store_cost (stmt_info, ncopies_for_cost, false,
++				   dt[0], slp_node);
+ 	}
+ 
+       else
+@@ -579,7 +580,7 @@
+ 
+                   /* Analyze costs (for the first stmt in the group).  */
+                   vect_model_load_cost (vinfo_for_stmt (stmt),
+-                                        ncopies_for_cost, *node);
++                                        ncopies_for_cost, false, *node);
+                 }
+ 
+               /* Store the place of this load in the interleaving chain.  In
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-04-18 07:38:11 +0000
++++ new/gcc/tree-vect-stmts.c	2011-06-02 12:12:00 +0000
+@@ -42,6 +42,82 @@
+ #include "langhooks.h"
+ 
+ 
++/* Return a variable of type ELEM_TYPE[NELEMS].  */
++
++static tree
++create_vector_array (tree elem_type, unsigned HOST_WIDE_INT nelems)
++{
++  return create_tmp_var (build_array_type_nelts (elem_type, nelems),
++			 "vect_array");
++}
++
++/* ARRAY is an array of vectors created by create_vector_array.
++   Return an SSA_NAME for the vector in index N.  The reference
++   is part of the vectorization of STMT and the vector is associated
++   with scalar destination SCALAR_DEST.  */
++
++static tree
++read_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree scalar_dest,
++		   tree array, unsigned HOST_WIDE_INT n)
++{
++  tree vect_type, vect, vect_name, array_ref;
++  gimple new_stmt;
++
++  gcc_assert (TREE_CODE (TREE_TYPE (array)) == ARRAY_TYPE);
++  vect_type = TREE_TYPE (TREE_TYPE (array));
++  vect = vect_create_destination_var (scalar_dest, vect_type);
++  array_ref = build4 (ARRAY_REF, vect_type, array,
++		      build_int_cst (size_type_node, n),
++		      NULL_TREE, NULL_TREE);
++
++  new_stmt = gimple_build_assign (vect, array_ref);
++  vect_name = make_ssa_name (vect, new_stmt);
++  gimple_assign_set_lhs (new_stmt, vect_name);
++  vect_finish_stmt_generation (stmt, new_stmt, gsi);
++  mark_symbols_for_renaming (new_stmt);
++
++  return vect_name;
++}
++
++/* ARRAY is an array of vectors created by create_vector_array.
++   Emit code to store SSA_NAME VECT in index N of the array.
++   The store is part of the vectorization of STMT.  */
++
++static void
++write_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree vect,
++		    tree array, unsigned HOST_WIDE_INT n)
++{
++  tree array_ref;
++  gimple new_stmt;
++
++  array_ref = build4 (ARRAY_REF, TREE_TYPE (vect), array,
++		      build_int_cst (size_type_node, n),
++		      NULL_TREE, NULL_TREE);
++
++  new_stmt = gimple_build_assign (array_ref, vect);
++  vect_finish_stmt_generation (stmt, new_stmt, gsi);
++  mark_symbols_for_renaming (new_stmt);
++}
++
++/* PTR is a pointer to an array of type TYPE.  Return a representation
++   of *PTR.  The memory reference replaces those in FIRST_DR
++   (and its group).  */
++
++static tree
++create_array_ref (tree type, tree ptr, struct data_reference *first_dr)
++{
++  struct ptr_info_def *pi;
++  tree mem_ref, alias_ptr_type;
++
++  alias_ptr_type = reference_alias_ptr_type (DR_REF (first_dr));
++  mem_ref = build2 (MEM_REF, type, ptr, build_int_cst (alias_ptr_type, 0));
++  /* Arrays have the same alignment as their type.  */
++  pi = get_ptr_info (ptr);
++  pi->align = TYPE_ALIGN_UNIT (type);
++  pi->misalign = 0;
++  return mem_ref;
++}
++
+ /* Utility functions used by vect_mark_stmts_to_be_vectorized.  */
+ 
+ /* Function vect_mark_relevant.
+@@ -648,7 +724,8 @@
+ 
+ void
+ vect_model_store_cost (stmt_vec_info stmt_info, int ncopies,
+-		       enum vect_def_type dt, slp_tree slp_node)
++		       bool store_lanes_p, enum vect_def_type dt,
++		       slp_tree slp_node)
+ {
+   int group_size;
+   unsigned int inside_cost = 0, outside_cost = 0;
+@@ -685,9 +762,11 @@
+       first_dr = STMT_VINFO_DATA_REF (stmt_info);
+     }
+ 
+-  /* Is this an access in a group of stores, which provide strided access?
+-     If so, add in the cost of the permutes.  */
+-  if (group_size > 1)
++  /* We assume that the cost of a single store-lanes instruction is
++     equivalent to the cost of GROUP_SIZE separate stores.  If a strided
++     access is instead being provided by a permute-and-store operation,
++     include the cost of the permutes.  */
++  if (!store_lanes_p && group_size > 1)
+     {
+       /* Uses a high and low interleave operation for each needed permute.  */
+       inside_cost = ncopies * exact_log2(group_size) * group_size
+@@ -763,8 +842,8 @@
+    access scheme chosen.  */
+ 
+ void
+-vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, slp_tree slp_node)
+-
++vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, bool load_lanes_p,
++		      slp_tree slp_node)
+ {
+   int group_size;
+   gimple first_stmt;
+@@ -789,9 +868,11 @@
+       first_dr = dr;
+     }
+ 
+-  /* Is this an access in a group of loads providing strided access?
+-     If so, add in the cost of the permutes.  */
+-  if (group_size > 1)
++  /* We assume that the cost of a single load-lanes instruction is
++     equivalent to the cost of GROUP_SIZE separate loads.  If a strided
++     access is instead being provided by a load-and-permute operation,
++     include the cost of the permutes.  */
++  if (!load_lanes_p && group_size > 1)
+     {
+       /* Uses an even and odd extract operations for each needed permute.  */
+       inside_cost = ncopies * exact_log2(group_size) * group_size
+@@ -3329,6 +3410,7 @@
+   stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
+   struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr = NULL;
+   tree vectype = STMT_VINFO_VECTYPE (stmt_info);
++  tree elem_type;
+   loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
+   struct loop *loop = NULL;
+   enum machine_mode vec_mode;
+@@ -3344,6 +3426,7 @@
+   int j;
+   gimple next_stmt, first_stmt = NULL;
+   bool strided_store = false;
++  bool store_lanes_p = false;
+   unsigned int group_size, i;
+   VEC(tree,heap) *dr_chain = NULL, *oprnds = NULL, *result_chain = NULL;
+   bool inv_p;
+@@ -3351,6 +3434,7 @@
+   bool slp = (slp_node != NULL);
+   unsigned int vec_num;
+   bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
++  tree aggr_type;
+ 
+   if (loop_vinfo)
+     loop = LOOP_VINFO_LOOP (loop_vinfo);
+@@ -3404,7 +3488,8 @@
+ 
+   /* The scalar rhs type needs to be trivially convertible to the vector
+      component type.  This should always be the case.  */
+-  if (!useless_type_conversion_p (TREE_TYPE (vectype), TREE_TYPE (op)))
++  elem_type = TREE_TYPE (vectype);
++  if (!useless_type_conversion_p (elem_type, TREE_TYPE (op)))
+     {
+       if (vect_print_dump_info (REPORT_DETAILS))
+         fprintf (vect_dump, "???  operands of different types");
+@@ -3431,9 +3516,14 @@
+     {
+       strided_store = true;
+       first_stmt = DR_GROUP_FIRST_DR (stmt_info);
+-      if (!vect_strided_store_supported (vectype)
+-	  && !PURE_SLP_STMT (stmt_info) && !slp)
+-	return false;
++      if (!slp && !PURE_SLP_STMT (stmt_info))
++	{
++	  group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt));
++	  if (vect_store_lanes_supported (vectype, group_size))
++	    store_lanes_p = true;
++	  else if (!vect_strided_store_supported (vectype, group_size))
++	    return false;
++	}
+ 
+       if (first_stmt == stmt)
+ 	{
+@@ -3459,7 +3549,7 @@
+   if (!vec_stmt) /* transformation not required.  */
+     {
+       STMT_VINFO_TYPE (stmt_info) = store_vec_info_type;
+-      vect_model_store_cost (stmt_info, ncopies, dt, NULL);
++      vect_model_store_cost (stmt_info, ncopies, store_lanes_p, dt, NULL);
+       return true;
+     }
+ 
+@@ -3514,6 +3604,16 @@
+ 
+   alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false);
+   gcc_assert (alignment_support_scheme);
++  /* Targets with store-lane instructions must not require explicit
++     realignment.  */
++  gcc_assert (!store_lanes_p
++	      || alignment_support_scheme == dr_aligned
++	      || alignment_support_scheme == dr_unaligned_supported);
++
++  if (store_lanes_p)
++    aggr_type = build_array_type_nelts (elem_type, vec_num * nunits);
++  else
++    aggr_type = vectype;
+ 
+   /* In case the vectorization factor (VF) is bigger than the number
+      of elements that we can fit in a vectype (nunits), we have to generate
+@@ -3602,9 +3702,9 @@
+ 	  /* We should have catched mismatched types earlier.  */
+ 	  gcc_assert (useless_type_conversion_p (vectype,
+ 						 TREE_TYPE (vec_oprnd)));
+-	  dataref_ptr = vect_create_data_ref_ptr (first_stmt, NULL, NULL_TREE,
+-						  &dummy, &ptr_incr, false,
+-						  &inv_p);
++	  dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, NULL,
++						  NULL_TREE, &dummy,
++						  &ptr_incr, false, &inv_p);
+ 	  gcc_assert (bb_vinfo || !inv_p);
+ 	}
+       else
+@@ -3625,76 +3725,101 @@
+ 	      VEC_replace(tree, dr_chain, i, vec_oprnd);
+ 	      VEC_replace(tree, oprnds, i, vec_oprnd);
+ 	    }
+-	  dataref_ptr =
+-		bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE);
+-	}
+-
+-      if (strided_store)
+-	{
+-	  result_chain = VEC_alloc (tree, heap, group_size);
+-	  /* Permute.  */
+-	  if (!vect_permute_store_chain (dr_chain, group_size, stmt, gsi,
+-					 &result_chain))
+-	    return false;
+-	}
+-
+-      next_stmt = first_stmt;
+-      for (i = 0; i < vec_num; i++)
+-	{
+-	  struct ptr_info_def *pi;
+-
+-	  if (i > 0)
+-	    /* Bump the vector pointer.  */
+-	    dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
+-					   NULL_TREE);
+-
+-	  if (slp)
+-	    vec_oprnd = VEC_index (tree, vec_oprnds, i);
+-	  else if (strided_store)
+-	    /* For strided stores vectorized defs are interleaved in
+-	       vect_permute_store_chain().  */
+-	    vec_oprnd = VEC_index (tree, result_chain, i);
+-
+-	  data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr,
+-			     build_int_cst (reference_alias_ptr_type
+-					    (DR_REF (first_dr)), 0));
+-	  pi = get_ptr_info (dataref_ptr);
+-	  pi->align = TYPE_ALIGN_UNIT (vectype);
+-          if (aligned_access_p (first_dr))
+-	    pi->misalign = 0;
+-          else if (DR_MISALIGNMENT (first_dr) == -1)
+-	    {
+-	      TREE_TYPE (data_ref)
+-		= build_aligned_type (TREE_TYPE (data_ref),
+-				      TYPE_ALIGN (TREE_TYPE (vectype)));
+-	      pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype));
+-	      pi->misalign = 0;
+-	    }
+-	  else
+-	    {
+-	      TREE_TYPE (data_ref)
+-		= build_aligned_type (TREE_TYPE (data_ref),
+-				      TYPE_ALIGN (TREE_TYPE (vectype)));
+-	      pi->misalign = DR_MISALIGNMENT (first_dr);
+-	    }
+-
+-	  /* Arguments are ready.  Create the new vector stmt.  */
+-	  new_stmt = gimple_build_assign (data_ref, vec_oprnd);
++	  dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
++					 TYPE_SIZE_UNIT (aggr_type));
++	}
++
++      if (store_lanes_p)
++	{
++	  tree vec_array;
++
++	  /* Combine all the vectors into an array.  */
++	  vec_array = create_vector_array (vectype, vec_num);
++	  for (i = 0; i < vec_num; i++)
++	    {
++	      vec_oprnd = VEC_index (tree, dr_chain, i);
++	      write_vector_array (stmt, gsi, vec_oprnd, vec_array, i);
++	    }
++
++	  /* Emit:
++	       MEM_REF[...all elements...] = STORE_LANES (VEC_ARRAY).  */
++	  data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr);
++	  new_stmt = gimple_build_call_internal (IFN_STORE_LANES, 1, vec_array);
++	  gimple_call_set_lhs (new_stmt, data_ref);
+ 	  vect_finish_stmt_generation (stmt, new_stmt, gsi);
+ 	  mark_symbols_for_renaming (new_stmt);
+-
+-          if (slp)
+-            continue;
+-
+-          if (j == 0)
+-            STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt =  new_stmt;
++	}
++      else
++	{
++	  new_stmt = NULL;
++	  if (strided_store)
++	    {
++	      result_chain = VEC_alloc (tree, heap, group_size);
++	      /* Permute.  */
++	      vect_permute_store_chain (dr_chain, group_size, stmt, gsi,
++					&result_chain);
++	    }
++
++	  next_stmt = first_stmt;
++	  for (i = 0; i < vec_num; i++)
++	    {
++	      struct ptr_info_def *pi;
++
++	      if (i > 0)
++		/* Bump the vector pointer.  */
++		dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
++					       stmt, NULL_TREE);
++
++	      if (slp)
++		vec_oprnd = VEC_index (tree, vec_oprnds, i);
++	      else if (strided_store)
++		/* For strided stores vectorized defs are interleaved in
++		   vect_permute_store_chain().  */
++		vec_oprnd = VEC_index (tree, result_chain, i);
++
++	      data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr,
++				 build_int_cst (reference_alias_ptr_type
++						(DR_REF (first_dr)), 0));
++	      pi = get_ptr_info (dataref_ptr);
++	      pi->align = TYPE_ALIGN_UNIT (vectype);
++	      if (aligned_access_p (first_dr))
++		pi->misalign = 0;
++	      else if (DR_MISALIGNMENT (first_dr) == -1)
++		{
++		  TREE_TYPE (data_ref)
++		    = build_aligned_type (TREE_TYPE (data_ref),
++					  TYPE_ALIGN (elem_type));
++		  pi->align = TYPE_ALIGN_UNIT (elem_type);
++		  pi->misalign = 0;
++		}
++	      else
++		{
++		  TREE_TYPE (data_ref)
++		    = build_aligned_type (TREE_TYPE (data_ref),
++					  TYPE_ALIGN (elem_type));
++		  pi->misalign = DR_MISALIGNMENT (first_dr);
++		}
++
++	      /* Arguments are ready.  Create the new vector stmt.  */
++	      new_stmt = gimple_build_assign (data_ref, vec_oprnd);
++	      vect_finish_stmt_generation (stmt, new_stmt, gsi);
++	      mark_symbols_for_renaming (new_stmt);
++
++	      if (slp)
++		continue;
++
++	      next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt));
++	      if (!next_stmt)
++		break;
++	    }
++	}
++      if (!slp)
++	{
++	  if (j == 0)
++	    STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
+ 	  else
+ 	    STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
+-
+ 	  prev_stmt_info = vinfo_for_stmt (new_stmt);
+-	  next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt));
+-	  if (!next_stmt)
+-	    break;
+ 	}
+     }
+ 
+@@ -3805,6 +3930,7 @@
+   bool nested_in_vect_loop = false;
+   struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr;
+   tree vectype = STMT_VINFO_VECTYPE (stmt_info);
++  tree elem_type;
+   tree new_temp;
+   enum machine_mode mode;
+   gimple new_stmt = NULL;
+@@ -3821,6 +3947,7 @@
+   gimple phi = NULL;
+   VEC(tree,heap) *dr_chain = NULL;
+   bool strided_load = false;
++  bool load_lanes_p = false;
+   gimple first_stmt;
+   tree scalar_type;
+   bool inv_p;
+@@ -3833,6 +3960,7 @@
+   enum tree_code code;
+   bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
+   int vf;
++  tree aggr_type;
+ 
+   if (loop_vinfo)
+     {
+@@ -3909,7 +4037,8 @@
+ 
+   /* The vector component type needs to be trivially convertible to the
+      scalar lhs.  This should always be the case.  */
+-  if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), TREE_TYPE (vectype)))
++  elem_type = TREE_TYPE (vectype);
++  if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), elem_type))
+     {
+       if (vect_print_dump_info (REPORT_DETAILS))
+         fprintf (vect_dump, "???  operands of different types");
+@@ -3923,10 +4052,15 @@
+       /* FORNOW */
+       gcc_assert (! nested_in_vect_loop);
+ 
+-      /* Check if interleaving is supported.  */
+-      if (!vect_strided_load_supported (vectype)
+-	  && !PURE_SLP_STMT (stmt_info) && !slp)
+-	return false;
++      first_stmt = DR_GROUP_FIRST_DR (stmt_info);
++      if (!slp && !PURE_SLP_STMT (stmt_info))
++	{
++	  group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt));
++	  if (vect_load_lanes_supported (vectype, group_size))
++	    load_lanes_p = true;
++	  else if (!vect_strided_load_supported (vectype, group_size))
++	    return false;
++	}
+     }
+ 
+   if (negative)
+@@ -3951,12 +4085,12 @@
+   if (!vec_stmt) /* transformation not required.  */
+     {
+       STMT_VINFO_TYPE (stmt_info) = load_vec_info_type;
+-      vect_model_load_cost (stmt_info, ncopies, NULL);
++      vect_model_load_cost (stmt_info, ncopies, load_lanes_p, NULL);
+       return true;
+     }
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+-    fprintf (vect_dump, "transform load.");
++    fprintf (vect_dump, "transform load. ncopies = %d", ncopies);
+ 
+   /** Transform.  **/
+ 
+@@ -3982,8 +4116,6 @@
+     	}
+       else
+ 	vec_num = group_size;
+-
+-      dr_chain = VEC_alloc (tree, heap, vec_num);
+     }
+   else
+     {
+@@ -3994,6 +4126,11 @@
+ 
+   alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false);
+   gcc_assert (alignment_support_scheme);
++  /* Targets with load-lane instructions must not require explicit
++     realignment.  */
++  gcc_assert (!load_lanes_p
++	      || alignment_support_scheme == dr_aligned
++	      || alignment_support_scheme == dr_unaligned_supported);
+ 
+   /* In case the vectorization factor (VF) is bigger than the number
+      of elements that we can fit in a vectype (nunits), we have to generate
+@@ -4125,208 +4262,252 @@
+   if (negative)
+     offset = size_int (-TYPE_VECTOR_SUBPARTS (vectype) + 1);
+ 
++  if (load_lanes_p)
++    aggr_type = build_array_type_nelts (elem_type, vec_num * nunits);
++  else
++    aggr_type = vectype;
++
+   prev_stmt_info = NULL;
+   for (j = 0; j < ncopies; j++)
+     {
+       /* 1. Create the vector pointer update chain.  */
+       if (j == 0)
+-        dataref_ptr = vect_create_data_ref_ptr (first_stmt,
++        dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type,
+ 					        at_loop, offset,
+ 						&dummy, &ptr_incr, false,
+ 						&inv_p);
+       else
+-        dataref_ptr =
+-		bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE);
+-
+-      for (i = 0; i < vec_num; i++)
++        dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
++				       TYPE_SIZE_UNIT (aggr_type));
++
++      if (strided_load || slp_perm)
++	dr_chain = VEC_alloc (tree, heap, vec_num);
++
++      if (load_lanes_p)
+ 	{
+-	  if (i > 0)
+-	    dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
+-					   NULL_TREE);
+-
+-	  /* 2. Create the vector-load in the loop.  */
+-	  switch (alignment_support_scheme)
+-	    {
+-	    case dr_aligned:
+-	    case dr_unaligned_supported:
+-	      {
+-		struct ptr_info_def *pi;
+-		data_ref
+-		  = build2 (MEM_REF, vectype, dataref_ptr,
+-			    build_int_cst (reference_alias_ptr_type
+-					   (DR_REF (first_dr)), 0));
+-		pi = get_ptr_info (dataref_ptr);
+-		pi->align = TYPE_ALIGN_UNIT (vectype);
+-		if (alignment_support_scheme == dr_aligned)
+-		  {
+-		    gcc_assert (aligned_access_p (first_dr));
+-		    pi->misalign = 0;
+-		  }
+-		else if (DR_MISALIGNMENT (first_dr) == -1)
+-		  {
+-		    TREE_TYPE (data_ref)
+-		      = build_aligned_type (TREE_TYPE (data_ref),
+-					    TYPE_ALIGN (TREE_TYPE (vectype)));
+-		    pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype));
+-		    pi->misalign = 0;
+-		  }
+-		else
+-		  {
+-		    TREE_TYPE (data_ref)
+-		      = build_aligned_type (TREE_TYPE (data_ref),
+-					    TYPE_ALIGN (TREE_TYPE (vectype)));
+-		    pi->misalign = DR_MISALIGNMENT (first_dr);
+-		  }
+-		break;
+-	      }
+-	    case dr_explicit_realign:
+-	      {
+-		tree ptr, bump;
+-		tree vs_minus_1 = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
+-
+-		if (compute_in_loop)
+-		  msq = vect_setup_realignment (first_stmt, gsi,
+-						&realignment_token,
+-						dr_explicit_realign,
+-						dataref_ptr, NULL);
+-
+-		new_stmt = gimple_build_assign_with_ops
+-			     (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
+-			      build_int_cst
+-			        (TREE_TYPE (dataref_ptr),
+-				 -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
+-		ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
+-		gimple_assign_set_lhs (new_stmt, ptr);
+-		vect_finish_stmt_generation (stmt, new_stmt, gsi);
+-		data_ref
+-		  = build2 (MEM_REF, vectype, ptr,
+-			    build_int_cst (reference_alias_ptr_type
+-					     (DR_REF (first_dr)), 0));
+-		vec_dest = vect_create_destination_var (scalar_dest, vectype);
+-		new_stmt = gimple_build_assign (vec_dest, data_ref);
+-		new_temp = make_ssa_name (vec_dest, new_stmt);
+-		gimple_assign_set_lhs (new_stmt, new_temp);
+-		gimple_set_vdef (new_stmt, gimple_vdef (stmt));
+-		gimple_set_vuse (new_stmt, gimple_vuse (stmt));
+-		vect_finish_stmt_generation (stmt, new_stmt, gsi);
+-		msq = new_temp;
+-
+-		bump = size_binop (MULT_EXPR, vs_minus_1,
+-				   TYPE_SIZE_UNIT (scalar_type));
+-		ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump);
+-		new_stmt = gimple_build_assign_with_ops
+-			     (BIT_AND_EXPR, NULL_TREE, ptr,
+-			      build_int_cst
+-			        (TREE_TYPE (ptr),
+-				 -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
+-		ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
+-		gimple_assign_set_lhs (new_stmt, ptr);
+-		vect_finish_stmt_generation (stmt, new_stmt, gsi);
+-		data_ref
+-		  = build2 (MEM_REF, vectype, ptr,
+-			    build_int_cst (reference_alias_ptr_type
+-					     (DR_REF (first_dr)), 0));
+-	        break;
+-	      }
+-	    case dr_explicit_realign_optimized:
+-	      new_stmt = gimple_build_assign_with_ops
+-			   (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
+-			    build_int_cst
+-			      (TREE_TYPE (dataref_ptr),
+-			       -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
+-	      new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
+-	      gimple_assign_set_lhs (new_stmt, new_temp);
+-	      vect_finish_stmt_generation (stmt, new_stmt, gsi);
+-	      data_ref
+-		= build2 (MEM_REF, vectype, new_temp,
+-			  build_int_cst (reference_alias_ptr_type
+-					   (DR_REF (first_dr)), 0));
+-	      break;
+-	    default:
+-	      gcc_unreachable ();
+-	    }
+-	  vec_dest = vect_create_destination_var (scalar_dest, vectype);
+-	  new_stmt = gimple_build_assign (vec_dest, data_ref);
+-	  new_temp = make_ssa_name (vec_dest, new_stmt);
+-	  gimple_assign_set_lhs (new_stmt, new_temp);
++	  tree vec_array;
++
++	  vec_array = create_vector_array (vectype, vec_num);
++
++	  /* Emit:
++	       VEC_ARRAY = LOAD_LANES (MEM_REF[...all elements...]).  */
++	  data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr);
++	  new_stmt = gimple_build_call_internal (IFN_LOAD_LANES, 1, data_ref);
++	  gimple_call_set_lhs (new_stmt, vec_array);
+ 	  vect_finish_stmt_generation (stmt, new_stmt, gsi);
+ 	  mark_symbols_for_renaming (new_stmt);
+ 
+-	  /* 3. Handle explicit realignment if necessary/supported.  Create in
+-		loop: vec_dest = realign_load (msq, lsq, realignment_token)  */
+-	  if (alignment_support_scheme == dr_explicit_realign_optimized
+-	      || alignment_support_scheme == dr_explicit_realign)
+-	    {
+-	      tree tmp;
+-
+-	      lsq = gimple_assign_lhs (new_stmt);
+-	      if (!realignment_token)
+-		realignment_token = dataref_ptr;
++	  /* Extract each vector into an SSA_NAME.  */
++	  for (i = 0; i < vec_num; i++)
++	    {
++	      new_temp = read_vector_array (stmt, gsi, scalar_dest,
++					    vec_array, i);
++	      VEC_quick_push (tree, dr_chain, new_temp);
++	    }
++
++	  /* Record the mapping between SSA_NAMEs and statements.  */
++	  vect_record_strided_load_vectors (stmt, dr_chain);
++	}
++      else
++	{
++	  for (i = 0; i < vec_num; i++)
++	    {
++	      if (i > 0)
++		dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
++					       stmt, NULL_TREE);
++
++	      /* 2. Create the vector-load in the loop.  */
++	      switch (alignment_support_scheme)
++		{
++		case dr_aligned:
++		case dr_unaligned_supported:
++		  {
++		    struct ptr_info_def *pi;
++		    data_ref
++		      = build2 (MEM_REF, vectype, dataref_ptr,
++				build_int_cst (reference_alias_ptr_type
++					       (DR_REF (first_dr)), 0));
++		    pi = get_ptr_info (dataref_ptr);
++		    pi->align = TYPE_ALIGN_UNIT (vectype);
++		    if (alignment_support_scheme == dr_aligned)
++		      {
++			gcc_assert (aligned_access_p (first_dr));
++			pi->misalign = 0;
++		      }
++		    else if (DR_MISALIGNMENT (first_dr) == -1)
++		      {
++			TREE_TYPE (data_ref)
++			  = build_aligned_type (TREE_TYPE (data_ref),
++						TYPE_ALIGN (elem_type));
++			pi->align = TYPE_ALIGN_UNIT (elem_type);
++			pi->misalign = 0;
++		      }
++		    else
++		      {
++			TREE_TYPE (data_ref)
++			  = build_aligned_type (TREE_TYPE (data_ref),
++						TYPE_ALIGN (elem_type));
++			pi->misalign = DR_MISALIGNMENT (first_dr);
++		      }
++		    break;
++		  }
++		case dr_explicit_realign:
++		  {
++		    tree ptr, bump;
++		    tree vs_minus_1
++		      = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
++
++		    if (compute_in_loop)
++		      msq = vect_setup_realignment (first_stmt, gsi,
++						    &realignment_token,
++						    dr_explicit_realign,
++						    dataref_ptr, NULL);
++
++		    new_stmt = gimple_build_assign_with_ops
++				 (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
++				  build_int_cst
++				    (TREE_TYPE (dataref_ptr),
++				     -(HOST_WIDE_INT)
++				     TYPE_ALIGN_UNIT (vectype)));
++		    ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
++		    gimple_assign_set_lhs (new_stmt, ptr);
++		    vect_finish_stmt_generation (stmt, new_stmt, gsi);
++		    data_ref
++		      = build2 (MEM_REF, vectype, ptr,
++				build_int_cst (reference_alias_ptr_type
++						 (DR_REF (first_dr)), 0));
++		    vec_dest = vect_create_destination_var (scalar_dest,
++							    vectype);
++		    new_stmt = gimple_build_assign (vec_dest, data_ref);
++		    new_temp = make_ssa_name (vec_dest, new_stmt);
++		    gimple_assign_set_lhs (new_stmt, new_temp);
++		    gimple_set_vdef (new_stmt, gimple_vdef (stmt));
++		    gimple_set_vuse (new_stmt, gimple_vuse (stmt));
++		    vect_finish_stmt_generation (stmt, new_stmt, gsi);
++		    msq = new_temp;
++
++		    bump = size_binop (MULT_EXPR, vs_minus_1,
++				       TYPE_SIZE_UNIT (scalar_type));
++		    ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump);
++		    new_stmt = gimple_build_assign_with_ops
++				 (BIT_AND_EXPR, NULL_TREE, ptr,
++				  build_int_cst
++				    (TREE_TYPE (ptr),
++				     -(HOST_WIDE_INT)
++				     TYPE_ALIGN_UNIT (vectype)));
++		    ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
++		    gimple_assign_set_lhs (new_stmt, ptr);
++		    vect_finish_stmt_generation (stmt, new_stmt, gsi);
++		    data_ref
++		      = build2 (MEM_REF, vectype, ptr,
++				build_int_cst (reference_alias_ptr_type
++						 (DR_REF (first_dr)), 0));
++		    break;
++		  }
++		case dr_explicit_realign_optimized:
++		  new_stmt = gimple_build_assign_with_ops
++			       (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
++				build_int_cst
++				  (TREE_TYPE (dataref_ptr),
++				   -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
++		  new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr),
++					    new_stmt);
++		  gimple_assign_set_lhs (new_stmt, new_temp);
++		  vect_finish_stmt_generation (stmt, new_stmt, gsi);
++		  data_ref
++		    = build2 (MEM_REF, vectype, new_temp,
++			      build_int_cst (reference_alias_ptr_type
++					       (DR_REF (first_dr)), 0));
++		  break;
++		default:
++		  gcc_unreachable ();
++		}
+ 	      vec_dest = vect_create_destination_var (scalar_dest, vectype);
+-	      tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq,
+-			    realignment_token);
+-	      new_stmt = gimple_build_assign (vec_dest, tmp);
++	      new_stmt = gimple_build_assign (vec_dest, data_ref);
+ 	      new_temp = make_ssa_name (vec_dest, new_stmt);
+ 	      gimple_assign_set_lhs (new_stmt, new_temp);
+ 	      vect_finish_stmt_generation (stmt, new_stmt, gsi);
+-
+-	      if (alignment_support_scheme == dr_explicit_realign_optimized)
+-		{
+-		  gcc_assert (phi);
+-		  if (i == vec_num - 1 && j == ncopies - 1)
+-		    add_phi_arg (phi, lsq, loop_latch_edge (containing_loop),
+-				 UNKNOWN_LOCATION);
+-		  msq = lsq;
+-		}
+-	    }
+-
+-	  /* 4. Handle invariant-load.  */
+-	  if (inv_p && !bb_vinfo)
+-	    {
+-	      gcc_assert (!strided_load);
+-	      gcc_assert (nested_in_vect_loop_p (loop, stmt));
+-	      if (j == 0)
+-		{
+-		  int k;
+-		  tree t = NULL_TREE;
+-		  tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type);
+-
+-		  /* CHECKME: bitpos depends on endianess?  */
+-		  bitpos = bitsize_zero_node;
+-		  vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp,
+-				    bitsize, bitpos);
+-		  vec_dest =
+-			vect_create_destination_var (scalar_dest, NULL_TREE);
+-		  new_stmt = gimple_build_assign (vec_dest, vec_inv);
+-                  new_temp = make_ssa_name (vec_dest, new_stmt);
++	      mark_symbols_for_renaming (new_stmt);
++
++	      /* 3. Handle explicit realignment if necessary/supported.
++		    Create in loop:
++		       vec_dest = realign_load (msq, lsq, realignment_token)  */
++	      if (alignment_support_scheme == dr_explicit_realign_optimized
++		  || alignment_support_scheme == dr_explicit_realign)
++		{
++		  tree tmp;
++
++		  lsq = gimple_assign_lhs (new_stmt);
++		  if (!realignment_token)
++		    realignment_token = dataref_ptr;
++		  vec_dest = vect_create_destination_var (scalar_dest, vectype);
++		  tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq,
++				realignment_token);
++		  new_stmt = gimple_build_assign (vec_dest, tmp);
++		  new_temp = make_ssa_name (vec_dest, new_stmt);
+ 		  gimple_assign_set_lhs (new_stmt, new_temp);
+ 		  vect_finish_stmt_generation (stmt, new_stmt, gsi);
+ 
+-		  for (k = nunits - 1; k >= 0; --k)
+-		    t = tree_cons (NULL_TREE, new_temp, t);
+-		  /* FIXME: use build_constructor directly.  */
+-		  vec_inv = build_constructor_from_list (vectype, t);
+-		  new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi);
++		  if (alignment_support_scheme == dr_explicit_realign_optimized)
++		    {
++		      gcc_assert (phi);
++		      if (i == vec_num - 1 && j == ncopies - 1)
++			add_phi_arg (phi, lsq,
++				     loop_latch_edge (containing_loop),
++				     UNKNOWN_LOCATION);
++		      msq = lsq;
++		    }
++		}
++
++	      /* 4. Handle invariant-load.  */
++	      if (inv_p && !bb_vinfo)
++		{
++		  gcc_assert (!strided_load);
++		  gcc_assert (nested_in_vect_loop_p (loop, stmt));
++		  if (j == 0)
++		    {
++		      int k;
++		      tree t = NULL_TREE;
++		      tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type);
++
++		      /* CHECKME: bitpos depends on endianess?  */
++		      bitpos = bitsize_zero_node;
++		      vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp,
++					bitsize, bitpos);
++		      vec_dest = vect_create_destination_var (scalar_dest,
++							      NULL_TREE);
++		      new_stmt = gimple_build_assign (vec_dest, vec_inv);
++		      new_temp = make_ssa_name (vec_dest, new_stmt);
++		      gimple_assign_set_lhs (new_stmt, new_temp);
++		      vect_finish_stmt_generation (stmt, new_stmt, gsi);
++
++		      for (k = nunits - 1; k >= 0; --k)
++			t = tree_cons (NULL_TREE, new_temp, t);
++		      /* FIXME: use build_constructor directly.  */
++		      vec_inv = build_constructor_from_list (vectype, t);
++		      new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi);
++		      new_stmt = SSA_NAME_DEF_STMT (new_temp);
++		    }
++		  else
++		    gcc_unreachable (); /* FORNOW. */
++		}
++
++	      if (negative)
++		{
++		  new_temp = reverse_vec_elements (new_temp, stmt, gsi);
+ 		  new_stmt = SSA_NAME_DEF_STMT (new_temp);
+ 		}
+-	      else
+-		gcc_unreachable (); /* FORNOW. */
+-	    }
+-
+-	  if (negative)
+-	    {
+-	      new_temp = reverse_vec_elements (new_temp, stmt, gsi);
+-	      new_stmt = SSA_NAME_DEF_STMT (new_temp);
+-	    }
+-
+-	  /* Collect vector loads and later create their permutation in
+-	     vect_transform_strided_load ().  */
+-          if (strided_load || slp_perm)
+-            VEC_quick_push (tree, dr_chain, new_temp);
+-
+-         /* Store vector loads in the corresponding SLP_NODE.  */
+-	  if (slp && !slp_perm)
+-	    VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), new_stmt);
++
++	      /* Collect vector loads and later create their permutation in
++		 vect_transform_strided_load ().  */
++	      if (strided_load || slp_perm)
++		VEC_quick_push (tree, dr_chain, new_temp);
++
++	      /* Store vector loads in the corresponding SLP_NODE.  */
++	      if (slp && !slp_perm)
++		VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node),
++				new_stmt);
++	    }
+ 	}
+ 
+       if (slp && !slp_perm)
+@@ -4345,12 +4526,9 @@
+         {
+           if (strided_load)
+   	    {
+-	      if (!vect_transform_strided_load (stmt, dr_chain, group_size, gsi))
+-	        return false;
+-
++	      if (!load_lanes_p)
++		vect_transform_strided_load (stmt, dr_chain, group_size, gsi);
+ 	      *vec_stmt = STMT_VINFO_VEC_STMT (stmt_info);
+-              VEC_free (tree, heap, dr_chain);
+-	      dr_chain = VEC_alloc (tree, heap, group_size);
+ 	    }
+           else
+ 	    {
+@@ -4361,11 +4539,10 @@
+ 	      prev_stmt_info = vinfo_for_stmt (new_stmt);
+ 	    }
+         }
++      if (dr_chain)
++	VEC_free (tree, heap, dr_chain);
+     }
+ 
+-  if (dr_chain)
+-    VEC_free (tree, heap, dr_chain);
+-
+   return true;
+ }
+ 
+@@ -4769,27 +4946,6 @@
+        return false;
+     }
+ 
+-  if (!PURE_SLP_STMT (stmt_info))
+-    {
+-      /* Groups of strided accesses whose size is not a power of 2 are not
+-         vectorizable yet using loop-vectorization.  Therefore, if this stmt
+-	 feeds non-SLP-able stmts (i.e., this stmt has to be both SLPed and
+-	 loop-based vectorized), the loop cannot be vectorized.  */
+-      if (STMT_VINFO_STRIDED_ACCESS (stmt_info)
+-          && exact_log2 (DR_GROUP_SIZE (vinfo_for_stmt (
+-                                        DR_GROUP_FIRST_DR (stmt_info)))) == -1)
+-        {
+-          if (vect_print_dump_info (REPORT_DETAILS))
+-            {
+-              fprintf (vect_dump, "not vectorized: the size of group "
+-                                  "of strided accesses is not a power of 2");
+-              print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+-            }
+-
+-          return false;
+-        }
+-    }
+-
+   return true;
+ }
+ 
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2010-12-23 16:25:52 +0000
++++ new/gcc/tree-vectorizer.h	2011-05-05 15:43:06 +0000
+@@ -788,9 +788,9 @@
+ extern tree vectorizable_function (gimple, tree, tree);
+ extern void vect_model_simple_cost (stmt_vec_info, int, enum vect_def_type *,
+                                     slp_tree);
+-extern void vect_model_store_cost (stmt_vec_info, int, enum vect_def_type,
+-                                   slp_tree);
+-extern void vect_model_load_cost (stmt_vec_info, int, slp_tree);
++extern void vect_model_store_cost (stmt_vec_info, int, bool,
++				   enum vect_def_type, slp_tree);
++extern void vect_model_load_cost (stmt_vec_info, int, bool, slp_tree);
+ extern void vect_finish_stmt_generation (gimple, gimple,
+                                          gimple_stmt_iterator *);
+ extern bool vect_mark_stmts_to_be_vectorized (loop_vec_info);
+@@ -823,21 +823,22 @@
+ extern bool vect_analyze_data_ref_accesses (loop_vec_info, bb_vec_info);
+ extern bool vect_prune_runtime_alias_test_list (loop_vec_info);
+ extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *);
+-extern tree vect_create_data_ref_ptr (gimple, struct loop *, tree, tree *,
+-                                      gimple *, bool, bool *);
++extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree,
++				      tree *, gimple *, bool, bool *);
+ extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree);
+ extern tree vect_create_destination_var (tree, tree);
+-extern bool vect_strided_store_supported (tree);
+-extern bool vect_strided_load_supported (tree);
+-extern bool vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple,
++extern bool vect_strided_store_supported (tree, unsigned HOST_WIDE_INT);
++extern bool vect_store_lanes_supported (tree, unsigned HOST_WIDE_INT);
++extern bool vect_strided_load_supported (tree, unsigned HOST_WIDE_INT);
++extern bool vect_load_lanes_supported (tree, unsigned HOST_WIDE_INT);
++extern void vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple,
+                                     gimple_stmt_iterator *, VEC(tree,heap) **);
+ extern tree vect_setup_realignment (gimple, gimple_stmt_iterator *, tree *,
+                                     enum dr_alignment_support, tree,
+                                     struct loop **);
+-extern bool vect_permute_load_chain (VEC(tree,heap) *,unsigned int, gimple,
+-                                    gimple_stmt_iterator *, VEC(tree,heap) **);
+-extern bool vect_transform_strided_load (gimple, VEC(tree,heap) *, int,
++extern void vect_transform_strided_load (gimple, VEC(tree,heap) *, int,
+                                          gimple_stmt_iterator *);
++extern void vect_record_strided_load_vectors (gimple, VEC(tree,heap) *);
+ extern int vect_get_place_in_interleaving_chain (gimple, gimple);
+ extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *);
+ extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *,
+
+=== modified file 'gcc/tree.c'
+--- old/gcc/tree.c	2011-05-18 13:29:24 +0000
++++ new/gcc/tree.c	2011-06-02 12:12:00 +0000
+@@ -7321,6 +7321,15 @@
+   return build_array_type_1 (elt_type, index_type, false);
+ }
+ 
++/* Return a representation of ELT_TYPE[NELTS], using indices of type
++   sizetype.  */
++
++tree
++build_array_type_nelts (tree elt_type, unsigned HOST_WIDE_INT nelts)
++{
++  return build_array_type (elt_type, build_index_type (size_int (nelts - 1)));
++}
++
+ /* Recursively examines the array elements of TYPE, until a non-array
+    element type is found.  */
+ 
+
+=== modified file 'gcc/tree.h'
+--- old/gcc/tree.h	2011-03-11 22:38:58 +0000
++++ new/gcc/tree.h	2011-05-05 15:43:06 +0000
+@@ -4192,6 +4192,7 @@
+ extern tree build_index_type (tree);
+ extern tree build_array_type (tree, tree);
+ extern tree build_nonshared_array_type (tree, tree);
++extern tree build_array_type_nelts (tree, unsigned HOST_WIDE_INT);
+ extern tree build_function_type (tree, tree);
+ extern tree build_function_type_list (tree, ...);
+ extern tree build_function_type_skip_args (tree, bitmap);
+
+=== modified file 'gcc/value-prof.c'
+--- old/gcc/value-prof.c	2011-01-29 03:54:56 +0000
++++ new/gcc/value-prof.c	2011-05-05 15:42:22 +0000
+@@ -1242,6 +1242,9 @@
+   if (TREE_CODE (callee) == FUNCTION_DECL)
+     return false;
+ 
++  if (gimple_call_internal_p (stmt))
++    return false;
++
+   histogram = gimple_histogram_value_of_type (cfun, stmt, HIST_TYPE_INDIR_CALL);
+   if (!histogram)
+     return false;
+@@ -1630,6 +1633,7 @@
+   tree callee;
+ 
+   if (gimple_code (stmt) != GIMPLE_CALL
++      || gimple_call_internal_p (stmt)
+       || gimple_call_fndecl (stmt) != NULL_TREE)
+     return;
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch
new file mode 100644
index 0000000000..b64991836b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch
@@ -0,0 +1,329 @@
+2011-06-07  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2011-06-07  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.md (*maddhidi4tb, *maddhidi4tt): New define_insns.
+	(*maddhisi4tb, *maddhisi4tt): New define_insns.
+
+	gcc/testsuite/
+	* gcc.target/arm/smlatb-1.c: New file.
+	* gcc.target/arm/smlatt-1.c: New file.
+	* gcc.target/arm/smlaltb-1.c: New file.
+	* gcc.target/arm/smlaltt-1.c: New file.
+
+2011-06-07  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2011-06-07  Bernd Schmidt  <bernds@codesourcery.com>
+		    Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* simplify-rtx.c (simplify_unary_operation_1): Canonicalize widening
+	multiplies.
+	* doc/md.texi (Canonicalization of Instructions): Document widening
+	multiply canonicalization.
+
+	gcc/testsuite/
+	* gcc.target/arm/mla-2.c: New test.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-05-13 13:42:39 +0000
++++ new/gcc/config/arm/arm.md	2011-06-02 15:58:33 +0000
+@@ -1809,6 +1809,36 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
++;; Note: there is no maddhisi4ibt because this one is canonical form
++(define_insn "*maddhisi4tb"
++  [(set (match_operand:SI 0 "s_register_operand" "=r")
++	(plus:SI (mult:SI (ashiftrt:SI
++			   (match_operand:SI 1 "s_register_operand" "r")
++			   (const_int 16))
++			  (sign_extend:SI
++			   (match_operand:HI 2 "s_register_operand" "r")))
++		 (match_operand:SI 3 "s_register_operand" "r")))]
++  "TARGET_DSP_MULTIPLY"
++  "smlatb%?\\t%0, %1, %2, %3"
++  [(set_attr "insn" "smlaxy")
++   (set_attr "predicable" "yes")]
++)
++
++(define_insn "*maddhisi4tt"
++  [(set (match_operand:SI 0 "s_register_operand" "=r")
++	(plus:SI (mult:SI (ashiftrt:SI
++			   (match_operand:SI 1 "s_register_operand" "r")
++			   (const_int 16))
++			  (ashiftrt:SI
++			   (match_operand:SI 2 "s_register_operand" "r")
++			   (const_int 16)))
++		 (match_operand:SI 3 "s_register_operand" "r")))]
++  "TARGET_DSP_MULTIPLY"
++  "smlatt%?\\t%0, %1, %2, %3"
++  [(set_attr "insn" "smlaxy")
++   (set_attr "predicable" "yes")]
++)
++
+ (define_insn "*maddhidi4"
+   [(set (match_operand:DI 0 "s_register_operand" "=r")
+ 	(plus:DI
+@@ -1822,6 +1852,39 @@
+   [(set_attr "insn" "smlalxy")
+    (set_attr "predicable" "yes")])
+ 
++;; Note: there is no maddhidi4ibt because this one is canonical form
++(define_insn "*maddhidi4tb"
++  [(set (match_operand:DI 0 "s_register_operand" "=r")
++	(plus:DI
++	  (mult:DI (sign_extend:DI
++		    (ashiftrt:SI
++		     (match_operand:SI 1 "s_register_operand" "r")
++		     (const_int 16)))
++		   (sign_extend:DI
++		    (match_operand:HI 2 "s_register_operand" "r")))
++	  (match_operand:DI 3 "s_register_operand" "0")))]
++  "TARGET_DSP_MULTIPLY"
++  "smlaltb%?\\t%Q0, %R0, %1, %2"
++  [(set_attr "insn" "smlalxy")
++   (set_attr "predicable" "yes")])
++
++(define_insn "*maddhidi4tt"
++  [(set (match_operand:DI 0 "s_register_operand" "=r")
++	(plus:DI
++	  (mult:DI (sign_extend:DI
++		    (ashiftrt:SI
++		     (match_operand:SI 1 "s_register_operand" "r")
++		     (const_int 16)))
++		   (sign_extend:DI
++		    (ashiftrt:SI
++		     (match_operand:SI 2 "s_register_operand" "r")
++		     (const_int 16))))
++	  (match_operand:DI 3 "s_register_operand" "0")))]
++  "TARGET_DSP_MULTIPLY"
++  "smlaltt%?\\t%Q0, %R0, %1, %2"
++  [(set_attr "insn" "smlalxy")
++   (set_attr "predicable" "yes")])
++
+ (define_expand "mulsf3"
+   [(set (match_operand:SF          0 "s_register_operand" "")
+ 	(mult:SF (match_operand:SF 1 "s_register_operand" "")
+
+=== modified file 'gcc/doc/md.texi'
+--- old/gcc/doc/md.texi	2011-05-05 15:43:06 +0000
++++ new/gcc/doc/md.texi	2011-06-07 11:18:20 +0000
+@@ -5929,6 +5929,23 @@
+ will be written using @code{zero_extract} rather than the equivalent
+ @code{and} or @code{sign_extract} operations.
+ 
++@cindex @code{mult}, canonicalization of
++@item
++@code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
++(sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
++(sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
++for @code{zero_extend}.
++
++@item
++@code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
++@var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
++to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
++@var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
++patterns using @code{zero_extend} and @code{lshiftrt}.  If the second
++operand of @code{mult} is also a shift, then that is extended also.
++This transformation is only applied when it can be proven that the
++original operation had sufficient precision to prevent overflow.
++
+ @end itemize
+ 
+ Further canonicalization rules are defined in the function
+
+=== modified file 'gcc/simplify-rtx.c'
+--- old/gcc/simplify-rtx.c	2011-05-27 14:31:18 +0000
++++ new/gcc/simplify-rtx.c	2011-06-02 12:32:16 +0000
+@@ -1000,6 +1000,48 @@
+ 	  && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
+ 	return XEXP (op, 0);
+ 
++      /* Extending a widening multiplication should be canonicalized to
++	 a wider widening multiplication.  */
++      if (GET_CODE (op) == MULT)
++	{
++	  rtx lhs = XEXP (op, 0);
++	  rtx rhs = XEXP (op, 1);
++	  enum rtx_code lcode = GET_CODE (lhs);
++	  enum rtx_code rcode = GET_CODE (rhs);
++
++	  /* Widening multiplies usually extend both operands, but sometimes
++	     they use a shift to extract a portion of a register.  */
++	  if ((lcode == SIGN_EXTEND
++	       || (lcode == ASHIFTRT && CONST_INT_P (XEXP (lhs, 1))))
++	      && (rcode == SIGN_EXTEND
++		  || (rcode == ASHIFTRT && CONST_INT_P (XEXP (rhs, 1)))))
++	    {
++	      enum machine_mode lmode = GET_MODE (lhs);
++	      enum machine_mode rmode = GET_MODE (rhs);
++	      int bits;
++
++	      if (lcode == ASHIFTRT)
++		/* Number of bits not shifted off the end.  */
++		bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1));
++	      else /* lcode == SIGN_EXTEND */
++		/* Size of inner mode.  */
++		bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0)));
++
++	      if (rcode == ASHIFTRT)
++		bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1));
++	      else /* rcode == SIGN_EXTEND */
++		bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0)));
++
++	      /* We can only widen multiplies if the result is mathematiclly
++		 equivalent.  I.e. if overflow was impossible.  */
++	      if (bits <= GET_MODE_PRECISION (GET_MODE (op)))
++		return simplify_gen_binary
++			 (MULT, mode,
++			  simplify_gen_unary (SIGN_EXTEND, mode, lhs, lmode),
++			  simplify_gen_unary (SIGN_EXTEND, mode, rhs, rmode));
++	    }
++	}
++
+       /* Check for a sign extension of a subreg of a promoted
+ 	 variable, where the promotion is sign-extended, and the
+ 	 target mode is the same as the variable's promotion.  */
+@@ -1071,6 +1113,48 @@
+ 	  && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
+ 	return rtl_hooks.gen_lowpart_no_emit (mode, op);
+ 
++      /* Extending a widening multiplication should be canonicalized to
++	 a wider widening multiplication.  */
++      if (GET_CODE (op) == MULT)
++	{
++	  rtx lhs = XEXP (op, 0);
++	  rtx rhs = XEXP (op, 1);
++	  enum rtx_code lcode = GET_CODE (lhs);
++	  enum rtx_code rcode = GET_CODE (rhs);
++
++	  /* Widening multiplies usually extend both operands, but sometimes
++	     they use a shift to extract a portion of a register.  */
++	  if ((lcode == ZERO_EXTEND
++	       || (lcode == LSHIFTRT && CONST_INT_P (XEXP (lhs, 1))))
++	      && (rcode == ZERO_EXTEND
++		  || (rcode == LSHIFTRT && CONST_INT_P (XEXP (rhs, 1)))))
++	    {
++	      enum machine_mode lmode = GET_MODE (lhs);
++	      enum machine_mode rmode = GET_MODE (rhs);
++	      int bits;
++
++	      if (lcode == LSHIFTRT)
++		/* Number of bits not shifted off the end.  */
++		bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1));
++	      else /* lcode == ZERO_EXTEND */
++		/* Size of inner mode.  */
++		bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0)));
++
++	      if (rcode == LSHIFTRT)
++		bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1));
++	      else /* rcode == ZERO_EXTEND */
++		bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0)));
++
++	      /* We can only widen multiplies if the result is mathematiclly
++		 equivalent.  I.e. if overflow was impossible.  */
++	      if (bits <= GET_MODE_PRECISION (GET_MODE (op)))
++		return simplify_gen_binary
++			 (MULT, mode,
++			  simplify_gen_unary (ZERO_EXTEND, mode, lhs, lmode),
++			  simplify_gen_unary (ZERO_EXTEND, mode, rhs, rmode));
++	    }
++	}
++
+       /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>).  */
+       if (GET_CODE (op) == ZERO_EXTEND)
+ 	return simplify_gen_unary (ZERO_EXTEND, mode, XEXP (op, 0),
+
+=== added file 'gcc/testsuite/gcc.target/arm/mla-2.c'
+--- old/gcc/testsuite/gcc.target/arm/mla-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/mla-2.c	2011-06-02 12:32:16 +0000
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long foolong (long long x, short *a, short *b)
++{
++    return x + *a * *b;
++}
++
++/* { dg-final { scan-assembler "smlalbb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/smlaltb-1.c'
+--- old/gcc/testsuite/gcc.target/arm/smlaltb-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/smlaltb-1.c	2011-06-02 15:58:33 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long int
++foo (long long x, int in)
++{
++  short a = in & 0xffff;
++  short b = (in & 0xffff0000) >> 16;
++
++  return x + b * a;
++}
++
++/* { dg-final { scan-assembler "smlaltb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/smlaltt-1.c'
+--- old/gcc/testsuite/gcc.target/arm/smlaltt-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/smlaltt-1.c	2011-06-02 15:58:33 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long int
++foo (long long x, int in1, int in2)
++{
++  short a = (in1 & 0xffff0000) >> 16;
++  short b = (in2 & 0xffff0000) >> 16;
++
++  return x + b * a;
++}
++
++/* { dg-final { scan-assembler "smlaltt" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/smlatb-1.c'
+--- old/gcc/testsuite/gcc.target/arm/smlatb-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/smlatb-1.c	2011-06-02 15:58:33 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++int
++foo (int x, int in)
++{
++  short a = in & 0xffff;
++  short b = (in & 0xffff0000) >> 16;
++
++  return x + b * a;
++}
++
++/* { dg-final { scan-assembler "smlatb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/smlatt-1.c'
+--- old/gcc/testsuite/gcc.target/arm/smlatt-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/smlatt-1.c	2011-06-02 15:58:33 +0000
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++int
++foo (int x, int in1, int in2)
++{
++  short a = (in1 & 0xffff0000) >> 16;
++  short b = (in2 & 0xffff0000) >> 16;
++
++  return x + b * a;
++}
++
++/* { dg-final { scan-assembler "smlatt" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch
new file mode 100644
index 0000000000..b8f587c9f4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch
@@ -0,0 +1,120 @@
+2011-06-10  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline:
+	gcc/
+        2011-06-02  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+	* config/arm/neon.md (orndi3_neon): Actually split it.
+
+
+2011-06-10  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+        Backport from mainline.
+	gcc/
+        2011-05-26  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	* config/arm/neon.md ("orn<mode>3_neon"): Canonicalize not.
+	("orndi3_neon"): Likewise.
+	("bic<mode>3_neon"): Likewise.
+
+	gcc/testsuite
+	2011-05-26  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	* gcc.target/arm/neon-vorn-vbic.c: New test.
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2011-06-02 12:12:00 +0000
++++ new/gcc/config/arm/neon.md	2011-06-04 00:04:47 +0000
+@@ -783,30 +783,57 @@
+ 
+ (define_insn "orn<mode>3_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+-	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+-		 (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
++	(ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
++		 (match_operand:VDQ 1 "s_register_operand" "w")))]
+   "TARGET_NEON"
+   "vorn\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+   [(set_attr "neon_type" "neon_int_1")]
+ )
+ 
+-(define_insn "orndi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
+-	(ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0")
+-	         (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))]
++;; TODO: investigate whether we should disable 
++;; this and bicdi3_neon for the A8 in line with the other
++;; changes above. 
++(define_insn_and_split "orndi3_neon"
++  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
++	(ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r"))
++		(match_operand:DI 1 "s_register_operand" "w,r,r,0")))]
+   "TARGET_NEON"
+   "@
+    vorn\t%P0, %P1, %P2
+    #
++   #
+    #"
+-  [(set_attr "neon_type" "neon_int_1,*,*")
+-   (set_attr "length" "*,8,8")]
++  "reload_completed && 
++   (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))"
++  [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
++   (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
++  "
++  {
++    if (TARGET_THUMB2)
++      {
++        operands[3] = gen_highpart (SImode, operands[0]);
++        operands[0] = gen_lowpart (SImode, operands[0]);
++        operands[4] = gen_highpart (SImode, operands[2]);
++        operands[2] = gen_lowpart (SImode, operands[2]);
++        operands[5] = gen_highpart (SImode, operands[1]);
++        operands[1] = gen_lowpart (SImode, operands[1]);
++      }
++    else
++      {
++        emit_insn (gen_one_cmpldi2 (operands[0], operands[2]));
++        emit_insn (gen_iordi3 (operands[0], operands[1], operands[0]));
++        DONE;
++      }
++  }"
++  [(set_attr "neon_type" "neon_int_1,*,*,*")
++   (set_attr "length" "*,16,8,8")
++   (set_attr "arch" "any,a,t2,t2")]
+ )
+ 
+ (define_insn "bic<mode>3_neon"
+   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
+-	(and:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
+-		  (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
++	(and:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
++		 (match_operand:VDQ 1 "s_register_operand" "w")))]
+   "TARGET_NEON"
+   "vbic\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+   [(set_attr "neon_type" "neon_int_1")]
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c	2011-06-03 23:50:02 +0000
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize" } */
++/* { dg-add-options arm_neon } */
++
++void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
++{
++  int i;
++  for (i = 0; i < 9; i++)
++    c[i] = b[i] | (~a[i]);
++}
++void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
++{
++  int i;
++  for (i = 0; i < 9; i++)
++    c[i] = b[i] & (~a[i]);
++}
++
++/* { dg-final { scan-assembler "vorn\\t" } } */
++/* { dg-final { scan-assembler "vbic\\t" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch
new file mode 100644
index 0000000000..c515767946
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch
@@ -0,0 +1,545 @@
+2011-06-20  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+	2011-06-03  Julian Brown  <julian@codesourcery.com>
+
+	* config/arm/arm-cores.def (strongarm, strongarm110, strongarm1100)
+	(strongarm1110): Use strongarm tuning.
+	* config/arm/arm-protos.h (tune_params): Add max_insns_skipped
+	field.
+	* config/arm/arm.c (arm_strongarm_tune): New.
+	(arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune)
+	(arm_v6t2_tune, arm_cortex_tune, arm_cortex_a5_tune)
+	(arm_cortex_a9_tune, arm_fa726te_tune): Add max_insns_skipped field
+	setting, using previous defaults or 1 for Cortex-A5.
+	(arm_option_override): Set max_insns_skipped from current tuning.
+ 
+2011-06-14  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+	2011-06-02  Julian Brown  <julian@codesourcery.com>
+
+	* config/arm/arm-cores.def (cortex-a5): Use cortex_a5 tuning.
+	* config/arm/arm.c (arm_cortex_a5_branch_cost): New.
+	(arm_cortex_a5_tune): New.
+
+	2011-06-02  Julian Brown  <julian@codesourcery.com>
+
+	* config/arm/arm-protos.h (tune_params): Add branch_cost hook.
+	* config/arm/arm.c (arm_default_branch_cost): New.
+	(arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune)
+	(arm_v6t2_tune, arm_cortex_tune, arm_cortex_a9_tune)
+	(arm_fa726_tune): Set branch_cost field using
+	arm_default_branch_cost.
+	* config/arm/arm.h (BRANCH_COST): Use branch_cost hook from
+	current_tune structure.
+	* dojump.c (tm_p.h): Include file.
+
+        2011-06-02  Julian Brown  <julian@codesourcery.com>
+
+	* config/arm/arm-cores.def (arm1156t2-s, arm1156t2f-s): Use v6t2
+	tuning.
+	(cortex-a5, cortex-a8, cortex-a15, cortex-r4, cortex-r4f, cortex-m4)
+	(cortex-m3, cortex-m1, cortex-m0): Use cortex tuning.
+	* config/arm/arm-protos.h (tune_params): Add prefer_constant_pool
+	field.
+	* config/arm/arm.c (arm_slowmul_tune, arm_fastmul_tune)
+	(arm_xscale_tune, arm_9e_tune, arm_cortex_a9_tune)
+	(arm_fa726te_tune): Add prefer_constant_pool setting.
+	(arm_v6t2_tune, arm_cortex_tune): New.
+	* config/arm/arm.h (TARGET_USE_MOVT): Make dependent on
+	prefer_constant_pool setting.
+
+2011-06-14  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline
+	2011-06-01  Paul Brook  <paul@cpodesourcery.com>
+
+	* config/arm/arm-cores.def: Add cortex-r5.  Add DIV flags to
+	Cortex-A15.
+	* config/arm/arm-tune.md: Regenerate.
+	* config/arm/arm.c (FL_DIV): Rename...
+	(FL_THUMB_DIV): ... to this.
+	(FL_ARM_DIV): Define.
+	(FL_FOR_ARCH7R, FL_FOR_ARCH7M): Use FL_THUMB_DIV.
+	(arm_arch_hwdiv): Remove.
+	(arm_arch_thumb_hwdiv, arm_arch_arm_hwdiv): New variables.
+	(arm_issue_rate): Add cortexr5.
+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set
+	__ARM_ARCH_EXT_IDIV__.
+	(TARGET_IDIV): Define.
+	(arm_arch_hwdiv): Remove.
+	(arm_arch_arm_hwdiv, arm_arch_thumb_hwdiv): New prototypes.
+	* config/arm/arm.md (tune_cortexr4): Add cortexr5.
+	(divsi3, udivsi3): New patterns.
+	* config/arm/thumb2.md (divsi3, udivsi3): Remove.
+	* doc/invoke.texi: Document ARM -mcpu=cortex-r5
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2011-01-03 20:52:22 +0000
++++ new/gcc/config/arm/arm-cores.def	2011-06-14 16:00:30 +0000
+@@ -70,10 +70,10 @@
+ /* V4 Architecture Processors */
+ ARM_CORE("arm8",          arm8,		4,	             FL_MODE26 | FL_LDSCHED, fastmul)
+ ARM_CORE("arm810",        arm810,	4,	             FL_MODE26 | FL_LDSCHED, fastmul)
+-ARM_CORE("strongarm",     strongarm,	4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
+-ARM_CORE("strongarm110",  strongarm110,	4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
+-ARM_CORE("strongarm1100", strongarm1100, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
+-ARM_CORE("strongarm1110", strongarm1110, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
++ARM_CORE("strongarm",     strongarm,	4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
++ARM_CORE("strongarm110",  strongarm110,	4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
++ARM_CORE("strongarm1100", strongarm1100, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
++ARM_CORE("strongarm1110", strongarm1110, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
+ ARM_CORE("fa526",         fa526,        4,                               FL_LDSCHED, fastmul)
+ ARM_CORE("fa626",         fa626,        4,                               FL_LDSCHED, fastmul)
+ 
+@@ -122,15 +122,16 @@
+ ARM_CORE("arm1176jzf-s",  arm1176jzfs,	6ZK,				 FL_LDSCHED | FL_VFPV2, 9e)
+ ARM_CORE("mpcorenovfp",	  mpcorenovfp,	6K,				 FL_LDSCHED, 9e)
+ ARM_CORE("mpcore",	  mpcore,	6K,				 FL_LDSCHED | FL_VFPV2, 9e)
+-ARM_CORE("arm1156t2-s",	  arm1156t2s,	6T2,				 FL_LDSCHED, 9e)
+-ARM_CORE("arm1156t2f-s",  arm1156t2fs,  6T2,				 FL_LDSCHED | FL_VFPV2, 9e)
+-ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, 9e)
++ARM_CORE("arm1156t2-s",	  arm1156t2s,	6T2,				 FL_LDSCHED, v6t2)
++ARM_CORE("arm1156t2f-s",  arm1156t2fs,  6T2,				 FL_LDSCHED | FL_VFPV2, v6t2)
++ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
++ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
+-ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-m4",	  cortexm4,	7EM,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, 9e)
+-ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, 9e)
++ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
++ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, cortex)
++ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, cortex)
++ARM_CORE("cortex-r5",	  cortexr5,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
++ARM_CORE("cortex-m4",	  cortexm4,	7EM,				 FL_LDSCHED, cortex)
++ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCHED, cortex)
++ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, cortex)
++ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, cortex)
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-05-03 15:17:25 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-06-14 16:00:30 +0000
+@@ -219,9 +219,14 @@
+   bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
+   bool (*sched_adjust_cost) (rtx, rtx, rtx, int *);
+   int constant_limit;
++  /* Maximum number of instructions to conditionalise in
++     arm_final_prescan_insn.  */
++  int max_insns_skipped;
+   int num_prefetch_slots;
+   int l1_cache_size;
+   int l1_cache_line_size;
++  bool prefer_constant_pool;
++  int (*branch_cost) (bool, bool);
+ };
+ 
+ extern const struct tune_params *current_tune;
+
+=== modified file 'gcc/config/arm/arm-tune.md'
+--- old/gcc/config/arm/arm-tune.md	2010-12-20 17:48:51 +0000
++++ new/gcc/config/arm/arm-tune.md	2011-06-14 14:37:30 +0000
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from arm-cores.def
+ (define_attr "tune"
+-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
++	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-05-11 14:49:48 +0000
++++ new/gcc/config/arm/arm.c	2011-06-14 16:00:30 +0000
+@@ -255,6 +255,8 @@
+ static void arm_conditional_register_usage (void);
+ static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
+ static unsigned int arm_autovectorize_vector_sizes (void);
++static int arm_default_branch_cost (bool, bool);
++static int arm_cortex_a5_branch_cost (bool, bool);
+ 
+ 
+ /* Table of machine attributes.  */
+@@ -672,12 +674,13 @@
+ #define FL_THUMB2     (1 << 16)	      /* Thumb-2.  */
+ #define FL_NOTM	      (1 << 17)	      /* Instructions not present in the 'M'
+ 					 profile.  */
+-#define FL_DIV	      (1 << 18)	      /* Hardware divide.  */
++#define FL_THUMB_DIV  (1 << 18)	      /* Hardware divide (Thumb mode).  */
+ #define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */
+ #define FL_NEON       (1 << 20)       /* Neon instructions.  */
+ #define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
+ 					 architecture.  */
+ #define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
++#define FL_ARM_DIV    (1 << 23)	      /* Hardware divide (ARM mode).  */
+ 
+ #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+ 
+@@ -704,8 +707,8 @@
+ #define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
+ #define FL_FOR_ARCH7	((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
+ #define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+-#define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_DIV)
+-#define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_DIV)
++#define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_THUMB_DIV)
++#define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_THUMB_DIV)
+ #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
+ 
+ /* The bits in this mask specify which
+@@ -791,7 +794,8 @@
+ int arm_arch_thumb2;
+ 
+ /* Nonzero if chip supports integer division instruction.  */
+-int arm_arch_hwdiv;
++int arm_arch_arm_hwdiv;
++int arm_arch_thumb_hwdiv;
+ 
+ /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
+    we must report the mode of the memory reference from
+@@ -864,48 +868,117 @@
+ {
+   arm_slowmul_rtx_costs,
+   NULL,
+-  3,
+-  ARM_PREFETCH_NOT_BENEFICIAL
++  3,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  true,						/* Prefer constant pool.  */
++  arm_default_branch_cost
+ };
+ 
+ const struct tune_params arm_fastmul_tune =
+ {
+   arm_fastmul_rtx_costs,
+   NULL,
+-  1,
+-  ARM_PREFETCH_NOT_BENEFICIAL
++  1,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  true,						/* Prefer constant pool.  */
++  arm_default_branch_cost
++};
++
++/* StrongARM has early execution of branches, so a sequence that is worth
++   skipping is shorter.  Set max_insns_skipped to a lower value.  */
++
++const struct tune_params arm_strongarm_tune =
++{
++  arm_fastmul_rtx_costs,
++  NULL,
++  1,						/* Constant limit.  */
++  3,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  true,						/* Prefer constant pool.  */
++  arm_default_branch_cost
+ };
+ 
+ const struct tune_params arm_xscale_tune =
+ {
+   arm_xscale_rtx_costs,
+   xscale_sched_adjust_cost,
+-  2,
+-  ARM_PREFETCH_NOT_BENEFICIAL
++  2,						/* Constant limit.  */
++  3,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  true,						/* Prefer constant pool.  */
++  arm_default_branch_cost
+ };
+ 
+ const struct tune_params arm_9e_tune =
+ {
+   arm_9e_rtx_costs,
+   NULL,
+-  1,
+-  ARM_PREFETCH_NOT_BENEFICIAL
++  1,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  true,						/* Prefer constant pool.  */
++  arm_default_branch_cost
++};
++
++const struct tune_params arm_v6t2_tune =
++{
++  arm_9e_rtx_costs,
++  NULL,
++  1,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  false,					/* Prefer constant pool.  */
++  arm_default_branch_cost
++};
++
++/* Generic Cortex tuning.  Use more specific tunings if appropriate.  */
++const struct tune_params arm_cortex_tune =
++{
++  arm_9e_rtx_costs,
++  NULL,
++  1,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  false,					/* Prefer constant pool.  */
++  arm_default_branch_cost
++};
++
++/* Branches can be dual-issued on Cortex-A5, so conditional execution is
++   less appealing.  Set max_insns_skipped to a low value.  */
++
++const struct tune_params arm_cortex_a5_tune =
++{
++  arm_9e_rtx_costs,
++  NULL,
++  1,						/* Constant limit.  */
++  1,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  false,					/* Prefer constant pool.  */
++  arm_cortex_a5_branch_cost
+ };
+ 
+ const struct tune_params arm_cortex_a9_tune =
+ {
+   arm_9e_rtx_costs,
+   cortex_a9_sched_adjust_cost,
+-  1,
+-  ARM_PREFETCH_BENEFICIAL(4,32,32)
++  1,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_BENEFICIAL(4,32,32),
++  false,					/* Prefer constant pool.  */
++  arm_default_branch_cost
+ };
+ 
+ const struct tune_params arm_fa726te_tune =
+ {
+   arm_9e_rtx_costs,
+   fa726te_sched_adjust_cost,
+-  1,
+-  ARM_PREFETCH_NOT_BENEFICIAL
++  1,						/* Constant limit.  */
++  5,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  true,						/* Prefer constant pool.  */
++  arm_default_branch_cost
+ };
+ 
+ 
+@@ -1711,7 +1784,8 @@
+   arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
+   arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
+   arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
+-  arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
++  arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
++  arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
+   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
+ 
+   /* If we are not using the default (ARM mode) section anchor offset
+@@ -1991,12 +2065,7 @@
+       max_insns_skipped = 6;
+     }
+   else
+-    {
+-      /* StrongARM has early execution of branches, so a sequence
+-         that is worth skipping is shorter.  */
+-      if (arm_tune_strongarm)
+-        max_insns_skipped = 3;
+-    }
++    max_insns_skipped = current_tune->max_insns_skipped;
+ 
+   /* Hot/Cold partitioning is not currently supported, since we can't
+      handle literal pool placement in that case.  */
+@@ -8211,6 +8280,21 @@
+   return cost;
+ }
+ 
++static int
++arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED)
++{
++  if (TARGET_32BIT)
++    return (TARGET_THUMB2 && !speed_p) ? 1 : 4;
++  else
++    return (optimize > 0) ? 2 : 0;
++}
++
++static int
++arm_cortex_a5_branch_cost (bool speed_p, bool predictable_p)
++{
++  return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
++}
++
+ static int fp_consts_inited = 0;
+ 
+ /* Only zero is valid for VFP.  Other values are also valid for FPA.  */
+@@ -23123,6 +23207,7 @@
+     {
+     case cortexr4:
+     case cortexr4f:
++    case cortexr5:
+     case cortexa5:
+     case cortexa8:
+     case cortexa9:
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-06-02 12:12:00 +0000
++++ new/gcc/config/arm/arm.h	2011-06-14 14:53:07 +0000
+@@ -101,6 +101,8 @@
+ 	      builtin_define ("__ARM_PCS");		\
+ 	    builtin_define ("__ARM_EABI__");		\
+ 	  }						\
++	if (TARGET_IDIV)				\
++	  builtin_define ("__ARM_ARCH_EXT_IDIV__");	\
+     } while (0)
+ 
+ /* The various ARM cores.  */
+@@ -282,7 +284,8 @@
+   (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
+ 
+ /* Should MOVW/MOVT be used in preference to a constant pool.  */
+-#define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
++#define TARGET_USE_MOVT \
++  (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
+ 
+ /* We could use unified syntax for arm mode, but for now we just use it
+    for Thumb-2.  */
+@@ -303,6 +306,10 @@
+ /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}.  */
+ #define TARGET_HAVE_LDREXBHD	((arm_arch6k && TARGET_ARM) || arm_arch7)
+ 
++/* Nonzero if integer division instructions supported.  */
++#define TARGET_IDIV		((TARGET_ARM && arm_arch_arm_hwdiv) \
++				 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
++
+ /* True iff the full BPABI is being used.  If TARGET_BPABI is true,
+    then TARGET_AAPCS_BASED must be true -- but the converse does not
+    hold.  TARGET_BPABI implies the use of the BPABI runtime library,
+@@ -487,8 +494,11 @@
+ /* Nonzero if chip supports Thumb 2.  */
+ extern int arm_arch_thumb2;
+ 
+-/* Nonzero if chip supports integer division instruction.  */
+-extern int arm_arch_hwdiv;
++/* Nonzero if chip supports integer division instruction in ARM mode.  */
++extern int arm_arch_arm_hwdiv;
++
++/* Nonzero if chip supports integer division instruction in Thumb mode.  */
++extern int arm_arch_thumb_hwdiv;
+ 
+ #ifndef TARGET_DEFAULT
+ #define TARGET_DEFAULT  (MASK_APCS_FRAME)
+@@ -2018,8 +2028,8 @@
+ /* Try to generate sequences that don't involve branches, we can then use
+    conditional instructions */
+ #define BRANCH_COST(speed_p, predictable_p) \
+-  (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
+-		: (optimize > 0 ? 2 : 0))
++  (current_tune->branch_cost (speed_p, predictable_p))
++
+ 
+ /* Position Independent Code.  */
+ /* We decide which register to use based on the compilation options and
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-06-02 15:58:33 +0000
++++ new/gcc/config/arm/arm.md	2011-06-14 14:37:30 +0000
+@@ -490,7 +490,7 @@
+ 
+ (define_attr "tune_cortexr4" "yes,no"
+   (const (if_then_else
+-	  (eq_attr "tune" "cortexr4,cortexr4f")
++	  (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")
+ 	  (const_string "yes")
+ 	  (const_string "no"))))
+ 
+@@ -3738,6 +3738,28 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
++
++;; Division instructions
++(define_insn "divsi3"
++  [(set (match_operand:SI	  0 "s_register_operand" "=r")
++	(div:SI (match_operand:SI 1 "s_register_operand"  "r")
++		(match_operand:SI 2 "s_register_operand"  "r")))]
++  "TARGET_IDIV"
++  "sdiv%?\t%0, %1, %2"
++  [(set_attr "predicable" "yes")
++   (set_attr "insn" "sdiv")]
++)
++
++(define_insn "udivsi3"
++  [(set (match_operand:SI	   0 "s_register_operand" "=r")
++	(udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
++		 (match_operand:SI 2 "s_register_operand"  "r")))]
++  "TARGET_IDIV"
++  "udiv%?\t%0, %1, %2"
++  [(set_attr "predicable" "yes")
++   (set_attr "insn" "udiv")]
++)
++
+ 
+ ;; Unary arithmetic insns
+ 
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md	2011-05-11 07:15:47 +0000
++++ new/gcc/config/arm/thumb2.md	2011-06-14 14:37:30 +0000
+@@ -779,26 +779,6 @@
+    (set_attr "length" "2")]
+ )
+ 
+-(define_insn "divsi3"
+-  [(set (match_operand:SI	  0 "s_register_operand" "=r")
+-	(div:SI (match_operand:SI 1 "s_register_operand"  "r")
+-		(match_operand:SI 2 "s_register_operand"  "r")))]
+-  "TARGET_THUMB2 && arm_arch_hwdiv"
+-  "sdiv%?\t%0, %1, %2"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "insn" "sdiv")]
+-)
+-
+-(define_insn "udivsi3"
+-  [(set (match_operand:SI	   0 "s_register_operand" "=r")
+-	(udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
+-		 (match_operand:SI 2 "s_register_operand"  "r")))]
+-  "TARGET_THUMB2 && arm_arch_hwdiv"
+-  "udiv%?\t%0, %1, %2"
+-  [(set_attr "predicable" "yes")
+-   (set_attr "insn" "udiv")]
+-)
+-
+ (define_insn "*thumb2_subsi_short"
+   [(set (match_operand:SI 0 "low_register_operand" "=l")
+ 	(minus:SI (match_operand:SI 1 "low_register_operand" "l")
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2011-05-11 07:15:47 +0000
++++ new/gcc/doc/invoke.texi	2011-06-14 14:37:30 +0000
+@@ -10208,7 +10208,8 @@
+ @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
+ @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
+ @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
+-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3},
++@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
++@samp{cortex-m4}, @samp{cortex-m3},
+ @samp{cortex-m1},
+ @samp{cortex-m0},
+ @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+
+=== modified file 'gcc/dojump.c'
+--- old/gcc/dojump.c	2010-05-19 19:09:57 +0000
++++ new/gcc/dojump.c	2011-06-14 14:53:07 +0000
+@@ -36,6 +36,7 @@
+ #include "ggc.h"
+ #include "basic-block.h"
+ #include "output.h"
++#include "tm_p.h"
+ 
+ static bool prefer_and_bit_test (enum machine_mode, int);
+ static void do_jump_by_parts_greater (tree, tree, int, rtx, rtx, int);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch
new file mode 100644
index 0000000000..bbf9819ecd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch
@@ -0,0 +1,1355 @@
+2011-06-28  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from FSF:
+
+	2011-06-07  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vectorizer.h (vect_recog_func_ptr): Make last argument to be
+	a pointer.
+	* tree-vect-patterns.c (vect_recog_widen_sum_pattern,
+	vect_recog_widen_mult_pattern, vect_recog_dot_prod_pattern,
+	vect_recog_pow_pattern): Likewise.
+	(vect_pattern_recog_1): Remove declaration.
+	(widened_name_p): Remove declaration.  Add new argument to specify
+	whether to check that both types are either signed or unsigned.
+	(vect_recog_widen_mult_pattern): Update documentation.  Handle
+	unsigned patterns and multiplication by constants.
+	(vect_pattern_recog_1): Update vect_recog_func references.  Use
+	statement information from the statement returned from pattern
+	detection functions.
+	(vect_pattern_recog): Update vect_recog_func reference.
+	* tree-vect-stmts.c (vectorizable_type_promotion): For widening
+	multiplication by a constant use the type of the other operand.
+
+	gcc/testsuite
+	* lib/target-supports.exp
+	(check_effective_target_vect_widen_mult_qi_to_hi):
+	Add NEON as supporting target.
+	(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
+	(check_effective_target_vect_widen_mult_qi_to_hi_pattern): New.
+	(check_effective_target_vect_widen_mult_hi_to_si_pattern): New.
+	* gcc.dg/vect/vect-widen-mult-u8.c: Expect to be vectorized
+	using widening multiplication on targets that support it.
+	* gcc.dg/vect/vect-widen-mult-u16.c: Likewise.
+	* gcc.dg/vect/vect-widen-mult-const-s16.c: New test.
+	* gcc.dg/vect/vect-widen-mult-const-u16.c: New test.
+
+	and
+
+	2011-06-15  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-loop-manip.c (remove_dead_stmts_from_loop): Remove.
+	(slpeel_tree_peel_loop_to_edge): Don't call
+	remove_dead_stmts_from_loop.
+	* tree-vect-loop.c (vect_determine_vectorization_factor): Don't
+	remove irrelevant pattern statements.  For irrelevant statements
+	check if it is the last statement of a detected pattern, use
+	corresponding pattern statement instead.
+	(destroy_loop_vec_info): No need to remove pattern statements,
+	only free stmt_vec_info.
+	(vect_transform_loop): For irrelevant statements check if it is
+	the last statement of a detected pattern, use corresponding
+	pattern statement instead.
+	* tree-vect-patterns.c (vect_pattern_recog_1): Don't insert
+	pattern statements.  Set basic block for the new statement.
+	(vect_pattern_recog): Update documentation.
+	* tree-vect-stmts.c (vect_mark_stmts_to_be_vectorized): Scan
+	operands of pattern statements.
+	(vectorizable_call): Fix printing.  In case of a pattern statement
+	use the lhs of the original statement when creating a dummy
+	statement to replace the original call.
+	(vect_analyze_stmt): For irrelevant statements check if it is
+	the last statement of a detected pattern, use corresponding
+	pattern statement instead.
+	* tree-vect-slp.c (vect_schedule_slp_instance): For pattern
+	statements use gsi of the original statement.
+
+	and
+	2011-06-21  Ira Rosen  <ira.rosen@linaro.org>
+
+	PR tree-optimization/49478
+	gcc/
+
+	* tree-vect-loop.c (vectorizable_reduction): Handle DOT_PROD_EXPR
+	with constant operand.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c	2011-06-19 10:59:13 +0000
+@@ -0,0 +1,60 @@
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++#include <stdlib.h>
++
++#define N 32
++
++__attribute__ ((noinline)) void 
++foo (int *__restrict a,
++     short *__restrict b,
++     int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    a[i] = b[i] * 2333;
++
++  for (i = 0; i < n; i++)
++    if (a[i] != b[i] * 2333)
++      abort ();
++}
++
++__attribute__ ((noinline)) void
++bar (int *__restrict a,
++     short *__restrict b,
++     int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    a[i] = b[i] * (short) 2333;
++
++  for (i = 0; i < n; i++)
++    if (a[i] != b[i] * (short) 2333)
++      abort ();
++}
++
++int main (void)
++{
++  int i;
++  int a[N];
++  short b[N];
++
++  for (i = 0; i < N; i++)
++    {
++      a[i] = 0;
++      b[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (a, b, N);
++  bar (a, b, N);
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_widen_mult_hi_to_si } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c	2011-06-19 10:59:13 +0000
+@@ -0,0 +1,77 @@
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++#include <stdlib.h>
++
++#define N 32
++
++__attribute__ ((noinline)) void 
++foo (unsigned int *__restrict a,
++     unsigned short *__restrict b,
++     int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    a[i] = b[i] * 2333;
++
++  for (i = 0; i < n; i++)
++    if (a[i] != b[i] * 2333)
++      abort ();
++}
++
++__attribute__ ((noinline)) void
++bar (unsigned int *__restrict a,
++     unsigned short *__restrict b,
++     int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    a[i] = (unsigned short) 2333 * b[i];
++
++  for (i = 0; i < n; i++)
++    if (a[i] != b[i] * (unsigned short) 2333)
++      abort ();
++}
++
++__attribute__ ((noinline)) void
++baz (unsigned int *__restrict a,
++     unsigned short *__restrict b,
++     int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    a[i] = b[i] * 233333333;
++
++  for (i = 0; i < n; i++)
++    if (a[i] != b[i] * 233333333)
++      abort ();
++}
++
++
++int main (void)
++{
++  int i;
++  unsigned int a[N];
++  unsigned short b[N];
++
++  for (i = 0; i < N; i++)
++    {
++      a[i] = 0;
++      b[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (a, b, N);
++  bar (a, b, N);
++  baz (a, b, N);
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" { target vect_widen_mult_hi_to_si } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c	2010-05-27 12:23:45 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c	2011-06-19 10:59:13 +0000
+@@ -9,13 +9,11 @@
+ unsigned short Y[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+ unsigned int result[N];
+ 
+-/* short->int widening-mult */
++/* unsigned short->unsigned int widening-mult.  */
+ __attribute__ ((noinline)) int
+ foo1(int len) {
+   int i;
+ 
+-  /* Not vectorized because X[i] and Y[i] are casted to 'int'
+-     so the widening multiplication pattern is not recognized.  */
+   for (i=0; i<len; i++) {
+     result[i] = (unsigned int)(X[i] * Y[i]);
+   }
+@@ -43,8 +41,8 @@
+   return 0;
+ }
+ 
+-/*The induction loop is vectorized  */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_pack_trunc } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_widen_mult_hi_to_si || vect_unpack } } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c	2011-06-19 10:59:13 +0000
+@@ -9,7 +9,7 @@
+ unsigned char Y[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+ unsigned short result[N];
+ 
+-/* char->short widening-mult */
++/* unsigned char-> unsigned short widening-mult.  */
+ __attribute__ ((noinline)) int
+ foo1(int len) {
+   int i;
+@@ -28,8 +28,7 @@
+   for (i=0; i<N; i++) {
+     X[i] = i;
+     Y[i] = 64-i;
+-    if (i%4 == 0)
+-      X[i] = 5;
++    __asm__ volatile ("");
+   }
+ 
+   foo1 (N);
+@@ -43,5 +42,7 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_widen_mult_qi_to_hi || vect_unpack } } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { target vect_widen_mult_qi_to_hi_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_qi_to_hi_pattern } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-06-02 12:12:00 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-06-19 10:59:13 +0000
+@@ -2663,7 +2663,8 @@
+ 	} else {
+ 	    set et_vect_widen_mult_qi_to_hi_saved 0
+ 	}
+-        if { [istarget powerpc*-*-*] } {
++        if { [istarget powerpc*-*-*]
++              || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
+             set et_vect_widen_mult_qi_to_hi_saved 1
+         }
+     }
+@@ -2696,7 +2697,8 @@
+ 	      || [istarget spu-*-*]
+ 	      || [istarget ia64-*-*]
+ 	      || [istarget i?86-*-*]
+-	      || [istarget x86_64-*-*] } {
++	      || [istarget x86_64-*-*]
++              || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
+             set et_vect_widen_mult_hi_to_si_saved 1
+         }
+     }
+@@ -2705,6 +2707,52 @@
+ }
+ 
+ # Return 1 if the target plus current options supports a vector
++# widening multiplication of *char* args into *short* result, 0 otherwise.
++#
++# This won't change for different subtargets so cache the result.
++
++proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
++    global et_vect_widen_mult_qi_to_hi_pattern
++
++    if [info exists et_vect_widen_mult_qi_to_hi_pattern_saved] {
++        verbose "check_effective_target_vect_widen_mult_qi_to_hi_pattern: using cached result" 2
++    } else {
++        set et_vect_widen_mult_qi_to_hi_pattern_saved 0
++        if { [istarget powerpc*-*-*]
++              || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
++            set et_vect_widen_mult_qi_to_hi_pattern_saved 1
++        }
++    }
++    verbose "check_effective_target_vect_widen_mult_qi_to_hi_pattern: returning $et_vect_widen_mult_qi_to_hi_pattern_saved" 2
++    return $et_vect_widen_mult_qi_to_hi_pattern_saved
++}
++
++# Return 1 if the target plus current options supports a vector
++# widening multiplication of *short* args into *int* result, 0 otherwise.
++#
++# This won't change for different subtargets so cache the result.
++
++proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
++    global et_vect_widen_mult_hi_to_si_pattern
++
++    if [info exists et_vect_widen_mult_hi_to_si_pattern_saved] {
++        verbose "check_effective_target_vect_widen_mult_hi_to_si_pattern: using cached result" 2
++    } else {
++        set et_vect_widen_mult_hi_to_si_pattern_saved 0
++        if { [istarget powerpc*-*-*]
++              || [istarget spu-*-*]
++              || [istarget ia64-*-*]
++              || [istarget i?86-*-*]
++              || [istarget x86_64-*-*]
++              || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
++            set et_vect_widen_mult_hi_to_si_pattern_saved 1
++        }
++    }
++    verbose "check_effective_target_vect_widen_mult_hi_to_si_pattern: returning $et_vect_widen_mult_hi_to_si_pattern_saved" 2
++    return $et_vect_widen_mult_hi_to_si_pattern_saved
++}
++
++# Return 1 if the target plus current options supports a vector
+ # dot-product of signed chars, 0 otherwise.
+ #
+ # This won't change for different subtargets so cache the result.
+
+=== modified file 'gcc/tree-vect-loop-manip.c'
+--- old/gcc/tree-vect-loop-manip.c	2011-05-18 13:24:05 +0000
++++ new/gcc/tree-vect-loop-manip.c	2011-06-19 10:59:13 +0000
+@@ -1105,35 +1105,6 @@
+   first_niters = PHI_RESULT (newphi);
+ }
+ 
+-
+-/* Remove dead assignments from loop NEW_LOOP.  */
+-
+-static void
+-remove_dead_stmts_from_loop (struct loop *new_loop)
+-{
+-  basic_block *bbs = get_loop_body (new_loop);
+-  unsigned i;
+-  for (i = 0; i < new_loop->num_nodes; ++i)
+-    {
+-      gimple_stmt_iterator gsi;
+-      for (gsi = gsi_start_bb (bbs[i]); !gsi_end_p (gsi);)
+-	{
+-	  gimple stmt = gsi_stmt (gsi);
+-	  if (is_gimple_assign (stmt)
+-	      && TREE_CODE (gimple_assign_lhs (stmt)) == SSA_NAME
+-	      && has_zero_uses (gimple_assign_lhs (stmt)))
+-	    {
+-	      gsi_remove (&gsi, true);
+-	      release_defs (stmt);
+-	    }
+-	  else
+-	    gsi_next (&gsi);
+-	}
+-    }
+-  free (bbs);
+-}
+-
+-
+ /* Function slpeel_tree_peel_loop_to_edge.
+ 
+    Peel the first (last) iterations of LOOP into a new prolog (epilog) loop
+@@ -1445,13 +1416,6 @@
+   BITMAP_FREE (definitions);
+   delete_update_ssa ();
+ 
+-  /* Remove all pattern statements from the loop copy.  They will confuse
+-     the expander if DCE is disabled.
+-     ???  The pattern recognizer should be split into an analysis and
+-     a transformation phase that is then run only on the loop that is
+-     going to be transformed.  */
+-  remove_dead_stmts_from_loop (new_loop);
+-
+   adjust_vec_debug_stmts ();
+ 
+   return new_loop;
+
+=== modified file 'gcc/tree-vect-loop.c'
+--- old/gcc/tree-vect-loop.c	2011-03-01 13:18:25 +0000
++++ new/gcc/tree-vect-loop.c	2011-06-22 06:21:13 +0000
+@@ -244,7 +244,7 @@
+       for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
+         {
+ 	  tree vf_vectype;
+-	  gimple stmt = gsi_stmt (si);
++	  gimple stmt = gsi_stmt (si), pattern_stmt;
+ 	  stmt_info = vinfo_for_stmt (stmt);
+ 
+ 	  if (vect_print_dump_info (REPORT_DETAILS))
+@@ -259,9 +259,25 @@
+ 	  if (!STMT_VINFO_RELEVANT_P (stmt_info)
+ 	      && !STMT_VINFO_LIVE_P (stmt_info))
+ 	    {
+-	      if (vect_print_dump_info (REPORT_DETAILS))
+-	        fprintf (vect_dump, "skip.");
+-	      continue;
++              if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++                  && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
++                  && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
++                      || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
++                {
++                  stmt = pattern_stmt;
++                  stmt_info = vinfo_for_stmt (pattern_stmt);
++                  if (vect_print_dump_info (REPORT_DETAILS))
++                    {
++                      fprintf (vect_dump, "==> examining pattern statement: ");
++                      print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++                    }
++                }
++             else
++               {
++                 if (vect_print_dump_info (REPORT_DETAILS))
++                   fprintf (vect_dump, "skip.");
++                 continue;
++               }
+ 	    }
+ 
+ 	  if (gimple_get_lhs (stmt) == NULL_TREE)
+@@ -816,25 +832,17 @@
+ 
+           if (stmt_info)
+             {
+-              /* Check if this is a "pattern stmt" (introduced by the
+-                 vectorizer during the pattern recognition pass).  */
+-              bool remove_stmt_p = false;
+-              gimple orig_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
+-              if (orig_stmt)
+-                {
+-                  stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
+-                  if (orig_stmt_info
+-                      && STMT_VINFO_IN_PATTERN_P (orig_stmt_info))
+-                    remove_stmt_p = true;
+-                }
++              /* Check if this statement has a related "pattern stmt"
++                 (introduced by the vectorizer during the pattern recognition
++                 pass).  Free pattern's stmt_vec_info.  */
++              if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++                  && vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info)))
++                free_stmt_vec_info (STMT_VINFO_RELATED_STMT (stmt_info));
+ 
+               /* Free stmt_vec_info.  */
+               free_stmt_vec_info (stmt);
++            }
+ 
+-              /* Remove dead "pattern stmts".  */
+-              if (remove_stmt_p)
+-                gsi_remove (&si, true);
+-            }
+           gsi_next (&si);
+         }
+     }
+@@ -4262,6 +4270,25 @@
+       return false;
+     }
+ 
++  /* In case of widenning multiplication by a constant, we update the type
++     of the constant to be the type of the other operand.  We check that the
++     constant fits the type in the pattern recognition pass.  */
++  if (code == DOT_PROD_EXPR
++      && !types_compatible_p (TREE_TYPE (ops[0]), TREE_TYPE (ops[1])))
++    {
++      if (TREE_CODE (ops[0]) == INTEGER_CST)
++        ops[0] = fold_convert (TREE_TYPE (ops[1]), ops[0]);
++      else if (TREE_CODE (ops[1]) == INTEGER_CST)
++        ops[1] = fold_convert (TREE_TYPE (ops[0]), ops[1]);
++      else
++        {
++          if (vect_print_dump_info (REPORT_DETAILS))
++            fprintf (vect_dump, "invalid types in dot-prod");
++
++          return false;
++        }
++    }
++
+   if (!vec_stmt) /* transformation not required.  */
+     {
+       STMT_VINFO_TYPE (stmt_info) = reduc_vec_info_type;
+@@ -4796,7 +4823,7 @@
+ 
+       for (si = gsi_start_bb (bb); !gsi_end_p (si);)
+ 	{
+-	  gimple stmt = gsi_stmt (si);
++	  gimple stmt = gsi_stmt (si), pattern_stmt;
+ 	  bool is_store;
+ 
+ 	  if (vect_print_dump_info (REPORT_DETAILS))
+@@ -4821,14 +4848,25 @@
+ 
+ 	  if (!STMT_VINFO_RELEVANT_P (stmt_info)
+ 	      && !STMT_VINFO_LIVE_P (stmt_info))
+-	    {
+-	      gsi_next (&si);
+-	      continue;
++            {
++              if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++                  && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
++                  && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
++                      || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
++                {
++                  stmt = pattern_stmt;
++                  stmt_info = vinfo_for_stmt (stmt);
++                }
++              else
++	        {
++   	          gsi_next (&si);
++	          continue;
++                }
+ 	    }
+ 
+ 	  gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
+-	  nunits =
+-	    (unsigned int) TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info));
++	  nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
++                                               STMT_VINFO_VECTYPE (stmt_info));
+ 	  if (!STMT_SLP_TYPE (stmt_info)
+ 	      && nunits != (unsigned int) vectorization_factor
+               && vect_print_dump_info (REPORT_DETAILS))
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2010-12-02 11:47:12 +0000
++++ new/gcc/tree-vect-patterns.c	2011-06-22 12:10:44 +0000
+@@ -38,16 +38,11 @@
+ #include "recog.h"
+ #include "diagnostic-core.h"
+ 
+-/* Function prototypes */
+-static void vect_pattern_recog_1
+-  (gimple (* ) (gimple, tree *, tree *), gimple_stmt_iterator);
+-static bool widened_name_p (tree, gimple, tree *, gimple *);
+-
+ /* Pattern recognition functions  */
+-static gimple vect_recog_widen_sum_pattern (gimple, tree *, tree *);
+-static gimple vect_recog_widen_mult_pattern (gimple, tree *, tree *);
+-static gimple vect_recog_dot_prod_pattern (gimple, tree *, tree *);
+-static gimple vect_recog_pow_pattern (gimple, tree *, tree *);
++static gimple vect_recog_widen_sum_pattern (gimple *, tree *, tree *);
++static gimple vect_recog_widen_mult_pattern (gimple *, tree *, tree *);
++static gimple vect_recog_dot_prod_pattern (gimple *, tree *, tree *);
++static gimple vect_recog_pow_pattern (gimple *, tree *, tree *);
+ static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
+ 	vect_recog_widen_mult_pattern,
+ 	vect_recog_widen_sum_pattern,
+@@ -61,10 +56,12 @@
+    is a result of a type-promotion, such that:
+      DEF_STMT: NAME = NOP (name0)
+    where the type of name0 (HALF_TYPE) is smaller than the type of NAME.
+-*/
++   If CHECK_SIGN is TRUE, check that either both types are signed or both are
++   unsigned.  */
+ 
+ static bool
+-widened_name_p (tree name, gimple use_stmt, tree *half_type, gimple *def_stmt)
++widened_name_p (tree name, gimple use_stmt, tree *half_type, gimple *def_stmt,
++		bool check_sign)
+ {
+   tree dummy;
+   gimple dummy_gimple;
+@@ -98,7 +95,7 @@
+ 
+   *half_type = TREE_TYPE (oprnd0);
+   if (!INTEGRAL_TYPE_P (type) || !INTEGRAL_TYPE_P (*half_type)
+-      || (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*half_type))
++      || ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*half_type)) && check_sign)
+       || (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 2)))
+     return false;
+ 
+@@ -168,12 +165,12 @@
+          inner-loop nested in an outer-loop that us being vectorized).  */
+ 
+ static gimple
+-vect_recog_dot_prod_pattern (gimple last_stmt, tree *type_in, tree *type_out)
++vect_recog_dot_prod_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
+ {
+   gimple stmt;
+   tree oprnd0, oprnd1;
+   tree oprnd00, oprnd01;
+-  stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
++  stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
+   tree type, half_type;
+   gimple pattern_stmt;
+   tree prod_type;
+@@ -181,10 +178,10 @@
+   struct loop *loop = LOOP_VINFO_LOOP (loop_info);
+   tree var, rhs;
+ 
+-  if (!is_gimple_assign (last_stmt))
++  if (!is_gimple_assign (*last_stmt))
+     return NULL;
+ 
+-  type = gimple_expr_type (last_stmt);
++  type = gimple_expr_type (*last_stmt);
+ 
+   /* Look for the following pattern
+           DX = (TYPE1) X;
+@@ -210,7 +207,7 @@
+   /* Starting from LAST_STMT, follow the defs of its uses in search
+      of the above pattern.  */
+ 
+-  if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
++  if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
+     return NULL;
+ 
+   if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
+@@ -231,14 +228,14 @@
+ 
+       if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
+         return NULL;
+-      oprnd0 = gimple_assign_rhs1 (last_stmt);
+-      oprnd1 = gimple_assign_rhs2 (last_stmt);
++      oprnd0 = gimple_assign_rhs1 (*last_stmt);
++      oprnd1 = gimple_assign_rhs2 (*last_stmt);
+       if (!types_compatible_p (TREE_TYPE (oprnd0), type)
+ 	  || !types_compatible_p (TREE_TYPE (oprnd1), type))
+         return NULL;
+-      stmt = last_stmt;
++      stmt = *last_stmt;
+ 
+-      if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt))
++      if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt, true))
+         {
+           stmt = def_stmt;
+           oprnd0 = gimple_assign_rhs1 (stmt);
+@@ -293,10 +290,10 @@
+       if (!types_compatible_p (TREE_TYPE (oprnd0), prod_type)
+           || !types_compatible_p (TREE_TYPE (oprnd1), prod_type))
+         return NULL;
+-      if (!widened_name_p (oprnd0, stmt, &half_type0, &def_stmt))
++      if (!widened_name_p (oprnd0, stmt, &half_type0, &def_stmt, true))
+         return NULL;
+       oprnd00 = gimple_assign_rhs1 (def_stmt);
+-      if (!widened_name_p (oprnd1, stmt, &half_type1, &def_stmt))
++      if (!widened_name_p (oprnd1, stmt, &half_type1, &def_stmt, true))
+         return NULL;
+       oprnd01 = gimple_assign_rhs1 (def_stmt);
+       if (!types_compatible_p (half_type0, half_type1))
+@@ -322,7 +319,7 @@
+ 
+   /* We don't allow changing the order of the computation in the inner-loop
+      when doing outer-loop vectorization.  */
+-  gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
++  gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
+ 
+   return pattern_stmt;
+ }
+@@ -342,24 +339,47 @@
+ 
+    where type 'TYPE' is at least double the size of type 'type'.
+ 
+-   Input:
+-
+-   * LAST_STMT: A stmt from which the pattern search begins. In the example,
+-   when this function is called with S5, the pattern {S3,S4,S5} is be detected.
+-
+-   Output:
+-
+-   * TYPE_IN: The type of the input arguments to the pattern.
+-
+-   * TYPE_OUT: The type of the output  of this pattern.
+-
+-   * Return value: A new stmt that will be used to replace the sequence of
+-   stmts that constitute the pattern. In this case it will be:
+-        WIDEN_MULT <a_t, b_t>
+-*/
++   Also detect unsgigned cases:
++
++     unsigned type a_t, b_t;
++     unsigned TYPE u_prod_T;
++     TYPE a_T, b_T, prod_T;
++
++     S1  a_t = ;
++     S2  b_t = ;
++     S3  a_T = (TYPE) a_t;
++     S4  b_T = (TYPE) b_t;
++     S5  prod_T = a_T * b_T;
++     S6  u_prod_T = (unsigned TYPE) prod_T;
++
++   and multiplication by constants:
++
++     type a_t;
++     TYPE a_T, prod_T;
++
++     S1  a_t = ;
++     S3  a_T = (TYPE) a_t;
++     S5  prod_T = a_T * CONST;
++
++    Input:
++
++    * LAST_STMT: A stmt from which the pattern search begins.  In the example,
++    when this function is called with S5, the pattern {S3,S4,S5,(S6)} is
++    detected.
++
++    Output:
++
++    * TYPE_IN: The type of the input arguments to the pattern.
++
++    * TYPE_OUT: The type of the output of this pattern.
++
++    * Return value: A new stmt that will be used to replace the sequence of
++    stmts that constitute the pattern.  In this case it will be:
++         WIDEN_MULT <a_t, b_t>
++ */
+ 
+ static gimple
+-vect_recog_widen_mult_pattern (gimple last_stmt,
++vect_recog_widen_mult_pattern (gimple *last_stmt,
+ 			       tree *type_in,
+ 			       tree *type_out)
+ {
+@@ -367,39 +387,112 @@
+   tree oprnd0, oprnd1;
+   tree type, half_type0, half_type1;
+   gimple pattern_stmt;
+-  tree vectype, vectype_out;
++  tree vectype, vectype_out = NULL_TREE;
+   tree dummy;
+   tree var;
+   enum tree_code dummy_code;
+   int dummy_int;
+   VEC (tree, heap) *dummy_vec;
++  bool op0_ok, op1_ok;
+ 
+-  if (!is_gimple_assign (last_stmt))
++  if (!is_gimple_assign (*last_stmt))
+     return NULL;
+ 
+-  type = gimple_expr_type (last_stmt);
++  type = gimple_expr_type (*last_stmt);
+ 
+   /* Starting from LAST_STMT, follow the defs of its uses in search
+      of the above pattern.  */
+ 
+-  if (gimple_assign_rhs_code (last_stmt) != MULT_EXPR)
++  if (gimple_assign_rhs_code (*last_stmt) != MULT_EXPR)
+     return NULL;
+ 
+-  oprnd0 = gimple_assign_rhs1 (last_stmt);
+-  oprnd1 = gimple_assign_rhs2 (last_stmt);
++  oprnd0 = gimple_assign_rhs1 (*last_stmt);
++  oprnd1 = gimple_assign_rhs2 (*last_stmt);
+   if (!types_compatible_p (TREE_TYPE (oprnd0), type)
+       || !types_compatible_p (TREE_TYPE (oprnd1), type))
+     return NULL;
+ 
+-  /* Check argument 0 */
+-  if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0))
+-    return NULL;
+-  oprnd0 = gimple_assign_rhs1 (def_stmt0);
+-
+-  /* Check argument 1 */
+-  if (!widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1))
+-    return NULL;
+-  oprnd1 = gimple_assign_rhs1 (def_stmt1);
++  /* Check argument 0.  */
++  op0_ok = widened_name_p (oprnd0, *last_stmt, &half_type0, &def_stmt0, false);
++  /* Check argument 1.  */
++  op1_ok = widened_name_p (oprnd1, *last_stmt, &half_type1, &def_stmt1, false);
++
++  /* In case of multiplication by a constant one of the operands may not match
++     the pattern, but not both.  */
++  if (!op0_ok && !op1_ok)
++     return NULL;
++
++  if (op0_ok && op1_ok)
++    {
++      oprnd0 = gimple_assign_rhs1 (def_stmt0);
++      oprnd1 = gimple_assign_rhs1 (def_stmt1);
++    }
++  else if (!op0_ok)
++    {
++      if (CONSTANT_CLASS_P (oprnd0)
++         && TREE_CODE (half_type1) == INTEGER_TYPE
++         && tree_int_cst_lt (oprnd0, TYPE_MAXVAL (half_type1))
++         && tree_int_cst_lt (TYPE_MINVAL (half_type1), oprnd0))
++        {
++          /* OPRND0 is a constant of HALF_TYPE1.  */
++          half_type0 = half_type1;
++          oprnd1 = gimple_assign_rhs1 (def_stmt1);
++        }
++      else
++        return NULL;
++    }
++  else if (!op1_ok)
++    {
++      if (CONSTANT_CLASS_P (oprnd1)
++          && TREE_CODE (half_type0) == INTEGER_TYPE
++          && tree_int_cst_lt (oprnd1, TYPE_MAXVAL (half_type0))
++          && tree_int_cst_lt (TYPE_MINVAL (half_type0), oprnd1))
++        {
++          /* OPRND1 is a constant of HALF_TYPE0.  */
++          half_type1 = half_type0;
++          oprnd0 = gimple_assign_rhs1 (def_stmt0);
++        }
++      else
++        return NULL;
++    }
++
++  /* Handle unsigned case.  Look for
++     S6  u_prod_T = (unsigned TYPE) prod_T;
++     Use unsigned TYPE as the type for WIDEN_MULT_EXPR.  */
++  if (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (half_type0))
++    {
++      tree lhs = gimple_assign_lhs (*last_stmt), use_lhs;
++      imm_use_iterator imm_iter;
++      use_operand_p use_p;
++      int nuses = 0;
++      gimple use_stmt = NULL;
++      tree use_type;
++
++      if (TYPE_UNSIGNED (type) == TYPE_UNSIGNED (half_type1))
++        return NULL;
++
++      FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
++        {
++	  if (is_gimple_debug (USE_STMT (use_p)))
++	    continue;
++          use_stmt = USE_STMT (use_p);
++          nuses++;
++        }
++
++      if (nuses != 1 || !is_gimple_assign (use_stmt)
++          || gimple_assign_rhs_code (use_stmt) != NOP_EXPR)
++        return NULL;
++
++      use_lhs = gimple_assign_lhs (use_stmt);
++      use_type = TREE_TYPE (use_lhs);
++      if (!INTEGRAL_TYPE_P (use_type)
++          || (TYPE_UNSIGNED (type) == TYPE_UNSIGNED (use_type))
++          || (TYPE_PRECISION (type) != TYPE_PRECISION (use_type)))
++        return NULL;
++
++      type = use_type;
++      *last_stmt = use_stmt;
++    }
+ 
+   if (!types_compatible_p (half_type0, half_type1))
+     return NULL;
+@@ -413,7 +506,7 @@
+   vectype_out = get_vectype_for_scalar_type (type);
+   if (!vectype
+       || !vectype_out
+-      || !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt,
++      || !supportable_widening_operation (WIDEN_MULT_EXPR, *last_stmt,
+ 					  vectype_out, vectype,
+ 					  &dummy, &dummy, &dummy_code,
+ 					  &dummy_code, &dummy_int, &dummy_vec))
+@@ -462,16 +555,16 @@
+ */
+ 
+ static gimple
+-vect_recog_pow_pattern (gimple last_stmt, tree *type_in, tree *type_out)
++vect_recog_pow_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
+ {
+   tree fn, base, exp = NULL;
+   gimple stmt;
+   tree var;
+ 
+-  if (!is_gimple_call (last_stmt) || gimple_call_lhs (last_stmt) == NULL)
++  if (!is_gimple_call (*last_stmt) || gimple_call_lhs (*last_stmt) == NULL)
+     return NULL;
+ 
+-  fn = gimple_call_fndecl (last_stmt);
++  fn = gimple_call_fndecl (*last_stmt);
+   if (fn == NULL_TREE || DECL_BUILT_IN_CLASS (fn) != BUILT_IN_NORMAL)
+    return NULL;
+ 
+@@ -481,8 +574,8 @@
+     case BUILT_IN_POWI:
+     case BUILT_IN_POWF:
+     case BUILT_IN_POW:
+-      base = gimple_call_arg (last_stmt, 0);
+-      exp = gimple_call_arg (last_stmt, 1);
++      base = gimple_call_arg (*last_stmt, 0);
++      exp = gimple_call_arg (*last_stmt, 1);
+       if (TREE_CODE (exp) != REAL_CST
+ 	  && TREE_CODE (exp) != INTEGER_CST)
+         return NULL;
+@@ -574,21 +667,21 @@
+ 	 inner-loop nested in an outer-loop that us being vectorized).  */
+ 
+ static gimple
+-vect_recog_widen_sum_pattern (gimple last_stmt, tree *type_in, tree *type_out)
++vect_recog_widen_sum_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
+ {
+   gimple stmt;
+   tree oprnd0, oprnd1;
+-  stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
++  stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
+   tree type, half_type;
+   gimple pattern_stmt;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+   struct loop *loop = LOOP_VINFO_LOOP (loop_info);
+   tree var;
+ 
+-  if (!is_gimple_assign (last_stmt))
++  if (!is_gimple_assign (*last_stmt))
+     return NULL;
+ 
+-  type = gimple_expr_type (last_stmt);
++  type = gimple_expr_type (*last_stmt);
+ 
+   /* Look for the following pattern
+           DX = (TYPE) X;
+@@ -600,25 +693,25 @@
+   /* Starting from LAST_STMT, follow the defs of its uses in search
+      of the above pattern.  */
+ 
+-  if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
++  if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
+     return NULL;
+ 
+   if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
+     return NULL;
+ 
+-  oprnd0 = gimple_assign_rhs1 (last_stmt);
+-  oprnd1 = gimple_assign_rhs2 (last_stmt);
++  oprnd0 = gimple_assign_rhs1 (*last_stmt);
++  oprnd1 = gimple_assign_rhs2 (*last_stmt);
+   if (!types_compatible_p (TREE_TYPE (oprnd0), type)
+       || !types_compatible_p (TREE_TYPE (oprnd1), type))
+     return NULL;
+ 
+-  /* So far so good. Since last_stmt was detected as a (summation) reduction,
++  /* So far so good.  Since *last_stmt was detected as a (summation) reduction,
+      we know that oprnd1 is the reduction variable (defined by a loop-header
+      phi), and oprnd0 is an ssa-name defined by a stmt in the loop body.
+      Left to check that oprnd0 is defined by a cast from type 'type' to type
+      'TYPE'.  */
+ 
+-  if (!widened_name_p (oprnd0, last_stmt, &half_type, &stmt))
++  if (!widened_name_p (oprnd0, *last_stmt, &half_type, &stmt, true))
+     return NULL;
+ 
+   oprnd0 = gimple_assign_rhs1 (stmt);
+@@ -639,7 +732,7 @@
+ 
+   /* We don't allow changing the order of the computation in the inner-loop
+      when doing outer-loop vectorization.  */
+-  gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
++  gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
+ 
+   return pattern_stmt;
+ }
+@@ -669,23 +762,27 @@
+ 
+ static void
+ vect_pattern_recog_1 (
+-	gimple (* vect_recog_func) (gimple, tree *, tree *),
++	gimple (* vect_recog_func) (gimple *, tree *, tree *),
+ 	gimple_stmt_iterator si)
+ {
+   gimple stmt = gsi_stmt (si), pattern_stmt;
+-  stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
++  stmt_vec_info stmt_info;
+   stmt_vec_info pattern_stmt_info;
+-  loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
++  loop_vec_info loop_vinfo;
+   tree pattern_vectype;
+   tree type_in, type_out;
+   enum tree_code code;
+   int i;
+   gimple next;
+ 
+-  pattern_stmt = (* vect_recog_func) (stmt, &type_in, &type_out);
++  pattern_stmt = (* vect_recog_func) (&stmt, &type_in, &type_out);
+   if (!pattern_stmt)
+     return;
+ 
++  si = gsi_for_stmt (stmt);
++  stmt_info = vinfo_for_stmt (stmt);
++  loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
++ 
+   if (VECTOR_MODE_P (TYPE_MODE (type_in)))
+     {
+       /* No need to check target support (already checked by the pattern
+@@ -736,9 +833,9 @@
+     }
+ 
+   /* Mark the stmts that are involved in the pattern. */
+-  gsi_insert_before (&si, pattern_stmt, GSI_SAME_STMT);
+   set_vinfo_for_stmt (pattern_stmt,
+ 		      new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
++  gimple_set_bb (pattern_stmt, gimple_bb (stmt));
+   pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
+ 
+   STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
+@@ -761,8 +858,8 @@
+    LOOP_VINFO - a struct_loop_info of a loop in which we want to look for
+         computation idioms.
+ 
+-   Output - for each computation idiom that is detected we insert a new stmt
+-        that provides the same functionality and that can be vectorized. We
++   Output - for each computation idiom that is detected we create a new stmt
++        that provides the same functionality and that can be vectorized.  We
+         also record some information in the struct_stmt_info of the relevant
+         stmts, as explained below:
+ 
+@@ -777,52 +874,48 @@
+          S5: ... = ..use(a_0)..         -       -               -
+ 
+    Say the sequence {S1,S2,S3,S4} was detected as a pattern that can be
+-   represented by a single stmt. We then:
+-   - create a new stmt S6 that will replace the pattern.
+-   - insert the new stmt S6 before the last stmt in the pattern
++   represented by a single stmt.  We then:
++   - create a new stmt S6 equivalent to the pattern (the stmt is not
++     inserted into the code)
+    - fill in the STMT_VINFO fields as follows:
+ 
+                                   in_pattern_p  related_stmt    vec_stmt
+          S1: a_i = ....                 -       -               -
+          S2: a_2 = ..use(a_i)..         -       -               -
+          S3: a_1 = ..use(a_2)..         -       -               -
+-       > S6: a_new = ....               -       S4              -
+          S4: a_0 = ..use(a_1)..         true    S6              -
++          '---> S6: a_new = ....        -       S4              -
+          S5: ... = ..use(a_0)..         -       -               -
+ 
+    (the last stmt in the pattern (S4) and the new pattern stmt (S6) point
+-    to each other through the RELATED_STMT field).
++   to each other through the RELATED_STMT field).
+ 
+    S6 will be marked as relevant in vect_mark_stmts_to_be_vectorized instead
+    of S4 because it will replace all its uses.  Stmts {S1,S2,S3} will
+    remain irrelevant unless used by stmts other than S4.
+ 
+    If vectorization succeeds, vect_transform_stmt will skip over {S1,S2,S3}
+-   (because they are marked as irrelevant). It will vectorize S6, and record
++   (because they are marked as irrelevant).  It will vectorize S6, and record
+    a pointer to the new vector stmt VS6 both from S6 (as usual), and also
+-   from S4. We do that so that when we get to vectorizing stmts that use the
++   from S4.  We do that so that when we get to vectorizing stmts that use the
+    def of S4 (like S5 that uses a_0), we'll know where to take the relevant
+-   vector-def from. S4 will be skipped, and S5 will be vectorized as usual:
++   vector-def from.  S4 will be skipped, and S5 will be vectorized as usual:
+ 
+                                   in_pattern_p  related_stmt    vec_stmt
+          S1: a_i = ....                 -       -               -
+          S2: a_2 = ..use(a_i)..         -       -               -
+          S3: a_1 = ..use(a_2)..         -       -               -
+        > VS6: va_new = ....             -       -               -
+-         S6: a_new = ....               -       S4              VS6
+          S4: a_0 = ..use(a_1)..         true    S6              VS6
++          '---> S6: a_new = ....        -       S4              VS6
+        > VS5: ... = ..vuse(va_new)..    -       -               -
+          S5: ... = ..use(a_0)..         -       -               -
+ 
+-   DCE could then get rid of {S1,S2,S3,S4,S5,S6} (if their defs are not used
++   DCE could then get rid of {S1,S2,S3,S4,S5} (if their defs are not used
+    elsewhere), and we'll end up with:
+ 
+         VS6: va_new = ....
+-        VS5: ... = ..vuse(va_new)..
+-
+-   If vectorization does not succeed, DCE will clean S6 away (its def is
+-   not used), and we'll end up with the original sequence.
+-*/
++        VS5: ... = ..vuse(va_new)..  */
+ 
+ void
+ vect_pattern_recog (loop_vec_info loop_vinfo)
+@@ -832,7 +925,7 @@
+   unsigned int nbbs = loop->num_nodes;
+   gimple_stmt_iterator si;
+   unsigned int i, j;
+-  gimple (* vect_recog_func_ptr) (gimple, tree *, tree *);
++  gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vect_pattern_recog ===");
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-05-05 15:43:06 +0000
++++ new/gcc/tree-vect-slp.c	2011-06-19 10:59:13 +0000
+@@ -2510,6 +2510,8 @@
+       && STMT_VINFO_STRIDED_ACCESS (stmt_info)
+       && !REFERENCE_CLASS_P (gimple_get_lhs (stmt)))
+     si = gsi_for_stmt (SLP_INSTANCE_FIRST_LOAD_STMT (instance));
++  else if (is_pattern_stmt_p (stmt_info))
++     si = gsi_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
+   else
+     si = gsi_for_stmt (stmt);
+ 
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-06-02 12:12:00 +0000
++++ new/gcc/tree-vect-stmts.c	2011-06-22 06:21:13 +0000
+@@ -605,15 +605,76 @@
+             break;
+         }
+ 
+-      FOR_EACH_PHI_OR_STMT_USE (use_p, stmt, iter, SSA_OP_USE)
+-	{
+-	  tree op = USE_FROM_PTR (use_p);
+-	  if (!process_use (stmt, op, loop_vinfo, live_p, relevant, &worklist))
+-	    {
+-	      VEC_free (gimple, heap, worklist);
+-	      return false;
+-	    }
+-	}
++      if (is_pattern_stmt_p (vinfo_for_stmt (stmt)))
++        {
++          /* Pattern statements are not inserted into the code, so
++             FOR_EACH_PHI_OR_STMT_USE optimizes their operands out, and we
++             have to scan the RHS or function arguments instead.  */
++          if (is_gimple_assign (stmt))
++            {
++              tree rhs = gimple_assign_rhs1 (stmt);
++              if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
++                  == GIMPLE_SINGLE_RHS)
++                {
++                  unsigned int op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1
++                                                              (stmt));
++                  for (i = 0; i < op_num; i++)
++                    {
++                      tree op = TREE_OPERAND (rhs, i);
++                      if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                    &worklist))
++                       {
++                         VEC_free (gimple, heap, worklist);
++                         return false;
++                       }
++                    }
++                }
++              else if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
++                       == GIMPLE_BINARY_RHS)
++                {
++                  tree op = gimple_assign_rhs1 (stmt);
++                  if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                    &worklist))
++                    {
++                      VEC_free (gimple, heap, worklist);
++                      return false;
++                    }
++                  op = gimple_assign_rhs2 (stmt);
++                  if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                    &worklist))
++                    {
++                      VEC_free (gimple, heap, worklist);
++                      return false;
++                    }
++                }
++              else
++                return false;
++            }
++          else if (is_gimple_call (stmt))
++            {
++              for (i = 0; i < gimple_call_num_args (stmt); i++)
++                {
++                  tree arg = gimple_call_arg (stmt, i);
++                  if (!process_use (stmt, arg, loop_vinfo, live_p, relevant,
++                                    &worklist))
++                    {
++                      VEC_free (gimple, heap, worklist);
++                      return false;
++                    }
++                }
++            }
++        }
++      else
++        FOR_EACH_PHI_OR_STMT_USE (use_p, stmt, iter, SSA_OP_USE)
++          {
++            tree op = USE_FROM_PTR (use_p);
++            if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                              &worklist))
++              {
++                VEC_free (gimple, heap, worklist);
++                return false;
++              }
++          }
+     } /* while worklist */
+ 
+   VEC_free (gimple, heap, worklist);
+@@ -1405,6 +1466,7 @@
+   VEC(tree, heap) *vargs = NULL;
+   enum { NARROW, NONE, WIDEN } modifier;
+   size_t i, nargs;
++  tree lhs;
+ 
+   /* FORNOW: unsupported in basic block SLP.  */
+   gcc_assert (loop_vinfo);
+@@ -1542,7 +1604,7 @@
+   /** Transform.  **/
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+-    fprintf (vect_dump, "transform operation.");
++    fprintf (vect_dump, "transform call.");
+ 
+   /* Handle def.  */
+   scalar_dest = gimple_call_lhs (stmt);
+@@ -1661,8 +1723,11 @@
+      rhs of the statement with something harmless.  */
+ 
+   type = TREE_TYPE (scalar_dest);
+-  new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
+-				  build_zero_cst (type));
++  if (is_pattern_stmt_p (stmt_info))
++    lhs = gimple_call_lhs (STMT_VINFO_RELATED_STMT (stmt_info));
++  else
++    lhs = gimple_call_lhs (stmt);
++  new_stmt = gimple_build_assign (lhs, build_zero_cst (type));
+   set_vinfo_for_stmt (new_stmt, stmt_info);
+   set_vinfo_for_stmt (stmt, NULL);
+   STMT_VINFO_STMT (stmt_info) = new_stmt;
+@@ -3231,6 +3296,33 @@
+ 	fprintf (vect_dump, "use not simple.");
+       return false;
+     }
++
++  op_type = TREE_CODE_LENGTH (code);
++  if (op_type == binary_op)
++    {
++      bool ok;
++
++      op1 = gimple_assign_rhs2 (stmt);
++      if (code == WIDEN_MULT_EXPR)
++        {
++	  /* For WIDEN_MULT_EXPR, if OP0 is a constant, use the type of
++	     OP1.  */
++          if (CONSTANT_CLASS_P (op0))
++            ok = vect_is_simple_use_1 (op1, loop_vinfo, NULL,
++                             &def_stmt, &def, &dt[1], &vectype_in);
++          else
++            ok = vect_is_simple_use (op1, loop_vinfo, NULL, &def_stmt, &def,
++                                     &dt[1]);
++
++          if (!ok)
++            {
++	      if (vect_print_dump_info (REPORT_DETAILS))
++	        fprintf (vect_dump, "use not simple.");
++              return false;
++            }
++        }        
++    }
++
+   /* If op0 is an external or constant def use a vector type with
+      the same size as the output vector type.  */
+   if (!vectype_in)
+@@ -3263,18 +3355,6 @@
+ 
+   gcc_assert (ncopies >= 1);
+ 
+-  op_type = TREE_CODE_LENGTH (code);
+-  if (op_type == binary_op)
+-    {
+-      op1 = gimple_assign_rhs2 (stmt);
+-      if (!vect_is_simple_use (op1, loop_vinfo, NULL, &def_stmt, &def, &dt[1]))
+-        {
+-	  if (vect_print_dump_info (REPORT_DETAILS))
+-	    fprintf (vect_dump, "use not simple.");
+-          return false;
+-        }
+-    }
+-
+   /* Supportable by target?  */
+   if (!supportable_widening_operation (code, stmt, vectype_out, vectype_in,
+ 				       &decl1, &decl2, &code1, &code2,
+@@ -3300,6 +3380,14 @@
+     fprintf (vect_dump, "transform type promotion operation. ncopies = %d.",
+                         ncopies);
+ 
++  if (code == WIDEN_MULT_EXPR)
++    {
++      if (CONSTANT_CLASS_P (op0))
++	op0 = fold_convert (TREE_TYPE (op1), op0);
++      else if (CONSTANT_CLASS_P (op1))
++	op1 = fold_convert (TREE_TYPE (op0), op1);
++    }
++
+   /* Handle def.  */
+   /* In case of multi-step promotion, we first generate promotion operations
+      to the intermediate types, and then from that types to the final one.
+@@ -4824,10 +4912,26 @@
+   if (!STMT_VINFO_RELEVANT_P (stmt_info)
+       && !STMT_VINFO_LIVE_P (stmt_info))
+     {
+-      if (vect_print_dump_info (REPORT_DETAILS))
+-        fprintf (vect_dump, "irrelevant.");
++      gimple pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
++      if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++          && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
++              || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
++        {
++          stmt = pattern_stmt;
++          stmt_info = vinfo_for_stmt (pattern_stmt);
++          if (vect_print_dump_info (REPORT_DETAILS))
++            {
++              fprintf (vect_dump, "==> examining pattern statement: ");
++              print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++            }
++        }
++      else
++        {
++          if (vect_print_dump_info (REPORT_DETAILS))
++            fprintf (vect_dump, "irrelevant.");
+ 
+-      return true;
++          return true;
++        }
+     }
+ 
+   switch (STMT_VINFO_DEF_TYPE (stmt_info))
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2011-05-05 15:43:06 +0000
++++ new/gcc/tree-vectorizer.h	2011-06-19 10:59:13 +0000
+@@ -884,7 +884,7 @@
+ /* Pattern recognition functions.
+    Additional pattern recognition functions can (and will) be added
+    in the future.  */
+-typedef gimple (* vect_recog_func_ptr) (gimple, tree *, tree *);
++typedef gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
+ #define NUM_PATTERNS 4
+ void vect_pattern_recog (loop_vec_info);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
new file mode 100644
index 0000000000..4abfa02a77
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
@@ -0,0 +1,24 @@
+2011-06-28  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+	gcc/
+	2011-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/49385
+	* config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast
+	one of the operands is a register.
+Index: gcc-4_6-branch/gcc/config/arm/thumb2.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/thumb2.md	2011-09-16 20:22:40.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/thumb2.md	2011-09-16 20:28:47.648690433 -0700
+@@ -207,7 +207,9 @@
+ (define_insn "*thumb2_movhi_insn"
+   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
+ 	(match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
+-  "TARGET_THUMB2"
++  "TARGET_THUMB2
++  && (register_operand (operands[0], HImode)
++     || register_operand (operands[1], HImode))"
+   "@
+    mov%?\\t%0, %1\\t%@ movhi
+    movw%?\\t%0, %L1\\t%@ movhi
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch
new file mode 100644
index 0000000000..a548b1b683
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch
@@ -0,0 +1,25 @@
+2011-06-30  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+	LP 744754
+        2011-04-17  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* config/arm/arm.c (neon_struct_mem_operand):
+	Support POST_INC/PRE_DEC memory operands.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-06-27 22:14:07 +0000
++++ new/gcc/config/arm/arm.c	2011-06-29 09:13:17 +0000
+@@ -9357,6 +9357,11 @@
+   if (GET_CODE (ind) == REG)
+     return arm_address_register_rtx_p (ind, 0);
+ 
++  /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db).  */
++  if (GET_CODE (ind) == POST_INC
++      || GET_CODE (ind) == PRE_DEC)
++    return arm_address_register_rtx_p (XEXP (ind, 0), 0);
++
+   return FALSE;
+ }
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch
new file mode 100644
index 0000000000..15046a766e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch
@@ -0,0 +1,25 @@
+2011-07-03  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from FSF:
+	2011-06-12  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-data-refs.c (vect_peeling_hash_get_most_frequent):
+	Take number of iterations to peel into account for equally frequent
+	misalignment values.
+
+=== modified file 'gcc/tree-vect-data-refs.c'
+--- old/gcc/tree-vect-data-refs.c	2011-06-02 12:12:00 +0000
++++ new/gcc/tree-vect-data-refs.c	2011-06-29 11:20:24 +0000
+@@ -1256,7 +1256,9 @@
+   vect_peel_info elem = (vect_peel_info) *slot;
+   vect_peel_extended_info max = (vect_peel_extended_info) data;
+ 
+-  if (elem->count > max->peel_info.count)
++  if (elem->count > max->peel_info.count
++      || (elem->count == max->peel_info.count
++          && max->peel_info.npeel > elem->npeel))
+     {
+       max->peel_info.npeel = elem->npeel;
+       max->peel_info.count = elem->count;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch
new file mode 100644
index 0000000000..f1f7718eb5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch
@@ -0,0 +1,182 @@
+2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* builtins.c (get_object_alignment): Fix comment.
+	* fold-const.c (get_pointer_modulus_and_residue): Remove
+	allow_func_align.  Use get_object_alignment.
+	(fold_binary_loc): Update caller.
+
+2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-06-29  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR tree-optimization/49545
+	* builtins.c (get_object_alignment_1): Update function comment.
+	Do not use DECL_ALIGN for functions, but test
+	TARGET_PTRMEMFUNC_VBIT_LOCATION instead.
+	* fold-const.c (get_pointer_modulus_and_residue): Don't check
+	for functions here.
+	* tree-ssa-ccp.c (get_value_from_alignment): Likewise.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-06-29  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.dg/torture/pr49169.c: Restrict to ARM and MIPS targets.
+
+2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-07-27  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/49169
+	* fold-const.c (get_pointer_modulus_and_residue): Don't rely on
+	the alignment of function decls.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-07-27  Michael Hope  <michael.hope@linaro.org>
+		    Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR tree-optimization/49169
+	* gcc.dg/torture/pr49169.c: New test.
+
+=== modified file 'gcc/builtins.c'
+--- old/gcc/builtins.c	2011-03-03 21:56:58 +0000
++++ new/gcc/builtins.c	2011-07-04 09:52:27 +0000
+@@ -264,7 +264,14 @@
+ }
+ 
+ /* Return the alignment in bits of EXP, an object.
+-   Don't return more than MAX_ALIGN no matter what.  */
++   Don't return more than MAX_ALIGN no matter what.
++
++   Note that the address (and thus the alignment) computed here is based
++   on the address to which a symbol resolves, whereas DECL_ALIGN is based
++   on the address at which an object is actually located.  These two
++   addresses are not always the same.  For example, on ARM targets,
++   the address &foo of a Thumb function foo() has the lowest bit set,
++   whereas foo() itself starts on an even address.  */
+ 
+ unsigned int
+ get_object_alignment (tree exp, unsigned int max_align)
+@@ -286,7 +293,21 @@
+     exp = DECL_INITIAL (exp);
+   if (DECL_P (exp)
+       && TREE_CODE (exp) != LABEL_DECL)
+-    align = DECL_ALIGN (exp);
++    {
++      if (TREE_CODE (exp) == FUNCTION_DECL)
++	{
++	  /* Function addresses can encode extra information besides their
++	     alignment.  However, if TARGET_PTRMEMFUNC_VBIT_LOCATION
++	     allows the low bit to be used as a virtual bit, we know
++	     that the address itself must be 2-byte aligned.  */
++	  if (TARGET_PTRMEMFUNC_VBIT_LOCATION == ptrmemfunc_vbit_in_pfn)
++	    align = 2 * BITS_PER_UNIT;
++	  else
++	    align = BITS_PER_UNIT;
++	}
++      else
++	align = DECL_ALIGN (exp);
++    }
+   else if (CONSTANT_CLASS_P (exp))
+     {
+       align = TYPE_ALIGN (TREE_TYPE (exp));
+
+=== modified file 'gcc/fold-const.c'
+--- old/gcc/fold-const.c	2011-05-23 20:37:18 +0000
++++ new/gcc/fold-const.c	2011-07-04 09:52:27 +0000
+@@ -9232,15 +9232,10 @@
+    0 <= N < M as is common.  In general, the precise value of P is unknown.
+    M is chosen as large as possible such that constant N can be determined.
+ 
+-   Returns M and sets *RESIDUE to N.
+-
+-   If ALLOW_FUNC_ALIGN is true, do take functions' DECL_ALIGN_UNIT into
+-   account.  This is not always possible due to PR 35705.
+- */
++   Returns M and sets *RESIDUE to N.  */
+ 
+ static unsigned HOST_WIDE_INT
+-get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue,
+-				 bool allow_func_align)
++get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue)
+ {
+   enum tree_code code;
+ 
+@@ -9270,9 +9265,8 @@
+ 	    }
+ 	}
+ 
+-      if (DECL_P (expr)
+-	  && (allow_func_align || TREE_CODE (expr) != FUNCTION_DECL))
+-	return DECL_ALIGN_UNIT (expr);
++      if (DECL_P (expr))
++	return get_object_alignment (expr, ~0U) / BITS_PER_UNIT;
+     }
+   else if (code == POINTER_PLUS_EXPR)
+     {
+@@ -9282,8 +9276,7 @@
+ 
+       op0 = TREE_OPERAND (expr, 0);
+       STRIP_NOPS (op0);
+-      modulus = get_pointer_modulus_and_residue (op0, residue,
+-						 allow_func_align);
++      modulus = get_pointer_modulus_and_residue (op0, residue);
+ 
+       op1 = TREE_OPERAND (expr, 1);
+       STRIP_NOPS (op1);
+@@ -11163,8 +11156,7 @@
+ 	  unsigned HOST_WIDE_INT modulus, residue;
+ 	  unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg1);
+ 
+-	  modulus = get_pointer_modulus_and_residue (arg0, &residue,
+-						     integer_onep (arg1));
++	  modulus = get_pointer_modulus_and_residue (arg0, &residue);
+ 
+ 	  /* This works because modulus is a power of 2.  If this weren't the
+ 	     case, we'd have to replace it by its greatest power-of-2
+
+=== added file 'gcc/testsuite/gcc.dg/torture/pr49169.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49169.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49169.c	2011-06-29 09:46:06 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile { target { arm*-*-* || mips*-*-* } } } */
++
++#include <stdlib.h>
++#include <stdint.h>
++
++int
++main (void)
++{
++  void *p = main;
++  if ((intptr_t) p & 1)
++    abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "abort" } } */
+
+=== modified file 'gcc/tree-ssa-ccp.c'
+--- old/gcc/tree-ssa-ccp.c	2011-05-05 15:42:22 +0000
++++ new/gcc/tree-ssa-ccp.c	2011-06-29 09:46:06 +0000
+@@ -522,10 +522,6 @@
+     val = bit_value_binop (PLUS_EXPR, TREE_TYPE (expr),
+ 			   TREE_OPERAND (base, 0), TREE_OPERAND (base, 1));
+   else if (base
+-	   /* ???  While function decls have DECL_ALIGN their addresses
+-	      may encode extra information in the lower bits on some
+-	      targets (PR47239).  Simply punt for function decls for now.  */
+-	   && TREE_CODE (base) != FUNCTION_DECL
+ 	   && ((align = get_object_alignment (base, BIGGEST_ALIGNMENT))
+ 		> BITS_PER_UNIT))
+     {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
new file mode 100644
index 0000000000..3a149231f8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
@@ -0,0 +1,1281 @@
+2011-07-11  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from FSF:
+	2011-06-16  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vectorizer.h (vect_recog_func_ptr): Change the first
+	argument to be a VEC of statements.
+	* tree-vect-loop.c (vect_determine_vectorization_factor): Remove the
+	assert that pattern statements have to have their vector type set.
+	* tree-vect-patterns.c (vect_recog_widen_sum_pattern):
+	Change the first argument to be a VEC of statements.  Update
+	documentation.
+	(vect_recog_dot_prod_pattern, vect_recog_pow_pattern): Likewise.
+	(vect_handle_widen_mult_by_const): New function.
+	(vect_recog_widen_mult_pattern):  Change the first argument to be a
+	VEC of statements.  Update documentation.  Check that the constant is
+	INTEGER_CST.  Support multiplication by a constant that fits an
+	intermediate type - call vect_handle_widen_mult_by_const.
+	(vect_pattern_recog_1): Update vect_recog_func_ptr and its
+	call.  Handle additional pattern statements if necessary.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-widen-mult-half-u8.c: New test.
+
+	and
+	2011-06-30  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-loop.c (vect_determine_vectorization_factor): Handle
+	both pattern and original statements if necessary.
+	(vect_transform_loop): Likewise.
+	* tree-vect-patterns.c (vect_pattern_recog): Update documentation.
+	* tree-vect-stmts.c (vect_mark_relevant): Add new argument.
+	Mark the pattern statement only if the original statement doesn't
+	have its own uses.
+	(process_use): Call vect_mark_relevant with additional parameter.
+	(vect_mark_stmts_to_be_vectorized): Likewise.
+	(vect_get_vec_def_for_operand): Use vectorized pattern statement.
+	(vect_analyze_stmt): Handle both pattern and original statements
+	if necessary.
+	(vect_transform_stmt): Don't store vectorized pattern statement
+	in the original statement.
+	(vect_is_simple_use_1): Use related pattern statement only if the
+	original statement is irrelevant.
+	* tree-vect-slp.c (vect_get_and_check_slp_defs): Likewise.
+
+	gcc/testsuite/
+	* gcc.dg/vect/slp-widen-mult-half.c: New test.
+	* gcc.dg/vect/vect-widen-mult-half.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c'
+Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c	2012-01-09 15:03:29.156918805 -0800
+@@ -0,0 +1,52 @@
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++#include <stdlib.h>
++
++#define N 32
++#define COEF 32470
++#define COEF2 324700
++
++unsigned char in[N];
++int out[N];
++int out2[N];
++
++__attribute__ ((noinline)) void
++foo ()
++{
++  int i;
++
++  for (i = 0; i < N/2; i++)
++    {
++      out[2*i] = in[2*i] * COEF;
++      out2[2*i] = in[2*i] + COEF2;
++      out[2*i+1] = in[2*i+1] * COEF;
++      out2[2*i+1] = in[2*i+1] + COEF2;
++    }
++}
++
++int main (void)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo ();
++
++  for (i = 0; i < N; i++)
++    if (out[i] != in[i] * COEF || out2[i] != in[i] + COEF2)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_widen_mult_hi_to_si } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_widen_mult_hi_to_si } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c	2012-01-09 15:03:29.156918805 -0800
+@@ -0,0 +1,59 @@
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++#include <stdlib.h>
++
++#define N 32
++#define COEF 32470
++
++unsigned char in[N];
++int out[N];
++
++__attribute__ ((noinline)) void
++foo ()
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    out[i] = in[i] * COEF;
++}
++
++__attribute__ ((noinline)) void
++bar ()
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    out[i] = COEF * in[i];
++}
++
++int main (void)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo ();
++
++  for (i = 0; i < N; i++)
++    if (out[i] != in[i] * COEF)
++      abort ();
++
++  bar ();
++
++  for (i = 0; i < N; i++)
++    if (out[i] != in[i] * COEF)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_widen_mult_hi_to_si } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c	2012-01-09 15:03:29.160918806 -0800
+@@ -0,0 +1,49 @@
++/* { dg-require-effective-target vect_int } */
++
++#include "tree-vect.h"
++#include <stdlib.h>
++
++#define N 32
++#define COEF 32470
++#define COEF2 324700
++
++unsigned char in[N];
++int out[N];
++int out2[N];
++
++__attribute__ ((noinline)) void
++foo (int a)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      out[i] = in[i] * COEF;
++      out2[i] = in[i] + a;
++    }
++}
++
++int main (void)
++{
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (COEF2);
++
++  for (i = 0; i < N; i++)
++    if (out[i] != in[i] * COEF || out2[i] != in[i] + COEF2)
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_widen_mult_hi_to_si } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+Index: gcc-4_6-branch/gcc/tree-vect-loop.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vect-loop.c	2012-01-09 15:02:15.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vect-loop.c	2012-01-09 15:03:29.160918806 -0800
+@@ -181,6 +181,8 @@
+   stmt_vec_info stmt_info;
+   int i;
+   HOST_WIDE_INT dummy;
++  gimple stmt, pattern_stmt = NULL;
++  bool analyze_pattern_stmt = false;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vect_determine_vectorization_factor ===");
+@@ -241,12 +243,20 @@
+ 	    }
+ 	}
+ 
+-      for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
++      for (si = gsi_start_bb (bb); !gsi_end_p (si) || analyze_pattern_stmt;)
+         {
+-	  tree vf_vectype;
+-	  gimple stmt = gsi_stmt (si), pattern_stmt;
+-	  stmt_info = vinfo_for_stmt (stmt);
++          tree vf_vectype;
++
++          if (analyze_pattern_stmt)
++            {
++              stmt = pattern_stmt;
++              analyze_pattern_stmt = false;
++            }
++          else
++            stmt = gsi_stmt (si);
+ 
++         stmt_info = vinfo_for_stmt (stmt);
++              
+ 	  if (vect_print_dump_info (REPORT_DETAILS))
+ 	    {
+ 	      fprintf (vect_dump, "==> examining statement: ");
+@@ -276,10 +286,17 @@
+                {
+                  if (vect_print_dump_info (REPORT_DETAILS))
+                    fprintf (vect_dump, "skip.");
++                 gsi_next (&si);
+                  continue;
+                }
+ 	    }
+ 
++          else if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++                   && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
++                   && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
++                       || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
++            analyze_pattern_stmt = true;
++
+ 	  if (gimple_get_lhs (stmt) == NULL_TREE)
+ 	    {
+ 	      if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
+@@ -311,9 +328,7 @@
+ 	    }
+ 	  else
+ 	    {
+-	      gcc_assert (!STMT_VINFO_DATA_REF (stmt_info)
+-			  && !is_pattern_stmt_p (stmt_info));
+-
++	      gcc_assert (!STMT_VINFO_DATA_REF (stmt_info));
+ 	      scalar_type = TREE_TYPE (gimple_get_lhs (stmt));
+ 	      if (vect_print_dump_info (REPORT_DETAILS))
+ 		{
+@@ -385,6 +400,9 @@
+ 	  if (!vectorization_factor
+ 	      || (nunits > vectorization_factor))
+ 	    vectorization_factor = nunits;
++
++          if (!analyze_pattern_stmt)
++            gsi_next (&si);
+         }
+     }
+ 
+@@ -4740,6 +4758,8 @@
+   tree cond_expr = NULL_TREE;
+   gimple_seq cond_expr_stmt_list = NULL;
+   bool do_peeling_for_loop_bound;
++  gimple stmt, pattern_stmt;
++  bool transform_pattern_stmt = false;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vec_transform_loop ===");
+@@ -4827,11 +4847,19 @@
+ 	    }
+ 	}
+ 
+-      for (si = gsi_start_bb (bb); !gsi_end_p (si);)
++      pattern_stmt = NULL;
++      for (si = gsi_start_bb (bb); !gsi_end_p (si) || transform_pattern_stmt;)
+ 	{
+-	  gimple stmt = gsi_stmt (si), pattern_stmt;
+ 	  bool is_store;
+ 
++          if (transform_pattern_stmt)
++            {
++              stmt = pattern_stmt;
++              transform_pattern_stmt = false;
++            }
++          else
++            stmt = gsi_stmt (si);
++
+ 	  if (vect_print_dump_info (REPORT_DETAILS))
+ 	    {
+ 	      fprintf (vect_dump, "------>vectorizing statement: ");
+@@ -4869,6 +4897,11 @@
+ 	          continue;
+                 }
+ 	    }
++          else if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++                   && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
++                   && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
++                       || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
++            transform_pattern_stmt = true;
+ 
+ 	  gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
+ 	  nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
+@@ -4897,8 +4930,9 @@
+ 	      /* Hybrid SLP stmts must be vectorized in addition to SLP.  */
+ 	      if (!vinfo_for_stmt (stmt) || PURE_SLP_STMT (stmt_info))
+ 		{
+-		  gsi_next (&si);
+-		  continue;
++                  if (!transform_pattern_stmt)
++ 		    gsi_next (&si);
++  		  continue;
+ 		}
+ 	    }
+ 
+@@ -4917,7 +4951,7 @@
+ 		     the chain.  */
+ 		  vect_remove_stores (DR_GROUP_FIRST_DR (stmt_info));
+ 		  gsi_remove (&si, true);
+-		  continue;
++ 		  continue;
+ 		}
+ 	      else
+ 		{
+@@ -4927,7 +4961,9 @@
+ 		  continue;
+ 		}
+ 	    }
+-	  gsi_next (&si);
++
++          if (!transform_pattern_stmt)
++ 	    gsi_next (&si);
+ 	}		        /* stmts in BB */
+     }				/* BBs in loop */
+ 
+Index: gcc-4_6-branch/gcc/tree-vect-patterns.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vect-patterns.c	2012-01-09 15:02:15.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vect-patterns.c	2012-01-09 15:03:29.160918806 -0800
+@@ -39,10 +39,13 @@
+ #include "diagnostic-core.h"
+ 
+ /* Pattern recognition functions  */
+-static gimple vect_recog_widen_sum_pattern (gimple *, tree *, tree *);
+-static gimple vect_recog_widen_mult_pattern (gimple *, tree *, tree *);
+-static gimple vect_recog_dot_prod_pattern (gimple *, tree *, tree *);
+-static gimple vect_recog_pow_pattern (gimple *, tree *, tree *);
++static gimple vect_recog_widen_sum_pattern (VEC (gimple, heap) **, tree *,
++					    tree *);
++static gimple vect_recog_widen_mult_pattern (VEC (gimple, heap) **, tree *,
++					     tree *);
++static gimple vect_recog_dot_prod_pattern (VEC (gimple, heap) **, tree *,
++					   tree *);
++static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
+ static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
+ 	vect_recog_widen_mult_pattern,
+ 	vect_recog_widen_sum_pattern,
+@@ -142,9 +145,9 @@
+ 
+    Input:
+ 
+-   * LAST_STMT: A stmt from which the pattern search begins. In the example,
+-   when this function is called with S7, the pattern {S3,S4,S5,S6,S7} will be
+-   detected.
++   * STMTS: Contains a stmt from which the pattern search begins.  In the
++   example, when this function is called with S7, the pattern {S3,S4,S5,S6,S7}
++   will be detected.
+ 
+    Output:
+ 
+@@ -165,12 +168,13 @@
+          inner-loop nested in an outer-loop that us being vectorized).  */
+ 
+ static gimple
+-vect_recog_dot_prod_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
++vect_recog_dot_prod_pattern (VEC (gimple, heap) **stmts, tree *type_in,
++			     tree *type_out)
+ {
+-  gimple stmt;
++  gimple stmt, last_stmt = VEC_index (gimple, *stmts, 0);
+   tree oprnd0, oprnd1;
+   tree oprnd00, oprnd01;
+-  stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
++  stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
+   tree type, half_type;
+   gimple pattern_stmt;
+   tree prod_type;
+@@ -178,10 +182,10 @@
+   struct loop *loop = LOOP_VINFO_LOOP (loop_info);
+   tree var, rhs;
+ 
+-  if (!is_gimple_assign (*last_stmt))
++  if (!is_gimple_assign (last_stmt))
+     return NULL;
+ 
+-  type = gimple_expr_type (*last_stmt);
++  type = gimple_expr_type (last_stmt);
+ 
+   /* Look for the following pattern
+           DX = (TYPE1) X;
+@@ -207,7 +211,7 @@
+   /* Starting from LAST_STMT, follow the defs of its uses in search
+      of the above pattern.  */
+ 
+-  if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
++  if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
+     return NULL;
+ 
+   if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
+@@ -228,12 +232,12 @@
+ 
+       if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
+         return NULL;
+-      oprnd0 = gimple_assign_rhs1 (*last_stmt);
+-      oprnd1 = gimple_assign_rhs2 (*last_stmt);
++      oprnd0 = gimple_assign_rhs1 (last_stmt);
++      oprnd1 = gimple_assign_rhs2 (last_stmt);
+       if (!types_compatible_p (TREE_TYPE (oprnd0), type)
+ 	  || !types_compatible_p (TREE_TYPE (oprnd1), type))
+         return NULL;
+-      stmt = *last_stmt;
++      stmt = last_stmt;
+ 
+       if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt, true))
+         {
+@@ -319,11 +323,79 @@
+ 
+   /* We don't allow changing the order of the computation in the inner-loop
+      when doing outer-loop vectorization.  */
+-  gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
++  gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
+ 
+   return pattern_stmt;
+ }
+ 
++/* Handle two cases of multiplication by a constant.  The first one is when
++   the constant, CONST_OPRND, fits the type (HALF_TYPE) of the second
++   operand (OPRND).  In that case, we can peform widen-mult from HALF_TYPE to
++   TYPE.
++
++   Otherwise, if the type of the result (TYPE) is at least 4 times bigger than
++   HALF_TYPE, and CONST_OPRND fits an intermediate type (2 times smaller than
++   TYPE), we can perform widen-mult from the intermediate type to TYPE and
++   replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t;  */
++
++static bool
++vect_handle_widen_mult_by_const (tree const_oprnd, tree *oprnd,
++                                 VEC (gimple, heap) **stmts, tree type,
++                                 tree *half_type, gimple def_stmt)
++{
++  tree new_type, new_oprnd, tmp;
++  gimple new_stmt;
++
++  if (int_fits_type_p (const_oprnd, *half_type))
++    {
++      /* CONST_OPRND is a constant of HALF_TYPE.  */
++      *oprnd = gimple_assign_rhs1 (def_stmt);
++      return true;
++    }
++
++  if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
++      || !vinfo_for_stmt (def_stmt))
++    return false;
++
++  /* TYPE is 4 times bigger than HALF_TYPE, try widen-mult for
++     a type 2 times bigger than HALF_TYPE.  */
++  new_type = build_nonstandard_integer_type (TYPE_PRECISION (type) / 2,
++                                             TYPE_UNSIGNED (type));
++  if (!int_fits_type_p (const_oprnd, new_type))
++    return false;
++
++  /* Use NEW_TYPE for widen_mult.  */
++  if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
++    {
++      new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
++      /* Check if the already created pattern stmt is what we need.  */
++      if (!is_gimple_assign (new_stmt)
++          || gimple_assign_rhs_code (new_stmt) != NOP_EXPR
++          || TREE_TYPE (gimple_assign_lhs (new_stmt)) != new_type)
++        return false;
++
++      *oprnd = gimple_assign_lhs (new_stmt);
++    }
++  else
++    {
++      /* Create a_T = (NEW_TYPE) a_t;  */
++      *oprnd = gimple_assign_rhs1 (def_stmt);
++      tmp = create_tmp_var (new_type, NULL);
++      add_referenced_var (tmp);
++      new_oprnd = make_ssa_name (tmp, NULL);
++      new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd, *oprnd,
++                                               NULL_TREE);
++      SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
++      STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
++      VEC_safe_push (gimple, heap, *stmts, def_stmt);
++      *oprnd = new_oprnd;
++    }
++
++  *half_type = new_type;
++  return true;
++}
++
++
+ /* Function vect_recog_widen_mult_pattern
+ 
+    Try to find the following pattern:
+@@ -361,28 +433,47 @@
+      S3  a_T = (TYPE) a_t;
+      S5  prod_T = a_T * CONST;
+ 
+-    Input:
++   A special case of multiplication by constants is when 'TYPE' is 4 times
++   bigger than 'type', but CONST fits an intermediate type 2 times smaller
++   than 'TYPE'.  In that case we create an additional pattern stmt for S3
++   to create a variable of the intermediate type, and perform widen-mult
++   on the intermediate type as well:
++
++     type a_t;
++     interm_type a_it;
++     TYPE a_T, prod_T,  prod_T';
++
++     S1  a_t = ;
++     S3  a_T = (TYPE) a_t;
++           '--> a_it = (interm_type) a_t;
++     S5  prod_T = a_T * CONST;
++           '--> prod_T' = a_it w* CONST;
++
++   Input/Output:
+ 
+-    * LAST_STMT: A stmt from which the pattern search begins.  In the example,
+-    when this function is called with S5, the pattern {S3,S4,S5,(S6)} is
+-    detected.
++   * STMTS: Contains a stmt from which the pattern search begins.  In the
++   example, when this function is called with S5, the pattern {S3,S4,S5,(S6)}
++   is detected.  In case of unsigned widen-mult, the original stmt (S5) is
++   replaced with S6 in STMTS.  In case of multiplication by a constant
++   of an intermediate type (the last case above), STMTS also contains S3
++   (inserted before S5).
+ 
+-    Output:
++   Output:
+ 
+-    * TYPE_IN: The type of the input arguments to the pattern.
++   * TYPE_IN: The type of the input arguments to the pattern.
+ 
+-    * TYPE_OUT: The type of the output of this pattern.
++   * TYPE_OUT: The type of the output of this pattern.
+ 
+-    * Return value: A new stmt that will be used to replace the sequence of
+-    stmts that constitute the pattern.  In this case it will be:
+-         WIDEN_MULT <a_t, b_t>
+- */
++   * Return value: A new stmt that will be used to replace the sequence of
++   stmts that constitute the pattern.  In this case it will be:
++        WIDEN_MULT <a_t, b_t>
++*/
+ 
+ static gimple
+-vect_recog_widen_mult_pattern (gimple *last_stmt,
+-			       tree *type_in,
+-			       tree *type_out)
++vect_recog_widen_mult_pattern (VEC (gimple, heap) **stmts,
++                               tree *type_in, tree *type_out)
+ {
++  gimple last_stmt = VEC_pop (gimple, *stmts);
+   gimple def_stmt0, def_stmt1;
+   tree oprnd0, oprnd1;
+   tree type, half_type0, half_type1;
+@@ -395,27 +486,27 @@
+   VEC (tree, heap) *dummy_vec;
+   bool op0_ok, op1_ok;
+ 
+-  if (!is_gimple_assign (*last_stmt))
++  if (!is_gimple_assign (last_stmt))
+     return NULL;
+ 
+-  type = gimple_expr_type (*last_stmt);
++  type = gimple_expr_type (last_stmt);
+ 
+   /* Starting from LAST_STMT, follow the defs of its uses in search
+      of the above pattern.  */
+ 
+-  if (gimple_assign_rhs_code (*last_stmt) != MULT_EXPR)
++  if (gimple_assign_rhs_code (last_stmt) != MULT_EXPR)
+     return NULL;
+ 
+-  oprnd0 = gimple_assign_rhs1 (*last_stmt);
+-  oprnd1 = gimple_assign_rhs2 (*last_stmt);
++  oprnd0 = gimple_assign_rhs1 (last_stmt);
++  oprnd1 = gimple_assign_rhs2 (last_stmt);
+   if (!types_compatible_p (TREE_TYPE (oprnd0), type)
+       || !types_compatible_p (TREE_TYPE (oprnd1), type))
+     return NULL;
+ 
+   /* Check argument 0.  */
+-  op0_ok = widened_name_p (oprnd0, *last_stmt, &half_type0, &def_stmt0, false);
++  op0_ok = widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false);
+   /* Check argument 1.  */
+-  op1_ok = widened_name_p (oprnd1, *last_stmt, &half_type1, &def_stmt1, false);
++  op1_ok = widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1, false);
+ 
+   /* In case of multiplication by a constant one of the operands may not match
+      the pattern, but not both.  */
+@@ -429,29 +520,21 @@
+     }
+   else if (!op0_ok)
+     {
+-      if (CONSTANT_CLASS_P (oprnd0)
+-         && TREE_CODE (half_type1) == INTEGER_TYPE
+-         && tree_int_cst_lt (oprnd0, TYPE_MAXVAL (half_type1))
+-         && tree_int_cst_lt (TYPE_MINVAL (half_type1), oprnd0))
+-        {
+-          /* OPRND0 is a constant of HALF_TYPE1.  */
+-          half_type0 = half_type1;
+-          oprnd1 = gimple_assign_rhs1 (def_stmt1);
+-        }
++      if (TREE_CODE (oprnd0) == INTEGER_CST
++          && TREE_CODE (half_type1) == INTEGER_TYPE
++          && vect_handle_widen_mult_by_const (oprnd0, &oprnd1, stmts, type,
++                                              &half_type1, def_stmt1))
++        half_type0 = half_type1;
+       else
+         return NULL;
+     }
+   else if (!op1_ok)
+     {
+-      if (CONSTANT_CLASS_P (oprnd1)
++      if (TREE_CODE (oprnd1) == INTEGER_CST
+           && TREE_CODE (half_type0) == INTEGER_TYPE
+-          && tree_int_cst_lt (oprnd1, TYPE_MAXVAL (half_type0))
+-          && tree_int_cst_lt (TYPE_MINVAL (half_type0), oprnd1))
+-        {
+-          /* OPRND1 is a constant of HALF_TYPE0.  */
+-          half_type1 = half_type0;
+-          oprnd0 = gimple_assign_rhs1 (def_stmt0);
+-        }
++          && vect_handle_widen_mult_by_const (oprnd1, &oprnd0, stmts, type,
++                                              &half_type0, def_stmt0))
++        half_type1 = half_type0;
+       else
+         return NULL;
+     }
+@@ -461,7 +544,7 @@
+      Use unsigned TYPE as the type for WIDEN_MULT_EXPR.  */
+   if (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (half_type0))
+     {
+-      tree lhs = gimple_assign_lhs (*last_stmt), use_lhs;
++      tree lhs = gimple_assign_lhs (last_stmt), use_lhs;
+       imm_use_iterator imm_iter;
+       use_operand_p use_p;
+       int nuses = 0;
+@@ -491,7 +574,7 @@
+         return NULL;
+ 
+       type = use_type;
+-      *last_stmt = use_stmt;
++      last_stmt = use_stmt;
+     }
+ 
+   if (!types_compatible_p (half_type0, half_type1))
+@@ -506,7 +589,7 @@
+   vectype_out = get_vectype_for_scalar_type (type);
+   if (!vectype
+       || !vectype_out
+-      || !supportable_widening_operation (WIDEN_MULT_EXPR, *last_stmt,
++      || !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt,
+ 					  vectype_out, vectype,
+ 					  &dummy, &dummy, &dummy_code,
+ 					  &dummy_code, &dummy_int, &dummy_vec))
+@@ -524,6 +607,7 @@
+   if (vect_print_dump_info (REPORT_DETAILS))
+     print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
+ 
++  VEC_safe_push (gimple, heap, *stmts, last_stmt);
+   return pattern_stmt;
+ }
+ 
+@@ -555,16 +639,17 @@
+ */
+ 
+ static gimple
+-vect_recog_pow_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
++vect_recog_pow_pattern (VEC (gimple, heap) **stmts, tree *type_in, tree *type_out)
+ {
++  gimple last_stmt = VEC_index (gimple, *stmts, 0);
+   tree fn, base, exp = NULL;
+   gimple stmt;
+   tree var;
+ 
+-  if (!is_gimple_call (*last_stmt) || gimple_call_lhs (*last_stmt) == NULL)
++  if (!is_gimple_call (last_stmt) || gimple_call_lhs (last_stmt) == NULL)
+     return NULL;
+ 
+-  fn = gimple_call_fndecl (*last_stmt);
++  fn = gimple_call_fndecl (last_stmt);
+   if (fn == NULL_TREE || DECL_BUILT_IN_CLASS (fn) != BUILT_IN_NORMAL)
+    return NULL;
+ 
+@@ -574,8 +659,8 @@
+     case BUILT_IN_POWI:
+     case BUILT_IN_POWF:
+     case BUILT_IN_POW:
+-      base = gimple_call_arg (*last_stmt, 0);
+-      exp = gimple_call_arg (*last_stmt, 1);
++      base = gimple_call_arg (last_stmt, 0);
++      exp = gimple_call_arg (last_stmt, 1);
+       if (TREE_CODE (exp) != REAL_CST
+ 	  && TREE_CODE (exp) != INTEGER_CST)
+         return NULL;
+@@ -667,21 +752,23 @@
+ 	 inner-loop nested in an outer-loop that us being vectorized).  */
+ 
+ static gimple
+-vect_recog_widen_sum_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
++vect_recog_widen_sum_pattern (VEC (gimple, heap) **stmts, tree *type_in,
++                              tree *type_out)
+ {
++  gimple last_stmt = VEC_index (gimple, *stmts, 0); 
+   gimple stmt;
+   tree oprnd0, oprnd1;
+-  stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
++  stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
+   tree type, half_type;
+   gimple pattern_stmt;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+   struct loop *loop = LOOP_VINFO_LOOP (loop_info);
+   tree var;
+ 
+-  if (!is_gimple_assign (*last_stmt))
++  if (!is_gimple_assign (last_stmt))
+     return NULL;
+ 
+-  type = gimple_expr_type (*last_stmt);
++  type = gimple_expr_type (last_stmt);
+ 
+   /* Look for the following pattern
+           DX = (TYPE) X;
+@@ -693,25 +780,25 @@
+   /* Starting from LAST_STMT, follow the defs of its uses in search
+      of the above pattern.  */
+ 
+-  if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
++  if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
+     return NULL;
+ 
+   if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
+     return NULL;
+ 
+-  oprnd0 = gimple_assign_rhs1 (*last_stmt);
+-  oprnd1 = gimple_assign_rhs2 (*last_stmt);
++  oprnd0 = gimple_assign_rhs1 (last_stmt);
++  oprnd1 = gimple_assign_rhs2 (last_stmt);
+   if (!types_compatible_p (TREE_TYPE (oprnd0), type)
+       || !types_compatible_p (TREE_TYPE (oprnd1), type))
+     return NULL;
+ 
+-  /* So far so good.  Since *last_stmt was detected as a (summation) reduction,
++  /* So far so good.  Since last_stmt was detected as a (summation) reduction,
+      we know that oprnd1 is the reduction variable (defined by a loop-header
+      phi), and oprnd0 is an ssa-name defined by a stmt in the loop body.
+      Left to check that oprnd0 is defined by a cast from type 'type' to type
+      'TYPE'.  */
+ 
+-  if (!widened_name_p (oprnd0, *last_stmt, &half_type, &stmt, true))
++  if (!widened_name_p (oprnd0, last_stmt, &half_type, &stmt, true))
+     return NULL;
+ 
+   oprnd0 = gimple_assign_rhs1 (stmt);
+@@ -732,8 +819,9 @@
+ 
+   /* We don't allow changing the order of the computation in the inner-loop
+      when doing outer-loop vectorization.  */
+-  gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
++  gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
+ 
++  VEC_safe_push (gimple, heap, *stmts, last_stmt);
+   return pattern_stmt;
+ }
+ 
+@@ -762,7 +850,7 @@
+ 
+ static void
+ vect_pattern_recog_1 (
+-	gimple (* vect_recog_func) (gimple *, tree *, tree *),
++	gimple (* vect_recog_func) (VEC (gimple, heap) **, tree *, tree *),
+ 	gimple_stmt_iterator si)
+ {
+   gimple stmt = gsi_stmt (si), pattern_stmt;
+@@ -774,12 +862,14 @@
+   enum tree_code code;
+   int i;
+   gimple next;
++  VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
+ 
+-  pattern_stmt = (* vect_recog_func) (&stmt, &type_in, &type_out);
++  VEC_quick_push (gimple, stmts_to_replace, stmt);
++  pattern_stmt = (* vect_recog_func) (&stmts_to_replace, &type_in, &type_out);
+   if (!pattern_stmt)
+     return;
+ 
+-  si = gsi_for_stmt (stmt);
++  stmt = VEC_last (gimple, stmts_to_replace);
+   stmt_info = vinfo_for_stmt (stmt);
+   loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
+  
+@@ -849,6 +939,35 @@
+   FOR_EACH_VEC_ELT (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, next)
+     if (next == stmt)
+       VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i); 
++
++  /* In case of widen-mult by a constant, it is possible that an additional
++     pattern stmt is created and inserted in STMTS_TO_REPLACE.  We create a
++     stmt_info for it, and mark the relevant statements.  */
++  for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
++              && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
++       i++)
++    {
++      stmt_info = vinfo_for_stmt (stmt);
++      pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
++      if (vect_print_dump_info (REPORT_DETAILS))
++        {
++          fprintf (vect_dump, "additional pattern stmt: ");
++          print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
++        }
++
++      set_vinfo_for_stmt (pattern_stmt,
++                      new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
++      gimple_set_bb (pattern_stmt, gimple_bb (stmt));
++      pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
++
++      STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
++      STMT_VINFO_DEF_TYPE (pattern_stmt_info)
++        = STMT_VINFO_DEF_TYPE (stmt_info);
++      STMT_VINFO_VECTYPE (pattern_stmt_info) = STMT_VINFO_VECTYPE (stmt_info);
++      STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
++    }
++
++  VEC_free (gimple, heap, stmts_to_replace);
+ }
+ 
+ 
+@@ -896,10 +1015,8 @@
+ 
+    If vectorization succeeds, vect_transform_stmt will skip over {S1,S2,S3}
+    (because they are marked as irrelevant).  It will vectorize S6, and record
+-   a pointer to the new vector stmt VS6 both from S6 (as usual), and also
+-   from S4.  We do that so that when we get to vectorizing stmts that use the
+-   def of S4 (like S5 that uses a_0), we'll know where to take the relevant
+-   vector-def from.  S4 will be skipped, and S5 will be vectorized as usual:
++   a pointer to the new vector stmt VS6 from S6 (as usual).
++   S4 will be skipped, and S5 will be vectorized as usual:
+ 
+                                   in_pattern_p  related_stmt    vec_stmt
+          S1: a_i = ....                 -       -               -
+@@ -915,7 +1032,21 @@
+    elsewhere), and we'll end up with:
+ 
+         VS6: va_new = ....
+-        VS5: ... = ..vuse(va_new)..  */
++        VS5: ... = ..vuse(va_new)..  
++
++   In case of more than one pattern statements, e.g., widen-mult with
++   intermediate type:
++
++     S1  a_t = ;
++     S2  a_T = (TYPE) a_t;
++           '--> S3: a_it = (interm_type) a_t;
++     S4  prod_T = a_T * CONST;
++           '--> S5: prod_T' = a_it w* CONST;
++   
++   there may be other users of a_T outside the pattern. In that case S2 will
++   be marked as relevant (as well as S3), and both S2 and S3 will be analyzed
++   and vectorized.  The vector stmt VS2 will be recorded in S2, and VS3 will
++   be recorded in S3.  */
+ 
+ void
+ vect_pattern_recog (loop_vec_info loop_vinfo)
+@@ -925,7 +1056,7 @@
+   unsigned int nbbs = loop->num_nodes;
+   gimple_stmt_iterator si;
+   unsigned int i, j;
+-  gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
++  gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vect_pattern_recog ===");
+Index: gcc-4_6-branch/gcc/tree-vect-slp.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vect-slp.c	2012-01-09 15:02:15.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vect-slp.c	2012-01-09 15:03:29.160918806 -0800
+@@ -152,7 +152,9 @@
+       if (loop && def_stmt && gimple_bb (def_stmt)
+           && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
+           && vinfo_for_stmt (def_stmt)
+-          && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (def_stmt)))
++          && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (def_stmt))
++          && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
++          && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
+         {
+           if (!*first_stmt_dt0)
+             *pattern0 = true;
+Index: gcc-4_6-branch/gcc/tree-vect-stmts.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vect-stmts.c	2012-01-09 15:02:15.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vect-stmts.c	2012-01-09 15:06:23.636927250 -0800
+@@ -126,33 +126,72 @@
+ 
+ static void
+ vect_mark_relevant (VEC(gimple,heap) **worklist, gimple stmt,
+-		    enum vect_relevant relevant, bool live_p)
++		    enum vect_relevant relevant, bool live_p,
++		    bool used_in_pattern)
+ {
+   stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
+   enum vect_relevant save_relevant = STMT_VINFO_RELEVANT (stmt_info);
+   bool save_live_p = STMT_VINFO_LIVE_P (stmt_info);
++  gimple pattern_stmt;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "mark relevant %d, live %d.", relevant, live_p);
+ 
++  /* If this stmt is an original stmt in a pattern, we might need to mark its
++     related pattern stmt instead of the original stmt.  However, such stmts 
++     may have their own uses that are not in any pattern, in such cases the
++     stmt itself should be marked.  */
+   if (STMT_VINFO_IN_PATTERN_P (stmt_info))
+     {
+-      gimple pattern_stmt;
++      bool found = false;
++      if (!used_in_pattern)
++        {
++          imm_use_iterator imm_iter;
++          use_operand_p use_p;
++          gimple use_stmt;
++          tree lhs;
++
++          if (is_gimple_assign (stmt))
++            lhs = gimple_assign_lhs (stmt);
++          else
++            lhs = gimple_call_lhs (stmt);
++
++          /* This use is out of pattern use, if LHS has other uses that are
++             pattern uses, we should mark the stmt itself, and not the pattern
++             stmt.  */
++          FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
++            {
++              if (is_gimple_debug (USE_STMT (use_p)))
++                continue;
++              use_stmt = USE_STMT (use_p);
++
++              if (vinfo_for_stmt (use_stmt)
++                  && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (use_stmt)))
++                {
++                  found = true;
++                  break;
++                }
++            }
++        }
++
++      if (!found)
++        {
++          /* This is the last stmt in a sequence that was detected as a
++             pattern that can potentially be vectorized.  Don't mark the stmt
++             as relevant/live because it's not going to be vectorized.
++             Instead mark the pattern-stmt that replaces it.  */
++
++          pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
+ 
+-      /* This is the last stmt in a sequence that was detected as a
+-         pattern that can potentially be vectorized.  Don't mark the stmt
+-         as relevant/live because it's not going to be vectorized.
+-         Instead mark the pattern-stmt that replaces it.  */
+-
+-      pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
+-
+-      if (vect_print_dump_info (REPORT_DETAILS))
+-        fprintf (vect_dump, "last stmt in pattern. don't mark relevant/live.");
+-      stmt_info = vinfo_for_stmt (pattern_stmt);
+-      gcc_assert (STMT_VINFO_RELATED_STMT (stmt_info) == stmt);
+-      save_relevant = STMT_VINFO_RELEVANT (stmt_info);
+-      save_live_p = STMT_VINFO_LIVE_P (stmt_info);
+-      stmt = pattern_stmt;
++          if (vect_print_dump_info (REPORT_DETAILS))
++            fprintf (vect_dump, "last stmt in pattern. don't mark"
++                                " relevant/live.");
++          stmt_info = vinfo_for_stmt (pattern_stmt);
++          gcc_assert (STMT_VINFO_RELATED_STMT (stmt_info) == stmt);
++          save_relevant = STMT_VINFO_RELEVANT (stmt_info);
++          save_live_p = STMT_VINFO_LIVE_P (stmt_info);
++          stmt = pattern_stmt;
++        }
+     }
+ 
+   STMT_VINFO_LIVE_P (stmt_info) |= live_p;
+@@ -437,7 +476,8 @@
+         }
+     }
+ 
+-  vect_mark_relevant (worklist, def_stmt, relevant, live_p);
++  vect_mark_relevant (worklist, def_stmt, relevant, live_p,
++                      is_pattern_stmt_p (stmt_vinfo));
+   return true;
+ }
+ 
+@@ -494,7 +534,7 @@
+ 	    }
+ 
+ 	  if (vect_stmt_relevant_p (phi, loop_vinfo, &relevant, &live_p))
+-	    vect_mark_relevant (&worklist, phi, relevant, live_p);
++	    vect_mark_relevant (&worklist, phi, relevant, live_p, false);
+ 	}
+       for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
+ 	{
+@@ -506,7 +546,7 @@
+ 	    }
+ 
+ 	  if (vect_stmt_relevant_p (stmt, loop_vinfo, &relevant, &live_p))
+-            vect_mark_relevant (&worklist, stmt, relevant, live_p);
++            vect_mark_relevant (&worklist, stmt, relevant, live_p, false);
+ 	}
+     }
+ 
+@@ -613,42 +653,55 @@
+           if (is_gimple_assign (stmt))
+             {
+               tree rhs = gimple_assign_rhs1 (stmt);
+-              if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
+-                  == GIMPLE_SINGLE_RHS)
++              unsigned int op_num;
++              tree op;
++              switch (get_gimple_rhs_class (gimple_assign_rhs_code (stmt)))
+                 {
+-                  unsigned int op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1
+-                                                              (stmt));
+-                  for (i = 0; i < op_num; i++)
+-                    {
+-                      tree op = TREE_OPERAND (rhs, i);
+-                      if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
+-                                    &worklist))
++                  case GIMPLE_SINGLE_RHS:
++                     op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1 (stmt));
++                     for (i = 0; i < op_num; i++)
+                        {
+-                         VEC_free (gimple, heap, worklist);
+-                         return false;
++                         op = TREE_OPERAND (rhs, i);
++                         if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                           &worklist))
++                           {
++                             VEC_free (gimple, heap, worklist);
++                             return false;
++                           }
+                        }
+-                    }
+-                }
+-              else if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
+-                       == GIMPLE_BINARY_RHS)
+-                {
+-                  tree op = gimple_assign_rhs1 (stmt);
+-                  if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
+-                                    &worklist))
+-                    {
+-                      VEC_free (gimple, heap, worklist);
+-                      return false;
+-                    }
+-                  op = gimple_assign_rhs2 (stmt);
+-                  if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
+-                                    &worklist))
+-                    {
+-                      VEC_free (gimple, heap, worklist);
+-                      return false;
+-                    }
++                    break;
++                   
++                  case GIMPLE_BINARY_RHS:
++                    op = gimple_assign_rhs1 (stmt);
++                    if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                      &worklist))
++                      {
++                        VEC_free (gimple, heap, worklist);
++                        return false;
++                      }
++                    op = gimple_assign_rhs2 (stmt);
++                    if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                      &worklist))
++                      {
++                        VEC_free (gimple, heap, worklist);
++                        return false;
++                      }
++                    break;
++
++                  case GIMPLE_UNARY_RHS:
++                    op = gimple_assign_rhs1 (stmt);
++                    if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                      &worklist))
++                      {
++                        VEC_free (gimple, heap, worklist);
++                        return false;
++                      }
++
++                    break;
++                  
++                  default: 
++                    return false;
+                 }
+-              else
+-                return false;
+             }
+           else if (is_gimple_call (stmt))
+             {
+@@ -1210,7 +1263,14 @@
+ 
+         /* Get the def from the vectorized stmt.  */
+         def_stmt_info = vinfo_for_stmt (def_stmt);
++
+         vec_stmt = STMT_VINFO_VEC_STMT (def_stmt_info);
++        /* Get vectorized pattern statement.  */
++        if (!vec_stmt
++            && STMT_VINFO_IN_PATTERN_P (def_stmt_info)
++            && !STMT_VINFO_RELEVANT (def_stmt_info))
++          vec_stmt = STMT_VINFO_VEC_STMT (vinfo_for_stmt (
++                       STMT_VINFO_RELATED_STMT (def_stmt_info)));
+         gcc_assert (vec_stmt);
+ 	if (gimple_code (vec_stmt) == GIMPLE_PHI)
+ 	  vec_oprnd = PHI_RESULT (vec_stmt);
+@@ -4894,6 +4954,7 @@
+   enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info);
+   bool ok;
+   tree scalar_type, vectype;
++  gimple pattern_stmt;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     {
+@@ -4915,16 +4976,22 @@
+      - any LABEL_EXPRs in the loop
+      - computations that are used only for array indexing or loop control.
+      In basic blocks we only analyze statements that are a part of some SLP
+-     instance, therefore, all the statements are relevant.  */
++     instance, therefore, all the statements are relevant.  
++
++     Pattern statement need to be analyzed instead of the original statement
++     if the original statement is not relevant. Otherwise, we analyze both
++     statements.  */
+ 
++  pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
+   if (!STMT_VINFO_RELEVANT_P (stmt_info)
+       && !STMT_VINFO_LIVE_P (stmt_info))
+     {
+-      gimple pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
+       if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++          && pattern_stmt
+           && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
+               || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
+         {
++          /* Analyze PATTERN_STMT instead of the original stmt.  */
+           stmt = pattern_stmt;
+           stmt_info = vinfo_for_stmt (pattern_stmt);
+           if (vect_print_dump_info (REPORT_DETAILS))
+@@ -4941,6 +5008,21 @@
+           return true;
+         }
+     }
++  else if (STMT_VINFO_IN_PATTERN_P (stmt_info)
++           && pattern_stmt
++           && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
++               || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
++    {
++      /* Analyze PATTERN_STMT too.  */
++      if (vect_print_dump_info (REPORT_DETAILS))
++        {
++          fprintf (vect_dump, "==> examining pattern statement: ");
++          print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++        }
++
++      if (!vect_analyze_stmt (pattern_stmt, need_to_vectorize, node))
++        return false;
++   }
+ 
+   switch (STMT_VINFO_DEF_TYPE (stmt_info))
+     {
+@@ -5074,7 +5156,6 @@
+   bool is_store = false;
+   gimple vec_stmt = NULL;
+   stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
+-  gimple orig_stmt_in_pattern;
+   bool done;
+ 
+   switch (STMT_VINFO_TYPE (stmt_info))
+@@ -5213,21 +5294,7 @@
+     }
+ 
+   if (vec_stmt)
+-    {
+       STMT_VINFO_VEC_STMT (stmt_info) = vec_stmt;
+-      orig_stmt_in_pattern = STMT_VINFO_RELATED_STMT (stmt_info);
+-      if (orig_stmt_in_pattern)
+-	{
+-	  stmt_vec_info stmt_vinfo = vinfo_for_stmt (orig_stmt_in_pattern);
+-	  /* STMT was inserted by the vectorizer to replace a computation idiom.
+-	     ORIG_STMT_IN_PATTERN is a stmt in the original sequence that
+-	     computed this idiom.  We need to record a pointer to VEC_STMT in
+-	     the stmt_info of ORIG_STMT_IN_PATTERN.  See more details in the
+-	     documentation of vect_pattern_recog.  */
+-	  if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
+-	    STMT_VINFO_VEC_STMT (stmt_vinfo) = vec_stmt;
+-	}
+-    }
+ 
+   return is_store;
+ }
+@@ -5605,8 +5672,12 @@
+       || *dt == vect_nested_cycle)
+     {
+       stmt_vec_info stmt_info = vinfo_for_stmt (*def_stmt);
+-      if (STMT_VINFO_IN_PATTERN_P (stmt_info))
++
++      if (STMT_VINFO_IN_PATTERN_P (stmt_info) 
++          && !STMT_VINFO_RELEVANT (stmt_info)
++          && !STMT_VINFO_LIVE_P (stmt_info))
+ 	stmt_info = vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
++
+       *vectype = STMT_VINFO_VECTYPE (stmt_info);
+       gcc_assert (*vectype != NULL_TREE);
+     }
+Index: gcc-4_6-branch/gcc/tree-vectorizer.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vectorizer.h	2012-01-09 15:02:15.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vectorizer.h	2012-01-09 15:03:29.164918806 -0800
+@@ -890,7 +890,7 @@
+ /* Pattern recognition functions.
+    Additional pattern recognition functions can (and will) be added
+    in the future.  */
+-typedef gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
++typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+ #define NUM_PATTERNS 4
+ void vect_pattern_recog (loop_vec_info);
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch
new file mode 100644
index 0000000000..82ae3a1327
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch
@@ -0,0 +1,138 @@
+2011-07-11  Revital Eres  <revital.eres@linaro.org>
+
+	Backport from mainline -r175090.
+	gcc/
+	* ddg.c (add_intra_loop_mem_dep): New function.
+	(build_intra_loop_deps): Call it.
+
+	gcc/testsuite
+	* gcc.dg/sms-9.c: New file.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-05-13 16:03:40 +0000
++++ new/gcc/ddg.c	2011-07-04 11:00:06 +0000
+@@ -390,6 +390,33 @@
+ 			 &PATTERN (insn2));
+ }
+ 
++/* Given two nodes, analyze their RTL insns and add intra-loop mem deps
++   to ddg G.  */
++static void
++add_intra_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
++{
++
++  if ((from->cuid == to->cuid)
++      || !insns_may_alias_p (from->insn, to->insn))
++    /* Do not create edge if memory references have disjoint alias sets
++       or 'to' and 'from' are the same instruction.  */
++    return;
++
++  if (mem_write_insn_p (from->insn))
++    {
++      if (mem_read_insn_p (to->insn))
++	create_ddg_dep_no_link (g, from, to,
++				DEBUG_INSN_P (to->insn)
++				? ANTI_DEP : TRUE_DEP, MEM_DEP, 0);
++      else
++	create_ddg_dep_no_link (g, from, to,
++				DEBUG_INSN_P (to->insn)
++				? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 0);
++    }
++  else if (!mem_read_insn_p (to->insn))
++    create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 0);
++}
++
+ /* Given two nodes, analyze their RTL insns and add inter-loop mem deps
+    to ddg G.  */
+ static void
+@@ -477,10 +504,22 @@
+ 	      if (DEBUG_INSN_P (j_node->insn))
+ 		continue;
+ 	      if (mem_access_insn_p (j_node->insn))
+- 		/* Don't bother calculating inter-loop dep if an intra-loop dep
+-		   already exists.  */
++		{
++		  /* Don't bother calculating inter-loop dep if an intra-loop dep
++		     already exists.  */
+ 	      	  if (! TEST_BIT (dest_node->successors, j))
+ 		    add_inter_loop_mem_dep (g, dest_node, j_node);
++		  /* If -fmodulo-sched-allow-regmoves
++		     is set certain anti-dep edges are not created.
++		     It might be that these anti-dep edges are on the
++		     path from one memory instruction to another such that
++		     removing these edges could cause a violation of the
++		     memory dependencies.  Thus we add intra edges between
++		     every two memory instructions in this case.  */
++		  if (flag_modulo_sched_allow_regmoves
++		      && !TEST_BIT (dest_node->predecessors, j))
++		    add_intra_loop_mem_dep (g, j_node, dest_node);
++		}
+             }
+         }
+     }
+
+=== added file 'gcc/testsuite/gcc.dg/sms-9.c'
+--- old/gcc/testsuite/gcc.dg/sms-9.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/sms-9.c	2011-07-04 11:00:06 +0000
+@@ -0,0 +1,60 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fmodulo-sched -fno-auto-inc-dec -O2 -fmodulo-sched-allow-regmoves" } */
++
++#include <stdlib.h>
++#include <stdarg.h>
++
++struct df_ref_info
++{
++  unsigned int *begin;
++  unsigned int *count;
++};
++
++extern void *memset (void *s, int c, __SIZE_TYPE__ n);
++
++
++__attribute__ ((noinline))
++     int
++     df_reorganize_refs_by_reg_by_insn (struct df_ref_info *ref_info,
++					int num, unsigned int start)
++{
++  unsigned int m = num;
++  unsigned int offset = 77;
++  unsigned int r;
++
++  for (r = start; r < m; r++)
++    {
++      ref_info->begin[r] = offset;
++      offset += ref_info->count[r];
++      ref_info->count[r] = 0;
++    }
++
++  return offset;
++}
++
++int
++main ()
++{
++  struct df_ref_info temp;
++  int num = 100;
++  unsigned int start = 5;
++  int i, offset;
++
++  temp.begin = malloc (100 * sizeof (unsigned int));
++  temp.count = malloc (100 * sizeof (unsigned int));
++
++  memset (temp.begin, 0, sizeof (unsigned int) * num);
++  memset (temp.count, 0, sizeof (unsigned int) * num);
++
++  for (i = 0; i < num; i++)
++    temp.count[i] = i + 1;
++
++  offset = df_reorganize_refs_by_reg_by_insn (&temp, num, start);
++
++  if (offset != 5112)
++    abort ();
++
++  free (temp.begin);
++  free (temp.count);
++  return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch
new file mode 100644
index 0000000000..70c8638cd2
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch
@@ -0,0 +1,211 @@
+2011-07-11  Revital Eres  <revital.eres@linaro.org>
+ 
+	Backport from mainline -r175091
+	gcc/
+	* modulo-sched.c (struct ps_insn): Remove row_rest_count
+	field.
+	(struct partial_schedule): Add rows_length field.
+	(verify_partial_schedule): Check rows_length.
+	(ps_insert_empty_row): Handle rows_length.
+	(create_partial_schedule): Likewise.
+	(free_partial_schedule): Likewise.
+	(reset_partial_schedule): Likewise.
+	(create_ps_insn): Remove rest_count argument.
+	(remove_node_from_ps): Update rows_length.
+	(add_node_to_ps): Update rows_length and call create_ps_insn without
+	passing row_rest_count.
+	(rotate_partial_schedule): Update rows_length.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-05-13 16:03:40 +0000
++++ new/gcc/modulo-sched.c	2011-07-04 12:01:34 +0000
+@@ -134,8 +134,6 @@
+   ps_insn_ptr next_in_row,
+ 	      prev_in_row;
+ 
+-  /* The number of nodes in the same row that come after this node.  */
+-  int row_rest_count;
+ };
+ 
+ /* Holds the partial schedule as an array of II rows.  Each entry of the
+@@ -149,6 +147,12 @@
+   /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii).  */
+   ps_insn_ptr *rows;
+ 
++  /*  rows_length[i] holds the number of instructions in the row.
++      It is used only (as an optimization) to back off quickly from
++      trying to schedule a node in a full row; that is, to avoid running
++      through futile DFA state transitions.  */
++  int *rows_length;
++  
+   /* The earliest absolute cycle of an insn in the partial schedule.  */
+   int min_cycle;
+ 
+@@ -1907,6 +1911,7 @@
+   int ii = ps->ii;
+   int new_ii = ii + 1;
+   int row;
++  int *rows_length_new;
+ 
+   verify_partial_schedule (ps, sched_nodes);
+ 
+@@ -1921,9 +1926,11 @@
+   rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
+ 
+   rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
++  rows_length_new = (int *) xcalloc (new_ii, sizeof (int));
+   for (row = 0; row < split_row; row++)
+     {
+       rows_new[row] = ps->rows[row];
++      rows_length_new[row] = ps->rows_length[row];
+       ps->rows[row] = NULL;
+       for (crr_insn = rows_new[row];
+ 	   crr_insn; crr_insn = crr_insn->next_in_row)
+@@ -1944,6 +1951,7 @@
+   for (row = split_row; row < ii; row++)
+     {
+       rows_new[row + 1] = ps->rows[row];
++      rows_length_new[row + 1] = ps->rows_length[row];
+       ps->rows[row] = NULL;
+       for (crr_insn = rows_new[row + 1];
+ 	   crr_insn; crr_insn = crr_insn->next_in_row)
+@@ -1965,6 +1973,8 @@
+     + (SMODULO (ps->max_cycle, ii) >= split_row ? 1 : 0);
+   free (ps->rows);
+   ps->rows = rows_new;
++  free (ps->rows_length);
++  ps->rows_length = rows_length_new;
+   ps->ii = new_ii;
+   gcc_assert (ps->min_cycle >= 0);
+ 
+@@ -2040,16 +2050,23 @@
+   ps_insn_ptr crr_insn;
+ 
+   for (row = 0; row < ps->ii; row++)
+-    for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
+-      {
+-	ddg_node_ptr u = crr_insn->node;
+-
+-	gcc_assert (TEST_BIT (sched_nodes, u->cuid));
+-	/* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
+-	   popcount (sched_nodes) == number of insns in ps.  */
+-	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+-	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+-      }
++    {
++      int length = 0;
++      
++      for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
++	{
++	  ddg_node_ptr u = crr_insn->node;
++	  
++	  length++;
++	  gcc_assert (TEST_BIT (sched_nodes, u->cuid));
++	  /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
++	     popcount (sched_nodes) == number of insns in ps.  */
++	  gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
++	  gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
++	}
++      
++      gcc_assert (ps->rows_length[row] == length);
++    }
+ }
+ 
+ 
+@@ -2455,6 +2472,7 @@
+ {
+   partial_schedule_ptr ps = XNEW (struct partial_schedule);
+   ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
++  ps->rows_length = (int *) xcalloc (ii, sizeof (int));
+   ps->ii = ii;
+   ps->history = history;
+   ps->min_cycle = INT_MAX;
+@@ -2493,6 +2511,7 @@
+     return;
+   free_ps_insns (ps);
+   free (ps->rows);
++  free (ps->rows_length);
+   free (ps);
+ }
+ 
+@@ -2510,6 +2529,8 @@
+   ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii
+ 						 * sizeof (ps_insn_ptr));
+   memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr));
++  ps->rows_length = (int *) xrealloc (ps->rows_length, new_ii * sizeof (int));
++  memset (ps->rows_length, 0, new_ii * sizeof (int));
+   ps->ii = new_ii;
+   ps->min_cycle = INT_MAX;
+   ps->max_cycle = INT_MIN;
+@@ -2538,14 +2559,13 @@
+ 
+ /* Creates an object of PS_INSN and initializes it to the given parameters.  */
+ static ps_insn_ptr
+-create_ps_insn (ddg_node_ptr node, int rest_count, int cycle)
++create_ps_insn (ddg_node_ptr node, int cycle)
+ {
+   ps_insn_ptr ps_i = XNEW (struct ps_insn);
+ 
+   ps_i->node = node;
+   ps_i->next_in_row = NULL;
+   ps_i->prev_in_row = NULL;
+-  ps_i->row_rest_count = rest_count;
+   ps_i->cycle = cycle;
+ 
+   return ps_i;
+@@ -2578,6 +2598,8 @@
+       if (ps_i->next_in_row)
+ 	ps_i->next_in_row->prev_in_row = ps_i->prev_in_row;
+     }
++   
++  ps->rows_length[row] -= 1; 
+   free (ps_i);
+   return true;
+ }
+@@ -2734,17 +2756,12 @@
+ 		sbitmap must_precede, sbitmap must_follow)
+ {
+   ps_insn_ptr ps_i;
+-  int rest_count = 1;
+   int row = SMODULO (cycle, ps->ii);
+ 
+-  if (ps->rows[row]
+-      && ps->rows[row]->row_rest_count >= issue_rate)
++  if (ps->rows_length[row] >= issue_rate)
+     return NULL;
+ 
+-  if (ps->rows[row])
+-    rest_count += ps->rows[row]->row_rest_count;
+-
+-  ps_i = create_ps_insn (node, rest_count, cycle);
++  ps_i = create_ps_insn (node, cycle);
+ 
+   /* Finds and inserts PS_I according to MUST_FOLLOW and
+      MUST_PRECEDE.  */
+@@ -2754,6 +2771,7 @@
+       return NULL;
+     }
+ 
++  ps->rows_length[row] += 1;
+   return ps_i;
+ }
+ 
+@@ -2909,11 +2927,16 @@
+   for (i = 0; i < backward_rotates; i++)
+     {
+       ps_insn_ptr first_row = ps->rows[0];
++      int first_row_length = ps->rows_length[0];
+ 
+       for (row = 0; row < last_row; row++)
+-	ps->rows[row] = ps->rows[row+1];
++	{
++	  ps->rows[row] = ps->rows[row + 1];
++	  ps->rows_length[row] = ps->rows_length[row + 1]; 
++	}
+ 
+       ps->rows[last_row] = first_row;
++      ps->rows_length[last_row] = first_row_length;
+     }
+ 
+   ps->max_cycle -= start_cycle;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch
new file mode 100644
index 0000000000..d918f9c58c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch
@@ -0,0 +1,350 @@
+2011-07-11  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+	2011-06-22  Dmitry Plotnikov  <dplotnikov@ispras.ru>
+	Dmitry Melnik  <dm@ispras.ru>
+
+	* config/arm/arm.c (neon_immediate_valid_for_shift): New function.
+	(neon_output_shift_immediate): Ditto.
+	* config/arm/arm-protos.h (neon_immediate_valid_for_shift): New
+	prototype.
+	(neon_output_shift_immediate): Ditto.
+	* config/arm/neon.md (vashl<mode>3): Modified constraint.
+	(vashr<mode>3_imm): New insn pattern.
+	(vlshr<mode>3_imm): Ditto.
+	(vashr<mode>3): Modified constraint.
+	(vlshr<mode>3): Ditto.
+	* config/arm/predicates.md (imm_for_neon_lshift_operand): New
+	predicate.
+	(imm_for_neon_rshift_operand): Ditto.
+	(imm_lshift_or_reg_neon): Ditto.
+	(imm_rshift_or_reg_neon): Ditto.
+
+	* optabs.c (init_optabs): Init optab codes for vashl, vashr, vlshr.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-06-14 16:00:30 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-07-04 14:03:49 +0000
+@@ -64,8 +64,12 @@
+ extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
+ extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
+ 					   int *);
++extern int neon_immediate_valid_for_shift (rtx, enum machine_mode, rtx *,
++					   int *, bool);
+ extern char *neon_output_logic_immediate (const char *, rtx *,
+ 					  enum machine_mode, int, int);
++extern char *neon_output_shift_immediate (const char *, char, rtx *,
++					  enum machine_mode, int, bool);
+ extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode,
+ 				  rtx (*) (rtx, rtx, rtx));
+ extern rtx neon_make_constant (rtx);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-06-29 09:13:17 +0000
++++ new/gcc/config/arm/arm.c	2011-07-04 14:03:49 +0000
+@@ -8863,6 +8863,66 @@
+   return 1;
+ }
+ 
++/* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction.  If
++   the immediate is valid, write a constant suitable for using as an operand
++   to VSHR/VSHL to *MODCONST and the corresponding element width to
++   *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
++   because they have different limitations.  */
++
++int
++neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
++				rtx *modconst, int *elementwidth,
++				bool isleftshift)
++{
++  unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
++  unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
++  unsigned HOST_WIDE_INT last_elt = 0;
++  unsigned HOST_WIDE_INT maxshift;
++
++  /* Split vector constant out into a byte vector.  */
++  for (i = 0; i < n_elts; i++)
++    {
++      rtx el = CONST_VECTOR_ELT (op, i);
++      unsigned HOST_WIDE_INT elpart;
++
++      if (GET_CODE (el) == CONST_INT)
++        elpart = INTVAL (el);
++      else if (GET_CODE (el) == CONST_DOUBLE)
++        return 0;
++      else
++        gcc_unreachable ();
++
++      if (i != 0 && elpart != last_elt)
++        return 0;
++
++      last_elt = elpart;
++    }
++
++  /* Shift less than element size.  */
++  maxshift = innersize * 8;
++
++  if (isleftshift)
++    {
++      /* Left shift immediate value can be from 0 to <size>-1.  */
++      if (last_elt >= maxshift)
++        return 0;
++    }
++  else
++    {
++      /* Right shift immediate value can be from 1 to <size>.  */
++      if (last_elt == 0 || last_elt > maxshift)
++	return 0;
++    }
++
++  if (elementwidth)
++    *elementwidth = innersize * 8;
++
++  if (modconst)
++    *modconst = CONST_VECTOR_ELT (op, 0);
++
++  return 1;
++}
++
+ /* Return a string suitable for output of Neon immediate logic operation
+    MNEM.  */
+ 
+@@ -8885,6 +8945,28 @@
+   return templ;
+ }
+ 
++/* Return a string suitable for output of Neon immediate shift operation
++   (VSHR or VSHL) MNEM.  */
++
++char *
++neon_output_shift_immediate (const char *mnem, char sign, rtx *op2,
++			     enum machine_mode mode, int quad,
++			     bool isleftshift)
++{
++  int width, is_valid;
++  static char templ[40];
++
++  is_valid = neon_immediate_valid_for_shift (*op2, mode, op2, &width, isleftshift);
++  gcc_assert (is_valid != 0);
++
++  if (quad)
++    sprintf (templ, "%s.%c%d\t%%q0, %%q1, %%2", mnem, sign, width);
++  else
++    sprintf (templ, "%s.%c%d\t%%P0, %%P1, %%2", mnem, sign, width);
++
++  return templ;
++}
++
+ /* Output a sequence of pairwise operations to implement a reduction.
+    NOTE: We do "too much work" here, because pairwise operations work on two
+    registers-worth of operands in one go. Unfortunately we can't exploit those
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2011-07-01 09:19:21 +0000
++++ new/gcc/config/arm/neon.md	2011-07-04 14:03:49 +0000
+@@ -956,15 +956,57 @@
+ ; SImode elements.
+ 
+ (define_insn "vashl<mode>3"
+-  [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+-	(ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
+-		      (match_operand:VDQIW 2 "s_register_operand" "w")))]
+-  "TARGET_NEON"
+-  "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+-  [(set (attr "neon_type")
+-      (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+-                    (const_string "neon_vshl_ddd")
+-                    (const_string "neon_shift_3")))]
++  [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
++	(ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w")
++		      (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dn")))]
++  "TARGET_NEON"
++  {
++    switch (which_alternative)
++      {
++        case 0: return "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2";
++        case 1: return neon_output_shift_immediate ("vshl", 'i', &operands[2],
++                         			    <MODE>mode,
++						    VALID_NEON_QREG_MODE (<MODE>mode),
++						    true);
++        default: gcc_unreachable ();
++      }
++  }
++  [(set (attr "neon_type")
++      (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++                    (const_string "neon_vshl_ddd")
++                    (const_string "neon_shift_3")))]
++)
++
++(define_insn "vashr<mode>3_imm"
++  [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
++	(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
++			(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
++  "TARGET_NEON"
++  {
++    return neon_output_shift_immediate ("vshr", 's', &operands[2],
++					<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
++					false);
++  }
++  [(set (attr "neon_type")
++      (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++                    (const_string "neon_vshl_ddd")
++                    (const_string "neon_shift_3")))]
++)
++
++(define_insn "vlshr<mode>3_imm"
++  [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
++	(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
++			(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
++  "TARGET_NEON"
++  {
++    return neon_output_shift_immediate ("vshr", 'u', &operands[2],
++					<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
++					false);
++  }              
++  [(set (attr "neon_type")
++	(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++		      (const_string "neon_vshl_ddd")
++		      (const_string "neon_shift_3")))]
+ )
+ 
+ ; Used for implementing logical shift-right, which is a left-shift by a negative
+@@ -1004,28 +1046,34 @@
+ (define_expand "vashr<mode>3"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "")
+ 	(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
+-			(match_operand:VDQIW 2 "s_register_operand" "")))]
++			(match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
+   "TARGET_NEON"
+ {
+   rtx neg = gen_reg_rtx (<MODE>mode);
+-
+-  emit_insn (gen_neg<mode>2 (neg, operands[2]));
+-  emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
+-
++  if (REG_P (operands[2]))
++    {
++      emit_insn (gen_neg<mode>2 (neg, operands[2]));
++      emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
++    }
++  else
++    emit_insn (gen_vashr<mode>3_imm (operands[0], operands[1], operands[2]));
+   DONE;
+ })
+ 
+ (define_expand "vlshr<mode>3"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "")
+ 	(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
+-			(match_operand:VDQIW 2 "s_register_operand" "")))]
++			(match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
+   "TARGET_NEON"
+ {
+   rtx neg = gen_reg_rtx (<MODE>mode);
+-
+-  emit_insn (gen_neg<mode>2 (neg, operands[2]));
+-  emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
+-
++  if (REG_P (operands[2]))
++    {
++      emit_insn (gen_neg<mode>2 (neg, operands[2]));
++      emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
++    }
++  else
++    emit_insn (gen_vlshr<mode>3_imm (operands[0], operands[1], operands[2]));
+   DONE;
+ })
+ 
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-06-22 15:50:23 +0000
++++ new/gcc/config/arm/predicates.md	2011-07-04 14:03:49 +0000
+@@ -585,6 +585,26 @@
+   return neon_immediate_valid_for_move (op, mode, NULL, NULL);
+ })
+ 
++(define_predicate "imm_for_neon_lshift_operand"
++  (match_code "const_vector")
++{
++  return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
++})
++
++(define_predicate "imm_for_neon_rshift_operand"
++  (match_code "const_vector")
++{
++  return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
++})
++
++(define_predicate "imm_lshift_or_reg_neon"
++  (ior (match_operand 0 "s_register_operand")
++       (match_operand 0 "imm_for_neon_lshift_operand")))
++
++(define_predicate "imm_rshift_or_reg_neon"
++  (ior (match_operand 0 "s_register_operand")
++       (match_operand 0 "imm_for_neon_rshift_operand")))
++
+ (define_predicate "imm_for_neon_logic_operand"
+   (match_code "const_vector")
+ {
+
+=== modified file 'gcc/optabs.c'
+--- old/gcc/optabs.c	2011-03-04 10:27:10 +0000
++++ new/gcc/optabs.c	2011-07-04 14:03:49 +0000
+@@ -6171,6 +6171,9 @@
+   init_optab (usashl_optab, US_ASHIFT);
+   init_optab (ashr_optab, ASHIFTRT);
+   init_optab (lshr_optab, LSHIFTRT);
++  init_optabv (vashl_optab, ASHIFT);
++  init_optabv (vashr_optab, ASHIFTRT);
++  init_optabv (vlshr_optab, LSHIFTRT);
+   init_optab (rotl_optab, ROTATE);
+   init_optab (rotr_optab, ROTATERT);
+   init_optab (smin_optab, SMIN);
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c	2011-07-04 14:03:49 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
++/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */
++
++/* Verify that VSHR immediate is used.  */
++void f1(int n, unsigned int x[], unsigned int y[]) {
++  int i;
++  for (i = 0; i < n; ++i)
++    y[i] = x[i] >> 3;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c	2011-07-04 14:03:49 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
++/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
++
++/* Verify that VSHR immediate is used.  */
++void f1(int n, int x[], int y[]) {
++  int i;
++  for (i = 0; i < n; ++i)
++    y[i] = x[i] << 3;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c	2011-07-04 14:03:49 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
++/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */
++
++/* Verify that VSHR immediate is used.  */
++void f1(int n, int x[], int y[]) {
++  int i;
++  for (i = 0; i < n; ++i)
++    y[i] = x[i] >> 3;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch
new file mode 100644
index 0000000000..de3f29e193
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch
@@ -0,0 +1,119 @@
+2011-07-13  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	Backport from mainline:
+	gcc/
+	2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* reload1.c (choose_reload_regs): Use mode sizes to check whether
+	an old reload register completely defines the required value.
+
+	gcc/testsuite/
+	2011-07-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/arm/neon-modes-3.c: New test.
+
+=== modified file 'gcc/reload1.c'
+--- old/gcc/reload1.c	2011-07-01 09:19:21 +0000
++++ new/gcc/reload1.c	2011-07-11 10:06:50 +0000
+@@ -6451,6 +6451,8 @@
+ 
+ 	      if (regno >= 0
+ 		  && reg_last_reload_reg[regno] != 0
++		  && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
++		      >= GET_MODE_SIZE (mode) + byte)
+ #ifdef CANNOT_CHANGE_MODE_CLASS
+ 		  /* Verify that the register it's in can be used in
+ 		     mode MODE.  */
+@@ -6462,24 +6464,12 @@
+ 		{
+ 		  enum reg_class rclass = rld[r].rclass, last_class;
+ 		  rtx last_reg = reg_last_reload_reg[regno];
+-		  enum machine_mode need_mode;
+ 
+ 		  i = REGNO (last_reg);
+ 		  i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
+ 		  last_class = REGNO_REG_CLASS (i);
+ 
+-		  if (byte == 0)
+-		    need_mode = mode;
+-		  else
+-		    need_mode
+-		      = smallest_mode_for_size
+-		        (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
+-			 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
+-			 ? MODE_INT : GET_MODE_CLASS (mode));
+-
+-		  if ((GET_MODE_SIZE (GET_MODE (last_reg))
+-		       >= GET_MODE_SIZE (need_mode))
+-		      && reg_reloaded_contents[i] == regno
++		  if (reg_reloaded_contents[i] == regno
+ 		      && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
+ 		      && HARD_REGNO_MODE_OK (i, rld[r].mode)
+ 		      && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-3.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-modes-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-modes-3.c	2011-07-11 10:06:50 +0000
+@@ -0,0 +1,61 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n)
++{
++  float32x4x4_t a5, a6, a7, a8, a9;
++  int i;
++
++  a5 = *src;
++  a6 = *src;
++  a7 = *src;
++  a8 = *src;
++  a9 = *src;
++  while (n--)
++    {
++      for (i = 0; i < 8; i++)
++	{
++	  float32x4x4_t a0, a1, a2, a3, a4;
++
++	  a0 = *src;
++	  a1 = *src;
++	  a2 = *src;
++	  a3 = *src;
++	  a4 = *src;
++	  *src = a0;
++	  *dest = a0.val[0];
++	  *dest = a0.val[3];
++	  *src = a1;
++	  *dest = a1.val[0];
++	  *dest = a1.val[3];
++	  *src = a2;
++	  *dest = a2.val[0];
++	  *dest = a2.val[3];
++	  *src = a3;
++	  *dest = a3.val[0];
++	  *dest = a3.val[3];
++	  *src = a4;
++	  *dest = a4.val[0];
++	  *dest = a4.val[3];
++	}
++      *src = a5;
++      *dest = a5.val[0];
++      *dest = a5.val[3];
++      *src = a6;
++      *dest = a6.val[0];
++      *dest = a6.val[3];
++      *src = a7;
++      *dest = a7.val[0];
++      *dest = a7.val[3];
++      *src = a8;
++      *dest = a8.val[0];
++      *dest = a8.val[3];
++      *src = a9;
++      *dest = a9.val[0];
++      *dest = a9.val[3];
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch
new file mode 100644
index 0000000000..0b05c38240
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch
@@ -0,0 +1,67 @@
+2011-07-15  Michael Hope  <michael.hope@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-05  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* ifcvt.c (cond_exec_process_insns): Disallow converting a block
+	that contains the prologue.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-04-01  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* gcc.c-torture/compile/20110401-1.c: New test.
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c	2010-12-14 00:23:40 +0000
++++ new/gcc/ifcvt.c	2011-07-11 04:02:28 +0000
+@@ -1,5 +1,6 @@
+ /* If-conversion support.
+-   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
++   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010,
++   2011
+    Free Software Foundation, Inc.
+ 
+    This file is part of GCC.
+@@ -304,6 +305,10 @@
+ 
+   for (insn = start; ; insn = NEXT_INSN (insn))
+     {
++      /* dwarf2out can't cope with conditional prologues.  */
++      if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
++	return FALSE;
++
+       if (NOTE_P (insn) || DEBUG_INSN_P (insn))
+ 	goto insn_done;
+ 
+
+=== added file 'gcc/testsuite/gcc.c-torture/compile/20110401-1.c'
+--- old/gcc/testsuite/gcc.c-torture/compile/20110401-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.c-torture/compile/20110401-1.c	2011-07-11 04:02:28 +0000
+@@ -0,0 +1,22 @@
++void asn1_length_der (unsigned long int len, unsigned char *ans, int *ans_len)
++{
++    int k;
++    unsigned char temp[4];
++    if (len < 128) {
++	if (ans != ((void *) 0))
++	    ans[0] = (unsigned char) len;
++	*ans_len = 1;
++    } else {
++	k = 0;
++	while (len) {
++	    temp[k++] = len & 0xFF;
++	    len = len >> 8;
++	}
++	*ans_len = k + 1;
++	if (ans != ((void *) 0)) {
++	    ans[0] = ((unsigned char) k & 0x7F) + 128;
++	    while (k--)
++		ans[*ans_len - 1 - k] = temp[k];
++	}
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch
new file mode 100644
index 0000000000..3d4d5c5049
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch
@@ -0,0 +1,46 @@
+2011-07-15  Michael Hope  <michael.hope@linaro.org>
+
+	gcc/
+	Backport from mainline:
+	2011-03-22  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* combine.c (simplify_set): Try harder to find the best CC mode when
+	simplifying a nested COMPARE on the RHS.
+
+=== modified file 'gcc/combine.c'
+--- old/gcc/combine.c	2011-05-27 14:31:18 +0000
++++ new/gcc/combine.c	2011-07-11 03:52:31 +0000
+@@ -6287,10 +6287,18 @@
+       enum rtx_code new_code;
+       rtx op0, op1, tmp;
+       int other_changed = 0;
++      rtx inner_compare = NULL_RTX;
+       enum machine_mode compare_mode = GET_MODE (dest);
+ 
+       if (GET_CODE (src) == COMPARE)
+-	op0 = XEXP (src, 0), op1 = XEXP (src, 1);
++	{
++	  op0 = XEXP (src, 0), op1 = XEXP (src, 1);
++	  if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
++	    {
++	      inner_compare = op0;
++	      op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
++	    }
++	}
+       else
+ 	op0 = src, op1 = CONST0_RTX (GET_MODE (src));
+ 
+@@ -6332,6 +6340,12 @@
+ 	 need to use a different CC mode here.  */
+       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
+ 	compare_mode = GET_MODE (op0);
++      else if (inner_compare
++	       && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
++	       && new_code == old_code
++	       && op0 == XEXP (inner_compare, 0)
++	       && op1 == XEXP (inner_compare, 1))
++	compare_mode = GET_MODE (inner_compare);
+       else
+ 	compare_mode = SELECT_CC_MODE (new_code, op0, op1);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch
new file mode 100644
index 0000000000..68b682b3c6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch
@@ -0,0 +1,192 @@
+2011-07-15  Michael Hope  <michael.hope@linaro.org>
+
+	gcc/
+	Backport from mainline:
+	2011-06-29  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/arm/unwind-arm.c (enum __cxa_type_match_result): New.
+	(cxa_type_match): Correct declaration.
+	(__gnu_unwind_pr_common): Reconstruct
+	additional indirection when __cxa_type_match returns
+	succeeded_with_ptr_to_base.
+
+	libstdc++-v3/
+	Backport from mainline:
+
+	2011-06-29  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* libsupc++/eh_arm.c (__cxa_type_match): Construct address of
+	thrown object here.  Return succeded_with_ptr_to_base for all
+	pointer cases.
+
+=== modified file 'gcc/config/arm/unwind-arm.c'
+--- old/gcc/config/arm/unwind-arm.c	2011-03-22 10:59:10 +0000
++++ new/gcc/config/arm/unwind-arm.c	2011-07-11 03:35:44 +0000
+@@ -32,13 +32,18 @@
+ typedef unsigned char bool;
+ 
+ typedef struct _ZSt9type_info type_info; /* This names C++ type_info type */
++enum __cxa_type_match_result
++  {
++    ctm_failed = 0,
++    ctm_succeeded = 1,
++    ctm_succeeded_with_ptr_to_base = 2
++  };
+ 
+ void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp);
+ bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp);
+-bool __attribute__((weak)) __cxa_type_match(_Unwind_Control_Block *ucbp,
+-					    const type_info *rttip,
+-					    bool is_reference,
+-					    void **matched_object);
++enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match
++  (_Unwind_Control_Block *ucbp, const type_info *rttip,
++   bool is_reference, void **matched_object);
+ 
+ _Unwind_Ptr __attribute__((weak))
+ __gnu_Unwind_Find_exidx (_Unwind_Ptr, int *);
+@@ -1107,6 +1112,7 @@
+ 		      _uw rtti;
+ 		      bool is_reference = (data[0] & uint32_highbit) != 0;
+ 		      void *matched;
++		      enum __cxa_type_match_result match_type;
+ 
+ 		      /* Check for no-throw areas.  */
+ 		      if (data[1] == (_uw) -2)
+@@ -1118,17 +1124,31 @@
+ 			{
+ 			  /* Match a catch specification.  */
+ 			  rtti = _Unwind_decode_target2 ((_uw) &data[1]);
+-			  if (!__cxa_type_match (ucbp, (type_info *) rtti,
+-						 is_reference,
+-						 &matched))
+-			    matched = (void *)0;
++			  match_type = __cxa_type_match (ucbp,
++							 (type_info *) rtti,
++							 is_reference,
++							 &matched);
+ 			}
++		      else
++			match_type = ctm_succeeded;
+ 
+-		      if (matched)
++		      if (match_type)
+ 			{
+ 			  ucbp->barrier_cache.sp =
+ 			    _Unwind_GetGR (context, R_SP);
+-			  ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
++			  // ctm_succeeded_with_ptr_to_base really
++			  // means _c_t_m indirected the pointer
++			  // object.  We have to reconstruct the
++			  // additional pointer layer by using a temporary.
++			  if (match_type == ctm_succeeded_with_ptr_to_base)
++			    {
++			      ucbp->barrier_cache.bitpattern[2]
++				= (_uw) matched;
++			      ucbp->barrier_cache.bitpattern[0]
++				= (_uw) &ucbp->barrier_cache.bitpattern[2];
++			    }
++			  else
++			    ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
+ 			  ucbp->barrier_cache.bitpattern[1] = (_uw) data;
+ 			  return _URC_HANDLER_FOUND;
+ 			}
+
+=== modified file 'libstdc++-v3/libsupc++/eh_arm.cc'
+--- old/libstdc++-v3/libsupc++/eh_arm.cc	2011-01-03 20:52:22 +0000
++++ new/libstdc++-v3/libsupc++/eh_arm.cc	2011-07-11 03:35:44 +0000
+@@ -30,10 +30,11 @@
+ using namespace __cxxabiv1;
+ 
+ 
+-// Given the thrown type THROW_TYPE, pointer to a variable containing a
+-// pointer to the exception object THROWN_PTR_P and a type CATCH_TYPE to
+-// compare against, return whether or not there is a match and if so,
+-// update *THROWN_PTR_P.
++// Given the thrown type THROW_TYPE, exception object UE_HEADER and a
++// type CATCH_TYPE to compare against, return whether or not there is
++// a match and if so, update *THROWN_PTR_P to point to either the
++// type-matched object, or in the case of a pointer type, the object
++// pointed to by the pointer.
+ 
+ extern "C" __cxa_type_match_result
+ __cxa_type_match(_Unwind_Exception* ue_header,
+@@ -41,51 +42,51 @@
+ 		 bool is_reference __attribute__((__unused__)),
+ 		 void** thrown_ptr_p)
+ {
+-  bool forced_unwind = __is_gxx_forced_unwind_class(ue_header->exception_class);
+-  bool foreign_exception = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
+-  bool dependent_exception =
+-    __is_dependent_exception(ue_header->exception_class);
++  bool forced_unwind
++    = __is_gxx_forced_unwind_class(ue_header->exception_class);
++  bool foreign_exception
++    = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
++  bool dependent_exception
++    = __is_dependent_exception(ue_header->exception_class);
+   __cxa_exception* xh = __get_exception_header_from_ue(ue_header);
+   __cxa_dependent_exception *dx = __get_dependent_exception_from_ue(ue_header);
+   const std::type_info* throw_type;
++  void *thrown_ptr = 0;
+ 
+   if (forced_unwind)
+     throw_type = &typeid(abi::__forced_unwind);
+   else if (foreign_exception)
+     throw_type = &typeid(abi::__foreign_exception);
+-  else if (dependent_exception)
+-    throw_type = __get_exception_header_from_obj
+-      (dx->primaryException)->exceptionType;
+   else
+-    throw_type = xh->exceptionType;
+-
+-  void* thrown_ptr = *thrown_ptr_p;
++    {
++      if (dependent_exception)
++	xh = __get_exception_header_from_obj (dx->primaryException);
++      throw_type = xh->exceptionType;
++      // We used to require the caller set the target of thrown_ptr_p,
++      // but that's incorrect -- the EHABI makes no such requirement
++      // -- and not all callers will set it.  Fortunately callers that
++      // do initialize will always pass us the value we calculate
++      // here, so there's no backwards compatibility problem.
++      thrown_ptr = __get_object_from_ue (ue_header);
++    }
++  
++  __cxa_type_match_result result = ctm_succeeded;
+ 
+   // Pointer types need to adjust the actual pointer, not
+   // the pointer to pointer that is the exception object.
+   // This also has the effect of passing pointer types
+   // "by value" through the __cxa_begin_catch return value.
+   if (throw_type->__is_pointer_p())
+-    thrown_ptr = *(void**) thrown_ptr;
++    {
++      thrown_ptr = *(void**) thrown_ptr;
++      // We need to indicate the indirection to our caller.
++      result = ctm_succeeded_with_ptr_to_base;
++    }
+ 
+   if (catch_type->__do_catch(throw_type, &thrown_ptr, 1))
+     {
+       *thrown_ptr_p = thrown_ptr;
+-
+-      if (typeid(*catch_type) == typeid (typeid(void*)))
+-	{
+-	  const __pointer_type_info *catch_pointer_type =
+-	    static_cast<const __pointer_type_info *> (catch_type);
+-	  const __pointer_type_info *throw_pointer_type =
+-	    static_cast<const __pointer_type_info *> (throw_type);
+-
+-	  if (typeid (*catch_pointer_type->__pointee) != typeid (void)
+-	      && (*catch_pointer_type->__pointee != 
+-		  *throw_pointer_type->__pointee))
+-	    return ctm_succeeded_with_ptr_to_base;
+-	}
+-
+-      return ctm_succeeded;
++      return result;
+     }
+ 
+   return ctm_failed;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch
new file mode 100644
index 0000000000..b42b425dc1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch
@@ -0,0 +1,225 @@
+2011-07-15  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r174540
+	LP: #807573
+
+	gcc/
+	2011-06-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	PR rtl-optimization/48830
+	PR rtl-optimization/48808
+	PR rtl-optimization/48792
+	* reload.c (push_reload): Check contains_reg_of_mode.
+	* reload1.c (strip_paradoxical_subreg): New function.
+	(gen_reload_chain_without_interm_reg_p): Use it to handle
+	paradoxical subregs.
+	(emit_output_reload_insns, gen_reload): Likewise.
+
+	gcc/testsuite/
+	2011-06-01  Eric Botcazou  <ebotcazou@adacore.com>
+		    Hans-Peter Nilsson  <hp@axis.com>
+
+	PR rtl-optimization/48830
+	* gcc.target/sparc/ultrasp12.c: New test.
+
+=== modified file 'gcc/reload.c'
+--- old/gcc/reload.c	2011-07-01 09:19:21 +0000
++++ new/gcc/reload.c	2011-07-13 02:09:08 +0000
+@@ -1017,6 +1017,7 @@
+ #ifdef CANNOT_CHANGE_MODE_CLASS
+       && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, rclass)
+ #endif
++      && contains_reg_of_mode[(int) rclass][(int) GET_MODE (SUBREG_REG (in))]
+       && (CONSTANT_P (SUBREG_REG (in))
+ 	  || GET_CODE (SUBREG_REG (in)) == PLUS
+ 	  || strict_low
+@@ -1123,6 +1124,7 @@
+ #ifdef CANNOT_CHANGE_MODE_CLASS
+       && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, rclass)
+ #endif
++      && contains_reg_of_mode[(int) rclass][(int) GET_MODE (SUBREG_REG (out))]
+       && (CONSTANT_P (SUBREG_REG (out))
+ 	  || strict_low
+ 	  || (((REG_P (SUBREG_REG (out))
+
+=== modified file 'gcc/reload1.c'
+--- old/gcc/reload1.c	2011-07-11 10:06:50 +0000
++++ new/gcc/reload1.c	2011-07-14 22:14:45 +0000
+@@ -4476,6 +4476,43 @@
+ 	}
+     }
+ }
++
++/* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
++   If *OP_PTR is a paradoxical subreg, try to remove that subreg
++   and apply the corresponding narrowing subreg to *OTHER_PTR.
++   Return true if the operands were changed, false otherwise.  */
++
++static bool
++strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
++{
++  rtx op, inner, other, tem;
++
++  op = *op_ptr;
++  if (GET_CODE (op) != SUBREG)
++    return false;
++
++  inner = SUBREG_REG (op);
++  if (GET_MODE_SIZE (GET_MODE (op)) <= GET_MODE_SIZE (GET_MODE (inner)))
++    return false;
++
++  other = *other_ptr;
++  tem = gen_lowpart_common (GET_MODE (inner), other);
++  if (!tem)
++    return false;
++
++  /* If the lowpart operation turned a hard register into a subreg,
++     rather than simplifying it to another hard register, then the
++     mode change cannot be properly represented.  For example, OTHER
++     might be valid in its current mode, but not in the new one.  */
++  if (GET_CODE (tem) == SUBREG
++      && REG_P (other)
++      && HARD_REGISTER_P (other))
++    return false;
++
++  *op_ptr = inner;
++  *other_ptr = tem;
++  return true;
++}
+ 
+ /* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
+    examine all of the reload insns between PREV and NEXT exclusive, and
+@@ -5556,7 +5593,7 @@
+      chain reloads or do need an intermediate hard registers.  */
+   bool result = true;
+   int regno, n, code;
+-  rtx out, in, tem, insn;
++  rtx out, in, insn;
+   rtx last = get_last_insn ();
+ 
+   /* Make r2 a component of r1.  */
+@@ -5575,11 +5612,7 @@
+ 
+   /* If IN is a paradoxical SUBREG, remove it and try to put the
+      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
+-  if (GET_CODE (in) == SUBREG
+-      && (GET_MODE_SIZE (GET_MODE (in))
+-	  > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
+-      && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
+-    in = SUBREG_REG (in), out = tem;
++  strip_paradoxical_subreg (&in, &out);
+ 
+   if (GET_CODE (in) == PLUS
+       && (REG_P (XEXP (in, 0))
+@@ -7571,7 +7604,6 @@
+ 	      if (tertiary_icode != CODE_FOR_nothing)
+ 		{
+ 		  rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
+-		  rtx tem;
+ 
+ 		  /* Copy primary reload reg to secondary reload reg.
+ 		     (Note that these have been swapped above, then
+@@ -7580,13 +7612,7 @@
+ 		  /* If REAL_OLD is a paradoxical SUBREG, remove it
+ 		     and try to put the opposite SUBREG on
+ 		     RELOADREG.  */
+-		  if (GET_CODE (real_old) == SUBREG
+-		      && (GET_MODE_SIZE (GET_MODE (real_old))
+-			  > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
+-		      && 0 != (tem = gen_lowpart_common
+-			       (GET_MODE (SUBREG_REG (real_old)),
+-				reloadreg)))
+-		    real_old = SUBREG_REG (real_old), reloadreg = tem;
++		  strip_paradoxical_subreg (&real_old, &reloadreg);
+ 
+ 		  gen_reload (reloadreg, second_reloadreg,
+ 			      rl->opnum, rl->when_needed);
+@@ -8402,16 +8428,8 @@
+ 
+   /* If IN is a paradoxical SUBREG, remove it and try to put the
+      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
+-  if (GET_CODE (in) == SUBREG
+-      && (GET_MODE_SIZE (GET_MODE (in))
+-	  > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
+-      && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
+-    in = SUBREG_REG (in), out = tem;
+-  else if (GET_CODE (out) == SUBREG
+-	   && (GET_MODE_SIZE (GET_MODE (out))
+-	       > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
+-	   && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
+-    out = SUBREG_REG (out), in = tem;
++  if (!strip_paradoxical_subreg (&in, &out))
++    strip_paradoxical_subreg (&out, &in);
+ 
+   /* How to do this reload can get quite tricky.  Normally, we are being
+      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
+
+=== added file 'gcc/testsuite/gcc.target/sparc/ultrasp12.c'
+--- old/gcc/testsuite/gcc.target/sparc/ultrasp12.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/sparc/ultrasp12.c	2011-07-13 02:09:08 +0000
+@@ -0,0 +1,64 @@
++/* PR rtl-optimization/48830 */
++/* Testcase by Hans-Peter Nilsson <hp@gcc.gnu.org> */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target lp64 } */
++/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
++
++typedef unsigned char uint8_t;
++typedef unsigned int uint32_t;
++typedef unsigned long int uint64_t;
++typedef unsigned long int uintmax_t;
++typedef unsigned char rc_vec_t __attribute__((__vector_size__(8)));
++typedef short rc_svec_type_ __attribute__((__vector_size__(8)));
++typedef unsigned char rc_vec4_type_ __attribute__((__vector_size__(4)));
++
++void
++rc_stat_xsum_acc(const uint8_t *__restrict src1, int src1_dim,
++                 const uint8_t *__restrict src2, int src2_dim,
++                 int len, int height, uintmax_t sum[5])
++{
++    uint32_t s1 = 0;
++    uint32_t s2 = 0;
++    uintmax_t s11 = 0;
++    uintmax_t s22 = 0;
++    uintmax_t s12 = 0;
++    int full = len / ((1024) < (1024) ? (1024) : (1024));
++    int rem = len % ((1024) < (1024) ? (1024) : (1024));
++    int rem1 = rem / 1;
++    int y;
++    unsigned int rc_gsr_scale_ __attribute__ ((__unused__)) = 7; unsigned int rc_gsr_align_ __attribute__ ((__unused__)) = 4; unsigned int rc_gsr_set_ __attribute__ ((__unused__)) = 0; register unsigned int rc_gsr_fakedep_ __attribute__ ((__unused__)) = 0; unsigned int rc_gsr_ldinit_ __attribute__ ((__unused__)) = 0;
++    for (y = 0; y < height; y++) {
++        rc_vec_t a1, a2, a11, a22, a12;
++        int i1 = (y)*(src1_dim);
++        int i2 = (y)*(src2_dim);
++        int x;
++        ((a1) = ((rc_vec_t) {0}));
++        ((a2) = ((rc_vec_t) {0}));
++        ((a11) = ((rc_vec_t) {0}));
++        ((a22) = ((rc_vec_t) {0}));
++        ((a12) = ((rc_vec_t) {0}));
++        for (x = 0; x < full; x++) {
++            int k;
++            for (k = 0; k < ((1024) < (1024) ? (1024) : (1024)) /
++                            1; k++)
++            {
++                do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0);
++
++            }
++            do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
++        }
++        for (x = 0; x < rem1; x++) {
++            do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0);
++        }
++        do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
++
++        do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
++    }
++    sum[0] = s1;
++    sum[1] = s2;
++    sum[2] = s11;
++    sum[3] = s22;
++    sum[4] = s12;
++    ;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch
new file mode 100644
index 0000000000..a86ddfdec0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch
@@ -0,0 +1,741 @@
+2011-07-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	PR middle-end/49736
+	* expr.c (all_zeros_p): Undo bogus part of last change.
+
+2011-07-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	Backport from mainline:
+	gcc/cp/
+	2011-07-13  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* typeck2.c (split_nonconstant_init_1): Pass the initializer directly,
+	rather than a pointer to it.  Return true if the whole of the value
+	was initialized by the generated statements.  Use
+	complete_ctor_at_level_p instead of count_type_elements.
+
+	gcc/
+	2011-07-13  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* tree.h (categorize_ctor_elements): Remove comment.  Fix long line.
+	(count_type_elements): Delete.
+	(complete_ctor_at_level_p): Declare.
+	* expr.c (flexible_array_member_p): New function, split out from...
+	(count_type_elements): ...here.  Make static.  Replace allow_flexarr
+	parameter with for_ctor_p.  When for_ctor_p is true, return the
+	number of elements that should appear in the top-level constructor,
+	otherwise return an estimate of the number of scalars.
+	(categorize_ctor_elements): Replace p_must_clear with p_complete.
+	(categorize_ctor_elements_1): Likewise.  Use complete_ctor_at_level_p.
+	(complete_ctor_at_level_p): New function, borrowing union logic
+	from old categorize_ctor_elements_1.
+	(mostly_zeros_p): Return true if the constructor is not complete.
+	(all_zeros_p): Update call to categorize_ctor_elements.
+	* gimplify.c (gimplify_init_constructor): Update call to
+	categorize_ctor_elements.  Don't call count_type_elements.
+	Unconditionally prevent clearing for variable-sized types,
+	otherwise rely on categorize_ctor_elements to detect
+	incomplete initializers.
+
+	gcc/testsuite/
+	2011-07-13  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* gcc.target/arm/pr48183.c: New test.
+
+=== modified file 'gcc/cp/typeck2.c'
+--- old/gcc/cp/typeck2.c	2011-05-20 21:29:14 +0000
++++ new/gcc/cp/typeck2.c	2011-07-13 13:17:31 +0000
+@@ -473,18 +473,20 @@
+ 
+ 
+ /* The recursive part of split_nonconstant_init.  DEST is an lvalue
+-   expression to which INIT should be assigned.  INIT is a CONSTRUCTOR.  */
++   expression to which INIT should be assigned.  INIT is a CONSTRUCTOR.
++   Return true if the whole of the value was initialized by the
++   generated statements.  */
+ 
+-static void
+-split_nonconstant_init_1 (tree dest, tree *initp)
++static bool
++split_nonconstant_init_1 (tree dest, tree init)
+ {
+   unsigned HOST_WIDE_INT idx;
+-  tree init = *initp;
+   tree field_index, value;
+   tree type = TREE_TYPE (dest);
+   tree inner_type = NULL;
+   bool array_type_p = false;
+-  HOST_WIDE_INT num_type_elements, num_initialized_elements;
++  bool complete_p = true;
++  HOST_WIDE_INT num_split_elts = 0;
+ 
+   switch (TREE_CODE (type))
+     {
+@@ -496,7 +498,6 @@
+     case RECORD_TYPE:
+     case UNION_TYPE:
+     case QUAL_UNION_TYPE:
+-      num_initialized_elements = 0;
+       FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx,
+ 				field_index, value)
+ 	{
+@@ -519,13 +520,14 @@
+ 		sub = build3 (COMPONENT_REF, inner_type, dest, field_index,
+ 			      NULL_TREE);
+ 
+-	      split_nonconstant_init_1 (sub, &value);
++	      if (!split_nonconstant_init_1 (sub, value))
++		complete_p = false;
++	      num_split_elts++;
+ 	    }
+ 	  else if (!initializer_constant_valid_p (value, inner_type))
+ 	    {
+ 	      tree code;
+ 	      tree sub;
+-	      HOST_WIDE_INT inner_elements;
+ 
+ 	      /* FIXME: Ordered removal is O(1) so the whole function is
+ 		 worst-case quadratic. This could be fixed using an aside
+@@ -549,21 +551,9 @@
+ 	      code = build_stmt (input_location, EXPR_STMT, code);
+ 	      add_stmt (code);
+ 
+-	      inner_elements = count_type_elements (inner_type, true);
+-	      if (inner_elements < 0)
+-		num_initialized_elements = -1;
+-	      else if (num_initialized_elements >= 0)
+-		num_initialized_elements += inner_elements;
+-	      continue;
++	      num_split_elts++;
+ 	    }
+ 	}
+-
+-      num_type_elements = count_type_elements (type, true);
+-      /* If all elements of the initializer are non-constant and
+-	 have been split out, we don't need the empty CONSTRUCTOR.  */
+-      if (num_type_elements > 0
+-	  && num_type_elements == num_initialized_elements)
+-	*initp = NULL;
+       break;
+ 
+     case VECTOR_TYPE:
+@@ -575,6 +565,7 @@
+ 	  code = build2 (MODIFY_EXPR, type, dest, cons);
+ 	  code = build_stmt (input_location, EXPR_STMT, code);
+ 	  add_stmt (code);
++	  num_split_elts += CONSTRUCTOR_NELTS (init);
+ 	}
+       break;
+ 
+@@ -584,6 +575,8 @@
+ 
+   /* The rest of the initializer is now a constant. */
+   TREE_CONSTANT (init) = 1;
++  return complete_p && complete_ctor_at_level_p (TREE_TYPE (init),
++						 num_split_elts, inner_type);
+ }
+ 
+ /* A subroutine of store_init_value.  Splits non-constant static
+@@ -599,7 +592,8 @@
+   if (TREE_CODE (init) == CONSTRUCTOR)
+     {
+       code = push_stmt_list ();
+-      split_nonconstant_init_1 (dest, &init);
++      if (split_nonconstant_init_1 (dest, init))
++	init = NULL_TREE;
+       code = pop_stmt_list (code);
+       DECL_INITIAL (dest) = init;
+       TREE_READONLY (dest) = 0;
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2011-06-02 12:12:00 +0000
++++ new/gcc/expr.c	2011-07-14 11:52:32 +0000
+@@ -4866,16 +4866,136 @@
+   return NULL_RTX;
+ }
+ 
++/* Return true if field F of structure TYPE is a flexible array.  */
++
++static bool
++flexible_array_member_p (const_tree f, const_tree type)
++{
++  const_tree tf;
++
++  tf = TREE_TYPE (f);
++  return (DECL_CHAIN (f) == NULL
++	  && TREE_CODE (tf) == ARRAY_TYPE
++	  && TYPE_DOMAIN (tf)
++	  && TYPE_MIN_VALUE (TYPE_DOMAIN (tf))
++	  && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf)))
++	  && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf))
++	  && int_size_in_bytes (type) >= 0);
++}
++
++/* If FOR_CTOR_P, return the number of top-level elements that a constructor
++   must have in order for it to completely initialize a value of type TYPE.
++   Return -1 if the number isn't known.
++
++   If !FOR_CTOR_P, return an estimate of the number of scalars in TYPE.  */
++
++static HOST_WIDE_INT
++count_type_elements (const_tree type, bool for_ctor_p)
++{
++  switch (TREE_CODE (type))
++    {
++    case ARRAY_TYPE:
++      {
++	tree nelts;
++
++	nelts = array_type_nelts (type);
++	if (nelts && host_integerp (nelts, 1))
++	  {
++	    unsigned HOST_WIDE_INT n;
++
++	    n = tree_low_cst (nelts, 1) + 1;
++	    if (n == 0 || for_ctor_p)
++	      return n;
++	    else
++	      return n * count_type_elements (TREE_TYPE (type), false);
++	  }
++	return for_ctor_p ? -1 : 1;
++      }
++
++    case RECORD_TYPE:
++      {
++	unsigned HOST_WIDE_INT n;
++	tree f;
++
++	n = 0;
++	for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
++	  if (TREE_CODE (f) == FIELD_DECL)
++	    {
++	      if (!for_ctor_p)
++		n += count_type_elements (TREE_TYPE (f), false);
++	      else if (!flexible_array_member_p (f, type))
++		/* Don't count flexible arrays, which are not supposed
++		   to be initialized.  */
++		n += 1;
++	    }
++
++	return n;
++      }
++
++    case UNION_TYPE:
++    case QUAL_UNION_TYPE:
++      {
++	tree f;
++	HOST_WIDE_INT n, m;
++
++	gcc_assert (!for_ctor_p);
++	/* Estimate the number of scalars in each field and pick the
++	   maximum.  Other estimates would do instead; the idea is simply
++	   to make sure that the estimate is not sensitive to the ordering
++	   of the fields.  */
++	n = 1;
++	for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
++	  if (TREE_CODE (f) == FIELD_DECL)
++	    {
++	      m = count_type_elements (TREE_TYPE (f), false);
++	      /* If the field doesn't span the whole union, add an extra
++		 scalar for the rest.  */
++	      if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (f)),
++				    TYPE_SIZE (type)) != 1)
++		m++;
++	      if (n < m)
++		n = m;
++	    }
++	return n;
++      }
++
++    case COMPLEX_TYPE:
++      return 2;
++
++    case VECTOR_TYPE:
++      return TYPE_VECTOR_SUBPARTS (type);
++
++    case INTEGER_TYPE:
++    case REAL_TYPE:
++    case FIXED_POINT_TYPE:
++    case ENUMERAL_TYPE:
++    case BOOLEAN_TYPE:
++    case POINTER_TYPE:
++    case OFFSET_TYPE:
++    case REFERENCE_TYPE:
++      return 1;
++
++    case ERROR_MARK:
++      return 0;
++
++    case VOID_TYPE:
++    case METHOD_TYPE:
++    case FUNCTION_TYPE:
++    case LANG_TYPE:
++    default:
++      gcc_unreachable ();
++    }
++}
++
+ /* Helper for categorize_ctor_elements.  Identical interface.  */
+ 
+ static bool
+ categorize_ctor_elements_1 (const_tree ctor, HOST_WIDE_INT *p_nz_elts,
+-			    HOST_WIDE_INT *p_elt_count,
+-			    bool *p_must_clear)
++			    HOST_WIDE_INT *p_init_elts, bool *p_complete)
+ {
+   unsigned HOST_WIDE_INT idx;
+-  HOST_WIDE_INT nz_elts, elt_count;
+-  tree value, purpose;
++  HOST_WIDE_INT nz_elts, init_elts, num_fields;
++  tree value, purpose, elt_type;
+ 
+   /* Whether CTOR is a valid constant initializer, in accordance with what
+      initializer_constant_valid_p does.  If inferred from the constructor
+@@ -4884,7 +5004,9 @@
+   bool const_p = const_from_elts_p ? true : TREE_STATIC (ctor);
+ 
+   nz_elts = 0;
+-  elt_count = 0;
++  init_elts = 0;
++  num_fields = 0;
++  elt_type = NULL_TREE;
+ 
+   FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), idx, purpose, value)
+     {
+@@ -4899,6 +5021,8 @@
+ 	    mult = (tree_low_cst (hi_index, 1)
+ 		    - tree_low_cst (lo_index, 1) + 1);
+ 	}
++      num_fields += mult;
++      elt_type = TREE_TYPE (value);
+ 
+       switch (TREE_CODE (value))
+ 	{
+@@ -4906,11 +5030,11 @@
+ 	  {
+ 	    HOST_WIDE_INT nz = 0, ic = 0;
+ 
+-	    bool const_elt_p
+-	      = categorize_ctor_elements_1 (value, &nz, &ic, p_must_clear);
++	    bool const_elt_p = categorize_ctor_elements_1 (value, &nz, &ic,
++							   p_complete);
+ 
+ 	    nz_elts += mult * nz;
+- 	    elt_count += mult * ic;
++ 	    init_elts += mult * ic;
+ 
+ 	    if (const_from_elts_p && const_p)
+ 	      const_p = const_elt_p;
+@@ -4922,12 +5046,12 @@
+ 	case FIXED_CST:
+ 	  if (!initializer_zerop (value))
+ 	    nz_elts += mult;
+-	  elt_count += mult;
++	  init_elts += mult;
+ 	  break;
+ 
+ 	case STRING_CST:
+ 	  nz_elts += mult * TREE_STRING_LENGTH (value);
+-	  elt_count += mult * TREE_STRING_LENGTH (value);
++	  init_elts += mult * TREE_STRING_LENGTH (value);
+ 	  break;
+ 
+ 	case COMPLEX_CST:
+@@ -4935,7 +5059,7 @@
+ 	    nz_elts += mult;
+ 	  if (!initializer_zerop (TREE_IMAGPART (value)))
+ 	    nz_elts += mult;
+-	  elt_count += mult;
++	  init_elts += mult;
+ 	  break;
+ 
+ 	case VECTOR_CST:
+@@ -4945,65 +5069,31 @@
+ 	      {
+ 		if (!initializer_zerop (TREE_VALUE (v)))
+ 		  nz_elts += mult;
+-		elt_count += mult;
++		init_elts += mult;
+ 	      }
+ 	  }
+ 	  break;
+ 
+ 	default:
+ 	  {
+-	    HOST_WIDE_INT tc = count_type_elements (TREE_TYPE (value), true);
+-	    if (tc < 1)
+-	      tc = 1;
++	    HOST_WIDE_INT tc = count_type_elements (elt_type, false);
+ 	    nz_elts += mult * tc;
+-	    elt_count += mult * tc;
++	    init_elts += mult * tc;
+ 
+ 	    if (const_from_elts_p && const_p)
+-	      const_p = initializer_constant_valid_p (value, TREE_TYPE (value))
++	      const_p = initializer_constant_valid_p (value, elt_type)
+ 			!= NULL_TREE;
+ 	  }
+ 	  break;
+ 	}
+     }
+ 
+-  if (!*p_must_clear
+-      && (TREE_CODE (TREE_TYPE (ctor)) == UNION_TYPE
+-	  || TREE_CODE (TREE_TYPE (ctor)) == QUAL_UNION_TYPE))
+-    {
+-      tree init_sub_type;
+-      bool clear_this = true;
+-
+-      if (!VEC_empty (constructor_elt, CONSTRUCTOR_ELTS (ctor)))
+-	{
+-	  /* We don't expect more than one element of the union to be
+-	     initialized.  Not sure what we should do otherwise... */
+-          gcc_assert (VEC_length (constructor_elt, CONSTRUCTOR_ELTS (ctor))
+-		      == 1);
+-
+-          init_sub_type = TREE_TYPE (VEC_index (constructor_elt,
+-						CONSTRUCTOR_ELTS (ctor),
+-						0)->value);
+-
+-	  /* ??? We could look at each element of the union, and find the
+-	     largest element.  Which would avoid comparing the size of the
+-	     initialized element against any tail padding in the union.
+-	     Doesn't seem worth the effort...  */
+-	  if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (ctor)),
+-				TYPE_SIZE (init_sub_type)) == 1)
+-	    {
+-	      /* And now we have to find out if the element itself is fully
+-		 constructed.  E.g. for union { struct { int a, b; } s; } u
+-		 = { .s = { .a = 1 } }.  */
+-	      if (elt_count == count_type_elements (init_sub_type, false))
+-		clear_this = false;
+-	    }
+-	}
+-
+-      *p_must_clear = clear_this;
+-    }
++  if (*p_complete && !complete_ctor_at_level_p (TREE_TYPE (ctor),
++						num_fields, elt_type))
++    *p_complete = false;
+ 
+   *p_nz_elts += nz_elts;
+-  *p_elt_count += elt_count;
++  *p_init_elts += init_elts;
+ 
+   return const_p;
+ }
+@@ -5013,111 +5103,50 @@
+      and place it in *P_NZ_ELTS;
+    * how many scalar fields in total are in CTOR,
+      and place it in *P_ELT_COUNT.
+-   * if a type is a union, and the initializer from the constructor
+-     is not the largest element in the union, then set *p_must_clear.
++   * whether the constructor is complete -- in the sense that every
++     meaningful byte is explicitly given a value --
++     and place it in *P_COMPLETE.
+ 
+    Return whether or not CTOR is a valid static constant initializer, the same
+    as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0".  */
+ 
+ bool
+ categorize_ctor_elements (const_tree ctor, HOST_WIDE_INT *p_nz_elts,
+-			  HOST_WIDE_INT *p_elt_count,
+-			  bool *p_must_clear)
++			  HOST_WIDE_INT *p_init_elts, bool *p_complete)
+ {
+   *p_nz_elts = 0;
+-  *p_elt_count = 0;
+-  *p_must_clear = false;
++  *p_init_elts = 0;
++  *p_complete = true;
+ 
+-  return
+-    categorize_ctor_elements_1 (ctor, p_nz_elts, p_elt_count, p_must_clear);
++  return categorize_ctor_elements_1 (ctor, p_nz_elts, p_init_elts, p_complete);
+ }
+ 
+-/* Count the number of scalars in TYPE.  Return -1 on overflow or
+-   variable-sized.  If ALLOW_FLEXARR is true, don't count flexible
+-   array member at the end of the structure.  */
++/* TYPE is initialized by a constructor with NUM_ELTS elements, the last
++   of which had type LAST_TYPE.  Each element was itself a complete
++   initializer, in the sense that every meaningful byte was explicitly
++   given a value.  Return true if the same is true for the constructor
++   as a whole.  */
+ 
+-HOST_WIDE_INT
+-count_type_elements (const_tree type, bool allow_flexarr)
++bool
++complete_ctor_at_level_p (const_tree type, HOST_WIDE_INT num_elts,
++			  const_tree last_type)
+ {
+-  const HOST_WIDE_INT max = ~((HOST_WIDE_INT)1 << (HOST_BITS_PER_WIDE_INT-1));
+-  switch (TREE_CODE (type))
++  if (TREE_CODE (type) == UNION_TYPE
++      || TREE_CODE (type) == QUAL_UNION_TYPE)
+     {
+-    case ARRAY_TYPE:
+-      {
+-	tree telts = array_type_nelts (type);
+-	if (telts && host_integerp (telts, 1))
+-	  {
+-	    HOST_WIDE_INT n = tree_low_cst (telts, 1) + 1;
+-	    HOST_WIDE_INT m = count_type_elements (TREE_TYPE (type), false);
+-	    if (n == 0)
+-	      return 0;
+-	    else if (max / n > m)
+-	      return n * m;
+-	  }
+-	return -1;
+-      }
+-
+-    case RECORD_TYPE:
+-      {
+-	HOST_WIDE_INT n = 0, t;
+-	tree f;
+-
+-	for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
+-	  if (TREE_CODE (f) == FIELD_DECL)
+-	    {
+-	      t = count_type_elements (TREE_TYPE (f), false);
+-	      if (t < 0)
+-		{
+-		  /* Check for structures with flexible array member.  */
+-		  tree tf = TREE_TYPE (f);
+-		  if (allow_flexarr
+-		      && DECL_CHAIN (f) == NULL
+-		      && TREE_CODE (tf) == ARRAY_TYPE
+-		      && TYPE_DOMAIN (tf)
+-		      && TYPE_MIN_VALUE (TYPE_DOMAIN (tf))
+-		      && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf)))
+-		      && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf))
+-		      && int_size_in_bytes (type) >= 0)
+-		    break;
+-
+-		  return -1;
+-		}
+-	      n += t;
+-	    }
+-
+-	return n;
+-      }
+-
+-    case UNION_TYPE:
+-    case QUAL_UNION_TYPE:
+-      return -1;
+-
+-    case COMPLEX_TYPE:
+-      return 2;
+-
+-    case VECTOR_TYPE:
+-      return TYPE_VECTOR_SUBPARTS (type);
+-
+-    case INTEGER_TYPE:
+-    case REAL_TYPE:
+-    case FIXED_POINT_TYPE:
+-    case ENUMERAL_TYPE:
+-    case BOOLEAN_TYPE:
+-    case POINTER_TYPE:
+-    case OFFSET_TYPE:
+-    case REFERENCE_TYPE:
+-      return 1;
+-
+-    case ERROR_MARK:
+-      return 0;
+-
+-    case VOID_TYPE:
+-    case METHOD_TYPE:
+-    case FUNCTION_TYPE:
+-    case LANG_TYPE:
+-    default:
+-      gcc_unreachable ();
++      if (num_elts == 0)
++	return false;
++
++      gcc_assert (num_elts == 1 && last_type);
++
++      /* ??? We could look at each element of the union, and find the
++	 largest element.  Which would avoid comparing the size of the
++	 initialized element against any tail padding in the union.
++	 Doesn't seem worth the effort...  */
++      return simple_cst_equal (TYPE_SIZE (type), TYPE_SIZE (last_type)) == 1;
+     }
++
++  return count_type_elements (type, true) == num_elts;
+ }
+ 
+ /* Return 1 if EXP contains mostly (3/4)  zeros.  */
+@@ -5126,18 +5155,12 @@
+ mostly_zeros_p (const_tree exp)
+ {
+   if (TREE_CODE (exp) == CONSTRUCTOR)
+-
+     {
+-      HOST_WIDE_INT nz_elts, count, elts;
+-      bool must_clear;
+-
+-      categorize_ctor_elements (exp, &nz_elts, &count, &must_clear);
+-      if (must_clear)
+-	return 1;
+-
+-      elts = count_type_elements (TREE_TYPE (exp), false);
+-
+-      return nz_elts < elts / 4;
++      HOST_WIDE_INT nz_elts, init_elts;
++      bool complete_p;
++
++      categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p);
++      return !complete_p || nz_elts < init_elts / 4;
+     }
+ 
+   return initializer_zerop (exp);
+@@ -5149,12 +5172,11 @@
+ all_zeros_p (const_tree exp)
+ {
+   if (TREE_CODE (exp) == CONSTRUCTOR)
+-
+     {
+-      HOST_WIDE_INT nz_elts, count;
+-      bool must_clear;
++      HOST_WIDE_INT nz_elts, init_elts;
++      bool complete_p;
+ 
+-      categorize_ctor_elements (exp, &nz_elts, &count, &must_clear);
++      categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p);
+       return nz_elts == 0;
+     }
+ 
+
+=== modified file 'gcc/gimplify.c'
+--- old/gcc/gimplify.c	2011-05-26 10:27:57 +0000
++++ new/gcc/gimplify.c	2011-07-13 13:17:31 +0000
+@@ -3693,9 +3693,8 @@
+     case ARRAY_TYPE:
+       {
+ 	struct gimplify_init_ctor_preeval_data preeval_data;
+-	HOST_WIDE_INT num_type_elements, num_ctor_elements;
+-	HOST_WIDE_INT num_nonzero_elements;
+-	bool cleared, valid_const_initializer;
++	HOST_WIDE_INT num_ctor_elements, num_nonzero_elements;
++	bool cleared, complete_p, valid_const_initializer;
+ 
+ 	/* Aggregate types must lower constructors to initialization of
+ 	   individual elements.  The exception is that a CONSTRUCTOR node
+@@ -3712,7 +3711,7 @@
+ 	   can only do so if it known to be a valid constant initializer.  */
+ 	valid_const_initializer
+ 	  = categorize_ctor_elements (ctor, &num_nonzero_elements,
+-				      &num_ctor_elements, &cleared);
++				      &num_ctor_elements, &complete_p);
+ 
+ 	/* If a const aggregate variable is being initialized, then it
+ 	   should never be a lose to promote the variable to be static.  */
+@@ -3750,26 +3749,29 @@
+ 	   parts in, then generate code for the non-constant parts.  */
+ 	/* TODO.  There's code in cp/typeck.c to do this.  */
+ 
+-	num_type_elements = count_type_elements (type, true);
++	if (int_size_in_bytes (TREE_TYPE (ctor)) < 0)
++	  /* store_constructor will ignore the clearing of variable-sized
++	     objects.  Initializers for such objects must explicitly set
++	     every field that needs to be set.  */
++	  cleared = false;
++	else if (!complete_p)
++	  /* If the constructor isn't complete, clear the whole object
++	     beforehand.
+ 
+-	/* If count_type_elements could not determine number of type elements
+-	   for a constant-sized object, assume clearing is needed.
+-	   Don't do this for variable-sized objects, as store_constructor
+-	   will ignore the clearing of variable-sized objects.  */
+-	if (num_type_elements < 0 && int_size_in_bytes (type) >= 0)
++	     ??? This ought not to be needed.  For any element not present
++	     in the initializer, we should simply set them to zero.  Except
++	     we'd need to *find* the elements that are not present, and that
++	     requires trickery to avoid quadratic compile-time behavior in
++	     large cases or excessive memory use in small cases.  */
+ 	  cleared = true;
+-	/* If there are "lots" of zeros, then block clear the object first.  */
+-	else if (num_type_elements - num_nonzero_elements
++	else if (num_ctor_elements - num_nonzero_elements
+ 		 > CLEAR_RATIO (optimize_function_for_speed_p (cfun))
+-		 && num_nonzero_elements < num_type_elements/4)
+-	  cleared = true;
+-	/* ??? This bit ought not be needed.  For any element not present
+-	   in the initializer, we should simply set them to zero.  Except
+-	   we'd need to *find* the elements that are not present, and that
+-	   requires trickery to avoid quadratic compile-time behavior in
+-	   large cases or excessive memory use in small cases.  */
+-	else if (num_ctor_elements < num_type_elements)
+-	  cleared = true;
++		 && num_nonzero_elements < num_ctor_elements / 4)
++	  /* If there are "lots" of zeros, it's more efficient to clear
++	     the memory and then set the nonzero elements.  */
++	  cleared = true;
++	else
++	  cleared = false;
+ 
+ 	/* If there are "lots" of initialized elements, and all of them
+ 	   are valid address constants, then the entire initializer can
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr48183.c'
+--- old/gcc/testsuite/gcc.target/arm/pr48183.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr48183.c	2011-07-13 13:17:31 +0000
+@@ -0,0 +1,25 @@
++/* testsuite/gcc.target/arm/pr48183.c */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O -g" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n)
++{
++    unsigned i;
++    int16x4x2_t input;
++    int32x4x2_t mid;
++    int32x4x2_t output;
++
++    for (i = 0; i < n/2; i += 8) {
++        input = vld2_s16(src + i);
++        mid.val[0] = vmovl_s16(input.val[0]);
++        mid.val[1] = vmovl_s16(input.val[1]);
++        output.val[0] = vshlq_n_s32(mid.val[0], 8);
++        output.val[1] = vshlq_n_s32(mid.val[1], 8);
++        vst2q_s32((int32_t *)dst + i, output);
++    }
++}
+
+=== modified file 'gcc/tree.h'
+--- old/gcc/tree.h	2011-07-01 09:19:21 +0000
++++ new/gcc/tree.h	2011-07-13 13:17:31 +0000
+@@ -4627,21 +4627,10 @@
+ 
+ extern VEC(tree,gc) *ctor_to_vec (tree);
+ 
+-/* Examine CTOR to discover:
+-   * how many scalar fields are set to nonzero values,
+-     and place it in *P_NZ_ELTS;
+-   * how many scalar fields in total are in CTOR,
+-     and place it in *P_ELT_COUNT.
+-   * if a type is a union, and the initializer from the constructor
+-     is not the largest element in the union, then set *p_must_clear.
+-
+-   Return whether or not CTOR is a valid static constant initializer, the same
+-   as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0".  */
+-
+-extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, HOST_WIDE_INT *,
+-				      bool *);
+-
+-extern HOST_WIDE_INT count_type_elements (const_tree, bool);
++extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *,
++				      HOST_WIDE_INT *, bool *);
++
++extern bool complete_ctor_at_level_p (const_tree, HOST_WIDE_INT, const_tree);
+ 
+ /* integer_zerop (tree x) is nonzero if X is an integer constant of value 0.  */
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch
new file mode 100644
index 0000000000..5335a9e375
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch
@@ -0,0 +1,27 @@
+2011-07-21  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	gcc/
+	Backport from mainline:
+
+	2011-07-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* regcprop.c (maybe_mode_change): Check HARD_REGNO_MODE_OK.
+
+=== modified file 'gcc/regcprop.c'
+--- old/gcc/regcprop.c	2010-12-17 22:51:25 +0000
++++ new/gcc/regcprop.c	2011-07-21 11:30:53 +0000
+@@ -418,10 +418,9 @@
+ 
+       offset = ((WORDS_BIG_ENDIAN ? wordoffset : 0)
+ 		+ (BYTES_BIG_ENDIAN ? byteoffset : 0));
+-      return gen_rtx_raw_REG (new_mode,
+-			      regno + subreg_regno_offset (regno, orig_mode,
+-							   offset,
+-							   new_mode));
++      regno += subreg_regno_offset (regno, orig_mode, offset, new_mode);
++      if (HARD_REGNO_MODE_OK (regno, new_mode))
++	return gen_rtx_raw_REG (new_mode, regno);
+     }
+   return NULL_RTX;
+ }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch
new file mode 100644
index 0000000000..61e3916375
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch
@@ -0,0 +1,62 @@
+2011-07-31  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	Backport from trunk -r176970:
+
+	* modulo-sched.c: Change comment.
+	(reset_sched_times): Fix print message.
+	(print_partial_schedule): Add print info.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-07-04 12:01:34 +0000
++++ new/gcc/modulo-sched.c	2011-07-31 10:58:46 +0000
+@@ -84,13 +84,14 @@
+       II cycles (i.e. use register copies to prevent a def from overwriting
+       itself before reaching the use).
+ 
+-    SMS works with countable loops whose loop count can be easily
+-    adjusted.  This is because we peel a constant number of iterations
+-    into a prologue and epilogue for which we want to avoid emitting
+-    the control part, and a kernel which is to iterate that constant
+-    number of iterations less than the original loop.  So the control
+-    part should be a set of insns clearly identified and having its
+-    own iv, not otherwise used in the loop (at-least for now), which
++    SMS works with countable loops (1) whose control part can be easily
++    decoupled from the rest of the loop and (2) whose loop count can
++    be easily adjusted.  This is because we peel a constant number of
++    iterations into a prologue and epilogue for which we want to avoid
++    emitting the control part, and a kernel which is to iterate that
++    constant number of iterations less than the original loop.  So the
++    control part should be a set of insns clearly identified and having
++    its own iv, not otherwise used in the loop (at-least for now), which
+     initializes a register before the loop to the number of iterations.
+     Currently SMS relies on the do-loop pattern to recognize such loops,
+     where (1) the control part comprises of all insns defining and/or
+@@ -598,8 +599,8 @@
+             /* Print the scheduling times after the rotation.  */
+             fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
+                      "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
+-                     INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
+-                     normalized_time);
++                     INSN_UID (crr_insn->node->insn), normalized_time,
++                     new_min_cycle);
+             if (JUMP_P (crr_insn->node->insn))
+               fprintf (dump_file, " (branch)");
+             fprintf (dump_file, "\n");
+@@ -2550,8 +2551,13 @@
+       fprintf (dump, "\n[ROW %d ]: ", i);
+       while (ps_i)
+ 	{
+-	  fprintf (dump, "%d, ",
+-		   INSN_UID (ps_i->node->insn));
++	  if (JUMP_P (ps_i->node->insn))
++	    fprintf (dump, "%d (branch), ",
++		     INSN_UID (ps_i->node->insn));
++	  else
++	    fprintf (dump, "%d, ",
++		     INSN_UID (ps_i->node->insn));
++	
+ 	  ps_i = ps_i->next_in_row;
+ 	}
+     }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch
new file mode 100644
index 0000000000..b82fe76d41
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch
@@ -0,0 +1,458 @@
+2011-08-09  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	Backport from trunk -r177235.
+	* modulo-sched.c (calculate_stage_count,
+	calculate_must_precede_follow, get_sched_window,
+	try_scheduling_node_in_cycle, remove_node_from_ps):
+	Add declaration.
+	(update_node_sched_params, set_must_precede_follow, optimize_sc):
+	New functions.
+	(reset_sched_times): Call update_node_sched_params.
+	(sms_schedule):	Call optimize_sc.
+	(get_sched_window): Change function arguments.
+	(sms_schedule_by_order): Update call to	get_sched_window.
+	Call set_must_precede_follow.
+	(calculate_stage_count): Add function argument.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-07-31 10:58:46 +0000
++++ new/gcc/modulo-sched.c	2011-08-09 04:51:48 +0000
+@@ -203,7 +203,16 @@
+                                     rtx, rtx);
+ static void duplicate_insns_of_cycles (partial_schedule_ptr,
+ 				       int, int, int, rtx);
+-static int calculate_stage_count (partial_schedule_ptr ps);
++static int calculate_stage_count (partial_schedule_ptr, int);
++static void calculate_must_precede_follow (ddg_node_ptr, int, int,
++					   int, int, sbitmap, sbitmap, sbitmap);
++static int get_sched_window (partial_schedule_ptr, ddg_node_ptr, 
++			     sbitmap, int, int *, int *, int *);
++static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
++					  int, int, sbitmap, int *, sbitmap,
++					  sbitmap);
++static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
++
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+ #define SCHED_FIRST_REG_MOVE(x) \
+@@ -577,6 +586,36 @@
+     }
+ }
+ 
++/* Update the sched_params (time, row and stage) for node U using the II,
++   the CYCLE of U and MIN_CYCLE.  
++   We're not simply taking the following
++   SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
++   because the stages may not be aligned on cycle 0.  */
++static void
++update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle)
++{
++  int sc_until_cycle_zero;
++  int stage;
++
++  SCHED_TIME (u) = cycle;
++  SCHED_ROW (u) = SMODULO (cycle, ii);
++
++  /* The calculation of stage count is done adding the number
++     of stages before cycle zero and after cycle zero.  */
++  sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
++
++  if (SCHED_TIME (u) < 0)
++    {
++      stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
++      SCHED_STAGE (u) = sc_until_cycle_zero - stage;
++    }
++  else
++    {
++      stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
++      SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
++    }
++}
++
+ /* Bump the SCHED_TIMEs of all nodes by AMOUNT.  Set the values of
+    SCHED_ROW and SCHED_STAGE.  */
+ static void
+@@ -592,7 +631,6 @@
+ 	ddg_node_ptr u = crr_insn->node;
+ 	int normalized_time = SCHED_TIME (u) - amount;
+ 	int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
+-        int sc_until_cycle_zero, stage;
+ 
+         if (dump_file)
+           {
+@@ -608,23 +646,9 @@
+ 	
+ 	gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+ 	gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
+-	SCHED_TIME (u) = normalized_time;
+-	SCHED_ROW (u) = SMODULO (normalized_time, ii);
+-      
+-        /* The calculation of stage count is done adding the number
+-           of stages before cycle zero and after cycle zero.  */
+-	sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
+-	
+-	if (SCHED_TIME (u) < 0)
+-	  {
+-	    stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
+-	    SCHED_STAGE (u) = sc_until_cycle_zero - stage;
+-	  }
+-	else
+-	  {
+-	    stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
+-	    SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
+-	  }
++
++	crr_insn->cycle = normalized_time;
++	update_node_sched_params (u, ii, normalized_time, new_min_cycle);
+       }
+ }
+  
+@@ -661,6 +685,206 @@
+ 			    PREV_INSN (last));
+ }
+ 
++/* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE
++   respectively only if cycle C falls on the border of the scheduling
++   window boundaries marked by START and END cycles.  STEP is the
++   direction of the window.  */
++static inline void
++set_must_precede_follow (sbitmap *tmp_follow, sbitmap must_follow,
++			 sbitmap *tmp_precede, sbitmap must_precede, int c,
++			 int start, int end, int step)
++{
++  *tmp_precede = NULL;
++  *tmp_follow = NULL;
++
++  if (c == start)
++    {
++      if (step == 1)
++	*tmp_precede = must_precede;
++      else			/* step == -1.  */
++	*tmp_follow = must_follow;
++    }
++  if (c == end - step)
++    {
++      if (step == 1)
++	*tmp_follow = must_follow;
++      else			/* step == -1.  */
++	*tmp_precede = must_precede;
++    }
++
++}
++
++/* Return True if the branch can be moved to row ii-1 while
++   normalizing the partial schedule PS to start from cycle zero and thus
++   optimize the SC.  Otherwise return False.  */
++static bool
++optimize_sc (partial_schedule_ptr ps, ddg_ptr g)
++{
++  int amount = PS_MIN_CYCLE (ps);
++  sbitmap sched_nodes = sbitmap_alloc (g->num_nodes);
++  int start, end, step;
++  int ii = ps->ii;
++  bool ok = false;
++  int stage_count, stage_count_curr;
++
++  /* Compare the SC after normalization and SC after bringing the branch
++     to row ii-1.  If they are equal just bail out.  */
++  stage_count = calculate_stage_count (ps, amount);
++  stage_count_curr =
++    calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1));
++
++  if (stage_count == stage_count_curr)
++    {
++      if (dump_file)
++	fprintf (dump_file, "SMS SC already optimized.\n");
++
++      ok = false;
++      goto clear;
++    }
++
++  if (dump_file)
++    {
++      fprintf (dump_file, "SMS Trying to optimize branch location\n");
++      fprintf (dump_file, "SMS partial schedule before trial:\n");
++      print_partial_schedule (ps, dump_file);
++    }
++
++  /* First, normalize the partial scheduling.  */
++  reset_sched_times (ps, amount);
++  rotate_partial_schedule (ps, amount);
++  if (dump_file)
++    {
++      fprintf (dump_file,
++	       "SMS partial schedule after normalization (ii, %d, SC %d):\n",
++	       ii, stage_count);
++      print_partial_schedule (ps, dump_file);
++    }
++
++  if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1)
++    {
++      ok = true;
++      goto clear;
++    }
++
++  sbitmap_ones (sched_nodes);
++
++  /* Calculate the new placement of the branch.  It should be in row
++     ii-1 and fall into it's scheduling window.  */
++  if (get_sched_window (ps, g->closing_branch, sched_nodes, ii, &start,
++			&step, &end) == 0)
++    {
++      bool success;
++      ps_insn_ptr next_ps_i;
++      int branch_cycle = SCHED_TIME (g->closing_branch);
++      int row = SMODULO (branch_cycle, ps->ii);
++      int num_splits = 0;
++      sbitmap must_precede, must_follow, tmp_precede, tmp_follow;
++      int c;
++
++      if (dump_file)
++	fprintf (dump_file, "\nTrying to schedule node %d "
++		 "INSN = %d  in (%d .. %d) step %d\n",
++		 g->closing_branch->cuid,
++		 (INSN_UID (g->closing_branch->insn)), start, end, step);
++
++      gcc_assert ((step > 0 && start < end) || (step < 0 && start > end));
++      if (step == 1)
++	{
++	  c = start + ii - SMODULO (start, ii) - 1;
++	  gcc_assert (c >= start);
++	  if (c >= end)
++	    {
++	      ok = false;
++	      if (dump_file)
++		fprintf (dump_file,
++			 "SMS failed to schedule branch at cycle: %d\n", c);
++	      goto clear;
++	    }
++	}
++      else
++	{
++	  c = start - SMODULO (start, ii) - 1;
++	  gcc_assert (c <= start);
++
++	  if (c <= end)
++	    {
++	      if (dump_file)
++		fprintf (dump_file,
++			 "SMS failed to schedule branch at cycle: %d\n", c);
++	      ok = false;
++	      goto clear;
++	    }
++	}
++
++      must_precede = sbitmap_alloc (g->num_nodes);
++      must_follow = sbitmap_alloc (g->num_nodes);
++
++      /* Try to schedule the branch is it's new cycle.  */
++      calculate_must_precede_follow (g->closing_branch, start, end,
++				     step, ii, sched_nodes,
++				     must_precede, must_follow);
++
++      set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
++			       must_precede, c, start, end, step);
++
++      /* Find the element in the partial schedule related to the closing
++         branch so we can remove it from it's current cycle.  */
++      for (next_ps_i = ps->rows[row];
++	   next_ps_i; next_ps_i = next_ps_i->next_in_row)
++	if (next_ps_i->node->cuid == g->closing_branch->cuid)
++	  break;
++
++      gcc_assert (next_ps_i);
++      gcc_assert (remove_node_from_ps (ps, next_ps_i));
++      success =
++	try_scheduling_node_in_cycle (ps, g->closing_branch,
++				      g->closing_branch->cuid, c,
++				      sched_nodes, &num_splits,
++				      tmp_precede, tmp_follow);
++      gcc_assert (num_splits == 0);
++      if (!success)
++	{
++	  if (dump_file)
++	    fprintf (dump_file,
++		     "SMS failed to schedule branch at cycle: %d, "
++		     "bringing it back to cycle %d\n", c, branch_cycle);
++
++	  /* The branch was failed to be placed in row ii - 1.
++	     Put it back in it's original place in the partial
++	     schedualing.  */
++	  set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
++				   must_precede, branch_cycle, start, end,
++				   step);
++	  success =
++	    try_scheduling_node_in_cycle (ps, g->closing_branch,
++					  g->closing_branch->cuid,
++					  branch_cycle, sched_nodes,
++					  &num_splits, tmp_precede,
++					  tmp_follow);
++	  gcc_assert (success && (num_splits == 0));
++	  ok = false;
++	}
++      else
++	{
++	  /* The branch is placed in row ii - 1.  */
++	  if (dump_file)
++	    fprintf (dump_file,
++		     "SMS success in moving branch to cycle %d\n", c);
++
++	  update_node_sched_params (g->closing_branch, ii, c,
++				    PS_MIN_CYCLE (ps));
++	  ok = true;
++	}
++
++      free (must_precede);
++      free (must_follow);
++    }
++
++clear:
++  free (sched_nodes);
++  return ok;
++}
++
+ static void
+ duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
+ 			   int to_stage, int for_prolog, rtx count_reg)
+@@ -1116,6 +1340,7 @@
+       int mii, rec_mii;
+       unsigned stage_count = 0;
+       HOST_WIDEST_INT loop_count = 0;
++      bool opt_sc_p = false;
+ 
+       if (! (g = g_arr[loop->num]))
+         continue;
+@@ -1197,14 +1422,32 @@
+       set_node_sched_params (g);
+ 
+       ps = sms_schedule_by_order (g, mii, maxii, node_order);
+-
+-       if (ps)
+-       {
+-         stage_count = calculate_stage_count (ps);
+-         gcc_assert(stage_count >= 1);
+-         PS_STAGE_COUNT(ps) = stage_count;
+-       }
+-
++      
++      if (ps)
++	{
++	  /* Try to achieve optimized SC by normalizing the partial
++	     schedule (having the cycles start from cycle zero).
++	     The branch location must be placed in row ii-1 in the
++	     final scheduling.	If failed, shift all instructions to
++	     position the branch in row ii-1.  */
++	  opt_sc_p = optimize_sc (ps, g);
++	  if (opt_sc_p)
++	    stage_count = calculate_stage_count (ps, 0);
++	  else
++	    {
++	      /* Bring the branch to cycle ii-1.  */
++	      int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
++	      
++	      if (dump_file)
++		fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
++	      
++	      stage_count = calculate_stage_count (ps, amount);
++	    }
++	  
++	  gcc_assert (stage_count >= 1);
++	  PS_STAGE_COUNT (ps) = stage_count;
++	}
++      
+       /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
+          1 means that there is no interleaving between iterations thus
+          we let the scheduling passes do the job in this case.  */
+@@ -1225,12 +1468,16 @@
+       else
+ 	{
+ 	  struct undo_replace_buff_elem *reg_move_replaces;
+-          int amount = SCHED_TIME (g->closing_branch) + 1;
++
++          if (!opt_sc_p)
++            {
++	      /* Rotate the partial schedule to have the branch in row ii-1.  */
++              int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
++	      
++              reset_sched_times (ps, amount);
++              rotate_partial_schedule (ps, amount);
++            }
+ 	  
+-	  /* Set the stage boundaries.	The closing_branch was scheduled
+-	     and should appear in the last (ii-1) row.  */
+-	  reset_sched_times (ps, amount);
+-	  rotate_partial_schedule (ps, amount);
+ 	  set_columns_for_ps (ps);
+ 
+ 	  canon_loop (loop);
+@@ -1382,13 +1629,11 @@
+    scheduling window is empty and zero otherwise.  */
+ 
+ static int
+-get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
++get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node,
+ 		  sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
+ {
+   int start, step, end;
+   ddg_edge_ptr e;
+-  int u = nodes_order [i];
+-  ddg_node_ptr u_node = &ps->g->nodes[u];
+   sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
+   sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
+   sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
+@@ -1800,7 +2045,7 @@
+ 
+ 	  /* Try to get non-empty scheduling window.  */
+ 	 success = 0;
+-         if (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start,
++         if (get_sched_window (ps, u_node, sched_nodes, ii, &start,
+                                 &step, &end) == 0)
+             {
+               if (dump_file)
+@@ -1817,24 +2062,11 @@
+ 
+               for (c = start; c != end; c += step)
+                 {
+-                  sbitmap tmp_precede = NULL;
+-                  sbitmap tmp_follow = NULL;
+-
+-                  if (c == start)
+-                    {
+-                      if (step == 1)
+-                        tmp_precede = must_precede;
+-                      else      /* step == -1.  */
+-                        tmp_follow = must_follow;
+-                    }
+-                  if (c == end - step)
+-                    {
+-                      if (step == 1)
+-                        tmp_follow = must_follow;
+-                      else      /* step == -1.  */
+-                        tmp_precede = must_precede;
+-                    }
+-
++		  sbitmap tmp_precede, tmp_follow;
++
++                  set_must_precede_follow (&tmp_follow, must_follow, 
++		                           &tmp_precede, must_precede, 
++                                           c, start, end, step);
+                   success =
+                     try_scheduling_node_in_cycle (ps, u_node, u, c,
+                                                   sched_nodes,
+@@ -2899,12 +3131,10 @@
+ }
+ 
+ /* Calculate the stage count of the partial schedule PS.  The calculation
+-   takes into account the rotation to bring the closing branch to row
+-   ii-1.  */
++   takes into account the rotation amount passed in ROTATION_AMOUNT.  */
+ int
+-calculate_stage_count (partial_schedule_ptr ps)
++calculate_stage_count (partial_schedule_ptr ps, int rotation_amount)
+ {
+-  int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
+   int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
+   int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
+   int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch
new file mode 100644
index 0000000000..608dd18336
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch
@@ -0,0 +1,39 @@
+ 2011-08-09  Revital Eres  <revital.eres@linaro.org>
+ 
+ 	gcc/
+	Backport from trunk -r176972:
+
+	* ddg.c (create_ddg_dep_from_intra_loop_link): Remove
+	the creation of anti-dep edge from a branch.
+	(add_cross_iteration_register_deps):
+	Create anti-dep edge from a branch.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-07-04 11:00:06 +0000
++++ new/gcc/ddg.c	2011-07-31 11:29:10 +0000
+@@ -197,11 +197,6 @@
+         }
+     }
+ 
+-  /* If a true dep edge enters the branch create an anti edge in the
+-     opposite direction to prevent the creation of reg-moves.  */
+-  if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
+-    create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
+-
+    latency = dep_cost (link);
+    e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
+    add_edge_to_ddg (g, e);
+@@ -306,8 +301,11 @@
+ 
+ 	  gcc_assert (first_def_node);
+ 
++         /* Always create the edge if the use node is a branch in
++            order to prevent the creation of reg-moves.  */
+           if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
+-              || !flag_modulo_sched_allow_regmoves)
++              || !flag_modulo_sched_allow_regmoves
++	      || JUMP_P (use_node->insn))
+             create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
+                                     REG_DEP, 1);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch
new file mode 100644
index 0000000000..55b7cc1078
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch
@@ -0,0 +1,94 @@
+2011-08-11  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+        2011-07-28  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	* config/arm/vfp.md ("*movdf_vfp"): Handle the VFP constraints
+	before the core constraints. Adjust attributes.
+	(*thumb2_movdf_vfp"): Likewise.
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2011-01-20 22:03:29 +0000
++++ new/gcc/config/arm/vfp.md	2011-07-27 12:59:19 +0000
+@@ -401,8 +401,8 @@
+ ;; DFmode moves
+ 
+ (define_insn "*movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,mF,r,UvF,w, w,r"))]
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
+   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
+    && (   register_operand (operands[0], DFmode)
+        || register_operand (operands[1], DFmode))"
+@@ -418,9 +418,9 @@
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+         return \"fconstd%?\\t%P0, #%G1\";
+       case 3: case 4:
++	return output_move_vfp (operands);
++      case 5: case 6:
+ 	return output_move_double (operands);
+-      case 5: case 6:
+-	return output_move_vfp (operands);
+       case 7:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
+@@ -435,7 +435,7 @@
+   "
+   [(set_attr "type"
+      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
+-   (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
++   (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
+ 			       (eq_attr "alternative" "7")
+ 				(if_then_else
+ 				 (eq (symbol_ref "TARGET_VFP_SINGLE")
+@@ -449,8 +449,8 @@
+ )
+ 
+ (define_insn "*thumb2_movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,mF,r,UvF,w, w,r"))]
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,UvF,w, mF,r, w,r"))]
+   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
+   "*
+   {
+@@ -463,10 +463,10 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+ 	return \"fconstd%?\\t%P0, #%G1\";
+-      case 3: case 4: case 8:
++      case 3: case 4:
++	return output_move_vfp (operands);
++      case 5: case 6: case 8:
+ 	return output_move_double (operands);
+-      case 5: case 6:
+-	return output_move_vfp (operands);
+       case 7:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
+@@ -478,8 +478,8 @@
+     }
+   "
+   [(set_attr "type"
+-     "r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*")
+-   (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
++     "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
++   (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
+ 			       (eq_attr "alternative" "7")
+ 				(if_then_else
+ 				 (eq (symbol_ref "TARGET_VFP_SINGLE")
+@@ -487,8 +487,8 @@
+ 				 (const_int 8)
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+-   (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
++   (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
+ )
+ 
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch
new file mode 100644
index 0000000000..bdb48ad1e6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch
@@ -0,0 +1,30 @@
+2011-08-15  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r177357
+
+	gcc/testsuite/
+	2011-08-04  Ian Bolton  <ian.bolton@arm.com>
+
+	* gcc.target/arm/vfp-1.c: no large negative offsets on Thumb2.
+
+=== modified file 'gcc/testsuite/gcc.target/arm/vfp-1.c'
+--- old/gcc/testsuite/gcc.target/arm/vfp-1.c	2011-01-01 08:52:03 +0000
++++ new/gcc/testsuite/gcc.target/arm/vfp-1.c	2011-08-09 23:22:51 +0000
+@@ -127,13 +127,13 @@
+ 
+ void test_ldst (float f[], double d[]) {
+   /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
+-  /* { dg-final { scan-assembler "flds.+ \\\[r0, #-1020\\\]" } } */
++  /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
+   /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
+-  /* { dg-final { scan-assembler "fsts.+ \\\[r0, #0\\\]\n" } } */
++  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */
+   f[256] = f[255] + f[-255];
+ 
+   /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
+-  /* { dg-final { scan-assembler "fldd.+ \\\[r1, #-1016\\\]" } } */
++  /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
+   /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
+   d[32] = d[127] + d[-127];
+ }
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch
new file mode 100644
index 0000000000..a384ce7a18
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch
@@ -0,0 +1,33 @@
+2011-08-15  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* config/rs6000/rs6000.c (paired_expand_vector_init): Don't create
+	CONST_VECTORs with symbolic elements.
+	(rs6000_expand_vector_init): Likewise.
+
+=== modified file 'gcc/config/rs6000/rs6000.c'
+--- old/gcc/config/rs6000/rs6000.c	2011-07-27 18:17:15 +0000
++++ new/gcc/config/rs6000/rs6000.c	2011-08-16 08:59:36 +0000
+@@ -5134,7 +5134,9 @@
+   for (i = 0; i < n_elts; ++i)
+     {
+       x = XVECEXP (vals, 0, i);
+-      if (!CONSTANT_P (x))
++      if (!(CONST_INT_P (x)
++	    || GET_CODE (x) == CONST_DOUBLE
++	    || GET_CODE (x) == CONST_FIXED))
+ 	++n_var;
+     }
+   if (n_var == 0)
+@@ -5286,7 +5288,9 @@
+   for (i = 0; i < n_elts; ++i)
+     {
+       x = XVECEXP (vals, 0, i);
+-      if (!CONSTANT_P (x))
++      if (!(CONST_INT_P (x)
++	    || GET_CODE (x) == CONST_DOUBLE
++	    || GET_CODE (x) == CONST_FIXED))
+ 	++n_var, one_var = i;
+       else if (x != CONST0_RTX (inner_mode))
+ 	all_const_zero = false;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch
new file mode 100644
index 0000000000..12c578c2b4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch
@@ -0,0 +1,61 @@
+2011-08-18  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-08-12  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* config/arm/arm.c (get_label_padding): New function.
+	(create_fix_barrier, arm_reorg): Use it.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-07-04 14:03:49 +0000
++++ new/gcc/config/arm/arm.c	2011-08-12 08:08:31 +0000
+@@ -11769,6 +11769,19 @@
+   return 0;
+ }
+ 
++/* Return the maximum amount of padding that will be inserted before
++   label LABEL.  */
++
++static HOST_WIDE_INT
++get_label_padding (rtx label)
++{
++  HOST_WIDE_INT align, min_insn_size;
++
++  align = 1 << label_to_alignment (label);
++  min_insn_size = TARGET_THUMB ? 2 : 4;
++  return align > min_insn_size ? align - min_insn_size : 0;
++}
++
+ /* Move a minipool fix MP from its current location to before MAX_MP.
+    If MAX_MP is NULL, then MP doesn't need moving, but the addressing
+    constraints may need updating.  */
+@@ -12315,8 +12328,12 @@
+ 	 within range.  */
+       gcc_assert (GET_CODE (from) != BARRIER);
+ 
+-      /* Count the length of this insn.  */
+-      count += get_attr_length (from);
++      /* Count the length of this insn.  This must stay in sync with the
++	 code that pushes minipool fixes.  */
++      if (LABEL_P (from))
++	count += get_label_padding (from);
++      else
++	count += get_attr_length (from);
+ 
+       /* If there is a jump table, add its length.  */
+       tmp = is_jump_table (from);
+@@ -12736,6 +12753,11 @@
+ 	      insn = table;
+ 	    }
+ 	}
++      else if (LABEL_P (insn))
++	/* Add the worst-case padding due to alignment.  We don't add
++	   the _current_ padding because the minipool insertions
++	   themselves might change it.  */
++	address += get_label_padding (insn);
+     }
+ 
+   fix = minipool_fix_head;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch
new file mode 100644
index 0000000000..29663c64a0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch
@@ -0,0 +1,2648 @@
+2011-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (arm_init_neon_builtins): Use 
+	n_operands instead of n_generator_args.
+
+2011-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline
+	2011-04-18  Jie Zhang  <jie@codesourcery.com>
+	Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.c (neon_builtin_type_bits): Remove.
+	(typedef enum neon_builtin_mode): New.
+	(T_MAX): Don't define.
+	(typedef enum neon_builtin_datum): Remove bits, codes[],
+	num_vars and base_fcode.  Add mode, code and fcode.
+	(VAR1, VAR2, VAR3, VAR4, VAR5, VAR6, VAR7, VAR8, VAR9
+	VAR10): Change accordingly.
+	(neon_builtin_data[]): Change accordingly
+	(arm_init_neon_builtins): Change accordingly.
+	(neon_builtin_compare): Remove.
+	(locate_neon_builtin_icode): Remove.
+	(arm_expand_neon_builtin): Change accordingly.
+
+	* arm.h (enum arm_builtins): Move to ...
+	* arm.c (enum arm_builtins): ... here; and rearrange builtin code.
+
+	* arm.c (arm_builtin_decl): Declare.
+	(TARGET_BUILTIN_DECL): Define.
+	(enum arm_builtins): Correct ARM_BUILTIN_MAX.
+	(arm_builtin_decls[]): New.
+	(arm_init_neon_builtins): Store builtin declarations in
+	arm_builtin_decls[].
+	(arm_init_tls_builtins): Likewise.
+	(arm_init_iwmmxt_builtins): Likewise.  Refactor initialization code.
+	(arm_builtin_decl): New.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-08-18 13:53:37 +0000
++++ new/gcc/config/arm/arm.c	2011-08-24 17:35:16 +0000
+@@ -162,6 +162,7 @@
+ static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
+ static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
+ static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
++static tree arm_builtin_decl (unsigned, bool);
+ static void emit_constant_insn (rtx cond, rtx pattern);
+ static rtx emit_set_insn (rtx, rtx);
+ static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
+@@ -415,6 +416,8 @@
+ #define TARGET_INIT_BUILTINS  arm_init_builtins
+ #undef  TARGET_EXPAND_BUILTIN
+ #define TARGET_EXPAND_BUILTIN arm_expand_builtin
++#undef  TARGET_BUILTIN_DECL
++#define TARGET_BUILTIN_DECL arm_builtin_decl
+ 
+ #undef TARGET_INIT_LIBFUNCS
+ #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
+@@ -18147,505 +18150,31 @@
+   return value;
+ }
+ 
+-#define def_mbuiltin(MASK, NAME, TYPE, CODE)				\
+-  do									\
+-    {									\
+-      if ((MASK) & insn_flags)						\
+-        add_builtin_function ((NAME), (TYPE), (CODE),			\
+-			     BUILT_IN_MD, NULL, NULL_TREE);		\
+-    }									\
+-  while (0)
+-
+-struct builtin_description
+-{
+-  const unsigned int       mask;
+-  const enum insn_code     icode;
+-  const char * const       name;
+-  const enum arm_builtins  code;
+-  const enum rtx_code      comparison;
+-  const unsigned int       flag;
+-};
+-
+-static const struct builtin_description bdesc_2arg[] =
+-{
+-#define IWMMXT_BUILTIN(code, string, builtin) \
+-  { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
+-    ARM_BUILTIN_##builtin, UNKNOWN, 0 },
+-
+-  IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
+-  IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
+-  IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
+-  IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
+-  IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
+-  IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
+-  IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
+-  IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
+-  IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
+-  IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
+-  IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
+-  IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
+-  IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
+-  IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
+-  IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
+-  IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
+-  IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
+-  IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
+-  IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
+-  IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
+-  IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
+-  IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
+-  IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
+-  IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
+-  IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
+-  IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
+-  IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
+-  IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
+-  IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
+-  IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
+-  IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
+-  IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
+-  IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
+-  IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
+-  IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
+-  IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
+-  IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
+-  IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
+-  IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
+-  IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
+-  IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
+-  IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
+-  IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
+-  IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
+-  IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
+-  IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
+-  IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
+-  IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
+-  IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
+-  IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
+-  IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
+-  IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
+-
+-#define IWMMXT_BUILTIN2(code, builtin) \
+-  { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
+-
+-  IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
+-  IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
+-  IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
+-  IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
+-  IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
+-  IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
+-  IWMMXT_BUILTIN2 (ashlv4hi3_di,    WSLLH)
+-  IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
+-  IWMMXT_BUILTIN2 (ashlv2si3_di,    WSLLW)
+-  IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
+-  IWMMXT_BUILTIN2 (ashldi3_di,      WSLLD)
+-  IWMMXT_BUILTIN2 (ashldi3_iwmmxt,  WSLLDI)
+-  IWMMXT_BUILTIN2 (lshrv4hi3_di,    WSRLH)
+-  IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
+-  IWMMXT_BUILTIN2 (lshrv2si3_di,    WSRLW)
+-  IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
+-  IWMMXT_BUILTIN2 (lshrdi3_di,      WSRLD)
+-  IWMMXT_BUILTIN2 (lshrdi3_iwmmxt,  WSRLDI)
+-  IWMMXT_BUILTIN2 (ashrv4hi3_di,    WSRAH)
+-  IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
+-  IWMMXT_BUILTIN2 (ashrv2si3_di,    WSRAW)
+-  IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
+-  IWMMXT_BUILTIN2 (ashrdi3_di,      WSRAD)
+-  IWMMXT_BUILTIN2 (ashrdi3_iwmmxt,  WSRADI)
+-  IWMMXT_BUILTIN2 (rorv4hi3_di,     WRORH)
+-  IWMMXT_BUILTIN2 (rorv4hi3,        WRORHI)
+-  IWMMXT_BUILTIN2 (rorv2si3_di,     WRORW)
+-  IWMMXT_BUILTIN2 (rorv2si3,        WRORWI)
+-  IWMMXT_BUILTIN2 (rordi3_di,       WRORD)
+-  IWMMXT_BUILTIN2 (rordi3,          WRORDI)
+-  IWMMXT_BUILTIN2 (iwmmxt_wmacuz,   WMACUZ)
+-  IWMMXT_BUILTIN2 (iwmmxt_wmacsz,   WMACSZ)
+-};
+-
+-static const struct builtin_description bdesc_1arg[] =
+-{
+-  IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
+-  IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
+-  IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
+-  IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
+-  IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
+-  IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
+-  IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
+-};
+-
+-/* Set up all the iWMMXt builtins.  This is
+-   not called if TARGET_IWMMXT is zero.  */
+-
+-static void
+-arm_init_iwmmxt_builtins (void)
+-{
+-  const struct builtin_description * d;
+-  size_t i;
+-  tree endlink = void_list_node;
+-
+-  tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
+-  tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
+-  tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
+-
+-  tree int_ftype_int
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, integer_type_node, endlink));
+-  tree v8qi_ftype_v8qi_v8qi_int
+-    = build_function_type (V8QI_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      tree_cons (NULL_TREE, V8QI_type_node,
+-						 tree_cons (NULL_TREE,
+-							    integer_type_node,
+-							    endlink))));
+-  tree v4hi_ftype_v4hi_int
+-    = build_function_type (V4HI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree v2si_ftype_v2si_int
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree v2si_ftype_di_di
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, long_long_integer_type_node,
+-				      tree_cons (NULL_TREE, long_long_integer_type_node,
+-						 endlink)));
+-  tree di_ftype_di_int
+-    = build_function_type (long_long_integer_type_node,
+-			   tree_cons (NULL_TREE, long_long_integer_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree di_ftype_di_int_int
+-    = build_function_type (long_long_integer_type_node,
+-			   tree_cons (NULL_TREE, long_long_integer_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 tree_cons (NULL_TREE,
+-							    integer_type_node,
+-							    endlink))));
+-  tree int_ftype_v8qi
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      endlink));
+-  tree int_ftype_v4hi
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      endlink));
+-  tree int_ftype_v2si
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      endlink));
+-  tree int_ftype_v8qi_int
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree int_ftype_v4hi_int
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree int_ftype_v2si_int
+-    = build_function_type (integer_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree v8qi_ftype_v8qi_int_int
+-    = build_function_type (V8QI_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 tree_cons (NULL_TREE,
+-							    integer_type_node,
+-							    endlink))));
+-  tree v4hi_ftype_v4hi_int_int
+-    = build_function_type (V4HI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 tree_cons (NULL_TREE,
+-							    integer_type_node,
+-							    endlink))));
+-  tree v2si_ftype_v2si_int_int
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 tree_cons (NULL_TREE,
+-							    integer_type_node,
+-							    endlink))));
+-  /* Miscellaneous.  */
+-  tree v8qi_ftype_v4hi_v4hi
+-    = build_function_type (V8QI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, V4HI_type_node,
+-						 endlink)));
+-  tree v4hi_ftype_v2si_v2si
+-    = build_function_type (V4HI_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      tree_cons (NULL_TREE, V2SI_type_node,
+-						 endlink)));
+-  tree v2si_ftype_v4hi_v4hi
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, V4HI_type_node,
+-						 endlink)));
+-  tree v2si_ftype_v8qi_v8qi
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      tree_cons (NULL_TREE, V8QI_type_node,
+-						 endlink)));
+-  tree v4hi_ftype_v4hi_di
+-    = build_function_type (V4HI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE,
+-						 long_long_integer_type_node,
+-						 endlink)));
+-  tree v2si_ftype_v2si_di
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      tree_cons (NULL_TREE,
+-						 long_long_integer_type_node,
+-						 endlink)));
+-  tree void_ftype_int_int
+-    = build_function_type (void_type_node,
+-			   tree_cons (NULL_TREE, integer_type_node,
+-				      tree_cons (NULL_TREE, integer_type_node,
+-						 endlink)));
+-  tree di_ftype_void
+-    = build_function_type (long_long_unsigned_type_node, endlink);
+-  tree di_ftype_v8qi
+-    = build_function_type (long_long_integer_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      endlink));
+-  tree di_ftype_v4hi
+-    = build_function_type (long_long_integer_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      endlink));
+-  tree di_ftype_v2si
+-    = build_function_type (long_long_integer_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      endlink));
+-  tree v2si_ftype_v4hi
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      endlink));
+-  tree v4hi_ftype_v8qi
+-    = build_function_type (V4HI_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      endlink));
+-
+-  tree di_ftype_di_v4hi_v4hi
+-    = build_function_type (long_long_unsigned_type_node,
+-			   tree_cons (NULL_TREE,
+-				      long_long_unsigned_type_node,
+-				      tree_cons (NULL_TREE, V4HI_type_node,
+-						 tree_cons (NULL_TREE,
+-							    V4HI_type_node,
+-							    endlink))));
+-
+-  tree di_ftype_v4hi_v4hi
+-    = build_function_type (long_long_unsigned_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, V4HI_type_node,
+-						 endlink)));
+-
+-  /* Normal vector binops.  */
+-  tree v8qi_ftype_v8qi_v8qi
+-    = build_function_type (V8QI_type_node,
+-			   tree_cons (NULL_TREE, V8QI_type_node,
+-				      tree_cons (NULL_TREE, V8QI_type_node,
+-						 endlink)));
+-  tree v4hi_ftype_v4hi_v4hi
+-    = build_function_type (V4HI_type_node,
+-			   tree_cons (NULL_TREE, V4HI_type_node,
+-				      tree_cons (NULL_TREE, V4HI_type_node,
+-						 endlink)));
+-  tree v2si_ftype_v2si_v2si
+-    = build_function_type (V2SI_type_node,
+-			   tree_cons (NULL_TREE, V2SI_type_node,
+-				      tree_cons (NULL_TREE, V2SI_type_node,
+-						 endlink)));
+-  tree di_ftype_di_di
+-    = build_function_type (long_long_unsigned_type_node,
+-			   tree_cons (NULL_TREE, long_long_unsigned_type_node,
+-				      tree_cons (NULL_TREE,
+-						 long_long_unsigned_type_node,
+-						 endlink)));
+-
+-  /* Add all builtins that are more or less simple operations on two
+-     operands.  */
+-  for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
+-    {
+-      /* Use one of the operands; the target can have a different mode for
+-	 mask-generating compares.  */
+-      enum machine_mode mode;
+-      tree type;
+-
+-      if (d->name == 0)
+-	continue;
+-
+-      mode = insn_data[d->icode].operand[1].mode;
+-
+-      switch (mode)
+-	{
+-	case V8QImode:
+-	  type = v8qi_ftype_v8qi_v8qi;
+-	  break;
+-	case V4HImode:
+-	  type = v4hi_ftype_v4hi_v4hi;
+-	  break;
+-	case V2SImode:
+-	  type = v2si_ftype_v2si_v2si;
+-	  break;
+-	case DImode:
+-	  type = di_ftype_di_di;
+-	  break;
+-
+-	default:
+-	  gcc_unreachable ();
+-	}
+-
+-      def_mbuiltin (d->mask, d->name, type, d->code);
+-    }
+-
+-  /* Add the remaining MMX insns with somewhat more complicated types.  */
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
+-
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
+-  def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
+-}
+-
+-static void
+-arm_init_tls_builtins (void)
+-{
+-  tree ftype, decl;
+-
+-  ftype = build_function_type (ptr_type_node, void_list_node);
+-  decl = add_builtin_function ("__builtin_thread_pointer", ftype,
+-			       ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
+-			       NULL, NULL_TREE);
+-  TREE_NOTHROW (decl) = 1;
+-  TREE_READONLY (decl) = 1;
+-}
+-
+-enum neon_builtin_type_bits {
+-  T_V8QI  = 0x0001,
+-  T_V4HI  = 0x0002,
+-  T_V2SI  = 0x0004,
+-  T_V2SF  = 0x0008,
+-  T_DI    = 0x0010,
+-  T_DREG  = 0x001F,
+-  T_V16QI = 0x0020,
+-  T_V8HI  = 0x0040,
+-  T_V4SI  = 0x0080,
+-  T_V4SF  = 0x0100,
+-  T_V2DI  = 0x0200,
+-  T_TI	  = 0x0400,
+-  T_QREG  = 0x07E0,
+-  T_EI	  = 0x0800,
+-  T_OI	  = 0x1000
+-};
++typedef enum {
++  T_V8QI,
++  T_V4HI,
++  T_V2SI,
++  T_V2SF,
++  T_DI,
++  T_V16QI,
++  T_V8HI,
++  T_V4SI,
++  T_V4SF,
++  T_V2DI,
++  T_TI,
++  T_EI,
++  T_OI,
++  T_MAX		/* Size of enum.  Keep last.  */
++} neon_builtin_type_mode;
++
++#define TYPE_MODE_BIT(X) (1 << (X))
++
++#define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI)	\
++		 | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF)	\
++		 | TYPE_MODE_BIT (T_DI))
++#define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI)	\
++		 | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF)	\
++		 | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
+ 
+ #define v8qi_UP  T_V8QI
+ #define v4hi_UP  T_V4HI
+@@ -18663,8 +18192,6 @@
+ 
+ #define UP(X) X##_UP
+ 
+-#define T_MAX 13
+-
+ typedef enum {
+   NEON_BINOP,
+   NEON_TERNOP,
+@@ -18708,49 +18235,42 @@
+ typedef struct {
+   const char *name;
+   const neon_itype itype;
+-  const int bits;
+-  const enum insn_code codes[T_MAX];
+-  const unsigned int num_vars;
+-  unsigned int base_fcode;
++  const neon_builtin_type_mode mode;
++  const enum insn_code code;
++  unsigned int fcode;
+ } neon_builtin_datum;
+ 
+ #define CF(N,X) CODE_FOR_neon_##N##X
+ 
+ #define VAR1(T, N, A) \
+-  #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0
++  {#N, NEON_##T, UP (A), CF (N, A), 0}
+ #define VAR2(T, N, A, B) \
+-  #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0
++  VAR1 (T, N, A), \
++  {#N, NEON_##T, UP (B), CF (N, B), 0}
+ #define VAR3(T, N, A, B, C) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C), \
+-  { CF (N, A), CF (N, B), CF (N, C) }, 3, 0
++  VAR2 (T, N, A, B), \
++  {#N, NEON_##T, UP (C), CF (N, C), 0}
+ #define VAR4(T, N, A, B, C, D) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0
++  VAR3 (T, N, A, B, C), \
++  {#N, NEON_##T, UP (D), CF (N, D), 0}
+ #define VAR5(T, N, A, B, C, D, E) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0
++  VAR4 (T, N, A, B, C, D), \
++  {#N, NEON_##T, UP (E), CF (N, E), 0}
+ #define VAR6(T, N, A, B, C, D, E, F) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0
++  VAR5 (T, N, A, B, C, D, E), \
++  {#N, NEON_##T, UP (F), CF (N, F), 0}
+ #define VAR7(T, N, A, B, C, D, E, F, G) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
+-    CF (N, G) }, 7, 0
++  VAR6 (T, N, A, B, C, D, E, F), \
++  {#N, NEON_##T, UP (G), CF (N, G), 0}
+ #define VAR8(T, N, A, B, C, D, E, F, G, H) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
+-                | UP (H), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
+-    CF (N, G), CF (N, H) }, 8, 0
++  VAR7 (T, N, A, B, C, D, E, F, G), \
++  {#N, NEON_##T, UP (H), CF (N, H), 0}
+ #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
+-                | UP (H) | UP (I), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
+-    CF (N, G), CF (N, H), CF (N, I) }, 9, 0
++  VAR8 (T, N, A, B, C, D, E, F, G, H), \
++  {#N, NEON_##T, UP (I), CF (N, I), 0}
+ #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
+-  #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
+-                | UP (H) | UP (I) | UP (J), \
+-  { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
+-    CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0
++  VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
++  {#N, NEON_##T, UP (J), CF (N, J), 0}
+ 
+ /* The mode entries in the following table correspond to the "key" type of the
+    instruction variant, i.e. equivalent to that which would be specified after
+@@ -18758,192 +18278,190 @@
+    (Signed/unsigned/polynomial types are not differentiated between though, and
+    are all mapped onto the same mode for a given element size.) The modes
+    listed per instruction should be the same as those defined for that
+-   instruction's pattern in neon.md.
+-   WARNING: Variants should be listed in the same increasing order as
+-   neon_builtin_type_bits.  */
++   instruction's pattern in neon.md.  */
+ 
+ static neon_builtin_datum neon_builtin_data[] =
+ {
+-  { VAR10 (BINOP, vadd,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) },
+-  { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) },
+-  { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) },
+-  { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) },
+-  { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) },
+-  { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) },
+-  { VAR2 (TERNOP, vqdmlal, v4hi, v2si) },
+-  { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) },
+-  { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) },
+-  { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) },
+-  { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) },
+-  { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) },
+-  { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) },
+-  { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) },
+-  { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) },
+-  { VAR2 (BINOP, vqdmull, v4hi, v2si) },
+-  { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) },
+-  { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) },
+-  { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) },
+-  { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) },
+-  { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR10 (BINOP, vsub,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) },
+-  { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) },
+-  { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) },
+-  { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR2 (BINOP, vcage, v2sf, v4sf) },
+-  { VAR2 (BINOP, vcagt, v2sf, v4sf) },
+-  { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) },
+-  { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) },
+-  { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) },
+-  { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) },
+-  { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) },
+-  { VAR2 (BINOP, vrecps, v2sf, v4sf) },
+-  { VAR2 (BINOP, vrsqrts, v2sf, v4sf) },
+-  { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
+-  { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
+-  { VAR2 (UNOP, vcnt, v8qi, v16qi) },
+-  { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) },
+-  { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) },
+-  { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
++  VAR10 (BINOP, vadd,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
++  VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
++  VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
++  VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si),
++  VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si),
++  VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
++  VAR2 (TERNOP, vqdmlal, v4hi, v2si),
++  VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
++  VAR3 (BINOP, vmull, v8qi, v4hi, v2si),
++  VAR2 (SCALARMULL, vmull_n, v4hi, v2si),
++  VAR2 (LANEMULL, vmull_lane, v4hi, v2si),
++  VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
++  VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
++  VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
++  VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
++  VAR2 (BINOP, vqdmull, v4hi, v2si),
++  VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
++  VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di),
++  VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
++  VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
++  VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR10 (BINOP, vsub,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
++  VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
++  VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
++  VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR2 (BINOP, vcage, v2sf, v4sf),
++  VAR2 (BINOP, vcagt, v2sf, v4sf),
++  VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR3 (BINOP, vabdl, v8qi, v4hi, v2si),
++  VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR3 (TERNOP, vabal, v8qi, v4hi, v2si),
++  VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
++  VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf),
++  VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf),
++  VAR2 (BINOP, vrecps, v2sf, v4sf),
++  VAR2 (BINOP, vrsqrts, v2sf, v4sf),
++  VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
++  VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
++  VAR2 (UNOP, vcnt, v8qi, v16qi),
++  VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
++  VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
++  VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
+   /* FIXME: vget_lane supports more variants than this!  */
+-  { VAR10 (GETLANE, vget_lane,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (SETLANE, vset_lane,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR10 (DUP, vdup_n,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (DUPLANE, vdup_lane,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) },
+-  { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) },
+-  { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) },
+-  { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) },
+-  { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) },
+-  { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) },
+-  { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) },
+-  { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) },
+-  { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) },
+-  { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) },
+-  { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) },
+-  { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) },
+-  { VAR10 (BINOP, vext,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) },
+-  { VAR2 (UNOP, vrev16, v8qi, v16qi) },
+-  { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) },
+-  { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) },
+-  { VAR10 (SELECT, vbsl,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR1 (VTBL, vtbl1, v8qi) },
+-  { VAR1 (VTBL, vtbl2, v8qi) },
+-  { VAR1 (VTBL, vtbl3, v8qi) },
+-  { VAR1 (VTBL, vtbl4, v8qi) },
+-  { VAR1 (VTBX, vtbx1, v8qi) },
+-  { VAR1 (VTBX, vtbx2, v8qi) },
+-  { VAR1 (VTBX, vtbx3, v8qi) },
+-  { VAR1 (VTBX, vtbx4, v8qi) },
+-  { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
+-  { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (LOAD1, vld1,
+-           v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (LOAD1LANE, vld1_lane,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (LOAD1, vld1_dup,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (STORE1, vst1,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (STORE1LANE, vst1_lane,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR9 (LOADSTRUCT,
+-	  vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
+-  { VAR7 (LOADSTRUCTLANE, vld2_lane,
+-	  v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR9 (STORESTRUCT, vst2,
+-	  v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
+-  { VAR7 (STORESTRUCTLANE, vst2_lane,
+-	  v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR9 (LOADSTRUCT,
+-	  vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
+-  { VAR7 (LOADSTRUCTLANE, vld3_lane,
+-	  v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR9 (STORESTRUCT, vst3,
+-	  v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
+-  { VAR7 (STORESTRUCTLANE, vst3_lane,
+-	  v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR9 (LOADSTRUCT, vld4,
+-	  v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
+-  { VAR7 (LOADSTRUCTLANE, vld4_lane,
+-	  v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) },
+-  { VAR9 (STORESTRUCT, vst4,
+-	  v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
+-  { VAR7 (STORESTRUCTLANE, vst4_lane,
+-	  v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
+-  { VAR10 (LOGICBINOP, vand,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (LOGICBINOP, vorr,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (BINOP, veor,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (LOGICBINOP, vbic,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
+-  { VAR10 (LOGICBINOP, vorn,
+-	   v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }
++  VAR10 (GETLANE, vget_lane,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (SETLANE, vset_lane,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
++  VAR10 (DUP, vdup_n,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (DUPLANE, vdup_lane,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
++  VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
++  VAR3 (UNOP, vqmovn, v8hi, v4si, v2di),
++  VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
++  VAR3 (UNOP, vmovl, v8qi, v4hi, v2si),
++  VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR2 (LANEMAC, vmlal_lane, v4hi, v2si),
++  VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
++  VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si),
++  VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
++  VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR2 (SCALARMAC, vmlal_n, v4hi, v2si),
++  VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
++  VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si),
++  VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
++  VAR10 (BINOP, vext,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
++  VAR2 (UNOP, vrev16, v8qi, v16qi),
++  VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf),
++  VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf),
++  VAR10 (SELECT, vbsl,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR1 (VTBL, vtbl1, v8qi),
++  VAR1 (VTBL, vtbl2, v8qi),
++  VAR1 (VTBL, vtbl3, v8qi),
++  VAR1 (VTBL, vtbl4, v8qi),
++  VAR1 (VTBX, vtbx1, v8qi),
++  VAR1 (VTBX, vtbx2, v8qi),
++  VAR1 (VTBX, vtbx3, v8qi),
++  VAR1 (VTBX, vtbx4, v8qi),
++  VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
++  VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
++  VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
++  VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
++  VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
++  VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
++  VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (LOAD1, vld1,
++         v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (LOAD1LANE, vld1_lane,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (LOAD1, vld1_dup,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (STORE1, vst1,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (STORE1LANE, vst1_lane,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR9 (LOADSTRUCT,
++	vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
++  VAR7 (LOADSTRUCTLANE, vld2_lane,
++	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di),
++  VAR9 (STORESTRUCT, vst2,
++	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
++  VAR7 (STORESTRUCTLANE, vst2_lane,
++	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR9 (LOADSTRUCT,
++	vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
++  VAR7 (LOADSTRUCTLANE, vld3_lane,
++	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di),
++  VAR9 (STORESTRUCT, vst3,
++	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
++  VAR7 (STORESTRUCTLANE, vst3_lane,
++	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR9 (LOADSTRUCT, vld4,
++	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
++  VAR7 (LOADSTRUCTLANE, vld4_lane,
++	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
++  VAR9 (STORESTRUCT, vst4,
++	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
++  VAR7 (STORESTRUCTLANE, vst4_lane,
++	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
++  VAR10 (LOGICBINOP, vand,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (LOGICBINOP, vorr,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (BINOP, veor,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (LOGICBINOP, vbic,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
++  VAR10 (LOGICBINOP, vorn,
++	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+ };
+ 
+ #undef CF
+@@ -18958,10 +18476,185 @@
+ #undef VAR9
+ #undef VAR10
+ 
++/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
++   symbolic names defined here (which would require too much duplication).
++   FIXME?  */
++enum arm_builtins
++{
++  ARM_BUILTIN_GETWCX,
++  ARM_BUILTIN_SETWCX,
++
++  ARM_BUILTIN_WZERO,
++
++  ARM_BUILTIN_WAVG2BR,
++  ARM_BUILTIN_WAVG2HR,
++  ARM_BUILTIN_WAVG2B,
++  ARM_BUILTIN_WAVG2H,
++
++  ARM_BUILTIN_WACCB,
++  ARM_BUILTIN_WACCH,
++  ARM_BUILTIN_WACCW,
++
++  ARM_BUILTIN_WMACS,
++  ARM_BUILTIN_WMACSZ,
++  ARM_BUILTIN_WMACU,
++  ARM_BUILTIN_WMACUZ,
++
++  ARM_BUILTIN_WSADB,
++  ARM_BUILTIN_WSADBZ,
++  ARM_BUILTIN_WSADH,
++  ARM_BUILTIN_WSADHZ,
++
++  ARM_BUILTIN_WALIGN,
++
++  ARM_BUILTIN_TMIA,
++  ARM_BUILTIN_TMIAPH,
++  ARM_BUILTIN_TMIABB,
++  ARM_BUILTIN_TMIABT,
++  ARM_BUILTIN_TMIATB,
++  ARM_BUILTIN_TMIATT,
++
++  ARM_BUILTIN_TMOVMSKB,
++  ARM_BUILTIN_TMOVMSKH,
++  ARM_BUILTIN_TMOVMSKW,
++
++  ARM_BUILTIN_TBCSTB,
++  ARM_BUILTIN_TBCSTH,
++  ARM_BUILTIN_TBCSTW,
++
++  ARM_BUILTIN_WMADDS,
++  ARM_BUILTIN_WMADDU,
++
++  ARM_BUILTIN_WPACKHSS,
++  ARM_BUILTIN_WPACKWSS,
++  ARM_BUILTIN_WPACKDSS,
++  ARM_BUILTIN_WPACKHUS,
++  ARM_BUILTIN_WPACKWUS,
++  ARM_BUILTIN_WPACKDUS,
++
++  ARM_BUILTIN_WADDB,
++  ARM_BUILTIN_WADDH,
++  ARM_BUILTIN_WADDW,
++  ARM_BUILTIN_WADDSSB,
++  ARM_BUILTIN_WADDSSH,
++  ARM_BUILTIN_WADDSSW,
++  ARM_BUILTIN_WADDUSB,
++  ARM_BUILTIN_WADDUSH,
++  ARM_BUILTIN_WADDUSW,
++  ARM_BUILTIN_WSUBB,
++  ARM_BUILTIN_WSUBH,
++  ARM_BUILTIN_WSUBW,
++  ARM_BUILTIN_WSUBSSB,
++  ARM_BUILTIN_WSUBSSH,
++  ARM_BUILTIN_WSUBSSW,
++  ARM_BUILTIN_WSUBUSB,
++  ARM_BUILTIN_WSUBUSH,
++  ARM_BUILTIN_WSUBUSW,
++
++  ARM_BUILTIN_WAND,
++  ARM_BUILTIN_WANDN,
++  ARM_BUILTIN_WOR,
++  ARM_BUILTIN_WXOR,
++
++  ARM_BUILTIN_WCMPEQB,
++  ARM_BUILTIN_WCMPEQH,
++  ARM_BUILTIN_WCMPEQW,
++  ARM_BUILTIN_WCMPGTUB,
++  ARM_BUILTIN_WCMPGTUH,
++  ARM_BUILTIN_WCMPGTUW,
++  ARM_BUILTIN_WCMPGTSB,
++  ARM_BUILTIN_WCMPGTSH,
++  ARM_BUILTIN_WCMPGTSW,
++
++  ARM_BUILTIN_TEXTRMSB,
++  ARM_BUILTIN_TEXTRMSH,
++  ARM_BUILTIN_TEXTRMSW,
++  ARM_BUILTIN_TEXTRMUB,
++  ARM_BUILTIN_TEXTRMUH,
++  ARM_BUILTIN_TEXTRMUW,
++  ARM_BUILTIN_TINSRB,
++  ARM_BUILTIN_TINSRH,
++  ARM_BUILTIN_TINSRW,
++
++  ARM_BUILTIN_WMAXSW,
++  ARM_BUILTIN_WMAXSH,
++  ARM_BUILTIN_WMAXSB,
++  ARM_BUILTIN_WMAXUW,
++  ARM_BUILTIN_WMAXUH,
++  ARM_BUILTIN_WMAXUB,
++  ARM_BUILTIN_WMINSW,
++  ARM_BUILTIN_WMINSH,
++  ARM_BUILTIN_WMINSB,
++  ARM_BUILTIN_WMINUW,
++  ARM_BUILTIN_WMINUH,
++  ARM_BUILTIN_WMINUB,
++
++  ARM_BUILTIN_WMULUM,
++  ARM_BUILTIN_WMULSM,
++  ARM_BUILTIN_WMULUL,
++
++  ARM_BUILTIN_PSADBH,
++  ARM_BUILTIN_WSHUFH,
++
++  ARM_BUILTIN_WSLLH,
++  ARM_BUILTIN_WSLLW,
++  ARM_BUILTIN_WSLLD,
++  ARM_BUILTIN_WSRAH,
++  ARM_BUILTIN_WSRAW,
++  ARM_BUILTIN_WSRAD,
++  ARM_BUILTIN_WSRLH,
++  ARM_BUILTIN_WSRLW,
++  ARM_BUILTIN_WSRLD,
++  ARM_BUILTIN_WRORH,
++  ARM_BUILTIN_WRORW,
++  ARM_BUILTIN_WRORD,
++  ARM_BUILTIN_WSLLHI,
++  ARM_BUILTIN_WSLLWI,
++  ARM_BUILTIN_WSLLDI,
++  ARM_BUILTIN_WSRAHI,
++  ARM_BUILTIN_WSRAWI,
++  ARM_BUILTIN_WSRADI,
++  ARM_BUILTIN_WSRLHI,
++  ARM_BUILTIN_WSRLWI,
++  ARM_BUILTIN_WSRLDI,
++  ARM_BUILTIN_WRORHI,
++  ARM_BUILTIN_WRORWI,
++  ARM_BUILTIN_WRORDI,
++
++  ARM_BUILTIN_WUNPCKIHB,
++  ARM_BUILTIN_WUNPCKIHH,
++  ARM_BUILTIN_WUNPCKIHW,
++  ARM_BUILTIN_WUNPCKILB,
++  ARM_BUILTIN_WUNPCKILH,
++  ARM_BUILTIN_WUNPCKILW,
++
++  ARM_BUILTIN_WUNPCKEHSB,
++  ARM_BUILTIN_WUNPCKEHSH,
++  ARM_BUILTIN_WUNPCKEHSW,
++  ARM_BUILTIN_WUNPCKEHUB,
++  ARM_BUILTIN_WUNPCKEHUH,
++  ARM_BUILTIN_WUNPCKEHUW,
++  ARM_BUILTIN_WUNPCKELSB,
++  ARM_BUILTIN_WUNPCKELSH,
++  ARM_BUILTIN_WUNPCKELSW,
++  ARM_BUILTIN_WUNPCKELUB,
++  ARM_BUILTIN_WUNPCKELUH,
++  ARM_BUILTIN_WUNPCKELUW,
++
++  ARM_BUILTIN_THREAD_POINTER,
++
++  ARM_BUILTIN_NEON_BASE,
++
++  ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data)
++};
++
++static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX];
++
+ static void
+ arm_init_neon_builtins (void)
+ {
+-  unsigned int i, fcode = ARM_BUILTIN_NEON_BASE;
++  unsigned int i, fcode;
++  tree decl;
+ 
+   tree neon_intQI_type_node;
+   tree neon_intHI_type_node;
+@@ -19209,250 +18902,740 @@
+         }
+     }
+ 
+-  for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++)
++  for (i = 0, fcode = ARM_BUILTIN_NEON_BASE;
++       i < ARRAY_SIZE (neon_builtin_data);
++       i++, fcode++)
+     {
+       neon_builtin_datum *d = &neon_builtin_data[i];
+-      unsigned int j, codeidx = 0;
+-
+-      d->base_fcode = fcode;
+-
+-      for (j = 0; j < T_MAX; j++)
+-	{
+-	  const char* const modenames[] = {
+-	    "v8qi", "v4hi", "v2si", "v2sf", "di",
+-	    "v16qi", "v8hi", "v4si", "v4sf", "v2di"
+-	  };
+-	  char namebuf[60];
+-	  tree ftype = NULL;
+-	  enum insn_code icode;
+-	  int is_load = 0, is_store = 0;
+-
+-          if ((d->bits & (1 << j)) == 0)
+-            continue;
+-
+-          icode = d->codes[codeidx++];
+-
+-          switch (d->itype)
+-            {
+-	    case NEON_LOAD1:
+-	    case NEON_LOAD1LANE:
+-	    case NEON_LOADSTRUCT:
+-	    case NEON_LOADSTRUCTLANE:
+-	      is_load = 1;
+-	      /* Fall through.  */
+-	    case NEON_STORE1:
+-	    case NEON_STORE1LANE:
+-	    case NEON_STORESTRUCT:
+-	    case NEON_STORESTRUCTLANE:
+-	      if (!is_load)
+-	        is_store = 1;
+-	      /* Fall through.  */
+-            case NEON_UNOP:
+-	    case NEON_BINOP:
+-	    case NEON_LOGICBINOP:
+-	    case NEON_SHIFTINSERT:
+-	    case NEON_TERNOP:
+-	    case NEON_GETLANE:
+-	    case NEON_SETLANE:
+-	    case NEON_CREATE:
+-	    case NEON_DUP:
+-	    case NEON_DUPLANE:
+-	    case NEON_SHIFTIMM:
+-	    case NEON_SHIFTACC:
+-	    case NEON_COMBINE:
+-	    case NEON_SPLIT:
+-	    case NEON_CONVERT:
+-	    case NEON_FIXCONV:
+-	    case NEON_LANEMUL:
+-	    case NEON_LANEMULL:
+-	    case NEON_LANEMULH:
+-	    case NEON_LANEMAC:
+-	    case NEON_SCALARMUL:
+-	    case NEON_SCALARMULL:
+-	    case NEON_SCALARMULH:
+-	    case NEON_SCALARMAC:
+-	    case NEON_SELECT:
+-	    case NEON_VTBL:
+-	    case NEON_VTBX:
+-	      {
+-		int k;
+-		tree return_type = void_type_node, args = void_list_node;
+-
+-		/* Build a function type directly from the insn_data for this
+-		   builtin.  The build_function_type() function takes care of
+-		   removing duplicates for us.  */
+-		for (k = insn_data[icode].n_operands - 1; k >= 0; k--)
+-		  {
+-		    tree eltype;
+-
+-		    if (is_load && k == 1)
+-		      {
+-		        /* Neon load patterns always have the memory operand
+-			   in the operand 1 position.  */
+-			gcc_assert (insn_data[icode].operand[k].predicate
+-				    == neon_struct_operand);
+-
+-			switch (1 << j)
+-			  {
+-			  case T_V8QI:
+-			  case T_V16QI:
+-			    eltype = const_intQI_pointer_node;
+-			    break;
+-
+-			  case T_V4HI:
+-			  case T_V8HI:
+-			    eltype = const_intHI_pointer_node;
+-			    break;
+-
+-			  case T_V2SI:
+-			  case T_V4SI:
+-			    eltype = const_intSI_pointer_node;
+-			    break;
+-
+-			  case T_V2SF:
+-			  case T_V4SF:
+-			    eltype = const_float_pointer_node;
+-			    break;
+-
+-			  case T_DI:
+-			  case T_V2DI:
+-			    eltype = const_intDI_pointer_node;
+-			    break;
+-
+-			  default: gcc_unreachable ();
+-			  }
+-  		      }
+-		    else if (is_store && k == 0)
+-		      {
+-		        /* Similarly, Neon store patterns use operand 0 as
+-			   the memory location to store to.  */
+-			gcc_assert (insn_data[icode].operand[k].predicate
+-				    == neon_struct_operand);
+-
+-			switch (1 << j)
+-			  {
+-			  case T_V8QI:
+-			  case T_V16QI:
+-			    eltype = intQI_pointer_node;
+-			    break;
+-
+-			  case T_V4HI:
+-			  case T_V8HI:
+-			    eltype = intHI_pointer_node;
+-			    break;
+-
+-			  case T_V2SI:
+-			  case T_V4SI:
+-			    eltype = intSI_pointer_node;
+-			    break;
+-
+-			  case T_V2SF:
+-			  case T_V4SF:
+-			    eltype = float_pointer_node;
+-			    break;
+-
+-			  case T_DI:
+-			  case T_V2DI:
+-			    eltype = intDI_pointer_node;
+-			    break;
+-
+-			  default: gcc_unreachable ();
+-			  }
+-		      }
+-		    else
+-		      {
+-			switch (insn_data[icode].operand[k].mode)
+-	        	  {
+-			  case VOIDmode: eltype = void_type_node; break;
+-			  /* Scalars.  */
+-			  case QImode: eltype = neon_intQI_type_node; break;
+-			  case HImode: eltype = neon_intHI_type_node; break;
+-			  case SImode: eltype = neon_intSI_type_node; break;
+-			  case SFmode: eltype = neon_float_type_node; break;
+-			  case DImode: eltype = neon_intDI_type_node; break;
+-			  case TImode: eltype = intTI_type_node; break;
+-			  case EImode: eltype = intEI_type_node; break;
+-			  case OImode: eltype = intOI_type_node; break;
+-			  case CImode: eltype = intCI_type_node; break;
+-			  case XImode: eltype = intXI_type_node; break;
+-			  /* 64-bit vectors.  */
+-			  case V8QImode: eltype = V8QI_type_node; break;
+-			  case V4HImode: eltype = V4HI_type_node; break;
+-			  case V2SImode: eltype = V2SI_type_node; break;
+-			  case V2SFmode: eltype = V2SF_type_node; break;
+-			  /* 128-bit vectors.  */
+-			  case V16QImode: eltype = V16QI_type_node; break;
+-			  case V8HImode: eltype = V8HI_type_node; break;
+-			  case V4SImode: eltype = V4SI_type_node; break;
+-			  case V4SFmode: eltype = V4SF_type_node; break;
+-			  case V2DImode: eltype = V2DI_type_node; break;
+-			  default: gcc_unreachable ();
+-			  }
+-		      }
+-
+-		    if (k == 0 && !is_store)
+-	              return_type = eltype;
+-		    else
+-		      args = tree_cons (NULL_TREE, eltype, args);
+-		  }
+-
+-		ftype = build_function_type (return_type, args);
+-	      }
+-	      break;
+-
+-	    case NEON_RESULTPAIR:
+-              {
+-                switch (insn_data[icode].operand[1].mode)
+-                  {
+-		  case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
+-                  case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
+-                  case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
+-                  case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
+-                  case DImode: ftype = void_ftype_pdi_di_di; break;
+-                  case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
+-                  case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
+-                  case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
+-                  case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
+-                  case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
+-                  default: gcc_unreachable ();
+-                  }
+-              }
+-              break;
+-
+-	    case NEON_REINTERP:
+-              {
+-                /* We iterate over 5 doubleword types, then 5 quadword
+-                   types.  */
+-                int rhs = j % 5;
+-                switch (insn_data[icode].operand[0].mode)
+-                  {
+-                  case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
+-                  case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
+-                  case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
+-                  case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
+-                  case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
+-                  case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
+-                  case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
+-                  case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
+-		  case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
+-                  case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
+-                  default: gcc_unreachable ();
+-                  }
+-              }
+-              break;
+-
+-            default:
+-              gcc_unreachable ();
+-            }
+-
+-          gcc_assert (ftype != NULL);
+-
+-          sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]);
+-
+-          add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL,
+-				NULL_TREE);
+-        }
+-    }
++
++      const char* const modenames[] = {
++	"v8qi", "v4hi", "v2si", "v2sf", "di",
++	"v16qi", "v8hi", "v4si", "v4sf", "v2di",
++	"ti", "ei", "oi"
++      };
++      char namebuf[60];
++      tree ftype = NULL;
++      int is_load = 0, is_store = 0;
++
++      gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
++
++      d->fcode = fcode;
++
++      switch (d->itype)
++	{
++	case NEON_LOAD1:
++	case NEON_LOAD1LANE:
++	case NEON_LOADSTRUCT:
++	case NEON_LOADSTRUCTLANE:
++	  is_load = 1;
++	  /* Fall through.  */
++	case NEON_STORE1:
++	case NEON_STORE1LANE:
++	case NEON_STORESTRUCT:
++	case NEON_STORESTRUCTLANE:
++	  if (!is_load)
++	    is_store = 1;
++	  /* Fall through.  */
++	case NEON_UNOP:
++	case NEON_BINOP:
++	case NEON_LOGICBINOP:
++	case NEON_SHIFTINSERT:
++	case NEON_TERNOP:
++	case NEON_GETLANE:
++	case NEON_SETLANE:
++	case NEON_CREATE:
++	case NEON_DUP:
++	case NEON_DUPLANE:
++	case NEON_SHIFTIMM:
++	case NEON_SHIFTACC:
++	case NEON_COMBINE:
++	case NEON_SPLIT:
++	case NEON_CONVERT:
++	case NEON_FIXCONV:
++	case NEON_LANEMUL:
++	case NEON_LANEMULL:
++	case NEON_LANEMULH:
++	case NEON_LANEMAC:
++	case NEON_SCALARMUL:
++	case NEON_SCALARMULL:
++	case NEON_SCALARMULH:
++	case NEON_SCALARMAC:
++	case NEON_SELECT:
++	case NEON_VTBL:
++	case NEON_VTBX:
++	  {
++	    int k;
++	    tree return_type = void_type_node, args = void_list_node;
++
++	    /* Build a function type directly from the insn_data for
++	       this builtin.  The build_function_type() function takes
++	       care of removing duplicates for us.  */
++	    for (k = insn_data[d->code].n_operands - 1; k >= 0; k--)
++	      {
++		tree eltype;
++
++		if (is_load && k == 1)
++		  {
++		    /* Neon load patterns always have the memory
++		       operand in the operand 1 position.  */
++		    gcc_assert (insn_data[d->code].operand[k].predicate
++				== neon_struct_operand);
++
++		    switch (d->mode)
++		      {
++		      case T_V8QI:
++		      case T_V16QI:
++			eltype = const_intQI_pointer_node;
++			break;
++
++		      case T_V4HI:
++		      case T_V8HI:
++			eltype = const_intHI_pointer_node;
++			break;
++
++		      case T_V2SI:
++		      case T_V4SI:
++			eltype = const_intSI_pointer_node;
++			break;
++
++		      case T_V2SF:
++		      case T_V4SF:
++			eltype = const_float_pointer_node;
++			break;
++
++		      case T_DI:
++		      case T_V2DI:
++			eltype = const_intDI_pointer_node;
++			break;
++
++		      default: gcc_unreachable ();
++		      }
++		  }
++		else if (is_store && k == 0)
++		  {
++		    /* Similarly, Neon store patterns use operand 0 as
++		       the memory location to store to.  */
++		    gcc_assert (insn_data[d->code].operand[k].predicate
++				== neon_struct_operand);
++
++		    switch (d->mode)
++		      {
++		      case T_V8QI:
++		      case T_V16QI:
++			eltype = intQI_pointer_node;
++			break;
++
++		      case T_V4HI:
++		      case T_V8HI:
++			eltype = intHI_pointer_node;
++			break;
++
++		      case T_V2SI:
++		      case T_V4SI:
++			eltype = intSI_pointer_node;
++			break;
++
++		      case T_V2SF:
++		      case T_V4SF:
++			eltype = float_pointer_node;
++			break;
++
++		      case T_DI:
++		      case T_V2DI:
++			eltype = intDI_pointer_node;
++			break;
++
++		      default: gcc_unreachable ();
++		      }
++		  }
++		else
++		  {
++		    switch (insn_data[d->code].operand[k].mode)
++		      {
++		      case VOIDmode: eltype = void_type_node; break;
++			/* Scalars.  */
++		      case QImode: eltype = neon_intQI_type_node; break;
++		      case HImode: eltype = neon_intHI_type_node; break;
++		      case SImode: eltype = neon_intSI_type_node; break;
++		      case SFmode: eltype = neon_float_type_node; break;
++		      case DImode: eltype = neon_intDI_type_node; break;
++		      case TImode: eltype = intTI_type_node; break;
++		      case EImode: eltype = intEI_type_node; break;
++		      case OImode: eltype = intOI_type_node; break;
++		      case CImode: eltype = intCI_type_node; break;
++		      case XImode: eltype = intXI_type_node; break;
++			/* 64-bit vectors.  */
++		      case V8QImode: eltype = V8QI_type_node; break;
++		      case V4HImode: eltype = V4HI_type_node; break;
++		      case V2SImode: eltype = V2SI_type_node; break;
++		      case V2SFmode: eltype = V2SF_type_node; break;
++			/* 128-bit vectors.  */
++		      case V16QImode: eltype = V16QI_type_node; break;
++		      case V8HImode: eltype = V8HI_type_node; break;
++		      case V4SImode: eltype = V4SI_type_node; break;
++		      case V4SFmode: eltype = V4SF_type_node; break;
++		      case V2DImode: eltype = V2DI_type_node; break;
++		      default: gcc_unreachable ();
++		      }
++		  }
++
++		if (k == 0 && !is_store)
++		  return_type = eltype;
++		else
++		  args = tree_cons (NULL_TREE, eltype, args);
++	      }
++
++	    ftype = build_function_type (return_type, args);
++	  }
++	  break;
++
++	case NEON_RESULTPAIR:
++	  {
++	    switch (insn_data[d->code].operand[1].mode)
++	      {
++	      case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
++	      case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
++	      case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
++	      case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
++	      case DImode: ftype = void_ftype_pdi_di_di; break;
++	      case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
++	      case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
++	      case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
++	      case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
++	      case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
++	      default: gcc_unreachable ();
++	      }
++	  }
++	  break;
++
++	case NEON_REINTERP:
++	  {
++	    /* We iterate over 5 doubleword types, then 5 quadword
++	       types.  */
++	    int rhs = d->mode % 5;
++	    switch (insn_data[d->code].operand[0].mode)
++	      {
++	      case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
++	      case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
++	      case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
++	      case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
++	      case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
++	      case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
++	      case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
++	      case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
++	      case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
++	      case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
++	      default: gcc_unreachable ();
++	      }
++	  }
++	  break;
++
++	default:
++	  gcc_unreachable ();
++	}
++
++      gcc_assert (ftype != NULL);
++
++      sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[d->mode]);
++
++      decl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, NULL,
++				   NULL_TREE);
++      arm_builtin_decls[fcode] = decl;
++    }
++}
++
++#define def_mbuiltin(MASK, NAME, TYPE, CODE)				\
++  do									\
++    {									\
++      if ((MASK) & insn_flags)						\
++	{								\
++	  tree bdecl;							\
++	  bdecl = add_builtin_function ((NAME), (TYPE), (CODE),		\
++					BUILT_IN_MD, NULL, NULL_TREE);	\
++	  arm_builtin_decls[CODE] = bdecl;				\
++	}								\
++    }									\
++  while (0)
++  
++struct builtin_description
++{
++  const unsigned int       mask;
++  const enum insn_code     icode;
++  const char * const       name;
++  const enum arm_builtins  code;
++  const enum rtx_code      comparison;
++  const unsigned int       flag;
++};
++  
++static const struct builtin_description bdesc_2arg[] =
++{
++#define IWMMXT_BUILTIN(code, string, builtin) \
++  { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
++    ARM_BUILTIN_##builtin, UNKNOWN, 0 },
++  
++  IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
++  IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
++  IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
++  IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
++  IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
++  IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
++  IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
++  IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
++  IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
++  IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
++  IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
++  IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
++  IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
++  IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
++  IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
++  IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
++  IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
++  IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
++  IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
++  IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
++  IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
++  IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
++  IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
++  IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
++  IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
++  IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
++  IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
++  IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
++  IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
++  IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
++  IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
++  IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
++  IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
++  IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
++  IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
++  IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
++  IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
++  IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
++  IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
++  IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
++  IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
++  IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
++  IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
++  IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
++  IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
++  IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
++  IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
++  IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
++  IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
++  IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
++  IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
++  IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
++  IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
++  IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
++  IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
++  IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
++  IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
++  IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
++  
++#define IWMMXT_BUILTIN2(code, builtin) \
++  { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
++  
++  IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
++  IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
++  IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
++  IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
++  IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
++  IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
++  IWMMXT_BUILTIN2 (ashlv4hi3_di,    WSLLH)
++  IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
++  IWMMXT_BUILTIN2 (ashlv2si3_di,    WSLLW)
++  IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
++  IWMMXT_BUILTIN2 (ashldi3_di,      WSLLD)
++  IWMMXT_BUILTIN2 (ashldi3_iwmmxt,  WSLLDI)
++  IWMMXT_BUILTIN2 (lshrv4hi3_di,    WSRLH)
++  IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
++  IWMMXT_BUILTIN2 (lshrv2si3_di,    WSRLW)
++  IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
++  IWMMXT_BUILTIN2 (lshrdi3_di,      WSRLD)
++  IWMMXT_BUILTIN2 (lshrdi3_iwmmxt,  WSRLDI)
++  IWMMXT_BUILTIN2 (ashrv4hi3_di,    WSRAH)
++  IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
++  IWMMXT_BUILTIN2 (ashrv2si3_di,    WSRAW)
++  IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
++  IWMMXT_BUILTIN2 (ashrdi3_di,      WSRAD)
++  IWMMXT_BUILTIN2 (ashrdi3_iwmmxt,  WSRADI)
++  IWMMXT_BUILTIN2 (rorv4hi3_di,     WRORH)
++  IWMMXT_BUILTIN2 (rorv4hi3,        WRORHI)
++  IWMMXT_BUILTIN2 (rorv2si3_di,     WRORW)
++  IWMMXT_BUILTIN2 (rorv2si3,        WRORWI)
++  IWMMXT_BUILTIN2 (rordi3_di,       WRORD)
++  IWMMXT_BUILTIN2 (rordi3,          WRORDI)
++  IWMMXT_BUILTIN2 (iwmmxt_wmacuz,   WMACUZ)
++  IWMMXT_BUILTIN2 (iwmmxt_wmacsz,   WMACSZ)
++};
++  
++static const struct builtin_description bdesc_1arg[] =
++{
++  IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
++  IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
++  IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
++  IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
++  IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
++  IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
++  IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
++  IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
++  IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
++  IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
++  IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
++  IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
++  IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
++  IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
++  IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
++  IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
++  IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
++  IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
++};
++  
++/* Set up all the iWMMXt builtins.  This is not called if
++   TARGET_IWMMXT is zero.  */
++
++static void
++arm_init_iwmmxt_builtins (void)
++{
++  const struct builtin_description * d;
++  size_t i;
++  tree endlink = void_list_node;
++
++  tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
++  tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
++  tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
++
++  tree int_ftype_int
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, integer_type_node, endlink));
++  tree v8qi_ftype_v8qi_v8qi_int
++    = build_function_type (V8QI_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      tree_cons (NULL_TREE, V8QI_type_node,
++						 tree_cons (NULL_TREE,
++							    integer_type_node,
++							    endlink))));
++  tree v4hi_ftype_v4hi_int
++    = build_function_type (V4HI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree v2si_ftype_v2si_int
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree v2si_ftype_di_di
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, long_long_integer_type_node,
++				      tree_cons (NULL_TREE,
++						 long_long_integer_type_node,
++						 endlink)));
++  tree di_ftype_di_int
++    = build_function_type (long_long_integer_type_node,
++			   tree_cons (NULL_TREE, long_long_integer_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree di_ftype_di_int_int
++    = build_function_type (long_long_integer_type_node,
++			   tree_cons (NULL_TREE, long_long_integer_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 tree_cons (NULL_TREE,
++							    integer_type_node,
++							    endlink))));
++  tree int_ftype_v8qi
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      endlink));
++  tree int_ftype_v4hi
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      endlink));
++  tree int_ftype_v2si
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      endlink));
++  tree int_ftype_v8qi_int
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree int_ftype_v4hi_int
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree int_ftype_v2si_int
++    = build_function_type (integer_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree v8qi_ftype_v8qi_int_int
++    = build_function_type (V8QI_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 tree_cons (NULL_TREE,
++							    integer_type_node,
++							    endlink))));
++  tree v4hi_ftype_v4hi_int_int
++    = build_function_type (V4HI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 tree_cons (NULL_TREE,
++							    integer_type_node,
++							    endlink))));
++  tree v2si_ftype_v2si_int_int
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 tree_cons (NULL_TREE,
++							    integer_type_node,
++							    endlink))));
++  /* Miscellaneous.  */
++  tree v8qi_ftype_v4hi_v4hi
++    = build_function_type (V8QI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, V4HI_type_node,
++						 endlink)));
++  tree v4hi_ftype_v2si_v2si
++    = build_function_type (V4HI_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      tree_cons (NULL_TREE, V2SI_type_node,
++						 endlink)));
++  tree v2si_ftype_v4hi_v4hi
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, V4HI_type_node,
++						 endlink)));
++  tree v2si_ftype_v8qi_v8qi
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      tree_cons (NULL_TREE, V8QI_type_node,
++						 endlink)));
++  tree v4hi_ftype_v4hi_di
++    = build_function_type (V4HI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE,
++						 long_long_integer_type_node,
++						 endlink)));
++  tree v2si_ftype_v2si_di
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      tree_cons (NULL_TREE,
++						 long_long_integer_type_node,
++						 endlink)));
++  tree void_ftype_int_int
++    = build_function_type (void_type_node,
++			   tree_cons (NULL_TREE, integer_type_node,
++				      tree_cons (NULL_TREE, integer_type_node,
++						 endlink)));
++  tree di_ftype_void
++    = build_function_type (long_long_unsigned_type_node, endlink);
++  tree di_ftype_v8qi
++    = build_function_type (long_long_integer_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      endlink));
++  tree di_ftype_v4hi
++    = build_function_type (long_long_integer_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      endlink));
++  tree di_ftype_v2si
++    = build_function_type (long_long_integer_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      endlink));
++  tree v2si_ftype_v4hi
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      endlink));
++  tree v4hi_ftype_v8qi
++    = build_function_type (V4HI_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      endlink));
++
++  tree di_ftype_di_v4hi_v4hi
++    = build_function_type (long_long_unsigned_type_node,
++			   tree_cons (NULL_TREE,
++				      long_long_unsigned_type_node,
++				      tree_cons (NULL_TREE, V4HI_type_node,
++						 tree_cons (NULL_TREE,
++							    V4HI_type_node,
++							    endlink))));
++
++  tree di_ftype_v4hi_v4hi
++    = build_function_type (long_long_unsigned_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, V4HI_type_node,
++						 endlink)));
++  
++  /* Normal vector binops.  */
++  tree v8qi_ftype_v8qi_v8qi
++    = build_function_type (V8QI_type_node,
++			   tree_cons (NULL_TREE, V8QI_type_node,
++				      tree_cons (NULL_TREE, V8QI_type_node,
++						 endlink)));
++  tree v4hi_ftype_v4hi_v4hi
++    = build_function_type (V4HI_type_node,
++			   tree_cons (NULL_TREE, V4HI_type_node,
++				      tree_cons (NULL_TREE, V4HI_type_node,
++						 endlink)));
++  tree v2si_ftype_v2si_v2si
++    = build_function_type (V2SI_type_node,
++			   tree_cons (NULL_TREE, V2SI_type_node,
++				      tree_cons (NULL_TREE, V2SI_type_node,
++						 endlink)));
++  tree di_ftype_di_di
++    = build_function_type (long_long_unsigned_type_node,
++			   tree_cons (NULL_TREE, long_long_unsigned_type_node,
++				      tree_cons (NULL_TREE,
++						 long_long_unsigned_type_node,
++						 endlink)));
++  
++  /* Add all builtins that are more or less simple operations on two
++     operands.  */
++  for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
++    {
++      /* Use one of the operands; the target can have a different mode for
++	 mask-generating compares.  */
++      enum machine_mode mode;
++      tree type;
++
++      if (d->name == 0)
++	continue;
++
++      mode = insn_data[d->icode].operand[1].mode;
++
++      switch (mode)
++	{
++	case V8QImode:
++	  type = v8qi_ftype_v8qi_v8qi;
++	  break;
++	case V4HImode:
++	  type = v4hi_ftype_v4hi_v4hi;
++	  break;
++	case V2SImode:
++	  type = v2si_ftype_v2si_v2si;
++	  break;
++	case DImode:
++	  type = di_ftype_di_di;
++	  break;
++
++	default:
++	  gcc_unreachable ();
++	}
++
++      def_mbuiltin (d->mask, d->name, type, d->code);
++    }
++
++  /* Add the remaining MMX insns with somewhat more complicated types.  */
++#define iwmmx_mbuiltin(NAME, TYPE, CODE)			\
++  def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE),	\
++		ARM_BUILTIN_ ## CODE)
++
++  iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
++  iwmmx_mbuiltin ("setwcx", void_ftype_int_int, SETWCX);
++  iwmmx_mbuiltin ("getwcx", int_ftype_int, GETWCX);
++
++  iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);
++  iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);
++  iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD);
++  iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI);
++  iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI);
++  iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI);
++
++  iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH);
++  iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW);
++  iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD);
++  iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI);
++  iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI);
++  iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI);
++
++  iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH);
++  iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW);
++  iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD);
++  iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI);
++  iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI);
++  iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI);
++
++  iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH);
++  iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW);
++  iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD);
++  iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI);
++  iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI);
++  iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI);
++
++  iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);
++
++  iwmmx_mbuiltin ("wsadb", v2si_ftype_v8qi_v8qi, WSADB);
++  iwmmx_mbuiltin ("wsadh", v2si_ftype_v4hi_v4hi, WSADH);
++  iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);
++  iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);
++
++  iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB);
++  iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH);
++  iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW);
++  iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB);
++  iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH);
++  iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW);
++  iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB);
++  iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH);
++  iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW);
++
++  iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB);
++  iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH);
++  iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW);
++
++  iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB);
++  iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);
++  iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);
++
++  iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);
++  iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);
++  iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);
++  iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS);
++  iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS);
++  iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS);
++
++  iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB);
++  iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH);
++  iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW);
++  iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB);
++  iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH);
++  iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW);
++  iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB);
++  iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH);
++  iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW);
++  iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB);
++  iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH);
++  iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW);
++
++  iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS);
++  iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ);
++  iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);
++  iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);
++
++  iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGN);
++  iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);
++  iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);
++  iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);
++  iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT);
++  iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);
++  iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);
++
++#undef iwmmx_mbuiltin
++}
++
++static void
++arm_init_tls_builtins (void)
++{
++  tree ftype, decl;
++
++  ftype = build_function_type (ptr_type_node, void_list_node);
++  decl = add_builtin_function ("__builtin_thread_pointer", ftype,
++			       ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
++			       NULL, NULL_TREE);
++  TREE_NOTHROW (decl) = 1;
++  TREE_READONLY (decl) = 1;
++  arm_builtin_decls[ARM_BUILTIN_THREAD_POINTER] = decl;
+ }
+ 
+ static void
+@@ -19479,6 +19662,17 @@
+     arm_init_fp16_builtins ();
+ }
+ 
++/* Return the ARM builtin for CODE.  */
++
++static tree
++arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
++{
++  if (code >= ARM_BUILTIN_MAX)
++    return error_mark_node;
++
++  return arm_builtin_decls[code];
++}
++
+ /* Implement TARGET_INVALID_PARAMETER_TYPE.  */
+ 
+ static const char *
+@@ -19630,58 +19824,6 @@
+   return target;
+ }
+ 
+-static int
+-neon_builtin_compare (const void *a, const void *b)
+-{
+-  const neon_builtin_datum *const key = (const neon_builtin_datum *) a;
+-  const neon_builtin_datum *const memb = (const neon_builtin_datum *) b;
+-  unsigned int soughtcode = key->base_fcode;
+-
+-  if (soughtcode >= memb->base_fcode
+-      && soughtcode < memb->base_fcode + memb->num_vars)
+-    return 0;
+-  else if (soughtcode < memb->base_fcode)
+-    return -1;
+-  else
+-    return 1;
+-}
+-
+-static enum insn_code
+-locate_neon_builtin_icode (int fcode, neon_itype *itype,
+-			   enum neon_builtin_type_bits *type_bit)
+-{
+-  neon_builtin_datum key
+-    = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
+-  neon_builtin_datum *found;
+-  int idx, type, ntypes;
+-
+-  key.base_fcode = fcode;
+-  found = (neon_builtin_datum *)
+-    bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data),
+-		   sizeof (neon_builtin_data[0]), neon_builtin_compare);
+-  gcc_assert (found);
+-  idx = fcode - (int) found->base_fcode;
+-  gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars);
+-
+-  if (itype)
+-    *itype = found->itype;
+-
+-  if (type_bit)
+-    {
+-      ntypes = 0;
+-      for (type = 0; type < T_MAX; type++)
+-	if (found->bits & (1 << type))
+-	  {
+-	    if (ntypes == idx)
+-	      break;
+-	    ntypes++;
+-	  }
+-      gcc_assert (type < T_MAX);
+-      *type_bit = (enum neon_builtin_type_bits) (1 << type);
+-    }
+-  return found->codes[idx];
+-}
+-
+ typedef enum {
+   NEON_ARG_COPY_TO_REG,
+   NEON_ARG_CONSTANT,
+@@ -19695,14 +19837,14 @@
+    and return an expression for the accessed memory.
+ 
+    The intrinsic function operates on a block of registers that has
+-   mode REG_MODE.  This block contains vectors of type TYPE_BIT.
++   mode REG_MODE.  This block contains vectors of type TYPE_MODE.
+    The function references the memory at EXP in mode MEM_MODE;
+    this mode may be BLKmode if no more suitable mode is available.  */
+ 
+ static tree
+ neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
+ 			  enum machine_mode reg_mode,
+-			  enum neon_builtin_type_bits type_bit)
++			  neon_builtin_type_mode type_mode)
+ {
+   HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
+   tree elem_type, upper_bound, array_type;
+@@ -19711,8 +19853,8 @@
+   reg_size = GET_MODE_SIZE (reg_mode);
+ 
+   /* Work out the size of each vector in bytes.  */
+-  gcc_assert (type_bit & (T_DREG | T_QREG));
+-  vector_size = (type_bit & T_QREG ? 16 : 8);
++  gcc_assert (TYPE_MODE_BIT (type_mode) & (TB_DREG | TB_QREG));
++  vector_size = (TYPE_MODE_BIT (type_mode) & TB_QREG ? 16 : 8);
+ 
+   /* Work out how many vectors there are.  */
+   gcc_assert (reg_size % vector_size == 0);
+@@ -19743,7 +19885,7 @@
+ /* Expand a Neon builtin.  */
+ static rtx
+ arm_expand_neon_args (rtx target, int icode, int have_retval,
+-		      enum neon_builtin_type_bits type_bit,
++		      neon_builtin_type_mode type_mode,
+ 		      tree exp, ...)
+ {
+   va_list ap;
+@@ -19779,7 +19921,7 @@
+             {
+               other_mode = insn_data[icode].operand[1 - opno].mode;
+               arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
+-                                                    other_mode, type_bit);
++                                                    other_mode, type_mode);
+             }
+           op[argc] = expand_normal (arg[argc]);
+ 
+@@ -19889,16 +20031,17 @@
+ static rtx
+ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+ {
+-  neon_itype itype;
+-  enum neon_builtin_type_bits type_bit;
+-  enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
++  neon_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
++  neon_itype itype = d->itype;
++  enum insn_code icode = d->code;
++  neon_builtin_type_mode type_mode = d->mode;
+ 
+   switch (itype)
+     {
+     case NEON_UNOP:
+     case NEON_CONVERT:
+     case NEON_DUPLANE:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_BINOP:
+@@ -19908,89 +20051,89 @@
+     case NEON_SCALARMULH:
+     case NEON_SHIFTINSERT:
+     case NEON_LOGICBINOP:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_STOP);
+ 
+     case NEON_TERNOP:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_GETLANE:
+     case NEON_FIXCONV:
+     case NEON_SHIFTIMM:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
+         NEON_ARG_STOP);
+ 
+     case NEON_CREATE:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_DUP:
+     case NEON_SPLIT:
+     case NEON_REINTERP:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_COMBINE:
+     case NEON_VTBL:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_RESULTPAIR:
+-      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 0, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_STOP);
+ 
+     case NEON_LANEMUL:
+     case NEON_LANEMULL:
+     case NEON_LANEMULH:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_LANEMAC:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SHIFTACC:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SCALARMAC:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+ 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_CONSTANT, NEON_ARG_STOP);
+ 
+     case NEON_SELECT:
+     case NEON_VTBX:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+ 	NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+         NEON_ARG_STOP);
+ 
+     case NEON_LOAD1:
+     case NEON_LOADSTRUCT:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+ 	NEON_ARG_MEMORY, NEON_ARG_STOP);
+ 
+     case NEON_LOAD1LANE:
+     case NEON_LOADSTRUCTLANE:
+-      return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 1, type_mode, exp,
+ 	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ 	NEON_ARG_STOP);
+ 
+     case NEON_STORE1:
+     case NEON_STORESTRUCT:
+-      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 0, type_mode, exp,
+ 	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+ 
+     case NEON_STORE1LANE:
+     case NEON_STORESTRUCTLANE:
+-      return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++      return arm_expand_neon_args (target, icode, 0, type_mode, exp,
+ 	NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ 	NEON_ARG_STOP);
+     }
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-08-13 08:32:32 +0000
++++ new/gcc/config/arm/arm.h	2011-08-24 17:35:16 +0000
+@@ -2269,178 +2269,6 @@
+    : arm_gen_return_addr_mask ())
+ 
+ 
+-/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
+-   symbolic names defined here (which would require too much duplication).
+-   FIXME?  */
+-enum arm_builtins
+-{
+-  ARM_BUILTIN_GETWCX,
+-  ARM_BUILTIN_SETWCX,
+-
+-  ARM_BUILTIN_WZERO,
+-
+-  ARM_BUILTIN_WAVG2BR,
+-  ARM_BUILTIN_WAVG2HR,
+-  ARM_BUILTIN_WAVG2B,
+-  ARM_BUILTIN_WAVG2H,
+-
+-  ARM_BUILTIN_WACCB,
+-  ARM_BUILTIN_WACCH,
+-  ARM_BUILTIN_WACCW,
+-
+-  ARM_BUILTIN_WMACS,
+-  ARM_BUILTIN_WMACSZ,
+-  ARM_BUILTIN_WMACU,
+-  ARM_BUILTIN_WMACUZ,
+-
+-  ARM_BUILTIN_WSADB,
+-  ARM_BUILTIN_WSADBZ,
+-  ARM_BUILTIN_WSADH,
+-  ARM_BUILTIN_WSADHZ,
+-
+-  ARM_BUILTIN_WALIGN,
+-
+-  ARM_BUILTIN_TMIA,
+-  ARM_BUILTIN_TMIAPH,
+-  ARM_BUILTIN_TMIABB,
+-  ARM_BUILTIN_TMIABT,
+-  ARM_BUILTIN_TMIATB,
+-  ARM_BUILTIN_TMIATT,
+-
+-  ARM_BUILTIN_TMOVMSKB,
+-  ARM_BUILTIN_TMOVMSKH,
+-  ARM_BUILTIN_TMOVMSKW,
+-
+-  ARM_BUILTIN_TBCSTB,
+-  ARM_BUILTIN_TBCSTH,
+-  ARM_BUILTIN_TBCSTW,
+-
+-  ARM_BUILTIN_WMADDS,
+-  ARM_BUILTIN_WMADDU,
+-
+-  ARM_BUILTIN_WPACKHSS,
+-  ARM_BUILTIN_WPACKWSS,
+-  ARM_BUILTIN_WPACKDSS,
+-  ARM_BUILTIN_WPACKHUS,
+-  ARM_BUILTIN_WPACKWUS,
+-  ARM_BUILTIN_WPACKDUS,
+-
+-  ARM_BUILTIN_WADDB,
+-  ARM_BUILTIN_WADDH,
+-  ARM_BUILTIN_WADDW,
+-  ARM_BUILTIN_WADDSSB,
+-  ARM_BUILTIN_WADDSSH,
+-  ARM_BUILTIN_WADDSSW,
+-  ARM_BUILTIN_WADDUSB,
+-  ARM_BUILTIN_WADDUSH,
+-  ARM_BUILTIN_WADDUSW,
+-  ARM_BUILTIN_WSUBB,
+-  ARM_BUILTIN_WSUBH,
+-  ARM_BUILTIN_WSUBW,
+-  ARM_BUILTIN_WSUBSSB,
+-  ARM_BUILTIN_WSUBSSH,
+-  ARM_BUILTIN_WSUBSSW,
+-  ARM_BUILTIN_WSUBUSB,
+-  ARM_BUILTIN_WSUBUSH,
+-  ARM_BUILTIN_WSUBUSW,
+-
+-  ARM_BUILTIN_WAND,
+-  ARM_BUILTIN_WANDN,
+-  ARM_BUILTIN_WOR,
+-  ARM_BUILTIN_WXOR,
+-
+-  ARM_BUILTIN_WCMPEQB,
+-  ARM_BUILTIN_WCMPEQH,
+-  ARM_BUILTIN_WCMPEQW,
+-  ARM_BUILTIN_WCMPGTUB,
+-  ARM_BUILTIN_WCMPGTUH,
+-  ARM_BUILTIN_WCMPGTUW,
+-  ARM_BUILTIN_WCMPGTSB,
+-  ARM_BUILTIN_WCMPGTSH,
+-  ARM_BUILTIN_WCMPGTSW,
+-
+-  ARM_BUILTIN_TEXTRMSB,
+-  ARM_BUILTIN_TEXTRMSH,
+-  ARM_BUILTIN_TEXTRMSW,
+-  ARM_BUILTIN_TEXTRMUB,
+-  ARM_BUILTIN_TEXTRMUH,
+-  ARM_BUILTIN_TEXTRMUW,
+-  ARM_BUILTIN_TINSRB,
+-  ARM_BUILTIN_TINSRH,
+-  ARM_BUILTIN_TINSRW,
+-
+-  ARM_BUILTIN_WMAXSW,
+-  ARM_BUILTIN_WMAXSH,
+-  ARM_BUILTIN_WMAXSB,
+-  ARM_BUILTIN_WMAXUW,
+-  ARM_BUILTIN_WMAXUH,
+-  ARM_BUILTIN_WMAXUB,
+-  ARM_BUILTIN_WMINSW,
+-  ARM_BUILTIN_WMINSH,
+-  ARM_BUILTIN_WMINSB,
+-  ARM_BUILTIN_WMINUW,
+-  ARM_BUILTIN_WMINUH,
+-  ARM_BUILTIN_WMINUB,
+-
+-  ARM_BUILTIN_WMULUM,
+-  ARM_BUILTIN_WMULSM,
+-  ARM_BUILTIN_WMULUL,
+-
+-  ARM_BUILTIN_PSADBH,
+-  ARM_BUILTIN_WSHUFH,
+-
+-  ARM_BUILTIN_WSLLH,
+-  ARM_BUILTIN_WSLLW,
+-  ARM_BUILTIN_WSLLD,
+-  ARM_BUILTIN_WSRAH,
+-  ARM_BUILTIN_WSRAW,
+-  ARM_BUILTIN_WSRAD,
+-  ARM_BUILTIN_WSRLH,
+-  ARM_BUILTIN_WSRLW,
+-  ARM_BUILTIN_WSRLD,
+-  ARM_BUILTIN_WRORH,
+-  ARM_BUILTIN_WRORW,
+-  ARM_BUILTIN_WRORD,
+-  ARM_BUILTIN_WSLLHI,
+-  ARM_BUILTIN_WSLLWI,
+-  ARM_BUILTIN_WSLLDI,
+-  ARM_BUILTIN_WSRAHI,
+-  ARM_BUILTIN_WSRAWI,
+-  ARM_BUILTIN_WSRADI,
+-  ARM_BUILTIN_WSRLHI,
+-  ARM_BUILTIN_WSRLWI,
+-  ARM_BUILTIN_WSRLDI,
+-  ARM_BUILTIN_WRORHI,
+-  ARM_BUILTIN_WRORWI,
+-  ARM_BUILTIN_WRORDI,
+-
+-  ARM_BUILTIN_WUNPCKIHB,
+-  ARM_BUILTIN_WUNPCKIHH,
+-  ARM_BUILTIN_WUNPCKIHW,
+-  ARM_BUILTIN_WUNPCKILB,
+-  ARM_BUILTIN_WUNPCKILH,
+-  ARM_BUILTIN_WUNPCKILW,
+-
+-  ARM_BUILTIN_WUNPCKEHSB,
+-  ARM_BUILTIN_WUNPCKEHSH,
+-  ARM_BUILTIN_WUNPCKEHSW,
+-  ARM_BUILTIN_WUNPCKEHUB,
+-  ARM_BUILTIN_WUNPCKEHUH,
+-  ARM_BUILTIN_WUNPCKEHUW,
+-  ARM_BUILTIN_WUNPCKELSB,
+-  ARM_BUILTIN_WUNPCKELSH,
+-  ARM_BUILTIN_WUNPCKELSW,
+-  ARM_BUILTIN_WUNPCKELUB,
+-  ARM_BUILTIN_WUNPCKELUH,
+-  ARM_BUILTIN_WUNPCKELUW,
+-
+-  ARM_BUILTIN_THREAD_POINTER,
+-
+-  ARM_BUILTIN_NEON_BASE,
+-
+-  ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE  /* FIXME: Wrong!  */
+-};
+-
+ /* Do not emit .note.GNU-stack by default.  */
+ #ifndef NEED_INDICATE_EXEC_STACK
+ #define NEED_INDICATE_EXEC_STACK	0
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch
new file mode 100644
index 0000000000..1a940975f3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch
@@ -0,0 +1,1255 @@
+2011-08-25  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (is_widening_mult_rhs_p): Handle constants
+	beyond conversions.
+	(convert_mult_to_widen): Convert constant inputs to the right type.
+	(convert_plusminus_to_widen): Don't automatically reject inputs that
+	are not an SSA_NAME.
+	Convert constant inputs to the right type.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-11.c: New file.
+	* gcc.target/arm/wmul-12.c: New file.
+	* gcc.target/arm/wmul-13.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (convert_plusminus_to_widen): Convert add_rhs
+	to the correct type.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-10.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (convert_mult_to_widen): Better handle
+	unsigned inputs of different modes.
+	(convert_plusminus_to_widen): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-9.c: New file.
+	* gcc.target/arm/wmul-bitfield-2.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (is_widening_mult_rhs_p): Add new argument
+	'type'.
+	Use 'type' from caller, not inferred from 'rhs'.
+	Don't reject non-conversion statements. Do return lhs in this case.
+	(is_widening_mult_p): Add new argument 'type'.
+	Use 'type' from caller, not inferred from 'stmt'.
+	Pass type to is_widening_mult_rhs_p.
+	(convert_mult_to_widen): Pass type to is_widening_mult_p.
+	(convert_plusminus_to_widen): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-8.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (is_widening_mult_p): Remove FIXME.
+	Ensure the the larger type is the first operand.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-7.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (convert_mult_to_widen): Convert
+	unsupported unsigned multiplies to signed.
+	(convert_plusminus_to_widen): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-6.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* tree-ssa-math-opts.c (convert_plusminus_to_widen): Permit a single
+	conversion statement separating multiply-and-accumulate.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-5.c: New file.
+	* gcc.target/arm/no-wmla-1.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.md (maddhidi4): Remove '*' from name.
+	* expr.c (expand_expr_real_2): Use find_widening_optab_handler.
+	* optabs.c (find_widening_optab_handler_and_mode): New function.
+	(expand_widen_pattern_expr): Use find_widening_optab_handler.
+	(expand_binop_directly): Likewise.
+	(expand_binop): Likewise.
+	* optabs.h (find_widening_optab_handler): New macro define.
+	(find_widening_optab_handler_and_mode): New prototype.
+	* tree-cfg.c (verify_gimple_assign_binary): Adjust WIDEN_MULT_EXPR
+	type precision rules.
+	(verify_gimple_assign_ternary): Likewise for WIDEN_MULT_PLUS_EXPR.
+	* tree-ssa-math-opts.c (build_and_insert_cast): New function.
+	(is_widening_mult_rhs_p): Allow widening by more than one mode.
+	Explicitly disallow mis-matched input types.
+	(convert_mult_to_widen): Use find_widening_optab_handler, and cast
+	input types to fit the new handler.
+	(convert_plusminus_to_widen): Likewise.
+
+	gcc/testsuite/
+	* gcc.target/arm/wmul-bitfield-1.c: New file.
+
+	2011-08-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* expr.c (expand_expr_real_2): Use widening_optab_handler.
+	* genopinit.c (optabs): Use set_widening_optab_handler for $N.
+	(gen_insn): $N now means $a must be wider than $b, not consecutive.
+	* optabs.c (widened_mode): New function.
+	(expand_widen_pattern_expr): Use widening_optab_handler.
+	(expand_binop_directly): Likewise.
+	(expand_binop): Likewise.
+	* optabs.h (widening_optab_handlers): New struct.
+	(optab_d): New member, 'widening'.
+	(widening_optab_handler): New function.
+	(set_widening_optab_handler): New function.
+	* tree-ssa-math-opts.c (convert_mult_to_widen): Use
+	widening_optab_handler.
+	(convert_plusminus_to_widen): Likewise.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-08-13 08:32:32 +0000
++++ new/gcc/config/arm/arm.md	2011-08-25 11:42:09 +0000
+@@ -1839,7 +1839,7 @@
+    (set_attr "predicable" "yes")]
+ )
+ 
+-(define_insn "*maddhidi4"
++(define_insn "maddhidi4"
+   [(set (match_operand:DI 0 "s_register_operand" "=r")
+ 	(plus:DI
+ 	  (mult:DI (sign_extend:DI
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2011-08-13 08:32:32 +0000
++++ new/gcc/expr.c	2011-08-25 11:42:09 +0000
+@@ -7688,18 +7688,16 @@
+ 	{
+ 	  enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0));
+ 	  this_optab = usmul_widen_optab;
+-	  if (mode == GET_MODE_2XWIDER_MODE (innermode))
++	  if (find_widening_optab_handler (this_optab, mode, innermode, 0)
++		!= CODE_FOR_nothing)
+ 	    {
+-	      if (optab_handler (this_optab, mode) != CODE_FOR_nothing)
+-		{
+-		  if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
+-		    expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
+-				     EXPAND_NORMAL);
+-		  else
+-		    expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
+-				     EXPAND_NORMAL);
+-		  goto binop3;
+-		}
++	      if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
++		expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
++				 EXPAND_NORMAL);
++	      else
++		expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
++				 EXPAND_NORMAL);
++	      goto binop3;
+ 	    }
+ 	}
+       /* Check for a multiplication with matching signedness.  */
+@@ -7714,10 +7712,10 @@
+ 	  optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
+ 	  this_optab = zextend_p ? umul_widen_optab : smul_widen_optab;
+ 
+-	  if (mode == GET_MODE_2XWIDER_MODE (innermode)
+-	      && TREE_CODE (treeop0) != INTEGER_CST)
++	  if (TREE_CODE (treeop0) != INTEGER_CST)
+ 	    {
+-	      if (optab_handler (this_optab, mode) != CODE_FOR_nothing)
++	      if (find_widening_optab_handler (this_optab, mode, innermode, 0)
++		    != CODE_FOR_nothing)
+ 		{
+ 		  expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
+ 				   EXPAND_NORMAL);
+@@ -7725,7 +7723,8 @@
+ 					       unsignedp, this_optab);
+ 		  return REDUCE_BIT_FIELD (temp);
+ 		}
+-	      if (optab_handler (other_optab, mode) != CODE_FOR_nothing
++	      if (find_widening_optab_handler (other_optab, mode, innermode, 0)
++		    != CODE_FOR_nothing
+ 		  && innermode == word_mode)
+ 		{
+ 		  rtx htem, hipart;
+
+=== modified file 'gcc/genopinit.c'
+--- old/gcc/genopinit.c	2011-05-05 15:43:06 +0000
++++ new/gcc/genopinit.c	2011-07-15 13:06:31 +0000
+@@ -46,10 +46,12 @@
+    used.  $A and $B are replaced with the full name of the mode; $a and $b
+    are replaced with the short form of the name, as above.
+ 
+-   If $N is present in the pattern, it means the two modes must be consecutive
+-   widths in the same mode class (e.g, QImode and HImode).  $I means that
+-   only full integer modes should be considered for the next mode, and $F
+-   means that only float modes should be considered.
++   If $N is present in the pattern, it means the two modes must be in
++   the same mode class, and $b must be greater than $a (e.g, QImode
++   and HImode).
++
++   $I means that only full integer modes should be considered for the
++   next mode, and $F means that only float modes should be considered.
+    $P means that both full and partial integer modes should be considered.
+    $Q means that only fixed-point modes should be considered.
+ 
+@@ -99,17 +101,17 @@
+   "set_optab_handler (smulv_optab, $A, CODE_FOR_$(mulv$I$a3$))",
+   "set_optab_handler (umul_highpart_optab, $A, CODE_FOR_$(umul$a3_highpart$))",
+   "set_optab_handler (smul_highpart_optab, $A, CODE_FOR_$(smul$a3_highpart$))",
+-  "set_optab_handler (smul_widen_optab, $B, CODE_FOR_$(mul$a$b3$)$N)",
+-  "set_optab_handler (umul_widen_optab, $B, CODE_FOR_$(umul$a$b3$)$N)",
+-  "set_optab_handler (usmul_widen_optab, $B, CODE_FOR_$(usmul$a$b3$)$N)",
+-  "set_optab_handler (smadd_widen_optab, $B, CODE_FOR_$(madd$a$b4$)$N)",
+-  "set_optab_handler (umadd_widen_optab, $B, CODE_FOR_$(umadd$a$b4$)$N)",
+-  "set_optab_handler (ssmadd_widen_optab, $B, CODE_FOR_$(ssmadd$a$b4$)$N)",
+-  "set_optab_handler (usmadd_widen_optab, $B, CODE_FOR_$(usmadd$a$b4$)$N)",
+-  "set_optab_handler (smsub_widen_optab, $B, CODE_FOR_$(msub$a$b4$)$N)",
+-  "set_optab_handler (umsub_widen_optab, $B, CODE_FOR_$(umsub$a$b4$)$N)",
+-  "set_optab_handler (ssmsub_widen_optab, $B, CODE_FOR_$(ssmsub$a$b4$)$N)",
+-  "set_optab_handler (usmsub_widen_optab, $B, CODE_FOR_$(usmsub$a$b4$)$N)",
++  "set_widening_optab_handler (smul_widen_optab, $B, $A, CODE_FOR_$(mul$a$b3$)$N)",
++  "set_widening_optab_handler (umul_widen_optab, $B, $A, CODE_FOR_$(umul$a$b3$)$N)",
++  "set_widening_optab_handler (usmul_widen_optab, $B, $A, CODE_FOR_$(usmul$a$b3$)$N)",
++  "set_widening_optab_handler (smadd_widen_optab, $B, $A, CODE_FOR_$(madd$a$b4$)$N)",
++  "set_widening_optab_handler (umadd_widen_optab, $B, $A, CODE_FOR_$(umadd$a$b4$)$N)",
++  "set_widening_optab_handler (ssmadd_widen_optab, $B, $A, CODE_FOR_$(ssmadd$a$b4$)$N)",
++  "set_widening_optab_handler (usmadd_widen_optab, $B, $A, CODE_FOR_$(usmadd$a$b4$)$N)",
++  "set_widening_optab_handler (smsub_widen_optab, $B, $A, CODE_FOR_$(msub$a$b4$)$N)",
++  "set_widening_optab_handler (umsub_widen_optab, $B, $A, CODE_FOR_$(umsub$a$b4$)$N)",
++  "set_widening_optab_handler (ssmsub_widen_optab, $B, $A, CODE_FOR_$(ssmsub$a$b4$)$N)",
++  "set_widening_optab_handler (usmsub_widen_optab, $B, $A, CODE_FOR_$(usmsub$a$b4$)$N)",
+   "set_optab_handler (sdiv_optab, $A, CODE_FOR_$(div$a3$))",
+   "set_optab_handler (ssdiv_optab, $A, CODE_FOR_$(ssdiv$Q$a3$))",
+   "set_optab_handler (sdivv_optab, $A, CODE_FOR_$(div$V$I$a3$))",
+@@ -304,7 +306,7 @@
+     {
+       int force_float = 0, force_int = 0, force_partial_int = 0;
+       int force_fixed = 0;
+-      int force_consec = 0;
++      int force_wider = 0;
+       int matches = 1;
+ 
+       for (pp = optabs[pindex]; pp[0] != '$' || pp[1] != '('; pp++)
+@@ -322,7 +324,7 @@
+ 	    switch (*++pp)
+ 	      {
+ 	      case 'N':
+-		force_consec = 1;
++		force_wider = 1;
+ 		break;
+ 	      case 'I':
+ 		force_int = 1;
+@@ -391,7 +393,10 @@
+ 			    || mode_class[i] == MODE_VECTOR_FRACT
+ 			    || mode_class[i] == MODE_VECTOR_UFRACT
+ 			    || mode_class[i] == MODE_VECTOR_ACCUM
+-			    || mode_class[i] == MODE_VECTOR_UACCUM))
++			    || mode_class[i] == MODE_VECTOR_UACCUM)
++			&& (! force_wider
++			    || *pp == 'a'
++			    || m1 < i))
+ 		      break;
+ 		  }
+ 
+@@ -411,8 +416,7 @@
+ 	}
+ 
+       if (matches && pp[0] == '$' && pp[1] == ')'
+-	  && *np == 0
+-	  && (! force_consec || (int) GET_MODE_WIDER_MODE(m1) == m2))
++	  && *np == 0)
+ 	break;
+     }
+ 
+
+=== modified file 'gcc/optabs.c'
+--- old/gcc/optabs.c	2011-07-04 14:03:49 +0000
++++ new/gcc/optabs.c	2011-08-11 15:46:01 +0000
+@@ -225,6 +225,61 @@
+   return 1;
+ }
+ 
++/* Given two input operands, OP0 and OP1, determine what the correct from_mode
++   for a widening operation would be.  In most cases this would be OP0, but if
++   that's a constant it'll be VOIDmode, which isn't useful.  */
++
++static enum machine_mode
++widened_mode (enum machine_mode to_mode, rtx op0, rtx op1)
++{
++  enum machine_mode m0 = GET_MODE (op0);
++  enum machine_mode m1 = GET_MODE (op1);
++  enum machine_mode result;
++
++  if (m0 == VOIDmode && m1 == VOIDmode)
++    return to_mode;
++  else if (m0 == VOIDmode || GET_MODE_SIZE (m0) < GET_MODE_SIZE (m1))
++    result = m1;
++  else
++    result = m0;
++
++  if (GET_MODE_SIZE (result) > GET_MODE_SIZE (to_mode))
++    return to_mode;
++
++  return result;
++}
++
++/* Find a widening optab even if it doesn't widen as much as we want.
++   E.g. if from_mode is HImode, and to_mode is DImode, and there is no
++   direct HI->SI insn, then return SI->DI, if that exists.
++   If PERMIT_NON_WIDENING is non-zero then this can be used with
++   non-widening optabs also.  */
++
++enum insn_code
++find_widening_optab_handler_and_mode (optab op, enum machine_mode to_mode,
++				      enum machine_mode from_mode,
++				      int permit_non_widening,
++				      enum machine_mode *found_mode)
++{
++  for (; (permit_non_widening || from_mode != to_mode)
++	 && GET_MODE_SIZE (from_mode) <= GET_MODE_SIZE (to_mode)
++	 && from_mode != VOIDmode;
++       from_mode = GET_MODE_WIDER_MODE (from_mode))
++    {
++      enum insn_code handler = widening_optab_handler (op, to_mode,
++						       from_mode);
++
++      if (handler != CODE_FOR_nothing)
++	{
++	  if (found_mode)
++	    *found_mode = from_mode;
++	  return handler;
++	}
++    }
++
++  return CODE_FOR_nothing;
++}
++
+ /* Widen OP to MODE and return the rtx for the widened operand.  UNSIGNEDP
+    says whether OP is signed or unsigned.  NO_EXTEND is nonzero if we need
+    not actually do a sign-extend or zero-extend, but can leave the
+@@ -517,8 +572,9 @@
+     optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default);
+   if (ops->code == WIDEN_MULT_PLUS_EXPR
+       || ops->code == WIDEN_MULT_MINUS_EXPR)
+-    icode = (int) optab_handler (widen_pattern_optab,
+-				 TYPE_MODE (TREE_TYPE (ops->op2)));
++    icode = (int) find_widening_optab_handler (widen_pattern_optab,
++					       TYPE_MODE (TREE_TYPE (ops->op2)),
++					       tmode0, 0);
+   else
+     icode = (int) optab_handler (widen_pattern_optab, tmode0);
+   gcc_assert (icode != CODE_FOR_nothing);
+@@ -1389,7 +1445,9 @@
+ 		       rtx target, int unsignedp, enum optab_methods methods,
+ 		       rtx last)
+ {
+-  int icode = (int) optab_handler (binoptab, mode);
++  enum machine_mode from_mode = widened_mode (mode, op0, op1);
++  int icode = (int) find_widening_optab_handler (binoptab, mode,
++						 from_mode, 1);
+   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
+   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
+   enum machine_mode tmp_mode;
+@@ -1546,7 +1604,9 @@
+   /* If we can do it with a three-operand insn, do so.  */
+ 
+   if (methods != OPTAB_MUST_WIDEN
+-      && optab_handler (binoptab, mode) != CODE_FOR_nothing)
++      && find_widening_optab_handler (binoptab, mode,
++				      widened_mode (mode, op0, op1), 1)
++	    != CODE_FOR_nothing)
+     {
+       temp = expand_binop_directly (mode, binoptab, op0, op1, target,
+ 				    unsignedp, methods, last);
+@@ -1586,8 +1646,9 @@
+ 
+   if (binoptab == smul_optab
+       && GET_MODE_WIDER_MODE (mode) != VOIDmode
+-      && (optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab),
+-			 GET_MODE_WIDER_MODE (mode))
++      && (widening_optab_handler ((unsignedp ? umul_widen_optab
++					     : smul_widen_optab),
++				  GET_MODE_WIDER_MODE (mode), mode)
+ 	  != CODE_FOR_nothing))
+     {
+       temp = expand_binop (GET_MODE_WIDER_MODE (mode),
+@@ -1618,9 +1679,11 @@
+ 	if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing
+ 	    || (binoptab == smul_optab
+ 		&& GET_MODE_WIDER_MODE (wider_mode) != VOIDmode
+-		&& (optab_handler ((unsignedp ? umul_widen_optab
+-				    : smul_widen_optab),
+-				   GET_MODE_WIDER_MODE (wider_mode))
++		&& (find_widening_optab_handler ((unsignedp
++						  ? umul_widen_optab
++						  : smul_widen_optab),
++						 GET_MODE_WIDER_MODE (wider_mode),
++						 mode, 0)
+ 		    != CODE_FOR_nothing)))
+ 	  {
+ 	    rtx xop0 = op0, xop1 = op1;
+@@ -2043,8 +2106,8 @@
+       && optab_handler (add_optab, word_mode) != CODE_FOR_nothing)
+     {
+       rtx product = NULL_RTX;
+-
+-      if (optab_handler (umul_widen_optab, mode) != CODE_FOR_nothing)
++      if (widening_optab_handler (umul_widen_optab, mode, word_mode)
++	    != CODE_FOR_nothing)
+ 	{
+ 	  product = expand_doubleword_mult (mode, op0, op1, target,
+ 					    true, methods);
+@@ -2053,7 +2116,8 @@
+ 	}
+ 
+       if (product == NULL_RTX
+-	  && optab_handler (smul_widen_optab, mode) != CODE_FOR_nothing)
++	  && widening_optab_handler (smul_widen_optab, mode, word_mode)
++		!= CODE_FOR_nothing)
+ 	{
+ 	  product = expand_doubleword_mult (mode, op0, op1, target,
+ 					    false, methods);
+@@ -2144,7 +2208,8 @@
+ 	   wider_mode != VOIDmode;
+ 	   wider_mode = GET_MODE_WIDER_MODE (wider_mode))
+ 	{
+-	  if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing
++	  if (find_widening_optab_handler (binoptab, wider_mode, mode, 1)
++		  != CODE_FOR_nothing
+ 	      || (methods == OPTAB_LIB
+ 		  && optab_libfunc (binoptab, wider_mode)))
+ 	    {
+
+=== modified file 'gcc/optabs.h'
+--- old/gcc/optabs.h	2011-05-05 15:43:06 +0000
++++ new/gcc/optabs.h	2011-07-27 14:12:45 +0000
+@@ -42,6 +42,11 @@
+   int insn_code;
+ };
+ 
++struct widening_optab_handlers
++{
++  struct optab_handlers handlers[NUM_MACHINE_MODES][NUM_MACHINE_MODES];
++};
++
+ struct optab_d
+ {
+   enum rtx_code code;
+@@ -50,6 +55,7 @@
+   void (*libcall_gen)(struct optab_d *, const char *name, char suffix,
+ 		      enum machine_mode);
+   struct optab_handlers handlers[NUM_MACHINE_MODES];
++  struct widening_optab_handlers *widening;
+ };
+ typedef struct optab_d * optab;
+ 
+@@ -799,6 +805,15 @@
+ extern void emit_unop_insn (int, rtx, rtx, enum rtx_code);
+ extern bool maybe_emit_unop_insn (int, rtx, rtx, enum rtx_code);
+ 
++/* Find a widening optab even if it doesn't widen as much as we want.  */
++#define find_widening_optab_handler(A,B,C,D) \
++  find_widening_optab_handler_and_mode (A, B, C, D, NULL)
++extern enum insn_code find_widening_optab_handler_and_mode (optab,
++							    enum machine_mode,
++							    enum machine_mode,
++							    int,
++							    enum machine_mode *);
++
+ /* An extra flag to control optab_for_tree_code's behavior.  This is needed to
+    distinguish between machines with a vector shift that takes a scalar for the
+    shift amount vs. machines that take a vector for the shift amount.  */
+@@ -874,6 +889,23 @@
+ 			   + (int) CODE_FOR_nothing);
+ }
+ 
++/* Like optab_handler, but for widening_operations that have a TO_MODE and
++  a FROM_MODE.  */
++
++static inline enum insn_code
++widening_optab_handler (optab op, enum machine_mode to_mode,
++			enum machine_mode from_mode)
++{
++  if (to_mode == from_mode || from_mode == VOIDmode)
++    return optab_handler (op, to_mode);
++
++  if (op->widening)
++    return (enum insn_code) (op->widening->handlers[(int) to_mode][(int) from_mode].insn_code
++			     + (int) CODE_FOR_nothing);
++
++  return CODE_FOR_nothing;
++}
++
+ /* Record that insn CODE should be used to implement mode MODE of OP.  */
+ 
+ static inline void
+@@ -882,6 +914,26 @@
+   op->handlers[(int) mode].insn_code = (int) code - (int) CODE_FOR_nothing;
+ }
+ 
++/* Like set_optab_handler, but for widening operations that have a TO_MODE
++   and a FROM_MODE.  */
++
++static inline void
++set_widening_optab_handler (optab op, enum machine_mode to_mode,
++			    enum machine_mode from_mode, enum insn_code code)
++{
++  if (to_mode == from_mode)
++    set_optab_handler (op, to_mode, code);
++  else
++    {
++      if (op->widening == NULL)
++	op->widening = (struct widening_optab_handlers *)
++	      xcalloc (1, sizeof (struct widening_optab_handlers));
++
++      op->widening->handlers[(int) to_mode][(int) from_mode].insn_code
++	  = (int) code - (int) CODE_FOR_nothing;
++    }
++}
++
+ /* Return the insn used to perform conversion OP from mode FROM_MODE
+    to mode TO_MODE; return CODE_FOR_nothing if the target does not have
+    such an insn.  */
+
+=== added file 'gcc/testsuite/gcc.target/arm/no-wmla-1.c'
+--- old/gcc/testsuite/gcc.target/arm/no-wmla-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/no-wmla-1.c	2011-07-15 13:52:38 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++int
++foo (int a, short b, short c)
++{
++     int bc = b * c;
++        return a + (short)bc;
++}
++
++/* { dg-final { scan-assembler "mul" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-10.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-10.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-10.c	2011-07-18 12:56:20 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++unsigned long long
++foo (unsigned short a, unsigned short *b, unsigned short *c)
++{
++  return (unsigned)a + (unsigned long long)*b * (unsigned long long)*c;
++}
++
++/* { dg-final { scan-assembler "umlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-11.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-11.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-11.c	2011-07-22 15:46:42 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (int *b)
++{
++  return 10 * (long long)*b;
++}
++
++/* { dg-final { scan-assembler "smull" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-12.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-12.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-12.c	2011-07-22 15:46:42 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (int *b, int *c)
++{
++  int tmp = *b * *c;
++  return 10 + (long long)tmp;
++}
++
++/* { dg-final { scan-assembler "smlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-13.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-13.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-13.c	2011-07-22 15:46:42 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (int *a, int *b)
++{
++  return *a + (long long)*b * 10;
++}
++
++/* { dg-final { scan-assembler "smlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-5.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-5.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-5.c	2011-07-15 13:52:38 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (long long a, char *b, char *c)
++{
++  return a + *b * *c;
++}
++
++/* { dg-final { scan-assembler "umlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-6.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-6.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-6.c	2011-07-15 13:59:11 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (long long a, unsigned char *b, signed char *c)
++{
++  return a + (long long)*b * (long long)*c;
++}
++
++/* { dg-final { scan-assembler "smlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-7.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-7.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-7.c	2011-07-15 14:11:23 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++unsigned long long
++foo (unsigned long long a, unsigned char *b, unsigned short *c)
++{
++  return a + *b * *c;
++}
++
++/* { dg-final { scan-assembler "umlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-8.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-8.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-8.c	2011-07-15 14:16:54 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (long long a, int *b, int *c)
++{
++  return a + *b * *c;
++}
++
++/* { dg-final { scan-assembler "smlal" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-9.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-9.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-9.c	2011-07-15 14:22:39 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++long long
++foo (long long a, short *b, char *c)
++{
++  return a + *b * *c;
++}
++
++/* { dg-final { scan-assembler "smlalbb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c	2011-07-15 13:44:50 +0000
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++struct bf
++{
++  int a : 3;
++  int b : 15;
++  int c : 3;
++};
++
++long long
++foo (long long a, struct bf b, struct bf c)
++{
++  return a + b.b * c.b;
++}
++
++/* { dg-final { scan-assembler "smlalbb" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c	2011-07-15 14:22:39 +0000
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=armv7-a" } */
++
++struct bf
++{
++  int a : 3;
++  unsigned int b : 15;
++  int c : 3;
++};
++
++long long
++foo (long long a, struct bf b, struct bf c)
++{
++  return a + b.b * c.c;
++}
++
++/* { dg-final { scan-assembler "smlalbb" } } */
+
+=== modified file 'gcc/tree-cfg.c'
+--- old/gcc/tree-cfg.c	2011-07-01 09:19:21 +0000
++++ new/gcc/tree-cfg.c	2011-07-15 13:44:50 +0000
+@@ -3574,7 +3574,7 @@
+     case WIDEN_MULT_EXPR:
+       if (TREE_CODE (lhs_type) != INTEGER_TYPE)
+ 	return true;
+-      return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type))
++      return ((2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type))
+ 	      || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)));
+ 
+     case WIDEN_SUM_EXPR:
+@@ -3667,7 +3667,7 @@
+ 	   && !FIXED_POINT_TYPE_P (rhs1_type))
+ 	  || !useless_type_conversion_p (rhs1_type, rhs2_type)
+ 	  || !useless_type_conversion_p (lhs_type, rhs3_type)
+-	  || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)
++	  || 2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type)
+ 	  || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))
+ 	{
+ 	  error ("type mismatch in widening multiply-accumulate expression");
+
+=== modified file 'gcc/tree-ssa-math-opts.c'
+--- old/gcc/tree-ssa-math-opts.c	2011-03-11 16:36:16 +0000
++++ new/gcc/tree-ssa-math-opts.c	2011-08-09 10:26:48 +0000
+@@ -1266,39 +1266,67 @@
+  }
+ };
+ 
+-/* Return true if RHS is a suitable operand for a widening multiplication.
++/* Build a gimple assignment to cast VAL to TARGET.  Insert the statement
++   prior to GSI's current position, and return the fresh SSA name.  */
++
++static tree
++build_and_insert_cast (gimple_stmt_iterator *gsi, location_t loc,
++		       tree target, tree val)
++{
++  tree result = make_ssa_name (target, NULL);
++  gimple stmt = gimple_build_assign_with_ops (CONVERT_EXPR, result, val, NULL);
++  gimple_set_location (stmt, loc);
++  gsi_insert_before (gsi, stmt, GSI_SAME_STMT);
++  return result;
++}
++
++/* Return true if RHS is a suitable operand for a widening multiplication,
++   assuming a target type of TYPE.
+    There are two cases:
+ 
+-     - RHS makes some value twice as wide.  Store that value in *NEW_RHS_OUT
+-       if so, and store its type in *TYPE_OUT.
++     - RHS makes some value at least twice as wide.  Store that value
++       in *NEW_RHS_OUT if so, and store its type in *TYPE_OUT.
+ 
+      - RHS is an integer constant.  Store that value in *NEW_RHS_OUT if so,
+        but leave *TYPE_OUT untouched.  */
+ 
+ static bool
+-is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out)
++is_widening_mult_rhs_p (tree type, tree rhs, tree *type_out,
++			tree *new_rhs_out)
+ {
+   gimple stmt;
+-  tree type, type1, rhs1;
++  tree type1, rhs1;
+   enum tree_code rhs_code;
+ 
+   if (TREE_CODE (rhs) == SSA_NAME)
+     {
+-      type = TREE_TYPE (rhs);
+       stmt = SSA_NAME_DEF_STMT (rhs);
+-      if (!is_gimple_assign (stmt))
+-	return false;
+-
+-      rhs_code = gimple_assign_rhs_code (stmt);
+-      if (TREE_CODE (type) == INTEGER_TYPE
+-	  ? !CONVERT_EXPR_CODE_P (rhs_code)
+-	  : rhs_code != FIXED_CONVERT_EXPR)
+-	return false;
+-
+-      rhs1 = gimple_assign_rhs1 (stmt);
++      if (is_gimple_assign (stmt))
++	{
++	  rhs_code = gimple_assign_rhs_code (stmt);
++	  if (TREE_CODE (type) == INTEGER_TYPE
++	      ? !CONVERT_EXPR_CODE_P (rhs_code)
++	      : rhs_code != FIXED_CONVERT_EXPR)
++	    rhs1 = rhs;
++	  else
++	    {
++	      rhs1 = gimple_assign_rhs1 (stmt);
++
++	      if (TREE_CODE (rhs1) == INTEGER_CST)
++		{
++		  *new_rhs_out = rhs1;
++		  *type_out = NULL;
++		  return true;
++		}
++	    }
++	}
++      else
++	rhs1 = rhs;
++
+       type1 = TREE_TYPE (rhs1);
++
+       if (TREE_CODE (type1) != TREE_CODE (type)
+-	  || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type))
++	  || TYPE_PRECISION (type1) * 2 > TYPE_PRECISION (type))
+ 	return false;
+ 
+       *new_rhs_out = rhs1;
+@@ -1316,28 +1344,27 @@
+   return false;
+ }
+ 
+-/* Return true if STMT performs a widening multiplication.  If so,
+-   store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT
+-   respectively.  Also fill *RHS1_OUT and *RHS2_OUT such that converting
+-   those operands to types *TYPE1_OUT and *TYPE2_OUT would give the
+-   operands of the multiplication.  */
++/* Return true if STMT performs a widening multiplication, assuming the
++   output type is TYPE.  If so, store the unwidened types of the operands
++   in *TYPE1_OUT and *TYPE2_OUT respectively.  Also fill *RHS1_OUT and
++   *RHS2_OUT such that converting those operands to types *TYPE1_OUT
++   and *TYPE2_OUT would give the operands of the multiplication.  */
+ 
+ static bool
+-is_widening_mult_p (gimple stmt,
++is_widening_mult_p (tree type, gimple stmt,
+ 		    tree *type1_out, tree *rhs1_out,
+ 		    tree *type2_out, tree *rhs2_out)
+ {
+-  tree type;
+-
+-  type = TREE_TYPE (gimple_assign_lhs (stmt));
+   if (TREE_CODE (type) != INTEGER_TYPE
+       && TREE_CODE (type) != FIXED_POINT_TYPE)
+     return false;
+ 
+-  if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out))
++  if (!is_widening_mult_rhs_p (type, gimple_assign_rhs1 (stmt), type1_out,
++			       rhs1_out))
+     return false;
+ 
+-  if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out))
++  if (!is_widening_mult_rhs_p (type, gimple_assign_rhs2 (stmt), type2_out,
++			       rhs2_out))
+     return false;
+ 
+   if (*type1_out == NULL)
+@@ -1354,6 +1381,18 @@
+       *type2_out = *type1_out;
+     }
+ 
++  /* Ensure that the larger of the two operands comes first. */
++  if (TYPE_PRECISION (*type1_out) < TYPE_PRECISION (*type2_out))
++    {
++      tree tmp;
++      tmp = *type1_out;
++      *type1_out = *type2_out;
++      *type2_out = tmp;
++      tmp = *rhs1_out;
++      *rhs1_out = *rhs2_out;
++      *rhs2_out = tmp;
++    }
++
+   return true;
+ }
+ 
+@@ -1362,31 +1401,100 @@
+    value is true iff we converted the statement.  */
+ 
+ static bool
+-convert_mult_to_widen (gimple stmt)
++convert_mult_to_widen (gimple stmt, gimple_stmt_iterator *gsi)
+ {
+-  tree lhs, rhs1, rhs2, type, type1, type2;
++  tree lhs, rhs1, rhs2, type, type1, type2, tmp = NULL;
+   enum insn_code handler;
++  enum machine_mode to_mode, from_mode, actual_mode;
++  optab op;
++  int actual_precision;
++  location_t loc = gimple_location (stmt);
++  bool from_unsigned1, from_unsigned2;
+ 
+   lhs = gimple_assign_lhs (stmt);
+   type = TREE_TYPE (lhs);
+   if (TREE_CODE (type) != INTEGER_TYPE)
+     return false;
+ 
+-  if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
++  if (!is_widening_mult_p (type, stmt, &type1, &rhs1, &type2, &rhs2))
+     return false;
+ 
+-  if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2))
+-    handler = optab_handler (umul_widen_optab, TYPE_MODE (type));
+-  else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2))
+-    handler = optab_handler (smul_widen_optab, TYPE_MODE (type));
++  to_mode = TYPE_MODE (type);
++  from_mode = TYPE_MODE (type1);
++  from_unsigned1 = TYPE_UNSIGNED (type1);
++  from_unsigned2 = TYPE_UNSIGNED (type2);
++
++  if (from_unsigned1 && from_unsigned2)
++    op = umul_widen_optab;
++  else if (!from_unsigned1 && !from_unsigned2)
++    op = smul_widen_optab;
+   else
+-    handler = optab_handler (usmul_widen_optab, TYPE_MODE (type));
++    op = usmul_widen_optab;
++
++  handler = find_widening_optab_handler_and_mode (op, to_mode, from_mode,
++						  0, &actual_mode);
+ 
+   if (handler == CODE_FOR_nothing)
+-    return false;
+-
+-  gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1));
+-  gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2));
++    {
++      if (op != smul_widen_optab)
++	{
++	  /* We can use a signed multiply with unsigned types as long as
++	     there is a wider mode to use, or it is the smaller of the two
++	     types that is unsigned.  Note that type1 >= type2, always.  */
++	  if ((TYPE_UNSIGNED (type1)
++	       && TYPE_PRECISION (type1) == GET_MODE_PRECISION (from_mode))
++	      || (TYPE_UNSIGNED (type2)
++		  && TYPE_PRECISION (type2) == GET_MODE_PRECISION (from_mode)))
++	    {
++	      from_mode = GET_MODE_WIDER_MODE (from_mode);
++	      if (GET_MODE_SIZE (to_mode) <= GET_MODE_SIZE (from_mode))
++		return false;
++	    }
++
++	  op = smul_widen_optab;
++	  handler = find_widening_optab_handler_and_mode (op, to_mode,
++							  from_mode, 0,
++							  &actual_mode);
++
++	  if (handler == CODE_FOR_nothing)
++	    return false;
++
++	  from_unsigned1 = from_unsigned2 = false;
++	}
++      else
++	return false;
++    }
++
++  /* Ensure that the inputs to the handler are in the correct precison
++     for the opcode.  This will be the full mode size.  */
++  actual_precision = GET_MODE_PRECISION (actual_mode);
++  if (actual_precision != TYPE_PRECISION (type1)
++      || from_unsigned1 != TYPE_UNSIGNED (type1))
++    {
++      tmp = create_tmp_var (build_nonstandard_integer_type
++				(actual_precision, from_unsigned1),
++			    NULL);
++      rhs1 = build_and_insert_cast (gsi, loc, tmp, rhs1);
++    }
++  if (actual_precision != TYPE_PRECISION (type2)
++      || from_unsigned2 != TYPE_UNSIGNED (type2))
++    {
++      /* Reuse the same type info, if possible.  */
++      if (!tmp || from_unsigned1 != from_unsigned2)
++	tmp = create_tmp_var (build_nonstandard_integer_type
++				(actual_precision, from_unsigned2),
++			      NULL);
++      rhs2 = build_and_insert_cast (gsi, loc, tmp, rhs2);
++    }
++
++  /* Handle constants.  */
++  if (TREE_CODE (rhs1) == INTEGER_CST)
++    rhs1 = fold_convert (type1, rhs1);
++  if (TREE_CODE (rhs2) == INTEGER_CST)
++    rhs2 = fold_convert (type2, rhs2);
++
++  gimple_assign_set_rhs1 (stmt, rhs1);
++  gimple_assign_set_rhs2 (stmt, rhs2);
+   gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR);
+   update_stmt (stmt);
+   return true;
+@@ -1403,11 +1511,17 @@
+ 			    enum tree_code code)
+ {
+   gimple rhs1_stmt = NULL, rhs2_stmt = NULL;
+-  tree type, type1, type2;
++  gimple conv1_stmt = NULL, conv2_stmt = NULL, conv_stmt;
++  tree type, type1, type2, optype, tmp = NULL;
+   tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs;
+   enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK;
+   optab this_optab;
+   enum tree_code wmult_code;
++  enum insn_code handler;
++  enum machine_mode to_mode, from_mode, actual_mode;
++  location_t loc = gimple_location (stmt);
++  int actual_precision;
++  bool from_unsigned1, from_unsigned2;
+ 
+   lhs = gimple_assign_lhs (stmt);
+   type = TREE_TYPE (lhs);
+@@ -1429,8 +1543,6 @@
+       if (is_gimple_assign (rhs1_stmt))
+ 	rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
+     }
+-  else
+-    return false;
+ 
+   if (TREE_CODE (rhs2) == SSA_NAME)
+     {
+@@ -1438,57 +1550,160 @@
+       if (is_gimple_assign (rhs2_stmt))
+ 	rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
+     }
+-  else
+-    return false;
+-
+-  if (code == PLUS_EXPR && rhs1_code == MULT_EXPR)
+-    {
+-      if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
+-			       &type2, &mult_rhs2))
+-	return false;
+-      add_rhs = rhs2;
+-    }
+-  else if (rhs2_code == MULT_EXPR)
+-    {
+-      if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
+-			       &type2, &mult_rhs2))
+-	return false;
+-      add_rhs = rhs1;
+-    }
+-  else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR)
+-    {
+-      mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt);
+-      mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt);
+-      type1 = TREE_TYPE (mult_rhs1);
+-      type2 = TREE_TYPE (mult_rhs2);
+-      add_rhs = rhs2;
+-    }
+-  else if (rhs2_code == WIDEN_MULT_EXPR)
+-    {
+-      mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt);
+-      mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt);
+-      type1 = TREE_TYPE (mult_rhs1);
+-      type2 = TREE_TYPE (mult_rhs2);
+-      add_rhs = rhs1;
+-    }
+-  else
+-    return false;
+-
+-  if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2))
+-    return false;
++
++  /* Allow for one conversion statement between the multiply
++     and addition/subtraction statement.  If there are more than
++     one conversions then we assume they would invalidate this
++     transformation.  If that's not the case then they should have
++     been folded before now.  */
++  if (CONVERT_EXPR_CODE_P (rhs1_code))
++    {
++      conv1_stmt = rhs1_stmt;
++      rhs1 = gimple_assign_rhs1 (rhs1_stmt);
++      if (TREE_CODE (rhs1) == SSA_NAME)
++	{
++	  rhs1_stmt = SSA_NAME_DEF_STMT (rhs1);
++	  if (is_gimple_assign (rhs1_stmt))
++	    rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
++	}
++      else
++	return false;
++    }
++  if (CONVERT_EXPR_CODE_P (rhs2_code))
++    {
++      conv2_stmt = rhs2_stmt;
++      rhs2 = gimple_assign_rhs1 (rhs2_stmt);
++      if (TREE_CODE (rhs2) == SSA_NAME)
++	{
++	  rhs2_stmt = SSA_NAME_DEF_STMT (rhs2);
++	  if (is_gimple_assign (rhs2_stmt))
++	    rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
++	}
++      else
++	return false;
++    }
++
++  /* If code is WIDEN_MULT_EXPR then it would seem unnecessary to call
++     is_widening_mult_p, but we still need the rhs returns.
++
++     It might also appear that it would be sufficient to use the existing
++     operands of the widening multiply, but that would limit the choice of
++     multiply-and-accumulate instructions.  */
++  if (code == PLUS_EXPR
++      && (rhs1_code == MULT_EXPR || rhs1_code == WIDEN_MULT_EXPR))
++    {
++      if (!is_widening_mult_p (type, rhs1_stmt, &type1, &mult_rhs1,
++			       &type2, &mult_rhs2))
++	return false;
++      add_rhs = rhs2;
++      conv_stmt = conv1_stmt;
++    }
++  else if (rhs2_code == MULT_EXPR || rhs2_code == WIDEN_MULT_EXPR)
++    {
++      if (!is_widening_mult_p (type, rhs2_stmt, &type1, &mult_rhs1,
++			       &type2, &mult_rhs2))
++	return false;
++      add_rhs = rhs1;
++      conv_stmt = conv2_stmt;
++    }
++  else
++    return false;
++
++  to_mode = TYPE_MODE (type);
++  from_mode = TYPE_MODE (type1);
++  from_unsigned1 = TYPE_UNSIGNED (type1);
++  from_unsigned2 = TYPE_UNSIGNED (type2);
++
++  /* There's no such thing as a mixed sign madd yet, so use a wider mode.  */
++  if (from_unsigned1 != from_unsigned2)
++    {
++      /* We can use a signed multiply with unsigned types as long as
++	 there is a wider mode to use, or it is the smaller of the two
++	 types that is unsigned.  Note that type1 >= type2, always.  */
++      if ((from_unsigned1
++	   && TYPE_PRECISION (type1) == GET_MODE_PRECISION (from_mode))
++	  || (from_unsigned2
++	      && TYPE_PRECISION (type2) == GET_MODE_PRECISION (from_mode)))
++	{
++	  from_mode = GET_MODE_WIDER_MODE (from_mode);
++	  if (GET_MODE_SIZE (from_mode) >= GET_MODE_SIZE (to_mode))
++	    return false;
++	}
++
++      from_unsigned1 = from_unsigned2 = false;
++    }
++
++  /* If there was a conversion between the multiply and addition
++     then we need to make sure it fits a multiply-and-accumulate.
++     The should be a single mode change which does not change the
++     value.  */
++  if (conv_stmt)
++    {
++      /* We use the original, unmodified data types for this.  */
++      tree from_type = TREE_TYPE (gimple_assign_rhs1 (conv_stmt));
++      tree to_type = TREE_TYPE (gimple_assign_lhs (conv_stmt));
++      int data_size = TYPE_PRECISION (type1) + TYPE_PRECISION (type2);
++      bool is_unsigned = TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2);
++
++      if (TYPE_PRECISION (from_type) > TYPE_PRECISION (to_type))
++	{
++	  /* Conversion is a truncate.  */
++	  if (TYPE_PRECISION (to_type) < data_size)
++	    return false;
++	}
++      else if (TYPE_PRECISION (from_type) < TYPE_PRECISION (to_type))
++	{
++	  /* Conversion is an extend.  Check it's the right sort.  */
++	  if (TYPE_UNSIGNED (from_type) != is_unsigned
++	      && !(is_unsigned && TYPE_PRECISION (from_type) > data_size))
++	    return false;
++	}
++      /* else convert is a no-op for our purposes.  */
++    }
+ 
+   /* Verify that the machine can perform a widening multiply
+      accumulate in this mode/signedness combination, otherwise
+      this transformation is likely to pessimize code.  */
+-  this_optab = optab_for_tree_code (wmult_code, type1, optab_default);
+-  if (optab_handler (this_optab, TYPE_MODE (type)) == CODE_FOR_nothing)
++  optype = build_nonstandard_integer_type (from_mode, from_unsigned1);
++  this_optab = optab_for_tree_code (wmult_code, optype, optab_default);
++  handler = find_widening_optab_handler_and_mode (this_optab, to_mode,
++						  from_mode, 0, &actual_mode);
++
++  if (handler == CODE_FOR_nothing)
+     return false;
+ 
+-  /* ??? May need some type verification here?  */
+-
+-  gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code,
+-				    fold_convert (type1, mult_rhs1),
+-				    fold_convert (type2, mult_rhs2),
++  /* Ensure that the inputs to the handler are in the correct precison
++     for the opcode.  This will be the full mode size.  */
++  actual_precision = GET_MODE_PRECISION (actual_mode);
++  if (actual_precision != TYPE_PRECISION (type1)
++      || from_unsigned1 != TYPE_UNSIGNED (type1))
++    {
++      tmp = create_tmp_var (build_nonstandard_integer_type
++				(actual_precision, from_unsigned1),
++			    NULL);
++      mult_rhs1 = build_and_insert_cast (gsi, loc, tmp, mult_rhs1);
++    }
++  if (actual_precision != TYPE_PRECISION (type2)
++      || from_unsigned2 != TYPE_UNSIGNED (type2))
++    {
++      if (!tmp || from_unsigned1 != from_unsigned2)
++	tmp = create_tmp_var (build_nonstandard_integer_type
++				(actual_precision, from_unsigned2),
++			      NULL);
++      mult_rhs2 = build_and_insert_cast (gsi, loc, tmp, mult_rhs2);
++    }
++
++  if (!useless_type_conversion_p (type, TREE_TYPE (add_rhs)))
++    add_rhs = build_and_insert_cast (gsi, loc, create_tmp_var (type, NULL),
++				     add_rhs);
++
++  /* Handle constants.  */
++  if (TREE_CODE (mult_rhs1) == INTEGER_CST)
++    rhs1 = fold_convert (type1, mult_rhs1);
++  if (TREE_CODE (mult_rhs2) == INTEGER_CST)
++    rhs2 = fold_convert (type2, mult_rhs2);
++
++  gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, mult_rhs1, mult_rhs2,
+ 				    add_rhs);
+   update_stmt (gsi_stmt (*gsi));
+   return true;
+@@ -1696,7 +1911,7 @@
+ 	      switch (code)
+ 		{
+ 		case MULT_EXPR:
+-		  if (!convert_mult_to_widen (stmt)
++		  if (!convert_mult_to_widen (stmt, &gsi)
+ 		      && convert_mult_to_fma (stmt,
+ 					      gimple_assign_rhs1 (stmt),
+ 					      gimple_assign_rhs2 (stmt)))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch
new file mode 100644
index 0000000000..8230beb91e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch
@@ -0,0 +1,23 @@
+2011-08-26  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-08-26  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* df-problems.c (df_note_bb_compute): Pass uses rather than defs
+	to df_set_dead_notes_for_mw.
+
+=== modified file 'gcc/df-problems.c'
+--- old/gcc/df-problems.c	2011-07-07 19:10:01 +0000
++++ new/gcc/df-problems.c	2011-08-26 14:32:47 +0000
+@@ -3375,7 +3375,7 @@
+       while (*mws_rec)
+ 	{
+ 	  struct df_mw_hardreg *mws = *mws_rec;
+-	  if ((DF_MWS_REG_DEF_P (mws))
++	  if (DF_MWS_REG_USE_P (mws)
+ 	      && !df_ignore_stack_reg (mws->start_regno))
+ 	    {
+ 	      bool really_add_notes = debug_insn != 0;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch
new file mode 100644
index 0000000000..aa067b7113
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch
@@ -0,0 +1,23 @@
+2011-09-05  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+
+	2011-08-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+        PR target/48328
+	* config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance
+	for tbh instructions.
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-08-24 17:35:16 +0000
++++ new/gcc/config/arm/arm.h	2011-09-05 14:32:11 +0000
+@@ -1961,7 +1961,7 @@
+       : min >= -4096 && max < 4096					\
+       ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode)	\
+       : SImode)								\
+-   : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode		\
++   : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode		\
+       : (max >= 0x200) ? HImode						\
+       : QImode))
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch
new file mode 100644
index 0000000000..c440db91e1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch
@@ -0,0 +1,75 @@
+ 2011-09-05  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+ 
+       Backport from mainline.
+       2011-08-26  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       * config/arm/cortex-a9.md ("cortex_a9_mult_long"): New.
+       ("cortex_a9_multiply_long"): New and use above.  Handle all
+        long multiply cases.
+       ("cortex_a9_multiply"): Handle smmul and smmulr.
+       ("cortex_a9_mac"): Handle smmla.
+
+=== modified file 'gcc/config/arm/cortex-a9.md'
+--- old/gcc/config/arm/cortex-a9.md	2011-01-18 15:28:08 +0000
++++ new/gcc/config/arm/cortex-a9.md	2011-08-26 08:52:15 +0000
+@@ -68,7 +68,8 @@
+   "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
+ (define_reservation "cortex_a9_mac"
+   "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
+-
++(define_reservation "cortex_a9_mult_long"
++  "cortex_a9_mac_m1*3, cortex_a9_mac_m2, cortex_a9_p0_wb")
+ 
+ ;; Issue at the same time along the load store pipeline and
+ ;; the VFP / Neon pipeline is not possible.
+@@ -139,29 +140,35 @@
+        (eq_attr "insn" "smlaxy"))
+   "cortex_a9_mac16")
+ 
+-
+ (define_insn_reservation "cortex_a9_multiply" 4
+   (and (eq_attr "tune" "cortexa9")
+-       (eq_attr "insn" "mul"))
++       (eq_attr "insn" "mul,smmul,smmulr"))
+        "cortex_a9_mult")
+ 
+ (define_insn_reservation "cortex_a9_mac" 4
+   (and (eq_attr "tune" "cortexa9")
+-       (eq_attr "insn" "mla"))
++       (eq_attr "insn" "mla,smmla"))
+        "cortex_a9_mac")
+ 
++(define_insn_reservation "cortex_a9_multiply_long" 5
++  (and (eq_attr "tune" "cortexa9")
++       (eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
++       "cortex_a9_mult_long")
++
+ ;; An instruction with a result in E2 can be forwarded
+ ;; to E2 or E1 or M1 or the load store unit in the next cycle.
+ 
+ (define_bypass 1 "cortex_a9_dp"
+                  "cortex_a9_dp_shift, cortex_a9_multiply,
+  cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
+- cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
++ cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4, 
++ cortex_a9_multiply_long")
+ 
+ (define_bypass 2 "cortex_a9_dp_shift"
+                  "cortex_a9_dp_shift, cortex_a9_multiply,
+  cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
+- cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
++ cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
++ cortex_a9_multiply_long")
+ 
+ ;; An instruction in the load store pipeline can provide
+ ;; read access to a DP instruction in the P0 default pipeline
+@@ -212,7 +219,7 @@
+ 
+ (define_bypass 1
+   "cortex_a9_fps"
+-  "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply")
++  "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_multiply_long")
+ 
+ ;; Scheduling on the FP_ADD pipeline.
+ (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch
new file mode 100644
index 0000000000..dfdeec7245
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch
@@ -0,0 +1,1270 @@
+2011-09-07  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-08-04  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vectorizer.h (struct _stmt_vec_info): Add new field for
+	pattern def statement, and its access macro.
+	(NUM_PATTERNS): Set to 5.
+	* tree-vect-loop.c (vect_determine_vectorization_factor): Handle
+	pattern def statement.
+	(vect_transform_loop): Likewise.
+	* tree-vect-patterns.c (vect_vect_recog_func_ptrs): Add new
+	function vect_recog_over_widening_pattern ().
+	(vect_operation_fits_smaller_type): New function.
+	(vect_recog_over_widening_pattern, vect_mark_pattern_stmts):
+	Likewise.
+	(vect_pattern_recog_1): Move the code that marks pattern
+	statements to vect_mark_pattern_stmts (), and call it.  Update
+	documentation.
+	* tree-vect-stmts.c (vect_supportable_shift): New function.
+	(vect_analyze_stmt): Handle pattern def statement.
+	(new_stmt_vec_info): Initialize pattern def statement.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-over-widen-1.c: New test.
+	* gcc.dg/vect/vect-over-widen-2.c: New test.
+	* gcc.dg/vect/vect-over-widen-3.c: New test.
+	* gcc.dg/vect/vect-over-widen-4.c: New test.
+
+
+	2011-08-09  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	PR tree-optimization/50014
+	* tree-vect-loop.c (vectorizable_reduction): Get def type before
+	calling vect_get_vec_def_for_stmt_copy ().
+
+	gcc/testsuite/
+	PR tree-optimization/50014
+	* gcc.dg/vect/pr50014.c: New test.
+
+
+	2011-08-11  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	PR tree-optimization/50039
+	* tree-vect-patterns.c (vect_operation_fits_smaller_type): Check
+	that DEF_STMT has a stmt_vec_info.
+
+	gcc/testsuite/
+	PR tree-optimization/50039
+	* gcc.dg/vect/vect.exp: Run no-tree-fre-* tests with -fno-tree-fre.
+	* gcc.dg/vect/no-tree-fre-pr50039.c: New test.
+
+
+	2011-09-04  Jakub Jelinek  <jakub@redhat.com>
+		    Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	PR tree-optimization/50208
+	* tree-vect-patterns.c (vect_handle_widen_mult_by_const): Add an
+	argument.  Check that def_stmt is inside the loop.
+	(vect_recog_widen_mult_pattern): Update calls to
+	vect_handle_widen_mult_by_cons.
+	(vect_operation_fits_smaller_type): Check that def_stmt is
+	inside the loop.
+
+	gcc/testsuite/
+	PR tree-optimization/50208
+	* gcc.dg/vect/no-fre-pre-pr50208.c: New test.
+	* gcc.dg/vect/vect.exp: Run no-fre-pre-*.c tests with
+	-fno-tree-fre -fno-tree-pre.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++
++char c;
++int a, b;
++
++void foo (int j)
++{
++  int i;
++  while (--j)
++    {
++      b = 3;
++      for (i = 0; i < 2; ++i)
++        a = b ^ c;
++    }
++}
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== added file 'gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++
++extern unsigned char g_5;
++extern int g_31, g_76;
++int main(void) {
++ int i, j;
++    for (j=0; j < 2; ++j) {
++        g_31 = -3;
++        for (i=0; i < 2; ++i)
++          g_76 = (g_31 ? g_31+1 : 0) ^ g_5;
++    }
++}
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/pr50014.c'
+--- old/gcc/testsuite/gcc.dg/vect/pr50014.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/pr50014.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target vect_int } */
++
++int f(unsigned char *s, int n)
++{
++  int sum = 0;
++  int i;
++
++  for (i = 0; i < n; i++)
++    sum += 256 * s[i];
++
++  return sum;
++}
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,64 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdlib.h>
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++
++/* Modified rgb to rgb conversion from FFmpeg.  */
++__attribute__ ((noinline)) void
++foo (unsigned char *src, unsigned char *dst)
++{
++  unsigned char *s = src;
++  unsigned short *d = (unsigned short *)dst;
++  int i;
++
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      *d = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
++      d++;
++    }
++
++  s = src;
++  d = (unsigned short *)dst;
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
++        abort ();
++      d++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  unsigned char in[N], out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,65 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdlib.h>
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++
++/* Modified rgb to rgb conversion from FFmpeg.  */
++__attribute__ ((noinline)) void
++foo (unsigned char *src, unsigned char *dst)
++{
++  unsigned char *s = src;
++  int *d = (int *)dst;
++  int i;
++
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      *d = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
++      d++;
++    }
++
++  s = src;
++  d = (int *)dst;
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
++        abort ();
++      d++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  unsigned char in[N], out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* Final value stays in int, so no over-widening is detected at the moment.  */
++/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 0 "vect" } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,64 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdlib.h>
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++
++/* Modified rgb to rgb conversion from FFmpeg.  */
++__attribute__ ((noinline)) void
++foo (unsigned char *src, unsigned char *dst)
++{
++  unsigned char *s = src;
++  unsigned short *d = (unsigned short *)dst;
++  int i;
++
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      *d = ((b>>3) | ((g&0xFFC)<<3) | ((r+0xF8)>>8) | (a<<9));
++      d++;
++    }
++
++  s = src;
++  d = (unsigned short *)dst;
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      if (*d != ((b>>3) | ((g&0xFFC)<<3) | ((r+0xF8)>>8) | (a<<9)))
++        abort ();
++      d++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  unsigned char in[N], out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c	2011-09-05 06:23:37 +0000
+@@ -0,0 +1,68 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdlib.h>
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++
++/* Modified rgb to rgb conversion from FFmpeg.  */
++__attribute__ ((noinline)) int
++foo (unsigned char *src, unsigned char *dst)
++{
++  unsigned char *s = src;
++  unsigned short *d = (unsigned short *)dst, res;
++  int i, result = 0;
++
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      res = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
++      *d = res;
++      result += res;
++      d++;
++    }
++
++  s = src;
++  d = (unsigned short *)dst;
++  for (i = 0; i < N/4; i++)
++    {
++      const int b = *s++;
++      const int g = *s++;
++      const int r = *s++;
++      const int a = *s++;
++      if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
++        abort ();
++      d++;
++    }
++
++  return result;
++}
++
++int main (void)
++{
++  int i;
++  unsigned char in[N], out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
+--- old/gcc/testsuite/gcc.dg/vect/vect.exp	2011-05-05 15:43:31 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect.exp	2011-09-05 06:23:37 +0000
+@@ -245,6 +245,18 @@
+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-tree-reassoc-bb-slp-*.\[cS\]]]  \
+         "" $VECT_SLP_CFLAGS
+ 
++# -fno-tree-fre
++set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
++lappend DEFAULT_VECTCFLAGS "-fno-tree-fre"
++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-tree-fre-*.\[cS\]]]  \
++        "" $DEFAULT_VECTCFLAGS
++
++# -fno-tree-fre -fno-tree-pre
++set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
++lappend DEFAULT_VECTCFLAGS "-fno-tree-fre" "-fno-tree-pre"
++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-fre-pre*.\[cS\]]]  \
++        "" $DEFAULT_VECTCFLAGS
++
+ # Clean up.
+ set dg-do-what-default ${save-dg-do-what-default}
+ 
+
+=== modified file 'gcc/tree-vect-loop.c'
+--- old/gcc/tree-vect-loop.c	2011-07-11 11:02:55 +0000
++++ new/gcc/tree-vect-loop.c	2011-09-05 06:23:37 +0000
+@@ -181,8 +181,8 @@
+   stmt_vec_info stmt_info;
+   int i;
+   HOST_WIDE_INT dummy;
+-  gimple stmt, pattern_stmt = NULL;
+-  bool analyze_pattern_stmt = false;
++  gimple stmt, pattern_stmt = NULL, pattern_def_stmt = NULL;
++  bool analyze_pattern_stmt = false, pattern_def = false;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vect_determine_vectorization_factor ===");
+@@ -297,6 +297,29 @@
+                        || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
+             analyze_pattern_stmt = true;
+ 
++          /* If a pattern statement has a def stmt, analyze it too.  */
++          if (is_pattern_stmt_p (stmt_info)
++              && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
++              && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
++                  || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
++            {
++              if (pattern_def)
++                pattern_def = false;
++              else
++                {
++                  if (vect_print_dump_info (REPORT_DETAILS))
++                    {
++                      fprintf (vect_dump, "==> examining pattern def stmt: ");
++                      print_gimple_stmt (vect_dump, pattern_def_stmt, 0,
++                                         TDF_SLIM);
++                    }
++
++                  pattern_def = true;
++                  stmt = pattern_def_stmt;
++                  stmt_info = vinfo_for_stmt (stmt);
++                }
++            }
++
+ 	  if (gimple_get_lhs (stmt) == NULL_TREE)
+ 	    {
+ 	      if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
+@@ -401,7 +424,7 @@
+ 	      || (nunits > vectorization_factor))
+ 	    vectorization_factor = nunits;
+ 
+-          if (!analyze_pattern_stmt)
++          if (!analyze_pattern_stmt && !pattern_def)
+             gsi_next (&si);
+         }
+     }
+@@ -3985,7 +4008,7 @@
+   VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL, *vect_defs = NULL;
+   VEC (gimple, heap) *phis = NULL;
+   int vec_num;
+-  tree def0, def1, tem;
++  tree def0, def1, tem, op0, op1 = NULL_TREE;
+ 
+   if (nested_in_vect_loop_p (loop, stmt))
+     {
+@@ -4418,8 +4441,6 @@
+       /* Handle uses.  */
+       if (j == 0)
+         {
+-          tree op0, op1 = NULL_TREE;
+-
+           op0 = ops[!reduc_index];
+           if (op_type == ternary_op)
+             {
+@@ -4449,11 +4470,19 @@
+         {
+           if (!slp_node)
+             {
+-              enum vect_def_type dt = vect_unknown_def_type; /* Dummy */
+-              loop_vec_def0 = vect_get_vec_def_for_stmt_copy (dt, loop_vec_def0);
++              enum vect_def_type dt;
++              gimple dummy_stmt;
++              tree dummy;
++
++              vect_is_simple_use (ops[!reduc_index], loop_vinfo, NULL,
++                                  &dummy_stmt, &dummy, &dt);
++              loop_vec_def0 = vect_get_vec_def_for_stmt_copy (dt,
++                                                              loop_vec_def0);
+               VEC_replace (tree, vec_oprnds0, 0, loop_vec_def0);
+               if (op_type == ternary_op)
+                 {
++                  vect_is_simple_use (op1, loop_vinfo, NULL, &dummy_stmt,
++                                      &dummy, &dt);
+                   loop_vec_def1 = vect_get_vec_def_for_stmt_copy (dt,
+                                                                 loop_vec_def1);
+                   VEC_replace (tree, vec_oprnds1, 0, loop_vec_def1);
+@@ -4758,8 +4787,8 @@
+   tree cond_expr = NULL_TREE;
+   gimple_seq cond_expr_stmt_list = NULL;
+   bool do_peeling_for_loop_bound;
+-  gimple stmt, pattern_stmt;
+-  bool transform_pattern_stmt = false;
++  gimple stmt, pattern_stmt, pattern_def_stmt;
++  bool transform_pattern_stmt = false, pattern_def = false;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vec_transform_loop ===");
+@@ -4903,6 +4932,30 @@
+                        || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
+             transform_pattern_stmt = true;
+ 
++          /* If pattern statement has a def stmt, vectorize it too.  */
++          if (is_pattern_stmt_p (stmt_info)
++              && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
++              && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
++                  || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
++            {
++              if (pattern_def)
++                pattern_def = false;
++              else
++                {
++                  if (vect_print_dump_info (REPORT_DETAILS))
++                    {
++                      fprintf (vect_dump, "==> vectorizing pattern def"
++                                          " stmt: ");
++                      print_gimple_stmt (vect_dump, pattern_def_stmt, 0,
++                                         TDF_SLIM);
++                    }
++
++                  pattern_def = true;
++                  stmt = pattern_def_stmt;
++                  stmt_info = vinfo_for_stmt (stmt);
++                }
++            }
++
+ 	  gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
+ 	  nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
+                                                STMT_VINFO_VECTYPE (stmt_info));
+@@ -4930,7 +4983,7 @@
+ 	      /* Hybrid SLP stmts must be vectorized in addition to SLP.  */
+ 	      if (!vinfo_for_stmt (stmt) || PURE_SLP_STMT (stmt_info))
+ 		{
+-                  if (!transform_pattern_stmt)
++                  if (!transform_pattern_stmt && !pattern_def)
+  		    gsi_next (&si);
+   		  continue;
+ 		}
+@@ -4962,7 +5015,7 @@
+ 		}
+ 	    }
+ 
+-          if (!transform_pattern_stmt)
++          if (!transform_pattern_stmt && !pattern_def)
+  	    gsi_next (&si);
+ 	}		        /* stmts in BB */
+     }				/* BBs in loop */
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2011-07-06 12:04:10 +0000
++++ new/gcc/tree-vect-patterns.c	2011-09-05 06:23:37 +0000
+@@ -46,11 +46,14 @@
+ static gimple vect_recog_dot_prod_pattern (VEC (gimple, heap) **, tree *,
+ 					   tree *);
+ static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
++static gimple vect_recog_over_widening_pattern (VEC (gimple, heap) **, tree *,
++                                                 tree *);
+ static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
+ 	vect_recog_widen_mult_pattern,
+ 	vect_recog_widen_sum_pattern,
+ 	vect_recog_dot_prod_pattern,
+-	vect_recog_pow_pattern};
++	vect_recog_pow_pattern,
++        vect_recog_over_widening_pattern};
+ 
+ 
+ /* Function widened_name_p
+@@ -339,12 +342,14 @@
+    replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t;  */
+ 
+ static bool
+-vect_handle_widen_mult_by_const (tree const_oprnd, tree *oprnd,
++vect_handle_widen_mult_by_const (gimple stmt, tree const_oprnd, tree *oprnd,
+                                  VEC (gimple, heap) **stmts, tree type,
+                                  tree *half_type, gimple def_stmt)
+ {
+   tree new_type, new_oprnd, tmp;
+   gimple new_stmt;
++  loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
++  struct loop *loop = LOOP_VINFO_LOOP (loop_info);
+ 
+   if (int_fits_type_p (const_oprnd, *half_type))
+     {
+@@ -354,6 +359,8 @@
+     }
+ 
+   if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
++      || !gimple_bb (def_stmt)
++      || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
+       || !vinfo_for_stmt (def_stmt))
+     return false;
+ 
+@@ -522,7 +529,8 @@
+     {
+       if (TREE_CODE (oprnd0) == INTEGER_CST
+           && TREE_CODE (half_type1) == INTEGER_TYPE
+-          && vect_handle_widen_mult_by_const (oprnd0, &oprnd1, stmts, type,
++          && vect_handle_widen_mult_by_const (last_stmt, oprnd0, &oprnd1, 
++		                              stmts, type,
+                                               &half_type1, def_stmt1))
+         half_type0 = half_type1;
+       else
+@@ -532,7 +540,8 @@
+     {
+       if (TREE_CODE (oprnd1) == INTEGER_CST
+           && TREE_CODE (half_type0) == INTEGER_TYPE
+-          && vect_handle_widen_mult_by_const (oprnd1, &oprnd0, stmts, type,
++          && vect_handle_widen_mult_by_const (last_stmt, oprnd1, &oprnd0,
++		                              stmts, type,
+                                               &half_type0, def_stmt0))
+         half_type1 = half_type0;
+       else
+@@ -826,6 +835,424 @@
+ }
+ 
+ 
++/* Return TRUE if the operation in STMT can be performed on a smaller type.
++
++   Input:
++   STMT - a statement to check.
++   DEF - we support operations with two operands, one of which is constant.
++         The other operand can be defined by a demotion operation, or by a
++         previous statement in a sequence of over-promoted operations.  In the
++         later case DEF is used to replace that operand.  (It is defined by a
++         pattern statement we created for the previous statement in the
++         sequence).
++
++   Input/output:
++   NEW_TYPE - Output: a smaller type that we are trying to use.  Input: if not
++         NULL, it's the type of DEF.
++   STMTS - additional pattern statements.  If a pattern statement (type
++         conversion) is created in this function, its original statement is
++         added to STMTS.
++
++   Output:
++   OP0, OP1 - if the operation fits a smaller type, OP0 and OP1 are the new
++         operands to use in the new pattern statement for STMT (will be created
++         in vect_recog_over_widening_pattern ()).
++   NEW_DEF_STMT - in case DEF has to be promoted, we create two pattern
++         statements for STMT: the first one is a type promotion and the second
++         one is the operation itself.  We return the type promotion statement
++         in NEW_DEF_STMT and further store it in STMT_VINFO_PATTERN_DEF_STMT of
++         the second pattern statement.  */
++
++static bool
++vect_operation_fits_smaller_type (gimple stmt, tree def, tree *new_type,
++                                  tree *op0, tree *op1, gimple *new_def_stmt,
++                                  VEC (gimple, heap) **stmts)
++{
++  enum tree_code code;
++  tree const_oprnd, oprnd;
++  tree interm_type = NULL_TREE, half_type, tmp, new_oprnd, type;
++  gimple def_stmt, new_stmt;
++  bool first = false;
++  loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
++  struct loop *loop = LOOP_VINFO_LOOP (loop_info);
++
++  *new_def_stmt = NULL;
++
++  if (!is_gimple_assign (stmt))
++    return false;
++
++  code = gimple_assign_rhs_code (stmt);
++  if (code != LSHIFT_EXPR && code != RSHIFT_EXPR
++      && code != BIT_IOR_EXPR && code != BIT_XOR_EXPR && code != BIT_AND_EXPR)
++    return false;
++
++  oprnd = gimple_assign_rhs1 (stmt);
++  const_oprnd = gimple_assign_rhs2 (stmt);
++  type = gimple_expr_type (stmt);
++
++  if (TREE_CODE (oprnd) != SSA_NAME
++      || TREE_CODE (const_oprnd) != INTEGER_CST)
++    return false;
++
++  /* If we are in the middle of a sequence, we use DEF from a previous
++     statement.  Otherwise, OPRND has to be a result of type promotion.  */
++  if (*new_type)
++    {
++      half_type = *new_type;
++      oprnd = def;
++    }
++  else
++    {
++      first = true;
++      if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
++          || !gimple_bb (def_stmt)
++          || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
++          || !vinfo_for_stmt (def_stmt))
++        return false;
++    }
++
++  /* Can we perform the operation on a smaller type?  */
++  switch (code)
++    {
++      case BIT_IOR_EXPR:
++      case BIT_XOR_EXPR:
++      case BIT_AND_EXPR:
++        if (!int_fits_type_p (const_oprnd, half_type))
++          {
++            /* HALF_TYPE is not enough.  Try a bigger type if possible.  */
++            if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
++              return false;
++
++            interm_type = build_nonstandard_integer_type (
++                        TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
++            if (!int_fits_type_p (const_oprnd, interm_type))
++              return false;
++          }
++
++        break;
++
++      case LSHIFT_EXPR:
++        /* Try intermediate type - HALF_TYPE is not enough for sure.  */
++        if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
++          return false;
++
++        /* Check that HALF_TYPE size + shift amount <= INTERM_TYPE size.
++          (e.g., if the original value was char, the shift amount is at most 8
++           if we want to use short).  */
++        if (compare_tree_int (const_oprnd, TYPE_PRECISION (half_type)) == 1)
++          return false;
++
++        interm_type = build_nonstandard_integer_type (
++                        TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
++
++        if (!vect_supportable_shift (code, interm_type))
++          return false;
++
++        break;
++
++      case RSHIFT_EXPR:
++        if (vect_supportable_shift (code, half_type))
++          break;
++
++        /* Try intermediate type - HALF_TYPE is not supported.  */
++        if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
++          return false;
++
++        interm_type = build_nonstandard_integer_type (
++                        TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
++
++        if (!vect_supportable_shift (code, interm_type))
++          return false;
++
++        break;
++
++      default:
++        gcc_unreachable ();
++    }
++
++  /* There are four possible cases:
++     1. OPRND is defined by a type promotion (in that case FIRST is TRUE, it's
++        the first statement in the sequence)
++        a. The original, HALF_TYPE, is not enough - we replace the promotion
++           from HALF_TYPE to TYPE with a promotion to INTERM_TYPE.
++        b. HALF_TYPE is sufficient, OPRND is set as the RHS of the original
++           promotion.
++     2. OPRND is defined by a pattern statement we created.
++        a. Its type is not sufficient for the operation, we create a new stmt:
++           a type conversion for OPRND from HALF_TYPE to INTERM_TYPE.  We store
++           this statement in NEW_DEF_STMT, and it is later put in
++           STMT_VINFO_PATTERN_DEF_STMT of the pattern statement for STMT.
++        b. OPRND is good to use in the new statement.  */
++  if (first)
++    {
++      if (interm_type)
++        {
++          /* Replace the original type conversion HALF_TYPE->TYPE with
++             HALF_TYPE->INTERM_TYPE.  */
++          if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
++            {
++              new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
++              /* Check if the already created pattern stmt is what we need.  */
++              if (!is_gimple_assign (new_stmt)
++                  || gimple_assign_rhs_code (new_stmt) != NOP_EXPR
++                  || TREE_TYPE (gimple_assign_lhs (new_stmt)) != interm_type)
++                return false;
++
++              oprnd = gimple_assign_lhs (new_stmt);
++            }
++          else
++            {
++              /* Create NEW_OPRND = (INTERM_TYPE) OPRND.  */
++              oprnd = gimple_assign_rhs1 (def_stmt);
++              tmp = create_tmp_reg (interm_type, NULL);
++              add_referenced_var (tmp);
++              new_oprnd = make_ssa_name (tmp, NULL);
++              new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
++                                                       oprnd, NULL_TREE);
++              SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
++              STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
++              VEC_safe_push (gimple, heap, *stmts, def_stmt);
++              oprnd = new_oprnd;
++            }
++        }
++      else
++        {
++          /* Retrieve the operand before the type promotion.  */
++          oprnd = gimple_assign_rhs1 (def_stmt);
++        }
++    }
++  else
++    {
++      if (interm_type)
++        {
++          /* Create a type conversion HALF_TYPE->INTERM_TYPE.  */
++          tmp = create_tmp_reg (interm_type, NULL);
++          add_referenced_var (tmp);
++          new_oprnd = make_ssa_name (tmp, NULL);
++          new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
++                                                   oprnd, NULL_TREE);
++          SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
++          oprnd = new_oprnd;
++          *new_def_stmt = new_stmt;
++        }
++
++      /* Otherwise, OPRND is already set.  */
++    }
++
++  if (interm_type)
++    *new_type = interm_type;
++  else
++    *new_type = half_type;
++
++  *op0 = oprnd;
++  *op1 = fold_convert (*new_type, const_oprnd);
++
++  return true;
++}
++
++
++/* Try to find a statement or a sequence of statements that can be performed
++   on a smaller type:
++
++     type x_t;
++     TYPE x_T, res0_T, res1_T;
++   loop:
++     S1  x_t = *p;
++     S2  x_T = (TYPE) x_t;
++     S3  res0_T = op (x_T, C0);
++     S4  res1_T = op (res0_T, C1);
++     S5  ... = () res1_T;  - type demotion
++
++   where type 'TYPE' is at least double the size of type 'type', C0 and C1 are
++   constants.
++   Check if S3 and S4 can be done on a smaller type than 'TYPE', it can either
++   be 'type' or some intermediate type.  For now, we expect S5 to be a type
++   demotion operation.  We also check that S3 and S4 have only one use.
++.
++
++*/
++static gimple
++vect_recog_over_widening_pattern (VEC (gimple, heap) **stmts,
++                                  tree *type_in, tree *type_out)
++{
++  gimple stmt = VEC_pop (gimple, *stmts);
++  gimple pattern_stmt = NULL, new_def_stmt, prev_stmt = NULL, use_stmt = NULL;
++  tree op0, op1, vectype = NULL_TREE, lhs, use_lhs, use_type;
++  imm_use_iterator imm_iter;
++  use_operand_p use_p;
++  int nuses = 0;
++  tree var = NULL_TREE, new_type = NULL_TREE, tmp, new_oprnd;
++  bool first;
++  struct loop *loop = (gimple_bb (stmt))->loop_father;
++
++  first = true;
++  while (1)
++    {
++      if (!vinfo_for_stmt (stmt)
++          || STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (stmt)))
++        return NULL;
++
++      new_def_stmt = NULL;
++      if (!vect_operation_fits_smaller_type (stmt, var, &new_type,
++                                             &op0, &op1, &new_def_stmt,
++                                             stmts))
++        {
++          if (first)
++            return NULL;
++          else
++            break;
++        }
++
++      /* STMT can be performed on a smaller type.  Check its uses.  */
++      lhs = gimple_assign_lhs (stmt);
++      nuses = 0;
++      FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
++        {
++          if (is_gimple_debug (USE_STMT (use_p)))
++            continue;
++          use_stmt = USE_STMT (use_p);
++          nuses++;
++        }
++
++      if (nuses != 1 || !is_gimple_assign (use_stmt)
++          || !gimple_bb (use_stmt)
++          || !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
++        return NULL;
++
++      /* Create pattern statement for STMT.  */
++      vectype = get_vectype_for_scalar_type (new_type);
++      if (!vectype)
++        return NULL;
++
++      /* We want to collect all the statements for which we create pattern
++         statetments, except for the case when the last statement in the
++         sequence doesn't have a corresponding pattern statement.  In such
++         case we associate the last pattern statement with the last statement
++         in the sequence.  Therefore, we only add an original statetement to
++         the list if we know that it is not the last.  */
++      if (prev_stmt)
++        VEC_safe_push (gimple, heap, *stmts, prev_stmt);
++
++      var = vect_recog_temp_ssa_var (new_type, NULL);
++      pattern_stmt = gimple_build_assign_with_ops (
++                          gimple_assign_rhs_code (stmt), var, op0, op1);
++      SSA_NAME_DEF_STMT (var) = pattern_stmt;
++      STMT_VINFO_RELATED_STMT (vinfo_for_stmt (stmt)) = pattern_stmt;
++      STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (stmt)) = new_def_stmt;
++
++      if (vect_print_dump_info (REPORT_DETAILS))
++        {
++          fprintf (vect_dump, "created pattern stmt: ");
++          print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
++        }
++
++      prev_stmt = stmt;
++      stmt = use_stmt;
++
++      first = false;
++    }
++
++  /* We got a sequence.  We expect it to end with a type demotion operation.
++     Otherwise, we quit (for now).  There are three possible cases: the
++     conversion is to NEW_TYPE (we don't do anything), the conversion is to
++     a type bigger than NEW_TYPE and/or the signedness of USE_TYPE and
++     NEW_TYPE differs (we create a new conversion statement).  */
++  if (CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (use_stmt)))
++    {
++      use_lhs = gimple_assign_lhs (use_stmt);
++      use_type = TREE_TYPE (use_lhs);
++      /* Support only type promotion or signedess change.  */
++      if (!INTEGRAL_TYPE_P (use_type)
++          || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
++        return NULL;
++
++      if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
++          || TYPE_PRECISION (new_type) != TYPE_PRECISION (use_type))
++        {
++          /* Create NEW_TYPE->USE_TYPE conversion.  */
++          tmp = create_tmp_reg (use_type, NULL);
++          add_referenced_var (tmp);
++          new_oprnd = make_ssa_name (tmp, NULL);
++          pattern_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
++                                                       var, NULL_TREE);
++          SSA_NAME_DEF_STMT (new_oprnd) = pattern_stmt;
++          STMT_VINFO_RELATED_STMT (vinfo_for_stmt (use_stmt)) = pattern_stmt;
++
++          *type_in = get_vectype_for_scalar_type (new_type);
++          *type_out = get_vectype_for_scalar_type (use_type);
++
++          /* We created a pattern statement for the last statement in the
++             sequence, so we don't need to associate it with the pattern
++             statement created for PREV_STMT.  Therefore, we add PREV_STMT
++             to the list in order to mark it later in vect_pattern_recog_1.  */
++          if (prev_stmt)
++            VEC_safe_push (gimple, heap, *stmts, prev_stmt);
++        }
++      else
++        {
++          if (prev_stmt)
++            STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (use_stmt))
++               = STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (prev_stmt));
++
++          *type_in = vectype;
++          *type_out = NULL_TREE;
++        }
++
++      VEC_safe_push (gimple, heap, *stmts, use_stmt);
++    }
++  else
++    /* TODO: support general case, create a conversion to the correct type.  */
++    return NULL;
++
++  /* Pattern detected.  */
++  if (vect_print_dump_info (REPORT_DETAILS))
++    {
++      fprintf (vect_dump, "vect_recog_over_widening_pattern: detected: ");
++      print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
++    }
++
++  return pattern_stmt;
++}
++
++
++/* Mark statements that are involved in a pattern.  */
++
++static inline void
++vect_mark_pattern_stmts (gimple orig_stmt, gimple pattern_stmt,
++                         tree pattern_vectype)
++{
++  stmt_vec_info pattern_stmt_info, def_stmt_info;
++  stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
++  loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (orig_stmt_info);
++  gimple def_stmt;
++
++  set_vinfo_for_stmt (pattern_stmt,
++                      new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
++  gimple_set_bb (pattern_stmt, gimple_bb (orig_stmt));
++  pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
++
++  STMT_VINFO_RELATED_STMT (pattern_stmt_info) = orig_stmt;
++  STMT_VINFO_DEF_TYPE (pattern_stmt_info)
++	= STMT_VINFO_DEF_TYPE (orig_stmt_info);
++  STMT_VINFO_VECTYPE (pattern_stmt_info) = pattern_vectype;
++  STMT_VINFO_IN_PATTERN_P (orig_stmt_info) = true;
++  STMT_VINFO_RELATED_STMT (orig_stmt_info) = pattern_stmt;
++  STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info)
++	= STMT_VINFO_PATTERN_DEF_STMT (orig_stmt_info);
++  if (STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info))
++    {
++      def_stmt = STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info);
++      set_vinfo_for_stmt (def_stmt,
++                          new_stmt_vec_info (def_stmt, loop_vinfo, NULL));
++      gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
++      def_stmt_info = vinfo_for_stmt (def_stmt);
++      STMT_VINFO_RELATED_STMT (def_stmt_info) = orig_stmt;
++      STMT_VINFO_DEF_TYPE (def_stmt_info)
++	= STMT_VINFO_DEF_TYPE (orig_stmt_info);
++      STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
++    }
++}
++
+ /* Function vect_pattern_recog_1
+ 
+    Input:
+@@ -855,7 +1282,6 @@
+ {
+   gimple stmt = gsi_stmt (si), pattern_stmt;
+   stmt_vec_info stmt_info;
+-  stmt_vec_info pattern_stmt_info;
+   loop_vec_info loop_vinfo;
+   tree pattern_vectype;
+   tree type_in, type_out;
+@@ -923,16 +1349,7 @@
+     }
+ 
+   /* Mark the stmts that are involved in the pattern. */
+-  set_vinfo_for_stmt (pattern_stmt,
+-		      new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
+-  gimple_set_bb (pattern_stmt, gimple_bb (stmt));
+-  pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
+-
+-  STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
+-  STMT_VINFO_DEF_TYPE (pattern_stmt_info) = STMT_VINFO_DEF_TYPE (stmt_info);
+-  STMT_VINFO_VECTYPE (pattern_stmt_info) = pattern_vectype;
+-  STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
+-  STMT_VINFO_RELATED_STMT (stmt_info) = pattern_stmt;
++  vect_mark_pattern_stmts (stmt, pattern_stmt, pattern_vectype);
+ 
+   /* Patterns cannot be vectorized using SLP, because they change the order of
+      computation.  */
+@@ -940,9 +1357,9 @@
+     if (next == stmt)
+       VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i); 
+ 
+-  /* In case of widen-mult by a constant, it is possible that an additional
+-     pattern stmt is created and inserted in STMTS_TO_REPLACE.  We create a
+-     stmt_info for it, and mark the relevant statements.  */
++  /* It is possible that additional pattern stmts are created and inserted in
++     STMTS_TO_REPLACE.  We create a stmt_info for each of them, and mark the
++     relevant statements.  */
+   for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
+               && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
+        i++)
+@@ -955,16 +1372,7 @@
+           print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
+         }
+ 
+-      set_vinfo_for_stmt (pattern_stmt,
+-                      new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
+-      gimple_set_bb (pattern_stmt, gimple_bb (stmt));
+-      pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
+-
+-      STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
+-      STMT_VINFO_DEF_TYPE (pattern_stmt_info)
+-        = STMT_VINFO_DEF_TYPE (stmt_info);
+-      STMT_VINFO_VECTYPE (pattern_stmt_info) = STMT_VINFO_VECTYPE (stmt_info);
+-      STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
++      vect_mark_pattern_stmts (stmt, pattern_stmt, NULL_TREE);
+     }
+ 
+   VEC_free (gimple, heap, stmts_to_replace);
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-07-06 12:04:10 +0000
++++ new/gcc/tree-vect-stmts.c	2011-09-05 06:23:37 +0000
+@@ -2246,6 +2246,42 @@
+ }
+ 
+ 
++/* Return TRUE if CODE (a shift operation) is supported for SCALAR_TYPE
++   either as shift by a scalar or by a vector.  */
++
++bool
++vect_supportable_shift (enum tree_code code, tree scalar_type)
++{
++
++  enum machine_mode vec_mode;
++  optab optab;
++  int icode;
++  tree vectype;
++
++  vectype = get_vectype_for_scalar_type (scalar_type);
++  if (!vectype)
++    return false;
++
++  optab = optab_for_tree_code (code, vectype, optab_scalar);
++  if (!optab
++      || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
++    {
++      optab = optab_for_tree_code (code, vectype, optab_vector);
++      if (!optab
++          || (optab_handler (optab, TYPE_MODE (vectype))
++                      == CODE_FOR_nothing))
++        return false;
++    }
++
++  vec_mode = TYPE_MODE (vectype);
++  icode = (int) optab_handler (optab, vec_mode);
++  if (icode == CODE_FOR_nothing)
++    return false;
++
++  return true;
++}
++
++
+ /* Function vectorizable_shift.
+ 
+    Check if STMT performs a shift operation that can be vectorized.
+@@ -4946,7 +4982,7 @@
+   enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info);
+   bool ok;
+   tree scalar_type, vectype;
+-  gimple pattern_stmt;
++  gimple pattern_stmt, pattern_def_stmt;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     {
+@@ -5016,6 +5052,23 @@
+         return false;
+    }
+ 
++  if (is_pattern_stmt_p (stmt_info)
++      && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
++      && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
++          || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
++    {
++      /* Analyze def stmt of STMT if it's a pattern stmt.  */
++      if (vect_print_dump_info (REPORT_DETAILS))
++        {
++          fprintf (vect_dump, "==> examining pattern def statement: ");
++          print_gimple_stmt (vect_dump, pattern_def_stmt, 0, TDF_SLIM);
++        }
++
++      if (!vect_analyze_stmt (pattern_def_stmt, need_to_vectorize, node))
++        return false;
++   }
++
++
+   switch (STMT_VINFO_DEF_TYPE (stmt_info))
+     {
+       case vect_internal_def:
+@@ -5336,6 +5389,7 @@
+   STMT_VINFO_VECTORIZABLE (res) = true;
+   STMT_VINFO_IN_PATTERN_P (res) = false;
+   STMT_VINFO_RELATED_STMT (res) = NULL;
++  STMT_VINFO_PATTERN_DEF_STMT (res) = NULL;
+   STMT_VINFO_DATA_REF (res) = NULL;
+ 
+   STMT_VINFO_DR_BASE_ADDRESS (res) = NULL;
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2011-07-11 11:02:55 +0000
++++ new/gcc/tree-vectorizer.h	2011-09-05 06:23:37 +0000
+@@ -464,6 +464,9 @@
+         pattern).  */
+   gimple related_stmt;
+ 
++  /* Used to keep a def stmt of a pattern stmt if such exists.  */
++  gimple pattern_def_stmt;
++
+   /* List of datarefs that are known to have the same alignment as the dataref
+      of this stmt.  */
+   VEC(dr_p,heap) *same_align_refs;
+@@ -531,6 +534,7 @@
+ 
+ #define STMT_VINFO_IN_PATTERN_P(S)         (S)->in_pattern_p
+ #define STMT_VINFO_RELATED_STMT(S)         (S)->related_stmt
++#define STMT_VINFO_PATTERN_DEF_STMT(S)     (S)->pattern_def_stmt
+ #define STMT_VINFO_SAME_ALIGN_REFS(S)      (S)->same_align_refs
+ #define STMT_VINFO_DEF_TYPE(S)             (S)->def_type
+ #define STMT_VINFO_DR_GROUP_FIRST_DR(S)    (S)->first_dr
+@@ -814,6 +818,7 @@
+ extern void vect_get_load_cost (struct data_reference *, int, bool,
+                                 unsigned int *, unsigned int *);
+ extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
++extern bool vect_supportable_shift (enum tree_code, tree);
+ 
+ /* In tree-vect-data-refs.c.  */
+ extern bool vect_can_force_dr_alignment_p (const_tree, unsigned int);
+@@ -891,7 +896,7 @@
+    Additional pattern recognition functions can (and will) be added
+    in the future.  */
+ typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+-#define NUM_PATTERNS 4
++#define NUM_PATTERNS 5
+ void vect_pattern_recog (loop_vec_info);
+ 
+ /* In tree-vectorizer.c.  */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch
new file mode 100644
index 0000000000..ade96fdd11
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch
@@ -0,0 +1,948 @@
+2011-09-12  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2011-08-30  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (optimal_immediate_sequence_1): Make b1, b2,
+	b3 and b4 unsigned.
+
+	2011-08-30  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_gen_constant): Set can_negate correctly
+	when code is SET.
+
+	2011-08-26  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (struct four_ints): New type.
+	(count_insns_for_constant): Delete function.
+	(find_best_start): Delete function.
+	(optimal_immediate_sequence): New function.
+	(optimal_immediate_sequence_1): New function.
+	(arm_gen_constant): Move constant splitting code to
+	optimal_immediate_sequence.
+	Rewrite constant negation/invertion code.
+
+	gcc/testsuite/
+	* gcc.target/arm/thumb2-replicated-constant1.c: New file.
+	* gcc.target/arm/thumb2-replicated-constant2.c: New file.
+	* gcc.target/arm/thumb2-replicated-constant3.c: New file.
+	* gcc.target/arm/thumb2-replicated-constant4.c: New file.
+
+	2011-08-26  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm-protos.h (const_ok_for_op): Add prototype.
+	* config/arm/arm.c (const_ok_for_op): Add support for addw/subw.
+	Remove prototype. Remove static function type.
+	* config/arm/arm.md (*arm_addsi3): Add addw/subw support.
+	Add arch attribute.
+	* config/arm/constraints.md (Pj, PJ): New constraints.
+
+	2011-04-20  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_gen_constant): Move mowv support ....
+	(const_ok_for_op): ... to here.
+
+	2011-04-20  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_gen_constant): Remove redundant can_invert.
+
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-07-04 14:03:49 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-08-25 13:26:58 +0000
+@@ -46,6 +46,7 @@
+ extern bool arm_small_register_classes_for_mode_p (enum machine_mode);
+ extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);
+ extern int const_ok_for_arm (HOST_WIDE_INT);
++extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
+ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
+ 			       HOST_WIDE_INT, rtx, rtx, int);
+ extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-08-24 17:35:16 +0000
++++ new/gcc/config/arm/arm.c	2011-09-06 12:57:56 +0000
+@@ -63,6 +63,11 @@
+ 
+ void (*arm_lang_output_object_attributes_hook)(void);
+ 
++struct four_ints
++{
++  int i[4];
++};
++
+ /* Forward function declarations.  */
+ static bool arm_needs_doubleword_align (enum machine_mode, const_tree);
+ static int arm_compute_static_chain_stack_bytes (void);
+@@ -81,7 +86,6 @@
+ static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
+ static int thumb_far_jump_used_p (void);
+ static bool thumb_force_lr_save (void);
+-static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
+ static rtx emit_sfm (int, int);
+ static unsigned arm_size_return_regs (void);
+ static bool arm_assemble_integer (rtx, unsigned int, int);
+@@ -129,7 +133,13 @@
+ static int arm_comp_type_attributes (const_tree, const_tree);
+ static void arm_set_default_type_attributes (tree);
+ static int arm_adjust_cost (rtx, rtx, rtx, int);
+-static int count_insns_for_constant (HOST_WIDE_INT, int);
++static int optimal_immediate_sequence (enum rtx_code code,
++				       unsigned HOST_WIDE_INT val,
++				       struct four_ints *return_sequence);
++static int optimal_immediate_sequence_1 (enum rtx_code code,
++					 unsigned HOST_WIDE_INT val,
++					 struct four_ints *return_sequence,
++					 int i);
+ static int arm_get_strip_length (int);
+ static bool arm_function_ok_for_sibcall (tree, tree);
+ static enum machine_mode arm_promote_function_mode (const_tree,
+@@ -2525,7 +2535,7 @@
+ }
+ 
+ /* Return true if I is a valid constant for the operation CODE.  */
+-static int
++int
+ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
+ {
+   if (const_ok_for_arm (i))
+@@ -2533,7 +2543,21 @@
+ 
+   switch (code)
+     {
++    case SET:
++      /* See if we can use movw.  */
++      if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
++	return 1;
++      else
++	return 0;
++
+     case PLUS:
++      /* See if we can use addw or subw.  */
++      if (TARGET_THUMB2
++	  && ((i & 0xfffff000) == 0
++	      || ((-i) & 0xfffff000) == 0))
++	return 1;
++      /* else fall through.  */
++
+     case COMPARE:
+     case EQ:
+     case NE:
+@@ -2649,68 +2673,41 @@
+ 			   1);
+ }
+ 
+-/* Return the number of instructions required to synthesize the given
+-   constant, if we start emitting them from bit-position I.  */
+-static int
+-count_insns_for_constant (HOST_WIDE_INT remainder, int i)
+-{
+-  HOST_WIDE_INT temp1;
+-  int step_size = TARGET_ARM ? 2 : 1;
+-  int num_insns = 0;
+-
+-  gcc_assert (TARGET_ARM || i == 0);
+-
+-  do
+-    {
+-      int end;
+-
+-      if (i <= 0)
+-	i += 32;
+-      if (remainder & (((1 << step_size) - 1) << (i - step_size)))
+-	{
+-	  end = i - 8;
+-	  if (end < 0)
+-	    end += 32;
+-	  temp1 = remainder & ((0x0ff << end)
+-				    | ((i < end) ? (0xff >> (32 - end)) : 0));
+-	  remainder &= ~temp1;
+-	  num_insns++;
+-	  i -= 8 - step_size;
+-	}
+-      i -= step_size;
+-    } while (remainder);
+-  return num_insns;
+-}
+-
+-static int
+-find_best_start (unsigned HOST_WIDE_INT remainder)
++/* Return a sequence of integers, in RETURN_SEQUENCE that fit into
++   ARM/THUMB2 immediates, and add up to VAL.
++   Thr function return value gives the number of insns required.  */
++static int
++optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
++			    struct four_ints *return_sequence)
+ {
+   int best_consecutive_zeros = 0;
+   int i;
+   int best_start = 0;
++  int insns1, insns2;
++  struct four_ints tmp_sequence;
+ 
+   /* If we aren't targetting ARM, the best place to start is always at
+-     the bottom.  */
+-  if (! TARGET_ARM)
+-    return 0;
+-
+-  for (i = 0; i < 32; i += 2)
++     the bottom, otherwise look more closely.  */
++  if (TARGET_ARM)
+     {
+-      int consecutive_zeros = 0;
+-
+-      if (!(remainder & (3 << i)))
++      for (i = 0; i < 32; i += 2)
+ 	{
+-	  while ((i < 32) && !(remainder & (3 << i)))
+-	    {
+-	      consecutive_zeros += 2;
+-	      i += 2;
+-	    }
+-	  if (consecutive_zeros > best_consecutive_zeros)
+-	    {
+-	      best_consecutive_zeros = consecutive_zeros;
+-	      best_start = i - consecutive_zeros;
+-	    }
+-	  i -= 2;
++	  int consecutive_zeros = 0;
++
++	  if (!(val & (3 << i)))
++	    {
++	      while ((i < 32) && !(val & (3 << i)))
++		{
++		  consecutive_zeros += 2;
++		  i += 2;
++		}
++	      if (consecutive_zeros > best_consecutive_zeros)
++		{
++		  best_consecutive_zeros = consecutive_zeros;
++		  best_start = i - consecutive_zeros;
++		}
++	      i -= 2;
++	    }
+ 	}
+     }
+ 
+@@ -2737,13 +2734,161 @@
+      the constant starting from `best_start', and also starting from
+      zero (i.e. with bit 31 first to be output).  If `best_start' doesn't
+      yield a shorter sequence, we may as well use zero.  */
++  insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
+   if (best_start != 0
+-      && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
+-      && (count_insns_for_constant (remainder, 0) <=
+-	  count_insns_for_constant (remainder, best_start)))
+-    best_start = 0;
+-
+-  return best_start;
++      && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
++    {
++      insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
++      if (insns2 <= insns1)
++	{
++	  *return_sequence = tmp_sequence;
++	  insns1 = insns2;
++	}
++    }
++
++  return insns1;
++}
++
++/* As for optimal_immediate_sequence, but starting at bit-position I.  */
++static int
++optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
++			     struct four_ints *return_sequence, int i)
++{
++  int remainder = val & 0xffffffff;
++  int insns = 0;
++
++  /* Try and find a way of doing the job in either two or three
++     instructions.
++     
++     In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
++     location.  We start at position I.  This may be the MSB, or
++     optimial_immediate_sequence may have positioned it at the largest block 
++     of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
++     wrapping around to the top of the word when we drop off the bottom.
++     In the worst case this code should produce no more than four insns.
++
++     In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
++     constants, shifted to any arbitrary location.  We should always start
++     at the MSB.  */
++  do
++    {
++      int end;
++      unsigned int b1, b2, b3, b4;
++      unsigned HOST_WIDE_INT result;
++      int loc;
++
++      gcc_assert (insns < 4);
++
++      if (i <= 0)
++	i += 32;
++
++      /* First, find the next normal 12/8-bit shifted/rotated immediate.  */
++      if (remainder & ((TARGET_ARM ? (3 << (i - 2)) : (1 << (i - 1)))))
++	{
++	  loc = i;
++	  if (i <= 12 && TARGET_THUMB2 && code == PLUS)
++	    /* We can use addw/subw for the last 12 bits.  */
++	    result = remainder;
++	  else
++	    {
++	      /* Use an 8-bit shifted/rotated immediate.  */
++	      end = i - 8;
++	      if (end < 0)
++		end += 32;
++	      result = remainder & ((0x0ff << end)
++				   | ((i < end) ? (0xff >> (32 - end))
++						: 0));
++	      i -= 8;
++	    }
++	}
++      else
++	{
++	  /* Arm allows rotates by a multiple of two. Thumb-2 allows
++	     arbitrary shifts.  */
++	  i -= TARGET_ARM ? 2 : 1;
++	  continue;
++	}
++
++      /* Next, see if we can do a better job with a thumb2 replicated
++	 constant.
++       
++         We do it this way around to catch the cases like 0x01F001E0 where
++	 two 8-bit immediates would work, but a replicated constant would
++	 make it worse.
++       
++         TODO: 16-bit constants that don't clear all the bits, but still win.
++         TODO: Arithmetic splitting for set/add/sub, rather than bitwise.  */
++      if (TARGET_THUMB2)
++	{
++	  b1 = (remainder & 0xff000000) >> 24;
++	  b2 = (remainder & 0x00ff0000) >> 16;
++	  b3 = (remainder & 0x0000ff00) >> 8;
++	  b4 = remainder & 0xff;
++
++	  if (loc > 24)
++	    {
++	      /* The 8-bit immediate already found clears b1 (and maybe b2),
++		 but must leave b3 and b4 alone.  */
++
++	      /* First try to find a 32-bit replicated constant that clears
++		 almost everything.  We can assume that we can't do it in one,
++		 or else we wouldn't be here.  */
++	      unsigned int tmp = b1 & b2 & b3 & b4;
++	      unsigned int tmp2 = tmp + (tmp << 8) + (tmp << 16)
++				  + (tmp << 24);
++	      unsigned int matching_bytes = (tmp == b1) + (tmp == b2)
++					    + (tmp == b3) + (tmp == b4);
++	      if (tmp
++		  && (matching_bytes >= 3
++		      || (matching_bytes == 2
++			  && const_ok_for_op (remainder & ~tmp2, code))))
++		{
++		  /* At least 3 of the bytes match, and the fourth has at 
++		     least as many bits set, or two of the bytes match
++		     and it will only require one more insn to finish.  */
++		  result = tmp2;
++		  i = tmp != b1 ? 32
++		      : tmp != b2 ? 24
++		      : tmp != b3 ? 16
++		      : 8;
++		}
++
++	      /* Second, try to find a 16-bit replicated constant that can
++		 leave three of the bytes clear.  If b2 or b4 is already
++		 zero, then we can.  If the 8-bit from above would not
++		 clear b2 anyway, then we still win.  */
++	      else if (b1 == b3 && (!b2 || !b4
++			       || (remainder & 0x00ff0000 & ~result)))
++		{
++		  result = remainder & 0xff00ff00;
++		  i = 24;
++		}
++	    }
++	  else if (loc > 16)
++	    {
++	      /* The 8-bit immediate already found clears b2 (and maybe b3)
++		 and we don't get here unless b1 is alredy clear, but it will
++		 leave b4 unchanged.  */
++
++	      /* If we can clear b2 and b4 at once, then we win, since the
++		 8-bits couldn't possibly reach that far.  */
++	      if (b2 == b4)
++		{
++		  result = remainder & 0x00ff00ff;
++		  i = 16;
++		}
++	    }
++	}
++
++      return_sequence->i[insns++] = result;
++      remainder &= ~result;
++
++      if (code == SET || code == MINUS)
++	code = PLUS;
++    }
++  while (remainder);
++
++  return insns;
+ }
+ 
+ /* Emit an instruction with the indicated PATTERN.  If COND is
+@@ -2760,7 +2905,6 @@
+ 
+ /* As above, but extra parameter GENERATE which, if clear, suppresses
+    RTL generation.  */
+-/* ??? This needs more work for thumb2.  */
+ 
+ static int
+ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
+@@ -2772,15 +2916,15 @@
+   int final_invert = 0;
+   int can_negate_initial = 0;
+   int i;
+-  int num_bits_set = 0;
+   int set_sign_bit_copies = 0;
+   int clear_sign_bit_copies = 0;
+   int clear_zero_bit_copies = 0;
+   int set_zero_bit_copies = 0;
+-  int insns = 0;
++  int insns = 0, neg_insns, inv_insns;
+   unsigned HOST_WIDE_INT temp1, temp2;
+   unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
+-  int step_size = TARGET_ARM ? 2 : 1;
++  struct four_ints *immediates;
++  struct four_ints pos_immediates, neg_immediates, inv_immediates;
+ 
+   /* Find out which operations are safe for a given CODE.  Also do a quick
+      check for degenerate cases; these can occur when DImode operations
+@@ -2789,7 +2933,6 @@
+     {
+     case SET:
+       can_invert = 1;
+-      can_negate = 1;
+       break;
+ 
+     case PLUS:
+@@ -2817,9 +2960,6 @@
+ 				gen_rtx_SET (VOIDmode, target, source));
+ 	  return 1;
+ 	}
+-
+-      if (TARGET_THUMB2)
+-	can_invert = 1;
+       break;
+ 
+     case AND:
+@@ -2861,6 +3001,7 @@
+ 					     gen_rtx_NOT (mode, source)));
+ 	  return 1;
+ 	}
++      final_invert = 1;
+       break;
+ 
+     case MINUS:
+@@ -2883,7 +3024,6 @@
+ 							    source)));
+ 	  return 1;
+ 	}
+-      can_negate = 1;
+ 
+       break;
+ 
+@@ -2892,9 +3032,7 @@
+     }
+ 
+   /* If we can do it in one insn get out quickly.  */
+-  if (const_ok_for_arm (val)
+-      || (can_negate_initial && const_ok_for_arm (-val))
+-      || (can_invert && const_ok_for_arm (~val)))
++  if (const_ok_for_op (val, code))
+     {
+       if (generate)
+ 	emit_constant_insn (cond,
+@@ -2947,15 +3085,6 @@
+   switch (code)
+     {
+     case SET:
+-      /* See if we can use movw.  */
+-      if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
+-	{
+-	  if (generate)
+-	    emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
+-						   GEN_INT (val)));
+-	  return 1;
+-	}
+-
+       /* See if we can do this by sign_extending a constant that is known
+ 	 to be negative.  This is a good, way of doing it, since the shift
+ 	 may well merge into a subsequent insn.  */
+@@ -3306,121 +3435,97 @@
+       break;
+     }
+ 
+-  for (i = 0; i < 32; i++)
+-    if (remainder & (1 << i))
+-      num_bits_set++;
+-
+-  if ((code == AND)
+-      || (code != IOR && can_invert && num_bits_set > 16))
+-    remainder ^= 0xffffffff;
+-  else if (code == PLUS && num_bits_set > 16)
+-    remainder = (-remainder) & 0xffffffff;
+-
+-  /* For XOR, if more than half the bits are set and there's a sequence
+-     of more than 8 consecutive ones in the pattern then we can XOR by the
+-     inverted constant and then invert the final result; this may save an
+-     instruction and might also lead to the final mvn being merged with
+-     some other operation.  */
+-  else if (code == XOR && num_bits_set > 16
+-	   && (count_insns_for_constant (remainder ^ 0xffffffff,
+-					 find_best_start
+-					 (remainder ^ 0xffffffff))
+-	       < count_insns_for_constant (remainder,
+-					   find_best_start (remainder))))
+-    {
+-      remainder ^= 0xffffffff;
+-      final_invert = 1;
++  /* Calculate what the instruction sequences would be if we generated it
++     normally, negated, or inverted.  */
++  if (code == AND)
++    /* AND cannot be split into multiple insns, so invert and use BIC.  */
++    insns = 99;
++  else
++    insns = optimal_immediate_sequence (code, remainder, &pos_immediates);
++
++  if (can_negate)
++    neg_insns = optimal_immediate_sequence (code, (-remainder) & 0xffffffff,
++					    &neg_immediates);
++  else
++    neg_insns = 99;
++
++  if (can_invert || final_invert)
++    inv_insns = optimal_immediate_sequence (code, remainder ^ 0xffffffff,
++					    &inv_immediates);
++  else
++    inv_insns = 99;
++
++  immediates = &pos_immediates;
++
++  /* Is the negated immediate sequence more efficient?  */
++  if (neg_insns < insns && neg_insns <= inv_insns)
++    {
++      insns = neg_insns;
++      immediates = &neg_immediates;
++    }
++  else
++    can_negate = 0;
++
++  /* Is the inverted immediate sequence more efficient?
++     We must allow for an extra NOT instruction for XOR operations, although
++     there is some chance that the final 'mvn' will get optimized later.  */
++  if ((inv_insns + 1) < insns || (!final_invert && inv_insns < insns))
++    {
++      insns = inv_insns;
++      immediates = &inv_immediates;
+     }
+   else
+     {
+       can_invert = 0;
+-      can_negate = 0;
++      final_invert = 0;
+     }
+ 
+-  /* Now try and find a way of doing the job in either two or three
+-     instructions.
+-     We start by looking for the largest block of zeros that are aligned on
+-     a 2-bit boundary, we then fill up the temps, wrapping around to the
+-     top of the word when we drop off the bottom.
+-     In the worst case this code should produce no more than four insns.
+-     Thumb-2 constants are shifted, not rotated, so the MSB is always the
+-     best place to start.  */
+-
+-  /* ??? Use thumb2 replicated constants when the high and low halfwords are
+-     the same.  */
+-  {
+-    /* Now start emitting the insns.  */
+-    i = find_best_start (remainder);
+-    do
+-      {
+-	int end;
+-
+-	if (i <= 0)
+-	  i += 32;
+-	if (remainder & (3 << (i - 2)))
+-	  {
+-	    end = i - 8;
+-	    if (end < 0)
+-	      end += 32;
+-	    temp1 = remainder & ((0x0ff << end)
+-				 | ((i < end) ? (0xff >> (32 - end)) : 0));
+-	    remainder &= ~temp1;
+-
+-	    if (generate)
+-	      {
+-		rtx new_src, temp1_rtx;
+-
+-		if (code == SET || code == MINUS)
+-		  {
+-		    new_src = (subtargets ? gen_reg_rtx (mode) : target);
+-		    if (can_invert && code != MINUS)
+-		      temp1 = ~temp1;
+-		  }
+-		else
+-		  {
+-		    if ((final_invert || remainder) && subtargets)
+-		      new_src = gen_reg_rtx (mode);
+-		    else
+-		      new_src = target;
+-		    if (can_invert)
+-		      temp1 = ~temp1;
+-		    else if (can_negate)
+-		      temp1 = -temp1;
+-		  }
+-
+-		temp1 = trunc_int_for_mode (temp1, mode);
+-		temp1_rtx = GEN_INT (temp1);
+-
+-		if (code == SET)
+-		  ;
+-		else if (code == MINUS)
+-		  temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
+-		else
+-		  temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
+-
+-		emit_constant_insn (cond,
+-				    gen_rtx_SET (VOIDmode, new_src,
+-						 temp1_rtx));
+-		source = new_src;
+-	      }
+-
+-	    if (code == SET)
+-	      {
+-		can_invert = 0;
+-		code = PLUS;
+-	      }
+-	    else if (code == MINUS)
++  /* Now output the chosen sequence as instructions.  */
++  if (generate)
++    {
++      for (i = 0; i < insns; i++)
++	{
++	  rtx new_src, temp1_rtx;
++
++	  temp1 = immediates->i[i];
++
++	  if (code == SET || code == MINUS)
++	    new_src = (subtargets ? gen_reg_rtx (mode) : target);
++	  else if ((final_invert || i < (insns - 1)) && subtargets)
++	    new_src = gen_reg_rtx (mode);
++	  else
++	    new_src = target;
++
++	  if (can_invert)
++	    temp1 = ~temp1;
++	  else if (can_negate)
++	    temp1 = -temp1;
++
++	  temp1 = trunc_int_for_mode (temp1, mode);
++	  temp1_rtx = GEN_INT (temp1);
++
++	  if (code == SET)
++	    ;
++	  else if (code == MINUS)
++	    temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
++	  else
++	    temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
++
++	  emit_constant_insn (cond,
++			      gen_rtx_SET (VOIDmode, new_src,
++					   temp1_rtx));
++	  source = new_src;
++
++	  if (code == SET)
++	    {
++	      can_negate = can_invert;
++	      can_invert = 0;
+ 	      code = PLUS;
+-
+-	    insns++;
+-	    i -= 8 - step_size;
+-	  }
+-	/* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
+-	   shifts.  */
+-	i -= step_size;
+-      }
+-    while (remainder);
+-  }
++	    }
++	  else if (code == MINUS)
++	    code = PLUS;
++	}
++    }
+ 
+   if (final_invert)
+     {
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-08-25 11:42:09 +0000
++++ new/gcc/config/arm/arm.md	2011-08-25 13:26:58 +0000
+@@ -701,21 +701,24 @@
+ ;;  (plus (reg rN) (reg sp)) into (reg rN).  In this case reload will
+ ;; put the duplicated register first, and not try the commutative version.
+ (define_insn_and_split "*arm_addsi3"
+-  [(set (match_operand:SI          0 "s_register_operand" "=r, k,r,r, k,r")
+-	(plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k,rk")
+-		 (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,L, L,?n")))]
++  [(set (match_operand:SI          0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r")
++	(plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk")
++		 (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]
+   "TARGET_32BIT"
+   "@
+    add%?\\t%0, %1, %2
+    add%?\\t%0, %1, %2
+    add%?\\t%0, %2, %1
+-   sub%?\\t%0, %1, #%n2
+-   sub%?\\t%0, %1, #%n2
++   addw%?\\t%0, %1, %2
++   addw%?\\t%0, %1, %2
++   sub%?\\t%0, %1, #%n2
++   sub%?\\t%0, %1, #%n2
++   subw%?\\t%0, %1, #%n2
++   subw%?\\t%0, %1, #%n2
+    #"
+   "TARGET_32BIT
+    && GET_CODE (operands[2]) == CONST_INT
+-   && !(const_ok_for_arm (INTVAL (operands[2]))
+-        || const_ok_for_arm (-INTVAL (operands[2])))
++   && !const_ok_for_op (INTVAL (operands[2]), PLUS)
+    && (reload_completed || !arm_eliminable_register (operands[1]))"
+   [(clobber (const_int 0))]
+   "
+@@ -724,8 +727,9 @@
+ 		      operands[1], 0);
+   DONE;
+   "
+-  [(set_attr "length" "4,4,4,4,4,16")
+-   (set_attr "predicable" "yes")]
++  [(set_attr "length" "4,4,4,4,4,4,4,4,4,16")
++   (set_attr "predicable" "yes")
++   (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")]
+ )
+ 
+ (define_insn_and_split "*thumb1_addsi3"
+
+=== modified file 'gcc/config/arm/constraints.md'
+--- old/gcc/config/arm/constraints.md	2011-01-03 20:52:22 +0000
++++ new/gcc/config/arm/constraints.md	2011-08-25 13:26:58 +0000
+@@ -31,7 +31,7 @@
+ ;; The following multi-letter normal constraints have been used:
+ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
+ ;; in Thumb-1 state: Pa, Pb, Pc, Pd
+-;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px
++;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
+ 
+ ;; The following memory constraints have been used:
+ ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
+@@ -74,6 +74,18 @@
+ 	   (and (match_code "const_int")
+                 (match_test "(ival & 0xffff0000) == 0")))))
+ 
++(define_constraint "Pj"
++ "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
++ (and (match_code "const_int")
++      (and (match_test "TARGET_THUMB2")
++	   (match_test "(ival & 0xfffff000) == 0"))))
++
++(define_constraint "PJ"
++ "@internal A constant that satisfies the Pj constrant if negated."
++ (and (match_code "const_int")
++      (and (match_test "TARGET_THUMB2")
++	   (match_test "((-ival) & 0xfffff000) == 0"))))
++
+ (define_register_constraint "k" "STACK_REG"
+  "@internal The stack register.")
+ 
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c	2011-08-25 13:31:00 +0000
+@@ -0,0 +1,27 @@
++/* Ensure simple replicated constant immediates work.  */
++/* { dg-options "-mthumb -O2" } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++
++int
++foo1 (int a)
++{
++  return a + 0xfefefefe;
++}
++
++/* { dg-final { scan-assembler "add.*#-16843010" } } */
++
++int
++foo2 (int a)
++{
++  return a - 0xab00ab00;
++}
++
++/* { dg-final { scan-assembler "sub.*#-1426019584" } } */
++
++int
++foo3 (int a)
++{
++  return a & 0x00cd00cd;
++}
++
++/* { dg-final { scan-assembler "and.*#13435085" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c	2011-08-25 13:31:00 +0000
+@@ -0,0 +1,75 @@
++/* Ensure split constants can use replicated patterns.  */
++/* { dg-options "-mthumb -O2" } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++
++int
++foo1 (int a)
++{
++  return a + 0xfe00fe01;
++}
++
++/* { dg-final { scan-assembler "add.*#-33489408" } } */
++/* { dg-final { scan-assembler "add.*#1" } } */
++
++int
++foo2 (int a)
++{
++  return a + 0xdd01dd00;
++}
++
++/* { dg-final { scan-assembler "add.*#-587145984" } } */
++/* { dg-final { scan-assembler "add.*#65536" } } */
++
++int
++foo3 (int a)
++{
++  return a + 0x00443344;
++}
++
++/* { dg-final { scan-assembler "add.*#4456516" } } */
++/* { dg-final { scan-assembler "add.*#13056" } } */
++
++int
++foo4 (int a)
++{
++  return a + 0x77330033;
++}
++
++/* { dg-final { scan-assembler "add.*#1996488704" } } */
++/* { dg-final { scan-assembler "add.*#3342387" } } */
++
++int
++foo5 (int a)
++{
++  return a + 0x11221122;
++}
++
++/* { dg-final { scan-assembler "add.*#285217024" } } */
++/* { dg-final { scan-assembler "add.*#2228258" } } */
++
++int
++foo6 (int a)
++{
++  return a + 0x66666677;
++}
++
++/* { dg-final { scan-assembler "add.*#1717986918" } } */
++/* { dg-final { scan-assembler "add.*#17" } } */
++
++int
++foo7 (int a)
++{
++  return a + 0x99888888;
++}
++
++/* { dg-final { scan-assembler "add.*#-2004318072" } } */
++/* { dg-final { scan-assembler "add.*#285212672" } } */
++
++int
++foo8 (int a)
++{
++  return a + 0xdddddfff;
++}
++
++/* { dg-final { scan-assembler "add.*#-572662307" } } */
++/* { dg-final { scan-assembler "addw.*#546" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c	2011-08-25 13:31:00 +0000
+@@ -0,0 +1,28 @@
++/* Ensure negated/inverted replicated constant immediates work.  */
++/* { dg-options "-mthumb -O2" } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++
++int
++foo1 (int a)
++{
++  return a | 0xffffff00;
++}
++
++/* { dg-final { scan-assembler "orn.*#255" } } */
++
++int
++foo2 (int a)
++{
++  return a & 0xffeeffee;
++}
++
++/* { dg-final { scan-assembler "bic.*#1114129" } } */
++
++int
++foo3 (int a)
++{
++  return a & 0xaaaaaa00;
++}
++
++/* { dg-final { scan-assembler "and.*#-1431655766" } } */
++/* { dg-final { scan-assembler "bic.*#170" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c	2011-08-25 13:31:00 +0000
+@@ -0,0 +1,22 @@
++/* Ensure replicated constants don't make things worse.  */
++/* { dg-options "-mthumb -O2" } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++
++int
++foo1 (int a)
++{
++  /* It might be tempting to use 0x01000100, but it wouldn't help. */
++  return a + 0x01f001e0;
++}
++
++/* { dg-final { scan-assembler "add.*#32505856" } } */
++/* { dg-final { scan-assembler "add.*#480" } } */
++
++int
++foo2 (int a)
++{
++  return a + 0x0f100e10;
++}
++
++/* { dg-final { scan-assembler "add.*#252706816" } } */
++/* { dg-final { scan-assembler "add.*#3600" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch
new file mode 100644
index 0000000000..5b36959b6b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch
@@ -0,0 +1,201 @@
+2011-09-12  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	PR target/49030
+	* config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
+	* config/arm/arm.c (maybe_get_arm_condition_code): New function,
+	reusing the old code from get_arm_condition_code.  Return ARM_NV
+	for invalid comparison codes.
+	(get_arm_condition_code): Redefine in terms of
+	maybe_get_arm_condition_code.
+	* config/arm/predicates.md (arm_comparison_operator): Use
+	maybe_get_arm_condition_code.
+
+	gcc/testsuite/
+	PR target/49030
+	* gcc.dg/torture/pr49030.c: New test.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-08-25 13:26:58 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-09-12 11:03:11 +0000
+@@ -179,6 +179,7 @@
+ #endif
+ extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
+ #ifdef RTX_CODE
++extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
+ extern void thumb1_final_prescan_insn (rtx);
+ extern void thumb2_final_prescan_insn (rtx);
+ extern const char *thumb_load_double_from_address (rtx *);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-09-06 12:57:56 +0000
++++ new/gcc/config/arm/arm.c	2011-09-12 11:03:11 +0000
+@@ -17494,10 +17494,10 @@
+    decremented/zeroed by arm_asm_output_opcode as the insns are output.  */
+ 
+ /* Returns the index of the ARM condition code string in
+-   `arm_condition_codes'.  COMPARISON should be an rtx like
+-   `(eq (...) (...))'.  */
+-static enum arm_cond_code
+-get_arm_condition_code (rtx comparison)
++   `arm_condition_codes', or ARM_NV if the comparison is invalid.
++   COMPARISON should be an rtx like `(eq (...) (...))'.  */
++enum arm_cond_code
++maybe_get_arm_condition_code (rtx comparison)
+ {
+   enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
+   enum arm_cond_code code;
+@@ -17521,11 +17521,11 @@
+     case CC_DLTUmode: code = ARM_CC;
+ 
+     dominance:
+-      gcc_assert (comp_code == EQ || comp_code == NE);
+-
+       if (comp_code == EQ)
+ 	return ARM_INVERSE_CONDITION_CODE (code);
+-      return code;
++      if (comp_code == NE)
++	return code;
++      return ARM_NV;
+ 
+     case CC_NOOVmode:
+       switch (comp_code)
+@@ -17534,7 +17534,7 @@
+ 	case EQ: return ARM_EQ;
+ 	case GE: return ARM_PL;
+ 	case LT: return ARM_MI;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Zmode:
+@@ -17542,7 +17542,7 @@
+ 	{
+ 	case NE: return ARM_NE;
+ 	case EQ: return ARM_EQ;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Nmode:
+@@ -17550,7 +17550,7 @@
+ 	{
+ 	case NE: return ARM_MI;
+ 	case EQ: return ARM_PL;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CCFPEmode:
+@@ -17575,7 +17575,7 @@
+ 	  /* UNEQ and LTGT do not have a representation.  */
+ 	case UNEQ: /* Fall through.  */
+ 	case LTGT: /* Fall through.  */
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_SWPmode:
+@@ -17591,7 +17591,7 @@
+ 	case GTU: return ARM_CC;
+ 	case LEU: return ARM_CS;
+ 	case LTU: return ARM_HI;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Cmode:
+@@ -17599,7 +17599,7 @@
+ 	{
+ 	case LTU: return ARM_CS;
+ 	case GEU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_CZmode:
+@@ -17611,7 +17611,7 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_NCVmode:
+@@ -17621,7 +17621,7 @@
+ 	case LT: return ARM_LT;
+ 	case GEU: return ARM_CS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CCmode:
+@@ -17637,13 +17637,22 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     default: gcc_unreachable ();
+     }
+ }
+ 
++/* Like maybe_get_arm_condition_code, but never return ARM_NV.  */
++static enum arm_cond_code
++get_arm_condition_code (rtx comparison)
++{
++  enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
++  gcc_assert (code != ARM_NV);
++  return code;
++}
++
+ /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
+    instructions.  */
+ void
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-08-13 08:40:36 +0000
++++ new/gcc/config/arm/predicates.md	2011-09-05 09:40:19 +0000
+@@ -242,10 +242,9 @@
+ ;; True for integer comparisons and, if FP is active, for comparisons
+ ;; other than LTGT or UNEQ.
+ (define_special_predicate "arm_comparison_operator"
+-  (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
+-       (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
+-			 && (TARGET_FPA || TARGET_VFP)")
+-            (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
++  (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
++		    unordered,ordered,unlt,unle,unge,ungt")
++       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
+ 
+ (define_special_predicate "lt_ge_comparison_operator"
+   (match_code "lt,ge"))
+
+=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49030.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49030.c	2011-09-05 09:40:19 +0000
+@@ -0,0 +1,19 @@
++void
++sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
++		       unsigned long dst_skip)
++{
++  long long y;
++  while (nsamples--)
++    {
++      y = (long long) (*src * 8388608.0f) << 8;
++      if (y > 2147483647) {
++	*(int *) dst = 2147483647;
++      } else if (y < -2147483647 - 1) {
++	*(int *) dst = -2147483647 - 1;
++      } else {
++	*(int *) dst = (int) y;
++      }
++      dst += dst_skip;
++      src++;
++    }
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch
new file mode 100644
index 0000000000..09d0767914
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch
@@ -0,0 +1,38 @@
+2011-09-01  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/predicates.md (shift_amount_operand): Ensure shift
+	amount is positive.
+
+	gcc/testsuite/
+	* gcc.dg/pr50193-1.c: New file.
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-09-05 09:40:19 +0000
++++ new/gcc/config/arm/predicates.md	2011-09-12 11:24:34 +0000
+@@ -132,7 +132,8 @@
+ (define_predicate "shift_amount_operand"
+   (ior (and (match_test "TARGET_ARM")
+ 	    (match_operand 0 "s_register_operand"))
+-       (match_operand 0 "const_int_operand")))
++       (and (match_operand 0 "const_int_operand")
++	    (match_test "INTVAL (op) > 0"))))
+ 
+ (define_predicate "arm_add_operand"
+   (ior (match_operand 0 "arm_rhs_operand")
+
+=== added file 'gcc/testsuite/gcc.dg/pr50193-1.c'
+--- old/gcc/testsuite/gcc.dg/pr50193-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr50193-1.c	2011-09-01 12:22:14 +0000
+@@ -0,0 +1,10 @@
++/* PR 50193: ARM: ICE on a | (b << negative-constant) */
++/* Ensure that the compiler doesn't ICE.  */
++
++/* { dg-options "-O2" } */
++
++int
++foo(int a, int b)
++{
++  return a | (b << -3); /* { dg-warning "left shift count is negative" } */
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch
new file mode 100644
index 0000000000..5dec32fa71
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch
@@ -0,0 +1,47 @@
+2011-09-12  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2011-09-08  Andrew Stubbs  <ams@codesourcery.com>
+
+	PR tree-optimization/50318
+
+	gcc/
+	* tree-ssa-math-opts.c (convert_plusminus_to_widen): Correct
+	typo in use of mult_rhs1 and mult_rhs2.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr50318-1.c: New file.
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr50318-1.c'
+--- old/gcc/testsuite/gcc.target/arm/pr50318-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr50318-1.c	2011-09-08 20:11:43 +0000
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++/* { dg-require-effective-target arm_dsp } */
++
++long long test (unsigned int sec, unsigned long long nsecs)
++{
++   return (long long)(long)sec * 1000000000L + (long long)(unsigned
++   long)nsecs;
++}
++
++/* { dg-final { scan-assembler "umlal" } } */
+
+=== modified file 'gcc/tree-ssa-math-opts.c'
+--- old/gcc/tree-ssa-math-opts.c	2011-08-09 10:26:48 +0000
++++ new/gcc/tree-ssa-math-opts.c	2011-09-08 20:11:43 +0000
+@@ -1699,9 +1699,9 @@
+ 
+   /* Handle constants.  */
+   if (TREE_CODE (mult_rhs1) == INTEGER_CST)
+-    rhs1 = fold_convert (type1, mult_rhs1);
++    mult_rhs1 = fold_convert (type1, mult_rhs1);
+   if (TREE_CODE (mult_rhs2) == INTEGER_CST)
+-    rhs2 = fold_convert (type2, mult_rhs2);
++    mult_rhs2 = fold_convert (type2, mult_rhs2);
+ 
+   gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, mult_rhs1, mult_rhs2,
+ 				    add_rhs);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch
new file mode 100644
index 0000000000..2b96854c95
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch
@@ -0,0 +1,92 @@
+2011-09-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/testsuite/
+	* gcc.target/arm/pr50099.c: Fix testcase from previous commit.
+
+2011-09-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	LP:838994
+	gcc/
+	Backport from mainline.
+
+        2011-09-06  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+        PR target/50099
+	* config/arm/iterators.md (qhs_zextenddi_cstr): New.
+	(qhs_zextenddi_op): New.
+	* config/arm/arm.md ("zero_extend<mode>di2"): Use them.
+	* config/arm/predicates.md ("arm_extendqisi_mem_op"):
+	Distinguish between ARM and Thumb2 states.
+
+	gcc/testsuite/
+	* gcc.target/arm/pr50099.c: New test.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-08-25 13:26:58 +0000
++++ new/gcc/config/arm/arm.md	2011-09-12 12:32:29 +0000
+@@ -4136,8 +4136,8 @@
+ 
+ (define_insn "zero_extend<mode>di2"
+   [(set (match_operand:DI 0 "s_register_operand" "=r")
+-        (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
+-					    "<qhs_extenddi_cstr>")))]
++        (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
++					    "<qhs_zextenddi_cstr>")))]
+   "TARGET_32BIT <qhs_zextenddi_cond>"
+   "#"
+   [(set_attr "length" "8")
+
+=== modified file 'gcc/config/arm/iterators.md'
+--- old/gcc/config/arm/iterators.md	2011-05-03 15:14:56 +0000
++++ new/gcc/config/arm/iterators.md	2011-09-06 14:29:24 +0000
+@@ -379,10 +379,14 @@
+ (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
+ (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
+ 				      (QI "&& arm_arch6")])
++(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
++				   (HI "nonimmediate_operand")
++				   (QI "nonimmediate_operand")])
+ (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+ 				   (HI "nonimmediate_operand")
+-				   (QI "nonimmediate_operand")])
+-(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
++				   (QI "arm_reg_or_extendqisi_mem_op")])
++(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
++(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
+ 
+ ;;----------------------------------------------------------------------------
+ ;; Code attributes
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-09-12 11:24:34 +0000
++++ new/gcc/config/arm/predicates.md	2011-09-12 12:32:29 +0000
+@@ -289,8 +289,11 @@
+ 
+ (define_special_predicate "arm_extendqisi_mem_op"
+   (and (match_operand 0 "memory_operand")
+-       (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
+-						    SIGN_EXTEND, 0)")))
++       (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
++                                                                 XEXP (op, 0),
++						                 SIGN_EXTEND,
++								 0)
++                               : memory_address_p (QImode, XEXP (op, 0))")))
+ 
+ (define_special_predicate "arm_reg_or_extendqisi_mem_op"
+   (ior (match_operand 0 "arm_extendqisi_mem_op")
+
+=== added file 'gcc/testsuite/gcc.target/arm/pr50099.c'
+--- old/gcc/testsuite/gcc.target/arm/pr50099.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/pr50099.c	2011-09-09 16:42:45 +0000
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++long long foo (signed char * arg)
++{
++  long long temp_1;
++
++  temp_1 = arg[256]; 
++  return temp_1;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch
new file mode 100644
index 0000000000..9474030f57
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch
@@ -0,0 +1,767 @@
+2011-08-26  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from FSF mainline:
+        2011-04-06  Wei Guozhi  <carrot@google.com>
+
+        PR target/47855
+	gcc/
+        * config/arm/arm.md (arm_cmpsi_insn): Compute attr "length".
+        (arm_cond_branch): Likewise.
+        (arm_cond_branch_reversed): Likewise.
+        (arm_jump): Likewise.
+        (push_multi): Likewise.
+        * config/arm/constraints.md (Py): New constraint.
+
+	2011-04-08  Wei Guozhi  <carrot@google.com>
+
+	PR target/47855
+	* config/arm/arm-protos.h (arm_attr_length_push_multi): New prototype.
+	* config/arm/arm.c (arm_attr_length_push_multi): New function.
+	* config/arm/arm.md (*push_multi): Change the length computation to
+	call a C function.
+
+2011-08-26  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from FSF mainline:
+
+        2011-08-18  Jiangning Liu  <jiangning.liu@arm.com>
+
+	gcc/
+	* config/arm/arm.md (*ior_scc_scc): Enable for Thumb2 as well.
+	(*ior_scc_scc_cmp): Likewise
+	(*and_scc_scc): Likewise.
+	(*and_scc_scc_cmp): Likewise.
+	(*and_scc_scc_nodom): Likewise.
+	(*cmp_ite0, *cmp_ite1, *cmp_and, *cmp_ior): Handle Thumb2.
+
+	gcc/testsuite
+	* gcc.target/arm/thumb2-cond-cmp-1.c: New. Make sure conditional
+	compare can be generated.
+	* gcc.target/arm/thumb2-cond-cmp-2.c: Likewise.
+	* gcc.target/arm/thumb2-cond-cmp-3.c: Likewise.
+	* gcc.target/arm/thumb2-cond-cmp-4.c: Likewise.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-09-12 11:03:11 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-09-12 14:14:00 +0000
+@@ -156,6 +156,7 @@
+ extern const char *arm_output_memory_barrier (rtx *);
+ extern const char *arm_output_sync_insn (rtx, rtx *);
+ extern unsigned int arm_sync_loop_insns (rtx , rtx *);
++extern int arm_attr_length_push_multi(rtx, rtx);
+ 
+ #if defined TREE_CODE
+ extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-09-12 11:03:11 +0000
++++ new/gcc/config/arm/arm.c	2011-09-12 14:14:00 +0000
+@@ -24391,4 +24391,30 @@
+     return NO_REGS;
+ }
+ 
++/* Compute the atrribute "length" of insn "*push_multi".
++   So this function MUST be kept in sync with that insn pattern.  */
++int
++arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
++{
++  int i, regno, hi_reg;
++  int num_saves = XVECLEN (parallel_op, 0);
++
++  /* ARM mode.  */
++  if (TARGET_ARM)
++    return 4;
++
++  /* Thumb2 mode.  */
++  regno = REGNO (first_op);
++  hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
++  for (i = 1; i < num_saves && !hi_reg; i++)
++    {
++      regno = REGNO (XEXP (XVECEXP (parallel_op, 0, i), 0));
++      hi_reg |= (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
++    }
++
++  if (!hi_reg)
++    return 2;
++  return 4;
++}
++
+ #include "gt-arm.h"
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-09-12 12:32:29 +0000
++++ new/gcc/config/arm/arm.md	2011-09-12 14:14:00 +0000
+@@ -48,6 +48,15 @@
+    (DOM_CC_X_OR_Y   2)
+   ]
+ )
++;; conditional compare combination
++(define_constants
++  [(CMP_CMP 0)
++   (CMN_CMP 1)
++   (CMP_CMN 2)
++   (CMN_CMN 3)
++   (NUM_OF_COND_CMP 4)
++  ]
++)
+ 
+ ;; UNSPEC Usage:
+ ;; Note: sin and cos are no-longer used.
+@@ -7198,13 +7207,17 @@
+ 
+ (define_insn "*arm_cmpsi_insn"
+   [(set (reg:CC CC_REGNUM)
+-	(compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
+-		    (match_operand:SI 1 "arm_add_operand"    "rI,L")))]
++	(compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r")
++		    (match_operand:SI 1 "arm_add_operand"    "Py,r,rI,L")))]
+   "TARGET_32BIT"
+   "@
+    cmp%?\\t%0, %1
++   cmp%?\\t%0, %1
++   cmp%?\\t%0, %1
+    cmn%?\\t%0, #%n1"
+-  [(set_attr "conds" "set")]
++  [(set_attr "conds" "set")
++   (set_attr "arch" "t2,t2,any,any")
++   (set_attr "length" "2,2,4,4")]
+ )
+ 
+ (define_insn "*cmpsi_shiftsi"
+@@ -7375,7 +7388,14 @@
+   return \"b%d1\\t%l0\";
+   "
+   [(set_attr "conds" "use")
+-   (set_attr "type" "branch")]
++   (set_attr "type" "branch")
++   (set (attr "length")
++	(if_then_else
++	   (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
++		(and (ge (minus (match_dup 0) (pc)) (const_int -250))
++		     (le (minus (match_dup 0) (pc)) (const_int 256))))
++	   (const_int 2)
++	   (const_int 4)))]
+ )
+ 
+ (define_insn "*arm_cond_branch_reversed"
+@@ -7394,7 +7414,14 @@
+   return \"b%D1\\t%l0\";
+   "
+   [(set_attr "conds" "use")
+-   (set_attr "type" "branch")]
++   (set_attr "type" "branch")
++   (set (attr "length")
++	(if_then_else
++	   (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
++		(and (ge (minus (match_dup 0) (pc)) (const_int -250))
++		     (le (minus (match_dup 0) (pc)) (const_int 256))))
++	   (const_int 2)
++	   (const_int 4)))]
+ )
+ 
+ 
+@@ -7846,7 +7873,14 @@
+     return \"b%?\\t%l0\";
+   }
+   "
+-  [(set_attr "predicable" "yes")]
++  [(set_attr "predicable" "yes")
++   (set (attr "length")
++	(if_then_else
++	   (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
++		(and (ge (minus (match_dup 0) (pc)) (const_int -2044))
++		     (le (minus (match_dup 0) (pc)) (const_int 2048))))
++	   (const_int 2)
++	   (const_int 4)))]
+ )
+ 
+ (define_insn "*thumb_jump"
+@@ -8931,40 +8965,85 @@
+    (set_attr "length" "8,12")]
+ )
+ 
+-;; ??? Is it worth using these conditional patterns in Thumb-2 mode?
+ (define_insn "*cmp_ite0"
+   [(set (match_operand 6 "dominant_cc_register" "")
+ 	(compare
+ 	 (if_then_else:SI
+ 	  (match_operator 4 "arm_comparison_operator"
+-	   [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
++	   [(match_operand:SI 0 "s_register_operand"
++	        "l,l,l,r,r,r,r,r,r")
++	    (match_operand:SI 1 "arm_add_operand"
++	        "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
+ 	  (match_operator:SI 5 "arm_comparison_operator"
+-	   [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])
++	   [(match_operand:SI 2 "s_register_operand"
++	        "l,r,r,l,l,r,r,r,r")
++	    (match_operand:SI 3 "arm_add_operand"
++	        "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
+ 	  (const_int 0))
+ 	 (const_int 0)))]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "*
+   {
+-    static const char * const opcodes[4][2] =
+-    {
+-      {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\",
+-       \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"},
+-      {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\",
+-       \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"},
+-      {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\",
+-       \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"},
+-      {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\",
+-       \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"}
+-    };
++    static const char * const cmp1[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp%d5\\t%0, %1\",
++       \"cmp%d4\\t%2, %3\"},
++      {\"cmn%d5\\t%0, #%n1\",
++       \"cmp%d4\\t%2, %3\"},
++      {\"cmp%d5\\t%0, %1\",
++       \"cmn%d4\\t%2, #%n3\"},
++      {\"cmn%d5\\t%0, #%n1\",
++       \"cmn%d4\\t%2, #%n3\"}
++    };
++    static const char * const cmp2[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp\\t%2, %3\",
++       \"cmp\\t%0, %1\"},
++      {\"cmp\\t%2, %3\",
++       \"cmn\\t%0, #%n1\"},
++      {\"cmn\\t%2, #%n3\",
++       \"cmp\\t%0, %1\"},
++      {\"cmn\\t%2, #%n3\",
++       \"cmn\\t%0, #%n1\"}
++    };
++    static const char * const ite[2] =
++    {
++      \"it\\t%d5\",
++      \"it\\t%d4\"
++    };
++    static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
++                                   CMP_CMP, CMN_CMP, CMP_CMP,
++                                   CMN_CMP, CMP_CMN, CMN_CMN};
+     int swap =
+       comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
+ 
+-    return opcodes[which_alternative][swap];
++    output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
++    if (TARGET_THUMB2) {
++      output_asm_insn (ite[swap], operands);
++    }
++    output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
++    return \"\";
+   }"
+   [(set_attr "conds" "set")
+-   (set_attr "length" "8")]
++   (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
++   (set_attr_alternative "length"
++      [(const_int 6)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))])]
+ )
+ 
+ (define_insn "*cmp_ite1"
+@@ -8972,35 +9051,81 @@
+ 	(compare
+ 	 (if_then_else:SI
+ 	  (match_operator 4 "arm_comparison_operator"
+-	   [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
++	   [(match_operand:SI 0 "s_register_operand"
++	        "l,l,l,r,r,r,r,r,r")
++	    (match_operand:SI 1 "arm_add_operand"
++	        "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
+ 	  (match_operator:SI 5 "arm_comparison_operator"
+-	   [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])
++	   [(match_operand:SI 2 "s_register_operand"
++	        "l,r,r,l,l,r,r,r,r")
++	    (match_operand:SI 3 "arm_add_operand"
++	        "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
+ 	  (const_int 1))
+ 	 (const_int 0)))]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "*
+   {
+-    static const char * const opcodes[4][2] =
+-    {
+-      {\"cmp\\t%0, %1\;cmp%d4\\t%2, %3\",
+-       \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"},
+-      {\"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\",
+-       \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"},
+-      {\"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\",
+-       \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"},
+-      {\"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\",
+-       \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"}
+-    };
++    static const char * const cmp1[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp\\t%0, %1\",
++       \"cmp\\t%2, %3\"},
++      {\"cmn\\t%0, #%n1\",
++       \"cmp\\t%2, %3\"},
++      {\"cmp\\t%0, %1\",
++       \"cmn\\t%2, #%n3\"},
++      {\"cmn\\t%0, #%n1\",
++       \"cmn\\t%2, #%n3\"}
++    };
++    static const char * const cmp2[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp%d4\\t%2, %3\",
++       \"cmp%D5\\t%0, %1\"},
++      {\"cmp%d4\\t%2, %3\",
++       \"cmn%D5\\t%0, #%n1\"},
++      {\"cmn%d4\\t%2, #%n3\",
++       \"cmp%D5\\t%0, %1\"},
++      {\"cmn%d4\\t%2, #%n3\",
++       \"cmn%D5\\t%0, #%n1\"}
++    };
++    static const char * const ite[2] =
++    {
++      \"it\\t%d4\",
++      \"it\\t%D5\"
++    };
++    static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
++                                   CMP_CMP, CMN_CMP, CMP_CMP,
++                                   CMN_CMP, CMP_CMN, CMN_CMN};
+     int swap =
+       comparison_dominates_p (GET_CODE (operands[5]),
+ 			      reverse_condition (GET_CODE (operands[4])));
+ 
+-    return opcodes[which_alternative][swap];
++    output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
++    if (TARGET_THUMB2) {
++      output_asm_insn (ite[swap], operands);
++    }
++    output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
++    return \"\";
+   }"
+   [(set_attr "conds" "set")
+-   (set_attr "length" "8")]
++   (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
++   (set_attr_alternative "length"
++      [(const_int 6)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))])]
+ )
+ 
+ (define_insn "*cmp_and"
+@@ -9008,34 +9133,80 @@
+ 	(compare
+ 	 (and:SI
+ 	  (match_operator 4 "arm_comparison_operator"
+-	   [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
++	   [(match_operand:SI 0 "s_register_operand" 
++	        "l,l,l,r,r,r,r,r,r")
++	    (match_operand:SI 1 "arm_add_operand" 
++	        "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
+ 	  (match_operator:SI 5 "arm_comparison_operator"
+-	   [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]))
++	   [(match_operand:SI 2 "s_register_operand" 
++	        "l,r,r,l,l,r,r,r,r")
++	    (match_operand:SI 3 "arm_add_operand" 
++	        "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
+ 	 (const_int 0)))]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "*
+   {
+-    static const char *const opcodes[4][2] =
+-    {
+-      {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\",
+-       \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"},
+-      {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\",
+-       \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"},
+-      {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\",
+-       \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"},
+-      {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\",
+-       \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"}
+-    };
++    static const char *const cmp1[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp%d5\\t%0, %1\",
++       \"cmp%d4\\t%2, %3\"},
++      {\"cmn%d5\\t%0, #%n1\",
++       \"cmp%d4\\t%2, %3\"},
++      {\"cmp%d5\\t%0, %1\",
++       \"cmn%d4\\t%2, #%n3\"},
++      {\"cmn%d5\\t%0, #%n1\",
++       \"cmn%d4\\t%2, #%n3\"}
++    };
++    static const char *const cmp2[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp\\t%2, %3\",
++       \"cmp\\t%0, %1\"},
++      {\"cmp\\t%2, %3\",
++       \"cmn\\t%0, #%n1\"},
++      {\"cmn\\t%2, #%n3\",
++       \"cmp\\t%0, %1\"},
++      {\"cmn\\t%2, #%n3\",
++       \"cmn\\t%0, #%n1\"}
++    };
++    static const char *const ite[2] =
++    {
++      \"it\\t%d5\",
++      \"it\\t%d4\"
++    };
++    static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
++                                   CMP_CMP, CMN_CMP, CMP_CMP,
++                                   CMN_CMP, CMP_CMN, CMN_CMN};
+     int swap =
+       comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
+ 
+-    return opcodes[which_alternative][swap];
++    output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
++    if (TARGET_THUMB2) {
++      output_asm_insn (ite[swap], operands);
++    }
++    output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
++    return \"\";
+   }"
+   [(set_attr "conds" "set")
+    (set_attr "predicable" "no")
+-   (set_attr "length" "8")]
++   (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
++   (set_attr_alternative "length"
++      [(const_int 6)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))])]
+ )
+ 
+ (define_insn "*cmp_ior"
+@@ -9043,34 +9214,80 @@
+ 	(compare
+ 	 (ior:SI
+ 	  (match_operator 4 "arm_comparison_operator"
+-	   [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
++	   [(match_operand:SI 0 "s_register_operand"
++	        "l,l,l,r,r,r,r,r,r")
++	    (match_operand:SI 1 "arm_add_operand"
++	        "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
+ 	  (match_operator:SI 5 "arm_comparison_operator"
+-	   [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
+-	    (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]))
++	   [(match_operand:SI 2 "s_register_operand"
++	        "l,r,r,l,l,r,r,r,r")
++	    (match_operand:SI 3 "arm_add_operand"
++	        "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
+ 	 (const_int 0)))]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "*
+-{
+-  static const char *const opcodes[4][2] =
+   {
+-    {\"cmp\\t%0, %1\;cmp%D4\\t%2, %3\",
+-     \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"},
+-    {\"cmn\\t%0, #%n1\;cmp%D4\\t%2, %3\",
+-     \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"},
+-    {\"cmp\\t%0, %1\;cmn%D4\\t%2, #%n3\",
+-     \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"},
+-    {\"cmn\\t%0, #%n1\;cmn%D4\\t%2, #%n3\",
+-     \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"}
+-  };
+-  int swap =
+-    comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
++    static const char *const cmp1[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp\\t%0, %1\",
++       \"cmp\\t%2, %3\"},
++      {\"cmn\\t%0, #%n1\",
++       \"cmp\\t%2, %3\"},
++      {\"cmp\\t%0, %1\",
++       \"cmn\\t%2, #%n3\"},
++      {\"cmn\\t%0, #%n1\",
++       \"cmn\\t%2, #%n3\"}
++    };
++    static const char *const cmp2[NUM_OF_COND_CMP][2] =
++    {
++      {\"cmp%D4\\t%2, %3\",
++       \"cmp%D5\\t%0, %1\"},
++      {\"cmp%D4\\t%2, %3\",
++       \"cmn%D5\\t%0, #%n1\"},
++      {\"cmn%D4\\t%2, #%n3\",
++       \"cmp%D5\\t%0, %1\"},
++      {\"cmn%D4\\t%2, #%n3\",
++       \"cmn%D5\\t%0, #%n1\"}
++    };
++    static const char *const ite[2] =
++    {
++      \"it\\t%D4\",
++      \"it\\t%D5\"
++    };
++    static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
++                                   CMP_CMP, CMN_CMP, CMP_CMP,
++                                   CMN_CMP, CMP_CMN, CMN_CMN};
++    int swap =
++      comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
+ 
+-  return opcodes[which_alternative][swap];
+-}
+-"
++    output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
++    if (TARGET_THUMB2) {
++      output_asm_insn (ite[swap], operands);
++    }
++    output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
++    return \"\";
++  }
++  "
+   [(set_attr "conds" "set")
+-   (set_attr "length" "8")]
++   (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
++   (set_attr_alternative "length"
++      [(const_int 6)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (const_int 8)
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))
++       (if_then_else (eq_attr "is_thumb" "no")
++           (const_int 8)
++           (const_int 10))])]
+ )
+ 
+ (define_insn_and_split "*ior_scc_scc"
+@@ -9082,11 +9299,11 @@
+ 		 [(match_operand:SI 4 "s_register_operand" "r")
+ 		  (match_operand:SI 5 "arm_add_operand" "rIL")])))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM
++  "TARGET_32BIT
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
+        != CCmode)"
+   "#"
+-  "TARGET_ARM && reload_completed"
++  "TARGET_32BIT && reload_completed"
+   [(set (match_dup 7)
+ 	(compare
+ 	 (ior:SI
+@@ -9115,9 +9332,9 @@
+    (set (match_operand:SI 7 "s_register_operand" "=r")
+ 	(ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
+ 		(match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "#"
+-  "TARGET_ARM && reload_completed"
++  "TARGET_32BIT && reload_completed"
+   [(set (match_dup 0)
+ 	(compare
+ 	 (ior:SI
+@@ -9138,11 +9355,11 @@
+ 		 [(match_operand:SI 4 "s_register_operand" "r")
+ 		  (match_operand:SI 5 "arm_add_operand" "rIL")])))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM
++  "TARGET_32BIT
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+        != CCmode)"
+   "#"
+-  "TARGET_ARM && reload_completed
++  "TARGET_32BIT && reload_completed
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+        != CCmode)"
+   [(set (match_dup 7)
+@@ -9173,9 +9390,9 @@
+    (set (match_operand:SI 7 "s_register_operand" "=r")
+ 	(and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
+ 		(match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
+-  "TARGET_ARM"
++  "TARGET_32BIT"
+   "#"
+-  "TARGET_ARM && reload_completed"
++  "TARGET_32BIT && reload_completed"
+   [(set (match_dup 0)
+ 	(compare
+ 	 (and:SI
+@@ -9200,11 +9417,11 @@
+ 		 [(match_operand:SI 4 "s_register_operand" "r,r,r")
+ 		  (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM
++  "TARGET_32BIT
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+        == CCmode)"
+   "#"
+-  "TARGET_ARM && reload_completed"
++  "TARGET_32BIT && reload_completed"
+   [(parallel [(set (match_dup 0)
+ 		   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
+ 	      (clobber (reg:CC CC_REGNUM))])
+@@ -10314,6 +10531,8 @@
+ ;; Push multiple registers to the stack.  Registers are in parallel (use ...)
+ ;; expressions.  For simplicity, the first register is also in the unspec
+ ;; part.
++;; To avoid the usage of GNU extension, the length attribute is computed
++;; in a C function arm_attr_length_push_multi.
+ (define_insn "*push_multi"
+   [(match_parallel 2 "multi_register_push"
+     [(set (match_operand:BLK 0 "memory_operand" "=m")
+@@ -10353,7 +10572,9 @@
+ 
+     return \"\";
+   }"
+-  [(set_attr "type" "store4")]
++  [(set_attr "type" "store4")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_push_multi (operands[2], operands[1])"))]
+ )
+ 
+ (define_insn "stack_tie"
+
+=== modified file 'gcc/config/arm/constraints.md'
+--- old/gcc/config/arm/constraints.md	2011-08-25 13:26:58 +0000
++++ new/gcc/config/arm/constraints.md	2011-09-12 14:14:00 +0000
+@@ -31,7 +31,7 @@
+ ;; The following multi-letter normal constraints have been used:
+ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
+ ;; in Thumb-1 state: Pa, Pb, Pc, Pd
+-;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
++;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
+ 
+ ;; The following memory constraints have been used:
+ ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
+@@ -201,6 +201,11 @@
+   (and (match_code "const_int")
+        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
+ 
++(define_constraint "Py"
++  "@internal In Thumb-2 state a constant in the range 0 to 255"
++  (and (match_code "const_int")
++       (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
++
+ (define_constraint "G"
+  "In ARM/Thumb-2 state a valid FPA immediate constant."
+  (and (match_code "const_double")
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c	2011-09-12 14:14:00 +0000
+@@ -0,0 +1,13 @@
++/* Use conditional compare */
++/* { dg-options "-O2" } */
++/* { dg-skip-if "" { arm_thumb1_ok } } */
++/* { dg-final { scan-assembler "cmpne" } } */
++
++int f(int i, int j) 
++{
++  if ( (i == '+') || (j == '-') ) {
++    return 1;
++  } else {
++    return 0;
++  }
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c	2011-09-12 14:14:00 +0000
+@@ -0,0 +1,13 @@
++/* Use conditional compare */                                                                                         
++/* { dg-options "-O2" } */
++/* { dg-skip-if "" { arm_thumb1_ok } } */
++/* { dg-final { scan-assembler "cmpeq" } } */
++
++int f(int i, int j) 
++{
++  if ( (i == '+') && (j == '-') ) {
++    return 1;
++  } else {
++    return 0;
++  }
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c	2011-09-12 14:14:00 +0000
+@@ -0,0 +1,12 @@
++/* Use conditional compare */                                                                                         
++/* { dg-options "-O2" } */
++/* { dg-skip-if "" { arm_thumb1_ok } } */
++/* { dg-final { scan-assembler "cmpgt" } } */
++
++int f(int i, int j)
++{
++  if ( (i >= '+') ? (j > '-') : 0)
++    return 1;
++  else
++    return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c'
+--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c	2011-09-12 14:14:00 +0000
+@@ -0,0 +1,12 @@
++/* Use conditional compare */                                                                                         
++/* { dg-options "-O2" } */
++/* { dg-skip-if "" { arm_thumb1_ok } } */
++/* { dg-final { scan-assembler "cmpgt" } } */
++
++int f(int i, int j)
++{
++  if ( (i >= '+') ? (j <= '-') : 1)
++    return 1;
++  else
++    return 0;
++}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch
new file mode 100644
index 0000000000..41b5c6dbf9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch
@@ -0,0 +1,203 @@
+2011-09-15  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	Revert:
+
+	gcc/
+	PR target/49030
+	* config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
+	* config/arm/arm.c (maybe_get_arm_condition_code): New function,
+	reusing the old code from get_arm_condition_code.  Return ARM_NV
+	for invalid comparison codes.
+	(get_arm_condition_code): Redefine in terms of
+	maybe_get_arm_condition_code.
+	* config/arm/predicates.md (arm_comparison_operator): Use
+	maybe_get_arm_condition_code.
+
+	gcc/testsuite/
+	PR target/49030
+	* gcc.dg/torture/pr49030.c: New test.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-09-12 14:14:00 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-09-15 09:45:31 +0000
+@@ -180,7 +180,6 @@
+ #endif
+ extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
+ #ifdef RTX_CODE
+-extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
+ extern void thumb1_final_prescan_insn (rtx);
+ extern void thumb2_final_prescan_insn (rtx);
+ extern const char *thumb_load_double_from_address (rtx *);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-09-12 14:14:00 +0000
++++ new/gcc/config/arm/arm.c	2011-09-15 09:45:31 +0000
+@@ -17494,10 +17494,10 @@
+    decremented/zeroed by arm_asm_output_opcode as the insns are output.  */
+ 
+ /* Returns the index of the ARM condition code string in
+-   `arm_condition_codes', or ARM_NV if the comparison is invalid.
+-   COMPARISON should be an rtx like `(eq (...) (...))'.  */
+-enum arm_cond_code
+-maybe_get_arm_condition_code (rtx comparison)
++   `arm_condition_codes'.  COMPARISON should be an rtx like
++   `(eq (...) (...))'.  */
++static enum arm_cond_code
++get_arm_condition_code (rtx comparison)
+ {
+   enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
+   enum arm_cond_code code;
+@@ -17521,11 +17521,11 @@
+     case CC_DLTUmode: code = ARM_CC;
+ 
+     dominance:
++      gcc_assert (comp_code == EQ || comp_code == NE);
++
+       if (comp_code == EQ)
+ 	return ARM_INVERSE_CONDITION_CODE (code);
+-      if (comp_code == NE)
+-	return code;
+-      return ARM_NV;
++      return code;
+ 
+     case CC_NOOVmode:
+       switch (comp_code)
+@@ -17534,7 +17534,7 @@
+ 	case EQ: return ARM_EQ;
+ 	case GE: return ARM_PL;
+ 	case LT: return ARM_MI;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CC_Zmode:
+@@ -17542,7 +17542,7 @@
+ 	{
+ 	case NE: return ARM_NE;
+ 	case EQ: return ARM_EQ;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CC_Nmode:
+@@ -17550,7 +17550,7 @@
+ 	{
+ 	case NE: return ARM_MI;
+ 	case EQ: return ARM_PL;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CCFPEmode:
+@@ -17575,7 +17575,7 @@
+ 	  /* UNEQ and LTGT do not have a representation.  */
+ 	case UNEQ: /* Fall through.  */
+ 	case LTGT: /* Fall through.  */
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CC_SWPmode:
+@@ -17591,7 +17591,7 @@
+ 	case GTU: return ARM_CC;
+ 	case LEU: return ARM_CS;
+ 	case LTU: return ARM_HI;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CC_Cmode:
+@@ -17599,7 +17599,7 @@
+ 	{
+ 	case LTU: return ARM_CS;
+ 	case GEU: return ARM_CC;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CC_CZmode:
+@@ -17611,7 +17611,7 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CC_NCVmode:
+@@ -17621,7 +17621,7 @@
+ 	case LT: return ARM_LT;
+ 	case GEU: return ARM_CS;
+ 	case LTU: return ARM_CC;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     case CCmode:
+@@ -17637,22 +17637,13 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: return ARM_NV;
++	default: gcc_unreachable ();
+ 	}
+ 
+     default: gcc_unreachable ();
+     }
+ }
+ 
+-/* Like maybe_get_arm_condition_code, but never return ARM_NV.  */
+-static enum arm_cond_code
+-get_arm_condition_code (rtx comparison)
+-{
+-  enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
+-  gcc_assert (code != ARM_NV);
+-  return code;
+-}
+-
+ /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
+    instructions.  */
+ void
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-09-12 12:32:29 +0000
++++ new/gcc/config/arm/predicates.md	2011-09-15 09:45:31 +0000
+@@ -243,9 +243,10 @@
+ ;; True for integer comparisons and, if FP is active, for comparisons
+ ;; other than LTGT or UNEQ.
+ (define_special_predicate "arm_comparison_operator"
+-  (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
+-		    unordered,ordered,unlt,unle,unge,ungt")
+-       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
++  (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
++       (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
++			 && (TARGET_FPA || TARGET_VFP)")
++            (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
+ 
+ (define_special_predicate "lt_ge_comparison_operator"
+   (match_code "lt,ge"))
+
+=== removed file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49030.c	2011-09-05 09:40:19 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49030.c	1970-01-01 00:00:00 +0000
+@@ -1,19 +0,0 @@
+-void
+-sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
+-		       unsigned long dst_skip)
+-{
+-  long long y;
+-  while (nsamples--)
+-    {
+-      y = (long long) (*src * 8388608.0f) << 8;
+-      if (y > 2147483647) {
+-	*(int *) dst = 2147483647;
+-      } else if (y < -2147483647 - 1) {
+-	*(int *) dst = -2147483647 - 1;
+-      } else {
+-	*(int *) dst = (int) y;
+-      }
+-      dst += dst_skip;
+-      src++;
+-    }
+-}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch
new file mode 100644
index 0000000000..91b2191cb8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch
@@ -0,0 +1,80 @@
+2011-09-22  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	Backport from trunk -r178804:
+	modulo-sched.c (remove_node_from_ps): Return void
+	instead of bool.
+	(optimize_sc): Adjust call to remove_node_from_ps.
+	(sms_schedule): Add print info.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-08-09 04:51:48 +0000
++++ new/gcc/modulo-sched.c	2011-09-14 11:06:06 +0000
+@@ -211,7 +211,7 @@
+ static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
+ 					  int, int, sbitmap, int *, sbitmap,
+ 					  sbitmap);
+-static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
++static void remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
+ 
+ #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+ #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+@@ -834,8 +834,7 @@
+ 	if (next_ps_i->node->cuid == g->closing_branch->cuid)
+ 	  break;
+ 
+-      gcc_assert (next_ps_i);
+-      gcc_assert (remove_node_from_ps (ps, next_ps_i));
++      remove_node_from_ps (ps, next_ps_i);
+       success =
+ 	try_scheduling_node_in_cycle (ps, g->closing_branch,
+ 				      g->closing_branch->cuid, c,
+@@ -1485,8 +1484,8 @@
+           if (dump_file)
+             {
+ 	      fprintf (dump_file,
+-		       "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
+-		       stage_count);
++		       "%s:%d SMS succeeded %d %d (with ii, sc)\n",
++		       insn_file (tail), insn_line (tail), ps->ii, stage_count);
+ 	      print_partial_schedule (ps, dump_file);
+ 	    }
+  
+@@ -2810,22 +2809,18 @@
+ }
+ 
+ 
+-/* Removes the given PS_INSN from the partial schedule.  Returns false if the
+-   node is not found in the partial schedule, else returns true.  */
+-static bool
++/* Removes the given PS_INSN from the partial schedule.  */  
++static void 
+ remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i)
+ {
+   int row;
+ 
+-  if (!ps || !ps_i)
+-    return false;
+-
++  gcc_assert (ps && ps_i);
++  
+   row = SMODULO (ps_i->cycle, ps->ii);
+   if (! ps_i->prev_in_row)
+     {
+-      if (ps_i != ps->rows[row])
+-	return false;
+-
++      gcc_assert (ps_i == ps->rows[row]);
+       ps->rows[row] = ps_i->next_in_row;
+       if (ps->rows[row])
+ 	ps->rows[row]->prev_in_row = NULL;
+@@ -2839,7 +2834,7 @@
+    
+   ps->rows_length[row] -= 1; 
+   free (ps_i);
+-  return true;
++  return;
+ }
+ 
+ /* Unlike what literature describes for modulo scheduling (which focuses
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch
new file mode 100644
index 0000000000..16779bbf1e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch
@@ -0,0 +1,528 @@
+2011-09-25  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/testsuite/
+	* lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
+	Replace check_effective_target_arm_neon with
+	check_effective_target_arm_neon_ok.
+
+	Backport from mainline:
+
+	2011-09-06  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (arm_preferred_simd_mode): Check
+	TARGET_NEON_VECTORIZE_DOUBLE instead of
+	TARGET_NEON_VECTORIZE_QUAD.
+	(arm_autovectorize_vector_sizes): Likewise.
+	* config/arm/arm.opt (mvectorize-with-neon-quad): Make inverse
+	mask of mvectorize-with-neon-double.  Add RejectNegative.
+	(mvectorize-with-neon-double): New.
+
+	gcc/testsuite/
+	* lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
+	New procedure.
+	(add_options_for_quad_vectors): Replace with ...
+	(add_options_for_double_vectors): ... this.
+	* gfortran.dg/vect/pr19049.f90: Expect more printings on targets that
+	support multiple vector sizes since the vectorizer attempts to
+	vectorize with both vector sizes.
+	* gcc.dg/vect/no-vfa-vect-79.c,
+	gcc.dg/vect/no-vfa-vect-102a.c, gcc.dg/vect/vect-outer-1a.c,
+	gcc.dg/vect/vect-outer-1b.c, gcc.dg/vect/vect-outer-2b.c,
+	gcc.dg/vect/vect-outer-3a.c, gcc.dg/vect/no-vfa-vect-37.c,
+	gcc.dg/vect/vect-outer-3b.c, gcc.dg/vect/no-vfa-vect-101.c,
+	gcc.dg/vect/no-vfa-vect-102.c, gcc.dg/vect/vect-reduc-dot-s8b.c,
+	gcc.dg/vect/vect-outer-1.c, gcc.dg/vect/vect-104.c: Likewise.
+	* gcc.dg/vect/vect-42.c: Run with 64 bit vectors if applicable.
+	* gcc.dg/vect/vect-multitypes-6.c, gcc.dg/vect/vect-52.c,
+	gcc.dg/vect/vect-54.c, gcc.dg/vect/vect-46.c, gcc.dg/vect/vect-48.c,
+	gcc.dg/vect/vect-96.c, gcc.dg/vect/vect-multitypes-3.c,
+	gcc.dg/vect/vect-40.c: Likewise.
+	* gcc.dg/vect/vect-outer-5.c: Remove quad-vectors option as
+	redundant.
+	* gcc.dg/vect/vect-109.c, gcc.dg/vect/vect-peel-1.c,
+	gcc.dg/vect/vect-peel-2.c, gcc.dg/vect/slp-25.c,
+	gcc.dg/vect/vect-multitypes-1.c, gcc.dg/vect/slp-3.c,
+	gcc.dg/vect/no-vfa-pr29145.c, gcc.dg/vect/vect-multitypes-4.c:
+	Likewise.
+	* gcc.dg/vect/vect-peel-4.c: Make ia global.
+	
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-09-15 09:45:31 +0000
++++ new/gcc/config/arm/arm.c	2011-09-19 07:44:24 +0000
+@@ -22974,7 +22974,7 @@
+   return false;
+ }
+ 
+-/* Use the option -mvectorize-with-neon-quad to override the use of doubleword
++/* Use the option -mvectorize-with-neon-double to override the use of quardword
+    registers when autovectorizing for Neon, at least until multiple vector
+    widths are supported properly by the middle-end.  */
+ 
+@@ -22985,15 +22985,15 @@
+     switch (mode)
+       {
+       case SFmode:
+-	return TARGET_NEON_VECTORIZE_QUAD ? V4SFmode : V2SFmode;
++	return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode;
+       case SImode:
+-	return TARGET_NEON_VECTORIZE_QUAD ? V4SImode : V2SImode;
++	return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode;
+       case HImode:
+-	return TARGET_NEON_VECTORIZE_QUAD ? V8HImode : V4HImode;
++	return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode;
+       case QImode:
+-	return TARGET_NEON_VECTORIZE_QUAD ? V16QImode : V8QImode;
++	return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode;
+       case DImode:
+-	if (TARGET_NEON_VECTORIZE_QUAD)
++	if (!TARGET_NEON_VECTORIZE_DOUBLE)
+ 	  return V2DImode;
+ 	break;
+ 
+@@ -24226,7 +24226,7 @@
+ static unsigned int
+ arm_autovectorize_vector_sizes (void)
+ {
+-  return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
++  return TARGET_NEON_VECTORIZE_DOUBLE ? 0 : (16 | 8);
+ }
+ 
+ static bool
+
+=== modified file 'gcc/config/arm/arm.opt'
+--- old/gcc/config/arm/arm.opt	2009-06-18 11:24:10 +0000
++++ new/gcc/config/arm/arm.opt	2011-09-19 07:44:24 +0000
+@@ -158,9 +158,13 @@
+ Assume big endian bytes, little endian words
+ 
+ mvectorize-with-neon-quad
+-Target Report Mask(NEON_VECTORIZE_QUAD)
++Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE)
+ Use Neon quad-word (rather than double-word) registers for vectorization
+ 
++mvectorize-with-neon-double
++Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE)
++Use Neon double-word (rather than quad-word) registers for vectorization
++
+ mword-relocations
+ Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
+ Only generate absolute relocations on word sized values.
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c	2011-04-28 11:46:58 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-101.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-101.c	2007-09-04 12:05:19 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-101.c	2011-09-19 07:44:24 +0000
+@@ -45,6 +45,7 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
+-/* { dg-final { scan-tree-dump-times "can't determine dependence" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "can't determine dependence" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "can't determine dependence" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-102.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102.c	2007-09-12 07:48:44 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102.c	2011-09-19 07:44:24 +0000
+@@ -53,6 +53,7 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
+-/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-102a.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102a.c	2007-09-12 07:48:44 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102a.c	2011-09-19 07:44:24 +0000
+@@ -53,6 +53,7 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
+-/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-37.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-37.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-37.c	2011-09-19 07:44:24 +0000
+@@ -58,5 +58,6 @@
+    If/when the aliasing problems are resolved, unalignment may
+    prevent vectorization on some targets.  */
+ /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "can't determine dependence between" 2 "vect" } } */
++/* { dg-final { scan-tree-dump-times "can't determine dependence" 2 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "can't determine dependence" 4 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-79.c'
+--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-79.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-79.c	2011-09-19 07:44:24 +0000
+@@ -46,5 +46,6 @@
+   If/when the aliasing problems are resolved, unalignment may
+   prevent vectorization on some targets.  */
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "can't determine dependence between" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "can't determine dependence" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "can't determine dependence" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-25.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-25.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-25.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-3.c	2011-04-28 11:46:58 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-3.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-104.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-104.c	2007-09-12 07:48:44 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-104.c	2011-09-19 07:44:24 +0000
+@@ -64,6 +64,7 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
+-/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+ 
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-109.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-109.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-109.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-40.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-40.c	2009-05-25 14:18:21 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-40.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-42.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-42.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-42.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-46.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-46.c	2009-05-25 14:18:21 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-46.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-48.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-48.c	2009-11-04 10:22:22 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-48.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-52.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-52.c	2009-11-04 10:22:22 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-52.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-54.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-54.c	2009-10-27 11:46:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-54.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_float } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-96.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-96.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-96.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c	2009-11-04 10:22:22 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c	2010-10-04 14:59:30 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c	2009-11-10 18:01:22 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c	2011-09-19 07:44:24 +0000
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target vect_int } */
++/* { dg-add-options double_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-1.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-1.c	2011-09-19 07:44:24 +0000
+@@ -22,5 +22,6 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-1a.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-1a.c	2009-06-16 06:21:12 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-1a.c	2011-09-19 07:44:24 +0000
+@@ -20,5 +20,6 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-1b.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-1b.c	2007-08-19 11:02:48 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-1b.c	2011-09-19 07:44:24 +0000
+@@ -22,5 +22,6 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-2b.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-2b.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-2b.c	2011-09-19 07:44:24 +0000
+@@ -37,5 +37,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strided access in outer loop." 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-3a.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-3a.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-3a.c	2011-09-19 07:44:24 +0000
+@@ -49,5 +49,6 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail vect_no_align } } } */
+-/* { dg-final { scan-tree-dump-times "step doesn't divide the vector-size" 2 "vect" } } */
++/* { dg-final { scan-tree-dump-times "step doesn't divide the vector-size" 2 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "step doesn't divide the vector-size" 3 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-3b.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-3b.c	2009-05-08 12:39:01 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-3b.c	2011-09-19 07:44:24 +0000
+@@ -49,5 +49,6 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "strided access in outer loop" 4 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c	2011-04-28 11:46:58 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_float } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include <signal.h>
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-peel-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-peel-1.c	2011-01-10 12:41:40 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-peel-1.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-peel-2.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-peel-2.c	2011-01-10 12:41:40 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-peel-2.c	2011-09-19 07:44:24 +0000
+@@ -1,5 +1,4 @@
+ /* { dg-require-effective-target vect_int } */
+-/* { dg-add-options quad_vectors } */
+ 
+ #include <stdarg.h>
+ #include "tree-vect.h"
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-peel-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-peel-4.c	2011-01-10 12:41:40 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-peel-4.c	2011-09-19 07:44:24 +0000
+@@ -6,12 +6,12 @@
+ #define N 128
+ 
+ int ib[N+7];
++int ia[N+1];
+ 
+ __attribute__ ((noinline))
+ int main1 ()
+ {
+   int i;
+-  int ia[N+1];
+ 
+   /* Don't peel keeping one load and the store aligned.  */
+   for (i = 0; i <= N; i++)
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8b.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8b.c	2010-05-27 12:23:45 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8b.c	2011-09-19 07:44:24 +0000
+@@ -58,7 +58,8 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */
+-/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_multiple_sizes } } } */
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail *-*-* } } } */
+ 
+
+=== modified file 'gcc/testsuite/gfortran.dg/vect/pr19049.f90'
+--- old/gcc/testsuite/gfortran.dg/vect/pr19049.f90	2005-07-25 11:05:07 +0000
++++ new/gcc/testsuite/gfortran.dg/vect/pr19049.f90	2011-09-19 07:44:24 +0000
+@@ -19,6 +19,7 @@
+       end
+ 
+ ! { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } }
+-! { dg-final { scan-tree-dump-times "complicated access pattern" 1 "vect" } }
++! { dg-final { scan-tree-dump-times "complicated access pattern" 1 "vect" { xfail vect_multiple_sizes } } }
++! { dg-final { scan-tree-dump-times "complicated access pattern" 2 "vect" { target vect_multiple_sizes } } }
+ ! { dg-final { cleanup-tree-dump "vect" } }
+ 
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-08-13 08:32:32 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-09-20 07:54:28 +0000
+@@ -3265,6 +3265,24 @@
+     }]
+ }
+ 
++# Return 1 if the target supports multiple vector sizes
++
++proc check_effective_target_vect_multiple_sizes { } {
++    global et_vect_multiple_sizes
++
++    if [info exists et_vect_multiple_sizes_saved] {
++        verbose "check_effective_target_vect_multiple_sizes: using cached result" 2
++    } else {
++        set et_vect_multiple_sizes_saved 0
++          if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
++           set et_vect_multiple_sizes_saved 1
++        }
++    }
++
++    verbose "check_effective_target_vect_multiple_sizes: returning $et_vect_multiple_sizes_saved" 2
++    return $et_vect_multiple_sizes_saved
++}
++
+ # Return 1 if the target supports section-anchors
+ 
+ proc check_effective_target_section_anchors { } {
+@@ -3648,11 +3666,11 @@
+     return $flags
+ }
+ 
+-# Add to FLAGS the flags needed to enable 128-bit vectors.
++# Add to FLAGS the flags needed to enable 64-bit vectors.
+ 
+-proc add_options_for_quad_vectors { flags } {
++proc add_options_for_double_vectors { flags } {
+     if [is-effective-target arm_neon_ok] {
+-	return "$flags -mvectorize-with-neon-quad"
++	return "$flags -mvectorize-with-neon-double"
+     }
+ 
+     return $flags
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch
new file mode 100644
index 0000000000..2f70b1b9c2
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch
@@ -0,0 +1,387 @@
+2011-09-28  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-28  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/neon.md (neon_move_lo_quad_<mode>): Delete.
+	(neon_move_hi_quad_<mode>): Likewise.
+	(move_hi_quad_<mode>, move_lo_quad_<mode>): Use subreg moves.
+
+2011-09-28  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-27  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/neon.md (neon_vget_highv16qi, neon_vget_highv8hi)
+	(neon_vget_highv4si, neon_vget_highv4sf, neon_vget_highv2di)
+	(neon_vget_lowv16qi, neon_vget_lowv8hi, neon_vget_lowv4si)
+	(neon_vget_lowv4sf, neon_vget_lowv2di): Turn into define_expands
+	that produce subreg moves.  Define using VQX iterators.
+
+2011-09-28  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* simplify-rtx.c (simplify_subreg): Check that the inner mode is
+	a scalar integer before applying integer-only optimisations to
+	inner arithmetic.
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2011-07-04 14:03:49 +0000
++++ new/gcc/config/arm/neon.md	2011-09-28 15:14:59 +0000
+@@ -1235,66 +1235,14 @@
+                     (const_string "neon_int_1") (const_string "neon_int_5")))]
+ )
+ 
+-; FIXME: We wouldn't need the following insns if we could write subregs of
+-; vector registers. Make an attempt at removing unnecessary moves, though
+-; we're really at the mercy of the register allocator.
+-
+-(define_insn "neon_move_lo_quad_<mode>"
+-  [(set (match_operand:ANY128 0 "s_register_operand" "+w")
+-        (vec_concat:ANY128
+-          (match_operand:<V_HALF> 1 "s_register_operand" "w")
+-          (vec_select:<V_HALF> 
+-		(match_dup 0)
+-	        (match_operand:ANY128 2 "vect_par_constant_high" ""))))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%e0, %P1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_move_hi_quad_<mode>"
+-  [(set (match_operand:ANY128 0 "s_register_operand" "+w")
+-        (vec_concat:ANY128
+-          (vec_select:<V_HALF>
+-		(match_dup 0)
+-	        (match_operand:ANY128 2 "vect_par_constant_low" ""))
+-          (match_operand:<V_HALF> 1 "s_register_operand" "w")))]
+-	   
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%f0, %P1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+ (define_expand "move_hi_quad_<mode>"
+  [(match_operand:ANY128 0 "s_register_operand" "")
+   (match_operand:<V_HALF> 1 "s_register_operand" "")]
+  "TARGET_NEON"
+ {
+-  rtvec v = rtvec_alloc (<V_mode_nunits>/2);
+-  rtx t1;
+-  int i;
+-
+-  for (i=0; i < (<V_mode_nunits>/2); i++)
+-     RTVEC_ELT (v, i) = GEN_INT (i);
+-
+-  t1 = gen_rtx_PARALLEL (<MODE>mode, v);
+-  emit_insn (gen_neon_move_hi_quad_<mode> (operands[0], operands[1], t1));
+-
++  emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0], <MODE>mode,
++				       GET_MODE_SIZE (<V_HALF>mode)),
++		  operands[1]);
+   DONE;
+ })
+ 
+@@ -1303,16 +1251,9 @@
+   (match_operand:<V_HALF> 1 "s_register_operand" "")]
+  "TARGET_NEON"
+ {
+-  rtvec v = rtvec_alloc (<V_mode_nunits>/2);
+-  rtx t1;
+-  int i;
+-
+-  for (i=0; i < (<V_mode_nunits>/2); i++)
+-     RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
+-
+-  t1 = gen_rtx_PARALLEL (<MODE>mode, v);
+-  emit_insn (gen_neon_move_lo_quad_<mode> (operands[0], operands[1], t1));
+-
++  emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0],
++				       <MODE>mode, 0),
++		  operands[1]);
+   DONE;
+ })
+ 
+@@ -2950,183 +2891,27 @@
+    (set_attr "neon_type" "neon_bp_simple")]
+ )
+ 
+-(define_insn "neon_vget_highv16qi"
+-  [(set (match_operand:V8QI 0 "s_register_operand" "=w")
+-	(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
+-                         (parallel [(const_int 8) (const_int 9)
+-			            (const_int 10) (const_int 11)
+-				    (const_int 12) (const_int 13)
+-				    (const_int 14) (const_int 15)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src + 2)
+-    return "vmov\t%P0, %f1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_highv8hi"
+-  [(set (match_operand:V4HI 0 "s_register_operand" "=w")
+-	(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
+-	                 (parallel [(const_int 4) (const_int 5)
+-			            (const_int 6) (const_int 7)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src + 2)
+-    return "vmov\t%P0, %f1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_highv4si"
+-  [(set (match_operand:V2SI 0 "s_register_operand" "=w")
+-	(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
+-	                 (parallel [(const_int 2) (const_int 3)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src + 2)
+-    return "vmov\t%P0, %f1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_highv4sf"
+-  [(set (match_operand:V2SF 0 "s_register_operand" "=w")
+-	(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
+-	                 (parallel [(const_int 2) (const_int 3)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src + 2)
+-    return "vmov\t%P0, %f1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_highv2di"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
+-	               (parallel [(const_int 1)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src + 2)
+-    return "vmov\t%P0, %f1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_lowv16qi"
+-  [(set (match_operand:V8QI 0 "s_register_operand" "=w")
+-	(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
+-                         (parallel [(const_int 0) (const_int 1)
+-			            (const_int 2) (const_int 3)
+-				    (const_int 4) (const_int 5)
+-				    (const_int 6) (const_int 7)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%P0, %e1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_lowv8hi"
+-  [(set (match_operand:V4HI 0 "s_register_operand" "=w")
+-	(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
+-	                 (parallel [(const_int 0) (const_int 1)
+-			            (const_int 2) (const_int 3)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%P0, %e1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_lowv4si"
+-  [(set (match_operand:V2SI 0 "s_register_operand" "=w")
+-	(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
+-	                 (parallel [(const_int 0) (const_int 1)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%P0, %e1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_lowv4sf"
+-  [(set (match_operand:V2SF 0 "s_register_operand" "=w")
+-	(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
+-	                 (parallel [(const_int 0) (const_int 1)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%P0, %e1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
+-
+-(define_insn "neon_vget_lowv2di"
+-  [(set (match_operand:DI 0 "s_register_operand" "=w")
+-	(vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
+-	               (parallel [(const_int 0)])))]
+-  "TARGET_NEON"
+-{
+-  int dest = REGNO (operands[0]);
+-  int src = REGNO (operands[1]);
+-
+-  if (dest != src)
+-    return "vmov\t%P0, %e1";
+-  else
+-    return "";
+-}
+-  [(set_attr "neon_type" "neon_bp_simple")]
+-)
++(define_expand "neon_vget_high<mode>"
++  [(match_operand:<V_HALF> 0 "s_register_operand")
++   (match_operand:VQX 1 "s_register_operand")]
++  "TARGET_NEON"
++{
++  emit_move_insn (operands[0],
++		  simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode,
++				       GET_MODE_SIZE (<V_HALF>mode)));
++  DONE;
++})
++
++(define_expand "neon_vget_low<mode>"
++  [(match_operand:<V_HALF> 0 "s_register_operand")
++   (match_operand:VQX 1 "s_register_operand")]
++  "TARGET_NEON"
++{
++  emit_move_insn (operands[0],
++		  simplify_gen_subreg (<V_HALF>mode, operands[1],
++				       <MODE>mode, 0));
++  DONE;
++})
+ 
+ (define_insn "neon_vcvt<mode>"
+   [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+
+=== modified file 'gcc/simplify-rtx.c'
+--- old/gcc/simplify-rtx.c	2011-08-13 08:32:32 +0000
++++ new/gcc/simplify-rtx.c	2011-09-28 15:11:59 +0000
+@@ -5567,6 +5567,7 @@
+   /* Optimize SUBREG truncations of zero and sign extended values.  */
+   if ((GET_CODE (op) == ZERO_EXTEND
+        || GET_CODE (op) == SIGN_EXTEND)
++      && SCALAR_INT_MODE_P (innermode)
+       && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode))
+     {
+       unsigned int bitpos = subreg_lsb_1 (outermode, innermode, byte);
+@@ -5605,6 +5606,7 @@
+   if ((GET_CODE (op) == LSHIFTRT
+        || GET_CODE (op) == ASHIFTRT)
+       && SCALAR_INT_MODE_P (outermode)
++      && SCALAR_INT_MODE_P (innermode)
+       /* Ensure that OUTERMODE is at least twice as wide as the INNERMODE
+ 	 to avoid the possibility that an outer LSHIFTRT shifts by more
+ 	 than the sign extension's sign_bit_copies and introduces zeros
+@@ -5624,6 +5626,7 @@
+   if ((GET_CODE (op) == LSHIFTRT
+        || GET_CODE (op) == ASHIFTRT)
+       && SCALAR_INT_MODE_P (outermode)
++      && SCALAR_INT_MODE_P (innermode)
+       && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode)
+       && CONST_INT_P (XEXP (op, 1))
+       && GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
+@@ -5638,6 +5641,7 @@
+      the outer subreg is effectively a truncation to the original mode.  */
+   if (GET_CODE (op) == ASHIFT
+       && SCALAR_INT_MODE_P (outermode)
++      && SCALAR_INT_MODE_P (innermode)
+       && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode)
+       && CONST_INT_P (XEXP (op, 1))
+       && (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
+@@ -5651,7 +5655,7 @@
+   /* Recognize a word extraction from a multi-word subreg.  */
+   if ((GET_CODE (op) == LSHIFTRT
+        || GET_CODE (op) == ASHIFTRT)
+-      && SCALAR_INT_MODE_P (outermode)
++      && SCALAR_INT_MODE_P (innermode)
+       && GET_MODE_BITSIZE (outermode) >= BITS_PER_WORD
+       && GET_MODE_BITSIZE (innermode) >= (2 * GET_MODE_BITSIZE (outermode))
+       && CONST_INT_P (XEXP (op, 1))
+@@ -5673,6 +5677,7 @@
+ 
+   if ((GET_CODE (op) == LSHIFTRT
+        || GET_CODE (op) == ASHIFTRT)
++      && SCALAR_INT_MODE_P (innermode)
+       && MEM_P (XEXP (op, 0))
+       && CONST_INT_P (XEXP (op, 1))
+       && GET_MODE_SIZE (outermode) < GET_MODE_SIZE (GET_MODE (op))
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch
new file mode 100644
index 0000000000..d44f8cf1a5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch
@@ -0,0 +1,290 @@
+2011-10-01  Revital Eres  <revital.eres@linaro.org> 
+
+	gcc/
+	Backport from mainline -r179380 and -r179381
+
+	* ddg.c (autoinc_var_is_used_p): New function.
+	(create_ddg_dep_from_intra_loop_link,
+	add_cross_iteration_register_deps): Call it.
+	* ddg.h (autoinc_var_is_used_p): Declare.
+	* modulo-sched.c (sms_schedule): Handle instructions with REG_INC.
+	(generate_reg_moves): Call autoinc_var_is_used_p.  Skip
+	instructions that do not set a register and verify no regmoves
+	are created for !single_set instructions.
+
+	gcc/testsuite/
+
+	* gcc.dg/sms-10.c: New file
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-07-31 11:29:10 +0000
++++ new/gcc/ddg.c	2011-10-02 06:56:53 +0000
+@@ -145,6 +145,27 @@
+   return rtx_mem_access_p (PATTERN (insn));
+ }
+ 
++/* Return true if DEF_INSN contains address being auto-inc or auto-dec
++   which is used in USE_INSN.  Otherwise return false.  The result is
++   being used to decide whether to remove the edge between def_insn and
++   use_insn when -fmodulo-sched-allow-regmoves is set.  This function
++   doesn't need to consider the specific address register; no reg_moves
++   will be allowed for any life range defined by def_insn and used
++   by use_insn, if use_insn uses an address register auto-inc'ed by
++   def_insn.  */
++bool
++autoinc_var_is_used_p (rtx def_insn, rtx use_insn)
++{
++  rtx note;
++
++  for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1))
++    if (REG_NOTE_KIND (note) == REG_INC
++	&& reg_referenced_p (XEXP (note, 0), PATTERN (use_insn)))
++      return true;
++
++  return false;
++}
++
+ /* Computes the dependence parameters (latency, distance etc.), creates
+    a ddg_edge and adds it to the given DDG.  */
+ static void
+@@ -173,10 +194,15 @@
+      compensate for that by generating reg-moves based on the life-range
+      analysis.  The anti-deps that will be deleted are the ones which
+      have true-deps edges in the opposite direction (in other words
+-     the kernel has only one def of the relevant register).  TODO:
+-     support the removal of all anti-deps edges, i.e. including those
++     the kernel has only one def of the relevant register).
++     If the address that is being auto-inc or auto-dec in DEST_NODE
++     is used in SRC_NODE then do not remove the edge to make sure
++     reg-moves will not be created for this address.  
++     TODO: support the removal of all anti-deps edges, i.e. including those
+      whose register has multiple defs in the loop.  */
+-  if (flag_modulo_sched_allow_regmoves && (t == ANTI_DEP && dt == REG_DEP))
++  if (flag_modulo_sched_allow_regmoves 
++      && (t == ANTI_DEP && dt == REG_DEP)
++      && !autoinc_var_is_used_p (dest_node->insn, src_node->insn))
+     {
+       rtx set;
+ 
+@@ -302,10 +328,14 @@
+ 	  gcc_assert (first_def_node);
+ 
+          /* Always create the edge if the use node is a branch in
+-            order to prevent the creation of reg-moves.  */
++            order to prevent the creation of reg-moves.  
++            If the address that is being auto-inc or auto-dec in LAST_DEF
++            is used in USE_INSN then do not remove the edge to make sure
++            reg-moves will not be created for that address.  */
+           if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
+               || !flag_modulo_sched_allow_regmoves
+-	      || JUMP_P (use_node->insn))
++	      || JUMP_P (use_node->insn)
++              || autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn))
+             create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
+                                     REG_DEP, 1);
+ 
+
+=== modified file 'gcc/ddg.h'
+--- old/gcc/ddg.h	2009-11-25 10:55:54 +0000
++++ new/gcc/ddg.h	2011-10-02 06:56:53 +0000
+@@ -186,4 +186,6 @@
+ int find_nodes_on_paths (sbitmap result, ddg_ptr, sbitmap from, sbitmap to);
+ int longest_simple_path (ddg_ptr, int from, int to, sbitmap via);
+ 
++bool autoinc_var_is_used_p (rtx, rtx);
++
+ #endif /* GCC_DDG_H */
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-09-14 11:06:06 +0000
++++ new/gcc/modulo-sched.c	2011-10-02 06:56:53 +0000
+@@ -477,7 +477,12 @@
+       sbitmap *uses_of_defs;
+       rtx last_reg_move;
+       rtx prev_reg, old_reg;
+-
++      rtx set = single_set (u->insn);
++      
++      /* Skip instructions that do not set a register.  */
++      if ((set && !REG_P (SET_DEST (set))))
++        continue;
++ 
+       /* Compute the number of reg_moves needed for u, by looking at life
+ 	 ranges started at u (excluding self-loops).  */
+       for (e = u->out; e; e = e->next_out)
+@@ -494,6 +499,20 @@
+ 		&& SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
+ 	      nreg_moves4e--;
+ 
++            if (nreg_moves4e >= 1)
++	      {
++		/* !single_set instructions are not supported yet and
++		   thus we do not except to encounter them in the loop
++		   except from the doloop part.  For the latter case
++		   we assume no regmoves are generated as the doloop
++		   instructions are tied to the branch with an edge.  */
++		gcc_assert (set);
++		/* If the instruction contains auto-inc register then
++		   validate that the regmov is being generated for the
++		   target regsiter rather then the inc'ed register.	*/
++		gcc_assert (!autoinc_var_is_used_p (u->insn, e->dest->insn));
++	      }
++	    
+ 	    nreg_moves = MAX (nreg_moves, nreg_moves4e);
+ 	  }
+ 
+@@ -1266,12 +1285,10 @@
+ 	continue;
+       }
+ 
+-      /* Don't handle BBs with calls or barriers or auto-increment insns 
+-	 (to avoid creating invalid reg-moves for the auto-increment insns),
++      /* Don't handle BBs with calls or barriers
+ 	 or !single_set with the exception of instructions that include
+ 	 count_reg---these instructions are part of the control part
+ 	 that do-loop recognizes.
+-         ??? Should handle auto-increment insns.
+          ??? Should handle insns defining subregs.  */
+      for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
+       {
+@@ -1282,7 +1299,6 @@
+             || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
+                 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
+                 && !reg_mentioned_p (count_reg, insn))
+-            || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
+             || (INSN_P (insn) && (set = single_set (insn))
+                 && GET_CODE (SET_DEST (set)) == SUBREG))
+         break;
+@@ -1296,8 +1312,6 @@
+ 		fprintf (dump_file, "SMS loop-with-call\n");
+ 	      else if (BARRIER_P (insn))
+ 		fprintf (dump_file, "SMS loop-with-barrier\n");
+-              else if (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
+-                fprintf (dump_file, "SMS reg inc\n");
+               else if ((NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
+                 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE))
+                 fprintf (dump_file, "SMS loop-with-not-single-set\n");
+
+=== added file 'gcc/testsuite/gcc.dg/sms-10.c'
+--- old/gcc/testsuite/gcc.dg/sms-10.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/sms-10.c	2011-10-02 06:56:53 +0000
+@@ -0,0 +1,118 @@
++ /* { dg-do run } */
++ /* { dg-options "-O2 -fmodulo-sched -fmodulo-sched-allow-regmoves -fdump-rtl-sms" } */
++
++
++typedef __SIZE_TYPE__ size_t;
++extern void *malloc (size_t);
++extern void free (void *);
++extern void abort (void);
++
++struct regstat_n_sets_and_refs_t
++{
++  int sets;
++  int refs;
++};
++
++struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs;
++
++struct df_reg_info
++{
++  unsigned int n_refs;
++};
++
++struct df_d
++{
++  struct df_reg_info **def_regs;
++  struct df_reg_info **use_regs;
++};
++struct df_d *df;
++
++static inline int
++REG_N_SETS (int regno)
++{
++  return regstat_n_sets_and_refs[regno].sets;
++}
++
++__attribute__ ((noinline))
++     int max_reg_num (void)
++{
++  return 100;
++}
++
++__attribute__ ((noinline))
++     void regstat_init_n_sets_and_refs (void)
++{
++  unsigned int i;
++  unsigned int max_regno = max_reg_num ();
++
++  for (i = 0; i < max_regno; i++)
++    {
++      (regstat_n_sets_and_refs[i].sets = (df->def_regs[(i)]->n_refs));
++      (regstat_n_sets_and_refs[i].refs =
++       (df->use_regs[(i)]->n_refs) + REG_N_SETS (i));
++    }
++}
++
++int a_sets[100] =
++  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
++  21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
++  40, 41, 42,
++  43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
++  62, 63, 64,
++  65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
++  84, 85, 86,
++  87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99
++};
++
++int a_refs[100] =
++  { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38,
++  40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76,
++  78, 80, 82,
++  84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116,
++  118, 120,
++  122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150,
++  152, 154, 156,
++  158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180, 182, 184, 186,
++  188, 190, 192,
++  194, 196, 198
++};
++
++int
++main ()
++{
++  struct df_reg_info *b[100], *c[100];
++  struct df_d df1;
++  size_t s = sizeof (struct df_reg_info);
++  struct regstat_n_sets_and_refs_t a[100];
++
++  df = &df1;
++  regstat_n_sets_and_refs = a;
++  int i;
++
++  for (i = 0; i < 100; i++)
++    {
++      b[i] = (struct df_reg_info *) malloc (s);
++      b[i]->n_refs = i;
++      c[i] = (struct df_reg_info *) malloc (s);
++      c[i]->n_refs = i;
++    }
++
++  df1.def_regs = b;
++  df1.use_regs = c;
++  regstat_init_n_sets_and_refs ();
++
++  for (i = 0; i < 100; i++)
++    if ((a[i].sets != a_sets[i]) || (a[i].refs != a_refs[i]))
++      abort ();
++
++  for (i = 0; i < 100; i++)
++    {
++      free (b[i]);
++      free (c[i]);
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-rtl-dump-times "SMS succeeded" 1 "sms" { target powerpc*-*-* } } } */
++/* { dg-final { cleanup-rtl-dump "sms" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch
new file mode 100644
index 0000000000..ef98142bc4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch
@@ -0,0 +1,105 @@
+2011-10-03  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline:
+
+	2011-09-13  Sevak Sargsyan <sevak.sargsyan@ispras.ru>
+
+	gcc/
+	* config/arm/neon.md (neon_vabd<mode>_2, neon_vabd<mode>_3): New
+	define_insn patterns for combine.
+
+	gcc/testsuite/
+	* gcc.target/arm/neon-combine-sub-abs-into-vabd.c: New test.
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2011-09-28 15:14:59 +0000
++++ new/gcc/config/arm/neon.md	2011-10-03 01:32:17 +0000
+@@ -5428,3 +5428,32 @@
+   emit_insn (gen_neon_vec_pack_trunc_<V_double> (operands[0], tempreg));
+   DONE;
+ })
++
++(define_insn "neon_vabd<mode>_2"
++ [(set (match_operand:VDQ 0 "s_register_operand" "=w")
++       (abs:VDQ (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
++                           (match_operand:VDQ 2 "s_register_operand" "w"))))]
++ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
++ "vabd.<V_s_elem> %<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set (attr "neon_type")
++       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
++                     (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++                                   (const_string "neon_fp_vadd_ddd_vabs_dd")
++                                   (const_string "neon_fp_vadd_qqq_vabs_qq"))
++                     (const_string "neon_int_5")))]
++)
++
++(define_insn "neon_vabd<mode>_3"
++ [(set (match_operand:VDQ 0 "s_register_operand" "=w")
++       (abs:VDQ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "w")
++                             (match_operand:VDQ 2 "s_register_operand" "w")]
++                 UNSPEC_VSUB)))]
++ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
++ "vabd.<V_if_elem> %<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set (attr "neon_type")
++       (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
++                     (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
++                                   (const_string "neon_fp_vadd_ddd_vabs_dd")
++                                   (const_string "neon_fp_vadd_qqq_vabs_qq"))
++                     (const_string "neon_int_5")))]
++)
+
+=== added file 'gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c'
+--- old/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c	2011-10-03 01:32:17 +0000
+@@ -0,0 +1,50 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -funsafe-math-optimizations" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++float32x2_t f_sub_abs_to_vabd_32()
++{
++  float32x2_t val1 = vdup_n_f32 (10);
++  float32x2_t val2 = vdup_n_f32 (30);
++  float32x2_t sres = vsub_f32(val1, val2);
++  float32x2_t res = vabs_f32 (sres);
++
++  return res;
++}
++/* { dg-final { scan-assembler "vabd\.f32" } }*/
++
++#include <arm_neon.h>
++int8x8_t sub_abs_to_vabd_8()
++{
++  int8x8_t val1 = vdup_n_s8 (10);
++  int8x8_t val2 = vdup_n_s8 (30);
++  int8x8_t sres = vsub_s8(val1, val2);
++  int8x8_t res = vabs_s8 (sres);
++
++  return res;
++}
++/* { dg-final { scan-assembler "vabd\.s8" } }*/
++
++int16x4_t sub_abs_to_vabd_16()
++{
++  int16x4_t val1 = vdup_n_s16 (10);
++  int16x4_t val2 = vdup_n_s16 (30);
++  int16x4_t sres = vsub_s16(val1, val2);
++  int16x4_t res = vabs_s16 (sres);
++
++  return res;
++}
++/* { dg-final { scan-assembler "vabd\.s16" } }*/
++
++int32x2_t sub_abs_to_vabd_32()
++{
++  int32x2_t val1 = vdup_n_s32 (10);
++  int32x2_t val2 = vdup_n_s32 (30);
++  int32x2_t sres = vsub_s32(val1, val2);
++  int32x2_t res = vabs_s32 (sres);
++
++   return res;
++}
++/* { dg-final { scan-assembler "vabd\.s32" } }*/
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch
new file mode 100644
index 0000000000..e097ec27fa
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch
@@ -0,0 +1,436 @@
+2011-10-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-22  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/arm/predicates.md (expandable_comparison_operator): New
+	predicate, extracted from...
+	(arm_comparison_operator): ...here.
+	* config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
+	(cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
+	(movdfcc): Use expandable_comparison_operator.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-09-22  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* gcc.target/arm/cmp-1.c: New test.
+	* gcc.target/arm/cmp-2.c: Likewise.
+
+2011-10-03  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-09-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR target/49030
+	* config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
+	* config/arm/arm.c (maybe_get_arm_condition_code): New function,
+	reusing the old code from get_arm_condition_code.  Return ARM_NV
+	for invalid comparison codes.
+	(get_arm_condition_code): Redefine in terms of
+	maybe_get_arm_condition_code.
+	* config/arm/predicates.md (arm_comparison_operator): Use
+	maybe_get_arm_condition_code.
+
+	gcc/testsuite/
+	Backport from mainline:
+
+	2011-09-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR target/49030
+	* gcc.dg/torture/pr49030.c: New test.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-09-15 09:45:31 +0000
++++ new/gcc/config/arm/arm-protos.h	2011-10-03 09:46:40 +0000
+@@ -180,6 +180,7 @@
+ #endif
+ extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
+ #ifdef RTX_CODE
++extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
+ extern void thumb1_final_prescan_insn (rtx);
+ extern void thumb2_final_prescan_insn (rtx);
+ extern const char *thumb_load_double_from_address (rtx *);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-09-19 07:44:24 +0000
++++ new/gcc/config/arm/arm.c	2011-10-03 09:46:40 +0000
+@@ -17494,10 +17494,10 @@
+    decremented/zeroed by arm_asm_output_opcode as the insns are output.  */
+ 
+ /* Returns the index of the ARM condition code string in
+-   `arm_condition_codes'.  COMPARISON should be an rtx like
+-   `(eq (...) (...))'.  */
+-static enum arm_cond_code
+-get_arm_condition_code (rtx comparison)
++   `arm_condition_codes', or ARM_NV if the comparison is invalid.
++   COMPARISON should be an rtx like `(eq (...) (...))'.  */
++enum arm_cond_code
++maybe_get_arm_condition_code (rtx comparison)
+ {
+   enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
+   enum arm_cond_code code;
+@@ -17521,11 +17521,11 @@
+     case CC_DLTUmode: code = ARM_CC;
+ 
+     dominance:
+-      gcc_assert (comp_code == EQ || comp_code == NE);
+-
+       if (comp_code == EQ)
+ 	return ARM_INVERSE_CONDITION_CODE (code);
+-      return code;
++      if (comp_code == NE)
++	return code;
++      return ARM_NV;
+ 
+     case CC_NOOVmode:
+       switch (comp_code)
+@@ -17534,7 +17534,7 @@
+ 	case EQ: return ARM_EQ;
+ 	case GE: return ARM_PL;
+ 	case LT: return ARM_MI;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Zmode:
+@@ -17542,7 +17542,7 @@
+ 	{
+ 	case NE: return ARM_NE;
+ 	case EQ: return ARM_EQ;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Nmode:
+@@ -17550,7 +17550,7 @@
+ 	{
+ 	case NE: return ARM_MI;
+ 	case EQ: return ARM_PL;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CCFPEmode:
+@@ -17575,7 +17575,7 @@
+ 	  /* UNEQ and LTGT do not have a representation.  */
+ 	case UNEQ: /* Fall through.  */
+ 	case LTGT: /* Fall through.  */
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_SWPmode:
+@@ -17591,7 +17591,7 @@
+ 	case GTU: return ARM_CC;
+ 	case LEU: return ARM_CS;
+ 	case LTU: return ARM_HI;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_Cmode:
+@@ -17599,7 +17599,7 @@
+ 	{
+ 	case LTU: return ARM_CS;
+ 	case GEU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_CZmode:
+@@ -17611,7 +17611,7 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CC_NCVmode:
+@@ -17621,7 +17621,7 @@
+ 	case LT: return ARM_LT;
+ 	case GEU: return ARM_CS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     case CCmode:
+@@ -17637,13 +17637,22 @@
+ 	case GTU: return ARM_HI;
+ 	case LEU: return ARM_LS;
+ 	case LTU: return ARM_CC;
+-	default: gcc_unreachable ();
++	default: return ARM_NV;
+ 	}
+ 
+     default: gcc_unreachable ();
+     }
+ }
+ 
++/* Like maybe_get_arm_condition_code, but never return ARM_NV.  */
++static enum arm_cond_code
++get_arm_condition_code (rtx comparison)
++{
++  enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
++  gcc_assert (code != ARM_NV);
++  return code;
++}
++
+ /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
+    instructions.  */
+ void
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-09-12 14:14:00 +0000
++++ new/gcc/config/arm/arm.md	2011-10-03 09:47:33 +0000
+@@ -6543,7 +6543,7 @@
+ 
+ (define_expand "cbranchsi4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:SI 1 "s_register_operand" "")
+ 	        (match_operand:SI 2 "nonmemory_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -6594,7 +6594,7 @@
+ 
+ (define_expand "cbranchsf4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:SF 1 "s_register_operand" "")
+ 	        (match_operand:SF 2 "arm_float_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -6606,7 +6606,7 @@
+ 
+ (define_expand "cbranchdf4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:DF 1 "s_register_operand" "")
+ 	        (match_operand:DF 2 "arm_float_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -6618,7 +6618,7 @@
+ 
+ (define_expand "cbranchdi4"
+   [(set (pc) (if_then_else
+-	      (match_operator 0 "arm_comparison_operator"
++	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:DI 1 "cmpdi_operand" "")
+ 	        (match_operand:DI 2 "cmpdi_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+@@ -7473,7 +7473,7 @@
+ 
+ (define_expand "cstoresi4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:SI 2 "s_register_operand" "")
+ 	  (match_operand:SI 3 "reg_or_int_operand" "")]))]
+   "TARGET_32BIT || TARGET_THUMB1"
+@@ -7609,7 +7609,7 @@
+ 
+ (define_expand "cstoresf4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:SF 2 "s_register_operand" "")
+ 	  (match_operand:SF 3 "arm_float_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -7619,7 +7619,7 @@
+ 
+ (define_expand "cstoredf4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:DF 2 "s_register_operand" "")
+ 	  (match_operand:DF 3 "arm_float_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+@@ -7629,7 +7629,7 @@
+ 
+ (define_expand "cstoredi4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(match_operator:SI 1 "arm_comparison_operator"
++	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:DI 2 "cmpdi_operand" "")
+ 	  (match_operand:DI 3 "cmpdi_operand" "")]))]
+   "TARGET_32BIT"
+@@ -7749,7 +7749,7 @@
+ 
+ (define_expand "movsicc"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+-	(if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
++	(if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
+ 			 (match_operand:SI 2 "arm_not_operand" "")
+ 			 (match_operand:SI 3 "arm_not_operand" "")))]
+   "TARGET_32BIT"
+@@ -7769,7 +7769,7 @@
+ 
+ (define_expand "movsfcc"
+   [(set (match_operand:SF 0 "s_register_operand" "")
+-	(if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
++	(if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
+ 			 (match_operand:SF 2 "s_register_operand" "")
+ 			 (match_operand:SF 3 "nonmemory_operand" "")))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -7795,7 +7795,7 @@
+ 
+ (define_expand "movdfcc"
+   [(set (match_operand:DF 0 "s_register_operand" "")
+-	(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
++	(if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
+ 			 (match_operand:DF 2 "s_register_operand" "")
+ 			 (match_operand:DF 3 "arm_float_add_operand" "")))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-09-15 09:45:31 +0000
++++ new/gcc/config/arm/predicates.md	2011-10-03 09:47:33 +0000
+@@ -242,11 +242,15 @@
+ 
+ ;; True for integer comparisons and, if FP is active, for comparisons
+ ;; other than LTGT or UNEQ.
++(define_special_predicate "expandable_comparison_operator"
++  (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
++	       unordered,ordered,unlt,unle,unge,ungt"))
++
++;; Likewise, but only accept comparisons that are directly supported
++;; by ARM condition codes.
+ (define_special_predicate "arm_comparison_operator"
+-  (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
+-       (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
+-			 && (TARGET_FPA || TARGET_VFP)")
+-            (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
++  (and (match_operand 0 "expandable_comparison_operator")
++       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
+ 
+ (define_special_predicate "lt_ge_comparison_operator"
+   (match_code "lt,ge"))
+
+=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49030.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49030.c	2011-10-03 09:46:40 +0000
+@@ -0,0 +1,19 @@
++void
++sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
++		       unsigned long dst_skip)
++{
++  long long y;
++  while (nsamples--)
++    {
++      y = (long long) (*src * 8388608.0f) << 8;
++      if (y > 2147483647) {
++	*(int *) dst = 2147483647;
++      } else if (y < -2147483647 - 1) {
++	*(int *) dst = -2147483647 - 1;
++      } else {
++	*(int *) dst = (int) y;
++      }
++      dst += dst_skip;
++      src++;
++    }
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/cmp-1.c'
+--- old/gcc/testsuite/gcc.target/arm/cmp-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/cmp-1.c	2011-10-03 09:47:33 +0000
+@@ -0,0 +1,37 @@
++/* { dg-do compile } */
++/* { dg-options "-O" } */
++/* { dg-final { scan-assembler-not "\tbl\t" } } */
++/* { dg-final { scan-assembler-not "__aeabi" } } */
++int x, y;
++
++#define TEST_EXPR(NAME, ARGS, EXPR)			\
++  int NAME##1 ARGS { return (EXPR); }			\
++  int NAME##2 ARGS { return !(EXPR); }			\
++  int NAME##3 ARGS { return (EXPR) ? x : y; }		\
++  void NAME##4 ARGS { if (EXPR) x++; }			\
++  void NAME##5 ARGS { if (!(EXPR)) x++; }
++
++#define TEST(NAME, TYPE, OPERATOR) \
++  TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2)	\
++  TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2)	\
++  TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2)	\
++  TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
++  TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100)		\
++  TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
++
++#define TEST_OP(NAME, OPERATOR) \
++  TEST (sc_##NAME, signed char, OPERATOR)		\
++  TEST (uc_##NAME, unsigned char, OPERATOR)		\
++  TEST (ss_##NAME, short, OPERATOR)			\
++  TEST (us_##NAME, unsigned short, OPERATOR)		\
++  TEST (si_##NAME, int, OPERATOR)			\
++  TEST (ui_##NAME, unsigned int, OPERATOR)		\
++  TEST (sll_##NAME, long long, OPERATOR)		\
++  TEST (ull_##NAME, unsigned long long, OPERATOR)
++
++TEST_OP (eq, ==)
++TEST_OP (ne, !=)
++TEST_OP (lt, <)
++TEST_OP (gt, >)
++TEST_OP (le, <=)
++TEST_OP (ge, >=)
+
+=== added file 'gcc/testsuite/gcc.target/arm/cmp-2.c'
+--- old/gcc/testsuite/gcc.target/arm/cmp-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/cmp-2.c	2011-10-03 09:47:33 +0000
+@@ -0,0 +1,49 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
++/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
++/* { dg-final { scan-assembler-not "\tbl\t" } } */
++/* { dg-final { scan-assembler-not "__aeabi" } } */
++int x, y;
++
++#define EQ(X, Y) ((X) == (Y))
++#define NE(X, Y) ((X) != (Y))
++#define LT(X, Y) ((X) < (Y))
++#define GT(X, Y) ((X) > (Y))
++#define LE(X, Y) ((X) <= (Y))
++#define GE(X, Y) ((X) >= (Y))
++
++#define TEST_EXPR(NAME, ARGS, EXPR)			\
++  int NAME##1 ARGS { return (EXPR); }			\
++  int NAME##2 ARGS { return !(EXPR); }			\
++  int NAME##3 ARGS { return (EXPR) ? x : y; }		\
++  void NAME##4 ARGS { if (EXPR) x++; }			\
++  void NAME##5 ARGS { if (!(EXPR)) x++; }
++
++#define TEST(NAME, TYPE, OPERATOR) \
++  TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2))		\
++  TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2))	\
++  TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2))	\
++  TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2))	\
++  TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100))			\
++  TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
++
++#define TEST_OP(NAME, OPERATOR) \
++  TEST (f_##NAME, float, OPERATOR)		\
++  TEST (d_##NAME, double, OPERATOR)		\
++  TEST (ld_##NAME, long double, OPERATOR)
++
++TEST_OP (eq, EQ)
++TEST_OP (ne, NE)
++TEST_OP (lt, LT)
++TEST_OP (gt, GT)
++TEST_OP (le, LE)
++TEST_OP (ge, GE)
++TEST_OP (blt, __builtin_isless)
++TEST_OP (bgt, __builtin_isgreater)
++TEST_OP (ble, __builtin_islessequal)
++TEST_OP (bge, __builtin_isgreaterequal)
++/* This one should be expanded into separate ordered and equality
++   comparisons.  */
++TEST_OP (blg, __builtin_islessgreater)
++TEST_OP (bun, __builtin_isunordered)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch
new file mode 100644
index 0000000000..4a886ce56d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch
@@ -0,0 +1,378 @@
+2011-10-06  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-09-25  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-data-ref.c (dr_analyze_innermost): Add new argument.
+	Allow not simple iv if analyzing basic block.
+	(create_data_ref): Update call to dr_analyze_innermost.
+	(stmt_with_adjacent_zero_store_dr_p, ref_base_address): Likewise.
+	* tree-loop-distribution.c (generate_memset_zero): Likewise.
+	* tree-predcom.c (find_looparound_phi): Likewise.
+	* tree-data-ref.h (dr_analyze_innermost): Add new argument.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-24.c: New.
+
+
+	2011-09-15  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Allow
+	read-after-read dependencies in basic block SLP.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-25.c: New.
+
+
+	2011-04-21  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* tree-vect-data-refs.c (vect_drs_dependent_in_basic_block): Use
+	operand_equal_p to compare DR_BASE_ADDRESSes.
+	(vect_check_interleaving): Likewise.
+
+	gcc/testsuite/
+	* gcc.dg/vect/vect-119.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-24.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-24.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-24.c	2011-10-02 08:43:10 +0000
+@@ -0,0 +1,59 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define A 3
++#define N 256
++
++short src[N], dst[N];
++
++void foo (short * __restrict__ dst, short * __restrict__ src, int h,
++          int stride, int dummy)
++{
++  int i;
++  h /= 8;
++  for (i = 0; i < h; i++)
++    {
++      dst[0] += A*src[0];
++      dst[1] += A*src[1];
++      dst[2] += A*src[2];
++      dst[3] += A*src[3];
++      dst[4] += A*src[4];
++      dst[5] += A*src[5];
++      dst[6] += A*src[6];
++      dst[7] += A*src[7];
++      dst += stride;
++      src += stride;
++      if (dummy == 32)
++        abort ();
++    }
++}
++
++
++int main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      dst[i] = 0;
++      src[i] = i;
++    }
++
++  foo (dst, src, N, 8, 0);
++
++  for (i = 0; i < N; i++)
++    {
++      if (dst[i] != A * i)
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-25.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-25.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-25.c	2011-10-02 08:43:10 +0000
+@@ -0,0 +1,59 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define A 3
++#define B 4
++#define N 256
++
++short src[N], dst[N];
++
++void foo (short * __restrict__ dst, short * __restrict__ src, int h, int stride, int dummy)
++{
++  int i;
++  h /= 16;
++  for (i = 0; i < h; i++)
++    {
++      dst[0] += A*src[0] + src[stride];
++      dst[1] += A*src[1] + src[1+stride];
++      dst[2] += A*src[2] + src[2+stride];
++      dst[3] += A*src[3] + src[3+stride];
++      dst[4] += A*src[4] + src[4+stride];
++      dst[5] += A*src[5] + src[5+stride];
++      dst[6] += A*src[6] + src[6+stride];
++      dst[7] += A*src[7] + src[7+stride];
++      dst += 8;
++      src += 8;
++      if (dummy == 32)
++        abort ();
++   }
++}
++
++
++int main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++       dst[i] = 0;
++       src[i] = i;
++    }
++
++  foo (dst, src, N, 8, 0);
++
++  for (i = 0; i < N/2; i++)
++    {
++      if (dst[i] != A * i + i + 8)
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-119.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-119.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-119.c	2011-10-02 08:43:10 +0000
+@@ -0,0 +1,28 @@
++/* { dg-do compile } */
++
++#define OUTER 32
++#define INNER 40
++
++static unsigned int
++bar (const unsigned int x[INNER][2], unsigned int sum)
++{
++  int i;
++
++  for (i = 0; i < INNER; i++)
++    sum += x[i][0] * x[i][0] + x[i][1] * x[i][1];
++  return sum;
++}
++
++unsigned int foo (const unsigned int x[OUTER][INNER][2])
++{
++  int i;
++  unsigned int sum;
++
++  sum = 0.0f;
++  for (i = 0; i < OUTER; i++)
++    sum = bar (x[i], sum);
++  return sum;
++}
++
++/* { dg-final { scan-tree-dump-times "Detected interleaving of size 2" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/tree-data-ref.c'
+--- old/gcc/tree-data-ref.c	2011-05-26 14:27:33 +0000
++++ new/gcc/tree-data-ref.c	2011-10-02 08:43:10 +0000
+@@ -721,11 +721,11 @@
+ }
+ 
+ /* Analyzes the behavior of the memory reference DR in the innermost loop or
+-   basic block that contains it. Returns true if analysis succeed or false
++   basic block that contains it.  Returns true if analysis succeed or false
+    otherwise.  */
+ 
+ bool
+-dr_analyze_innermost (struct data_reference *dr)
++dr_analyze_innermost (struct data_reference *dr, struct loop *nest)
+ {
+   gimple stmt = DR_STMT (dr);
+   struct loop *loop = loop_containing_stmt (stmt);
+@@ -768,14 +768,25 @@
+     }
+   else
+     base = build_fold_addr_expr (base);
++
+   if (in_loop)
+     {
+       if (!simple_iv (loop, loop_containing_stmt (stmt), base, &base_iv,
+                       false))
+         {
+-          if (dump_file && (dump_flags & TDF_DETAILS))
+-	    fprintf (dump_file, "failed: evolution of base is not affine.\n");
+-          return false;
++          if (nest)
++            {
++              if (dump_file && (dump_flags & TDF_DETAILS))
++                fprintf (dump_file, "failed: evolution of base is not"
++                                    " affine.\n");
++              return false;
++            }
++          else
++            {
++              base_iv.base = base;
++              base_iv.step = ssize_int (0);
++              base_iv.no_overflow = true;
++            }
+         }
+     }
+   else
+@@ -800,10 +811,18 @@
+       else if (!simple_iv (loop, loop_containing_stmt (stmt),
+                            poffset, &offset_iv, false))
+         {
+-          if (dump_file && (dump_flags & TDF_DETAILS))
+-            fprintf (dump_file, "failed: evolution of offset is not"
+-                                " affine.\n");
+-          return false;
++          if (nest)
++            {
++              if (dump_file && (dump_flags & TDF_DETAILS))
++                fprintf (dump_file, "failed: evolution of offset is not"
++                                    " affine.\n");
++              return false;
++            }
++          else
++            {
++              offset_iv.base = poffset;
++              offset_iv.step = ssize_int (0);
++            }
+         }
+     }
+ 
+@@ -967,7 +986,7 @@
+   DR_REF (dr) = memref;
+   DR_IS_READ (dr) = is_read;
+ 
+-  dr_analyze_innermost (dr);
++  dr_analyze_innermost (dr, nest);
+   dr_analyze_indices (dr, nest, loop);
+   dr_analyze_alias (dr);
+ 
+@@ -5185,7 +5204,7 @@
+   DR_STMT (dr) = stmt;
+   DR_REF (dr) = op0;
+ 
+-  res = dr_analyze_innermost (dr)
++  res = dr_analyze_innermost (dr, loop_containing_stmt (stmt))
+     && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0));
+ 
+   free_data_ref (dr);
+@@ -5225,7 +5244,7 @@
+ 
+   DR_STMT (dr) = stmt;
+   DR_REF (dr) = *ref->pos;
+-  dr_analyze_innermost (dr);
++  dr_analyze_innermost (dr, loop_containing_stmt (stmt));
+   base_address = DR_BASE_ADDRESS (dr);
+ 
+   if (!base_address)
+
+=== modified file 'gcc/tree-data-ref.h'
+--- old/gcc/tree-data-ref.h	2011-03-27 09:38:18 +0000
++++ new/gcc/tree-data-ref.h	2011-10-02 08:43:10 +0000
+@@ -386,7 +386,7 @@
+ DEF_VEC_ALLOC_O (data_ref_loc, heap);
+ 
+ bool get_references_in_stmt (gimple, VEC (data_ref_loc, heap) **);
+-bool dr_analyze_innermost (struct data_reference *);
++bool dr_analyze_innermost (struct data_reference *, struct loop *);
+ extern bool compute_data_dependences_for_loop (struct loop *, bool,
+ 					       VEC (loop_p, heap) **,
+ 					       VEC (data_reference_p, heap) **,
+
+=== modified file 'gcc/tree-loop-distribution.c'
+--- old/gcc/tree-loop-distribution.c	2011-05-11 13:07:54 +0000
++++ new/gcc/tree-loop-distribution.c	2011-10-02 08:43:10 +0000
+@@ -267,7 +267,7 @@
+ 
+   DR_STMT (dr) = stmt;
+   DR_REF (dr) = op0;
+-  res = dr_analyze_innermost (dr);
++  res = dr_analyze_innermost (dr, loop_containing_stmt (stmt));
+   gcc_assert (res && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0)));
+ 
+   nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
+
+=== modified file 'gcc/tree-predcom.c'
+--- old/gcc/tree-predcom.c	2011-02-11 14:19:44 +0000
++++ new/gcc/tree-predcom.c	2011-10-02 08:43:10 +0000
+@@ -1114,7 +1114,7 @@
+   memset (&init_dr, 0, sizeof (struct data_reference));
+   DR_REF (&init_dr) = init_ref;
+   DR_STMT (&init_dr) = phi;
+-  if (!dr_analyze_innermost (&init_dr))
++  if (!dr_analyze_innermost (&init_dr, loop))
+     return NULL;
+ 
+   if (!valid_initializer_p (&init_dr, ref->distance + 1, root->ref))
+
+=== modified file 'gcc/tree-vect-data-refs.c'
+--- old/gcc/tree-vect-data-refs.c	2011-07-04 11:13:51 +0000
++++ new/gcc/tree-vect-data-refs.c	2011-10-02 08:43:10 +0000
+@@ -353,11 +353,7 @@
+ 
+   /* Check that the data-refs have same bases and offsets.  If not, we can't
+      determine if they are dependent.  */
+-  if ((DR_BASE_ADDRESS (dra) != DR_BASE_ADDRESS (drb)
+-       && (TREE_CODE (DR_BASE_ADDRESS (dra)) != ADDR_EXPR
+-           || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
+-           || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
+-           != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
++  if (!operand_equal_p (DR_BASE_ADDRESS (dra), DR_BASE_ADDRESS (drb), 0)
+       || !dr_equal_offsets_p (dra, drb))
+     return true;
+ 
+@@ -403,11 +399,7 @@
+ 
+   /* Check that the data-refs have same first location (except init) and they
+      are both either store or load (not load and store).  */
+-  if ((DR_BASE_ADDRESS (dra) != DR_BASE_ADDRESS (drb)
+-       && (TREE_CODE (DR_BASE_ADDRESS (dra)) != ADDR_EXPR
+-	   || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
+-	   || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
+-	   != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
++  if (!operand_equal_p (DR_BASE_ADDRESS (dra), DR_BASE_ADDRESS (drb), 0)
+       || !dr_equal_offsets_p (dra, drb)
+       || !tree_int_cst_compare (DR_INIT (dra), DR_INIT (drb))
+       || DR_IS_READ (dra) != DR_IS_READ (drb))
+@@ -615,6 +607,11 @@
+       if (vect_check_interleaving (dra, drb))
+          return false;
+ 
++      /* Read-read is OK (we need this check here, after checking for
++         interleaving).  */
++      if (DR_IS_READ (dra) && DR_IS_READ (drb))
++        return false;
++
+       if (vect_print_dump_info (REPORT_DR_DETAILS))
+         {
+           fprintf (vect_dump, "can't determine dependence between ");
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch
new file mode 100644
index 0000000000..f25a37858d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch
@@ -0,0 +1,240 @@
+2011-10-06  Ira Rosen  <ira.rosen@linaro.org>
+ 
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-26.c: Simplify to make the basic block
+	vectorizable.
+
+	Backport from mainline:
+
+	2011-09-25  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-slp.c (vect_slp_analyze_bb_1): Split out core part
+	of vect_analyze_bb here.
+	(vect_analyze_bb): Loop over vector sizes calling vect_analyze_bb_1.
+
+	gcc/testsuite/
+	* lib/target-supports.exp (check_effective_target_vect64): New.
+	* gcc.dg/vect/bb-slp-11.c: Expect the error message twice in case
+	of multiple vector sizes.
+	* gcc.dg/vect/bb-slp-26.c: New.
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/bb-slp-11.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-11.c	2010-11-22 12:16:52 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-11.c	2011-10-02 10:40:34 +0000
+@@ -49,6 +49,7 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 0 "slp" } } */
+-/* { dg-final { scan-tree-dump-times "SLP with multiple types" 1 "slp" } } */
++/* { dg-final { scan-tree-dump-times "SLP with multiple types" 1 "slp" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "SLP with multiple types" 2 "slp" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "slp" } } */
+   
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-26.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-26.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-26.c	2011-10-02 10:40:34 +0000
+@@ -0,0 +1,60 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define A 3
++#define B 4
++#define N 256
++
++char src[N], dst[N];
++
++void foo (char * __restrict__ dst, char * __restrict__ src, int h,
++          int stride, int dummy)
++{
++  int i;
++  h /= 16;
++  for (i = 0; i < h; i++)
++    {
++      dst[0] += A*src[0];
++      dst[1] += A*src[1];
++      dst[2] += A*src[2];
++      dst[3] += A*src[3];
++      dst[4] += A*src[4];
++      dst[5] += A*src[5];
++      dst[6] += A*src[6];
++      dst[7] += A*src[7];
++      dst += 8;
++      src += 8;
++      if (dummy == 32)
++        abort ();
++   }
++}
++
++
++int main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++       dst[i] = 0;
++       src[i] = i/8;
++    }
++
++  foo (dst, src, N, 8, 0);
++
++  for (i = 0; i < N/2; i++)
++    {
++      if (dst[i] != A * src[i])
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect64 } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-09-20 07:54:28 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-10-02 10:40:34 +0000
+@@ -3283,6 +3283,24 @@
+     return $et_vect_multiple_sizes_saved
+ }
+ 
++# Return 1 if the target supports vectors of 64 bits.
++
++proc check_effective_target_vect64 { } {
++    global et_vect64
++
++    if [info exists et_vect64_saved] {
++        verbose "check_effective_target_vect64: using cached result" 2
++    } else {
++        set et_vect64_saved 0
++        if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
++           set et_vect64_saved 1
++        }
++    }
++
++    verbose "check_effective_target_vect64: returning $et_vect64_saved" 2
++    return $et_vect64_saved
++}
++
+ # Return 1 if the target supports section-anchors
+ 
+ proc check_effective_target_section_anchors { } {
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-07-06 12:04:10 +0000
++++ new/gcc/tree-vect-slp.c	2011-10-02 10:40:34 +0000
+@@ -1664,42 +1664,18 @@
+ 
+ /* Check if the basic block can be vectorized.  */
+ 
+-bb_vec_info
+-vect_slp_analyze_bb (basic_block bb)
++static bb_vec_info
++vect_slp_analyze_bb_1 (basic_block bb)
+ {
+   bb_vec_info bb_vinfo;
+   VEC (ddr_p, heap) *ddrs;
+   VEC (slp_instance, heap) *slp_instances;
+   slp_instance instance;
+-  int i, insns = 0;
+-  gimple_stmt_iterator gsi;
++  int i;
+   int min_vf = 2;
+   int max_vf = MAX_VECTORIZATION_FACTOR;
+   bool data_dependence_in_bb = false;
+ 
+-  current_vector_size = 0;
+-
+-  if (vect_print_dump_info (REPORT_DETAILS))
+-    fprintf (vect_dump, "===vect_slp_analyze_bb===\n");
+-
+-  for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
+-    {
+-      gimple stmt = gsi_stmt (gsi);
+-      if (!is_gimple_debug (stmt)
+-	  && !gimple_nop_p (stmt)
+-	  && gimple_code (stmt) != GIMPLE_LABEL)
+-	insns++;
+-    }
+-
+-  if (insns > PARAM_VALUE (PARAM_SLP_MAX_INSNS_IN_BB))
+-    {
+-      if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
+-        fprintf (vect_dump, "not vectorized: too many instructions in basic "
+-                            "block.\n");
+-
+-      return NULL;
+-    }
+-
+   bb_vinfo = new_bb_vec_info (bb);
+   if (!bb_vinfo)
+     return NULL;
+@@ -1819,6 +1795,61 @@
+ }
+ 
+ 
++bb_vec_info
++vect_slp_analyze_bb (basic_block bb)
++{
++  bb_vec_info bb_vinfo;
++  int insns = 0;
++  gimple_stmt_iterator gsi;
++  unsigned int vector_sizes;
++
++  if (vect_print_dump_info (REPORT_DETAILS))
++    fprintf (vect_dump, "===vect_slp_analyze_bb===\n");
++
++  for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
++    {
++      gimple stmt = gsi_stmt (gsi);
++      if (!is_gimple_debug (stmt)
++          && !gimple_nop_p (stmt)
++          && gimple_code (stmt) != GIMPLE_LABEL)
++        insns++;
++    }
++
++  if (insns > PARAM_VALUE (PARAM_SLP_MAX_INSNS_IN_BB))
++    {
++      if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
++        fprintf (vect_dump, "not vectorized: too many instructions in basic "
++                            "block.\n");
++
++      return NULL;
++    }
++
++  /* Autodetect first vector size we try.  */
++  current_vector_size = 0;
++  vector_sizes = targetm.vectorize.autovectorize_vector_sizes ();
++
++  while (1)
++    {
++      bb_vinfo = vect_slp_analyze_bb_1 (bb);
++      if (bb_vinfo)
++        return bb_vinfo;
++
++      destroy_bb_vec_info (bb_vinfo);
++
++      vector_sizes &= ~current_vector_size;
++      if (vector_sizes == 0
++          || current_vector_size == 0)
++        return NULL;
++
++      /* Try the next biggest vector size.  */
++      current_vector_size = 1 << floor_log2 (vector_sizes);
++      if (vect_print_dump_info (REPORT_DETAILS))
++        fprintf (vect_dump, "***** Re-trying analysis with "
++                 "vector size %d\n", current_vector_size);
++    }
++}
++
++
+ /* SLP costs are calculated according to SLP instance unrolling factor (i.e.,
+    the number of created vector stmts depends on the unrolling factor).
+    However, the actual number of vector stmts for every SLP node depends on
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch
new file mode 100644
index 0000000000..13e6fd26e5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch
@@ -0,0 +1,124 @@
+2011-10-13  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+
+	2011-10-07  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/predicates.md (shift_amount_operand): Remove constant
+	range check.
+	(shift_operator): Check range of constants for all shift operators.
+
+	gcc/testsuite/
+	* gcc.dg/pr50193-1.c: New file.
+	* gcc.target/arm/shiftable.c: New file.
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-10-03 09:47:33 +0000
++++ new/gcc/config/arm/predicates.md	2011-10-10 11:43:28 +0000
+@@ -129,11 +129,12 @@
+   (ior (match_operand 0 "arm_rhs_operand")
+        (match_operand 0 "memory_operand")))
+ 
++;; This doesn't have to do much because the constant is already checked
++;; in the shift_operator predicate.
+ (define_predicate "shift_amount_operand"
+   (ior (and (match_test "TARGET_ARM")
+ 	    (match_operand 0 "s_register_operand"))
+-       (and (match_operand 0 "const_int_operand")
+-	    (match_test "INTVAL (op) > 0"))))
++       (match_operand 0 "const_int_operand")))
+ 
+ (define_predicate "arm_add_operand"
+   (ior (match_operand 0 "arm_rhs_operand")
+@@ -219,13 +220,20 @@
+        (match_test "mode == GET_MODE (op)")))
+ 
+ ;; True for shift operators.
++;; Notes:
++;;  * mult is only permitted with a constant shift amount
++;;  * patterns that permit register shift amounts only in ARM mode use
++;;    shift_amount_operand, patterns that always allow registers do not,
++;;    so we don't have to worry about that sort of thing here.
+ (define_special_predicate "shift_operator"
+   (and (ior (ior (and (match_code "mult")
+ 		      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
+ 		 (and (match_code "rotate")
+ 		      (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
+ 				   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
+-	    (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
++	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
++		 (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
++			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ ;; True for MULT, to identify which variant of shift_operator is in use.
+
+=== added file 'gcc/testsuite/gcc.target/arm/shiftable.c'
+--- old/gcc/testsuite/gcc.target/arm/shiftable.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/shiftable.c	2011-10-10 11:43:28 +0000
+@@ -0,0 +1,63 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++/* { dg-require-effective-target arm32 } */
++
++/* ARM has shift-and-alu insns.  Depending on the ALU op GCC represents some
++   of these as a left shift, others as a multiply.  Check that we match the
++    right one.  */
++
++int
++plus (int a, int b)
++{
++  return (a * 64) + b;
++}
++
++/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
++
++int
++minus (int a, int b)
++{
++  return a - (b * 64);
++}
++
++/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
++
++int
++ior (int a, int b)
++{
++  return (a * 64) | b;
++}
++
++/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
++
++int
++xor (int a, int b)
++{
++  return (a * 64) ^ b;
++}
++
++/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
++
++int
++and (int a, int b)
++{
++  return (a * 64) & b;
++}
++
++/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
++
++int
++rsb (int a, int b)
++{
++  return (a * 64) - b;
++}
++
++/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
++
++int
++mvn (int a, int b)
++{
++  return ~(a * 64);
++}
++
++/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch
new file mode 100644
index 0000000000..6642f8a667
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch
@@ -0,0 +1,362 @@
+2011-10-16  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-09-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-stmts.c (vectorizable_type_demotion): Handle basic block
+	vectorization.
+	(vectorizable_type_promotion): Likewise.
+	(vect_analyze_stmt): Call vectorizable_type_demotion and
+	vectorizable_type_promotion for basic blocks.
+	(supportable_widening_operation): Don't assume loop vectorization.
+	* tree-vect-slp.c (vect_build_slp_tree): Allow multiple types for
+	basic blocks.  Update vectorization factor for basic block
+	vectorization.
+	(vect_analyze_slp_instance): Allow multiple types for basic block
+	vectorization.  Recheck unrolling factor after construction of SLP
+	instance.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-11.c: Expect to get vectorized with 64-bit
+	vectors.
+	* gcc.dg/vect/bb-slp-27.c: New.
+	* gcc.dg/vect/bb-slp-28.c: New.
+
+
+	2011-10-04  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/testsuite/
+	* lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
+	Make et_vect_multiple_sizes_saved global.
+	(check_effective_target_vect64): Make et_vect64_saved global.
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/bb-slp-11.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-11.c	2011-10-02 10:40:34 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-11.c	2011-10-06 11:08:08 +0000
+@@ -48,8 +48,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 0 "slp" } } */
+-/* { dg-final { scan-tree-dump-times "SLP with multiple types" 1 "slp" { xfail vect_multiple_sizes } } } */
+-/* { dg-final { scan-tree-dump-times "SLP with multiple types" 2 "slp" { target vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect64 } } } */
+ /* { dg-final { cleanup-tree-dump "slp" } } */
+   
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-27.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-27.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-27.c	2011-10-06 11:08:08 +0000
+@@ -0,0 +1,49 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define A 3
++#define N 16
++
++short src[N], dst[N];
++
++void foo (int a)
++{
++  dst[0] += a*src[0];
++  dst[1] += a*src[1];
++  dst[2] += a*src[2];
++  dst[3] += a*src[3];
++  dst[4] += a*src[4];
++  dst[5] += a*src[5];
++  dst[6] += a*src[6];
++  dst[7] += a*src[7];
++}
++
++
++int main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      dst[i] = 0;
++      src[i] = i;
++    }
++
++  foo (A);
++
++  for (i = 0; i < 8; i++)
++    {
++      if (dst[i] != A * i)
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_int_mult && { vect_unpack && vect_pack_trunc } } } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-28.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-28.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-28.c	2011-10-06 11:08:08 +0000
+@@ -0,0 +1,71 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define A 300
++#define N 16
++
++char src[N];
++short dst[N];
++short src1[N], dst1[N];
++
++void foo (int a)
++{
++  dst[0] = (short) (a * (int) src[0]);
++  dst[1] = (short) (a * (int) src[1]);
++  dst[2] = (short) (a * (int) src[2]);
++  dst[3] = (short) (a * (int) src[3]);
++  dst[4] = (short) (a * (int) src[4]);
++  dst[5] = (short) (a * (int) src[5]);
++  dst[6] = (short) (a * (int) src[6]);
++  dst[7] = (short) (a * (int) src[7]);
++  dst[8] = (short) (a * (int) src[8]);
++  dst[9] = (short) (a * (int) src[9]);
++  dst[10] = (short) (a * (int) src[10]);
++  dst[11] = (short) (a * (int) src[11]);
++  dst[12] = (short) (a * (int) src[12]);
++  dst[13] = (short) (a * (int) src[13]);
++  dst[14] = (short) (a * (int) src[14]);
++  dst[15] = (short) (a * (int) src[15]);
++
++  dst1[0] += src1[0];
++  dst1[1] += src1[1];
++  dst1[2] += src1[2];
++  dst1[3] += src1[3];
++  dst1[4] += src1[4];
++  dst1[5] += src1[5];
++  dst1[6] += src1[6];
++  dst1[7] += src1[7];
++}
++
++
++int main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      dst[i] = 2;
++      dst1[i] = 0;
++      src[i] = i;
++      src1[i] = i+2;
++    }
++
++  foo (A);
++
++  for (i = 0; i < N; i++)
++    {
++      if (dst[i] != A * i
++          || (i < N/2 && dst1[i] != i + 2))
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_int_mult &&  { vect_pack_trunc && vect_unpack } } } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-10-02 10:40:34 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-10-06 11:08:08 +0000
+@@ -3268,7 +3268,7 @@
+ # Return 1 if the target supports multiple vector sizes
+ 
+ proc check_effective_target_vect_multiple_sizes { } {
+-    global et_vect_multiple_sizes
++    global et_vect_multiple_sizes_saved
+ 
+     if [info exists et_vect_multiple_sizes_saved] {
+         verbose "check_effective_target_vect_multiple_sizes: using cached result" 2
+@@ -3286,7 +3286,7 @@
+ # Return 1 if the target supports vectors of 64 bits.
+ 
+ proc check_effective_target_vect64 { } {
+-    global et_vect64
++    global et_vect64_saved
+ 
+     if [info exists et_vect64_saved] {
+         verbose "check_effective_target_vect64: using cached result" 2
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-10-02 10:40:34 +0000
++++ new/gcc/tree-vect-slp.c	2011-10-06 11:08:08 +0000
+@@ -386,20 +386,15 @@
+           return false;
+         }
+ 
+-      ncopies = vectorization_factor / TYPE_VECTOR_SUBPARTS (vectype);
+-      if (ncopies != 1)
+-        {
+-	  if (vect_print_dump_info (REPORT_SLP))
+-            fprintf (vect_dump, "SLP with multiple types ");
+-
+-          /* FORNOW: multiple types are unsupported in BB SLP.  */
+-	  if (bb_vinfo)
+-	    return false;
+-        }
+-
+       /* In case of multiple types we need to detect the smallest type.  */
+       if (*max_nunits < TYPE_VECTOR_SUBPARTS (vectype))
+-        *max_nunits = TYPE_VECTOR_SUBPARTS (vectype);
++        {
++          *max_nunits = TYPE_VECTOR_SUBPARTS (vectype);
++          if (bb_vinfo)
++            vectorization_factor = *max_nunits;
++        }
++
++      ncopies = vectorization_factor / TYPE_VECTOR_SUBPARTS (vectype);
+ 
+       if (is_gimple_call (stmt))
+ 	rhs_code = CALL_EXPR;
+@@ -1183,7 +1178,6 @@
+   if (loop_vinfo)
+     vectorization_factor = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
+   else
+-    /* No multitypes in BB SLP.  */
+     vectorization_factor = nunits;
+ 
+   /* Calculate the unrolling factor.  */
+@@ -1246,16 +1240,23 @@
+ 			   &max_nunits, &load_permutation, &loads,
+ 			   vectorization_factor))
+     {
++      /* Calculate the unrolling factor based on the smallest type.  */
++      if (max_nunits > nunits)
++        unrolling_factor = least_common_multiple (max_nunits, group_size)
++                           / group_size;
++
++      if (unrolling_factor != 1 && !loop_vinfo)
++        {
++          if (vect_print_dump_info (REPORT_SLP))
++            fprintf (vect_dump, "Build SLP failed: unrolling required in basic"
++                               " block SLP");
++          return false;
++        }
++
+       /* Create a new SLP instance.  */
+       new_instance = XNEW (struct _slp_instance);
+       SLP_INSTANCE_TREE (new_instance) = node;
+       SLP_INSTANCE_GROUP_SIZE (new_instance) = group_size;
+-      /* Calculate the unrolling factor based on the smallest type in the
+-         loop.  */
+-      if (max_nunits > nunits)
+-        unrolling_factor = least_common_multiple (max_nunits, group_size)
+-                           / group_size;
+-
+       SLP_INSTANCE_UNROLLING_FACTOR (new_instance) = unrolling_factor;
+       SLP_INSTANCE_OUTSIDE_OF_LOOP_COST (new_instance) = outside_cost;
+       SLP_INSTANCE_INSIDE_OF_LOOP_COST (new_instance) = inside_cost;
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-10-04 08:57:25 +0000
++++ new/gcc/tree-vect-stmts.c	2011-10-16 12:16:07 +0000
+@@ -3081,11 +3081,9 @@
+   VEC (tree, heap) *vec_oprnds0 = NULL;
+   VEC (tree, heap) *vec_dsts = NULL, *interm_types = NULL, *tmp_vec_dsts = NULL;
+   tree last_oprnd, intermediate_type;
+-
+-  /* FORNOW: not supported by basic block SLP vectorization.  */
+-  gcc_assert (loop_vinfo);
+-
+-  if (!STMT_VINFO_RELEVANT_P (stmt_info))
++  bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
++
++  if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
+     return false;
+ 
+   if (STMT_VINFO_DEF_TYPE (stmt_info) != vect_internal_def)
+@@ -3113,7 +3111,7 @@
+ 	     && SCALAR_FLOAT_TYPE_P (TREE_TYPE (op0))
+ 	     && CONVERT_EXPR_CODE_P (code))))
+     return false;
+-  if (!vect_is_simple_use_1 (op0, loop_vinfo, NULL,
++  if (!vect_is_simple_use_1 (op0, loop_vinfo, bb_vinfo,
+ 			     &def_stmt, &def, &dt[0], &vectype_in))
+     {
+       if (vect_print_dump_info (REPORT_DETAILS))
+@@ -3360,11 +3358,9 @@
+   int multi_step_cvt = 0;
+   VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
+   VEC (tree, heap) *vec_dsts = NULL, *interm_types = NULL, *tmp_vec_dsts = NULL;
+-
+-  /* FORNOW: not supported by basic block SLP vectorization.  */
+-  gcc_assert (loop_vinfo);
+-
+-  if (!STMT_VINFO_RELEVANT_P (stmt_info))
++  bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
++
++  if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
+     return false;
+ 
+   if (STMT_VINFO_DEF_TYPE (stmt_info) != vect_internal_def)
+@@ -3393,7 +3389,7 @@
+ 	     && SCALAR_FLOAT_TYPE_P (TREE_TYPE (op0))
+ 	     && CONVERT_EXPR_CODE_P (code))))
+     return false;
+-  if (!vect_is_simple_use_1 (op0, loop_vinfo, NULL,
++  if (!vect_is_simple_use_1 (op0, loop_vinfo, bb_vinfo,
+ 			     &def_stmt, &def, &dt[0], &vectype_in))
+     {
+       if (vect_print_dump_info (REPORT_DETAILS))
+@@ -5153,7 +5149,9 @@
+     else
+       {
+         if (bb_vinfo)
+-          ok = (vectorizable_shift (stmt, NULL, NULL, node)
++          ok = (vectorizable_type_promotion (stmt, NULL, NULL, node)
++                || vectorizable_type_demotion (stmt, NULL, NULL, node)
++               || vectorizable_shift (stmt, NULL, NULL, node)
+                 || vectorizable_operation (stmt, NULL, NULL, node)
+                 || vectorizable_assignment (stmt, NULL, NULL, node)
+                 || vectorizable_load (stmt, NULL, NULL, node, NULL)
+@@ -5780,7 +5778,7 @@
+ {
+   stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_info);
+-  struct loop *vect_loop = LOOP_VINFO_LOOP (loop_info);
++  struct loop *vect_loop = NULL;
+   bool ordered_p;
+   enum machine_mode vec_mode;
+   enum insn_code icode1, icode2;
+@@ -5789,6 +5787,9 @@
+   tree wide_vectype = vectype_out;
+   enum tree_code c1, c2;
+ 
++  if (loop_info)
++    vect_loop = LOOP_VINFO_LOOP (loop_info);
++
+   /* The result of a vectorized widening operation usually requires two vectors
+      (because the widened results do not fit int one vector). The generated
+      vector results would normally be expected to be generated in the same
+@@ -5809,7 +5810,8 @@
+      iterations in parallel).  We therefore don't allow to change the order
+      of the computation in the inner-loop during outer-loop vectorization.  */
+ 
+-   if (STMT_VINFO_RELEVANT (stmt_info) == vect_used_by_reduction
++   if (vect_loop
++       && STMT_VINFO_RELEVANT (stmt_info) == vect_used_by_reduction
+        && !nested_in_vect_loop_p (vect_loop, stmt))
+      ordered_p = false;
+    else
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch
new file mode 100644
index 0000000000..28caa40076
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch
@@ -0,0 +1,622 @@
+2011-10-17  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r178852:
+
+	2011-09-14  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_override_options): Add unaligned_access
+	support.
+	(arm_file_start): Emit attribute for unaligned access as appropriate.
+	* config/arm/arm.md (UNSPEC_UNALIGNED_LOAD)
+	(UNSPEC_UNALIGNED_STORE): Add constants for unspecs.
+	(insv, extzv): Add unaligned-access support.
+	(extv): Change to expander. Likewise.
+	(extzv_t1, extv_regsi): Add helpers.
+	(unaligned_loadsi, unaligned_loadhis, unaligned_loadhiu)
+	(unaligned_storesi, unaligned_storehi): New.
+	(*extv_reg): New (previous extv implementation).
+	* config/arm/arm.opt (munaligned_access): Add option.
+	* config/arm/constraints.md (Uw): New constraint.
+	* expmed.c (store_bit_field_1): Adjust bitfield numbering according
+	to size of access, not size of unit, when BITS_BIG_ENDIAN !=
+	BYTES_BIG_ENDIAN. Don't use bitfield accesses for
+	volatile accesses when -fstrict-volatile-bitfields is in effect.
+	(extract_bit_field_1): Likewise.
+
+	Backport from mainline r172697:
+
+	2011-04-19  Wei Guozhi  <carrot@google.com>
+
+	PR target/47855
+	gcc/
+	* config/arm/arm-protos.h (thumb1_legitimate_address_p): New prototype.
+	* config/arm/arm.c (thumb1_legitimate_address_p): Remove the static
+	linkage.
+	* config/arm/constraints.md (Uu): New constraint.
+	* config/arm/arm.md (*arm_movqi_insn): Compute attr "length".
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+Index: gcc-4_6-branch/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm-protos.h	2012-03-05 16:07:15.000000000 -0800
++++ gcc-4_6-branch/gcc/config/arm/arm-protos.h	2012-03-05 16:07:50.392936694 -0800
+@@ -59,6 +59,7 @@
+ 					   int);
+ extern rtx thumb_legitimize_reload_address (rtx *, enum machine_mode, int, int,
+ 					    int);
++extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int);
+ extern int arm_const_double_rtx (rtx);
+ extern int neg_const_double_rtx_ok_for_fpa (rtx);
+ extern int vfp3_const_double_rtx (rtx);
+Index: gcc-4_6-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.c	2012-03-05 16:07:15.000000000 -0800
++++ gcc-4_6-branch/gcc/config/arm/arm.c	2012-03-05 16:07:50.400936694 -0800
+@@ -2065,6 +2065,28 @@
+ 	fix_cm3_ldrd = 0;
+     }
+ 
++  /* Enable -munaligned-access by default for
++     - all ARMv6 architecture-based processors
++     - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
++
++     Disable -munaligned-access by default for
++     - all pre-ARMv6 architecture-based processors
++     - ARMv6-M architecture-based processors.  */
++
++  if (unaligned_access == 2)
++    {
++      if (arm_arch6 && (arm_arch_notm || arm_arch7))
++	unaligned_access = 1;
++      else
++	unaligned_access = 0;
++    }
++  else if (unaligned_access == 1
++	   && !(arm_arch6 && (arm_arch_notm || arm_arch7)))
++    {
++      warning (0, "target CPU does not support unaligned accesses");
++      unaligned_access = 0;
++    }
++
+   if (TARGET_THUMB1 && flag_schedule_insns)
+     {
+       /* Don't warn since it's on by default in -O2.  */
+@@ -6123,7 +6145,7 @@
+    addresses based on the frame pointer or arg pointer until the
+    reload pass starts.  This is so that eliminating such addresses
+    into stack based ones won't produce impossible code.  */
+-static int
++int
+ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
+ {
+   /* ??? Not clear if this is right.  Experiment.  */
+@@ -22251,6 +22273,10 @@
+ 	val = 6;
+       asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
+ 
++      /* Tag_CPU_unaligned_access.  */
++      asm_fprintf (asm_out_file, "\t.eabi_attribute 34, %d\n",
++		   unaligned_access);
++
+       /* Tag_ABI_FP_16bit_format.  */
+       if (arm_fp16_format)
+ 	asm_fprintf (asm_out_file, "\t.eabi_attribute 38, %d\n",
+Index: gcc-4_6-branch/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.md	2012-03-05 16:07:15.000000000 -0800
++++ gcc-4_6-branch/gcc/config/arm/arm.md	2012-03-05 16:09:26.284941314 -0800
+@@ -114,6 +114,10 @@
+                              ; another symbolic address.
+    (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
+    (UNSPEC_PIC_UNIFIED 29)  ; Create a common pic addressing form.
++   (UNSPEC_UNALIGNED_LOAD 30)  ; Used to represent ldr/ldrh instructions that access
++                               ; unaligned locations, on architectures which support
++                               ; that.
++   (UNSPEC_UNALIGNED_STORE 31) ; Same for str/strh.
+   ]
+ )
+ 
+@@ -2461,10 +2465,10 @@
+ ;;; this insv pattern, so this pattern needs to be reevalutated.
+ 
+ (define_expand "insv"
+-  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "")
+-                         (match_operand:SI 1 "general_operand" "")
+-                         (match_operand:SI 2 "general_operand" ""))
+-        (match_operand:SI 3 "reg_or_int_operand" ""))]
++  [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
++                      (match_operand 1 "general_operand" "")
++                      (match_operand 2 "general_operand" ""))
++        (match_operand 3 "reg_or_int_operand" ""))]
+   "TARGET_ARM || arm_arch_thumb2"
+   "
+   {
+@@ -2475,35 +2479,70 @@
+ 
+     if (arm_arch_thumb2)
+       {
+-	bool use_bfi = TRUE;
+-
+-	if (GET_CODE (operands[3]) == CONST_INT)
++        if (unaligned_access && MEM_P (operands[0])
++	    && s_register_operand (operands[3], GET_MODE (operands[3]))
++	    && (width == 16 || width == 32) && (start_bit % BITS_PER_UNIT) == 0)
+ 	  {
+-	    HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
++	    rtx base_addr;
++
++	    if (BYTES_BIG_ENDIAN)
++	      start_bit = GET_MODE_BITSIZE (GET_MODE (operands[3])) - width
++			  - start_bit;
+ 
+-	    if (val == 0)
++	    if (width == 32)
+ 	      {
+-		emit_insn (gen_insv_zero (operands[0], operands[1],
+-					  operands[2]));
+-		DONE;
++	        base_addr = adjust_address (operands[0], SImode,
++					    start_bit / BITS_PER_UNIT);
++		emit_insn (gen_unaligned_storesi (base_addr, operands[3]));
+ 	      }
++	    else
++	      {
++	        rtx tmp = gen_reg_rtx (HImode);
+ 
+-	    /* See if the set can be done with a single orr instruction.  */
+-	    if (val == mask && const_ok_for_arm (val << start_bit))
+-	      use_bfi = FALSE;
++	        base_addr = adjust_address (operands[0], HImode,
++					    start_bit / BITS_PER_UNIT);
++		emit_move_insn (tmp, gen_lowpart (HImode, operands[3]));
++		emit_insn (gen_unaligned_storehi (base_addr, tmp));
++	      }
++	    DONE;
+ 	  }
+-	  
+-	if (use_bfi)
++	else if (s_register_operand (operands[0], GET_MODE (operands[0])))
+ 	  {
+-	    if (GET_CODE (operands[3]) != REG)
+-	      operands[3] = force_reg (SImode, operands[3]);
++	    bool use_bfi = TRUE;
+ 
+-	    emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
+-				    operands[3]));
+-	    DONE;
++	    if (GET_CODE (operands[3]) == CONST_INT)
++	      {
++		HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
++
++		if (val == 0)
++		  {
++		    emit_insn (gen_insv_zero (operands[0], operands[1],
++					      operands[2]));
++		    DONE;
++		  }
++
++		/* See if the set can be done with a single orr instruction.  */
++		if (val == mask && const_ok_for_arm (val << start_bit))
++		  use_bfi = FALSE;
++	      }
++
++	    if (use_bfi)
++	      {
++		if (GET_CODE (operands[3]) != REG)
++		  operands[3] = force_reg (SImode, operands[3]);
++
++		emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
++					operands[3]));
++		DONE;
++	      }
+ 	  }
++	else
++	  FAIL;
+       }
+ 
++    if (!s_register_operand (operands[0], GET_MODE (operands[0])))
++      FAIL;
++
+     target = copy_rtx (operands[0]);
+     /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical 
+        subreg as the final target.  */
+@@ -3695,12 +3734,10 @@
+ ;; to reduce register pressure later on.
+ 
+ (define_expand "extzv"
+-  [(set (match_dup 4)
+-	(ashift:SI (match_operand:SI   1 "register_operand" "")
+-		   (match_operand:SI   2 "const_int_operand" "")))
+-   (set (match_operand:SI              0 "register_operand" "")
+-	(lshiftrt:SI (match_dup 4)
+-		     (match_operand:SI 3 "const_int_operand" "")))]
++  [(set (match_operand 0 "s_register_operand" "")
++	(zero_extract (match_operand 1 "nonimmediate_operand" "")
++		      (match_operand 2 "const_int_operand" "")
++		      (match_operand 3 "const_int_operand" "")))]
+   "TARGET_THUMB1 || arm_arch_thumb2"
+   "
+   {
+@@ -3709,10 +3746,57 @@
+     
+     if (arm_arch_thumb2)
+       {
+-	emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
+-				 operands[3]));
+-	DONE;
++	HOST_WIDE_INT width = INTVAL (operands[2]);
++	HOST_WIDE_INT bitpos = INTVAL (operands[3]);
++
++	if (unaligned_access && MEM_P (operands[1])
++	    && (width == 16 || width == 32) && (bitpos % BITS_PER_UNIT) == 0)
++	  {
++	    rtx base_addr;
++
++	    if (BYTES_BIG_ENDIAN)
++	      bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width
++		       - bitpos;
++
++	    if (width == 32)
++              {
++		base_addr = adjust_address (operands[1], SImode,
++					    bitpos / BITS_PER_UNIT);
++		emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
++              }
++	    else
++              {
++		rtx dest = operands[0];
++		rtx tmp = gen_reg_rtx (SImode);
++
++		/* We may get a paradoxical subreg here.  Strip it off.  */
++		if (GET_CODE (dest) == SUBREG
++		    && GET_MODE (dest) == SImode
++		    && GET_MODE (SUBREG_REG (dest)) == HImode)
++		  dest = SUBREG_REG (dest);
++
++		if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
++		  FAIL;
++
++		base_addr = adjust_address (operands[1], HImode,
++					    bitpos / BITS_PER_UNIT);
++		emit_insn (gen_unaligned_loadhiu (tmp, base_addr));
++		emit_move_insn (gen_lowpart (SImode, dest), tmp);
++	      }
++	    DONE;
++	  }
++	else if (s_register_operand (operands[1], GET_MODE (operands[1])))
++	  {
++	    emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
++				     operands[3]));
++	    DONE;
++	  }
++	else
++	  FAIL;
+       }
++    
++    if (!s_register_operand (operands[1], GET_MODE (operands[1])))
++      FAIL;
+ 
+     operands[3] = GEN_INT (rshift);
+     
+@@ -3722,12 +3806,154 @@
+         DONE;
+       }
+       
+-    operands[2] = GEN_INT (lshift);
+-    operands[4] = gen_reg_rtx (SImode);
++    emit_insn (gen_extzv_t1 (operands[0], operands[1], GEN_INT (lshift),
++			     operands[3], gen_reg_rtx (SImode)));
++    DONE;
+   }"
+ )
+ 
+-(define_insn "extv"
++;; Helper for extzv, for the Thumb-1 register-shifts case.
++
++(define_expand "extzv_t1"
++  [(set (match_operand:SI 4 "s_register_operand" "")
++	(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
++		   (match_operand:SI 2 "const_int_operand" "")))
++   (set (match_operand:SI 0 "s_register_operand" "")
++	(lshiftrt:SI (match_dup 4)
++		     (match_operand:SI 3 "const_int_operand" "")))]
++  "TARGET_THUMB1"
++  "")
++
++(define_expand "extv"
++  [(set (match_operand 0 "s_register_operand" "")
++	(sign_extract (match_operand 1 "nonimmediate_operand" "")
++		      (match_operand 2 "const_int_operand" "")
++		      (match_operand 3 "const_int_operand" "")))]
++  "arm_arch_thumb2"
++{
++  HOST_WIDE_INT width = INTVAL (operands[2]);
++  HOST_WIDE_INT bitpos = INTVAL (operands[3]);
++
++  if (unaligned_access && MEM_P (operands[1]) && (width == 16 || width == 32)
++      && (bitpos % BITS_PER_UNIT)  == 0)
++    {
++      rtx base_addr;
++      
++      if (BYTES_BIG_ENDIAN)
++	bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width - bitpos;
++      
++      if (width == 32)
++        {
++	  base_addr = adjust_address (operands[1], SImode,
++				      bitpos / BITS_PER_UNIT);
++	  emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
++        }
++      else
++        {
++	  rtx dest = operands[0];
++	  rtx tmp = gen_reg_rtx (SImode);
++	  
++	  /* We may get a paradoxical subreg here.  Strip it off.  */
++	  if (GET_CODE (dest) == SUBREG
++	      && GET_MODE (dest) == SImode
++	      && GET_MODE (SUBREG_REG (dest)) == HImode)
++	    dest = SUBREG_REG (dest);
++	  
++	  if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
++	    FAIL;
++	  
++	  base_addr = adjust_address (operands[1], HImode,
++				      bitpos / BITS_PER_UNIT);
++	  emit_insn (gen_unaligned_loadhis (tmp, base_addr));
++	  emit_move_insn (gen_lowpart (SImode, dest), tmp);
++	}
++
++      DONE;
++    }
++  else if (!s_register_operand (operands[1], GET_MODE (operands[1])))
++    FAIL;
++  else if (GET_MODE (operands[0]) == SImode
++	   && GET_MODE (operands[1]) == SImode)
++    {
++      emit_insn (gen_extv_regsi (operands[0], operands[1], operands[2],
++				 operands[3]));
++      DONE;
++    }
++
++  FAIL;
++})
++
++; Helper to expand register forms of extv with the proper modes.
++
++(define_expand "extv_regsi"
++  [(set (match_operand:SI 0 "s_register_operand" "")
++	(sign_extract:SI (match_operand:SI 1 "s_register_operand" "")
++			 (match_operand 2 "const_int_operand" "")
++			 (match_operand 3 "const_int_operand" "")))]
++  ""
++{
++})
++
++; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
++
++(define_insn "unaligned_loadsi"
++  [(set (match_operand:SI 0 "s_register_operand" "=l,r")
++	(unspec:SI [(match_operand:SI 1 "memory_operand" "Uw,m")]
++		   UNSPEC_UNALIGNED_LOAD))]
++  "unaligned_access && TARGET_32BIT"
++  "ldr%?\t%0, %1\t@ unaligned"
++  [(set_attr "arch" "t2,any")
++   (set_attr "length" "2,4")
++   (set_attr "predicable" "yes")
++   (set_attr "type" "load1")])
++
++(define_insn "unaligned_loadhis"
++  [(set (match_operand:SI 0 "s_register_operand" "=l,r")
++	(sign_extend:SI
++	  (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")]
++		     UNSPEC_UNALIGNED_LOAD)))]
++  "unaligned_access && TARGET_32BIT"
++  "ldr%(sh%)\t%0, %1\t@ unaligned"
++  [(set_attr "arch" "t2,any")
++   (set_attr "length" "2,4")
++   (set_attr "predicable" "yes")
++   (set_attr "type" "load_byte")])
++
++(define_insn "unaligned_loadhiu"
++  [(set (match_operand:SI 0 "s_register_operand" "=l,r")
++	(zero_extend:SI
++	  (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")]
++		     UNSPEC_UNALIGNED_LOAD)))]
++  "unaligned_access && TARGET_32BIT"
++  "ldr%(h%)\t%0, %1\t@ unaligned"
++  [(set_attr "arch" "t2,any")
++   (set_attr "length" "2,4")
++   (set_attr "predicable" "yes")
++   (set_attr "type" "load_byte")])
++
++(define_insn "unaligned_storesi"
++  [(set (match_operand:SI 0 "memory_operand" "=Uw,m")
++	(unspec:SI [(match_operand:SI 1 "s_register_operand" "l,r")]
++		   UNSPEC_UNALIGNED_STORE))]
++  "unaligned_access && TARGET_32BIT"
++  "str%?\t%1, %0\t@ unaligned"
++  [(set_attr "arch" "t2,any")
++   (set_attr "length" "2,4")
++   (set_attr "predicable" "yes")
++   (set_attr "type" "store1")])
++
++(define_insn "unaligned_storehi"
++  [(set (match_operand:HI 0 "memory_operand" "=Uw,m")
++	(unspec:HI [(match_operand:HI 1 "s_register_operand" "l,r")]
++		   UNSPEC_UNALIGNED_STORE))]
++  "unaligned_access && TARGET_32BIT"
++  "str%(h%)\t%1, %0\t@ unaligned"
++  [(set_attr "arch" "t2,any")
++   (set_attr "length" "2,4")
++   (set_attr "predicable" "yes")
++   (set_attr "type" "store1")])
++
++(define_insn "*extv_reg"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
+                          (match_operand:SI 2 "const_int_operand" "M")
+@@ -6069,8 +6295,8 @@
+ 
+ 
+ (define_insn "*arm_movqi_insn"
+-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
+-	(match_operand:QI 1 "general_operand" "rI,K,m,r"))]
++  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,l,Uu,r,m")
++	(match_operand:QI 1 "general_operand" "rI,K,Uu,l,m,r"))]
+   "TARGET_32BIT
+    && (   register_operand (operands[0], QImode)
+        || register_operand (operands[1], QImode))"
+@@ -6078,10 +6304,14 @@
+    mov%?\\t%0, %1
+    mvn%?\\t%0, #%B1
+    ldr%(b%)\\t%0, %1
++   str%(b%)\\t%1, %0
++   ldr%(b%)\\t%0, %1
+    str%(b%)\\t%1, %0"
+-  [(set_attr "type" "*,*,load1,store1")
+-   (set_attr "insn" "mov,mvn,*,*")
+-   (set_attr "predicable" "yes")]
++  [(set_attr "type" "*,*,load1,store1,load1,store1")
++   (set_attr "insn" "mov,mvn,*,*,*,*")
++   (set_attr "predicable" "yes")
++   (set_attr "arch" "any,any,t2,t2,any,any")
++   (set_attr "length" "4,4,2,2,4,4")]
+ )
+ 
+ (define_insn "*thumb1_movqi_insn"
+Index: gcc-4_6-branch/gcc/config/arm/arm.opt
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.opt	2012-03-05 16:07:14.000000000 -0800
++++ gcc-4_6-branch/gcc/config/arm/arm.opt	2012-03-05 16:07:50.404936697 -0800
+@@ -173,3 +173,7 @@
+ Target Report Var(fix_cm3_ldrd) Init(2)
+ Avoid overlapping destination and address registers on LDRD instructions
+ that may trigger Cortex-M3 errata.
++
++munaligned-access
++Target Report Var(unaligned_access) Init(2)
++Enable unaligned word and halfword accesses to packed data.
+Index: gcc-4_6-branch/gcc/config/arm/constraints.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/constraints.md	2012-03-05 16:07:14.000000000 -0800
++++ gcc-4_6-branch/gcc/config/arm/constraints.md	2012-03-05 16:07:50.404936697 -0800
+@@ -36,6 +36,7 @@
+ ;; The following memory constraints have been used:
+ ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
+ ;; in ARM state: Uq
++;; in Thumb state: Uu, Uw
+ 
+ 
+ (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
+@@ -344,6 +345,27 @@
+  (and (match_code "mem")
+       (match_test "REG_P (XEXP (op, 0))")))
+ 
++(define_memory_constraint "Uu"
++ "@internal
++  In Thumb state an address that is valid in 16bit encoding."
++ (and (match_code "mem")
++      (match_test "TARGET_THUMB
++		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
++						   0)")))
++
++; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
++; are actually LDM/STM instructions, so cannot be used to access unaligned
++; data.
++(define_memory_constraint "Uw"
++ "@internal
++  In Thumb state an address that is valid in 16bit encoding, and that can be
++  used for unaligned accesses."
++ (and (match_code "mem")
++      (match_test "TARGET_THUMB
++		   && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
++						   0)
++		   && GET_CODE (XEXP (op, 0)) != POST_INC")))
++
+ ;; We used to have constraint letters for S and R in ARM state, but
+ ;; all uses of these now appear to have been removed.
+ 
+Index: gcc-4_6-branch/gcc/expmed.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/expmed.c	2012-01-04 15:37:51.000000000 -0800
++++ gcc-4_6-branch/gcc/expmed.c	2012-03-05 16:07:50.404936697 -0800
+@@ -657,6 +657,10 @@
+       && GET_MODE (value) != BLKmode
+       && bitsize > 0
+       && GET_MODE_BITSIZE (op_mode) >= bitsize
++      /* Do not use insv for volatile bitfields when
++         -fstrict-volatile-bitfields is in effect.  */
++      && !(MEM_P (op0) && MEM_VOLATILE_P (op0)
++	   && flag_strict_volatile_bitfields > 0)
+       && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
+ 	    && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode)))
+       && insn_data[CODE_FOR_insv].operand[1].predicate (GEN_INT (bitsize),
+@@ -700,19 +704,21 @@
+ 	  copy_back = true;
+ 	}
+ 
+-      /* On big-endian machines, we count bits from the most significant.
+-	 If the bit field insn does not, we must invert.  */
+-
+-      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
+-	xbitpos = unit - bitsize - xbitpos;
+-
+       /* We have been counting XBITPOS within UNIT.
+ 	 Count instead within the size of the register.  */
+-      if (BITS_BIG_ENDIAN && !MEM_P (xop0))
++      if (BYTES_BIG_ENDIAN && !MEM_P (xop0))
+ 	xbitpos += GET_MODE_BITSIZE (op_mode) - unit;
+ 
+       unit = GET_MODE_BITSIZE (op_mode);
+ 
++      /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
++         "backwards" from the size of the unit we are inserting into.
++	 Otherwise, we count bits from the most significant on a
++	 BYTES/BITS_BIG_ENDIAN machine.  */
++
++      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
++	xbitpos = unit - bitsize - xbitpos;
++
+       /* Convert VALUE to op_mode (which insv insn wants) in VALUE1.  */
+       value1 = value;
+       if (GET_MODE (value) != op_mode)
+@@ -1528,6 +1534,10 @@
+   if (ext_mode != MAX_MACHINE_MODE
+       && bitsize > 0
+       && GET_MODE_BITSIZE (ext_mode) >= bitsize
++      /* Do not use extv/extzv for volatile bitfields when
++         -fstrict-volatile-bitfields is in effect.  */
++      && !(MEM_P (op0) && MEM_VOLATILE_P (op0)
++	   && flag_strict_volatile_bitfields > 0)
+       /* If op0 is a register, we need it in EXT_MODE to make it
+ 	 acceptable to the format of ext(z)v.  */
+       && !(GET_CODE (op0) == SUBREG && GET_MODE (op0) != ext_mode)
+@@ -1552,17 +1562,20 @@
+ 	/* Get ref to first byte containing part of the field.  */
+ 	xop0 = adjust_address (xop0, byte_mode, xoffset);
+ 
+-      /* On big-endian machines, we count bits from the most significant.
+-	 If the bit field insn does not, we must invert.  */
+-      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
+-	xbitpos = unit - bitsize - xbitpos;
+-
+       /* Now convert from counting within UNIT to counting in EXT_MODE.  */
+-      if (BITS_BIG_ENDIAN && !MEM_P (xop0))
++      if (BYTES_BIG_ENDIAN && !MEM_P (xop0))
+ 	xbitpos += GET_MODE_BITSIZE (ext_mode) - unit;
+ 
+       unit = GET_MODE_BITSIZE (ext_mode);
+ 
++      /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
++         "backwards" from the size of the unit we are extracting from.
++	 Otherwise, we count bits from the most significant on a
++	 BYTES/BITS_BIG_ENDIAN machine.  */
++
++      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
++	xbitpos = unit - bitsize - xbitpos;
++
+       if (xtarget == 0)
+ 	xtarget = xspec_target = gen_reg_rtx (tmode);
+ 
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch
new file mode 100644
index 0000000000..3c0ff00856
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch
@@ -0,0 +1,1951 @@
+2011-10-17  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-10-10  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* modulo-sched.c (ps_reg_move_info): Add num_consecutive_stages.
+	(SCHED_FIRST_REG_MOVE, SCHED_NREG_MOVES): Delete.
+	(node_sched_params): Remove first_reg_move and nreg_moves.
+	(ps_num_consecutive_stages, extend_node_sched_params): New functions.
+	(update_node_sched_params): Move up file.
+	(print_node_sched_params): Print the stage.  Don't dump info related
+	to first_reg_move and nreg_moves.
+	(set_columns_for_row): New function.
+	(set_columns_for_ps): Move up file and use set_columns_for_row.
+	(schedule_reg_move): New function.
+	(schedule_reg_moves): Call extend_node_sched_params and
+	schedule_reg_move.  Extend size of uses bitmap.  Initialize
+	num_consecutive_stages.  Return false if a move could not be
+	scheduled.
+	(apply_reg_moves): Don't emit moves here.
+	(permute_partial_schedule): Handle register moves.
+	(duplicate_insns_of_cycles): Remove for_prolog.  Emit moves according
+	to the same stage-count test as ddg nodes.
+	(generate_prolog_epilog): Update calls accordingly.
+	(sms_schedule): Allow move-scheduling to add a new first stage.
+
+2011-10-17  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-10-10  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* modulo-sched.c (ps_insn): Adjust comment.
+	(ps_reg_move_info): New structure.
+	(partial_schedule): Add reg_moves field.
+	(SCHED_PARAMS): Use node_sched_param_vec instead of node_sched_params.
+	(node_sched_params): Turn first_reg_move into an identifier.
+	(ps_reg_move): New function.
+	(ps_rtl_insn): Cope with register moves.
+	(ps_first_note): Adjust comment and assert that the instruction
+	isn't a register move.
+	(node_sched_params): Replace with...
+	(node_sched_param_vec): ...this vector.
+	(set_node_sched_params): Adjust accordingly.
+	(print_node_sched_params): Take a partial schedule instead of a ddg.
+	Use ps_rtl_insn and ps_reg_move.
+	(generate_reg_moves): Rename to...
+	(schedule_reg_moves): ...this.  Remove rescan parameter.  Record each
+	move in the partial schedule, but don't emit it here.  Don't perform
+	register substitutions here either.
+	(apply_reg_moves): New function.
+	(duplicate_insns_of_cycles): Use register indices directly,
+	rather than finding instructions using PREV_INSN.  Use ps_reg_move.
+	(sms_schedule): Call schedule_reg_moves before committing to
+	a partial schedule.   Try the next ii if the schedule fails.
+	Use apply_reg_moves instead of generate_reg_moves.  Adjust
+	call to print_node_sched_params.  Free node_sched_param_vec
+	instead of node_sched_params.
+	(create_partial_schedule): Initialize reg_moves.
+	(free_partial_schedule): Free reg_moves.
+
+2011-10-17  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-10-10  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* modulo-sched.c (ps_insn): Replace node field with an identifier.
+	(SCHED_ASAP): Replace with..
+	(NODE_ASAP): ...this macro.
+	(SCHED_PARAMS): New macro.
+	(SCHED_TIME, SCHED_FIRST_REG_MOVE, SCHED_NREG_MOVES, SCHED_ROW)
+	(SCHED_STAGE, SCHED_COLUMN): Redefine using SCHED_PARAMS.
+	(node_sched_params): Remove asap.
+	(ps_rtl_insn, ps_first_note): New functions.
+	(set_node_sched_params): Use XCNEWVEC.  Don't copy across the
+	asap values.
+	(print_node_sched_params): Use SCHED_PARAMS and NODE_ASAP.
+	(generate_reg_moves): Pass ids to the SCHED_* macros.
+	(update_node_sched_params): Take a ps insn identifier rather than
+	a node as parameter.  Use ps_rtl_insn.
+	(set_columns_for_ps): Update for above field and SCHED_* macro changes.
+	(permute_partial_schedule): Use ps_rtl_insn and ps_first_note.
+	(optimize_sc): Update for above field and SCHED_* macro changes.
+	Update calls to try_scheduling_node_in_cycle and
+	update_node_sched_params.
+	(duplicate_insns_of_cycles): Adjust for above field and SCHED_*
+	macro changes.  Use ps_rtl_insn and ps_first_note.
+	(sms_schedule): Pass ids to the SCHED_* macros.
+	(get_sched_window): Adjust for above field and SCHED_* macro changes.
+	Use NODE_ASAP instead of SCHED_ASAP.
+	(try_scheduling_node_in_cycle): Remove node parameter.  Update
+	call to ps_add_node_check_conflicts.  Pass ids to the SCHED_*
+	macros.
+	(sms_schedule_by_order): Update call to try_scheduling_node_in_cycle.
+	(ps_insert_empty_row): Adjust for above field changes.
+	(compute_split_row): Use ids rather than nodes.
+	(verify_partial_schedule): Adjust for above field changes.
+	(print_partial_schedule): Use ps_rtl_insn.
+	(create_ps_insn): Take an id rather than a node.
+	(ps_insn_find_column): Adjust for above field changes.
+	Use ps_rtl_insn.
+	(ps_insn_advance_column): Adjust for above field changes.
+	(add_node_to_ps): Remove node parameter.  Update call to
+	create_ps_insn.
+	(ps_has_conflicts): Use ps_rtl_insn.
+	(ps_add_node_check_conflicts): Replace node parameter than an id.
+
+2011-10-17  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-10-10  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* modulo-sched.c (undo_replace_buff_elem): Delete.
+	(generate_reg_moves): Don't build and return an undo list.
+	(free_undo_replace_buff): Delete.
+	(sms_schedule): Adjust call to generate_reg_moves.
+	Don't call free_undo_replace_buff.
+
+2011-10-17  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-08-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* modulo-sched.c (get_sched_window): Use a table for the debug output.
+	Print the current ii.
+	(sms_schedule_by_order): Reduce whitespace in dump line.
+
+2011-10-17  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-08-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* modulo-sched.c (get_sched_window): Use just one loop for predecessors
+	and one loop for successors.  Fix upper bound of memory range.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-10-02 06:56:53 +0000
++++ new/gcc/modulo-sched.c	2011-10-10 14:35:32 +0000
+@@ -124,8 +124,10 @@
+ /* A single instruction in the partial schedule.  */
+ struct ps_insn
+ {
+-  /* The corresponding DDG_NODE.  */
+-  ddg_node_ptr node;
++  /* Identifies the instruction to be scheduled.  Values smaller than
++     the ddg's num_nodes refer directly to ddg nodes.  A value of
++     X - num_nodes refers to register move X.  */
++  int id;
+ 
+   /* The (absolute) cycle in which the PS instruction is scheduled.
+      Same as SCHED_TIME (node).  */
+@@ -137,6 +139,33 @@
+ 
+ };
+ 
++/* Information about a register move that has been added to a partial
++   schedule.  */
++struct ps_reg_move_info
++{
++  /* The source of the move is defined by the ps_insn with id DEF.
++     The destination is used by the ps_insns with the ids in USES.  */
++  int def;
++  sbitmap uses;
++
++  /* The original form of USES' instructions used OLD_REG, but they
++     should now use NEW_REG.  */
++  rtx old_reg;
++  rtx new_reg;
++
++  /* The number of consecutive stages that the move occupies.  */
++  int num_consecutive_stages;
++
++  /* An instruction that sets NEW_REG to the correct value.  The first
++     move associated with DEF will have an rhs of OLD_REG; later moves
++     use the result of the previous move.  */
++  rtx insn;
++};
++
++typedef struct ps_reg_move_info ps_reg_move_info;
++DEF_VEC_O (ps_reg_move_info);
++DEF_VEC_ALLOC_O (ps_reg_move_info, heap);
++
+ /* Holds the partial schedule as an array of II rows.  Each entry of the
+    array points to a linked list of PS_INSNs, which represents the
+    instructions that are scheduled for that row.  */
+@@ -148,6 +177,10 @@
+   /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii).  */
+   ps_insn_ptr *rows;
+ 
++  /* All the moves added for this partial schedule.  Index X has
++     a ps_insn id of X + g->num_nodes.  */
++  VEC (ps_reg_move_info, heap) *reg_moves;
++
+   /*  rows_length[i] holds the number of instructions in the row.
+       It is used only (as an optimization) to back off quickly from
+       trying to schedule a node in a full row; that is, to avoid running
+@@ -165,17 +198,6 @@
+   int stage_count;  /* The stage count of the partial schedule.  */
+ };
+ 
+-/* We use this to record all the register replacements we do in
+-   the kernel so we can undo SMS if it is not profitable.  */
+-struct undo_replace_buff_elem
+-{
+-  rtx insn;
+-  rtx orig_reg;
+-  rtx new_reg;
+-  struct undo_replace_buff_elem *next;
+-};
+-
+-
+ 
+ static partial_schedule_ptr create_partial_schedule (int ii, ddg_ptr, int history);
+ static void free_partial_schedule (partial_schedule_ptr);
+@@ -183,9 +205,7 @@
+ void print_partial_schedule (partial_schedule_ptr, FILE *);
+ static void verify_partial_schedule (partial_schedule_ptr, sbitmap);
+ static ps_insn_ptr ps_add_node_check_conflicts (partial_schedule_ptr,
+-						ddg_node_ptr node, int cycle,
+-						sbitmap must_precede,
+-						sbitmap must_follow);
++						int, int, sbitmap, sbitmap);
+ static void rotate_partial_schedule (partial_schedule_ptr, int);
+ void set_row_column_for_ps (partial_schedule_ptr);
+ static void ps_insert_empty_row (partial_schedule_ptr, int, sbitmap);
+@@ -201,43 +221,27 @@
+ static void permute_partial_schedule (partial_schedule_ptr, rtx);
+ static void generate_prolog_epilog (partial_schedule_ptr, struct loop *,
+                                     rtx, rtx);
+-static void duplicate_insns_of_cycles (partial_schedule_ptr,
+-				       int, int, int, rtx);
+ static int calculate_stage_count (partial_schedule_ptr, int);
+ static void calculate_must_precede_follow (ddg_node_ptr, int, int,
+ 					   int, int, sbitmap, sbitmap, sbitmap);
+ static int get_sched_window (partial_schedule_ptr, ddg_node_ptr, 
+ 			     sbitmap, int, int *, int *, int *);
+-static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
+-					  int, int, sbitmap, int *, sbitmap,
+-					  sbitmap);
++static bool try_scheduling_node_in_cycle (partial_schedule_ptr, int, int,
++					  sbitmap, int *, sbitmap, sbitmap);
+ static void remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
+ 
+-#define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
+-#define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
+-#define SCHED_FIRST_REG_MOVE(x) \
+-	(((node_sched_params_ptr)(x)->aux.info)->first_reg_move)
+-#define SCHED_NREG_MOVES(x) \
+-	(((node_sched_params_ptr)(x)->aux.info)->nreg_moves)
+-#define SCHED_ROW(x) (((node_sched_params_ptr)(x)->aux.info)->row)
+-#define SCHED_STAGE(x) (((node_sched_params_ptr)(x)->aux.info)->stage)
+-#define SCHED_COLUMN(x) (((node_sched_params_ptr)(x)->aux.info)->column)
++#define NODE_ASAP(node) ((node)->aux.count)
++
++#define SCHED_PARAMS(x) VEC_index (node_sched_params, node_sched_param_vec, x)
++#define SCHED_TIME(x) (SCHED_PARAMS (x)->time)
++#define SCHED_ROW(x) (SCHED_PARAMS (x)->row)
++#define SCHED_STAGE(x) (SCHED_PARAMS (x)->stage)
++#define SCHED_COLUMN(x) (SCHED_PARAMS (x)->column)
+ 
+ /* The scheduling parameters held for each node.  */
+ typedef struct node_sched_params
+ {
+-  int asap;	/* A lower-bound on the absolute scheduling cycle.  */
+-  int time;	/* The absolute scheduling cycle (time >= asap).  */
+-
+-  /* The following field (first_reg_move) is a pointer to the first
+-     register-move instruction added to handle the modulo-variable-expansion
+-     of the register defined by this node.  This register-move copies the
+-     original register defined by the node.  */
+-  rtx first_reg_move;
+-
+-  /* The number of register-move instructions added, immediately preceding
+-     first_reg_move.  */
+-  int nreg_moves;
++  int time;	/* The absolute scheduling cycle.  */
+ 
+   int row;    /* Holds time % ii.  */
+   int stage;  /* Holds time / ii.  */
+@@ -247,6 +251,9 @@
+   int column;
+ } *node_sched_params_ptr;
+ 
++typedef struct node_sched_params node_sched_params;
++DEF_VEC_O (node_sched_params);
++DEF_VEC_ALLOC_O (node_sched_params, heap);
+ 
+ /* The following three functions are copied from the current scheduler
+    code in order to use sched_analyze() for computing the dependencies.
+@@ -296,6 +303,49 @@
+   0
+ };
+ 
++/* Partial schedule instruction ID in PS is a register move.  Return
++   information about it.  */
++static struct ps_reg_move_info *
++ps_reg_move (partial_schedule_ptr ps, int id)
++{
++  gcc_checking_assert (id >= ps->g->num_nodes);
++  return VEC_index (ps_reg_move_info, ps->reg_moves, id - ps->g->num_nodes);
++}
++
++/* Return the rtl instruction that is being scheduled by partial schedule
++   instruction ID, which belongs to schedule PS.  */
++static rtx
++ps_rtl_insn (partial_schedule_ptr ps, int id)
++{
++  if (id < ps->g->num_nodes)
++    return ps->g->nodes[id].insn;
++  else
++    return ps_reg_move (ps, id)->insn;
++}
++
++/* Partial schedule instruction ID, which belongs to PS, occured in
++   the original (unscheduled) loop.  Return the first instruction
++   in the loop that was associated with ps_rtl_insn (PS, ID).
++   If the instruction had some notes before it, this is the first
++   of those notes.  */
++static rtx
++ps_first_note (partial_schedule_ptr ps, int id)
++{
++  gcc_assert (id < ps->g->num_nodes);
++  return ps->g->nodes[id].first_note;
++}
++
++/* Return the number of consecutive stages that are occupied by
++   partial schedule instruction ID in PS.  */
++static int
++ps_num_consecutive_stages (partial_schedule_ptr ps, int id)
++{
++  if (id < ps->g->num_nodes)
++    return 1;
++  else
++    return ps_reg_move (ps, id)->num_consecutive_stages;
++}
++
+ /* Given HEAD and TAIL which are the first and last insns in a loop;
+    return the register which controls the loop.  Return zero if it has
+    more than one occurrence in the loop besides the control part or the
+@@ -396,35 +446,59 @@
+ }
+ 
+ 
+-/* Points to the array that contains the sched data for each node.  */
+-static node_sched_params_ptr node_sched_params;
++/* A vector that contains the sched data for each ps_insn.  */
++static VEC (node_sched_params, heap) *node_sched_param_vec;
+ 
+-/* Allocate sched_params for each node and initialize it.  Assumes that
+-   the aux field of each node contain the asap bound (computed earlier),
+-   and copies it into the sched_params field.  */
++/* Allocate sched_params for each node and initialize it.  */
+ static void
+ set_node_sched_params (ddg_ptr g)
+ {
+-  int i;
+-
+-  /* Allocate for each node in the DDG a place to hold the "sched_data".  */
+-  /* Initialize ASAP/ALAP/HIGHT to zero.  */
+-  node_sched_params = (node_sched_params_ptr)
+-		       xcalloc (g->num_nodes,
+-				sizeof (struct node_sched_params));
+-
+-  /* Set the pointer of the general data of the node to point to the
+-     appropriate sched_params structure.  */
+-  for (i = 0; i < g->num_nodes; i++)
+-    {
+-      /* Watch out for aliasing problems?  */
+-      node_sched_params[i].asap = g->nodes[i].aux.count;
+-      g->nodes[i].aux.info = &node_sched_params[i];
+-    }
+-}
+-
+-static void
+-print_node_sched_params (FILE *file, int num_nodes, ddg_ptr g)
++  VEC_truncate (node_sched_params, node_sched_param_vec, 0);
++  VEC_safe_grow_cleared (node_sched_params, heap,
++			 node_sched_param_vec, g->num_nodes);
++}
++
++/* Make sure that node_sched_param_vec has an entry for every move in PS.  */
++static void
++extend_node_sched_params (partial_schedule_ptr ps)
++{
++  VEC_safe_grow_cleared (node_sched_params, heap, node_sched_param_vec,
++			 ps->g->num_nodes + VEC_length (ps_reg_move_info,
++							ps->reg_moves));
++}
++
++/* Update the sched_params (time, row and stage) for node U using the II,
++   the CYCLE of U and MIN_CYCLE.
++   We're not simply taking the following
++   SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
++   because the stages may not be aligned on cycle 0.  */
++static void
++update_node_sched_params (int u, int ii, int cycle, int min_cycle)
++{
++  int sc_until_cycle_zero;
++  int stage;
++
++  SCHED_TIME (u) = cycle;
++  SCHED_ROW (u) = SMODULO (cycle, ii);
++
++  /* The calculation of stage count is done adding the number
++     of stages before cycle zero and after cycle zero.  */
++  sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
++
++  if (SCHED_TIME (u) < 0)
++    {
++      stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
++      SCHED_STAGE (u) = sc_until_cycle_zero - stage;
++    }
++  else
++    {
++      stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
++      SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
++    }
++}
++
++static void
++print_node_sched_params (FILE *file, int num_nodes, partial_schedule_ptr ps)
+ {
+   int i;
+ 
+@@ -432,22 +506,170 @@
+     return;
+   for (i = 0; i < num_nodes; i++)
+     {
+-      node_sched_params_ptr nsp = &node_sched_params[i];
+-      rtx reg_move = nsp->first_reg_move;
+-      int j;
++      node_sched_params_ptr nsp = SCHED_PARAMS (i);
+ 
+       fprintf (file, "Node = %d; INSN = %d\n", i,
+-	       (INSN_UID (g->nodes[i].insn)));
+-      fprintf (file, " asap = %d:\n", nsp->asap);
++	       INSN_UID (ps_rtl_insn (ps, i)));
++      fprintf (file, " asap = %d:\n", NODE_ASAP (&ps->g->nodes[i]));
+       fprintf (file, " time = %d:\n", nsp->time);
+-      fprintf (file, " nreg_moves = %d:\n", nsp->nreg_moves);
+-      for (j = 0; j < nsp->nreg_moves; j++)
++      fprintf (file, " stage = %d:\n", nsp->stage);
++    }
++}
++
++/* Set SCHED_COLUMN for each instruction in row ROW of PS.  */
++static void
++set_columns_for_row (partial_schedule_ptr ps, int row)
++{
++  ps_insn_ptr cur_insn;
++  int column;
++
++  column = 0;
++  for (cur_insn = ps->rows[row]; cur_insn; cur_insn = cur_insn->next_in_row)
++    SCHED_COLUMN (cur_insn->id) = column++;
++}
++
++/* Set SCHED_COLUMN for each instruction in PS.  */
++static void
++set_columns_for_ps (partial_schedule_ptr ps)
++{
++  int row;
++
++  for (row = 0; row < ps->ii; row++)
++    set_columns_for_row (ps, row);
++}
++
++/* Try to schedule the move with ps_insn identifier I_REG_MOVE in PS.
++   Its single predecessor has already been scheduled, as has its
++   ddg node successors.  (The move may have also another move as its
++   successor, in which case that successor will be scheduled later.)
++
++   The move is part of a chain that satisfies register dependencies
++   between a producing ddg node and various consuming ddg nodes.
++   If some of these dependencies have a distance of 1 (meaning that
++   the use is upward-exposoed) then DISTANCE1_USES is nonnull and
++   contains the set of uses with distance-1 dependencies.
++   DISTANCE1_USES is null otherwise.
++
++   MUST_FOLLOW is a scratch bitmap that is big enough to hold
++   all current ps_insn ids.
++
++   Return true on success.  */
++static bool
++schedule_reg_move (partial_schedule_ptr ps, int i_reg_move,
++		   sbitmap distance1_uses, sbitmap must_follow)
++{
++  unsigned int u;
++  int this_time, this_distance, this_start, this_end, this_latency;
++  int start, end, c, ii;
++  sbitmap_iterator sbi;
++  ps_reg_move_info *move;
++  rtx this_insn;
++  ps_insn_ptr psi;
++
++  move = ps_reg_move (ps, i_reg_move);
++  ii = ps->ii;
++  if (dump_file)
++    {
++      fprintf (dump_file, "Scheduling register move INSN %d; ii = %d"
++	       ", min cycle = %d\n\n", INSN_UID (move->insn), ii,
++	       PS_MIN_CYCLE (ps));
++      print_rtl_single (dump_file, move->insn);
++      fprintf (dump_file, "\n%11s %11s %5s\n", "start", "end", "time");
++      fprintf (dump_file, "=========== =========== =====\n");
++    }
++
++  start = INT_MIN;
++  end = INT_MAX;
++
++  /* For dependencies of distance 1 between a producer ddg node A
++     and consumer ddg node B, we have a chain of dependencies:
++
++        A --(T,L1,1)--> M1 --(T,L2,0)--> M2 ... --(T,Ln,0)--> B
++
++     where Mi is the ith move.  For dependencies of distance 0 between
++     a producer ddg node A and consumer ddg node C, we have a chain of
++     dependencies:
++
++        A --(T,L1',0)--> M1' --(T,L2',0)--> M2' ... --(T,Ln',0)--> C
++
++     where Mi' occupies the same position as Mi but occurs a stage later.
++     We can only schedule each move once, so if we have both types of
++     chain, we model the second as:
++
++        A --(T,L1',1)--> M1 --(T,L2',0)--> M2 ... --(T,Ln',-1)--> C
++
++     First handle the dependencies between the previously-scheduled
++     predecessor and the move.  */
++  this_insn = ps_rtl_insn (ps, move->def);
++  this_latency = insn_latency (this_insn, move->insn);
++  this_distance = distance1_uses && move->def < ps->g->num_nodes ? 1 : 0;
++  this_time = SCHED_TIME (move->def) - this_distance * ii;
++  this_start = this_time + this_latency;
++  this_end = this_time + ii;
++  if (dump_file)
++    fprintf (dump_file, "%11d %11d %5d %d --(T,%d,%d)--> %d\n",
++	     this_start, this_end, SCHED_TIME (move->def),
++	     INSN_UID (this_insn), this_latency, this_distance,
++	     INSN_UID (move->insn));
++
++  if (start < this_start)
++    start = this_start;
++  if (end > this_end)
++    end = this_end;
++
++  /* Handle the dependencies between the move and previously-scheduled
++     successors.  */
++  EXECUTE_IF_SET_IN_SBITMAP (move->uses, 0, u, sbi)
++    {
++      this_insn = ps_rtl_insn (ps, u);
++      this_latency = insn_latency (move->insn, this_insn);
++      if (distance1_uses && !TEST_BIT (distance1_uses, u))
++	this_distance = -1;
++      else
++	this_distance = 0;
++      this_time = SCHED_TIME (u) + this_distance * ii;
++      this_start = this_time - ii;
++      this_end = this_time - this_latency;
++      if (dump_file)
++	fprintf (dump_file, "%11d %11d %5d %d --(T,%d,%d)--> %d\n",
++		 this_start, this_end, SCHED_TIME (u), INSN_UID (move->insn),
++		 this_latency, this_distance, INSN_UID (this_insn));
++
++      if (start < this_start)
++	start = this_start;
++      if (end > this_end)
++	end = this_end;
++    }
++
++  if (dump_file)
++    {
++      fprintf (dump_file, "----------- ----------- -----\n");
++      fprintf (dump_file, "%11d %11d %5s %s\n", start, end, "", "(max, min)");
++    }
++
++  sbitmap_zero (must_follow);
++  SET_BIT (must_follow, move->def);
++
++  start = MAX (start, end - (ii - 1));
++  for (c = end; c >= start; c--)
++    {
++      psi = ps_add_node_check_conflicts (ps, i_reg_move, c,
++					 move->uses, must_follow);
++      if (psi)
+ 	{
+-	  fprintf (file, " reg_move = ");
+-	  print_rtl_single (file, reg_move);
+-	  reg_move = PREV_INSN (reg_move);
++	  update_node_sched_params (i_reg_move, ii, c, PS_MIN_CYCLE (ps));
++	  if (dump_file)
++	    fprintf (dump_file, "\nScheduled register move INSN %d at"
++		     " time %d, row %d\n\n", INSN_UID (move->insn), c,
++		     SCHED_ROW (i_reg_move));
++	  return true;
+ 	}
+     }
++
++  if (dump_file)
++    fprintf (dump_file, "\nNo available slot\n\n");
++
++  return false;
+ }
+ 
+ /*
+@@ -461,22 +683,23 @@
+    nreg_moves = ----------------------------------- + 1 - {   dependence.
+                             ii                          { 1 if not.
+ */
+-static struct undo_replace_buff_elem *
+-generate_reg_moves (partial_schedule_ptr ps, bool rescan)
++static bool
++schedule_reg_moves (partial_schedule_ptr ps)
+ {
+   ddg_ptr g = ps->g;
+   int ii = ps->ii;
+   int i;
+-  struct undo_replace_buff_elem *reg_move_replaces = NULL;
+ 
+   for (i = 0; i < g->num_nodes; i++)
+     {
+       ddg_node_ptr u = &g->nodes[i];
+       ddg_edge_ptr e;
+       int nreg_moves = 0, i_reg_move;
+-      sbitmap *uses_of_defs;
+-      rtx last_reg_move;
+       rtx prev_reg, old_reg;
++      int first_move;
++      int distances[2];
++      sbitmap must_follow;
++      sbitmap distance1_uses;
+       rtx set = single_set (u->insn);
+       
+       /* Skip instructions that do not set a register.  */
+@@ -485,18 +708,21 @@
+  
+       /* Compute the number of reg_moves needed for u, by looking at life
+ 	 ranges started at u (excluding self-loops).  */
++      distances[0] = distances[1] = false;
+       for (e = u->out; e; e = e->next_out)
+ 	if (e->type == TRUE_DEP && e->dest != e->src)
+ 	  {
+-	    int nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
++	    int nreg_moves4e = (SCHED_TIME (e->dest->cuid)
++				- SCHED_TIME (e->src->cuid)) / ii;
+ 
+             if (e->distance == 1)
+-              nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
++              nreg_moves4e = (SCHED_TIME (e->dest->cuid)
++			      - SCHED_TIME (e->src->cuid) + ii) / ii;
+ 
+ 	    /* If dest precedes src in the schedule of the kernel, then dest
+ 	       will read before src writes and we can save one reg_copy.  */
+-	    if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
+-		&& SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
++	    if (SCHED_ROW (e->dest->cuid) == SCHED_ROW (e->src->cuid)
++		&& SCHED_COLUMN (e->dest->cuid) < SCHED_COLUMN (e->src->cuid))
+ 	      nreg_moves4e--;
+ 
+             if (nreg_moves4e >= 1)
+@@ -513,125 +739,105 @@
+ 		gcc_assert (!autoinc_var_is_used_p (u->insn, e->dest->insn));
+ 	      }
+ 	    
++	    if (nreg_moves4e)
++	      {
++		gcc_assert (e->distance < 2);
++		distances[e->distance] = true;
++	      }
+ 	    nreg_moves = MAX (nreg_moves, nreg_moves4e);
+ 	  }
+ 
+       if (nreg_moves == 0)
+ 	continue;
+ 
++      /* Create NREG_MOVES register moves.  */
++      first_move = VEC_length (ps_reg_move_info, ps->reg_moves);
++      VEC_safe_grow_cleared (ps_reg_move_info, heap, ps->reg_moves,
++			     first_move + nreg_moves);
++      extend_node_sched_params (ps);
++
++      /* Record the moves associated with this node.  */
++      first_move += ps->g->num_nodes;
++
++      /* Generate each move.  */
++      old_reg = prev_reg = SET_DEST (single_set (u->insn));
++      for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
++	{
++	  ps_reg_move_info *move = ps_reg_move (ps, first_move + i_reg_move);
++
++	  move->def = i_reg_move > 0 ? first_move + i_reg_move - 1 : i;
++	  move->uses = sbitmap_alloc (first_move + nreg_moves);
++	  move->old_reg = old_reg;
++	  move->new_reg = gen_reg_rtx (GET_MODE (prev_reg));
++	  move->num_consecutive_stages = distances[0] && distances[1] ? 2 : 1;
++	  move->insn = gen_move_insn (move->new_reg, copy_rtx (prev_reg));
++	  sbitmap_zero (move->uses);
++
++	  prev_reg = move->new_reg;
++	}
++
++      distance1_uses = distances[1] ? sbitmap_alloc (g->num_nodes) : NULL;
++
+       /* Every use of the register defined by node may require a different
+ 	 copy of this register, depending on the time the use is scheduled.
+-	 Set a bitmap vector, telling which nodes use each copy of this
+-	 register.  */
+-      uses_of_defs = sbitmap_vector_alloc (nreg_moves, g->num_nodes);
+-      sbitmap_vector_zero (uses_of_defs, nreg_moves);
++	 Record which uses require which move results.  */
+       for (e = u->out; e; e = e->next_out)
+ 	if (e->type == TRUE_DEP && e->dest != e->src)
+ 	  {
+-	    int dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
++	    int dest_copy = (SCHED_TIME (e->dest->cuid)
++			     - SCHED_TIME (e->src->cuid)) / ii;
+ 
+ 	    if (e->distance == 1)
+-	      dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
++	      dest_copy = (SCHED_TIME (e->dest->cuid)
++			   - SCHED_TIME (e->src->cuid) + ii) / ii;
+ 
+-	    if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
+-		&& SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
++	    if (SCHED_ROW (e->dest->cuid) == SCHED_ROW (e->src->cuid)
++		&& SCHED_COLUMN (e->dest->cuid) < SCHED_COLUMN (e->src->cuid))
+ 	      dest_copy--;
+ 
+ 	    if (dest_copy)
+-	      SET_BIT (uses_of_defs[dest_copy - 1], e->dest->cuid);
++	      {
++		ps_reg_move_info *move;
++
++		move = ps_reg_move (ps, first_move + dest_copy - 1);
++		SET_BIT (move->uses, e->dest->cuid);
++		if (e->distance == 1)
++		  SET_BIT (distance1_uses, e->dest->cuid);
++	      }
+ 	  }
+ 
+-      /* Now generate the reg_moves, attaching relevant uses to them.  */
+-      SCHED_NREG_MOVES (u) = nreg_moves;
+-      old_reg = prev_reg = copy_rtx (SET_DEST (single_set (u->insn)));
+-      /* Insert the reg-moves right before the notes which precede
+-         the insn they relates to.  */
+-      last_reg_move = u->first_note;
+-
++      must_follow = sbitmap_alloc (first_move + nreg_moves);
+       for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
++	if (!schedule_reg_move (ps, first_move + i_reg_move,
++				distance1_uses, must_follow))
++	  break;
++      sbitmap_free (must_follow);
++      if (distance1_uses)
++	sbitmap_free (distance1_uses);
++      if (i_reg_move < nreg_moves)
++	return false;
++    }
++  return true;
++}
++
++/* Emit the moves associatied with PS.  Apply the substitutions
++   associated with them.  */
++static void
++apply_reg_moves (partial_schedule_ptr ps)
++{
++  ps_reg_move_info *move;
++  int i;
++
++  FOR_EACH_VEC_ELT (ps_reg_move_info, ps->reg_moves, i, move)
++    {
++      unsigned int i_use;
++      sbitmap_iterator sbi;
++
++      EXECUTE_IF_SET_IN_SBITMAP (move->uses, 0, i_use, sbi)
+ 	{
+-	  unsigned int i_use = 0;
+-	  rtx new_reg = gen_reg_rtx (GET_MODE (prev_reg));
+-	  rtx reg_move = gen_move_insn (new_reg, prev_reg);
+-	  sbitmap_iterator sbi;
+-
+-	  add_insn_before (reg_move, last_reg_move, NULL);
+-	  last_reg_move = reg_move;
+-
+-	  if (!SCHED_FIRST_REG_MOVE (u))
+-	    SCHED_FIRST_REG_MOVE (u) = reg_move;
+-
+-	  EXECUTE_IF_SET_IN_SBITMAP (uses_of_defs[i_reg_move], 0, i_use, sbi)
+-	    {
+-	      struct undo_replace_buff_elem *rep;
+-
+-	      rep = (struct undo_replace_buff_elem *)
+-		    xcalloc (1, sizeof (struct undo_replace_buff_elem));
+-	      rep->insn = g->nodes[i_use].insn;
+-	      rep->orig_reg = old_reg;
+-	      rep->new_reg = new_reg;
+-
+-	      if (! reg_move_replaces)
+-		reg_move_replaces = rep;
+-	      else
+-		{
+-		  rep->next = reg_move_replaces;
+-		  reg_move_replaces = rep;
+-		}
+-
+-	      replace_rtx (g->nodes[i_use].insn, old_reg, new_reg);
+-	      if (rescan)
+-		df_insn_rescan (g->nodes[i_use].insn);
+-	    }
+-
+-	  prev_reg = new_reg;
++	  replace_rtx (ps->g->nodes[i_use].insn, move->old_reg, move->new_reg);
++	  df_insn_rescan (ps->g->nodes[i_use].insn);
+ 	}
+-      sbitmap_vector_free (uses_of_defs);
+-    }
+-  return reg_move_replaces;
+-}
+-
+-/* Free memory allocated for the undo buffer.  */
+-static void
+-free_undo_replace_buff (struct undo_replace_buff_elem *reg_move_replaces)
+-{
+-
+-  while (reg_move_replaces)
+-    {
+-      struct undo_replace_buff_elem *rep = reg_move_replaces;
+-
+-      reg_move_replaces = reg_move_replaces->next;
+-      free (rep);
+-    }
+-}
+-
+-/* Update the sched_params (time, row and stage) for node U using the II,
+-   the CYCLE of U and MIN_CYCLE.  
+-   We're not simply taking the following
+-   SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
+-   because the stages may not be aligned on cycle 0.  */
+-static void
+-update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle)
+-{
+-  int sc_until_cycle_zero;
+-  int stage;
+-
+-  SCHED_TIME (u) = cycle;
+-  SCHED_ROW (u) = SMODULO (cycle, ii);
+-
+-  /* The calculation of stage count is done adding the number
+-     of stages before cycle zero and after cycle zero.  */
+-  sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
+-
+-  if (SCHED_TIME (u) < 0)
+-    {
+-      stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
+-      SCHED_STAGE (u) = sc_until_cycle_zero - stage;
+-    }
+-  else
+-    {
+-      stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
+-      SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
+     }
+ }
+ 
+@@ -647,18 +853,19 @@
+   for (row = 0; row < ii; row++)
+     for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
+       {
+-	ddg_node_ptr u = crr_insn->node;
++	int u = crr_insn->id;
+ 	int normalized_time = SCHED_TIME (u) - amount;
+ 	int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
+ 
+         if (dump_file)
+           {
+             /* Print the scheduling times after the rotation.  */
++	    rtx insn = ps_rtl_insn (ps, u);
++
+             fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
+-                     "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
+-                     INSN_UID (crr_insn->node->insn), normalized_time,
+-                     new_min_cycle);
+-            if (JUMP_P (crr_insn->node->insn))
++                     "crr_insn->cycle=%d, min_cycle=%d", u,
++                     INSN_UID (insn), normalized_time, new_min_cycle);
++            if (JUMP_P (insn))
+               fprintf (dump_file, " (branch)");
+             fprintf (dump_file, "\n");
+           }
+@@ -671,22 +878,6 @@
+       }
+ }
+  
+-/* Set SCHED_COLUMN of each node according to its position in PS.  */
+-static void
+-set_columns_for_ps (partial_schedule_ptr ps)
+-{
+-  int row;
+-
+-  for (row = 0; row < ps->ii; row++)
+-    {
+-      ps_insn_ptr cur_insn = ps->rows[row];
+-      int column = 0;
+-
+-      for (; cur_insn; cur_insn = cur_insn->next_in_row)
+-	SCHED_COLUMN (cur_insn->node) = column++;
+-    }
+-}
+-
+ /* Permute the insns according to their order in PS, from row 0 to
+    row ii-1, and position them right before LAST.  This schedules
+    the insns of the loop kernel.  */
+@@ -699,9 +890,18 @@
+ 
+   for (row = 0; row < ii ; row++)
+     for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
+-      if (PREV_INSN (last) != ps_ij->node->insn)
+-      	reorder_insns_nobb (ps_ij->node->first_note, ps_ij->node->insn,
+-			    PREV_INSN (last));
++      {
++	rtx insn = ps_rtl_insn (ps, ps_ij->id);
++
++	if (PREV_INSN (last) != insn)
++	  {
++	    if (ps_ij->id < ps->g->num_nodes)
++	      reorder_insns_nobb (ps_first_note (ps, ps_ij->id), insn,
++				  PREV_INSN (last));
++	    else
++	      add_insn_before (insn, last, NULL);
++	  }
++      }
+ }
+ 
+ /* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE
+@@ -750,7 +950,7 @@
+      to row ii-1.  If they are equal just bail out.  */
+   stage_count = calculate_stage_count (ps, amount);
+   stage_count_curr =
+-    calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1));
++    calculate_stage_count (ps, SCHED_TIME (g->closing_branch->cuid) - (ii - 1));
+ 
+   if (stage_count == stage_count_curr)
+     {
+@@ -779,7 +979,7 @@
+       print_partial_schedule (ps, dump_file);
+     }
+ 
+-  if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1)
++  if (SMODULO (SCHED_TIME (g->closing_branch->cuid), ii) == ii - 1)
+     {
+       ok = true;
+       goto clear;
+@@ -794,7 +994,7 @@
+     {
+       bool success;
+       ps_insn_ptr next_ps_i;
+-      int branch_cycle = SCHED_TIME (g->closing_branch);
++      int branch_cycle = SCHED_TIME (g->closing_branch->cuid);
+       int row = SMODULO (branch_cycle, ps->ii);
+       int num_splits = 0;
+       sbitmap must_precede, must_follow, tmp_precede, tmp_follow;
+@@ -850,13 +1050,12 @@
+          branch so we can remove it from it's current cycle.  */
+       for (next_ps_i = ps->rows[row];
+ 	   next_ps_i; next_ps_i = next_ps_i->next_in_row)
+-	if (next_ps_i->node->cuid == g->closing_branch->cuid)
++	if (next_ps_i->id == g->closing_branch->cuid)
+ 	  break;
+ 
+       remove_node_from_ps (ps, next_ps_i);
+       success =
+-	try_scheduling_node_in_cycle (ps, g->closing_branch,
+-				      g->closing_branch->cuid, c,
++	try_scheduling_node_in_cycle (ps, g->closing_branch->cuid, c,
+ 				      sched_nodes, &num_splits,
+ 				      tmp_precede, tmp_follow);
+       gcc_assert (num_splits == 0);
+@@ -874,8 +1073,7 @@
+ 				   must_precede, branch_cycle, start, end,
+ 				   step);
+ 	  success =
+-	    try_scheduling_node_in_cycle (ps, g->closing_branch,
+-					  g->closing_branch->cuid,
++	    try_scheduling_node_in_cycle (ps, g->closing_branch->cuid,
+ 					  branch_cycle, sched_nodes,
+ 					  &num_splits, tmp_precede,
+ 					  tmp_follow);
+@@ -889,7 +1087,7 @@
+ 	    fprintf (dump_file,
+ 		     "SMS success in moving branch to cycle %d\n", c);
+ 
+-	  update_node_sched_params (g->closing_branch, ii, c,
++	  update_node_sched_params (g->closing_branch->cuid, ii, c,
+ 				    PS_MIN_CYCLE (ps));
+ 	  ok = true;
+ 	}
+@@ -905,7 +1103,7 @@
+ 
+ static void
+ duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
+-			   int to_stage, int for_prolog, rtx count_reg)
++			   int to_stage, rtx count_reg)
+ {
+   int row;
+   ps_insn_ptr ps_ij;
+@@ -913,9 +1111,9 @@
+   for (row = 0; row < ps->ii; row++)
+     for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
+       {
+-	ddg_node_ptr u_node = ps_ij->node;
+-	int j, i_reg_moves;
+-	rtx reg_move = NULL_RTX;
++	int u = ps_ij->id;
++	int first_u, last_u;
++	rtx u_insn;
+ 
+         /* Do not duplicate any insn which refers to count_reg as it
+            belongs to the control part.
+@@ -923,52 +1121,20 @@
+            be ignored.
+            TODO: This should be done by analyzing the control part of
+            the loop.  */
+-        if (reg_mentioned_p (count_reg, u_node->insn)
+-            || JUMP_P (ps_ij->node->insn))
++	u_insn = ps_rtl_insn (ps, u);
++        if (reg_mentioned_p (count_reg, u_insn)
++            || JUMP_P (u_insn))
+           continue;
+ 
+-	if (for_prolog)
+-	  {
+-	    /* SCHED_STAGE (u_node) >= from_stage == 0.  Generate increasing
+-	       number of reg_moves starting with the second occurrence of
+-	       u_node, which is generated if its SCHED_STAGE <= to_stage.  */
+-	    i_reg_moves = to_stage - SCHED_STAGE (u_node) + 1;
+-	    i_reg_moves = MAX (i_reg_moves, 0);
+-	    i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
+-
+-	    /* The reg_moves start from the *first* reg_move backwards.  */
+-	    if (i_reg_moves)
+-	      {
+-		reg_move = SCHED_FIRST_REG_MOVE (u_node);
+-		for (j = 1; j < i_reg_moves; j++)
+-		  reg_move = PREV_INSN (reg_move);
+-	      }
+-	  }
+-	else /* It's for the epilog.  */
+-	  {
+-	    /* SCHED_STAGE (u_node) <= to_stage.  Generate all reg_moves,
+-	       starting to decrease one stage after u_node no longer occurs;
+-	       that is, generate all reg_moves until
+-	       SCHED_STAGE (u_node) == from_stage - 1.  */
+-	    i_reg_moves = SCHED_NREG_MOVES (u_node)
+-	    	       - (from_stage - SCHED_STAGE (u_node) - 1);
+-	    i_reg_moves = MAX (i_reg_moves, 0);
+-	    i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
+-
+-	    /* The reg_moves start from the *last* reg_move forwards.  */
+-	    if (i_reg_moves)
+-	      {
+-		reg_move = SCHED_FIRST_REG_MOVE (u_node);
+-		for (j = 1; j < SCHED_NREG_MOVES (u_node); j++)
+-		  reg_move = PREV_INSN (reg_move);
+-	      }
+-	  }
+-
+-	for (j = 0; j < i_reg_moves; j++, reg_move = NEXT_INSN (reg_move))
+-	  emit_insn (copy_rtx (PATTERN (reg_move)));
+-	if (SCHED_STAGE (u_node) >= from_stage
+-	    && SCHED_STAGE (u_node) <= to_stage)
+-	  duplicate_insn_chain (u_node->first_note, u_node->insn);
++	first_u = SCHED_STAGE (u);
++	last_u = first_u + ps_num_consecutive_stages (ps, u) - 1;
++	if (from_stage <= last_u && to_stage >= first_u)
++	  {
++	    if (u < ps->g->num_nodes)
++	      duplicate_insn_chain (ps_first_note (ps, u), u_insn);
++	    else
++	      emit_insn (copy_rtx (PATTERN (u_insn)));
++	  }
+       }
+ }
+ 
+@@ -1002,7 +1168,7 @@
+     }
+ 
+   for (i = 0; i < last_stage; i++)
+-    duplicate_insns_of_cycles (ps, 0, i, 1, count_reg);
++    duplicate_insns_of_cycles (ps, 0, i, count_reg);
+ 
+   /* Put the prolog on the entry edge.  */
+   e = loop_preheader_edge (loop);
+@@ -1014,7 +1180,7 @@
+   start_sequence ();
+ 
+   for (i = 0; i < last_stage; i++)
+-    duplicate_insns_of_cycles (ps, i + 1, last_stage, 0, count_reg);
++    duplicate_insns_of_cycles (ps, i + 1, last_stage, count_reg);
+ 
+   /* Put the epilogue on the exit edge.  */
+   gcc_assert (single_exit (loop));
+@@ -1350,10 +1516,9 @@
+     {
+       rtx head, tail;
+       rtx count_reg, count_init;
+-      int mii, rec_mii;
+-      unsigned stage_count = 0;
++      int mii, rec_mii, stage_count, min_cycle;
+       HOST_WIDEST_INT loop_count = 0;
+-      bool opt_sc_p = false;
++      bool opt_sc_p;
+ 
+       if (! (g = g_arr[loop->num]))
+         continue;
+@@ -1430,62 +1595,63 @@
+ 	fprintf (dump_file, "SMS iis %d %d %d (rec_mii, mii, maxii)\n",
+ 		 rec_mii, mii, maxii);
+ 
+-      /* After sms_order_nodes and before sms_schedule_by_order, to copy over
+-	 ASAP.  */
+-      set_node_sched_params (g);
+-
+-      ps = sms_schedule_by_order (g, mii, maxii, node_order);
+-      
+-      if (ps)
++      for (;;)
+ 	{
+-	  /* Try to achieve optimized SC by normalizing the partial
+-	     schedule (having the cycles start from cycle zero).
+-	     The branch location must be placed in row ii-1 in the
+-	     final scheduling.	If failed, shift all instructions to
+-	     position the branch in row ii-1.  */
+-	  opt_sc_p = optimize_sc (ps, g);
+-	  if (opt_sc_p)
+-	    stage_count = calculate_stage_count (ps, 0);
+-	  else
++	  set_node_sched_params (g);
++
++	  stage_count = 0;
++	  opt_sc_p = false;
++	  ps = sms_schedule_by_order (g, mii, maxii, node_order);
++      
++	  if (ps)
+ 	    {
+-	      /* Bring the branch to cycle ii-1.  */
+-	      int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
++	      /* Try to achieve optimized SC by normalizing the partial
++		 schedule (having the cycles start from cycle zero).
++		 The branch location must be placed in row ii-1 in the
++		 final scheduling.	If failed, shift all instructions to
++		 position the branch in row ii-1.  */
++	      opt_sc_p = optimize_sc (ps, g);
++	      if (opt_sc_p)
++		stage_count = calculate_stage_count (ps, 0);
++	      else
++		{
++		  /* Bring the branch to cycle ii-1.  */
++		  int amount = (SCHED_TIME (g->closing_branch->cuid)
++				- (ps->ii - 1));
+ 	      
++		  if (dump_file)
++		    fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
++
++		  stage_count = calculate_stage_count (ps, amount);
++		}
++	  
++	      gcc_assert (stage_count >= 1);
++	    }
++      
++	  /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
++	     1 means that there is no interleaving between iterations thus
++	     we let the scheduling passes do the job in this case.  */
++	  if (stage_count < PARAM_VALUE (PARAM_SMS_MIN_SC)
++	      || (count_init && (loop_count <= stage_count))
++	      || (flag_branch_probabilities && (trip_count <= stage_count)))
++	    {
+ 	      if (dump_file)
+-		fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
+-	      
+-	      stage_count = calculate_stage_count (ps, amount);
+-	    }
+-	  
+-	  gcc_assert (stage_count >= 1);
+-	  PS_STAGE_COUNT (ps) = stage_count;
+-	}
+-      
+-      /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
+-         1 means that there is no interleaving between iterations thus
+-         we let the scheduling passes do the job in this case.  */
+-      if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
+-	  || (count_init && (loop_count <= stage_count))
+-	  || (flag_branch_probabilities && (trip_count <= stage_count)))
+-	{
+-	  if (dump_file)
+-	    {
+-	      fprintf (dump_file, "SMS failed... \n");
+-	      fprintf (dump_file, "SMS sched-failed (stage-count=%d, loop-count=", stage_count);
+-	      fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
+-	      fprintf (dump_file, ", trip-count=");
+-	      fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
+-	      fprintf (dump_file, ")\n");
+-	    }
+-	}
+-      else
+-	{
+-	  struct undo_replace_buff_elem *reg_move_replaces;
++		{
++		  fprintf (dump_file, "SMS failed... \n");
++		  fprintf (dump_file, "SMS sched-failed (stage-count=%d,"
++			   " loop-count=", stage_count);
++		  fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
++		  fprintf (dump_file, ", trip-count=");
++		  fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
++		  fprintf (dump_file, ")\n");
++		}
++	      break;
++	    }
+ 
+           if (!opt_sc_p)
+             {
+ 	      /* Rotate the partial schedule to have the branch in row ii-1.  */
+-              int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
++              int amount = SCHED_TIME (g->closing_branch->cuid) - (ps->ii - 1);
+ 	      
+               reset_sched_times (ps, amount);
+               rotate_partial_schedule (ps, amount);
+@@ -1493,6 +1659,29 @@
+ 	  
+ 	  set_columns_for_ps (ps);
+ 
++	  min_cycle = PS_MIN_CYCLE (ps) - SMODULO (PS_MIN_CYCLE (ps), ps->ii);
++	  if (!schedule_reg_moves (ps))
++	    {
++	      mii = ps->ii + 1;
++	      free_partial_schedule (ps);
++	      continue;
++	    }
++
++	  /* Moves that handle incoming values might have been added
++	     to a new first stage.  Bump the stage count if so.
++
++	     ??? Perhaps we could consider rotating the schedule here
++	     instead?  */
++	  if (PS_MIN_CYCLE (ps) < min_cycle)
++	    {
++	      reset_sched_times (ps, 0);
++	      stage_count++;
++	    }
++
++	  /* The stage count should now be correct without rotation.  */
++	  gcc_checking_assert (stage_count == calculate_stage_count (ps, 0));
++	  PS_STAGE_COUNT (ps) = stage_count;
++
+ 	  canon_loop (loop);
+ 
+           if (dump_file)
+@@ -1531,17 +1720,16 @@
+ 	  /* The life-info is not valid any more.  */
+ 	  df_set_bb_dirty (g->bb);
+ 
+-	  reg_move_replaces = generate_reg_moves (ps, true);
++	  apply_reg_moves (ps);
+ 	  if (dump_file)
+-	    print_node_sched_params (dump_file, g->num_nodes, g);
++	    print_node_sched_params (dump_file, g->num_nodes, ps);
+ 	  /* Generate prolog and epilog.  */
+           generate_prolog_epilog (ps, loop, count_reg, count_init);
+-
+-	  free_undo_replace_buff (reg_move_replaces);
++	  break;
+ 	}
+ 
+       free_partial_schedule (ps);
+-      free (node_sched_params);
++      VEC_free (node_sched_params, heap, node_sched_param_vec);
+       free (node_order);
+       free_ddg (g);
+     }
+@@ -1643,9 +1831,11 @@
+ 
+ static int
+ get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node,
+-		  sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
++		  sbitmap sched_nodes, int ii, int *start_p, int *step_p,
++		  int *end_p)
+ {
+   int start, step, end;
++  int early_start, late_start;
+   ddg_edge_ptr e;
+   sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
+   sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
+@@ -1653,6 +1843,8 @@
+   sbitmap u_node_succs = NODE_SUCCESSORS (u_node);
+   int psp_not_empty;
+   int pss_not_empty;
++  int count_preds;
++  int count_succs;
+ 
+   /* 1. compute sched window for u (start, end, step).  */
+   sbitmap_zero (psp);
+@@ -1660,214 +1852,119 @@
+   psp_not_empty = sbitmap_a_and_b_cg (psp, u_node_preds, sched_nodes);
+   pss_not_empty = sbitmap_a_and_b_cg (pss, u_node_succs, sched_nodes);
+ 
+-  if (psp_not_empty && !pss_not_empty)
+-    {
+-      int early_start = INT_MIN;
+-
+-      end = INT_MAX;
+-      for (e = u_node->in; e != 0; e = e->next_in)
+-	{
+-	  ddg_node_ptr v_node = e->src;
+-
+-          if (dump_file)
+-            {
+-	      fprintf (dump_file, "\nProcessing edge: ");
+-              print_ddg_edge (dump_file, e);
+-	      fprintf (dump_file,
+-		       "\nScheduling %d (%d) in psp_not_empty,"
+-		       " checking p %d (%d): ", u_node->cuid,
+-		       INSN_UID (u_node->insn), v_node->cuid, INSN_UID
+-		       (v_node->insn));
+-            }
+-
+-	  if (TEST_BIT (sched_nodes, v_node->cuid))
+-	    {
+-              int p_st = SCHED_TIME (v_node);
+-
+-              early_start =
+-                MAX (early_start, p_st + e->latency - (e->distance * ii));
+-
+-              if (dump_file)
+-                fprintf (dump_file,
+-                         "pred st = %d; early_start = %d; latency: %d",
+-                         p_st, early_start, e->latency);
+-
+-	      if (e->data_type == MEM_DEP)
+-		end = MIN (end, SCHED_TIME (v_node) + ii - 1);
+-	    }
+-         else if (dump_file)
+-            fprintf (dump_file, "the node is not scheduled\n");
+-	}
+-      start = early_start;
+-      end = MIN (end, early_start + ii);
+-      /* Schedule the node close to it's predecessors.  */
+-      step = 1;
+-
+-      if (dump_file)
+-        fprintf (dump_file,
+-		 "\nScheduling %d (%d) in a window (%d..%d) with step %d\n",
+-		 u_node->cuid, INSN_UID (u_node->insn), start, end, step);
+-    }
+-
+-  else if (!psp_not_empty && pss_not_empty)
+-    {
+-      int late_start = INT_MAX;
+-
+-      end = INT_MIN;
+-      for (e = u_node->out; e != 0; e = e->next_out)
+-	{
+-	  ddg_node_ptr v_node = e->dest;
+-
+-          if (dump_file)
+-            {
+-              fprintf (dump_file, "\nProcessing edge:");
+-              print_ddg_edge (dump_file, e);
+-              fprintf (dump_file,
+-                       "\nScheduling %d (%d) in pss_not_empty,"
+-                       " checking s %d (%d): ", u_node->cuid,
+-                       INSN_UID (u_node->insn), v_node->cuid, INSN_UID
+-                       (v_node->insn));
+-            }
+-
+-	  if (TEST_BIT (sched_nodes, v_node->cuid))
+-	    {
+-              int s_st = SCHED_TIME (v_node);
+-
+-              late_start = MIN (late_start,
+-                                s_st - e->latency + (e->distance * ii));
+-
+-              if (dump_file)
+-                fprintf (dump_file,
+-                         "succ st = %d; late_start = %d; latency = %d",
+-                         s_st, late_start, e->latency);
+-
+-	      if (e->data_type == MEM_DEP)
+-		end = MAX (end, SCHED_TIME (v_node) - ii + 1);
+-             if (dump_file)
+-                 fprintf (dump_file, "end = %d\n", end);
+-
+-	    }
+-          else if (dump_file)
+-            fprintf (dump_file, "the node is not scheduled\n");
+-
+-	}
+-      start = late_start;
+-      end = MAX (end, late_start - ii);
+-      /* Schedule the node close to it's successors.  */
++  /* We first compute a forward range (start <= end), then decide whether
++     to reverse it.  */
++  early_start = INT_MIN;
++  late_start = INT_MAX;
++  start = INT_MIN;
++  end = INT_MAX;
++  step = 1;
++
++  count_preds = 0;
++  count_succs = 0;
++
++  if (dump_file && (psp_not_empty || pss_not_empty))
++    {
++      fprintf (dump_file, "\nAnalyzing dependencies for node %d (INSN %d)"
++	       "; ii = %d\n\n", u_node->cuid, INSN_UID (u_node->insn), ii);
++      fprintf (dump_file, "%11s %11s %11s %11s %5s\n",
++	       "start", "early start", "late start", "end", "time");
++      fprintf (dump_file, "=========== =========== =========== ==========="
++	       " =====\n");
++    }
++  /* Calculate early_start and limit end.  Both bounds are inclusive.  */
++  if (psp_not_empty)
++    for (e = u_node->in; e != 0; e = e->next_in)
++      {
++	int v = e->src->cuid;
++
++	if (TEST_BIT (sched_nodes, v))
++	  {
++	    int p_st = SCHED_TIME (v);
++	    int earliest = p_st + e->latency - (e->distance * ii);
++	    int latest = (e->data_type == MEM_DEP ? p_st + ii - 1 : INT_MAX);
++
++	    if (dump_file)
++	      {
++		fprintf (dump_file, "%11s %11d %11s %11d %5d",
++			 "", earliest, "", latest, p_st);
++		print_ddg_edge (dump_file, e);
++		fprintf (dump_file, "\n");
++	      }
++
++	    early_start = MAX (early_start, earliest);
++	    end = MIN (end, latest);
++
++	    if (e->type == TRUE_DEP && e->data_type == REG_DEP)
++	      count_preds++;
++	  }
++      }
++
++  /* Calculate late_start and limit start.  Both bounds are inclusive.  */
++  if (pss_not_empty)
++    for (e = u_node->out; e != 0; e = e->next_out)
++      {
++	int v = e->dest->cuid;
++
++	if (TEST_BIT (sched_nodes, v))
++	  {
++	    int s_st = SCHED_TIME (v);
++	    int earliest = (e->data_type == MEM_DEP ? s_st - ii + 1 : INT_MIN);
++	    int latest = s_st - e->latency + (e->distance * ii);
++
++	    if (dump_file)
++	      {
++		fprintf (dump_file, "%11d %11s %11d %11s %5d",
++			 earliest, "", latest, "", s_st);
++		print_ddg_edge (dump_file, e);
++		fprintf (dump_file, "\n");
++	      }
++
++	    start = MAX (start, earliest);
++	    late_start = MIN (late_start, latest);
++
++	    if (e->type == TRUE_DEP && e->data_type == REG_DEP)
++	      count_succs++;
++	  }
++      }
++
++  if (dump_file && (psp_not_empty || pss_not_empty))
++    {
++      fprintf (dump_file, "----------- ----------- ----------- -----------"
++	       " -----\n");
++      fprintf (dump_file, "%11d %11d %11d %11d %5s %s\n",
++	       start, early_start, late_start, end, "",
++	       "(max, max, min, min)");
++    }
++
++  /* Get a target scheduling window no bigger than ii.  */
++  if (early_start == INT_MIN && late_start == INT_MAX)
++    early_start = NODE_ASAP (u_node);
++  else if (early_start == INT_MIN)
++    early_start = late_start - (ii - 1);
++  late_start = MIN (late_start, early_start + (ii - 1));
++
++  /* Apply memory dependence limits.  */
++  start = MAX (start, early_start);
++  end = MIN (end, late_start);
++
++  if (dump_file && (psp_not_empty || pss_not_empty))
++    fprintf (dump_file, "%11s %11d %11d %11s %5s final window\n",
++	     "", start, end, "", "");
++
++  /* If there are at least as many successors as predecessors, schedule the
++     node close to its successors.  */
++  if (pss_not_empty && count_succs >= count_preds)
++    {
++      int tmp = end;
++      end = start;
++      start = tmp;
+       step = -1;
+-
+-      if (dump_file)
+-        fprintf (dump_file,
+-                 "\nScheduling %d (%d) in a window (%d..%d) with step %d\n",
+-                 u_node->cuid, INSN_UID (u_node->insn), start, end, step);
+-
+-    }
+-
+-  else if (psp_not_empty && pss_not_empty)
+-    {
+-      int early_start = INT_MIN;
+-      int late_start = INT_MAX;
+-      int count_preds = 0;
+-      int count_succs = 0;
+-
+-      start = INT_MIN;
+-      end = INT_MAX;
+-      for (e = u_node->in; e != 0; e = e->next_in)
+-	{
+-	  ddg_node_ptr v_node = e->src;
+-
+-	  if (dump_file)
+-	    {
+-              fprintf (dump_file, "\nProcessing edge:");
+-              print_ddg_edge (dump_file, e);
+-	      fprintf (dump_file,
+-		       "\nScheduling %d (%d) in psp_pss_not_empty,"
+-		       " checking p %d (%d): ", u_node->cuid, INSN_UID
+-		       (u_node->insn), v_node->cuid, INSN_UID
+-		       (v_node->insn));
+-	    }
+-
+-	  if (TEST_BIT (sched_nodes, v_node->cuid))
+-	    {
+-              int p_st = SCHED_TIME (v_node);
+-
+-	      early_start = MAX (early_start,
+-				 p_st + e->latency
+-				 - (e->distance * ii));
+-
+-              if (dump_file)
+-                fprintf (dump_file,
+-                         "pred st = %d; early_start = %d; latency = %d",
+-                         p_st, early_start, e->latency);
+-
+-              if (e->type == TRUE_DEP && e->data_type == REG_DEP)
+-                count_preds++;
+-
+-	      if (e->data_type == MEM_DEP)
+-		end = MIN (end, SCHED_TIME (v_node) + ii - 1);
+-	    }
+-          else if (dump_file)
+-            fprintf (dump_file, "the node is not scheduled\n");
+-
+-	}
+-      for (e = u_node->out; e != 0; e = e->next_out)
+-	{
+-	  ddg_node_ptr v_node = e->dest;
+-
+-	  if (dump_file)
+-	    {
+-              fprintf (dump_file, "\nProcessing edge:");
+-              print_ddg_edge (dump_file, e);
+-	      fprintf (dump_file,
+-		       "\nScheduling %d (%d) in psp_pss_not_empty,"
+-		       " checking s %d (%d): ", u_node->cuid, INSN_UID
+-		       (u_node->insn), v_node->cuid, INSN_UID
+-		       (v_node->insn));
+-	    }
+-
+-	  if (TEST_BIT (sched_nodes, v_node->cuid))
+-	    {
+-              int s_st = SCHED_TIME (v_node);
+-
+-	      late_start = MIN (late_start,
+-				s_st - e->latency
+-				+ (e->distance * ii));
+-
+-              if (dump_file)
+-                fprintf (dump_file,
+-                         "succ st = %d; late_start = %d; latency = %d",
+-                         s_st, late_start, e->latency);
+-
+-               if (e->type == TRUE_DEP && e->data_type == REG_DEP)
+-                 count_succs++;
+-
+-	      if (e->data_type == MEM_DEP)
+-		start = MAX (start, SCHED_TIME (v_node) - ii + 1);
+-	    }
+-          else if (dump_file)
+-            fprintf (dump_file, "the node is not scheduled\n");
+-
+-	}
+-      start = MAX (start, early_start);
+-      end = MIN (end, MIN (early_start + ii, late_start + 1));
+-      step = 1;
+-      /* If there are more successors than predecessors schedule the
+-         node close to it's successors.  */
+-      if (count_succs >= count_preds)
+-        {
+-          int old_start = start;
+-
+-          start = end - 1;
+-          end = old_start - 1;
+-          step = -1;
+-        }
+-    }
+-  else /* psp is empty && pss is empty.  */
+-    {
+-      start = SCHED_ASAP (u_node);
+-      end = start + ii;
+-      step = 1;
+-    }
++    }
++
++  /* Now that we've finalized the window, make END an exclusive rather
++     than an inclusive bound.  */
++  end += step;
+ 
+   *start_p = start;
+   *step_p = step;
+@@ -1880,10 +1977,10 @@
+       if (dump_file)
+ 	fprintf (dump_file, "\nEmpty window: start=%d, end=%d, step=%d\n",
+ 		 start, end, step);
+-    return -1;
++      return -1;
+     }
+ 
+-    return 0;
++  return 0;
+ }
+ 
+ /* Calculate MUST_PRECEDE/MUST_FOLLOW bitmaps of U_NODE; which is the
+@@ -1939,7 +2036,7 @@
+       SCHED_TIME (e->src) - (e->distance * ii) == first_cycle_in_window  */
+   for (e = u_node->in; e != 0; e = e->next_in)
+     if (TEST_BIT (sched_nodes, e->src->cuid)
+-	&& ((SCHED_TIME (e->src) - (e->distance * ii)) ==
++	&& ((SCHED_TIME (e->src->cuid) - (e->distance * ii)) ==
+              first_cycle_in_window))
+       {
+ 	if (dump_file)
+@@ -1964,7 +2061,7 @@
+       SCHED_TIME (e->dest) + (e->distance * ii) == last_cycle_in_window  */
+   for (e = u_node->out; e != 0; e = e->next_out)
+     if (TEST_BIT (sched_nodes, e->dest->cuid)
+-	&& ((SCHED_TIME (e->dest) + (e->distance * ii)) ==
++	&& ((SCHED_TIME (e->dest->cuid) + (e->distance * ii)) ==
+              last_cycle_in_window))
+       {
+ 	if (dump_file)
+@@ -1988,7 +2085,7 @@
+    last row of the scheduling window)  */
+ 
+ static bool
+-try_scheduling_node_in_cycle (partial_schedule_ptr ps, ddg_node_ptr u_node,
++try_scheduling_node_in_cycle (partial_schedule_ptr ps,
+ 			      int u, int cycle, sbitmap sched_nodes,
+ 			      int *num_splits, sbitmap must_precede,
+ 			      sbitmap must_follow)
+@@ -1997,11 +2094,10 @@
+   bool success = 0;
+ 
+   verify_partial_schedule (ps, sched_nodes);
+-  psi = ps_add_node_check_conflicts (ps, u_node, cycle,
+-				     must_precede, must_follow);
++  psi = ps_add_node_check_conflicts (ps, u, cycle, must_precede, must_follow);
+   if (psi)
+     {
+-      SCHED_TIME (u_node) = cycle;
++      SCHED_TIME (u) = cycle;
+       SET_BIT (sched_nodes, u);
+       success = 1;
+       *num_splits = 0;
+@@ -2062,8 +2158,8 @@
+                                 &step, &end) == 0)
+             {
+               if (dump_file)
+-                fprintf (dump_file, "\nTrying to schedule node %d \
+-                        INSN = %d  in (%d .. %d) step %d\n", u, (INSN_UID
++                fprintf (dump_file, "\nTrying to schedule node %d "
++			 "INSN = %d  in (%d .. %d) step %d\n", u, (INSN_UID
+                         (g->nodes[u].insn)), start, end, step);
+ 
+               gcc_assert ((step > 0 && start < end)
+@@ -2081,7 +2177,7 @@
+ 		                           &tmp_precede, must_precede, 
+                                            c, start, end, step);
+                   success =
+-                    try_scheduling_node_in_cycle (ps, u_node, u, c,
++                    try_scheduling_node_in_cycle (ps, u, c,
+                                                   sched_nodes,
+                                                   &num_splits, tmp_precede,
+                                                   tmp_follow);
+@@ -2181,7 +2277,7 @@
+       for (crr_insn = rows_new[row];
+ 	   crr_insn; crr_insn = crr_insn->next_in_row)
+ 	{
+-	  ddg_node_ptr u = crr_insn->node;
++	  int u = crr_insn->id;
+ 	  int new_time = SCHED_TIME (u) + (SCHED_TIME (u) / ii);
+ 
+ 	  SCHED_TIME (u) = new_time;
+@@ -2202,7 +2298,7 @@
+       for (crr_insn = rows_new[row + 1];
+ 	   crr_insn; crr_insn = crr_insn->next_in_row)
+ 	{
+-	  ddg_node_ptr u = crr_insn->node;
++	  int u = crr_insn->id;
+ 	  int new_time = SCHED_TIME (u) + (SCHED_TIME (u) / ii) + 1;
+ 
+ 	  SCHED_TIME (u) = new_time;
+@@ -2242,24 +2338,24 @@
+ {
+   ddg_edge_ptr e;
+   int lower = INT_MIN, upper = INT_MAX;
+-  ddg_node_ptr crit_pred = NULL;
+-  ddg_node_ptr crit_succ = NULL;
++  int crit_pred = -1;
++  int crit_succ = -1;
+   int crit_cycle;
+ 
+   for (e = u_node->in; e != 0; e = e->next_in)
+     {
+-      ddg_node_ptr v_node = e->src;
++      int v = e->src->cuid;
+ 
+-      if (TEST_BIT (sched_nodes, v_node->cuid)
+-	  && (low == SCHED_TIME (v_node) + e->latency - (e->distance * ii)))
+-	if (SCHED_TIME (v_node) > lower)
++      if (TEST_BIT (sched_nodes, v)
++	  && (low == SCHED_TIME (v) + e->latency - (e->distance * ii)))
++	if (SCHED_TIME (v) > lower)
+ 	  {
+-	    crit_pred = v_node;
+-	    lower = SCHED_TIME (v_node);
++	    crit_pred = v;
++	    lower = SCHED_TIME (v);
+ 	  }
+     }
+ 
+-  if (crit_pred != NULL)
++  if (crit_pred >= 0)
+     {
+       crit_cycle = SCHED_TIME (crit_pred) + 1;
+       return SMODULO (crit_cycle, ii);
+@@ -2267,17 +2363,18 @@
+ 
+   for (e = u_node->out; e != 0; e = e->next_out)
+     {
+-      ddg_node_ptr v_node = e->dest;
+-      if (TEST_BIT (sched_nodes, v_node->cuid)
+-	  && (up == SCHED_TIME (v_node) - e->latency + (e->distance * ii)))
+-	if (SCHED_TIME (v_node) < upper)
++      int v = e->dest->cuid;
++
++      if (TEST_BIT (sched_nodes, v)
++	  && (up == SCHED_TIME (v) - e->latency + (e->distance * ii)))
++	if (SCHED_TIME (v) < upper)
+ 	  {
+-	    crit_succ = v_node;
+-	    upper = SCHED_TIME (v_node);
++	    crit_succ = v;
++	    upper = SCHED_TIME (v);
+ 	  }
+     }
+ 
+-  if (crit_succ != NULL)
++  if (crit_succ >= 0)
+     {
+       crit_cycle = SCHED_TIME (crit_succ);
+       return SMODULO (crit_cycle, ii);
+@@ -2301,10 +2398,10 @@
+       
+       for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
+ 	{
+-	  ddg_node_ptr u = crr_insn->node;
++	  int u = crr_insn->id;
+ 	  
+ 	  length++;
+-	  gcc_assert (TEST_BIT (sched_nodes, u->cuid));
++	  gcc_assert (TEST_BIT (sched_nodes, u));
+ 	  /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
+ 	     popcount (sched_nodes) == number of insns in ps.  */
+ 	  gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
+@@ -2719,6 +2816,7 @@
+   partial_schedule_ptr ps = XNEW (struct partial_schedule);
+   ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
+   ps->rows_length = (int *) xcalloc (ii, sizeof (int));
++  ps->reg_moves = NULL;
+   ps->ii = ii;
+   ps->history = history;
+   ps->min_cycle = INT_MAX;
+@@ -2753,8 +2851,16 @@
+ static void
+ free_partial_schedule (partial_schedule_ptr ps)
+ {
++  ps_reg_move_info *move;
++  unsigned int i;
++
+   if (!ps)
+     return;
++
++  FOR_EACH_VEC_ELT (ps_reg_move_info, ps->reg_moves, i, move)
++    sbitmap_free (move->uses);
++  VEC_free (ps_reg_move_info, heap, ps->reg_moves);
++
+   free_ps_insns (ps);
+   free (ps->rows);
+   free (ps->rows_length);
+@@ -2796,12 +2902,12 @@
+       fprintf (dump, "\n[ROW %d ]: ", i);
+       while (ps_i)
+ 	{
+-	  if (JUMP_P (ps_i->node->insn))
+-	    fprintf (dump, "%d (branch), ",
+-		     INSN_UID (ps_i->node->insn));
++	  rtx insn = ps_rtl_insn (ps, ps_i->id);
++
++	  if (JUMP_P (insn))
++	    fprintf (dump, "%d (branch), ", INSN_UID (insn));
+ 	  else
+-	    fprintf (dump, "%d, ",
+-		     INSN_UID (ps_i->node->insn));
++	    fprintf (dump, "%d, ", INSN_UID (insn));
+ 	
+ 	  ps_i = ps_i->next_in_row;
+ 	}
+@@ -2810,11 +2916,11 @@
+ 
+ /* Creates an object of PS_INSN and initializes it to the given parameters.  */
+ static ps_insn_ptr
+-create_ps_insn (ddg_node_ptr node, int cycle)
++create_ps_insn (int id, int cycle)
+ {
+   ps_insn_ptr ps_i = XNEW (struct ps_insn);
+ 
+-  ps_i->node = node;
++  ps_i->id = id;
+   ps_i->next_in_row = NULL;
+   ps_i->prev_in_row = NULL;
+   ps_i->cycle = cycle;
+@@ -2879,10 +2985,11 @@
+        next_ps_i;
+        next_ps_i = next_ps_i->next_in_row)
+     {
+-      if (must_follow && TEST_BIT (must_follow, next_ps_i->node->cuid)
++      if (must_follow
++	  && TEST_BIT (must_follow, next_ps_i->id)
+ 	  && ! first_must_follow)
+         first_must_follow = next_ps_i;
+-      if (must_precede && TEST_BIT (must_precede, next_ps_i->node->cuid))
++      if (must_precede && TEST_BIT (must_precede, next_ps_i->id))
+         {
+           /* If we have already met a node that must follow, then
+ 	     there is no possible column.  */
+@@ -2893,8 +3000,8 @@
+         }
+       /* The closing branch must be the last in the row.  */
+       if (must_precede 
+-	  && TEST_BIT (must_precede, next_ps_i->node->cuid) 
+-	  && JUMP_P (next_ps_i->node->insn))     
++	  && TEST_BIT (must_precede, next_ps_i->id)
++	  && JUMP_P (ps_rtl_insn (ps, next_ps_i->id)))
+ 	return false;
+              
+        last_in_row = next_ps_i;
+@@ -2903,7 +3010,7 @@
+   /* The closing branch is scheduled as well.  Make sure there is no
+      dependent instruction after it as the branch should be the last
+      instruction in the row.  */
+-  if (JUMP_P (ps_i->node->insn)) 
++  if (JUMP_P (ps_rtl_insn (ps, ps_i->id)))
+     {
+       if (first_must_follow)
+ 	return false;
+@@ -2954,7 +3061,6 @@
+ {
+   ps_insn_ptr prev, next;
+   int row;
+-  ddg_node_ptr next_node;
+ 
+   if (!ps || !ps_i)
+     return false;
+@@ -2964,11 +3070,9 @@
+   if (! ps_i->next_in_row)
+     return false;
+ 
+-  next_node = ps_i->next_in_row->node;
+-
+   /* Check if next_in_row is dependent on ps_i, both having same sched
+      times (typically ANTI_DEP).  If so, ps_i cannot skip over it.  */
+-  if (must_follow && TEST_BIT (must_follow, next_node->cuid))
++  if (must_follow && TEST_BIT (must_follow, ps_i->next_in_row->id))
+     return false;
+ 
+   /* Advance PS_I over its next_in_row in the doubly linked list.  */
+@@ -2999,7 +3103,7 @@
+    before/after (respectively) the node pointed to by PS_I when scheduled
+    in the same cycle.  */
+ static ps_insn_ptr
+-add_node_to_ps (partial_schedule_ptr ps, ddg_node_ptr node, int cycle,
++add_node_to_ps (partial_schedule_ptr ps, int id, int cycle,
+ 		sbitmap must_precede, sbitmap must_follow)
+ {
+   ps_insn_ptr ps_i;
+@@ -3008,7 +3112,7 @@
+   if (ps->rows_length[row] >= issue_rate)
+     return NULL;
+ 
+-  ps_i = create_ps_insn (node, cycle);
++  ps_i = create_ps_insn (id, cycle);
+ 
+   /* Finds and inserts PS_I according to MUST_FOLLOW and
+      MUST_PRECEDE.  */
+@@ -3060,7 +3164,7 @@
+ 	   crr_insn;
+ 	   crr_insn = crr_insn->next_in_row)
+ 	{
+-	  rtx insn = crr_insn->node->insn;
++	  rtx insn = ps_rtl_insn (ps, crr_insn->id);
+ 
+ 	  if (!NONDEBUG_INSN_P (insn))
+ 	    continue;
+@@ -3097,7 +3201,7 @@
+    cuid N must be come before/after (respectively) the node pointed to by
+    PS_I when scheduled in the same cycle.  */
+ ps_insn_ptr
+-ps_add_node_check_conflicts (partial_schedule_ptr ps, ddg_node_ptr n,
++ps_add_node_check_conflicts (partial_schedule_ptr ps, int n,
+    			     int c, sbitmap must_precede,
+ 			     sbitmap must_follow)
+ {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch
new file mode 100644
index 0000000000..02f8e51779
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch
@@ -0,0 +1,147 @@
+2011-10-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF:
+
+	2011-09-09  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm-cores.def (generic-armv7-a): New architecture.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Regenerate.
+	* config/arm/arm.c (arm_file_start): Output .arch directive when
+	user passes -mcpu=generic-*.
+	(arm_issue_rate): Add genericv7a support.
+	* config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec.
+	(ASM_CPU_SPEC): New define.
+	* config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec).
+	* config/arm/semi.h (ASM_SPEC): Likewise.
+	* doc/invoke.texi (ARM Options): Document -mcpu=generic-*
+	and -mtune=generic-*.
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2011-06-14 16:00:30 +0000
++++ new/gcc/config/arm/arm-cores.def	2011-10-19 16:46:51 +0000
+@@ -124,6 +124,7 @@
+ ARM_CORE("mpcore",	  mpcore,	6K,				 FL_LDSCHED | FL_VFPV2, 9e)
+ ARM_CORE("arm1156t2-s",	  arm1156t2s,	6T2,				 FL_LDSCHED, v6t2)
+ ARM_CORE("arm1156t2f-s",  arm1156t2fs,  6T2,				 FL_LDSCHED | FL_VFPV2, v6t2)
++ARM_CORE("generic-armv7-a", genericv7a,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
+ ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
+@@ -135,3 +136,4 @@
+ ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, cortex)
++
+
+=== modified file 'gcc/config/arm/arm-tune.md'
+--- old/gcc/config/arm/arm-tune.md	2011-06-14 14:37:30 +0000
++++ new/gcc/config/arm/arm-tune.md	2011-10-19 16:46:51 +0000
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from arm-cores.def
+ (define_attr "tune"
+-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
++	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-10-11 02:31:01 +0000
++++ new/gcc/config/arm/arm.c	2011-10-19 16:46:51 +0000
+@@ -22185,6 +22185,8 @@
+       const char *fpu_name;
+       if (arm_selected_arch)
+ 	asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
++      else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
++	asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
+       else
+ 	asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
+ 
+@@ -23717,6 +23719,7 @@
+     case cortexr4:
+     case cortexr4f:
+     case cortexr5:
++    case genericv7a:
+     case cortexa5:
+     case cortexa8:
+     case cortexa9:
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-09-05 14:32:11 +0000
++++ new/gcc/config/arm/arm.h	2011-10-19 16:46:51 +0000
+@@ -198,6 +198,7 @@
+    Do not define this macro if it does not need to do anything.  */
+ #define EXTRA_SPECS						\
+   { "subtarget_cpp_spec",	SUBTARGET_CPP_SPEC },           \
++  { "asm_cpu_spec",		ASM_CPU_SPEC },			\
+   SUBTARGET_EXTRA_SPECS
+ 
+ #ifndef SUBTARGET_EXTRA_SPECS
+@@ -2278,4 +2279,8 @@
+    instruction.  */
+ #define MAX_LDM_STM_OPS 4
+ 
++#define ASM_CPU_SPEC \
++   " %{mcpu=generic-*:-march=%*;"				\
++   "   :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
++
+ #endif /* ! GCC_ARM_H */
+
+=== modified file 'gcc/config/arm/elf.h'
+--- old/gcc/config/arm/elf.h	2009-06-21 19:48:15 +0000
++++ new/gcc/config/arm/elf.h	2011-10-19 16:46:51 +0000
+@@ -56,8 +56,7 @@
+ #define ASM_SPEC "\
+ %{mbig-endian:-EB} \
+ %{mlittle-endian:-EL} \
+-%{mcpu=*:-mcpu=%*} \
+-%{march=*:-march=%*} \
++%(asm_cpu_spec) \
+ %{mapcs-*:-mapcs-%*} \
+ %(subtarget_asm_float_spec) \
+ %{mthumb-interwork:-mthumb-interwork} \
+
+=== modified file 'gcc/config/arm/semi.h'
+--- old/gcc/config/arm/semi.h	2007-08-02 09:49:31 +0000
++++ new/gcc/config/arm/semi.h	2011-10-19 16:46:51 +0000
+@@ -65,8 +65,7 @@
+ #define ASM_SPEC "\
+ %{fpic|fpie: -k} %{fPIC|fPIE: -k} \
+ %{mbig-endian:-EB} \
+-%{mcpu=*:-mcpu=%*} \
+-%{march=*:-march=%*} \
++%(arm_cpu_spec) \
+ %{mapcs-float:-mfloat} \
+ %{msoft-float:-mfloat-abi=soft} %{mhard-float:-mfloat-abi=hard} \
+ %{mfloat-abi=*} %{mfpu=*} \
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2011-08-13 08:32:32 +0000
++++ new/gcc/doc/invoke.texi	2011-10-19 16:46:51 +0000
+@@ -10215,6 +10215,10 @@
+ @samp{cortex-m0},
+ @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+ 
++@option{-mcpu=generic-@var{arch}} is also permissible, and is
++equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
++See @option{-mtune} for more information.
++
+ @item -mtune=@var{name}
+ @opindex mtune
+ This option is very similar to the @option{-mcpu=} option, except that
+@@ -10226,6 +10230,13 @@
+ For some ARM implementations better performance can be obtained by using
+ this option.
+ 
++@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
++performance for a blend of processors within architecture @var{arch}.
++The aim is to generate code that run well on the current most popular
++processors, balancing between optimizations that benefit some CPUs in the
++range, and avoiding performance pitfalls of other CPUs.  The effects of
++this option may change in future GCC versions as CPU models come and go.
++
+ @item -march=@var{name}
+ @opindex march
+ This specifies the name of the target ARM architecture.  GCC uses this
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch
new file mode 100644
index 0000000000..695aa85591
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch
@@ -0,0 +1,304 @@
+2011-10-19  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from FSF:
+	
+	2011-10-18  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/arm/driver-arm.c (host_detect_local_cpu): Close the file
+	before exiting.
+
+	2011-10-18  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config.host (arm*-*-linux*): Add driver-arm.o and x-arm.
+	* config/arm/arm.opt: Add 'native' processor_type and
+	arm_arch enum values.
+	* config/arm/arm.h (host_detect_local_cpu): New prototype.
+	(EXTRA_SPEC_FUNCTIONS): New define.
+	(MCPU_MTUNE_NATIVE_SPECS): New define.
+	(DRIVER_SELF_SPECS): New define.
+	* config/arm/driver-arm.c: New file.
+	* config/arm/x-arm: New file.
+	* doc/invoke.texi (ARM Options): Document -mcpu=native,
+	-mtune=native and -march=native.
+
+=== modified file 'gcc/config.host'
+--- old/gcc/config.host	2011-02-15 09:49:14 +0000
++++ new/gcc/config.host	2011-10-19 17:01:50 +0000
+@@ -100,6 +100,14 @@
+ esac
+ 
+ case ${host} in
++  arm*-*-linux*)
++    case ${target} in
++      arm*-*-*)
++	host_extra_gcc_objs="driver-arm.o"
++	host_xmake_file="${host_xmake_file} arm/x-arm"
++	;;
++    esac
++    ;;
+   alpha*-*-linux*)
+     case ${target} in
+       alpha*-*-linux*)
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-10-19 16:46:51 +0000
++++ new/gcc/config/arm/arm.h	2011-10-19 17:01:50 +0000
+@@ -2283,4 +2283,21 @@
+    " %{mcpu=generic-*:-march=%*;"				\
+    "   :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
+ 
++/* -mcpu=native handling only makes sense with compiler running on
++   an ARM chip.  */
++#if defined(__arm__)
++extern const char *host_detect_local_cpu (int argc, const char **argv);
++# define EXTRA_SPEC_FUNCTIONS						\
++  { "local_cpu_detect", host_detect_local_cpu },
++
++# define MCPU_MTUNE_NATIVE_SPECS					\
++   " %{march=native:%<march=native %:local_cpu_detect(arch)}"		\
++   " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"		\
++   " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
++#else
++# define MCPU_MTUNE_NATIVE_SPECS ""
++#endif
++
++#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
++
+ #endif /* ! GCC_ARM_H */
+
+=== modified file 'gcc/config/arm/arm.opt'
+--- old/gcc/config/arm/arm.opt	2011-10-11 02:31:01 +0000
++++ new/gcc/config/arm/arm.opt	2011-10-19 17:01:50 +0000
+@@ -48,6 +48,11 @@
+ Target RejectNegative Joined
+ Specify the name of the target architecture
+ 
++; Other arm_arch values are loaded from arm-tables.opt
++; but that is a generated file and this is an odd-one-out.
++EnumValue
++Enum(arm_arch) String(native) Value(-1) DriverOnly
++
+ marm
+ Target RejectNegative InverseMask(THUMB) Undocumented
+ 
+@@ -153,6 +158,11 @@
+ Target RejectNegative Joined
+ Tune code for the given processor
+ 
++; Other processor_type values are loaded from arm-tables.opt
++; but that is a generated file and this is an odd-one-out.
++EnumValue
++Enum(processor_type) String(native) Value(-1) DriverOnly
++
+ mwords-little-endian
+ Target Report RejectNegative Mask(LITTLE_WORDS)
+ Assume big endian bytes, little endian words
+
+=== added file 'gcc/config/arm/driver-arm.c'
+--- old/gcc/config/arm/driver-arm.c	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/driver-arm.c	2011-10-19 17:07:55 +0000
+@@ -0,0 +1,149 @@
++/* Subroutines for the gcc driver.
++   Copyright (C) 2011 Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#include "config.h"
++#include "system.h"
++#include "coretypes.h"
++#include "tm.h"
++#include "configargs.h"
++
++struct vendor_cpu {
++  const char *part_no;
++  const char *arch_name;
++  const char *cpu_name;
++};
++
++static struct vendor_cpu arm_cpu_table[] = {
++    {"0x926", "armv5te", "arm926ej-s"},
++    {"0xa26", "armv5te", "arm1026ej-s"},
++    {"0xb02", "armv6k", "mpcore"},
++    {"0xb36", "armv6j", "arm1136j-s"},
++    {"0xb56", "armv6t2", "arm1156t2-s"},
++    {"0xb76", "armv6zk", "arm1176jz-s"},
++    {"0xc05", "armv7-a", "cortex-a5"},
++    {"0xc08", "armv7-a", "cortex-a8"},
++    {"0xc09", "armv7-a", "cortex-a9"},
++    {"0xc0f", "armv7-a", "cortex-a15"},
++    {"0xc14", "armv7-r", "cortex-r4"},
++    {"0xc15", "armv7-r", "cortex-r5"},
++    {"0xc20", "armv6-m", "cortex-m0"},
++    {"0xc21", "armv6-m", "cortex-m1"},
++    {"0xc23", "armv7-m", "cortex-m3"},
++    {"0xc24", "armv7e-m", "cortex-m4"},
++    {NULL, NULL, NULL}
++};
++
++struct {
++  const char *vendor_no;
++  const struct vendor_cpu *vendor_parts;
++} vendors[] = {
++    {"0x41", arm_cpu_table},
++    {NULL, NULL}
++};
++
++/* This will be called by the spec parser in gcc.c when it sees
++   a %:local_cpu_detect(args) construct.  Currently it will be called
++   with either "arch", "cpu" or "tune" as argument depending on if
++   -march=native, -mcpu=native or -mtune=native is to be substituted.
++
++   It returns a string containing new command line parameters to be
++   put at the place of the above two options, depending on what CPU
++   this is executed.  E.g. "-march=armv7-a" on a Cortex-A8 for
++   -march=native.  If the routine can't detect a known processor,
++   the -march or -mtune option is discarded.
++
++   ARGC and ARGV are set depending on the actual arguments given
++   in the spec.  */
++const char *
++host_detect_local_cpu (int argc, const char **argv)
++{
++  const char *val = NULL;
++  char buf[128];
++  FILE *f = NULL;
++  bool arch;
++  const struct vendor_cpu *cpu_table = NULL;
++
++  if (argc < 1)
++    goto not_found;
++
++  arch = strcmp (argv[0], "arch") == 0;
++  if (!arch && strcmp (argv[0], "cpu") != 0 && strcmp (argv[0], "tune"))
++    goto not_found;
++
++  f = fopen ("/proc/cpuinfo", "r");
++  if (f == NULL)
++    goto not_found;
++
++  while (fgets (buf, sizeof (buf), f) != NULL)
++    {
++      /* Ensure that CPU implementer is ARM (0x41).  */
++      if (strncmp (buf, "CPU implementer", sizeof ("CPU implementer") - 1) == 0)
++	{
++	  int i;
++	  for (i = 0; vendors[i].vendor_no != NULL; i++)
++	    if (strstr (buf, vendors[i].vendor_no) != NULL)
++	      {
++		cpu_table = vendors[i].vendor_parts;
++		break;
++	      }
++	}
++
++      /* Detect arch/cpu.  */
++      if (strncmp (buf, "CPU part", sizeof ("CPU part") - 1) == 0)
++	{
++	  int i;
++
++	  if (cpu_table == NULL)
++	    goto not_found;
++
++	  for (i = 0; cpu_table[i].part_no != NULL; i++)
++	    if (strstr (buf, cpu_table[i].part_no) != NULL)
++	      {
++		val = arch ? cpu_table[i].arch_name : cpu_table[i].cpu_name;
++		break;
++	      }
++	  break;
++	}
++    }
++
++  fclose (f);
++
++  if (val == NULL)
++    goto not_found;
++
++  return concat ("-m", argv[0], "=", val, NULL);
++
++not_found:
++  {
++    unsigned int i;
++    unsigned int opt;
++    const char *search[] = {NULL, "arch"};
++
++    if (f)
++      fclose (f);
++
++    search[0] = argv[0];
++    for (opt = 0; opt < ARRAY_SIZE (search); opt++)
++      for (i = 0; i < ARRAY_SIZE (configure_default_options); i++)
++	if (strcmp (configure_default_options[i].name, search[opt]) == 0)
++	  return concat ("-m", search[opt], "=",
++			 configure_default_options[i].value, NULL);
++    return NULL;
++  }
++}
+
+=== added file 'gcc/config/arm/x-arm'
+--- old/gcc/config/arm/x-arm	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/x-arm	2011-10-19 17:01:50 +0000
+@@ -0,0 +1,3 @@
++driver-arm.o: $(srcdir)/config/arm/driver-arm.c \
++  $(CONFIG_H) $(SYSTEM_H)
++	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2011-10-19 16:46:51 +0000
++++ new/gcc/doc/invoke.texi	2011-10-19 17:01:50 +0000
+@@ -10215,10 +10215,16 @@
+ @samp{cortex-m0},
+ @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+ 
++
+ @option{-mcpu=generic-@var{arch}} is also permissible, and is
+ equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
+ See @option{-mtune} for more information.
+ 
++@option{-mcpu=native} causes the compiler to auto-detect the CPU
++of the build computer.  At present, this feature is only supported on
++Linux, and not all architectures are recognised.  If the auto-detect is
++unsuccessful the option has no effect.
++
+ @item -mtune=@var{name}
+ @opindex mtune
+ This option is very similar to the @option{-mcpu=} option, except that
+@@ -10237,6 +10243,11 @@
+ range, and avoiding performance pitfalls of other CPUs.  The effects of
+ this option may change in future GCC versions as CPU models come and go.
+ 
++@option{-mtune=native} causes the compiler to auto-detect the CPU
++of the build computer.  At present, this feature is only supported on
++Linux, and not all architectures are recognised.  If the auto-detect is
++unsuccessful the option has no effect.
++
+ @item -march=@var{name}
+ @opindex march
+ This specifies the name of the target ARM architecture.  GCC uses this
+@@ -10250,6 +10261,11 @@
+ @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
+ @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+ 
++@option{-march=native} causes the compiler to auto-detect the architecture
++of the build computer.  At present, this feature is only supported on
++Linux, and not all architectures are recognised.  If the auto-detect is
++unsuccessful the option has no effect.
++
+ @item -mfpu=@var{name}
+ @itemx -mfpe=@var{number}
+ @itemx -mfp=@var{number}
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch
new file mode 100644
index 0000000000..ad91d77366
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch
@@ -0,0 +1,123 @@
+2011-10-19  Andrew Stubbs  <ams@codesourcery.com>
+ 
+ 	Backport from FSF:
+
+	2011-10-18  Andrew Stubbs  <ams@codesourcery.com>
+
+	PR tree-optimization/50717
+
+	gcc/
+	* tree-ssa-math-opts.c (is_widening_mult_p): Remove the 'type'
+	parameter.  Calculate 'type' from stmt.
+	(convert_mult_to_widen): Update call the is_widening_mult_p.
+	(convert_plusminus_to_widen): Likewise.
+
+	gcc/testsuite/
+	* gcc.dg/pr50717-1.c: New file.
+	* gcc.target/arm/wmul-12.c: Correct types.
+	* gcc.target/arm/wmul-8.c: Correct types.
+
+=== added file 'gcc/testsuite/gcc.dg/pr50717-1.c'
+--- old/gcc/testsuite/gcc.dg/pr50717-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/pr50717-1.c	2011-10-19 14:42:50 +0000
+@@ -0,0 +1,26 @@
++/* PR tree-optimization/50717  */
++/* Ensure that widening multiply-and-accumulate is not used where integer
++   type promotion or users' casts should prevent it.  */
++
++/* { dg-options "-O2 -fdump-tree-widening_mul" } */
++
++long long
++f (unsigned int a, char b, long long c)
++{
++  return (a * b) + c;
++}
++
++int
++g (short a, short b, int c)
++{
++  return (short)(a * b) + c;
++}
++
++int
++h (char a, char b, int c)
++{
++  return (char)(a * b) + c;
++}
++
++/* { dg-final { scan-tree-dump-times "WIDEN_MULT_PLUS_EXPR" 0 "widening_mul" } } */
++/* { dg-final { cleanup-tree-dump "widening_mul" } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/wmul-12.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-12.c	2011-07-22 15:46:42 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-12.c	2011-10-19 14:42:50 +0000
+@@ -4,8 +4,8 @@
+ long long
+ foo (int *b, int *c)
+ {
+-  int tmp = *b * *c;
+-  return 10 + (long long)tmp;
++  long long tmp = (long long)*b * *c;
++  return 10 + tmp;
+ }
+ 
+ /* { dg-final { scan-assembler "smlal" } } */
+
+=== modified file 'gcc/testsuite/gcc.target/arm/wmul-8.c'
+--- old/gcc/testsuite/gcc.target/arm/wmul-8.c	2011-07-15 14:16:54 +0000
++++ new/gcc/testsuite/gcc.target/arm/wmul-8.c	2011-10-19 14:42:50 +0000
+@@ -4,7 +4,7 @@
+ long long
+ foo (long long a, int *b, int *c)
+ {
+-  return a + *b * *c;
++  return a + (long long)*b * *c;
+ }
+ 
+ /* { dg-final { scan-assembler "smlal" } } */
+
+=== modified file 'gcc/tree-ssa-math-opts.c'
+--- old/gcc/tree-ssa-math-opts.c	2011-09-08 20:11:43 +0000
++++ new/gcc/tree-ssa-math-opts.c	2011-10-19 14:42:50 +0000
+@@ -1351,10 +1351,12 @@
+    and *TYPE2_OUT would give the operands of the multiplication.  */
+ 
+ static bool
+-is_widening_mult_p (tree type, gimple stmt,
++is_widening_mult_p (gimple stmt,
+ 		    tree *type1_out, tree *rhs1_out,
+ 		    tree *type2_out, tree *rhs2_out)
+ {
++  tree type = TREE_TYPE (gimple_assign_lhs (stmt));
++
+   if (TREE_CODE (type) != INTEGER_TYPE
+       && TREE_CODE (type) != FIXED_POINT_TYPE)
+     return false;
+@@ -1416,7 +1418,7 @@
+   if (TREE_CODE (type) != INTEGER_TYPE)
+     return false;
+ 
+-  if (!is_widening_mult_p (type, stmt, &type1, &rhs1, &type2, &rhs2))
++  if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
+     return false;
+ 
+   to_mode = TYPE_MODE (type);
+@@ -1592,7 +1594,7 @@
+   if (code == PLUS_EXPR
+       && (rhs1_code == MULT_EXPR || rhs1_code == WIDEN_MULT_EXPR))
+     {
+-      if (!is_widening_mult_p (type, rhs1_stmt, &type1, &mult_rhs1,
++      if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
+ 			       &type2, &mult_rhs2))
+ 	return false;
+       add_rhs = rhs2;
+@@ -1600,7 +1602,7 @@
+     }
+   else if (rhs2_code == MULT_EXPR || rhs2_code == WIDEN_MULT_EXPR)
+     {
+-      if (!is_widening_mult_p (type, rhs2_stmt, &type1, &mult_rhs1,
++      if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
+ 			       &type2, &mult_rhs2))
+ 	return false;
+       add_rhs = rhs1;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch
new file mode 100644
index 0000000000..843f1cff25
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch
@@ -0,0 +1,24 @@
+2011-10-21  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF mainline:
+	
+	2011-10-21  Andrew Stubbs  <ams@codesourcery.com>
+
+	PR target/50809
+
+	gcc/
+	* config/arm/driver-arm.c (vendors): Make static.
+
+=== modified file 'gcc/config/arm/driver-arm.c'
+--- old/gcc/config/arm/driver-arm.c	2011-10-19 17:07:55 +0000
++++ new/gcc/config/arm/driver-arm.c	2011-10-21 19:27:47 +0000
+@@ -49,7 +49,7 @@
+     {NULL, NULL, NULL}
+ };
+ 
+-struct {
++static struct {
+   const char *vendor_no;
+   const struct vendor_cpu *vendor_parts;
+ } vendors[] = {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch
new file mode 100644
index 0000000000..1ad48e512e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch
@@ -0,0 +1,453 @@
+2011-10-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-10-16  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vect-stmts.c (vectorizable_load): For SLP without permutation
+	treat the first load of the node as the first element in its
+	interleaving chain.
+	* tree-vect-slp.c (vect_get_and_check_slp_defs): Swap the operands if
+	necessary and possible.
+	(vect_build_slp_tree): Add new argument.  Allow load groups of any size
+	in basic blocks.  Keep all the loads for further permutation check.
+	Use the new argument to determine if there is a permutation.  Update
+	the recursive calls.
+	(vect_supported_load_permutation_p): Allow subchains of interleaving
+	chains in basic block vectorization.
+	(vect_analyze_slp_instance): Update the call to vect_build_slp_tree.
+	Check load permutation based on the new parameter.
+	(vect_schedule_slp_instance): Don't start from the first element in
+	interleaving chain unless the loads are permuted.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-29.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-29.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-29.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-29.c	2011-10-23 11:29:25 +0000
+@@ -0,0 +1,59 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define A 3
++#define B 4
++#define N 256
++
++short src[N], dst[N];
++
++void foo (short * __restrict__ dst, short * __restrict__ src, int h, int stride, int dummy)
++{
++  int i;
++  h /= 16;
++  for (i = 0; i < h; i++)
++    {
++      dst[0] = A*src[0] + B*src[1];
++      dst[1] = A*src[1] + B*src[2];
++      dst[2] = A*src[2] + B*src[3];
++      dst[3] = A*src[3] + B*src[4];
++      dst[4] = A*src[4] + B*src[5];
++      dst[5] = A*src[5] + B*src[6];
++      dst[6] = A*src[6] + B*src[7];
++      dst[7] = A*src[7] + B*src[8];
++      dst += stride;
++      src += stride;
++      if (dummy == 32)
++        abort ();
++   }
++}
++
++
++int main (void)
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++       dst[i] = 0;
++       src[i] = i;
++    }
++
++  foo (dst, src, N, 8, 0);
++
++  for (i = 0; i < N/2; i++)
++    {
++      if (dst[i] != A * src[i] + B * src[i+1])
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp"  { target { vect_int_mult &&  vect_element_align } } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-10-06 11:08:08 +0000
++++ new/gcc/tree-vect-slp.c	2011-10-23 11:29:25 +0000
+@@ -115,13 +115,15 @@
+ {
+   tree oprnd;
+   unsigned int i, number_of_oprnds;
+-  tree def;
++  tree def[2];
+   gimple def_stmt;
+   enum vect_def_type dt[2] = {vect_unknown_def_type, vect_unknown_def_type};
+   stmt_vec_info stmt_info =
+     vinfo_for_stmt (VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0));
+   enum gimple_rhs_class rhs_class;
+   struct loop *loop = NULL;
++  enum tree_code rhs_code;
++  bool different_types = false;
+ 
+   if (loop_vinfo)
+     loop = LOOP_VINFO_LOOP (loop_vinfo);
+@@ -133,7 +135,7 @@
+     {
+       oprnd = gimple_op (stmt, i + 1);
+ 
+-      if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def,
++      if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def[i],
+                                &dt[i])
+ 	  || (!def_stmt && dt[i] != vect_constant_def))
+ 	{
+@@ -188,11 +190,11 @@
+           switch (gimple_code (def_stmt))
+             {
+               case GIMPLE_PHI:
+-                def = gimple_phi_result (def_stmt);
++                def[i] = gimple_phi_result (def_stmt);
+                 break;
+ 
+               case GIMPLE_ASSIGN:
+-                def = gimple_assign_lhs (def_stmt);
++                def[i] = gimple_assign_lhs (def_stmt);
+                 break;
+ 
+               default:
+@@ -206,8 +208,8 @@
+ 	{
+ 	  /* op0 of the first stmt of the group - store its info.  */
+ 	  *first_stmt_dt0 = dt[i];
+-	  if (def)
+-	    *first_stmt_def0_type = TREE_TYPE (def);
++	  if (def[i])
++	    *first_stmt_def0_type = TREE_TYPE (def[i]);
+ 	  else
+ 	    *first_stmt_const_oprnd = oprnd;
+ 
+@@ -227,8 +229,8 @@
+ 	    {
+ 	      /* op1 of the first stmt of the group - store its info.  */
+ 	      *first_stmt_dt1 = dt[i];
+-	      if (def)
+-		*first_stmt_def1_type = TREE_TYPE (def);
++	      if (def[i])
++		*first_stmt_def1_type = TREE_TYPE (def[i]);
+ 	      else
+ 		{
+ 		  /* We assume that the stmt contains only one constant
+@@ -249,22 +251,53 @@
+ 		 the def-stmt/s of the first stmt.  */
+ 	      if ((i == 0
+ 		   && (*first_stmt_dt0 != dt[i]
+-		       || (*first_stmt_def0_type && def
++		       || (*first_stmt_def0_type && def[0]
+ 			   && !types_compatible_p (*first_stmt_def0_type,
+-						   TREE_TYPE (def)))))
++						   TREE_TYPE (def[0])))))
+ 		  || (i == 1
+ 		      && (*first_stmt_dt1 != dt[i]
+-			  || (*first_stmt_def1_type && def
++			  || (*first_stmt_def1_type && def[1]
+ 			      && !types_compatible_p (*first_stmt_def1_type,
+-						      TREE_TYPE (def)))))
+-		  || (!def
++						      TREE_TYPE (def[1])))))
++		  || (!def[i]
+ 		      && !types_compatible_p (TREE_TYPE (*first_stmt_const_oprnd),
+-					      TREE_TYPE (oprnd))))
++					      TREE_TYPE (oprnd)))
++                  || different_types)
+ 		{
+-		  if (vect_print_dump_info (REPORT_SLP))
+-		    fprintf (vect_dump, "Build SLP failed: different types ");
++                  if (i != number_of_oprnds - 1)
++                    different_types = true;
++                  else
++                   {
++                      if (is_gimple_assign (stmt)
++                          && (rhs_code = gimple_assign_rhs_code (stmt))
++                          && TREE_CODE_CLASS (rhs_code) == tcc_binary
++                          && commutative_tree_code (rhs_code)
++                          && *first_stmt_dt0 == dt[1]
++                          && *first_stmt_dt1 == dt[0]
++                          && def[0] && def[1]
++                          && !(*first_stmt_def0_type
++                               && !types_compatible_p (*first_stmt_def0_type,
++                                                       TREE_TYPE (def[1])))
++                          && !(*first_stmt_def1_type
++                               && !types_compatible_p (*first_stmt_def1_type,
++                                                       TREE_TYPE (def[0]))))
++                        {
++                           if (vect_print_dump_info (REPORT_SLP))
++                            {
++                              fprintf (vect_dump, "Swapping operands of ");
++                              print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++                            }
++                           swap_tree_operands (stmt, gimple_assign_rhs1_ptr (stmt),
++                                               gimple_assign_rhs2_ptr (stmt));
++                        }
++                      else
++                        {
++                          if (vect_print_dump_info (REPORT_SLP))
++                            fprintf (vect_dump, "Build SLP failed: different types ");
+ 
+-		  return false;
++                          return false;
++                        }
++                   }
+ 		}
+ 	    }
+ 	}
+@@ -278,10 +311,10 @@
+ 
+ 	case vect_internal_def:
+         case vect_reduction_def:
+-	  if (i == 0)
++	  if ((i == 0 && !different_types) || (i == 1 && different_types))
+ 	    VEC_safe_push (gimple, heap, *def_stmts0, def_stmt);
+ 	  else
+-	    VEC_safe_push (gimple, heap, *def_stmts1, def_stmt);
++ 	    VEC_safe_push (gimple, heap, *def_stmts1, def_stmt);
+ 	  break;
+ 
+ 	default:
+@@ -289,7 +322,7 @@
+ 	  if (vect_print_dump_info (REPORT_SLP))
+ 	    {
+ 	      fprintf (vect_dump, "Build SLP failed: illegal type of def ");
+-	      print_generic_expr (vect_dump, def, TDF_SLIM);
++	      print_generic_expr (vect_dump, def[i], TDF_SLIM);
+ 	    }
+ 
+ 	  return false;
+@@ -312,7 +345,7 @@
+                      int ncopies_for_cost, unsigned int *max_nunits,
+                      VEC (int, heap) **load_permutation,
+                      VEC (slp_tree, heap) **loads,
+-                     unsigned int vectorization_factor)
++                     unsigned int vectorization_factor, bool *loads_permuted)
+ {
+   VEC (gimple, heap) *def_stmts0 = VEC_alloc (gimple, heap, group_size);
+   VEC (gimple, heap) *def_stmts1 =  VEC_alloc (gimple, heap, group_size);
+@@ -523,7 +556,9 @@
+ 
+               /* Check that the size of interleaved loads group is not
+                  greater than the SLP group size.  */
+-              if (DR_GROUP_SIZE (vinfo_for_stmt (stmt)) > ncopies * group_size)
++              if (loop_vinfo
++                  && DR_GROUP_SIZE (vinfo_for_stmt (stmt)) 
++			> ncopies * group_size)
+                 {
+                   if (vect_print_dump_info (REPORT_SLP))
+                     {
+@@ -644,19 +679,22 @@
+   /* Strided loads were reached - stop the recursion.  */
+   if (stop_recursion)
+     {
++      VEC_safe_push (slp_tree, heap, *loads, *node);
+       if (permutation)
+         {
+-          VEC_safe_push (slp_tree, heap, *loads, *node);
++
++          *loads_permuted = true;
+           *inside_cost 
+             += targetm.vectorize.builtin_vectorization_cost (vec_perm, NULL, 0) 
+                * group_size;
+         }
+       else
+-        { 
+-          /* We don't check here complex numbers chains, so we keep them in
+-	     LOADS for further check in vect_supported_load_permutation_p.  */ 
++        {
++          /* We don't check here complex numbers chains, so we set
++             LOADS_PERMUTED for further check in
++             vect_supported_load_permutation_p.  */
+           if (rhs_code == REALPART_EXPR || rhs_code == IMAGPART_EXPR)
+-            VEC_safe_push (slp_tree, heap, *loads, *node);
++            *loads_permuted = true;
+         }
+ 
+       return true;
+@@ -675,7 +713,7 @@
+       if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &left_node, group_size,
+ 				inside_cost, outside_cost, ncopies_for_cost,
+ 				max_nunits, load_permutation, loads,
+-				vectorization_factor))
++				vectorization_factor, loads_permuted))
+ 	return false;
+ 
+       SLP_TREE_LEFT (*node) = left_node;
+@@ -693,7 +731,7 @@
+       if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &right_node, group_size,
+ 				inside_cost, outside_cost, ncopies_for_cost,
+ 				max_nunits, load_permutation, loads,
+-				vectorization_factor))
++				vectorization_factor, loads_permuted))
+ 	return false;
+ 
+       SLP_TREE_RIGHT (*node) = right_node;
+@@ -879,8 +917,10 @@
+   bool supported, bad_permutation = false;
+   sbitmap load_index;
+   slp_tree node, other_complex_node;
+-  gimple stmt, first = NULL, other_node_first;
++  gimple stmt, first = NULL, other_node_first, load, next_load, first_load;
+   unsigned complex_numbers = 0;
++  struct data_reference *dr;
++  bb_vec_info bb_vinfo;
+ 
+   /* FORNOW: permutations are only supported in SLP.  */
+   if (!slp_instn)
+@@ -1040,6 +1080,76 @@
+         }
+     }
+ 
++  /* In basic block vectorization we allow any subchain of an interleaving
++     chain.
++     FORNOW: not supported in loop SLP because of realignment compications.  */
++  bb_vinfo = STMT_VINFO_BB_VINFO (vinfo_for_stmt (stmt));
++  bad_permutation = false;
++  /* Check that for every node in the instance teh loads form a subchain.  */
++  if (bb_vinfo)
++    {
++      FOR_EACH_VEC_ELT (slp_tree, SLP_INSTANCE_LOADS (slp_instn), i, node)
++        {
++          next_load = NULL;
++          first_load = NULL;
++          FOR_EACH_VEC_ELT (gimple, SLP_TREE_SCALAR_STMTS (node), j, load)
++            {
++              if (!first_load)
++                first_load = DR_GROUP_FIRST_DR (vinfo_for_stmt (load));
++              else if (first_load
++                         != DR_GROUP_FIRST_DR (vinfo_for_stmt (load)))
++                {
++                  bad_permutation = true;
++	          break;
++	        }
++
++              if (j != 0 && next_load != load)
++                {
++                  bad_permutation = true;
++                  break;
++                }
++
++              next_load = DR_GROUP_NEXT_DR (vinfo_for_stmt (load));
++            }
++
++          if (bad_permutation)
++            break;
++        }
++
++      /* Check that the alignment of the first load in every subchain, i.e.,
++         the first statement in every load node, is supported.  */
++      if (!bad_permutation)
++        {
++          FOR_EACH_VEC_ELT (slp_tree, SLP_INSTANCE_LOADS (slp_instn), i, node)
++            {
++              first_load = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (node), 0);
++              if (first_load 
++		      != DR_GROUP_FIRST_DR (vinfo_for_stmt (first_load)))
++                {
++                  dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (first_load));
++                  if (vect_supportable_dr_alignment (dr, false)
++ 	               == dr_unaligned_unsupported)
++                    {
++   		      if (vect_print_dump_info (REPORT_SLP))
++		        {
++  	                  fprintf (vect_dump, "unsupported unaligned load ");
++                          print_gimple_stmt (vect_dump, first_load, 0,
++					     TDF_SLIM);
++                        }
++  		      bad_permutation = true;
++                      break;
++                    }
++	        }
++            }
++
++          if (!bad_permutation)
++            {
++              VEC_free (int, heap, SLP_INSTANCE_LOAD_PERMUTATION (slp_instn));
++              return true;
++    	    }
++        }
++    }
++
+   /* FORNOW: the only supported permutation is 0..01..1.. of length equal to
+      GROUP_SIZE and where each sequence of same drs is of GROUP_SIZE length as
+      well (unless it's reduction).  */
+@@ -1149,6 +1259,7 @@
+   VEC (int, heap) *load_permutation;
+   VEC (slp_tree, heap) *loads;
+   struct data_reference *dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (stmt));
++  bool loads_permuted = false;
+ 
+   if (dr)
+     {
+@@ -1238,7 +1349,7 @@
+   if (vect_build_slp_tree (loop_vinfo, bb_vinfo, &node, group_size,
+                            &inside_cost, &outside_cost, ncopies_for_cost,
+ 			   &max_nunits, &load_permutation, &loads,
+-			   vectorization_factor))
++			   vectorization_factor, &loads_permuted))
+     {
+       /* Calculate the unrolling factor based on the smallest type.  */
+       if (max_nunits > nunits)
+@@ -1263,7 +1374,8 @@
+       SLP_INSTANCE_LOADS (new_instance) = loads;
+       SLP_INSTANCE_FIRST_LOAD_STMT (new_instance) = NULL;
+       SLP_INSTANCE_LOAD_PERMUTATION (new_instance) = load_permutation;
+-      if (VEC_length (slp_tree, loads))
++
++      if (loads_permuted)
+         {
+           if (!vect_supported_load_permutation_p (new_instance, group_size,
+                                                   load_permutation))
+@@ -2542,10 +2654,11 @@
+   /* Loads should be inserted before the first load.  */
+   if (SLP_INSTANCE_FIRST_LOAD_STMT (instance)
+       && STMT_VINFO_STRIDED_ACCESS (stmt_info)
+-      && !REFERENCE_CLASS_P (gimple_get_lhs (stmt)))
++      && !REFERENCE_CLASS_P (gimple_get_lhs (stmt))
++      && SLP_INSTANCE_LOAD_PERMUTATION (instance))
+     si = gsi_for_stmt (SLP_INSTANCE_FIRST_LOAD_STMT (instance));
+   else if (is_pattern_stmt_p (stmt_info))
+-     si = gsi_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
++    si = gsi_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
+   else
+     si = gsi_for_stmt (stmt);
+ 
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-10-16 12:16:07 +0000
++++ new/gcc/tree-vect-stmts.c	2011-10-23 11:29:25 +0000
+@@ -4285,6 +4285,11 @@
+   if (strided_load)
+     {
+       first_stmt = DR_GROUP_FIRST_DR (stmt_info);
++      if (slp
++          && !SLP_INSTANCE_LOAD_PERMUTATION (slp_node_instance)
++          && first_stmt != VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0))
++        first_stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0);
++
+       /* Check if the chain of loads is already vectorized.  */
+       if (STMT_VINFO_VEC_STMT (vinfo_for_stmt (first_stmt)))
+ 	{
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch
new file mode 100644
index 0000000000..421a8fe3a9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch
@@ -0,0 +1,1505 @@
+	2011-10-18  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* doc/md.texi (vec_widen_ushiftl_hi, vec_widen_ushiftl_lo,
+	vec_widen_sshiftl_hi, vec_widen_sshiftl_lo): Document.
+	* tree-pretty-print.c (dump_generic_node): Handle WIDEN_LSHIFT_EXPR,
+	VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
+	(op_code_prio): Likewise.
+	(op_symbol_code): Handle WIDEN_LSHIFT_EXPR.
+	* optabs.c (optab_for_tree_code): Handle
+	VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
+	(init-optabs): Initialize optab codes for vec_widen_u/sshiftl_hi/lo.
+	* optabs.h (enum optab_index): Add OTI_vec_widen_u/sshiftl_hi/lo.
+	* genopinit.c (optabs): Initialize the new optabs.
+	* expr.c (expand_expr_real_2): Handle
+	VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
+	* gimple-pretty-print.c (dump_binary_rhs): Likewise.
+	* tree-vectorizer.h (NUM_PATTERNS): Increase to 8.
+	* tree.def (WIDEN_LSHIFT_EXPR, VEC_WIDEN_LSHIFT_HI_EXPR,
+	VEC_WIDEN_LSHIFT_LO_EXPR): New.
+	* cfgexpand.c (expand_debug_expr): Handle new tree codes.
+	* tree-vect-patterns.c (vect_vect_recog_func_ptrs): Add
+	vect_recog_widen_shift_pattern.
+	(vect_handle_widen_mult_by_const): Rename...
+	(vect_handle_widen_op_by_const): ...to this.  Handle shifts.
+	Add a new argument, update documentation.
+	(vect_recog_widen_mult_pattern): Assume that only second
+	operand can be constant.  Update call to
+	vect_handle_widen_op_by_const.
+	(vect_recog_over_widening_pattern): Fix typo.
+	(vect_recog_widen_shift_pattern): New.
+	* tree-vect-stmts.c (vectorizable_type_promotion): Handle
+	widening shifts.
+	(supportable_widening_operation): Likewise.
+	* tree-inline.c (estimate_operator_cost): Handle new tree codes.
+	* tree-vect-generic.c (expand_vector_operations_1): Likewise.
+	* tree-cfg.c (verify_gimple_assign_binary): Likewise.
+	* config/arm/neon.md (neon_vec_<US>shiftl_<mode>): New.
+	(vec_widen_<US>shiftl_lo_<mode>, neon_vec_<US>shiftl_hi_<mode>,
+	vec_widen_<US>shiftl_hi_<mode>, neon_vec_<US>shift_left_<mode>):
+	Likewise.
+	* config/arm/predicates.md (const_neon_scalar_shift_amount_operand):
+	New.
+	* config/arm/iterators.md (V_innermode): New.
+	* tree-vect-slp.c (vect_build_slp_tree): Require same shift operand
+	for widening shift.
+
+	gcc/testsuite
+	* testsuite/lib/target-supports.exp
+	(check_effective_target_vect_widen_shift): New.
+	* gcc.dg/vect/vect-widen-shift-s16.c: New.
+	* gcc.dg/vect/vect-widen-shift-s8.c: New.
+	* gcc.dg/vect/vect-widen-shift-u16.c: New.
+	* gcc.dg/vect/vect-widen-shift-u8.c: New.
+
+	2011-10-06  Jakub Jelinek  <jakub@redhat.com>
+
+	gcc/
+	* tree-vect-patterns.c (vect_pattern_recog_1): Use
+	vect_recog_func_ptr typedef for the first argument.
+	(vect_pattern_recog): Rename vect_recog_func_ptr variable
+	to vect_recog_func, use vect_recog_func_ptr typedef for it.
+
+	2011-10-16  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	PR tree-optimization/50727
+	* tree-vect-patterns.c (vect_operation_fits_smaller_type): Add
+	DEF_STMT to the list of statements to be replaced by the
+	pattern statements.
+
+	2011-10-09  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	PR tree-optimization/50635
+	* tree-vect-patterns.c (vect_handle_widen_mult_by_const): Add
+	DEF_STMT to the list of statements to be replaced by the
+	pattern statements.
+	(vect_handle_widen_mult_by_const): Don't check TYPE_OUT.
+
+=== modified file 'gcc/cfgexpand.c'
+--- old/gcc/cfgexpand.c	2011-07-01 09:19:21 +0000
++++ new/gcc/cfgexpand.c	2011-10-23 13:33:07 +0000
+@@ -3215,6 +3215,8 @@
+     case VEC_UNPACK_LO_EXPR:
+     case VEC_WIDEN_MULT_HI_EXPR:
+     case VEC_WIDEN_MULT_LO_EXPR:
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
+       return NULL;
+ 
+    /* Misc codes.  */
+
+=== modified file 'gcc/config/arm/iterators.md'
+--- old/gcc/config/arm/iterators.md	2011-09-06 14:29:24 +0000
++++ new/gcc/config/arm/iterators.md	2011-10-23 13:33:07 +0000
+@@ -388,6 +388,9 @@
+ (define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
+ (define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
+ 
++;; Mode attribute for vshll.
++(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
++
+ ;;----------------------------------------------------------------------------
+ ;; Code attributes
+ ;;----------------------------------------------------------------------------
+
+=== modified file 'gcc/config/arm/neon.md'
+--- old/gcc/config/arm/neon.md	2011-10-03 01:32:17 +0000
++++ new/gcc/config/arm/neon.md	2011-10-23 13:33:07 +0000
+@@ -5316,6 +5316,44 @@
+  }
+ )
+ 
++(define_insn "neon_vec_<US>shiftl_<mode>"
++ [(set (match_operand:<V_widen> 0 "register_operand" "=w")
++       (SE:<V_widen> (ashift:VW (match_operand:VW 1 "register_operand" "w")
++       (match_operand:<V_innermode> 2 "const_neon_scalar_shift_amount_operand" ""))))]
++  "TARGET_NEON"
++{
++  return "vshll.<US><V_sz_elem> %q0, %P1, %2";
++}
++  [(set_attr "neon_type" "neon_shift_1")]
++)
++
++(define_expand "vec_widen_<US>shiftl_lo_<mode>"
++  [(match_operand:<V_unpack> 0 "register_operand" "")
++   (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
++   (match_operand:SI 2 "immediate_operand" "i")]
++ "TARGET_NEON && !BYTES_BIG_ENDIAN"
++ {
++  emit_insn (gen_neon_vec_<US>shiftl_<V_half> (operands[0],
++		simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode, 0),
++		operands[2]));
++   DONE;
++ }
++)
++
++(define_expand "vec_widen_<US>shiftl_hi_<mode>"
++  [(match_operand:<V_unpack> 0 "register_operand" "")
++   (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
++   (match_operand:SI 2 "immediate_operand" "i")]
++ "TARGET_NEON && !BYTES_BIG_ENDIAN"
++ {
++  emit_insn (gen_neon_vec_<US>shiftl_<V_half> (operands[0],
++                simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode,
++				     GET_MODE_SIZE (<V_HALF>mode)),
++                operands[2]));
++   DONE;
++ }
++)
++
+ ;; Vectorize for non-neon-quad case
+ (define_insn "neon_unpack<US>_<mode>"
+  [(set (match_operand:<V_widen> 0 "register_operand" "=w")
+@@ -5392,6 +5430,34 @@
+  }
+ )
+ 
++(define_expand "vec_widen_<US>shiftl_hi_<mode>"
++ [(match_operand:<V_double_width> 0 "register_operand" "")
++   (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
++   (match_operand:SI 2 "immediate_operand" "i")]
++ "TARGET_NEON"
++ {
++   rtx tmpreg = gen_reg_rtx (<V_widen>mode);
++   emit_insn (gen_neon_vec_<US>shiftl_<mode> (tmpreg, operands[1], operands[2]));
++   emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
++
++   DONE;
++ }
++)
++
++(define_expand "vec_widen_<US>shiftl_lo_<mode>"
++  [(match_operand:<V_double_width> 0 "register_operand" "")
++   (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
++   (match_operand:SI 2 "immediate_operand" "i")]
++ "TARGET_NEON"
++ {
++   rtx tmpreg = gen_reg_rtx (<V_widen>mode);
++   emit_insn (gen_neon_vec_<US>shiftl_<mode> (tmpreg, operands[1], operands[2]));
++   emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
++
++   DONE;
++ }
++)
++
+ ;; The case when using all quad registers.
+ (define_insn "vec_pack_trunc_<mode>"
+  [(set (match_operand:<V_narrow_pack> 0 "register_operand" "=&w")
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-10-10 11:43:28 +0000
++++ new/gcc/config/arm/predicates.md	2011-10-23 13:33:07 +0000
+@@ -136,6 +136,11 @@
+ 	    (match_operand 0 "s_register_operand"))
+        (match_operand 0 "const_int_operand")))
+ 
++(define_predicate "const_neon_scalar_shift_amount_operand"
++  (and (match_code "const_int")
++       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
++	&& ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
++
+ (define_predicate "arm_add_operand"
+   (ior (match_operand 0 "arm_rhs_operand")
+        (match_operand 0 "arm_neg_immediate_operand")))
+
+=== modified file 'gcc/doc/md.texi'
+--- old/gcc/doc/md.texi	2011-08-13 08:32:32 +0000
++++ new/gcc/doc/md.texi	2011-10-23 13:33:07 +0000
+@@ -4230,6 +4230,17 @@
+ elements of the two vectors, and put the N/2 products of size 2*S in the
+ output vector (operand 0).
+ 
++@cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
++@cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
++@cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
++@cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
++@item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
++@itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
++Signed/Unsigned widening shift left.  The first input (operand 1) is a vector
++with N signed/unsigned elements of size S@.  Operand 2 is a constant.  Shift
++the high/low elements of operand 1, and put the N/2 results of size 2*S in the
++output vector (operand 0).
++
+ @cindex @code{mulhisi3} instruction pattern
+ @item @samp{mulhisi3}
+ Multiply operands 1 and 2, which have mode @code{HImode}, and store
+
+=== modified file 'gcc/expr.c'
+--- old/gcc/expr.c	2011-08-25 11:42:09 +0000
++++ new/gcc/expr.c	2011-10-23 13:33:07 +0000
+@@ -8290,6 +8290,19 @@
+ 	return target;
+       }
+ 
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
++      {
++        tree oprnd0 = treeop0;
++        tree oprnd1 = treeop1;
++
++        expand_operands (oprnd0, oprnd1, NULL_RTX, &op0, &op1, EXPAND_NORMAL);
++        target = expand_widen_pattern_expr (ops, op0, op1, NULL_RTX,
++                                            target, unsignedp);
++        gcc_assert (target);
++        return target;
++      }
++
+     case VEC_PACK_TRUNC_EXPR:
+     case VEC_PACK_SAT_EXPR:
+     case VEC_PACK_FIX_TRUNC_EXPR:
+
+=== modified file 'gcc/genopinit.c'
+--- old/gcc/genopinit.c	2011-07-15 13:06:31 +0000
++++ new/gcc/genopinit.c	2011-10-23 13:33:07 +0000
+@@ -268,6 +268,10 @@
+   "set_optab_handler (vec_widen_umult_lo_optab, $A, CODE_FOR_$(vec_widen_umult_lo_$a$))",
+   "set_optab_handler (vec_widen_smult_hi_optab, $A, CODE_FOR_$(vec_widen_smult_hi_$a$))",
+   "set_optab_handler (vec_widen_smult_lo_optab, $A, CODE_FOR_$(vec_widen_smult_lo_$a$))",
++  "set_optab_handler (vec_widen_ushiftl_hi_optab, $A, CODE_FOR_$(vec_widen_ushiftl_hi_$a$))",
++  "set_optab_handler (vec_widen_ushiftl_lo_optab, $A, CODE_FOR_$(vec_widen_ushiftl_lo_$a$))",
++  "set_optab_handler (vec_widen_sshiftl_hi_optab, $A, CODE_FOR_$(vec_widen_sshiftl_hi_$a$))",
++  "set_optab_handler (vec_widen_sshiftl_lo_optab, $A, CODE_FOR_$(vec_widen_sshiftl_lo_$a$))",
+   "set_optab_handler (vec_unpacks_hi_optab, $A, CODE_FOR_$(vec_unpacks_hi_$a$))",
+   "set_optab_handler (vec_unpacks_lo_optab, $A, CODE_FOR_$(vec_unpacks_lo_$a$))",
+   "set_optab_handler (vec_unpacku_hi_optab, $A, CODE_FOR_$(vec_unpacku_hi_$a$))",
+
+=== modified file 'gcc/gimple-pretty-print.c'
+--- old/gcc/gimple-pretty-print.c	2011-05-05 15:42:22 +0000
++++ new/gcc/gimple-pretty-print.c	2011-10-23 13:33:07 +0000
+@@ -343,6 +343,8 @@
+     case VEC_EXTRACT_ODD_EXPR:
+     case VEC_INTERLEAVE_HIGH_EXPR:
+     case VEC_INTERLEAVE_LOW_EXPR:
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
+       for (p = tree_code_name [(int) code]; *p; p++)
+ 	pp_character (buffer, TOUPPER (*p));
+       pp_string (buffer, " <");
+
+=== modified file 'gcc/optabs.c'
+--- old/gcc/optabs.c	2011-08-11 15:46:01 +0000
++++ new/gcc/optabs.c	2011-10-23 13:33:07 +0000
+@@ -454,6 +454,14 @@
+       return TYPE_UNSIGNED (type) ?
+ 	vec_widen_umult_lo_optab : vec_widen_smult_lo_optab;
+ 
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++      return TYPE_UNSIGNED (type) ?
++        vec_widen_ushiftl_hi_optab : vec_widen_sshiftl_hi_optab;
++
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
++      return TYPE_UNSIGNED (type) ?
++        vec_widen_ushiftl_lo_optab : vec_widen_sshiftl_lo_optab;
++
+     case VEC_UNPACK_HI_EXPR:
+       return TYPE_UNSIGNED (type) ?
+ 	vec_unpacku_hi_optab : vec_unpacks_hi_optab;
+@@ -6351,6 +6359,10 @@
+   init_optab (vec_widen_umult_lo_optab, UNKNOWN);
+   init_optab (vec_widen_smult_hi_optab, UNKNOWN);
+   init_optab (vec_widen_smult_lo_optab, UNKNOWN);
++  init_optab (vec_widen_ushiftl_hi_optab, UNKNOWN);
++  init_optab (vec_widen_ushiftl_lo_optab, UNKNOWN);
++  init_optab (vec_widen_sshiftl_hi_optab, UNKNOWN);
++  init_optab (vec_widen_sshiftl_lo_optab, UNKNOWN);
+   init_optab (vec_unpacks_hi_optab, UNKNOWN);
+   init_optab (vec_unpacks_lo_optab, UNKNOWN);
+   init_optab (vec_unpacku_hi_optab, UNKNOWN);
+
+=== modified file 'gcc/optabs.h'
+--- old/gcc/optabs.h	2011-07-27 14:12:45 +0000
++++ new/gcc/optabs.h	2011-10-23 13:33:07 +0000
+@@ -350,6 +350,12 @@
+   OTI_vec_widen_umult_lo,
+   OTI_vec_widen_smult_hi,
+   OTI_vec_widen_smult_lo,
++  /* Widening shift left.
++     The high/low part of the resulting vector is returned.  */
++  OTI_vec_widen_ushiftl_hi,
++  OTI_vec_widen_ushiftl_lo,
++  OTI_vec_widen_sshiftl_hi,
++  OTI_vec_widen_sshiftl_lo,
+   /* Extract and widen the high/low part of a vector of signed or
+      floating point elements.  */
+   OTI_vec_unpacks_hi,
+@@ -542,6 +548,10 @@
+ #define vec_widen_umult_lo_optab (&optab_table[OTI_vec_widen_umult_lo])
+ #define vec_widen_smult_hi_optab (&optab_table[OTI_vec_widen_smult_hi])
+ #define vec_widen_smult_lo_optab (&optab_table[OTI_vec_widen_smult_lo])
++#define vec_widen_ushiftl_hi_optab (&optab_table[OTI_vec_widen_ushiftl_hi])
++#define vec_widen_ushiftl_lo_optab (&optab_table[OTI_vec_widen_ushiftl_lo])
++#define vec_widen_sshiftl_hi_optab (&optab_table[OTI_vec_widen_sshiftl_hi])
++#define vec_widen_sshiftl_lo_optab (&optab_table[OTI_vec_widen_sshiftl_lo])
+ #define vec_unpacks_hi_optab (&optab_table[OTI_vec_unpacks_hi])
+ #define vec_unpacks_lo_optab (&optab_table[OTI_vec_unpacks_lo])
+ #define vec_unpacku_hi_optab (&optab_table[OTI_vec_unpacku_hi])
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c	2011-10-23 13:33:07 +0000
+@@ -0,0 +1,107 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++#define C 16
++
++__attribute__ ((noinline)) void
++foo (short *src, int *dst)
++{
++  int i;
++  short b, b0, b1, b2, b3, *s = src;
++  int *d = dst;
++
++  for (i = 0; i < N/4; i++)
++    {
++      b0 = *s++;
++      b1 = *s++;
++      b2 = *s++;
++      b3 = *s++;
++      *d = b0 << C;
++      d++;
++      *d = b1 << C;
++      d++;
++      *d = b2 << C;
++      d++;
++      *d = b3 << C;
++      d++;
++    }
++
++  s = src;
++  d = dst;
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      if (*d != b << C)
++        abort ();
++      d++;
++    }
++
++  s = src;
++  d = dst;
++  for (i = 0; i < N/4; i++)
++    {
++      b0 = *s++;
++      b1 = *s++;
++      b2 = *s++;
++      b3 = *s++;
++      *d = b0 << C;
++      d++;
++      *d = b1 << C;
++      d++;
++      *d = b2 << C;
++      d++;
++      *d = b3 << 6;
++      d++;
++    }
++
++  s = src;
++  d = dst;
++  for (i = 0; i < N/4; i++)
++    {
++      b = *s++;
++      if (*d != b << C)
++        abort ();
++      d++;
++      b = *s++;
++      if (*d != b << C)
++        abort ();
++      d++;
++      b = *s++;
++      if (*d != b << C)
++        abort ();
++      d++;
++      b = *s++;
++      if (*d != b << 6)
++        abort ();
++      d++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  short in[N];
++  int out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 8 "vect" { target vect_widen_shift } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c	2011-10-23 13:33:07 +0000
+@@ -0,0 +1,58 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++#define C 12
++
++__attribute__ ((noinline)) void
++foo (char *src, int *dst)
++{
++  int i;
++  char b, *s = src;
++  int *d = dst;
++
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      *d = b << C;
++      d++;
++    }
++
++  s = src;
++  d = dst;
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      if (*d != b << C)
++        abort ();
++      d++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  char in[N];
++  int out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c	2011-10-23 13:33:07 +0000
+@@ -0,0 +1,58 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++#define C 7
++
++__attribute__ ((noinline)) void
++foo (unsigned short *src, unsigned int *dst)
++{
++  int i;
++  unsigned short b, *s = src;
++  unsigned int *d = dst;
++
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      *d = b << C;
++      d++;
++    }
++
++  s = src;
++  d = dst;
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      if (*d != b << C)
++        abort ();
++      d++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  unsigned short in[N];
++  unsigned int out[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c	2011-10-23 13:33:07 +0000
+@@ -0,0 +1,65 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 64
++#define C1 10
++#define C2 5
++
++__attribute__ ((noinline)) void
++foo (unsigned char *src, unsigned int *dst1, unsigned int *dst2)
++{
++  int i;
++  unsigned char b, *s = src;
++  unsigned int *d1 = dst1, *d2 = dst2;
++
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      *d1 = b << C1;
++      d1++;
++      *d2 = b << C2;
++      d2++;
++    }
++
++  s = src;
++  d1 = dst1;
++  d2 = dst2;
++  for (i = 0; i < N; i++)
++    {
++      b = *s++;
++      if (*d1 != b << C1 || *d2 != b << C2)
++        abort ();
++      d1++;
++      d2++;
++    }
++}
++
++int main (void)
++{
++  int i;
++  unsigned char in[N];
++  unsigned int out1[N];
++  unsigned int out2[N];
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      in[i] = i;
++      out1[i] = 255;
++      out2[i] = 255;
++      __asm__ volatile ("");
++    }
++
++  foo (in, out1, out2);
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
++
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-10-06 11:08:08 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-10-23 13:33:07 +0000
+@@ -2783,6 +2783,26 @@
+ }
+ 
+ # Return 1 if the target plus current options supports a vector
++# widening shift, 0 otherwise.
++#
++# This won't change for different subtargets so cache the result.
++
++proc check_effective_target_vect_widen_shift { } {
++    global et_vect_widen_shift_saved
++
++    if [info exists et_vect_shift_saved] {
++        verbose "check_effective_target_vect_widen_shift: using cached result" 2
++    } else {
++        set et_vect_widen_shift_saved 0
++        if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
++            set et_vect_widen_shift_saved 1
++        }
++    }
++    verbose "check_effective_target_vect_widen_shift: returning $et_vect_widen_shift_saved" 2
++    return $et_vect_widen_shift_saved
++}
++
++# Return 1 if the target plus current options supports a vector
+ # dot-product of signed chars, 0 otherwise.
+ #
+ # This won't change for different subtargets so cache the result.
+
+=== modified file 'gcc/tree-cfg.c'
+--- old/gcc/tree-cfg.c	2011-07-15 13:44:50 +0000
++++ new/gcc/tree-cfg.c	2011-10-23 13:33:07 +0000
+@@ -3473,6 +3473,44 @@
+ 	return false;
+       }
+ 
++    case WIDEN_LSHIFT_EXPR:
++      {
++        if (!INTEGRAL_TYPE_P (lhs_type)
++            || !INTEGRAL_TYPE_P (rhs1_type)
++            || TREE_CODE (rhs2) != INTEGER_CST
++            || (2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type)))
++          {
++            error ("type mismatch in widening vector shift expression");
++            debug_generic_expr (lhs_type);
++            debug_generic_expr (rhs1_type);
++            debug_generic_expr (rhs2_type);
++            return true;
++          }
++
++        return false;
++      }
++
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
++      {
++        if (TREE_CODE (rhs1_type) != VECTOR_TYPE
++            || TREE_CODE (lhs_type) != VECTOR_TYPE
++            || !INTEGRAL_TYPE_P (TREE_TYPE (rhs1_type))
++            || !INTEGRAL_TYPE_P (TREE_TYPE (lhs_type))
++            || TREE_CODE (rhs2) != INTEGER_CST
++            || (2 * TYPE_PRECISION (TREE_TYPE (rhs1_type))
++                > TYPE_PRECISION (TREE_TYPE (lhs_type))))
++          {
++            error ("type mismatch in widening vector shift expression");
++            debug_generic_expr (lhs_type);
++            debug_generic_expr (rhs1_type);
++            debug_generic_expr (rhs2_type);
++            return true;
++          }
++
++        return false;
++      }
++
+     case PLUS_EXPR:
+     case MINUS_EXPR:
+       {
+
+=== modified file 'gcc/tree-inline.c'
+--- old/gcc/tree-inline.c	2011-08-13 08:32:32 +0000
++++ new/gcc/tree-inline.c	2011-10-23 13:33:07 +0000
+@@ -3343,6 +3343,7 @@
+     case DOT_PROD_EXPR:
+     case WIDEN_MULT_PLUS_EXPR:
+     case WIDEN_MULT_MINUS_EXPR:
++    case WIDEN_LSHIFT_EXPR:
+ 
+     case VEC_WIDEN_MULT_HI_EXPR:
+     case VEC_WIDEN_MULT_LO_EXPR:
+@@ -3357,6 +3358,8 @@
+     case VEC_EXTRACT_ODD_EXPR:
+     case VEC_INTERLEAVE_HIGH_EXPR:
+     case VEC_INTERLEAVE_LOW_EXPR:
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
+ 
+       return 1;
+ 
+
+=== modified file 'gcc/tree-pretty-print.c'
+--- old/gcc/tree-pretty-print.c	2010-11-05 09:00:50 +0000
++++ new/gcc/tree-pretty-print.c	2011-10-23 13:33:07 +0000
+@@ -1539,6 +1539,7 @@
+     case RROTATE_EXPR:
+     case VEC_LSHIFT_EXPR:
+     case VEC_RSHIFT_EXPR:
++    case WIDEN_LSHIFT_EXPR:
+     case BIT_IOR_EXPR:
+     case BIT_XOR_EXPR:
+     case BIT_AND_EXPR:
+@@ -2209,6 +2210,22 @@
+       pp_string (buffer, " > ");
+       break;
+ 
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++      pp_string (buffer, " VEC_WIDEN_LSHIFT_HI_EXPR < ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false);
++      pp_string (buffer, " > ");
++      break;
++
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
++      pp_string (buffer, " VEC_WIDEN_LSHIFT_HI_EXPR < ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
++      pp_string (buffer, ", ");
++      dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false);
++      pp_string (buffer, " > ");
++      break;
++
+     case VEC_UNPACK_HI_EXPR:
+       pp_string (buffer, " VEC_UNPACK_HI_EXPR < ");
+       dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
+@@ -2531,6 +2548,9 @@
+     case RSHIFT_EXPR:
+     case LROTATE_EXPR:
+     case RROTATE_EXPR:
++    case VEC_WIDEN_LSHIFT_HI_EXPR:
++    case VEC_WIDEN_LSHIFT_LO_EXPR:
++    case WIDEN_LSHIFT_EXPR:
+       return 11;
+ 
+     case WIDEN_SUM_EXPR:
+@@ -2706,6 +2726,9 @@
+     case VEC_RSHIFT_EXPR:
+       return "v>>";
+ 
++    case WIDEN_LSHIFT_EXPR:
++      return "w<<";
++
+     case POINTER_PLUS_EXPR:
+       return "+";
+ 
+
+=== modified file 'gcc/tree-vect-generic.c'
+--- old/gcc/tree-vect-generic.c	2011-02-08 14:16:50 +0000
++++ new/gcc/tree-vect-generic.c	2011-10-23 13:33:07 +0000
+@@ -552,7 +552,9 @@
+       || code == VEC_UNPACK_LO_EXPR
+       || code == VEC_PACK_TRUNC_EXPR
+       || code == VEC_PACK_SAT_EXPR
+-      || code == VEC_PACK_FIX_TRUNC_EXPR)
++      || code == VEC_PACK_FIX_TRUNC_EXPR
++      || code == VEC_WIDEN_LSHIFT_HI_EXPR
++      || code == VEC_WIDEN_LSHIFT_LO_EXPR)
+     type = TREE_TYPE (rhs1);
+ 
+   /* Optabs will try converting a negation into a subtraction, so
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2011-09-05 06:23:37 +0000
++++ new/gcc/tree-vect-patterns.c	2011-10-23 13:33:07 +0000
+@@ -48,12 +48,15 @@
+ static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
+ static gimple vect_recog_over_widening_pattern (VEC (gimple, heap) **, tree *,
+                                                  tree *);
++static gimple vect_recog_widen_shift_pattern (VEC (gimple, heap) **,
++                                       tree *, tree *);
+ static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
+ 	vect_recog_widen_mult_pattern,
+ 	vect_recog_widen_sum_pattern,
+ 	vect_recog_dot_prod_pattern,
+ 	vect_recog_pow_pattern,
+-        vect_recog_over_widening_pattern};
++        vect_recog_over_widening_pattern,
++	vect_recog_widen_shift_pattern};
+ 
+ 
+ /* Function widened_name_p
+@@ -331,27 +334,38 @@
+   return pattern_stmt;
+ }
+ 
+-/* Handle two cases of multiplication by a constant.  The first one is when
+-   the constant, CONST_OPRND, fits the type (HALF_TYPE) of the second
+-   operand (OPRND).  In that case, we can peform widen-mult from HALF_TYPE to
+-   TYPE.
++
++/* Handle widening operation by a constant.  At the moment we support MULT_EXPR
++   and LSHIFT_EXPR.
++
++   For MULT_EXPR we check that CONST_OPRND fits HALF_TYPE, and for LSHIFT_EXPR
++   we check that CONST_OPRND is less or equal to the size of HALF_TYPE.
+ 
+    Otherwise, if the type of the result (TYPE) is at least 4 times bigger than
+-   HALF_TYPE, and CONST_OPRND fits an intermediate type (2 times smaller than
+-   TYPE), we can perform widen-mult from the intermediate type to TYPE and
+-   replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t;  */
++   HALF_TYPE, and there is an intermediate type (2 times smaller than TYPE)
++   that satisfies the above restrictions,  we can perform a widening opeartion
++   from the intermediate type to TYPE and replace a_T = (TYPE) a_t;
++   with a_it = (interm_type) a_t;  */
+ 
+ static bool
+-vect_handle_widen_mult_by_const (gimple stmt, tree const_oprnd, tree *oprnd,
+-                                 VEC (gimple, heap) **stmts, tree type,
+-                                 tree *half_type, gimple def_stmt)
++vect_handle_widen_op_by_const (gimple stmt, enum tree_code code,
++                               tree const_oprnd, tree *oprnd,
++                               VEC (gimple, heap) **stmts, tree type,
++                               tree *half_type, gimple def_stmt)
+ {
+   tree new_type, new_oprnd, tmp;
+   gimple new_stmt;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
+   struct loop *loop = LOOP_VINFO_LOOP (loop_info);
+ 
+-  if (int_fits_type_p (const_oprnd, *half_type))
++  if (code != MULT_EXPR && code != LSHIFT_EXPR)
++    return false;
++
++  if (((code == MULT_EXPR && int_fits_type_p (const_oprnd, *half_type))
++        || (code == LSHIFT_EXPR
++            && compare_tree_int (const_oprnd, TYPE_PRECISION (*half_type))
++                != 1))
++      && TYPE_PRECISION (type) == (TYPE_PRECISION (*half_type) * 2))
+     {
+       /* CONST_OPRND is a constant of HALF_TYPE.  */
+       *oprnd = gimple_assign_rhs1 (def_stmt);
+@@ -364,14 +378,16 @@
+       || !vinfo_for_stmt (def_stmt))
+     return false;
+ 
+-  /* TYPE is 4 times bigger than HALF_TYPE, try widen-mult for
++  /* TYPE is 4 times bigger than HALF_TYPE, try widening operation for
+      a type 2 times bigger than HALF_TYPE.  */
+   new_type = build_nonstandard_integer_type (TYPE_PRECISION (type) / 2,
+                                              TYPE_UNSIGNED (type));
+-  if (!int_fits_type_p (const_oprnd, new_type))
++  if ((code == MULT_EXPR && !int_fits_type_p (const_oprnd, new_type))
++      || (code == LSHIFT_EXPR
++          && compare_tree_int (const_oprnd, TYPE_PRECISION (new_type)) == 1))
+     return false;
+ 
+-  /* Use NEW_TYPE for widen_mult.  */
++  /* Use NEW_TYPE for widening operation.  */
+   if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
+     {
+       new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
+@@ -381,6 +397,7 @@
+           || TREE_TYPE (gimple_assign_lhs (new_stmt)) != new_type)
+         return false;
+ 
++      VEC_safe_push (gimple, heap, *stmts, def_stmt);
+       *oprnd = gimple_assign_lhs (new_stmt);
+     }
+   else
+@@ -392,7 +409,6 @@
+       new_oprnd = make_ssa_name (tmp, NULL);
+       new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd, *oprnd,
+                                                NULL_TREE);
+-      SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
+       STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
+       VEC_safe_push (gimple, heap, *stmts, def_stmt);
+       *oprnd = new_oprnd;
+@@ -402,7 +418,6 @@
+   return true;
+ }
+ 
+-
+ /* Function vect_recog_widen_mult_pattern
+ 
+    Try to find the following pattern:
+@@ -491,7 +506,7 @@
+   enum tree_code dummy_code;
+   int dummy_int;
+   VEC (tree, heap) *dummy_vec;
+-  bool op0_ok, op1_ok;
++  bool op1_ok;
+ 
+   if (!is_gimple_assign (last_stmt))
+     return NULL;
+@@ -511,38 +526,23 @@
+     return NULL;
+ 
+   /* Check argument 0.  */
+-  op0_ok = widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false);
++  if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
++    return NULL;
+   /* Check argument 1.  */
+   op1_ok = widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1, false);
+ 
+-  /* In case of multiplication by a constant one of the operands may not match
+-     the pattern, but not both.  */
+-  if (!op0_ok && !op1_ok)
+-     return NULL;
+-
+-  if (op0_ok && op1_ok)
++  if (op1_ok)
+     {
+       oprnd0 = gimple_assign_rhs1 (def_stmt0);
+       oprnd1 = gimple_assign_rhs1 (def_stmt1);
+     }
+-  else if (!op0_ok)
+-    {
+-      if (TREE_CODE (oprnd0) == INTEGER_CST
+-          && TREE_CODE (half_type1) == INTEGER_TYPE
+-          && vect_handle_widen_mult_by_const (last_stmt, oprnd0, &oprnd1, 
+-		                              stmts, type,
+-                                              &half_type1, def_stmt1))
+-        half_type0 = half_type1;
+-      else
+-        return NULL;
+-    }
+-  else if (!op1_ok)
++  else
+     {
+       if (TREE_CODE (oprnd1) == INTEGER_CST
+           && TREE_CODE (half_type0) == INTEGER_TYPE
+-          && vect_handle_widen_mult_by_const (last_stmt, oprnd1, &oprnd0,
+-		                              stmts, type,
+-                                              &half_type0, def_stmt0))
++          && vect_handle_widen_op_by_const (last_stmt, MULT_EXPR, oprnd1,
++                                            &oprnd0, stmts, type,
++                                            &half_type0, def_stmt0))
+         half_type1 = half_type0;
+       else
+         return NULL;
+@@ -998,6 +998,7 @@
+                   || TREE_TYPE (gimple_assign_lhs (new_stmt)) != interm_type)
+                 return false;
+ 
++              VEC_safe_push (gimple, heap, *stmts, def_stmt);
+               oprnd = gimple_assign_lhs (new_stmt);
+             }
+           else
+@@ -1128,7 +1129,7 @@
+          statetments, except for the case when the last statement in the
+          sequence doesn't have a corresponding pattern statement.  In such
+          case we associate the last pattern statement with the last statement
+-         in the sequence.  Therefore, we only add an original statetement to
++         in the sequence.  Therefore, we only add the original statement to
+          the list if we know that it is not the last.  */
+       if (prev_stmt)
+         VEC_safe_push (gimple, heap, *stmts, prev_stmt);
+@@ -1215,6 +1216,231 @@
+ }
+ 
+ 
++/* Detect widening shift pattern:
++
++   type a_t;
++   TYPE a_T, res_T;
++
++   S1 a_t = ;
++   S2 a_T = (TYPE) a_t;
++   S3 res_T = a_T << CONST;
++
++  where type 'TYPE' is at least double the size of type 'type'.
++
++  Also detect unsigned cases:
++
++  unsigned type a_t;
++  unsigned TYPE u_res_T;
++  TYPE a_T, res_T;
++
++  S1 a_t = ;
++  S2 a_T = (TYPE) a_t;
++  S3 res_T = a_T << CONST;
++  S4 u_res_T = (unsigned TYPE) res_T;
++
++  And a case when 'TYPE' is 4 times bigger than 'type'.  In that case we
++  create an additional pattern stmt for S2 to create a variable of an
++  intermediate type, and perform widen-shift on the intermediate type:
++
++  type a_t;
++  interm_type a_it;
++  TYPE a_T, res_T, res_T';
++
++  S1 a_t = ;
++  S2 a_T = (TYPE) a_t;
++      '--> a_it = (interm_type) a_t;
++  S3 res_T = a_T << CONST;
++      '--> res_T' = a_it <<* CONST;
++
++  Input/Output:
++
++  * STMTS: Contains a stmt from which the pattern search begins.
++    In case of unsigned widen-shift, the original stmt (S3) is replaced with S4
++    in STMTS.  When an intermediate type is used and a pattern statement is
++    created for S2, we also put S2 here (before S3).
++
++  Output:
++
++  * TYPE_IN: The type of the input arguments to the pattern.
++
++  * TYPE_OUT: The type of the output of this pattern.
++
++  * Return value: A new stmt that will be used to replace the sequence of
++    stmts that constitute the pattern.  In this case it will be:
++    WIDEN_LSHIFT_EXPR <a_t, CONST>.  */
++
++static gimple
++vect_recog_widen_shift_pattern (VEC (gimple, heap) **stmts,
++                                tree *type_in, tree *type_out)
++{
++  gimple last_stmt = VEC_pop (gimple, *stmts);
++  gimple def_stmt0;
++  tree oprnd0, oprnd1;
++  tree type, half_type0;
++  gimple pattern_stmt, orig_stmt = NULL;
++  tree vectype, vectype_out = NULL_TREE;
++  tree dummy;
++  tree var;
++  enum tree_code dummy_code;
++  int dummy_int;
++  VEC (tree, heap) * dummy_vec;
++  gimple use_stmt = NULL;
++  bool over_widen = false;
++
++  if (!is_gimple_assign (last_stmt) || !vinfo_for_stmt (last_stmt))
++    return NULL;
++
++  orig_stmt = last_stmt;
++  if (STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (last_stmt)))
++    {
++      /* This statement was also detected as over-widening operation (it can't
++         be any other pattern, because only over-widening detects shifts).
++         LAST_STMT is the final type demotion statement, but its related
++         statement is shift.  We analyze the related statement to catch cases:
++
++         orig code:
++          type a_t;
++          itype res;
++          TYPE a_T, res_T;
++
++          S1 a_T = (TYPE) a_t;
++          S2 res_T = a_T << CONST;
++          S3 res = (itype)res_T;
++
++          (size of type * 2 <= size of itype
++           and size of itype * 2 <= size of TYPE)
++
++         code after over-widening pattern detection:
++
++          S1 a_T = (TYPE) a_t;
++               --> a_it = (itype) a_t;
++          S2 res_T = a_T << CONST;
++          S3 res = (itype)res_T;  <--- LAST_STMT
++               --> res = a_it << CONST;
++
++         after widen_shift:
++
++          S1 a_T = (TYPE) a_t;
++               --> a_it = (itype) a_t; - redundant
++          S2 res_T = a_T << CONST;
++          S3 res = (itype)res_T;
++               --> res = a_t w<< CONST;
++
++      i.e., we replace the three statements with res = a_t w<< CONST.  */
++      last_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (last_stmt));
++      over_widen = true;
++    }
++
++  if (gimple_assign_rhs_code (last_stmt) != LSHIFT_EXPR)
++    return NULL;
++
++  oprnd0 = gimple_assign_rhs1 (last_stmt);
++  oprnd1 = gimple_assign_rhs2 (last_stmt);
++  if (TREE_CODE (oprnd0) != SSA_NAME || TREE_CODE (oprnd1) != INTEGER_CST)
++    return NULL;
++
++  /* Check operand 0: it has to be defined by a type promotion.  */
++  if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
++    return NULL;
++
++  /* Check operand 1: has to be positive.  We check that it fits the type
++     in vect_handle_widen_op_by_const ().  */
++  if (tree_int_cst_compare (oprnd1, size_zero_node) <= 0)
++    return NULL;
++
++  oprnd0 = gimple_assign_rhs1 (def_stmt0);
++  type = gimple_expr_type (last_stmt);
++
++  /* Check if this a widening operation.  */
++  if (!vect_handle_widen_op_by_const (last_stmt, LSHIFT_EXPR, oprnd1,
++                                      &oprnd0, stmts,
++                                      type, &half_type0, def_stmt0))
++    return NULL;
++
++  /* Handle unsigned case.  Look for
++     S4  u_res_T = (unsigned TYPE) res_T;
++     Use unsigned TYPE as the type for WIDEN_LSHIFT_EXPR.  */
++  if (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (half_type0))
++    {
++      tree lhs = gimple_assign_lhs (last_stmt), use_lhs;
++      imm_use_iterator imm_iter;
++      use_operand_p use_p;
++      int nuses = 0;
++      tree use_type;
++
++      if (over_widen)
++        {
++          /* In case of over-widening pattern, S4 should be ORIG_STMT itself.
++             We check here that TYPE is the correct type for the operation,
++             i.e., it's the type of the original result.  */
++          tree orig_type = gimple_expr_type (orig_stmt);
++          if ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (orig_type))
++              || (TYPE_PRECISION (type) != TYPE_PRECISION (orig_type)))
++            return NULL;
++        }
++      else
++        {
++          FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
++            {
++              if (is_gimple_debug (USE_STMT (use_p)))
++                continue;
++              use_stmt = USE_STMT (use_p);
++              nuses++;
++            }
++
++          if (nuses != 1 || !is_gimple_assign (use_stmt)
++              || !CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (use_stmt)))
++            return NULL;
++
++          use_lhs = gimple_assign_lhs (use_stmt);
++          use_type = TREE_TYPE (use_lhs);
++
++          if (!INTEGRAL_TYPE_P (use_type)
++              || (TYPE_UNSIGNED (type) == TYPE_UNSIGNED (use_type))
++              || (TYPE_PRECISION (type) != TYPE_PRECISION (use_type)))
++            return NULL;
++
++          type = use_type;
++        }
++    }
++
++  /* Pattern detected.  */
++  if (vect_print_dump_info (REPORT_DETAILS))
++    fprintf (vect_dump, "vect_recog_widen_shift_pattern: detected: ");
++
++  /* Check target support.  */
++  vectype = get_vectype_for_scalar_type (half_type0);
++  vectype_out = get_vectype_for_scalar_type (type);
++
++  if (!vectype
++      || !vectype_out
++      || !supportable_widening_operation (WIDEN_LSHIFT_EXPR, last_stmt,
++                                          vectype_out, vectype,
++                                          &dummy, &dummy, &dummy_code,
++                                          &dummy_code, &dummy_int,
++                                          &dummy_vec))
++    return NULL;
++
++  *type_in = vectype;
++  *type_out = vectype_out;
++
++  /* Pattern supported.  Create a stmt to be used to replace the pattern.  */
++  var = vect_recog_temp_ssa_var (type, NULL);
++  pattern_stmt =
++    gimple_build_assign_with_ops (WIDEN_LSHIFT_EXPR, var, oprnd0, oprnd1);
++
++  if (vect_print_dump_info (REPORT_DETAILS))
++    print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
++
++  if (use_stmt)
++    last_stmt = use_stmt;
++  else
++    last_stmt = orig_stmt;
++
++  VEC_safe_push (gimple, heap, *stmts, last_stmt);
++  return pattern_stmt;
++}
++
+ /* Mark statements that are involved in a pattern.  */
+ 
+ static inline void
+@@ -1278,7 +1504,8 @@
+ static void
+ vect_pattern_recog_1 (
+ 	gimple (* vect_recog_func) (VEC (gimple, heap) **, tree *, tree *),
+-	gimple_stmt_iterator si)
++	gimple_stmt_iterator si,
++	VEC (gimple, heap) **stmts_to_replace)
+ {
+   gimple stmt = gsi_stmt (si), pattern_stmt;
+   stmt_vec_info stmt_info;
+@@ -1288,14 +1515,14 @@
+   enum tree_code code;
+   int i;
+   gimple next;
+-  VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
+ 
+-  VEC_quick_push (gimple, stmts_to_replace, stmt);
+-  pattern_stmt = (* vect_recog_func) (&stmts_to_replace, &type_in, &type_out);
++  VEC_truncate (gimple, *stmts_to_replace, 0);
++  VEC_quick_push (gimple, *stmts_to_replace, stmt);
++  pattern_stmt = (* vect_recog_func) (stmts_to_replace, &type_in, &type_out);
+   if (!pattern_stmt)
+     return;
+ 
+-  stmt = VEC_last (gimple, stmts_to_replace);
++  stmt = VEC_last (gimple, *stmts_to_replace);
+   stmt_info = vinfo_for_stmt (stmt);
+   loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
+  
+@@ -1303,8 +1530,6 @@
+     {
+       /* No need to check target support (already checked by the pattern
+          recognition function).  */
+-      if (type_out)
+-	gcc_assert (VECTOR_MODE_P (TYPE_MODE (type_out)));
+       pattern_vectype = type_out ? type_out : type_in;
+     }
+   else
+@@ -1360,8 +1585,8 @@
+   /* It is possible that additional pattern stmts are created and inserted in
+      STMTS_TO_REPLACE.  We create a stmt_info for each of them, and mark the
+      relevant statements.  */
+-  for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
+-              && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
++  for (i = 0; VEC_iterate (gimple, *stmts_to_replace, i, stmt)
++	      && (unsigned) i < (VEC_length (gimple, *stmts_to_replace) - 1);
+        i++)
+     {
+       stmt_info = vinfo_for_stmt (stmt);
+@@ -1374,8 +1599,6 @@
+ 
+       vect_mark_pattern_stmts (stmt, pattern_stmt, NULL_TREE);
+     }
+-
+-  VEC_free (gimple, heap, stmts_to_replace);
+ }
+ 
+ 
+@@ -1465,6 +1688,7 @@
+   gimple_stmt_iterator si;
+   unsigned int i, j;
+   gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
++  VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vect_pattern_recog ===");
+@@ -1480,8 +1704,11 @@
+           for (j = 0; j < NUM_PATTERNS; j++)
+             {
+               vect_recog_func_ptr = vect_vect_recog_func_ptrs[j];
+-              vect_pattern_recog_1 (vect_recog_func_ptr, si);
++	      vect_pattern_recog_1 (vect_recog_func_ptr, si,
++				    &stmts_to_replace);
+             }
+         }
+     }
++
++  VEC_free (gimple, heap, stmts_to_replace);
+ }
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-10-23 11:29:25 +0000
++++ new/gcc/tree-vect-slp.c	2011-10-27 11:27:59 +0000
+@@ -480,6 +480,11 @@
+ 		    }
+ 		}
+ 	    }
++	  else if (rhs_code == WIDEN_LSHIFT_EXPR)
++            {
++              need_same_oprnds = true;
++              first_op1 = gimple_assign_rhs2 (stmt);
++            }
+ 	}
+       else
+ 	{
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-10-23 11:29:25 +0000
++++ new/gcc/tree-vect-stmts.c	2011-10-27 11:27:59 +0000
+@@ -3359,6 +3359,7 @@
+   VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
+   VEC (tree, heap) *vec_dsts = NULL, *interm_types = NULL, *tmp_vec_dsts = NULL;
+   bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
++  unsigned int k;
+ 
+   if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
+     return false;
+@@ -3375,7 +3376,8 @@
+ 
+   code = gimple_assign_rhs_code (stmt);
+   if (!CONVERT_EXPR_CODE_P (code)
+-      && code != WIDEN_MULT_EXPR)
++      && code != WIDEN_MULT_EXPR
++      && code != WIDEN_LSHIFT_EXPR)
+     return false;
+ 
+   scalar_dest = gimple_assign_lhs (stmt);
+@@ -3403,7 +3405,7 @@
+       bool ok;
+ 
+       op1 = gimple_assign_rhs2 (stmt);
+-      if (code == WIDEN_MULT_EXPR)
++      if (code == WIDEN_MULT_EXPR || code == WIDEN_LSHIFT_EXPR)
+         {
+ 	  /* For WIDEN_MULT_EXPR, if OP0 is a constant, use the type of
+ 	     OP1.  */
+@@ -3480,7 +3482,7 @@
+     fprintf (vect_dump, "transform type promotion operation. ncopies = %d.",
+                         ncopies);
+ 
+-  if (code == WIDEN_MULT_EXPR)
++  if (code == WIDEN_MULT_EXPR || code == WIDEN_LSHIFT_EXPR)
+     {
+       if (CONSTANT_CLASS_P (op0))
+ 	op0 = fold_convert (TREE_TYPE (op1), op0);
+@@ -3521,6 +3523,8 @@
+       if (op_type == binary_op)
+         vec_oprnds1 = VEC_alloc (tree, heap, 1);
+     }
++  else if (code == WIDEN_LSHIFT_EXPR)
++    vec_oprnds1 = VEC_alloc (tree, heap, slp_node->vec_stmts_size);
+ 
+   /* In case the vectorization factor (VF) is bigger than the number
+      of elements that we can fit in a vectype (nunits), we have to generate
+@@ -3534,15 +3538,33 @@
+       if (j == 0)
+         {
+           if (slp_node)
+-              vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0,
+-                                 &vec_oprnds1, -1);
+-          else
++	    {
++	      if (code == WIDEN_LSHIFT_EXPR)
++                {
++                  vec_oprnd1 = op1;
++		  /* Store vec_oprnd1 for every vector stmt to be created
++		     for SLP_NODE.  We check during the analysis that all
++		     the shift arguments are the same.  */
++                  for (k = 0; k < slp_node->vec_stmts_size - 1; k++)
++                    VEC_quick_push (tree, vec_oprnds1, vec_oprnd1);
++
++    		  vect_get_slp_defs (op0, NULL_TREE, slp_node, &vec_oprnds0, NULL,
++ 	                             -1);
++                }
++              else
++                vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0,
++                                   &vec_oprnds1, -1);
++	    }
++	  else
+             {
+               vec_oprnd0 = vect_get_vec_def_for_operand (op0, stmt, NULL);
+               VEC_quick_push (tree, vec_oprnds0, vec_oprnd0);
+               if (op_type == binary_op)
+                 {
+-                  vec_oprnd1 = vect_get_vec_def_for_operand (op1, stmt, NULL);
++                  if (code == WIDEN_LSHIFT_EXPR)
++                    vec_oprnd1 = op1;
++                  else
++                    vec_oprnd1 = vect_get_vec_def_for_operand (op1, stmt, NULL);
+                   VEC_quick_push (tree, vec_oprnds1, vec_oprnd1);
+                 }
+             }
+@@ -3553,7 +3575,10 @@
+           VEC_replace (tree, vec_oprnds0, 0, vec_oprnd0);
+           if (op_type == binary_op)
+             {
+-              vec_oprnd1 = vect_get_vec_def_for_stmt_copy (dt[1], vec_oprnd1);
++              if (code == WIDEN_LSHIFT_EXPR)
++                vec_oprnd1 = op1;
++              else
++                vec_oprnd1 = vect_get_vec_def_for_stmt_copy (dt[1], vec_oprnd1);
+               VEC_replace (tree, vec_oprnds1, 0, vec_oprnd1);
+             }
+         }
+@@ -5853,6 +5878,19 @@
+         }
+       break;
+ 
++    case WIDEN_LSHIFT_EXPR:
++      if (BYTES_BIG_ENDIAN)
++        {
++          c1 = VEC_WIDEN_LSHIFT_HI_EXPR;
++          c2 = VEC_WIDEN_LSHIFT_LO_EXPR;
++        }
++      else
++        {
++          c2 = VEC_WIDEN_LSHIFT_HI_EXPR;
++          c1 = VEC_WIDEN_LSHIFT_LO_EXPR;
++        }
++      break;
++
+     CASE_CONVERT:
+       if (BYTES_BIG_ENDIAN)
+         {
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2011-09-05 06:23:37 +0000
++++ new/gcc/tree-vectorizer.h	2011-10-23 13:33:07 +0000
+@@ -896,7 +896,7 @@
+    Additional pattern recognition functions can (and will) be added
+    in the future.  */
+ typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+-#define NUM_PATTERNS 5
++#define NUM_PATTERNS 6 
+ void vect_pattern_recog (loop_vec_info);
+ 
+ /* In tree-vectorizer.c.  */
+
+=== modified file 'gcc/tree.def'
+--- old/gcc/tree.def	2011-01-21 14:14:12 +0000
++++ new/gcc/tree.def	2011-10-23 13:33:07 +0000
+@@ -1092,6 +1092,19 @@
+    is subtracted from t3.  */
+ DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_minus_expr", tcc_expression, 3)
+ 
++/* Widening shift left.
++   The first operand is of type t1.
++   The second operand is the number of bits to shift by; it need not be the
++   same type as the first operand and result.
++   Note that the result is undefined if the second operand is larger
++   than or equal to the first operand's type size.
++   The type of the entire expression is t2, such that t2 is at least twice
++   the size of t1.
++   WIDEN_LSHIFT_EXPR is equivalent to first widening (promoting)
++   the first argument from type t1 to type t2, and then shifting it
++   by the second argument.  */
++DEFTREECODE (WIDEN_LSHIFT_EXPR, "widen_lshift_expr", tcc_binary, 2)
++
+ /* Fused multiply-add.
+    All operands and the result are of the same type.  No intermediate
+    rounding is performed after multiplying operand one with operand two
+@@ -1147,6 +1160,16 @@
+ DEFTREECODE (VEC_INTERLEAVE_HIGH_EXPR, "vec_interleavehigh_expr", tcc_binary, 2)
+ DEFTREECODE (VEC_INTERLEAVE_LOW_EXPR, "vec_interleavelow_expr", tcc_binary, 2)
+ 
++/* Widening vector shift left in bits.
++   Operand 0 is a vector to be shifted with N elements of size S.
++   Operand 1 is an integer shift amount in bits.
++   The result of the operation is N elements of size 2*S.
++   VEC_WIDEN_LSHIFT_HI_EXPR computes the N/2 high results.
++   VEC_WIDEN_LSHIFT_LO_EXPR computes the N/2 low results.
++ */
++DEFTREECODE (VEC_WIDEN_LSHIFT_HI_EXPR, "widen_lshift_hi_expr", tcc_binary, 2)
++DEFTREECODE (VEC_WIDEN_LSHIFT_LO_EXPR, "widen_lshift_lo_expr", tcc_binary, 2)
++
+ /* PREDICT_EXPR.  Specify hint for branch prediction.  The
+    PREDICT_EXPR_PREDICTOR specify predictor and PREDICT_EXPR_OUTCOME the
+    outcome (0 for not taken and 1 for taken).  Once the profile is guessed
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch
new file mode 100644
index 0000000000..95b9ea9b83
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch
@@ -0,0 +1,61 @@
+2011-11-04  Revital Eres  <revital.eres@linaro.org>
+
+	Backport from mainline -r180673:
+
+	gcc/
+	* modulo-sched.c (generate_prolog_epilog): Mark prolog
+	and epilog as BB_DISABLE_SCHEDULE.
+	(mark_loop_unsched): New function.
+	(sms_schedule): Call it.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-10-10 14:35:32 +0000
++++ new/gcc/modulo-sched.c	2011-10-30 05:31:00 +0000
+@@ -1173,6 +1173,8 @@
+   /* Put the prolog on the entry edge.  */
+   e = loop_preheader_edge (loop);
+   split_edge_and_insert (e, get_insns ());
++  if (!flag_resched_modulo_sched)
++    e->dest->flags |= BB_DISABLE_SCHEDULE;
+ 
+   end_sequence ();
+ 
+@@ -1186,9 +1188,24 @@
+   gcc_assert (single_exit (loop));
+   e = single_exit (loop);
+   split_edge_and_insert (e, get_insns ());
++  if (!flag_resched_modulo_sched)
++    e->dest->flags |= BB_DISABLE_SCHEDULE;
++
+   end_sequence ();
+ }
+ 
++/* Mark LOOP as software pipelined so the later
++   scheduling passes don't touch it.  */
++static void
++mark_loop_unsched (struct loop *loop)
++{
++  unsigned i;
++  basic_block *bbs = get_loop_body (loop);
++
++  for (i = 0; i < loop->num_nodes; i++)
++    bbs[i]->flags |= BB_DISABLE_SCHEDULE;
++}
++
+ /* Return true if all the BBs of the loop are empty except the
+    loop header.  */
+ static bool
+@@ -1714,9 +1731,10 @@
+ 	  permute_partial_schedule (ps, g->closing_branch->first_note);
+ 
+           /* Mark this loop as software pipelined so the later
+-	     scheduling passes doesn't touch it.  */
++	     scheduling passes don't touch it.  */
+ 	  if (! flag_resched_modulo_sched)
+-	    g->bb->flags |= BB_DISABLE_SCHEDULE;
++	    mark_loop_unsched (loop);
++	  
+ 	  /* The life-info is not valid any more.  */
+ 	  df_set_bb_dirty (g->bb);
+ 
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch
new file mode 100644
index 0000000000..dcffe1945c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch
@@ -0,0 +1,23 @@
+2011-11-02  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from FSF mainline:
+
+	2011-11-01  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Recognize generic-armv7 tuning.
+
+=== modified file 'gcc/config/arm/bpabi.h'
+--- old/gcc/config/arm/bpabi.h	2010-12-20 17:48:51 +0000
++++ new/gcc/config/arm/bpabi.h	2011-11-02 21:02:53 +0000
+@@ -56,7 +56,8 @@
+   "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
+ 
+ #define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5"\
+-  "|mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15:%{!r:--be8}}}"
++  "|mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15|mcpu=generic-armv7-a"\
++  ":%{!r:--be8}}}"
+ 
+ /* Tell the assembler to build BPABI binaries.  */
+ #undef  SUBTARGET_EXTRA_ASM_SPEC
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch
new file mode 100644
index 0000000000..70a7bdfa2b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch
@@ -0,0 +1,1400 @@
+2011-11-17  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-11-03  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vectorizer.h (slp_void_p): New.
+	(struct _slp_tree): Replace left and right with children.  Update
+	documentation.
+	(struct _slp_oprnd_info): New.
+	(vect_get_vec_defs): Declare.
+	(vect_get_slp_defs): Update arguments.
+	* tree-vect-loop.c (vect_create_epilog_for_reduction): Call
+	vect_get_vec_defs instead of vect_get_slp_defs.
+	(vectorizable_reduction): Likewise.
+	* tree-vect-stmts.c (vect_get_vec_defs): Remove static, add argument.
+	Update call to vect_get_slp_defs.
+	(vectorizable_conversion): Update call to vect_get_vec_defs.
+	(vectorizable_assignment, vectorizable_shift,
+	vectorizable_operation): Likewise.
+	(vectorizable_type_demotion): Call vect_get_vec_defs instead of
+	vect_get_slp_defs.
+	(vectorizable_type_promotion, vectorizable_store): Likewise.
+	(vect_analyze_stmt): Fix typo.
+	* tree-vect-slp.c (vect_free_slp_tree): Update SLP tree traversal.
+	(vect_print_slp_tree, vect_mark_slp_stmts,
+	vect_mark_slp_stmts_relevant, vect_slp_rearrange_stmts,
+	vect_detect_hybrid_slp_stmts, vect_slp_analyze_node_operations,
+	vect_schedule_slp_instance): Likewise.
+	(vect_create_new_slp_node): New.
+	(vect_create_oprnd_info, vect_free_oprnd_info): Likewise.
+	(vect_get_and_check_slp_defs): Pass information about defs using
+	oprnds_info, allow any number of operands.
+	(vect_build_slp_tree): Likewise.  Update calls to
+	vect_get_and_check_slp_defs.  Fix comments.
+	(vect_analyze_slp_instance): Move node creation to
+	vect_create_new_slp_node.
+	(vect_get_slp_defs): Allow any number of operands.
+
+	2011-11-11  Jakub Jelinek  <jakub@redhat.com>
+
+	gcc/
+	* tree-vect-slp.c (vect_free_slp_tree): Also free SLP_TREE_CHILDREN
+	vector.
+	(vect_create_new_slp_node): Don't allocate node before checking stmt
+	type.
+	(vect_free_oprnd_info): Remove FREE_DEF_STMTS argument, always
+	free def_stmts vectors and additionally free oprnd_info.
+	(vect_build_slp_tree): Adjust callers.  Call it even if
+	stop_recursion.  If vect_create_new_slp_node or
+	vect_build_slp_tree fails, properly handle freeing memory.
+	If it succeeded, clear def_stmts in oprnd_info.
+
+=== modified file 'gcc/tree-vect-loop.c'
+--- old/gcc/tree-vect-loop.c	2011-09-05 06:23:37 +0000
++++ new/gcc/tree-vect-loop.c	2011-11-14 11:38:08 +0000
+@@ -3282,8 +3282,8 @@
+ 
+   /* Get the loop-entry arguments.  */
+   if (slp_node)
+-    vect_get_slp_defs (reduction_op, NULL_TREE, slp_node, &vec_initial_defs,
+-                       NULL, reduc_index);
++    vect_get_vec_defs (reduction_op, NULL_TREE, stmt, &vec_initial_defs,
++                       NULL, slp_node, reduc_index);
+   else
+     {
+       vec_initial_defs = VEC_alloc (tree, heap, 1);
+@@ -4451,8 +4451,8 @@
+             }
+ 
+           if (slp_node)
+-            vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0, &vec_oprnds1,
+-                               -1);
++            vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1,
++                               slp_node, -1);
+           else
+             {
+               loop_vec_def0 = vect_get_vec_def_for_operand (ops[!reduc_index],
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-10-27 11:27:59 +0000
++++ new/gcc/tree-vect-slp.c	2011-11-14 11:38:08 +0000
+@@ -67,15 +67,16 @@
+ static void
+ vect_free_slp_tree (slp_tree node)
+ {
++  int i;
++  slp_void_p child;
++
+   if (!node)
+     return;
+ 
+-  if (SLP_TREE_LEFT (node))
+-    vect_free_slp_tree (SLP_TREE_LEFT (node));
+-
+-  if (SLP_TREE_RIGHT (node))
+-    vect_free_slp_tree (SLP_TREE_RIGHT (node));
+-
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_free_slp_tree ((slp_tree) child);
++
++  VEC_free (slp_void_p, heap, SLP_TREE_CHILDREN (node));
+   VEC_free (gimple, heap, SLP_TREE_SCALAR_STMTS (node));
+ 
+   if (SLP_TREE_VEC_STMTS (node))
+@@ -96,48 +97,116 @@
+ }
+ 
+ 
+-/* Get the defs for the rhs of STMT (collect them in DEF_STMTS0/1), check that
+-   they are of a legal type and that they match the defs of the first stmt of
+-   the SLP group (stored in FIRST_STMT_...).  */
++/* Create an SLP node for SCALAR_STMTS.  */
++
++static slp_tree
++vect_create_new_slp_node (VEC (gimple, heap) *scalar_stmts)
++{
++  slp_tree node;
++  gimple stmt = VEC_index (gimple, scalar_stmts, 0);
++  unsigned int nops;
++
++  if (is_gimple_call (stmt))
++    nops = gimple_call_num_args (stmt);
++  else if (is_gimple_assign (stmt))
++    nops = gimple_num_ops (stmt) - 1;
++  else
++    return NULL;
++
++  node = XNEW (struct _slp_tree);
++  SLP_TREE_SCALAR_STMTS (node) = scalar_stmts;
++  SLP_TREE_VEC_STMTS (node) = NULL;
++  SLP_TREE_CHILDREN (node) = VEC_alloc (slp_void_p, heap, nops);
++  SLP_TREE_OUTSIDE_OF_LOOP_COST (node) = 0;
++  SLP_TREE_INSIDE_OF_LOOP_COST (node) = 0;
++
++  return node;
++}
++
++
++/* Allocate operands info for NOPS operands, and GROUP_SIZE def-stmts for each
++   operand.  */
++static VEC (slp_oprnd_info, heap) *
++vect_create_oprnd_info (int nops, int group_size)
++{
++  int i;
++  slp_oprnd_info oprnd_info;
++  VEC (slp_oprnd_info, heap) *oprnds_info;
++
++  oprnds_info = VEC_alloc (slp_oprnd_info, heap, nops);
++  for (i = 0; i < nops; i++)
++    {
++      oprnd_info = XNEW (struct _slp_oprnd_info);
++      oprnd_info->def_stmts = VEC_alloc (gimple, heap, group_size);
++      oprnd_info->first_dt = vect_uninitialized_def;
++      oprnd_info->first_def_type = NULL_TREE;
++      oprnd_info->first_const_oprnd = NULL_TREE;
++      oprnd_info->first_pattern = false;
++      VEC_quick_push (slp_oprnd_info, oprnds_info, oprnd_info);
++    }
++
++  return oprnds_info;
++}
++
++
++/* Free operands info.  */
++
++static void
++vect_free_oprnd_info (VEC (slp_oprnd_info, heap) **oprnds_info)
++{
++  int i;
++  slp_oprnd_info oprnd_info;
++
++  FOR_EACH_VEC_ELT (slp_oprnd_info, *oprnds_info, i, oprnd_info)
++    {
++      VEC_free (gimple, heap, oprnd_info->def_stmts);
++      XDELETE (oprnd_info);
++    }
++
++  VEC_free (slp_oprnd_info, heap, *oprnds_info);
++}
++
++
++/* Get the defs for the rhs of STMT (collect them in OPRNDS_INFO), check that
++   they are of a valid type and that they match the defs of the first stmt of
++   the SLP group (stored in OPRNDS_INFO).  */
+ 
+ static bool
+ vect_get_and_check_slp_defs (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo,
+                              slp_tree slp_node, gimple stmt,
+-			     VEC (gimple, heap) **def_stmts0,
+-			     VEC (gimple, heap) **def_stmts1,
+-			     enum vect_def_type *first_stmt_dt0,
+-			     enum vect_def_type *first_stmt_dt1,
+-			     tree *first_stmt_def0_type,
+-			     tree *first_stmt_def1_type,
+-			     tree *first_stmt_const_oprnd,
+-			     int ncopies_for_cost,
+-                             bool *pattern0, bool *pattern1)
++			     int ncopies_for_cost, bool first,
++                             VEC (slp_oprnd_info, heap) **oprnds_info)
+ {
+   tree oprnd;
+   unsigned int i, number_of_oprnds;
+-  tree def[2];
++  tree def, def_op0 = NULL_TREE;
+   gimple def_stmt;
+-  enum vect_def_type dt[2] = {vect_unknown_def_type, vect_unknown_def_type};
+-  stmt_vec_info stmt_info =
+-    vinfo_for_stmt (VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0));
+-  enum gimple_rhs_class rhs_class;
++  enum vect_def_type dt = vect_uninitialized_def;
++  enum vect_def_type dt_op0 = vect_uninitialized_def;
++  stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
++  tree lhs = gimple_get_lhs (stmt);
+   struct loop *loop = NULL;
+   enum tree_code rhs_code;
+   bool different_types = false;
++  bool pattern = false;
++  slp_oprnd_info oprnd_info, oprnd0_info, oprnd1_info;
+ 
+   if (loop_vinfo)
+     loop = LOOP_VINFO_LOOP (loop_vinfo);
+ 
+-  rhs_class = get_gimple_rhs_class (gimple_assign_rhs_code (stmt));
+-  number_of_oprnds = gimple_num_ops (stmt) - 1;	/* RHS only */
++  if (is_gimple_call (stmt))
++    number_of_oprnds = gimple_call_num_args (stmt);
++  else
++    number_of_oprnds = gimple_num_ops (stmt) - 1;
+ 
+   for (i = 0; i < number_of_oprnds; i++)
+     {
+       oprnd = gimple_op (stmt, i + 1);
++      oprnd_info = VEC_index (slp_oprnd_info, *oprnds_info, i);
+ 
+-      if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def[i],
+-                               &dt[i])
+-	  || (!def_stmt && dt[i] != vect_constant_def))
++      if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def,
++                               &dt)
++	  || (!def_stmt && dt != vect_constant_def))
+ 	{
+ 	  if (vect_print_dump_info (REPORT_SLP))
+ 	    {
+@@ -158,29 +227,24 @@
+           && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
+           && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
+         {
+-          if (!*first_stmt_dt0)
+-            *pattern0 = true;
+-          else
+-            {
+-              if (i == 1 && !*first_stmt_dt1)
+-                *pattern1 = true;
+-              else if ((i == 0 && !*pattern0) || (i == 1 && !*pattern1))
+-                {
+-                  if (vect_print_dump_info (REPORT_DETAILS))
+-                    {
+-                      fprintf (vect_dump, "Build SLP failed: some of the stmts"
+-                                     " are in a pattern, and others are not ");
+-                      print_generic_expr (vect_dump, oprnd, TDF_SLIM);
+-                    }
++          pattern = true;
++          if (!first && !oprnd_info->first_pattern)
++	    {
++	      if (vect_print_dump_info (REPORT_DETAILS))
++		{
++		  fprintf (vect_dump, "Build SLP failed: some of the stmts"
++				" are in a pattern, and others are not ");
++		  print_generic_expr (vect_dump, oprnd, TDF_SLIM);
++		}
+ 
+-                  return false;
+-                }
++	      return false;
+             }
+ 
+           def_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
+-          dt[i] = STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def_stmt));
++          dt = STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def_stmt));
+ 
+-          if (*dt == vect_unknown_def_type)
++          if (dt == vect_unknown_def_type
++	      || STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (def_stmt)))
+             {
+               if (vect_print_dump_info (REPORT_DETAILS))
+                 fprintf (vect_dump, "Unsupported pattern.");
+@@ -190,11 +254,11 @@
+           switch (gimple_code (def_stmt))
+             {
+               case GIMPLE_PHI:
+-                def[i] = gimple_phi_result (def_stmt);
++                def = gimple_phi_result (def_stmt);
+                 break;
+ 
+               case GIMPLE_ASSIGN:
+-                def[i] = gimple_assign_lhs (def_stmt);
++                def = gimple_assign_lhs (def_stmt);
+                 break;
+ 
+               default:
+@@ -204,117 +268,125 @@
+             }
+         }
+ 
+-      if (!*first_stmt_dt0)
++      if (first)
+ 	{
+-	  /* op0 of the first stmt of the group - store its info.  */
+-	  *first_stmt_dt0 = dt[i];
+-	  if (def[i])
+-	    *first_stmt_def0_type = TREE_TYPE (def[i]);
+-	  else
+-	    *first_stmt_const_oprnd = oprnd;
++          oprnd_info->first_dt = dt;
++          oprnd_info->first_pattern = pattern;
++          if (def)
++            {
++              oprnd_info->first_def_type = TREE_TYPE (def);
++              oprnd_info->first_const_oprnd = NULL_TREE;
++            }
++          else
++            {
++              oprnd_info->first_def_type = NULL_TREE;
++              oprnd_info->first_const_oprnd = oprnd;
++            }
+ 
+-	  /* Analyze costs (for the first stmt of the group only).  */
+-	  if (rhs_class != GIMPLE_SINGLE_RHS)
+-	    /* Not memory operation (we don't call this functions for loads).  */
+-	    vect_model_simple_cost (stmt_info, ncopies_for_cost, dt, slp_node);
+-	  else
+-	    /* Store.  */
+-	    vect_model_store_cost (stmt_info, ncopies_for_cost, false,
+-				   dt[0], slp_node);
++          if (i == 0)
++            {
++              def_op0 = def;
++              dt_op0 = dt;
++              /* Analyze costs (for the first stmt of the group only).  */
++              if (REFERENCE_CLASS_P (lhs))
++                /* Store.  */
++                vect_model_store_cost (stmt_info, ncopies_for_cost, false,
++                                       dt, slp_node);
++              else
++                /* Not memory operation (we don't call this function for
++                   loads).  */
++                vect_model_simple_cost (stmt_info, ncopies_for_cost, &dt,
++                                        slp_node);
++            }
+ 	}
+ 
+       else
+ 	{
+-	  if (!*first_stmt_dt1 && i == 1)
+-	    {
+-	      /* op1 of the first stmt of the group - store its info.  */
+-	      *first_stmt_dt1 = dt[i];
+-	      if (def[i])
+-		*first_stmt_def1_type = TREE_TYPE (def[i]);
+-	      else
+-		{
+-		  /* We assume that the stmt contains only one constant
+-		     operand. We fail otherwise, to be on the safe side.  */
+-		  if (*first_stmt_const_oprnd)
+-		    {
+-		      if (vect_print_dump_info (REPORT_SLP))
+-			fprintf (vect_dump, "Build SLP failed: two constant "
+-				 "oprnds in stmt");
+-		      return false;
+-		    }
+-		  *first_stmt_const_oprnd = oprnd;
+-		}
+-	    }
+-	  else
+-	    {
+-	      /* Not first stmt of the group, check that the def-stmt/s match
+-		 the def-stmt/s of the first stmt.  */
+-	      if ((i == 0
+-		   && (*first_stmt_dt0 != dt[i]
+-		       || (*first_stmt_def0_type && def[0]
+-			   && !types_compatible_p (*first_stmt_def0_type,
+-						   TREE_TYPE (def[0])))))
+-		  || (i == 1
+-		      && (*first_stmt_dt1 != dt[i]
+-			  || (*first_stmt_def1_type && def[1]
+-			      && !types_compatible_p (*first_stmt_def1_type,
+-						      TREE_TYPE (def[1])))))
+-		  || (!def[i]
+-		      && !types_compatible_p (TREE_TYPE (*first_stmt_const_oprnd),
+-					      TREE_TYPE (oprnd)))
+-                  || different_types)
+-		{
+-                  if (i != number_of_oprnds - 1)
+-                    different_types = true;
++          /* Not first stmt of the group, check that the def-stmt/s match
++             the def-stmt/s of the first stmt.  Allow different definition
++             types for reduction chains: the first stmt must be a
++             vect_reduction_def (a phi node), and the rest
++             vect_internal_def.  */
++          if (((oprnd_info->first_dt != dt
++                && !(oprnd_info->first_dt == vect_reduction_def
++                     && dt == vect_internal_def))
++               || (oprnd_info->first_def_type != NULL_TREE
++                   && def
++                   && !types_compatible_p (oprnd_info->first_def_type,
++                                           TREE_TYPE (def))))
++               || (!def
++                   && !types_compatible_p (TREE_TYPE (oprnd_info->first_const_oprnd),
++                                           TREE_TYPE (oprnd)))
++               || different_types)
++	    {
++              if (number_of_oprnds != 2)
++		{
++                  if (vect_print_dump_info (REPORT_SLP))
++                    fprintf (vect_dump, "Build SLP failed: different types ");
++
++                  return false;
++                }
++
++              /* Try to swap operands in case of binary operation.  */
++              if (i == 0)
++                different_types = true;
++              else
++		{
++                  oprnd0_info = VEC_index (slp_oprnd_info, *oprnds_info, 0);
++                  if (is_gimple_assign (stmt)
++                      && (rhs_code = gimple_assign_rhs_code (stmt))
++                      && TREE_CODE_CLASS (rhs_code) == tcc_binary
++                      && commutative_tree_code (rhs_code)
++                      && oprnd0_info->first_dt == dt
++                      && oprnd_info->first_dt == dt_op0
++                      && def_op0 && def
++                      && !(oprnd0_info->first_def_type
++                           && !types_compatible_p (oprnd0_info->first_def_type,
++                                                   TREE_TYPE (def)))
++                      && !(oprnd_info->first_def_type
++                           && !types_compatible_p (oprnd_info->first_def_type,
++                                                   TREE_TYPE (def_op0))))
++                    {
++                      if (vect_print_dump_info (REPORT_SLP))
++                       {
++                         fprintf (vect_dump, "Swapping operands of ");
++                         print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++                       }
++
++                      swap_tree_operands (stmt, gimple_assign_rhs1_ptr (stmt),
++                                          gimple_assign_rhs2_ptr (stmt));
++                    }
+                   else
+-                   {
+-                      if (is_gimple_assign (stmt)
+-                          && (rhs_code = gimple_assign_rhs_code (stmt))
+-                          && TREE_CODE_CLASS (rhs_code) == tcc_binary
+-                          && commutative_tree_code (rhs_code)
+-                          && *first_stmt_dt0 == dt[1]
+-                          && *first_stmt_dt1 == dt[0]
+-                          && def[0] && def[1]
+-                          && !(*first_stmt_def0_type
+-                               && !types_compatible_p (*first_stmt_def0_type,
+-                                                       TREE_TYPE (def[1])))
+-                          && !(*first_stmt_def1_type
+-                               && !types_compatible_p (*first_stmt_def1_type,
+-                                                       TREE_TYPE (def[0]))))
+-                        {
+-                           if (vect_print_dump_info (REPORT_SLP))
+-                            {
+-                              fprintf (vect_dump, "Swapping operands of ");
+-                              print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+-                            }
+-                           swap_tree_operands (stmt, gimple_assign_rhs1_ptr (stmt),
+-                                               gimple_assign_rhs2_ptr (stmt));
+-                        }
+-                      else
+-                        {
+-                          if (vect_print_dump_info (REPORT_SLP))
+-                            fprintf (vect_dump, "Build SLP failed: different types ");
+-
+-                          return false;
+-                        }
+-                   }
++                    {
++                      if (vect_print_dump_info (REPORT_SLP))
++                        fprintf (vect_dump, "Build SLP failed: different types ");
++ 
++                      return false;
++                    }
+ 		}
+ 	    }
+ 	}
+ 
+       /* Check the types of the definitions.  */
+-      switch (dt[i])
++      switch (dt)
+ 	{
+ 	case vect_constant_def:
+ 	case vect_external_def:
++        case vect_reduction_def:
+ 	  break;
+ 
+ 	case vect_internal_def:
+-        case vect_reduction_def:
+-	  if ((i == 0 && !different_types) || (i == 1 && different_types))
+-	    VEC_safe_push (gimple, heap, *def_stmts0, def_stmt);
++          if (different_types)
++            {
++              oprnd0_info = VEC_index (slp_oprnd_info, *oprnds_info, 0);
++              oprnd1_info = VEC_index (slp_oprnd_info, *oprnds_info, 0);
++              if (i == 0)
++                VEC_quick_push (gimple, oprnd1_info->def_stmts, def_stmt);
++              else
++                VEC_quick_push (gimple, oprnd0_info->def_stmts, def_stmt);
++            }
+ 	  else
+- 	    VEC_safe_push (gimple, heap, *def_stmts1, def_stmt);
++ 	    VEC_quick_push (gimple, oprnd_info->def_stmts, def_stmt);
+ 	  break;
+ 
+ 	default:
+@@ -322,7 +394,7 @@
+ 	  if (vect_print_dump_info (REPORT_SLP))
+ 	    {
+ 	      fprintf (vect_dump, "Build SLP failed: illegal type of def ");
+-	      print_generic_expr (vect_dump, def[i], TDF_SLIM);
++	      print_generic_expr (vect_dump, def, TDF_SLIM);
+ 	    }
+ 
+ 	  return false;
+@@ -347,15 +419,10 @@
+                      VEC (slp_tree, heap) **loads,
+                      unsigned int vectorization_factor, bool *loads_permuted)
+ {
+-  VEC (gimple, heap) *def_stmts0 = VEC_alloc (gimple, heap, group_size);
+-  VEC (gimple, heap) *def_stmts1 =  VEC_alloc (gimple, heap, group_size);
+   unsigned int i;
+   VEC (gimple, heap) *stmts = SLP_TREE_SCALAR_STMTS (*node);
+   gimple stmt = VEC_index (gimple, stmts, 0);
+-  enum vect_def_type first_stmt_dt0 = vect_uninitialized_def;
+-  enum vect_def_type first_stmt_dt1 = vect_uninitialized_def;
+   enum tree_code first_stmt_code = ERROR_MARK, rhs_code = ERROR_MARK;
+-  tree first_stmt_def1_type = NULL_TREE, first_stmt_def0_type = NULL_TREE;
+   tree lhs;
+   bool stop_recursion = false, need_same_oprnds = false;
+   tree vectype, scalar_type, first_op1 = NULL_TREE;
+@@ -364,13 +431,21 @@
+   int icode;
+   enum machine_mode optab_op2_mode;
+   enum machine_mode vec_mode;
+-  tree first_stmt_const_oprnd = NULL_TREE;
+   struct data_reference *first_dr;
+-  bool pattern0 = false, pattern1 = false;
+   HOST_WIDE_INT dummy;
+   bool permutation = false;
+   unsigned int load_place;
+   gimple first_load, prev_first_load = NULL;
++  VEC (slp_oprnd_info, heap) *oprnds_info;
++  unsigned int nops;
++  slp_oprnd_info oprnd_info;
++
++  if (is_gimple_call (stmt))
++    nops = gimple_call_num_args (stmt);
++  else
++    nops = gimple_num_ops (stmt) - 1;
++
++  oprnds_info = vect_create_oprnd_info (nops, group_size);
+ 
+   /* For every stmt in NODE find its def stmt/s.  */
+   FOR_EACH_VEC_ELT (gimple, stmts, i, stmt)
+@@ -391,6 +466,7 @@
+               print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+             }
+ 
++	  vect_free_oprnd_info (&oprnds_info);
+           return false;
+         }
+ 
+@@ -400,10 +476,11 @@
+ 	  if (vect_print_dump_info (REPORT_SLP))
+ 	    {
+ 	      fprintf (vect_dump,
+-		       "Build SLP failed: not GIMPLE_ASSIGN nor GIMPLE_CALL");
++		       "Build SLP failed: not GIMPLE_ASSIGN nor GIMPLE_CALL ");
+ 	      print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+ 	    }
+ 
++	  vect_free_oprnd_info (&oprnds_info);
+ 	  return false;
+ 	}
+ 
+@@ -416,6 +493,8 @@
+               fprintf (vect_dump, "Build SLP failed: unsupported data-type ");
+               print_generic_expr (vect_dump, scalar_type, TDF_SLIM);
+             }
++
++	  vect_free_oprnd_info (&oprnds_info);
+           return false;
+         }
+ 
+@@ -462,6 +541,7 @@
+ 		    {
+ 		      if (vect_print_dump_info (REPORT_SLP))
+ 			fprintf (vect_dump, "Build SLP failed: no optab.");
++	  	      vect_free_oprnd_info (&oprnds_info);
+ 		      return false;
+ 		    }
+ 		  icode = (int) optab_handler (optab, vec_mode);
+@@ -470,6 +550,7 @@
+ 		      if (vect_print_dump_info (REPORT_SLP))
+ 			fprintf (vect_dump, "Build SLP failed: "
+ 				            "op not supported by target.");
++	  	      vect_free_oprnd_info (&oprnds_info);
+ 		      return false;
+ 		    }
+ 		  optab_op2_mode = insn_data[icode].operand[2].mode;
+@@ -506,6 +587,7 @@
+ 		  print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+ 		}
+ 
++	      vect_free_oprnd_info (&oprnds_info);
+ 	      return false;
+ 	    }
+ 
+@@ -519,6 +601,7 @@
+ 		  print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+ 		}
+ 
++	      vect_free_oprnd_info (&oprnds_info);
+ 	      return false;
+ 	    }
+ 	}
+@@ -530,15 +613,12 @@
+ 	    {
+ 	      /* Store.  */
+ 	      if (!vect_get_and_check_slp_defs (loop_vinfo, bb_vinfo, *node,
+-						stmt, &def_stmts0, &def_stmts1,
+-						&first_stmt_dt0,
+-						&first_stmt_dt1,
+-						&first_stmt_def0_type,
+-						&first_stmt_def1_type,
+-						&first_stmt_const_oprnd,
+-						ncopies_for_cost,
+-                                                &pattern0, &pattern1))
+-		return false;
++						stmt, ncopies_for_cost,
++						(i == 0), &oprnds_info))
++		{
++	  	  vect_free_oprnd_info (&oprnds_info);
++ 		  return false;
++		}
+ 	    }
+ 	  else
+ 	    {
+@@ -556,6 +636,7 @@
+                       print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+                     }
+ 
++	  	  vect_free_oprnd_info (&oprnds_info);
+                   return false;
+                 }
+ 
+@@ -573,6 +654,7 @@
+                       print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+                     }
+ 
++	  	  vect_free_oprnd_info (&oprnds_info);
+                   return false;
+                 }
+ 
+@@ -593,6 +675,7 @@
+                           print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+                         }
+  
++	  	      vect_free_oprnd_info (&oprnds_info);
+                       return false;
+                     }
+                 }
+@@ -612,6 +695,7 @@
+                           print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+                         }
+ 
++	  	      vect_free_oprnd_info (&oprnds_info);
+                       return false;
+                     }
+ 
+@@ -639,7 +723,7 @@
+ 	{
+ 	  if (TREE_CODE_CLASS (rhs_code) == tcc_reference)
+ 	    {
+-	      /* Not strided load. */
++	      /* Not strided load.  */
+ 	      if (vect_print_dump_info (REPORT_SLP))
+ 		{
+ 		  fprintf (vect_dump, "Build SLP failed: not strided load ");
+@@ -647,6 +731,7 @@
+ 		}
+ 
+ 	      /* FORNOW: Not strided loads are not supported.  */
++	      vect_free_oprnd_info (&oprnds_info);
+ 	      return false;
+ 	    }
+ 
+@@ -661,19 +746,18 @@
+ 		  print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
+ 		}
+ 
++	      vect_free_oprnd_info (&oprnds_info);
+ 	      return false;
+ 	    }
+ 
+ 	  /* Find the def-stmts.  */
+ 	  if (!vect_get_and_check_slp_defs (loop_vinfo, bb_vinfo, *node, stmt,
+-					    &def_stmts0, &def_stmts1,
+-					    &first_stmt_dt0, &first_stmt_dt1,
+-					    &first_stmt_def0_type,
+-					    &first_stmt_def1_type,
+-					    &first_stmt_const_oprnd,
+-					    ncopies_for_cost,
+-                                            &pattern0, &pattern1))
+-	    return false;
++					    ncopies_for_cost, (i == 0),
++					    &oprnds_info))
++	    {
++	      vect_free_oprnd_info (&oprnds_info);
++	      return false;
++	    }
+ 	}
+     }
+ 
+@@ -702,46 +786,37 @@
+             *loads_permuted = true;
+         }
+ 
++      vect_free_oprnd_info (&oprnds_info);
+       return true;
+     }
+ 
+   /* Create SLP_TREE nodes for the definition node/s.  */
+-  if (first_stmt_dt0 == vect_internal_def)
+-    {
+-      slp_tree left_node = XNEW (struct _slp_tree);
+-      SLP_TREE_SCALAR_STMTS (left_node) = def_stmts0;
+-      SLP_TREE_VEC_STMTS (left_node) = NULL;
+-      SLP_TREE_LEFT (left_node) = NULL;
+-      SLP_TREE_RIGHT (left_node) = NULL;
+-      SLP_TREE_OUTSIDE_OF_LOOP_COST (left_node) = 0;
+-      SLP_TREE_INSIDE_OF_LOOP_COST (left_node) = 0;
+-      if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &left_node, group_size,
+-				inside_cost, outside_cost, ncopies_for_cost,
+-				max_nunits, load_permutation, loads,
+-				vectorization_factor, loads_permuted))
+-	return false;
+-
+-      SLP_TREE_LEFT (*node) = left_node;
+-    }
+-
+-  if (first_stmt_dt1 == vect_internal_def)
+-    {
+-      slp_tree right_node = XNEW (struct _slp_tree);
+-      SLP_TREE_SCALAR_STMTS (right_node) = def_stmts1;
+-      SLP_TREE_VEC_STMTS (right_node) = NULL;
+-      SLP_TREE_LEFT (right_node) = NULL;
+-      SLP_TREE_RIGHT (right_node) = NULL;
+-      SLP_TREE_OUTSIDE_OF_LOOP_COST (right_node) = 0;
+-      SLP_TREE_INSIDE_OF_LOOP_COST (right_node) = 0;
+-      if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &right_node, group_size,
+-				inside_cost, outside_cost, ncopies_for_cost,
+-				max_nunits, load_permutation, loads,
+-				vectorization_factor, loads_permuted))
+-	return false;
+-
+-      SLP_TREE_RIGHT (*node) = right_node;
+-    }
+-
++  FOR_EACH_VEC_ELT (slp_oprnd_info, oprnds_info, i, oprnd_info)
++    {
++      slp_tree child;
++
++      if (oprnd_info->first_dt != vect_internal_def)
++        continue;
++
++      child = vect_create_new_slp_node (oprnd_info->def_stmts);
++      if (!child
++          || !vect_build_slp_tree (loop_vinfo, bb_vinfo, &child, group_size,
++				inside_cost, outside_cost, ncopies_for_cost,
++				max_nunits, load_permutation, loads,
++				vectorization_factor, loads_permuted))
++        {
++	  if (child)
++	    oprnd_info->def_stmts = NULL;
++	  vect_free_slp_tree (child);
++	  vect_free_oprnd_info (&oprnds_info);
++   	  return false;
++	}
++
++      oprnd_info->def_stmts = NULL;
++      VEC_quick_push (slp_void_p, SLP_TREE_CHILDREN (*node), child);
++    }
++
++  vect_free_oprnd_info (&oprnds_info);
+   return true;
+ }
+ 
+@@ -751,6 +826,7 @@
+ {
+   int i;
+   gimple stmt;
++  slp_void_p child;
+ 
+   if (!node)
+     return;
+@@ -763,8 +839,8 @@
+     }
+   fprintf (vect_dump, "\n");
+ 
+-  vect_print_slp_tree (SLP_TREE_LEFT (node));
+-  vect_print_slp_tree (SLP_TREE_RIGHT (node));
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_print_slp_tree ((slp_tree) child);
+ }
+ 
+ 
+@@ -778,6 +854,7 @@
+ {
+   int i;
+   gimple stmt;
++  slp_void_p child;
+ 
+   if (!node)
+     return;
+@@ -786,8 +863,8 @@
+     if (j < 0 || i == j)
+       STMT_SLP_TYPE (vinfo_for_stmt (stmt)) = mark;
+ 
+-  vect_mark_slp_stmts (SLP_TREE_LEFT (node), mark, j);
+-  vect_mark_slp_stmts (SLP_TREE_RIGHT (node), mark, j);
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_mark_slp_stmts ((slp_tree) child, mark, j);
+ }
+ 
+ 
+@@ -799,6 +876,7 @@
+   int i;
+   gimple stmt;
+   stmt_vec_info stmt_info;
++  slp_void_p child;
+ 
+   if (!node)
+     return;
+@@ -811,8 +889,8 @@
+       STMT_VINFO_RELEVANT (stmt_info) = vect_used_in_scope;
+     }
+ 
+-  vect_mark_slp_stmts_relevant (SLP_TREE_LEFT (node));
+-  vect_mark_slp_stmts_relevant (SLP_TREE_RIGHT (node));
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_mark_slp_stmts_relevant ((slp_tree) child);
+ }
+ 
+ 
+@@ -885,12 +963,13 @@
+   gimple stmt;
+   VEC (gimple, heap) *tmp_stmts;
+   unsigned int index, i;
++  slp_void_p child;
+ 
+   if (!node)
+     return;
+ 
+-  vect_slp_rearrange_stmts (SLP_TREE_LEFT (node), group_size, permutation);
+-  vect_slp_rearrange_stmts (SLP_TREE_RIGHT (node), group_size, permutation);
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_slp_rearrange_stmts ((slp_tree) child, group_size, permutation);
+ 
+   gcc_assert (group_size == VEC_length (gimple, SLP_TREE_SCALAR_STMTS (node)));
+   tmp_stmts = VEC_alloc (gimple, heap, group_size);
+@@ -1253,7 +1332,7 @@
+                            gimple stmt)
+ {
+   slp_instance new_instance;
+-  slp_tree node = XNEW (struct _slp_tree);
++  slp_tree node;
+   unsigned int group_size = DR_GROUP_SIZE (vinfo_for_stmt (stmt));
+   unsigned int unrolling_factor = 1, nunits;
+   tree vectype, scalar_type = NULL_TREE;
+@@ -1265,6 +1344,7 @@
+   VEC (slp_tree, heap) *loads;
+   struct data_reference *dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (stmt));
+   bool loads_permuted = false;
++  VEC (gimple, heap) *scalar_stmts;
+ 
+   if (dr)
+     {
+@@ -1308,39 +1388,26 @@
+     }
+ 
+   /* Create a node (a root of the SLP tree) for the packed strided stores.  */
+-  SLP_TREE_SCALAR_STMTS (node) = VEC_alloc (gimple, heap, group_size);
++  scalar_stmts = VEC_alloc (gimple, heap, group_size);
+   next = stmt;
+   if (dr)
+     {
+       /* Collect the stores and store them in SLP_TREE_SCALAR_STMTS.  */
+       while (next)
+         {
+-          VEC_safe_push (gimple, heap, SLP_TREE_SCALAR_STMTS (node), next);
++          VEC_safe_push (gimple, heap, scalar_stmts, next);
+           next = DR_GROUP_NEXT_DR (vinfo_for_stmt (next));
+         }
+     }
+   else
+     {
+       /* Collect reduction statements.  */
+-      for (i = 0; VEC_iterate (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, 
+-                               next); 
+-           i++)
+-        {
+-          VEC_safe_push (gimple, heap, SLP_TREE_SCALAR_STMTS (node), next);
+-          if (vect_print_dump_info (REPORT_DETAILS))
+-            {
+-              fprintf (vect_dump, "pushing reduction into node: ");
+-              print_gimple_stmt (vect_dump, next, 0, TDF_SLIM);
+-            }
+-        }
++      VEC (gimple, heap) *reductions = LOOP_VINFO_REDUCTIONS (loop_vinfo);
++      for (i = 0; VEC_iterate (gimple, reductions, i, next); i++)
++        VEC_safe_push (gimple, heap, scalar_stmts, next);
+     }
+ 
+-  SLP_TREE_VEC_STMTS (node) = NULL;
+-  SLP_TREE_NUMBER_OF_VEC_STMTS (node) = 0;
+-  SLP_TREE_LEFT (node) = NULL;
+-  SLP_TREE_RIGHT (node) = NULL;
+-  SLP_TREE_OUTSIDE_OF_LOOP_COST (node) = 0;
+-  SLP_TREE_INSIDE_OF_LOOP_COST (node) = 0;
++  node = vect_create_new_slp_node (scalar_stmts);
+ 
+   /* Calculate the number of vector stmts to create based on the unrolling
+      factor (number of vectors is 1 if NUNITS >= GROUP_SIZE, and is
+@@ -1517,6 +1584,7 @@
+   imm_use_iterator imm_iter;
+   gimple use_stmt;
+   stmt_vec_info stmt_vinfo; 
++  slp_void_p child;
+ 
+   if (!node)
+     return;
+@@ -1534,8 +1602,8 @@
+                      == vect_reduction_def))
+ 	  vect_mark_slp_stmts (node, hybrid, i);
+ 
+-  vect_detect_hybrid_slp_stmts (SLP_TREE_LEFT (node));
+-  vect_detect_hybrid_slp_stmts (SLP_TREE_RIGHT (node));
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_detect_hybrid_slp_stmts ((slp_tree) child);
+ }
+ 
+ 
+@@ -1625,13 +1693,14 @@
+   bool dummy;
+   int i;
+   gimple stmt;
++  slp_void_p child;
+ 
+   if (!node)
+     return true;
+ 
+-  if (!vect_slp_analyze_node_operations (bb_vinfo, SLP_TREE_LEFT (node))
+-      || !vect_slp_analyze_node_operations (bb_vinfo, SLP_TREE_RIGHT (node)))
+-    return false;
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    if (!vect_slp_analyze_node_operations (bb_vinfo, (slp_tree) child))
++      return false;
+ 
+   FOR_EACH_VEC_ELT (gimple, SLP_TREE_SCALAR_STMTS (node), i, stmt)
+     {
+@@ -2207,88 +2276,102 @@
+    If the scalar definitions are loop invariants or constants, collect them and
+    call vect_get_constant_vectors() to create vector stmts.
+    Otherwise, the def-stmts must be already vectorized and the vectorized stmts
+-   must be stored in the LEFT/RIGHT node of SLP_NODE, and we call
+-   vect_get_slp_vect_defs() to retrieve them.
+-   If VEC_OPRNDS1 is NULL, don't get vector defs for the second operand (from
+-   the right node. This is used when the second operand must remain scalar.  */
++   must be stored in the corresponding child of SLP_NODE, and we call
++   vect_get_slp_vect_defs () to retrieve them.  */
+ 
+ void
+-vect_get_slp_defs (tree op0, tree op1, slp_tree slp_node,
+-                   VEC (tree,heap) **vec_oprnds0,
+-                   VEC (tree,heap) **vec_oprnds1, int reduc_index)
++vect_get_slp_defs (VEC (tree, heap) *ops, slp_tree slp_node,
++                   VEC (slp_void_p, heap) **vec_oprnds, int reduc_index)
+ {
+-  gimple first_stmt;
+-  enum tree_code code;
+-  int number_of_vects;
++  gimple first_stmt, first_def;
++  int number_of_vects = 0, i;
++  unsigned int child_index = 0;
+   HOST_WIDE_INT lhs_size_unit, rhs_size_unit;
++  slp_tree child = NULL;
++  VEC (tree, heap) *vec_defs;
++  tree oprnd, def_lhs;
++  bool vectorized_defs;
+ 
+   first_stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0);
+-  /* The number of vector defs is determined by the number of vector statements
+-     in the node from which we get those statements.  */
+-  if (SLP_TREE_LEFT (slp_node))
+-    number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (SLP_TREE_LEFT (slp_node));
+-  else
+-    {
+-      number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
+-      /* Number of vector stmts was calculated according to LHS in
+-         vect_schedule_slp_instance(), fix it by replacing LHS with RHS, if
+-         necessary.  See vect_get_smallest_scalar_type () for details.  */
+-      vect_get_smallest_scalar_type (first_stmt, &lhs_size_unit,
+-                                     &rhs_size_unit);
+-      if (rhs_size_unit != lhs_size_unit)
+-        {
+-          number_of_vects *= rhs_size_unit;
+-          number_of_vects /= lhs_size_unit;
+-        }
++  FOR_EACH_VEC_ELT (tree, ops, i, oprnd)
++   {
++     /* For each operand we check if it has vectorized definitions in a child
++        node or we need to create them (for invariants and constants).  We
++        check if the LHS of the first stmt of the next child matches OPRND.
++        If it does, we found the correct child.  Otherwise, we call
++        vect_get_constant_vectors (), and not advance CHILD_INDEX in order
++        to check this child node for the next operand.  */
++      vectorized_defs = false;
++      if (VEC_length (slp_void_p, SLP_TREE_CHILDREN (slp_node)) > child_index)
++        {
++          child = (slp_tree) VEC_index (slp_void_p,
++                                        SLP_TREE_CHILDREN (slp_node),
++                                        child_index);
++          first_def = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (child), 0);
++
++          /* In the end of a pattern sequence we have a use of the original stmt,
++             so we need to compare OPRND with the original def.  */
++          if (is_pattern_stmt_p (vinfo_for_stmt (first_def))
++              && !STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (first_stmt))
++              && !is_pattern_stmt_p (vinfo_for_stmt (first_stmt)))
++            first_def = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (first_def));
++
++          if (is_gimple_call (first_def))
++            def_lhs = gimple_call_lhs (first_def);
++          else
++            def_lhs = gimple_assign_lhs (first_def);
++
++          if (operand_equal_p (oprnd, def_lhs, 0))
++            {
++              /* The number of vector defs is determined by the number of
++                 vector statements in the node from which we get those
++                 statements.  */
++               number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (child);
++               vectorized_defs = true;
++               child_index++;
++            }
++        }
++
++      if (!vectorized_defs)
++        {
++          if (i == 0)
++            {
++              number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
++              /* Number of vector stmts was calculated according to LHS in
++                 vect_schedule_slp_instance (), fix it by replacing LHS with
++                 RHS, if necessary.  See vect_get_smallest_scalar_type () for
++                 details.  */
++              vect_get_smallest_scalar_type (first_stmt, &lhs_size_unit,
++                                             &rhs_size_unit);
++              if (rhs_size_unit != lhs_size_unit)
++                {
++                  number_of_vects *= rhs_size_unit;
++                  number_of_vects /= lhs_size_unit;
++                }
++            }
++        }
++
++      /* Allocate memory for vectorized defs.  */
++      vec_defs = VEC_alloc (tree, heap, number_of_vects);
++
++      /* For reduction defs we call vect_get_constant_vectors (), since we are
++         looking for initial loop invariant values.  */
++      if (vectorized_defs && reduc_index == -1)
++        /* The defs are already vectorized.  */
++        vect_get_slp_vect_defs (child, &vec_defs);
++      else
++        /* Build vectors from scalar defs.  */
++        vect_get_constant_vectors (oprnd, slp_node, &vec_defs, i,
++                                   number_of_vects, reduc_index);
++
++      VEC_quick_push (slp_void_p, *vec_oprnds, (slp_void_p) vec_defs);
++
++      /* For reductions, we only need initial values.  */
++      if (reduc_index != -1)
++        return;
+     }
+-
+-  /* Allocate memory for vectorized defs.  */
+-  *vec_oprnds0 = VEC_alloc (tree, heap, number_of_vects);
+-
+-  /* SLP_NODE corresponds either to a group of stores or to a group of
+-     unary/binary operations.  We don't call this function for loads.
+-     For reduction defs we call vect_get_constant_vectors(), since we are
+-     looking for initial loop invariant values.  */
+-  if (SLP_TREE_LEFT (slp_node) && reduc_index == -1)
+-    /* The defs are already vectorized.  */
+-    vect_get_slp_vect_defs (SLP_TREE_LEFT (slp_node), vec_oprnds0);
+-  else
+-    /* Build vectors from scalar defs.  */
+-    vect_get_constant_vectors (op0, slp_node, vec_oprnds0, 0, number_of_vects,
+-                               reduc_index);
+-
+-  if (STMT_VINFO_DATA_REF (vinfo_for_stmt (first_stmt)))
+-    /* Since we don't call this function with loads, this is a group of
+-       stores.  */
+-    return;
+-
+-  /* For reductions, we only need initial values.  */
+-  if (reduc_index != -1)
+-    return;
+-
+-  code = gimple_assign_rhs_code (first_stmt);
+-  if (get_gimple_rhs_class (code) != GIMPLE_BINARY_RHS || !vec_oprnds1)
+-    return;
+-
+-  /* The number of vector defs is determined by the number of vector statements
+-     in the node from which we get those statements.  */
+-  if (SLP_TREE_RIGHT (slp_node))
+-    number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (SLP_TREE_RIGHT (slp_node));
+-  else
+-    number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
+-
+-  *vec_oprnds1 = VEC_alloc (tree, heap, number_of_vects);
+-
+-  if (SLP_TREE_RIGHT (slp_node))
+-    /* The defs are already vectorized.  */
+-    vect_get_slp_vect_defs (SLP_TREE_RIGHT (slp_node), vec_oprnds1);
+-  else
+-    /* Build vectors from scalar defs.  */
+-    vect_get_constant_vectors (op1, slp_node, vec_oprnds1, 1, number_of_vects,
+-                               -1);
+ }
+ 
+-
+ /* Create NCOPIES permutation statements using the mask MASK_BYTES (by
+    building a vector of type MASK_TYPE from it) and two input vectors placed in
+    DR_CHAIN at FIRST_VEC_INDX and SECOND_VEC_INDX for the first copy and
+@@ -2605,14 +2688,14 @@
+   tree vectype;
+   int i;
+   slp_tree loads_node;
++  slp_void_p child;
+ 
+   if (!node)
+     return false;
+ 
+-  vect_schedule_slp_instance (SLP_TREE_LEFT (node), instance,
+-                              vectorization_factor);
+-  vect_schedule_slp_instance (SLP_TREE_RIGHT (node), instance,
+-                              vectorization_factor);
++  FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
++    vect_schedule_slp_instance ((slp_tree) child, instance,
++                                vectorization_factor);
+ 
+   stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (node), 0);
+   stmt_info = vinfo_for_stmt (stmt);
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-10-27 11:27:59 +0000
++++ new/gcc/tree-vect-stmts.c	2011-11-14 11:38:08 +0000
+@@ -1419,16 +1419,35 @@
+ }
+ 
+ 
+-/* Get vectorized definitions for OP0 and OP1, or SLP_NODE if it is not
+-   NULL.  */
++/* Get vectorized definitions for OP0 and OP1.
++   REDUC_INDEX is the index of reduction operand in case of reduction,
++   and -1 otherwise.  */
+ 
+-static void
++void
+ vect_get_vec_defs (tree op0, tree op1, gimple stmt,
+-		   VEC(tree,heap) **vec_oprnds0, VEC(tree,heap) **vec_oprnds1,
+-		   slp_tree slp_node)
++		   VEC (tree, heap) **vec_oprnds0,
++		   VEC (tree, heap) **vec_oprnds1,
++		   slp_tree slp_node, int reduc_index)
+ {
+   if (slp_node)
+-    vect_get_slp_defs (op0, op1, slp_node, vec_oprnds0, vec_oprnds1, -1);
++    {
++      int nops = (op1 == NULL_TREE) ? 1 : 2;
++      VEC (tree, heap) *ops = VEC_alloc (tree, heap, nops);
++      VEC (slp_void_p, heap) *vec_defs = VEC_alloc (slp_void_p, heap, nops);
++
++      VEC_quick_push (tree, ops, op0);
++      if (op1)
++        VEC_quick_push (tree, ops, op1);
++
++      vect_get_slp_defs (ops, slp_node, &vec_defs, reduc_index);
++
++      *vec_oprnds0 = (VEC (tree, heap) *) VEC_index (slp_void_p, vec_defs, 0);
++      if (op1)
++        *vec_oprnds1 = (VEC (tree, heap) *) VEC_index (slp_void_p, vec_defs, 1);
++
++      VEC_free (tree, heap, ops);
++      VEC_free (slp_void_p, heap, vec_defs);
++    }
+   else
+     {
+       tree vec_oprnd;
+@@ -2016,7 +2035,8 @@
+       for (j = 0; j < ncopies; j++)
+ 	{
+ 	  if (j == 0)
+-	    vect_get_vec_defs (op0, NULL, stmt, &vec_oprnds0, NULL, slp_node);
++	    vect_get_vec_defs (op0, NULL, stmt, &vec_oprnds0, NULL, slp_node,
++			       -1);
+ 	  else
+ 	    vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds0, NULL);
+ 
+@@ -2221,7 +2241,7 @@
+     {
+       /* Handle uses.  */
+       if (j == 0)
+-        vect_get_vec_defs (op, NULL, stmt, &vec_oprnds, NULL, slp_node);
++        vect_get_vec_defs (op, NULL, stmt, &vec_oprnds, NULL, slp_node, -1);
+       else
+         vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds, NULL);
+ 
+@@ -2576,10 +2596,10 @@
+              operand 1 should be of a vector type (the usual case).  */
+           if (vec_oprnd1)
+             vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
+-                               slp_node);
++                               slp_node, -1);
+           else
+             vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1,
+-                               slp_node);
++                               slp_node, -1);
+         }
+       else
+         vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds0, &vec_oprnds1);
+@@ -2887,10 +2907,10 @@
+ 	{
+ 	  if (op_type == binary_op || op_type == ternary_op)
+ 	    vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1,
+-			       slp_node);
++			       slp_node, -1);
+ 	  else
+ 	    vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
+-			       slp_node);
++			       slp_node, -1);
+ 	  if (op_type == ternary_op)
+ 	    {
+ 	      vec_oprnds2 = VEC_alloc (tree, heap, 1);
+@@ -3202,7 +3222,8 @@
+     {
+       /* Handle uses.  */
+       if (slp_node)
+-        vect_get_slp_defs (op0, NULL_TREE, slp_node, &vec_oprnds0, NULL, -1);
++        vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
++			   slp_node, -1);
+       else
+         {
+           VEC_free (tree, heap, vec_oprnds0);
+@@ -3548,12 +3569,12 @@
+                   for (k = 0; k < slp_node->vec_stmts_size - 1; k++)
+                     VEC_quick_push (tree, vec_oprnds1, vec_oprnd1);
+ 
+-    		  vect_get_slp_defs (op0, NULL_TREE, slp_node, &vec_oprnds0, NULL,
+- 	                             -1);
++    		  vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
++ 	                             slp_node, -1);
+                 }
+               else
+-                vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0,
+-                                   &vec_oprnds1, -1);
++                vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0,
++                                   &vec_oprnds1, slp_node, -1);
+ 	    }
+ 	  else
+             {
+@@ -3796,6 +3817,7 @@
+           vec_num = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
+           first_stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0); 
+           first_dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (first_stmt));
++	  op = gimple_assign_rhs1 (first_stmt);
+         } 
+       else
+         /* VEC_NUM is the number of vect stmts to be created for this 
+@@ -3878,8 +3900,8 @@
+           if (slp)
+             {
+ 	      /* Get vectorized arguments for SLP_NODE.  */
+-              vect_get_slp_defs (NULL_TREE, NULL_TREE, slp_node, &vec_oprnds,
+-                                 NULL, -1);
++              vect_get_vec_defs (op, NULL_TREE, stmt, &vec_oprnds,
++                                 NULL, slp_node, -1);
+ 
+               vec_oprnd = VEC_index (tree, vec_oprnds, 0);
+             }
+@@ -5040,7 +5062,7 @@
+      In basic blocks we only analyze statements that are a part of some SLP
+      instance, therefore, all the statements are relevant.  
+ 
+-     Pattern statement need to be analyzed instead of the original statement
++     Pattern statement needs to be analyzed instead of the original statement
+      if the original statement is not relevant. Otherwise, we analyze both
+      statements.  */
+ 
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2011-10-23 13:33:07 +0000
++++ new/gcc/tree-vectorizer.h	2011-11-14 11:38:08 +0000
+@@ -73,15 +73,15 @@
+ /************************************************************************
+   SLP
+  ************************************************************************/
++typedef void *slp_void_p;
++DEF_VEC_P (slp_void_p);
++DEF_VEC_ALLOC_P (slp_void_p, heap);
+ 
+-/* A computation tree of an SLP instance. Each node corresponds to a group of
++/* A computation tree of an SLP instance.  Each node corresponds to a group of
+    stmts to be packed in a SIMD stmt.  */
+ typedef struct _slp_tree {
+-  /* Only binary and unary operations are supported. LEFT child corresponds to
+-     the first operand and RIGHT child to the second if the operation is
+-     binary.  */
+-  struct _slp_tree *left;
+-  struct _slp_tree *right;
++  /* Nodes that contain def-stmts of this node statements operands.  */
++  VEC (slp_void_p, heap) *children;
+   /* A group of scalar stmts to be vectorized together.  */
+   VEC (gimple, heap) *stmts;
+   /* Vectorized stmt/s.  */
+@@ -146,14 +146,32 @@
+ #define SLP_INSTANCE_LOADS(S)                    (S)->loads
+ #define SLP_INSTANCE_FIRST_LOAD_STMT(S)          (S)->first_load
+ 
+-#define SLP_TREE_LEFT(S)                         (S)->left
+-#define SLP_TREE_RIGHT(S)                        (S)->right
++#define SLP_TREE_CHILDREN(S)                     (S)->children
+ #define SLP_TREE_SCALAR_STMTS(S)                 (S)->stmts
+ #define SLP_TREE_VEC_STMTS(S)                    (S)->vec_stmts
+ #define SLP_TREE_NUMBER_OF_VEC_STMTS(S)          (S)->vec_stmts_size
+ #define SLP_TREE_OUTSIDE_OF_LOOP_COST(S)         (S)->cost.outside_of_loop
+ #define SLP_TREE_INSIDE_OF_LOOP_COST(S)          (S)->cost.inside_of_loop
+ 
++/* This structure is used in creation of an SLP tree.  Each instance
++   corresponds to the same operand in a group of scalar stmts in an SLP
++   node.  */
++typedef struct _slp_oprnd_info
++{
++  /* Def-stmts for the operands.  */
++  VEC (gimple, heap) *def_stmts;
++  /* Information about the first statement, its vector def-type, type, the
++     operand itself in case it's constant, and an indication if it's a pattern
++     stmt.  */
++  enum vect_def_type first_dt;
++  tree first_def_type;
++  tree first_const_oprnd;
++  bool first_pattern;
++} *slp_oprnd_info;
++
++DEF_VEC_P(slp_oprnd_info);
++DEF_VEC_ALLOC_P(slp_oprnd_info, heap);
++
+ 
+ typedef struct _vect_peel_info
+ {
+@@ -819,6 +837,8 @@
+                                 unsigned int *, unsigned int *);
+ extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
+ extern bool vect_supportable_shift (enum tree_code, tree);
++extern void vect_get_vec_defs (tree, tree, gimple, VEC (tree, heap) **,
++			       VEC (tree, heap) **, slp_tree, int);
+ 
+ /* In tree-vect-data-refs.c.  */
+ extern bool vect_can_force_dr_alignment_p (const_tree, unsigned int);
+@@ -885,8 +905,9 @@
+ extern bool vect_analyze_slp (loop_vec_info, bb_vec_info);
+ extern void vect_make_slp_decision (loop_vec_info);
+ extern void vect_detect_hybrid_slp (loop_vec_info);
+-extern void vect_get_slp_defs (tree, tree, slp_tree, VEC (tree,heap) **,
+-                               VEC (tree,heap) **, int);
++extern void vect_get_slp_defs (VEC (tree, heap) *, slp_tree,
++			       VEC (slp_void_p, heap) **, int);
++
+ extern LOC find_bb_location (basic_block);
+ extern bb_vec_info vect_slp_analyze_bb (basic_block);
+ extern void vect_slp_transform_bb (basic_block);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch
new file mode 100644
index 0000000000..d72446919f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch
@@ -0,0 +1,515 @@
+2011-11-21  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r180131:
+
+	2011-10-18  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_block_move_unaligned_straight)
+	(arm_adjust_block_mem, arm_block_move_unaligned_loop)
+	(arm_movmemqi_unaligned): New.
+	(arm_gen_movmemqi): Support unaligned block copies.
+
+	gcc/testsuite/
+	* lib/target-supports.exp (check_effective_target_arm_unaligned): New.
+	* gcc.target/arm/unaligned-memcpy-1.c: New.
+	* gcc.target/arm/unaligned-memcpy-2.c: New.
+	* gcc.target/arm/unaligned-memcpy-3.c: New.
+	* gcc.target/arm/unaligned-memcpy-4.c: New.
+
+	2011-09-15  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	gcc/
+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): New builtin macro.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-10-26 11:38:30 +0000
++++ new/gcc/config/arm/arm.c	2011-11-21 01:45:54 +0000
+@@ -10803,6 +10803,335 @@
+   return true;
+ }
+ 
++/* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
++   unaligned copies on processors which support unaligned semantics for those
++   instructions.  INTERLEAVE_FACTOR can be used to attempt to hide load latency
++   (using more registers) by doing e.g. load/load/store/store for a factor of 2.
++   An interleave factor of 1 (the minimum) will perform no interleaving. 
++   Load/store multiple are used for aligned addresses where possible.  */
++
++static void
++arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
++				   HOST_WIDE_INT length,
++				   unsigned int interleave_factor)
++{
++  rtx *regs = XALLOCAVEC (rtx, interleave_factor);
++  int *regnos = XALLOCAVEC (int, interleave_factor);
++  HOST_WIDE_INT block_size_bytes = interleave_factor * UNITS_PER_WORD;
++  HOST_WIDE_INT i, j;
++  HOST_WIDE_INT remaining = length, words;
++  rtx halfword_tmp = NULL, byte_tmp = NULL;
++  rtx dst, src;
++  bool src_aligned = MEM_ALIGN (srcbase) >= BITS_PER_WORD;
++  bool dst_aligned = MEM_ALIGN (dstbase) >= BITS_PER_WORD;
++  HOST_WIDE_INT srcoffset, dstoffset;
++  HOST_WIDE_INT src_autoinc, dst_autoinc;
++  rtx mem, addr;
++  
++  gcc_assert (1 <= interleave_factor && interleave_factor <= 4);
++  
++  /* Use hard registers if we have aligned source or destination so we can use
++     load/store multiple with contiguous registers.  */
++  if (dst_aligned || src_aligned)
++    for (i = 0; i < interleave_factor; i++)
++      regs[i] = gen_rtx_REG (SImode, i);
++  else
++    for (i = 0; i < interleave_factor; i++)
++      regs[i] = gen_reg_rtx (SImode);
++
++  dst = copy_addr_to_reg (XEXP (dstbase, 0));
++  src = copy_addr_to_reg (XEXP (srcbase, 0));
++
++  srcoffset = dstoffset = 0;
++  
++  /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
++     For copying the last bytes we want to subtract this offset again.  */
++  src_autoinc = dst_autoinc = 0;
++
++  for (i = 0; i < interleave_factor; i++)
++    regnos[i] = i;
++
++  /* Copy BLOCK_SIZE_BYTES chunks.  */
++
++  for (i = 0; i + block_size_bytes <= length; i += block_size_bytes)
++    {
++      /* Load words.  */
++      if (src_aligned && interleave_factor > 1)
++	{
++	  emit_insn (arm_gen_load_multiple (regnos, interleave_factor, src,
++					    TRUE, srcbase, &srcoffset));
++	  src_autoinc += UNITS_PER_WORD * interleave_factor;
++	}
++      else
++	{
++	  for (j = 0; j < interleave_factor; j++)
++	    {
++	      addr = plus_constant (src, srcoffset + j * UNITS_PER_WORD
++					 - src_autoinc);
++	      mem = adjust_automodify_address (srcbase, SImode, addr,
++					       srcoffset + j * UNITS_PER_WORD);
++	      emit_insn (gen_unaligned_loadsi (regs[j], mem));
++	    }
++	  srcoffset += block_size_bytes;
++	}
++
++      /* Store words.  */
++      if (dst_aligned && interleave_factor > 1)
++	{
++	  emit_insn (arm_gen_store_multiple (regnos, interleave_factor, dst,
++					     TRUE, dstbase, &dstoffset));
++	  dst_autoinc += UNITS_PER_WORD * interleave_factor;
++	}
++      else
++	{
++	  for (j = 0; j < interleave_factor; j++)
++	    {
++	      addr = plus_constant (dst, dstoffset + j * UNITS_PER_WORD
++					 - dst_autoinc);
++	      mem = adjust_automodify_address (dstbase, SImode, addr,
++					       dstoffset + j * UNITS_PER_WORD);
++	      emit_insn (gen_unaligned_storesi (mem, regs[j]));
++	    }
++	  dstoffset += block_size_bytes;
++	}
++
++      remaining -= block_size_bytes;
++    }
++  
++  /* Copy any whole words left (note these aren't interleaved with any
++     subsequent halfword/byte load/stores in the interests of simplicity).  */
++  
++  words = remaining / UNITS_PER_WORD;
++
++  gcc_assert (words < interleave_factor);
++  
++  if (src_aligned && words > 1)
++    {
++      emit_insn (arm_gen_load_multiple (regnos, words, src, TRUE, srcbase,
++					&srcoffset));
++      src_autoinc += UNITS_PER_WORD * words;
++    }
++  else
++    {
++      for (j = 0; j < words; j++)
++	{
++	  addr = plus_constant (src,
++				srcoffset + j * UNITS_PER_WORD - src_autoinc);
++	  mem = adjust_automodify_address (srcbase, SImode, addr,
++					   srcoffset + j * UNITS_PER_WORD);
++	  emit_insn (gen_unaligned_loadsi (regs[j], mem));
++	}
++      srcoffset += words * UNITS_PER_WORD;
++    }
++
++  if (dst_aligned && words > 1)
++    {
++      emit_insn (arm_gen_store_multiple (regnos, words, dst, TRUE, dstbase,
++					 &dstoffset));
++      dst_autoinc += words * UNITS_PER_WORD;
++    }
++  else
++    {
++      for (j = 0; j < words; j++)
++	{
++	  addr = plus_constant (dst,
++				dstoffset + j * UNITS_PER_WORD - dst_autoinc);
++	  mem = adjust_automodify_address (dstbase, SImode, addr,
++					   dstoffset + j * UNITS_PER_WORD);
++	  emit_insn (gen_unaligned_storesi (mem, regs[j]));
++	}
++      dstoffset += words * UNITS_PER_WORD;
++    }
++
++  remaining -= words * UNITS_PER_WORD;
++  
++  gcc_assert (remaining < 4);
++  
++  /* Copy a halfword if necessary.  */
++  
++  if (remaining >= 2)
++    {
++      halfword_tmp = gen_reg_rtx (SImode);
++
++      addr = plus_constant (src, srcoffset - src_autoinc);
++      mem = adjust_automodify_address (srcbase, HImode, addr, srcoffset);
++      emit_insn (gen_unaligned_loadhiu (halfword_tmp, mem));
++
++      /* Either write out immediately, or delay until we've loaded the last
++	 byte, depending on interleave factor.  */
++      if (interleave_factor == 1)
++	{
++	  addr = plus_constant (dst, dstoffset - dst_autoinc);
++	  mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
++	  emit_insn (gen_unaligned_storehi (mem,
++		       gen_lowpart (HImode, halfword_tmp)));
++	  halfword_tmp = NULL;
++	  dstoffset += 2;
++	}
++
++      remaining -= 2;
++      srcoffset += 2;
++    }
++  
++  gcc_assert (remaining < 2);
++  
++  /* Copy last byte.  */
++  
++  if ((remaining & 1) != 0)
++    {
++      byte_tmp = gen_reg_rtx (SImode);
++
++      addr = plus_constant (src, srcoffset - src_autoinc);
++      mem = adjust_automodify_address (srcbase, QImode, addr, srcoffset);
++      emit_move_insn (gen_lowpart (QImode, byte_tmp), mem);
++
++      if (interleave_factor == 1)
++	{
++	  addr = plus_constant (dst, dstoffset - dst_autoinc);
++	  mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
++	  emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
++	  byte_tmp = NULL;
++	  dstoffset++;
++	}
++
++      remaining--;
++      srcoffset++;
++    }
++  
++  /* Store last halfword if we haven't done so already.  */
++  
++  if (halfword_tmp)
++    {
++      addr = plus_constant (dst, dstoffset - dst_autoinc);
++      mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
++      emit_insn (gen_unaligned_storehi (mem,
++		   gen_lowpart (HImode, halfword_tmp)));
++      dstoffset += 2;
++    }
++
++  /* Likewise for last byte.  */
++
++  if (byte_tmp)
++    {
++      addr = plus_constant (dst, dstoffset - dst_autoinc);
++      mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
++      emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
++      dstoffset++;
++    }
++  
++  gcc_assert (remaining == 0 && srcoffset == dstoffset);
++}
++
++/* From mips_adjust_block_mem:
++
++   Helper function for doing a loop-based block operation on memory
++   reference MEM.  Each iteration of the loop will operate on LENGTH
++   bytes of MEM.
++
++   Create a new base register for use within the loop and point it to
++   the start of MEM.  Create a new memory reference that uses this
++   register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
++
++static void
++arm_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg,
++		      rtx *loop_mem)
++{
++  *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
++  
++  /* Although the new mem does not refer to a known location,
++     it does keep up to LENGTH bytes of alignment.  */
++  *loop_mem = change_address (mem, BLKmode, *loop_reg);
++  set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
++}
++
++/* From mips_block_move_loop:
++
++   Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
++   bytes at a time.  LENGTH must be at least BYTES_PER_ITER.  Assume that
++   the memory regions do not overlap.  */
++
++static void
++arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length,
++			       unsigned int interleave_factor,
++			       HOST_WIDE_INT bytes_per_iter)
++{
++  rtx label, src_reg, dest_reg, final_src, test;
++  HOST_WIDE_INT leftover;
++  
++  leftover = length % bytes_per_iter;
++  length -= leftover;
++  
++  /* Create registers and memory references for use within the loop.  */
++  arm_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
++  arm_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
++  
++  /* Calculate the value that SRC_REG should have after the last iteration of
++     the loop.  */
++  final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
++				   0, 0, OPTAB_WIDEN);
++
++  /* Emit the start of the loop.  */
++  label = gen_label_rtx ();
++  emit_label (label);
++  
++  /* Emit the loop body.  */
++  arm_block_move_unaligned_straight (dest, src, bytes_per_iter,
++				     interleave_factor);
++
++  /* Move on to the next block.  */
++  emit_move_insn (src_reg, plus_constant (src_reg, bytes_per_iter));
++  emit_move_insn (dest_reg, plus_constant (dest_reg, bytes_per_iter));
++  
++  /* Emit the loop condition.  */
++  test = gen_rtx_NE (VOIDmode, src_reg, final_src);
++  emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
++  
++  /* Mop up any left-over bytes.  */
++  if (leftover)
++    arm_block_move_unaligned_straight (dest, src, leftover, interleave_factor);
++}
++
++/* Emit a block move when either the source or destination is unaligned (not
++   aligned to a four-byte boundary).  This may need further tuning depending on
++   core type, optimize_size setting, etc.  */
++
++static int
++arm_movmemqi_unaligned (rtx *operands)
++{
++  HOST_WIDE_INT length = INTVAL (operands[2]);
++  
++  if (optimize_size)
++    {
++      bool src_aligned = MEM_ALIGN (operands[1]) >= BITS_PER_WORD;
++      bool dst_aligned = MEM_ALIGN (operands[0]) >= BITS_PER_WORD;
++      /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
++	 size of code if optimizing for size.  We'll use ldm/stm if src_aligned
++	 or dst_aligned though: allow more interleaving in those cases since the
++	 resulting code can be smaller.  */
++      unsigned int interleave_factor = (src_aligned || dst_aligned) ? 2 : 1;
++      HOST_WIDE_INT bytes_per_iter = (src_aligned || dst_aligned) ? 8 : 4;
++      
++      if (length > 12)
++	arm_block_move_unaligned_loop (operands[0], operands[1], length,
++				       interleave_factor, bytes_per_iter);
++      else
++	arm_block_move_unaligned_straight (operands[0], operands[1], length,
++					   interleave_factor);
++    }
++  else
++    {
++      /* Note that the loop created by arm_block_move_unaligned_loop may be
++	 subject to loop unrolling, which makes tuning this condition a little
++	 redundant.  */
++      if (length > 32)
++	arm_block_move_unaligned_loop (operands[0], operands[1], length, 4, 16);
++      else
++	arm_block_move_unaligned_straight (operands[0], operands[1], length, 4);
++    }
++  
++  return 1;
++}
++
+ int
+ arm_gen_movmemqi (rtx *operands)
+ {
+@@ -10815,8 +11144,13 @@
+ 
+   if (GET_CODE (operands[2]) != CONST_INT
+       || GET_CODE (operands[3]) != CONST_INT
+-      || INTVAL (operands[2]) > 64
+-      || INTVAL (operands[3]) & 3)
++      || INTVAL (operands[2]) > 64)
++    return 0;
++
++  if (unaligned_access && (INTVAL (operands[3]) & 3) != 0)
++    return arm_movmemqi_unaligned (operands);
++
++  if (INTVAL (operands[3]) & 3)
+     return 0;
+ 
+   dstbase = operands[0];
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-10-19 17:01:50 +0000
++++ new/gcc/config/arm/arm.h	2011-11-21 01:45:54 +0000
+@@ -47,6 +47,8 @@
+     {							\
+ 	if (TARGET_DSP_MULTIPLY)			\
+ 	   builtin_define ("__ARM_FEATURE_DSP");	\
++	if (unaligned_access)				\
++	  builtin_define ("__ARM_FEATURE_UNALIGNED");	\
+ 	/* Define __arm__ even when in thumb mode, for	\
+ 	   consistency with armcc.  */			\
+ 	builtin_define ("__arm__");			\
+
+=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c'
+--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c	2011-10-19 22:56:19 +0000
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_unaligned } */
++/* { dg-options "-O2" } */
++
++#include <string.h>
++
++void unknown_alignment (char *dest, char *src)
++{
++  memcpy (dest, src, 15);
++}
++
++/* We should see three unaligned word loads and store pairs, one unaligned
++   ldrh/strh pair, and an ldrb/strb pair.  Sanity check that.  */
++
++/* { dg-final { scan-assembler-times "@ unaligned" 8 } } */
++/* { dg-final { scan-assembler-times "ldrh" 1 } } */
++/* { dg-final { scan-assembler-times "strh" 1 } } */
++/* { dg-final { scan-assembler-times "ldrb" 1 } } */
++/* { dg-final { scan-assembler-times "strb" 1 } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c'
+--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c	2011-10-19 22:56:19 +0000
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_unaligned } */
++/* { dg-options "-O2" } */
++
++#include <string.h>
++
++char dest[16];
++
++void aligned_dest (char *src)
++{
++  memcpy (dest, src, 15);
++}
++
++/* Expect a multi-word store for the main part of the copy, but subword
++   loads/stores for the remainder.  */
++
++/* { dg-final { scan-assembler-times "stmia" 1 } } */
++/* { dg-final { scan-assembler-times "ldrh" 1 } } */
++/* { dg-final { scan-assembler-times "strh" 1 } } */
++/* { dg-final { scan-assembler-times "ldrb" 1 } } */
++/* { dg-final { scan-assembler-times "strb" 1 } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c'
+--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c	2011-10-19 22:56:19 +0000
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_unaligned } */
++/* { dg-options "-O2" } */
++
++#include <string.h>
++
++char src[16];
++
++void aligned_src (char *dest)
++{
++  memcpy (dest, src, 15);
++}
++
++/* Expect a multi-word load for the main part of the copy, but subword
++   loads/stores for the remainder.  */
++
++/* { dg-final { scan-assembler-times "ldmia" 1 } } */
++/* { dg-final { scan-assembler-times "ldrh" 1 } } */
++/* { dg-final { scan-assembler-times "strh" 1 } } */
++/* { dg-final { scan-assembler-times "ldrb" 1 } } */
++/* { dg-final { scan-assembler-times "strb" 1 } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c'
+--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c	2011-10-19 22:56:19 +0000
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_unaligned } */
++/* { dg-options "-O2" } */
++
++#include <string.h>
++
++char src[16];
++char dest[16];
++
++void aligned_both (void)
++{
++  memcpy (dest, src, 15);
++}
++
++/* We know both src and dest to be aligned: expect multiword loads/stores.  */
++
++/* { dg-final { scan-assembler-times "ldmia" 1 } } */
++/* { dg-final { scan-assembler-times "stmia" 1 } } */
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-10-23 13:33:07 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-11-21 01:45:54 +0000
+@@ -1894,6 +1894,18 @@
+     }]
+ }
+ 
++# Return 1 if this is an ARM target that supports unaligned word/halfword
++# load/store instructions.
++
++proc check_effective_target_arm_unaligned { } {
++    return [check_no_compiler_messages arm_unaligned assembly {
++	#ifndef __ARM_FEATURE_UNALIGNED
++	#error no unaligned support
++	#endif
++	int i;
++    }]
++}
++
+ # Add the options needed for NEON.  We need either -mfloat-abi=softfp
+ # or -mfloat-abi=hard, but if one is already specified by the
+ # multilib, use it.  Similarly, if a -mfpu option already enables
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch
new file mode 100644
index 0000000000..2cf2741ba6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch
@@ -0,0 +1,375 @@
+2011-11-22  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-10-06  Jakub Jelinek  <jakub@redhat.com>
+
+	gcc/
+	PR tree-optimization/50596
+	* tree-vectorizer.h (vect_is_simple_cond): New prototype.
+	(NUM_PATTERNS): Change to 6.
+	* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): New
+	function.
+	(vect_vect_recog_func_ptrs): Add vect_recog_mixed_size_cond_pattern.
+	(vect_mark_pattern_stmts): Don't create stmt_vinfo for def_stmt
+	if it already has one, and don't set STMT_VINFO_VECTYPE in it
+	if it is already set.
+	* tree-vect-stmts.c (vect_mark_stmts_to_be_vectorized): Handle
+	COND_EXPR in pattern stmts.
+	(vect_is_simple_cond): No longer static.
+
+	gcc/testsuite:
+	PR tree-optimization/50596
+	* gcc.dg/vect/vect-cond-8.c: New test.
+
+	2011-10-07  Jakub Jelinek  <jakub@redhat.com>
+
+	gcc/
+	PR tree-optimization/50650
+	* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Don't
+	call vect_is_simple_cond here, instead fail if cond_expr isn't
+	COMPARISON_CLASS_P or if get_vectype_for_scalar_type returns NULL
+	for cond_expr's first operand.
+	* tree-vect-stmts.c (vect_is_simple_cond): Static again.
+	* tree-vectorizer.h (vect_is_simple_cond): Remove prototype.
+
+
+	gcc/
+	* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Reduce
+	it to integral types only.
+
+	gcc/testsuite/
+	* gcc.dg/vect/pr30858.c: Expect the error message twice for targets
+	with multiple vector sizes.
+	* gcc.dg/vect/vect-cond-8.c: Rename to...
+	* gcc.dg/vect/vect-cond-8a.c: ... this and change the type from float
+	to int.
+	* lib/target-supports.exp (check_effective_target_vect_condition):
+	Return true for NEON.
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/pr30858.c'
+Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/pr30858.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.dg/vect/pr30858.c	2012-01-04 15:33:52.000000000 -0800
++++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/pr30858.c	2012-03-05 16:23:47.748983031 -0800
+@@ -11,5 +11,6 @@
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
+-/* { dg-final { scan-tree-dump-times "Unknown def-use cycle pattern." 1 "vect" } } */
++/* { dg-final { scan-tree-dump-times "Unknown def-use cycle pattern." 1 "vect" { xfail vect_multiple_sizes } } } */
++/* { dg-final { scan-tree-dump-times "Unknown def-use cycle pattern." 2 "vect" { target vect_multiple_sizes } } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-cond-8a.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-cond-8a.c	2012-03-05 16:23:47.748983031 -0800
+@@ -0,0 +1,75 @@
++/* { dg-require-effective-target vect_condition } */
++
++#include "tree-vect.h"
++
++#define N 1024
++int a[N], b[N], c[N];
++char d[N], e[N], f[N];
++unsigned char k[N];
++
++__attribute__((noinline, noclone)) void
++f1 (void)
++{
++  int i;
++  for (i = 0; i < N; ++i)
++    k[i] = a[i] < b[i] ? 17 : 0;
++}
++
++__attribute__((noinline, noclone)) void
++f2 (void)
++{
++  int i;
++  for (i = 0; i < N; ++i)
++    k[i] = a[i] < b[i] ? 0 : 24;
++}
++
++__attribute__((noinline, noclone)) void
++f3 (void)
++{
++  int i;
++  for (i = 0; i < N; ++i)
++    k[i] = a[i] < b[i] ? 51 : 12;
++}
++
++int
++main ()
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      switch (i % 9)
++	{
++	case 0: asm (""); a[i] = - i - 1; b[i] = i + 1; break;
++	case 1: a[i] = 0; b[i] = 0; break;
++	case 2: a[i] = i + 1; b[i] = - i - 1; break;
++	case 3: a[i] = i; b[i] = i + 7; break;
++	case 4: a[i] = i; b[i] = i; break;
++	case 5: a[i] = i + 16; b[i] = i + 3; break;
++	case 6: a[i] = - i - 5; b[i] = - i; break;
++	case 7: a[i] = - i; b[i] = - i; break;
++	case 8: a[i] = - i; b[i] = - i - 7; break;
++	}
++      d[i] = i;
++      e[i] = 2 * i;
++    }
++  f1 ();
++  for (i = 0; i < N; i++)
++    if (k[i] != ((i % 3) == 0 ? 17 : 0))
++      abort ();
++  f2 ();
++  for (i = 0; i < N; i++)
++    if (k[i] != ((i % 3) == 0 ? 0 : 24))
++      abort ();
++  f3 ();
++  for (i = 0; i < N; i++)
++    if (k[i] != ((i % 3) == 0 ? 51 : 12))
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops" 3 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+Index: gcc-4_6-branch/gcc/tree-vect-patterns.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vect-patterns.c	2012-03-05 16:23:10.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vect-patterns.c	2012-03-05 16:23:47.748983031 -0800
+@@ -50,13 +50,16 @@
+                                                  tree *);
+ static gimple vect_recog_widen_shift_pattern (VEC (gimple, heap) **,
+                                        tree *, tree *);
++static gimple vect_recog_mixed_size_cond_pattern (VEC (gimple, heap) **,
++                                                 tree *, tree *);
+ static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
+ 	vect_recog_widen_mult_pattern,
+ 	vect_recog_widen_sum_pattern,
+ 	vect_recog_dot_prod_pattern,
+ 	vect_recog_pow_pattern,
+         vect_recog_over_widening_pattern,
+-	vect_recog_widen_shift_pattern};
++	vect_recog_widen_shift_pattern,
++	vect_recog_mixed_size_cond_pattern};
+ 
+ 
+ /* Function widened_name_p
+@@ -1441,6 +1444,118 @@
+   return pattern_stmt;
+ }
+ 
++/* Function vect_recog_mixed_size_cond_pattern
++
++   Try to find the following pattern:
++
++     type x_t, y_t;
++     TYPE a_T, b_T, c_T;
++   loop:
++     S1  a_T = x_t CMP y_t ? b_T : c_T;
++
++   where type 'TYPE' is an integral type which has different size
++   from 'type'.  b_T and c_T are constants and if 'TYPE' is wider
++   than 'type', the constants need to fit into an integer type
++   with the same width as 'type'.
++
++   Input:
++
++   * LAST_STMT: A stmt from which the pattern search begins.
++
++   Output:
++
++   * TYPE_IN: The type of the input arguments to the pattern.
++
++   * TYPE_OUT: The type of the output of this pattern.
++
++   * Return value: A new stmt that will be used to replace the pattern.
++	Additionally a def_stmt is added.
++
++	a_it = x_t CMP y_t ? b_it : c_it;
++	a_T = (TYPE) a_it;  */
++
++static gimple
++vect_recog_mixed_size_cond_pattern (VEC (gimple, heap) **stmts, tree *type_in,
++				    tree *type_out)
++{
++  gimple last_stmt = VEC_index (gimple, *stmts, 0);
++  tree cond_expr, then_clause, else_clause;
++  stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt), def_stmt_info;
++  tree type, vectype, comp_vectype, comp_type, op, tmp;
++  enum machine_mode cmpmode;
++  gimple pattern_stmt, def_stmt;
++  loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
++
++  if (!is_gimple_assign (last_stmt)
++      || gimple_assign_rhs_code (last_stmt) != COND_EXPR
++      || STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_internal_def)
++    return NULL;
++
++  op = gimple_assign_rhs1 (last_stmt);
++  cond_expr = TREE_OPERAND (op, 0);
++  then_clause = TREE_OPERAND (op, 1);
++  else_clause = TREE_OPERAND (op, 2);
++
++  if (TREE_CODE (then_clause) != INTEGER_CST
++      || TREE_CODE (else_clause) != INTEGER_CST)
++    return NULL;
++
++  if (!COMPARISON_CLASS_P (cond_expr))
++    return NULL;
++
++  type = gimple_expr_type (last_stmt);
++  comp_type = TREE_TYPE (TREE_OPERAND (cond_expr, 0));
++  if (!INTEGRAL_TYPE_P (comp_type)
++      || !INTEGRAL_TYPE_P (type))
++    return NULL;
++
++  comp_vectype = get_vectype_for_scalar_type (comp_type);
++  if (comp_vectype == NULL_TREE)
++    return NULL;
++
++  cmpmode = GET_MODE_INNER (TYPE_MODE (comp_vectype));
++
++  if (GET_MODE_BITSIZE (TYPE_MODE (type)) == GET_MODE_BITSIZE (cmpmode))
++    return NULL;
++
++  vectype = get_vectype_for_scalar_type (type);
++  if (vectype == NULL_TREE)
++    return NULL;
++
++  if (types_compatible_p (vectype, comp_vectype))
++    return NULL;
++
++  if (!expand_vec_cond_expr_p (comp_vectype, TYPE_MODE (comp_vectype)))
++    return NULL;
++
++  if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode))
++    {
++      if (!int_fits_type_p (then_clause, comp_type)
++	  || !int_fits_type_p (else_clause, comp_type))
++	return NULL;
++    }
++
++  tmp = build3 (COND_EXPR, comp_type, unshare_expr (cond_expr),
++		fold_convert (comp_type, then_clause),
++	       	fold_convert (comp_type, else_clause));
++  def_stmt = gimple_build_assign (vect_recog_temp_ssa_var (comp_type, NULL), tmp);
++
++  pattern_stmt
++    = gimple_build_assign_with_ops (NOP_EXPR,
++				    vect_recog_temp_ssa_var (type, NULL),
++				    gimple_assign_lhs (def_stmt), NULL_TREE);
++
++  STMT_VINFO_PATTERN_DEF_STMT (stmt_vinfo) = def_stmt;
++  def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
++  set_vinfo_for_stmt (def_stmt, def_stmt_info);
++  STMT_VINFO_VECTYPE (def_stmt_info) = comp_vectype;
++  *type_in = vectype;
++  *type_out = vectype;
++
++  return pattern_stmt;
++}
++
++
+ /* Mark statements that are involved in a pattern.  */
+ 
+ static inline void
+@@ -1468,14 +1583,18 @@
+   if (STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info))
+     {
+       def_stmt = STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info);
+-      set_vinfo_for_stmt (def_stmt,
+-                          new_stmt_vec_info (def_stmt, loop_vinfo, NULL));
+-      gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
+       def_stmt_info = vinfo_for_stmt (def_stmt);
++      if (def_stmt_info == NULL)
++	{
++	  def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
++	  set_vinfo_for_stmt (def_stmt, def_stmt_info);
++	}
++      gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
+       STMT_VINFO_RELATED_STMT (def_stmt_info) = orig_stmt;
+       STMT_VINFO_DEF_TYPE (def_stmt_info)
+ 	= STMT_VINFO_DEF_TYPE (orig_stmt_info);
+-      STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
++      if (STMT_VINFO_VECTYPE (def_stmt_info) == NULL_TREE)
++	STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
+     }
+ }
+ 
+Index: gcc-4_6-branch/gcc/tree-vect-stmts.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vect-stmts.c	2012-03-05 16:23:11.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vect-stmts.c	2012-03-05 16:23:47.748983031 -0800
+@@ -655,20 +655,40 @@
+               tree rhs = gimple_assign_rhs1 (stmt);
+               unsigned int op_num;
+               tree op;
++	      enum tree_code rhs_code;
+               switch (get_gimple_rhs_class (gimple_assign_rhs_code (stmt)))
+                 {
+                   case GIMPLE_SINGLE_RHS:
+-                     op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1 (stmt));
+-                     for (i = 0; i < op_num; i++)
+-                       {
+-                         op = TREE_OPERAND (rhs, i);
+-                         if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
+-                                           &worklist))
+-                           {
+-                             VEC_free (gimple, heap, worklist);
+-                             return false;
+-                           }
+-                       }
++                    op = gimple_assign_rhs1 (stmt);
++                    rhs_code = gimple_assign_rhs_code (stmt);
++		    i = 0;
++		    if (rhs_code == COND_EXPR
++			&& COMPARISON_CLASS_P (TREE_OPERAND (op, 0)))
++		      {
++			op = TREE_OPERAND (op, 0);
++			if (!process_use (stmt, TREE_OPERAND (op, 0),
++				   	  loop_vinfo,
++					  live_p, relevant, &worklist)
++			    || !process_use (stmt, TREE_OPERAND (op, 1),
++				   	 loop_vinfo,
++				         live_p, relevant, &worklist))
++		    	  {
++			    VEC_free (gimple, heap, worklist);
++			    return false;
++			  }
++		  	i = 1;
++		      }
++                    op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1 (stmt));
++                    for (i; i < op_num; i++)
++                      {
++                        op = TREE_OPERAND (rhs, i);
++                        if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
++                                          &worklist))
++                          {
++                            VEC_free (gimple, heap, worklist);
++                            return false;
++                          }
++                      }
+                     break;
+                    
+                   case GIMPLE_BINARY_RHS:
+Index: gcc-4_6-branch/gcc/tree-vectorizer.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/tree-vectorizer.h	2012-03-05 16:23:11.000000000 -0800
++++ gcc-4_6-branch/gcc/tree-vectorizer.h	2012-03-05 16:23:47.748983031 -0800
+@@ -917,7 +917,7 @@
+    Additional pattern recognition functions can (and will) be added
+    in the future.  */
+ typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+-#define NUM_PATTERNS 6 
++#define NUM_PATTERNS 7 
+ void vect_pattern_recog (loop_vec_info);
+ 
+ /* In tree-vectorizer.c.  */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch
new file mode 100644
index 0000000000..ea42ad6eeb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch
@@ -0,0 +1,805 @@
+2011-11-22  Ira Rosen  <ira.rosen@linaro.org>
+ 	Backport from mainline:
+ 
+	2011-11-06  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vectorizer.h (vectorizable_condition): Add argument.
+	* tree-vect-loop.c (vectorizable_reduction): Fail for condition
+	in SLP.  Update calls to vectorizable_condition.
+	* tree-vect-stmts.c (vect_is_simple_cond): Add basic block info to
+	the arguments.  Pass it to vect_is_simple_use_1.
+	(vectorizable_condition): Add slp_node to the arguments.  Support
+	vectorization of basic blocks.  Fail for reduction in SLP.  Update
+	calls to vect_is_simple_cond and vect_is_simple_use.  Support SLP:
+	call vect_get_slp_defs to get vector operands.
+	(vect_analyze_stmt): Update calls to vectorizable_condition.
+	(vect_transform_stmt): Likewise.
+	* tree-vect-slp.c (vect_create_new_slp_node): Handle COND_EXPR.
+	(vect_get_and_check_slp_defs): Handle COND_EXPR.  Allow pattern
+	def stmts.
+	(vect_build_slp_tree): Handle COND_EXPR.
+	(vect_analyze_slp_instance): Push pattern statements to root node.
+	(vect_get_constant_vectors): Fix comments.  Handle COND_EXPR.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-cond-1.c: New test.
+	* gcc.dg/vect/slp-cond-1.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c	2011-11-20 08:24:08 +0000
+@@ -0,0 +1,46 @@
++/* { dg-require-effective-target vect_condition } */
++
++#include "tree-vect.h"
++
++#define N 128
++
++__attribute__((noinline, noclone)) void
++foo (int *a, int stride)
++{
++  int i;
++
++  for (i = 0; i < N/stride; i++, a += stride)
++   {
++     a[0] = a[0] ? 1 : 5;
++     a[1] = a[1] ? 2 : 6;
++     a[2] = a[2] ? 3 : 7;
++     a[3] = a[3] ? 4 : 8;
++   }
++}
++
++
++int a[N];
++int main ()
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    a[i] = i;
++
++  foo (a, 4);
++
++  for (i = 1; i < N; i++)
++    if (a[i] != i%4 + 1)
++      abort ();
++
++  if (a[0] != 5)
++    abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/slp-cond-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/slp-cond-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/slp-cond-1.c	2011-11-20 08:24:08 +0000
+@@ -0,0 +1,126 @@
++/* { dg-require-effective-target vect_condition } */
++#include "tree-vect.h"
++
++#define N 32
++int a[N], b[N];
++int d[N], e[N];
++int k[N];
++
++__attribute__((noinline, noclone)) void
++f1 (void)
++{
++  int i;
++  for (i = 0; i < N/4; i++)
++    {
++      k[4*i] = a[4*i] < b[4*i] ? 17 : 0;
++      k[4*i+1] = a[4*i+1] < b[4*i+1] ? 17 : 0;
++      k[4*i+2] = a[4*i+2] < b[4*i+2] ? 17 : 0;
++      k[4*i+3] = a[4*i+3] < b[4*i+3] ? 17 : 0;
++    }
++}
++
++__attribute__((noinline, noclone)) void
++f2 (void)
++{
++  int i;
++  for (i = 0; i < N/2; ++i)
++    {
++      k[2*i] = a[2*i] < b[2*i] ? 0 : 24;
++      k[2*i+1] = a[2*i+1] < b[2*i+1] ? 7 : 4;
++    }
++}
++
++__attribute__((noinline, noclone)) void
++f3 (void)
++{
++  int i;
++  for (i = 0; i < N/2; ++i)
++    {
++      k[2*i] = a[2*i] < b[2*i] ? 51 : 12;
++      k[2*i+1] = a[2*i+1] > b[2*i+1] ? 51 : 12;
++    }
++}
++
++__attribute__((noinline, noclone)) void
++f4 (void)
++{
++  int i;
++  for (i = 0; i < N/2; ++i)
++    {
++      int d0 = d[2*i], e0 = e[2*i];
++      int d1 = d[2*i+1], e1 = e[2*i+1];
++      k[2*i] = a[2*i] >= b[2*i] ? d0 : e0;
++      k[2*i+1] = a[2*i+1] >= b[2*i+1] ? d1 : e1;
++    }
++}
++
++int
++main ()
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      switch (i % 9)
++	{
++	case 0: asm (""); a[i] = - i - 1; b[i] = i + 1; break;
++	case 1: a[i] = 0; b[i] = 0; break;
++	case 2: a[i] = i + 1; b[i] = - i - 1; break;
++	case 3: a[i] = i; b[i] = i + 7; break;
++	case 4: a[i] = i; b[i] = i; break;
++	case 5: a[i] = i + 16; b[i] = i + 3; break;
++	case 6: a[i] = - i - 5; b[i] = - i; break;
++	case 7: a[i] = - i; b[i] = - i; break;
++	case 8: a[i] = - i; b[i] = - i - 7; break;
++	}
++      d[i] = i;
++      e[i] = 2 * i;
++    }
++  f1 ();
++  for (i = 0; i < N; i++)
++    if (k[i] != ((i % 3) == 0 ? 17 : 0))
++      abort ();
++
++  f2 ();
++  for (i = 0; i < N; i++)
++    {
++      switch (i % 9)
++        {
++        case 0:
++	case 6:
++	  if (k[i] != ((i/9 % 2) == 0 ? 0 : 7))
++	    abort ();
++	  break;
++        case 1:
++        case 5:
++        case 7:
++	  if (k[i] != ((i/9 % 2) == 0 ? 4 : 24))
++            abort ();
++          break;
++        case 2:
++        case 4:
++        case 8:
++	  if (k[i] != ((i/9 % 2) == 0 ? 24 : 4))
++            abort ();
++          break;
++        case 3:
++	  if (k[i] != ((i/9 % 2) == 0 ? 7 : 0))
++            abort ();
++          break;
++        }
++    }
++
++  f3 ();
++
++  f4 ();
++  for (i = 0; i < N; i++)
++    if (k[i] != ((i % 3) == 0 ? e[i] : d[i]))
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" } } */
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/tree-vect-loop.c'
+--- old/gcc/tree-vect-loop.c	2011-11-14 11:38:08 +0000
++++ new/gcc/tree-vect-loop.c	2011-11-20 08:24:08 +0000
+@@ -4087,6 +4087,9 @@
+       gcc_unreachable ();
+     }
+ 
++  if (code == COND_EXPR && slp_node)
++    return false;
++
+   scalar_dest = gimple_assign_lhs (stmt);
+   scalar_type = TREE_TYPE (scalar_dest);
+   if (!POINTER_TYPE_P (scalar_type) && !INTEGRAL_TYPE_P (scalar_type)
+@@ -4161,7 +4164,7 @@
+ 
+   if (code == COND_EXPR)
+     {
+-      if (!vectorizable_condition (stmt, gsi, NULL, ops[reduc_index], 0))
++      if (!vectorizable_condition (stmt, gsi, NULL, ops[reduc_index], 0, NULL))
+         {
+           if (vect_print_dump_info (REPORT_DETAILS))
+             fprintf (vect_dump, "unsupported condition in reduction");
+@@ -4433,7 +4436,7 @@
+           gcc_assert (!slp_node);
+           vectorizable_condition (stmt, gsi, vec_stmt, 
+                                   PHI_RESULT (VEC_index (gimple, phis, 0)), 
+-                                  reduc_index);
++                                  reduc_index, NULL);
+           /* Multiple types are not supported for condition.  */
+           break;
+         }
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-11-14 11:38:08 +0000
++++ new/gcc/tree-vect-slp.c	2011-11-21 06:58:40 +0000
+@@ -109,7 +109,11 @@
+   if (is_gimple_call (stmt))
+     nops = gimple_call_num_args (stmt);
+   else if (is_gimple_assign (stmt))
+-    nops = gimple_num_ops (stmt) - 1;
++    {
++      nops = gimple_num_ops (stmt) - 1;
++      if (gimple_assign_rhs_code (stmt) == COND_EXPR)
++	nops = 4;
++    }
+   else
+     return NULL;
+ 
+@@ -190,20 +194,51 @@
+   bool different_types = false;
+   bool pattern = false;
+   slp_oprnd_info oprnd_info, oprnd0_info, oprnd1_info;
++  int op_idx = 1;
++  tree compare_rhs = NULL_TREE, rhs = NULL_TREE;
++  int cond_idx = -1;
+ 
+   if (loop_vinfo)
+     loop = LOOP_VINFO_LOOP (loop_vinfo);
+ 
+   if (is_gimple_call (stmt))
+     number_of_oprnds = gimple_call_num_args (stmt);
++  else if (is_gimple_assign (stmt))
++    {
++      number_of_oprnds = gimple_num_ops (stmt) - 1;
++      if (gimple_assign_rhs_code (stmt) == COND_EXPR)
++	{ 	      
++          number_of_oprnds = 4;
++	  cond_idx = 0;
++	  rhs = gimple_assign_rhs1 (stmt);
++	}	  
++    }
+   else
+-    number_of_oprnds = gimple_num_ops (stmt) - 1;
++    return false;
+ 
+   for (i = 0; i < number_of_oprnds; i++)
+     {
+-      oprnd = gimple_op (stmt, i + 1);
++      if (compare_rhs)
++	oprnd = compare_rhs;
++      else
++        oprnd = gimple_op (stmt, op_idx++);
++
+       oprnd_info = VEC_index (slp_oprnd_info, *oprnds_info, i);
+ 
++      if (-1 < cond_idx && cond_idx < 4)
++	{
++  	  if (compare_rhs)
++	    compare_rhs = NULL_TREE;
++	  else	  
++	    oprnd = TREE_OPERAND (rhs, cond_idx++);
++	}
++		      
++      if (COMPARISON_CLASS_P (oprnd))
++        {
++          compare_rhs = TREE_OPERAND (oprnd, 1);
++          oprnd = TREE_OPERAND (oprnd, 0);
++	}
++
+       if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def,
+                                &dt)
+ 	  || (!def_stmt && dt != vect_constant_def))
+@@ -243,8 +278,7 @@
+           def_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
+           dt = STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def_stmt));
+ 
+-          if (dt == vect_unknown_def_type
+-	      || STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (def_stmt)))
++          if (dt == vect_unknown_def_type)
+             {
+               if (vect_print_dump_info (REPORT_DETAILS))
+                 fprintf (vect_dump, "Unsupported pattern.");
+@@ -423,6 +457,7 @@
+   VEC (gimple, heap) *stmts = SLP_TREE_SCALAR_STMTS (*node);
+   gimple stmt = VEC_index (gimple, stmts, 0);
+   enum tree_code first_stmt_code = ERROR_MARK, rhs_code = ERROR_MARK;
++  enum tree_code first_cond_code = ERROR_MARK;
+   tree lhs;
+   bool stop_recursion = false, need_same_oprnds = false;
+   tree vectype, scalar_type, first_op1 = NULL_TREE;
+@@ -439,11 +474,18 @@
+   VEC (slp_oprnd_info, heap) *oprnds_info;
+   unsigned int nops;
+   slp_oprnd_info oprnd_info;
++  tree cond;
+ 
+   if (is_gimple_call (stmt))
+     nops = gimple_call_num_args (stmt);
++  else if (is_gimple_assign (stmt))
++    {
++      nops = gimple_num_ops (stmt) - 1;
++      if (gimple_assign_rhs_code (stmt) == COND_EXPR)
++	nops = 4;
++    }
+   else
+-    nops = gimple_num_ops (stmt) - 1;
++    return false;
+ 
+   oprnds_info = vect_create_oprnd_info (nops, group_size);
+ 
+@@ -484,6 +526,22 @@
+ 	  return false;
+ 	}
+ 
++       if (is_gimple_assign (stmt)
++	   && gimple_assign_rhs_code (stmt) == COND_EXPR
++           && (cond = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0))
++           && !COMPARISON_CLASS_P (cond))
++        {
++          if (vect_print_dump_info (REPORT_SLP))
++            {
++              fprintf (vect_dump,
++                       "Build SLP failed: condition is not comparison ");
++              print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++            }
++
++          vect_free_oprnd_info (&oprnds_info);
++          return false;
++        }
++
+       scalar_type = vect_get_smallest_scalar_type (stmt, &dummy, &dummy);
+       vectype = get_vectype_for_scalar_type (scalar_type);
+       if (!vectype)
+@@ -737,7 +795,8 @@
+ 
+ 	  /* Not memory operation.  */
+ 	  if (TREE_CODE_CLASS (rhs_code) != tcc_binary
+-	      && TREE_CODE_CLASS (rhs_code) != tcc_unary)
++	      && TREE_CODE_CLASS (rhs_code) != tcc_unary
++              && rhs_code != COND_EXPR)
+ 	    {
+ 	      if (vect_print_dump_info (REPORT_SLP))
+ 		{
+@@ -750,6 +809,26 @@
+ 	      return false;
+ 	    }
+ 
++          if (rhs_code == COND_EXPR)
++            {
++              tree cond_expr = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0);
++
++	      if (i == 0)
++		first_cond_code = TREE_CODE (cond_expr);
++              else if (first_cond_code != TREE_CODE (cond_expr))
++                {
++                  if (vect_print_dump_info (REPORT_SLP))
++                    {
++                      fprintf (vect_dump, "Build SLP failed: different"
++					  " operation");
++                      print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
++                    }
++
++		  vect_free_oprnd_info (&oprnds_info);
++                  return false;
++		}
++            }
++
+ 	  /* Find the def-stmts.  */
+ 	  if (!vect_get_and_check_slp_defs (loop_vinfo, bb_vinfo, *node, stmt,
+ 					    ncopies_for_cost, (i == 0),
+@@ -1395,7 +1474,12 @@
+       /* Collect the stores and store them in SLP_TREE_SCALAR_STMTS.  */
+       while (next)
+         {
+-          VEC_safe_push (gimple, heap, scalar_stmts, next);
++          if (STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (next))
++              && STMT_VINFO_RELATED_STMT (vinfo_for_stmt (next)))
++            VEC_safe_push (gimple, heap, scalar_stmts,
++                       STMT_VINFO_RELATED_STMT (vinfo_for_stmt (next)));
++          else
++            VEC_safe_push (gimple, heap, scalar_stmts, next);
+           next = DR_GROUP_NEXT_DR (vinfo_for_stmt (next));
+         }
+     }
+@@ -1404,7 +1488,7 @@
+       /* Collect reduction statements.  */
+       VEC (gimple, heap) *reductions = LOOP_VINFO_REDUCTIONS (loop_vinfo);
+       for (i = 0; VEC_iterate (gimple, reductions, i, next); i++)
+-        VEC_safe_push (gimple, heap, scalar_stmts, next);
++	VEC_safe_push (gimple, heap, scalar_stmts, next);
+     }
+ 
+   node = vect_create_new_slp_node (scalar_stmts);
+@@ -2160,15 +2244,15 @@
+ 
+      For example, we have two scalar operands, s1 and s2 (e.g., group of
+      strided accesses of size two), while NUNITS is four (i.e., four scalars
+-     of this type can be packed in a vector). The output vector will contain
+-     two copies of each scalar operand: {s1, s2, s1, s2}. (NUMBER_OF_COPIES
++     of this type can be packed in a vector).  The output vector will contain
++     two copies of each scalar operand: {s1, s2, s1, s2}.  (NUMBER_OF_COPIES
+      will be 2).
+ 
+      If GROUP_SIZE > NUNITS, the scalars will be split into several vectors
+      containing the operands.
+ 
+      For example, NUNITS is four as before, and the group size is 8
+-     (s1, s2, ..., s8). We will create two vectors {s1, s2, s3, s4} and
++     (s1, s2, ..., s8).  We will create two vectors {s1, s2, s3, s4} and
+      {s5, s6, s7, s8}.  */
+ 
+   number_of_copies = least_common_multiple (nunits, group_size) / group_size;
+@@ -2180,8 +2264,18 @@
+         {
+           if (is_store)
+             op = gimple_assign_rhs1 (stmt);
+-          else
++          else if (gimple_assign_rhs_code (stmt) != COND_EXPR)
+             op = gimple_op (stmt, op_num + 1);
++	  else
++	    {
++	      if (op_num == 0 || op_num == 1)
++		{
++		  tree cond = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0);
++		  op = TREE_OPERAND (cond, op_num);
++		}
++	      else
++		op = TREE_OPERAND (gimple_assign_rhs1 (stmt), op_num - 1);
++	    }
+ 
+           if (reduc_index != -1)
+             {
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-11-22 16:52:23 +0000
++++ new/gcc/tree-vect-stmts.c	2011-11-22 17:10:17 +0000
+@@ -4816,7 +4816,7 @@
+    condition operands are supportable using vec_is_simple_use.  */
+ 
+ static bool
+-vect_is_simple_cond (tree cond, loop_vec_info loop_vinfo)
++vect_is_simple_cond (tree cond, loop_vec_info loop_vinfo, bb_vec_info bb_vinfo)
+ {
+   tree lhs, rhs;
+   tree def;
+@@ -4831,7 +4831,7 @@
+   if (TREE_CODE (lhs) == SSA_NAME)
+     {
+       gimple lhs_def_stmt = SSA_NAME_DEF_STMT (lhs);
+-      if (!vect_is_simple_use (lhs, loop_vinfo, NULL, &lhs_def_stmt, &def,
++      if (!vect_is_simple_use (lhs, loop_vinfo, bb_vinfo, &lhs_def_stmt, &def,
+                                &dt))
+ 	return false;
+     }
+@@ -4842,7 +4842,7 @@
+   if (TREE_CODE (rhs) == SSA_NAME)
+     {
+       gimple rhs_def_stmt = SSA_NAME_DEF_STMT (rhs);
+-      if (!vect_is_simple_use (rhs, loop_vinfo, NULL, &rhs_def_stmt, &def,
++      if (!vect_is_simple_use (rhs, loop_vinfo, bb_vinfo, &rhs_def_stmt, &def,
+                                &dt))
+ 	return false;
+     }
+@@ -4868,7 +4868,8 @@
+ 
+ bool
+ vectorizable_condition (gimple stmt, gimple_stmt_iterator *gsi,
+-			gimple *vec_stmt, tree reduc_def, int reduc_index)
++			gimple *vec_stmt, tree reduc_def, int reduc_index,
++			slp_tree slp_node)
+ {
+   tree scalar_dest = NULL_TREE;
+   tree vec_dest = NULL_TREE;
+@@ -4885,19 +4886,24 @@
+   tree def;
+   enum vect_def_type dt, dts[4];
+   int nunits = TYPE_VECTOR_SUBPARTS (vectype);
+-  int ncopies = LOOP_VINFO_VECT_FACTOR (loop_vinfo) / nunits;
++  int ncopies;
+   enum tree_code code;
+   stmt_vec_info prev_stmt_info = NULL;
+-  int j;
++  int i, j;
++  bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
++  VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
++  VEC (tree, heap) *vec_oprnds2 = NULL, *vec_oprnds3 = NULL;
+ 
+-  /* FORNOW: unsupported in basic block SLP.  */
+-  gcc_assert (loop_vinfo);
++  if (slp_node || PURE_SLP_STMT (stmt_info))
++    ncopies = 1;
++  else
++    ncopies = LOOP_VINFO_VECT_FACTOR (loop_vinfo) / nunits;
+ 
+   gcc_assert (ncopies >= 1);
+-  if (reduc_index && ncopies > 1)
++  if (reduc_index && (ncopies > 1 || STMT_SLP_TYPE (stmt_info)))
+     return false; /* FORNOW */
+ 
+-  if (!STMT_VINFO_RELEVANT_P (stmt_info))
++  if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo) 
+     return false;
+ 
+   if (STMT_VINFO_DEF_TYPE (stmt_info) != vect_internal_def
+@@ -4905,10 +4911,6 @@
+            && reduc_def))
+     return false;
+ 
+-  /* FORNOW: SLP not supported.  */
+-  if (STMT_SLP_TYPE (stmt_info))
+-    return false;
+-
+   /* FORNOW: not yet supported.  */
+   if (STMT_VINFO_LIVE_P (stmt_info))
+     {
+@@ -4932,7 +4934,7 @@
+   then_clause = TREE_OPERAND (op, 1);
+   else_clause = TREE_OPERAND (op, 2);
+ 
+-  if (!vect_is_simple_cond (cond_expr, loop_vinfo))
++  if (!vect_is_simple_cond (cond_expr, loop_vinfo, bb_vinfo))
+     return false;
+ 
+   /* We do not handle two different vector types for the condition
+@@ -4944,7 +4946,7 @@
+   if (TREE_CODE (then_clause) == SSA_NAME)
+     {
+       gimple then_def_stmt = SSA_NAME_DEF_STMT (then_clause);
+-      if (!vect_is_simple_use (then_clause, loop_vinfo, NULL,
++      if (!vect_is_simple_use (then_clause, loop_vinfo, bb_vinfo,
+ 			       &then_def_stmt, &def, &dt))
+ 	return false;
+     }
+@@ -4956,7 +4958,7 @@
+   if (TREE_CODE (else_clause) == SSA_NAME)
+     {
+       gimple else_def_stmt = SSA_NAME_DEF_STMT (else_clause);
+-      if (!vect_is_simple_use (else_clause, loop_vinfo, NULL,
++      if (!vect_is_simple_use (else_clause, loop_vinfo, bb_vinfo,
+ 			       &else_def_stmt, &def, &dt))
+ 	return false;
+     }
+@@ -4974,7 +4976,15 @@
+       return expand_vec_cond_expr_p (TREE_TYPE (op), vec_mode);
+     }
+ 
+-  /* Transform */
++  /* Transform.  */
++
++  if (!slp_node)
++    {
++      vec_oprnds0 = VEC_alloc (tree, heap, 1);
++      vec_oprnds1 = VEC_alloc (tree, heap, 1);
++      vec_oprnds2 = VEC_alloc (tree, heap, 1);
++      vec_oprnds3 = VEC_alloc (tree, heap, 1);
++    }
+ 
+   /* Handle def.  */
+   scalar_dest = gimple_assign_lhs (stmt);
+@@ -4983,67 +4993,118 @@
+   /* Handle cond expr.  */
+   for (j = 0; j < ncopies; j++)
+     {
+-      gimple new_stmt;
++      gimple new_stmt = NULL;
+       if (j == 0)
+ 	{
+-	  gimple gtemp;
+-	  vec_cond_lhs =
++          if (slp_node)
++            {
++              VEC (tree, heap) *ops = VEC_alloc (tree, heap, 4);
++              VEC (slp_void_p, heap) *vec_defs;
++
++	      vec_defs = VEC_alloc (slp_void_p, heap, 4);
++              VEC_safe_push (tree, heap, ops, TREE_OPERAND (cond_expr, 0));
++              VEC_safe_push (tree, heap, ops, TREE_OPERAND (cond_expr, 1));
++              VEC_safe_push (tree, heap, ops, then_clause);
++              VEC_safe_push (tree, heap, ops, else_clause);
++              vect_get_slp_defs (ops, slp_node, &vec_defs, -1);
++              vec_oprnds3 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
++              vec_oprnds2 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
++              vec_oprnds1 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
++              vec_oprnds0 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
++
++              VEC_free (tree, heap, ops);
++              VEC_free (slp_void_p, heap, vec_defs);
++            }
++          else
++            {
++	      gimple gtemp;
++	      vec_cond_lhs =
+ 	      vect_get_vec_def_for_operand (TREE_OPERAND (cond_expr, 0),
+ 					    stmt, NULL);
+-	  vect_is_simple_use (TREE_OPERAND (cond_expr, 0), loop_vinfo,
++	      vect_is_simple_use (TREE_OPERAND (cond_expr, 0), loop_vinfo,
+ 			      NULL, &gtemp, &def, &dts[0]);
+-	  vec_cond_rhs =
+-	      vect_get_vec_def_for_operand (TREE_OPERAND (cond_expr, 1),
+-					    stmt, NULL);
+-	  vect_is_simple_use (TREE_OPERAND (cond_expr, 1), loop_vinfo,
+-			      NULL, &gtemp, &def, &dts[1]);
+-	  if (reduc_index == 1)
+-	    vec_then_clause = reduc_def;
+-	  else
+-	    {
+-	      vec_then_clause = vect_get_vec_def_for_operand (then_clause,
+-							      stmt, NULL);
+-	      vect_is_simple_use (then_clause, loop_vinfo,
+-				  NULL, &gtemp, &def, &dts[2]);
+-	    }
+-	  if (reduc_index == 2)
+-	    vec_else_clause = reduc_def;
+-	  else
+-	    {
+-	      vec_else_clause = vect_get_vec_def_for_operand (else_clause,
+-							      stmt, NULL);
+-	      vect_is_simple_use (else_clause, loop_vinfo,
++
++	      vec_cond_rhs =
++		vect_get_vec_def_for_operand (TREE_OPERAND (cond_expr, 1),
++						stmt, NULL);
++	      vect_is_simple_use (TREE_OPERAND (cond_expr, 1), loop_vinfo,
++					NULL, &gtemp, &def, &dts[1]);
++	      if (reduc_index == 1)
++		vec_then_clause = reduc_def;
++	      else
++		{
++		  vec_then_clause = vect_get_vec_def_for_operand (then_clause,
++		 		  			      stmt, NULL);
++	          vect_is_simple_use (then_clause, loop_vinfo,
++					  NULL, &gtemp, &def, &dts[2]);
++		}
++	      if (reduc_index == 2)
++		vec_else_clause = reduc_def;
++	      else
++		{
++		  vec_else_clause = vect_get_vec_def_for_operand (else_clause,
++							      stmt, NULL);
++		  vect_is_simple_use (else_clause, loop_vinfo,
+ 				  NULL, &gtemp, &def, &dts[3]);
++		}
+ 	    }
+ 	}
+       else
+ 	{
+-	  vec_cond_lhs = vect_get_vec_def_for_stmt_copy (dts[0], vec_cond_lhs);
+-	  vec_cond_rhs = vect_get_vec_def_for_stmt_copy (dts[1], vec_cond_rhs);
++	  vec_cond_lhs = vect_get_vec_def_for_stmt_copy (dts[0],
++						VEC_pop (tree, vec_oprnds0));
++	  vec_cond_rhs = vect_get_vec_def_for_stmt_copy (dts[1],
++						VEC_pop (tree, vec_oprnds1));
+ 	  vec_then_clause = vect_get_vec_def_for_stmt_copy (dts[2],
+-							    vec_then_clause);
++						VEC_pop (tree, vec_oprnds2));
+ 	  vec_else_clause = vect_get_vec_def_for_stmt_copy (dts[3],
+-							    vec_else_clause);
++						VEC_pop (tree, vec_oprnds3));
++	}
++
++      if (!slp_node)
++        {
++	  VEC_quick_push (tree, vec_oprnds0, vec_cond_lhs);
++	  VEC_quick_push (tree, vec_oprnds1, vec_cond_rhs);
++	  VEC_quick_push (tree, vec_oprnds2, vec_then_clause);
++	  VEC_quick_push (tree, vec_oprnds3, vec_else_clause);
+ 	}
+ 
+       /* Arguments are ready.  Create the new vector stmt.  */
+-      vec_compare = build2 (TREE_CODE (cond_expr), vectype,
+-			    vec_cond_lhs, vec_cond_rhs);
+-      vec_cond_expr = build3 (VEC_COND_EXPR, vectype,
+-			      vec_compare, vec_then_clause, vec_else_clause);
+-
+-      new_stmt = gimple_build_assign (vec_dest, vec_cond_expr);
+-      new_temp = make_ssa_name (vec_dest, new_stmt);
+-      gimple_assign_set_lhs (new_stmt, new_temp);
+-      vect_finish_stmt_generation (stmt, new_stmt, gsi);
+-      if (j == 0)
+-        STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
+-      else
+-        STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
+-
+-      prev_stmt_info = vinfo_for_stmt (new_stmt);
++      FOR_EACH_VEC_ELT (tree, vec_oprnds0, i, vec_cond_lhs)
++        {
++          vec_cond_rhs = VEC_index (tree, vec_oprnds1, i);
++          vec_then_clause = VEC_index (tree, vec_oprnds2, i);
++          vec_else_clause = VEC_index (tree, vec_oprnds3, i);
++
++          vec_compare = build2 (TREE_CODE (cond_expr), vectype,
++  			       vec_cond_lhs, vec_cond_rhs);
++          vec_cond_expr = build3 (VEC_COND_EXPR, vectype,
++ 		         vec_compare, vec_then_clause, vec_else_clause);
++
++          new_stmt = gimple_build_assign (vec_dest, vec_cond_expr);
++          new_temp = make_ssa_name (vec_dest, new_stmt);
++          gimple_assign_set_lhs (new_stmt, new_temp);
++          vect_finish_stmt_generation (stmt, new_stmt, gsi);
++          if (slp_node)
++            VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), new_stmt);
++        }
++
++        if (slp_node)
++          continue;
++
++        if (j == 0)
++          STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
++        else
++          STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
++
++        prev_stmt_info = vinfo_for_stmt (new_stmt);
+     }
+ 
++  VEC_free (tree, heap, vec_oprnds0);
++  VEC_free (tree, heap, vec_oprnds1);
++  VEC_free (tree, heap, vec_oprnds2);
++  VEC_free (tree, heap, vec_oprnds3);
++
+   return true;
+ }
+ 
+@@ -5217,7 +5278,7 @@
+             || vectorizable_call (stmt, NULL, NULL)
+             || vectorizable_store (stmt, NULL, NULL, NULL)
+             || vectorizable_reduction (stmt, NULL, NULL, NULL)
+-            || vectorizable_condition (stmt, NULL, NULL, NULL, 0));
++            || vectorizable_condition (stmt, NULL, NULL, NULL, 0, NULL));
+     else
+       {
+         if (bb_vinfo)
+@@ -5227,7 +5288,8 @@
+                 || vectorizable_operation (stmt, NULL, NULL, node)
+                 || vectorizable_assignment (stmt, NULL, NULL, node)
+                 || vectorizable_load (stmt, NULL, NULL, node, NULL)
+-                || vectorizable_store (stmt, NULL, NULL, node));
++                || vectorizable_store (stmt, NULL, NULL, node)
++                || vectorizable_condition (stmt, NULL, NULL, NULL, 0, node));
+       }
+ 
+   if (!ok)
+@@ -5343,8 +5405,7 @@
+       break;
+ 
+     case condition_vec_info_type:
+-      gcc_assert (!slp_node);
+-      done = vectorizable_condition (stmt, gsi, &vec_stmt, NULL, 0);
++      done = vectorizable_condition (stmt, gsi, &vec_stmt, NULL, 0, slp_node);
+       gcc_assert (done);
+       break;
+ 
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2011-11-22 16:52:23 +0000
++++ new/gcc/tree-vectorizer.h	2011-11-22 17:10:17 +0000
+@@ -832,7 +832,7 @@
+ extern void vect_remove_stores (gimple);
+ extern bool vect_analyze_stmt (gimple, bool *, slp_tree);
+ extern bool vectorizable_condition (gimple, gimple_stmt_iterator *, gimple *,
+-                                    tree, int);
++                                    tree, int, slp_tree);
+ extern void vect_get_load_cost (struct data_reference *, int, bool,
+                                 unsigned int *, unsigned int *);
+ extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch
new file mode 100644
index 0000000000..e501959c7a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch
@@ -0,0 +1,495 @@
+2011-11-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	gcc/
+	* tree-vectorizer.h (vect_pattern_recog): Add new argument.
+	* tree-vect-loop.c (vect_analyze_loop_2): Update call to
+	vect_pattern_recog.
+	* tree-vect-patterns.c (widened_name_p): Pass basic block
+	info to vect_is_simple_use.
+	(vect_recog_dot_prod_pattern): Fail for basic blocks.
+	(vect_recog_widen_sum_pattern): Likewise.
+	(vect_handle_widen_op_by_const): Support basic blocks.
+	(vect_operation_fits_smaller_type,
+	vect_recog_over_widening_pattern): Likewise.
+	(vect_recog_mixed_size_cond_pattern): Support basic blocks.
+	Add printing.
+	(vect_mark_pattern_stmts): Update calls to new_stmt_vec_info.
+	(vect_pattern_recog_1): Check for reduction only in loops.
+	(vect_pattern_recog): Add new argument.  Support basic blocks.
+	* tree-vect-stmts.c (vectorizable_conversion): Pass basic block
+	info to vect_is_simple_use_1.
+	* tree-vect-slp.c (vect_get_and_check_slp_defs): Support basic
+	blocks.
+	(vect_slp_analyze_bb_1): Call vect_pattern_recog.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-pattern-1.c: New test.
+	* gcc.dg/vect/bb-slp-pattern-2.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c	2011-11-23 06:37:10 +0000
+@@ -0,0 +1,55 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 8
++
++unsigned short X[N];
++unsigned short Y[N];
++unsigned int result[N];
++
++/* unsigned short->unsigned int widening-mult.  */
++__attribute__ ((noinline, noclone)) void 
++foo (void)
++{
++  result[0] = (unsigned int)(X[0] * Y[0]);
++  result[1] = (unsigned int)(X[1] * Y[1]);
++  result[2] = (unsigned int)(X[2] * Y[2]);
++  result[3] = (unsigned int)(X[3] * Y[3]);
++  result[4] = (unsigned int)(X[4] * Y[4]);
++  result[5] = (unsigned int)(X[5] * Y[5]);
++  result[6] = (unsigned int)(X[6] * Y[6]);
++  result[7] = (unsigned int)(X[7] * Y[7]);
++}
++
++int main (void)
++{
++  int i, tmp;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      X[i] = i;
++      Y[i] = 64-i;
++    }
++
++  foo ();
++
++  for (i = 0; i < N; i++)
++    {
++      __asm__ volatile ("");
++      tmp = X[i] * Y[i];
++      if (result[i] != tmp)
++        abort ();
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "slp" { target { vect_widen_mult_hi_to_si || vect_unpack } } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 8 "slp" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { scan-tree-dump-times "pattern recognized" 8 "slp" { target vect_widen_mult_hi_to_si_pattern } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-pattern-2.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-2.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-2.c	2011-11-23 06:37:10 +0000
+@@ -0,0 +1,53 @@
++/* { dg-require-effective-target vect_condition } */
++
++#include "tree-vect.h"
++
++#define N 128
++
++__attribute__((noinline, noclone)) void
++foo (short * __restrict__ a, int * __restrict__ b, int stride)
++{
++  int i;
++
++  for (i = 0; i < N/stride; i++, a += stride, b += stride)
++   {
++     a[0] = b[0] ? 1 : 7;
++     a[1] = b[1] ? 2 : 0;
++     a[2] = b[2] ? 3 : 0;
++     a[3] = b[3] ? 4 : 0;
++     a[4] = b[4] ? 5 : 0;
++     a[5] = b[5] ? 6 : 0;
++     a[6] = b[6] ? 7 : 0;
++     a[7] = b[7] ? 8 : 0;
++   }
++}
++
++short a[N];
++int b[N];
++int main ()
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      a[i] = i;
++      b[i] = -i;
++    }
++
++  foo (a, b, 8);
++
++  for (i = 1; i < N; i++)
++    if (a[i] != i%8 + 1)
++      abort ();
++
++  if (a[0] != 7)
++    abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_element_align && vect_pack_trunc } } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== modified file 'gcc/tree-vect-loop.c'
+--- old/gcc/tree-vect-loop.c	2011-11-20 08:24:08 +0000
++++ new/gcc/tree-vect-loop.c	2011-11-23 06:47:35 +0000
+@@ -1458,7 +1458,7 @@
+ 
+   vect_analyze_scalar_cycles (loop_vinfo);
+ 
+-  vect_pattern_recog (loop_vinfo);
++  vect_pattern_recog (loop_vinfo, NULL);
+ 
+   /* Data-flow analysis to detect stmts that do not need to be vectorized.  */
+ 
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2011-11-20 09:11:09 +0000
++++ new/gcc/tree-vect-patterns.c	2011-11-23 07:49:33 +0000
+@@ -83,11 +83,13 @@
+   tree oprnd0;
+   enum vect_def_type dt;
+   tree def;
++  bb_vec_info bb_vinfo;
+ 
+   stmt_vinfo = vinfo_for_stmt (use_stmt);
+   loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
++  bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
+ 
+-  if (!vect_is_simple_use (name, loop_vinfo, NULL, def_stmt, &def, &dt))
++  if (!vect_is_simple_use (name, loop_vinfo, bb_vinfo, def_stmt, &def, &dt))
+     return false;
+ 
+   if (dt != vect_internal_def
+@@ -111,7 +113,7 @@
+       || (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 2)))
+     return false;
+ 
+-  if (!vect_is_simple_use (oprnd0, loop_vinfo, NULL, &dummy_gimple, &dummy,
++  if (!vect_is_simple_use (oprnd0, loop_vinfo, bb_vinfo, &dummy_gimple, &dummy,
+                            &dt))
+     return false;
+ 
+@@ -188,9 +190,14 @@
+   gimple pattern_stmt;
+   tree prod_type;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+-  struct loop *loop = LOOP_VINFO_LOOP (loop_info);
++  struct loop *loop;
+   tree var, rhs;
+ 
++  if (!loop_info)
++    return NULL;
++
++  loop = LOOP_VINFO_LOOP (loop_info);
++
+   if (!is_gimple_assign (last_stmt))
+     return NULL;
+ 
+@@ -358,8 +365,16 @@
+ {
+   tree new_type, new_oprnd, tmp;
+   gimple new_stmt;
+-  loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
+-  struct loop *loop = LOOP_VINFO_LOOP (loop_info);
++  loop_vec_info loop_vinfo;
++  struct loop *loop = NULL;
++  bb_vec_info bb_vinfo;
++  stmt_vec_info stmt_vinfo;
++
++  stmt_vinfo = vinfo_for_stmt (stmt);
++  loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
++  bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
++  if (loop_vinfo)
++    loop = LOOP_VINFO_LOOP (loop_vinfo);
+ 
+   if (code != MULT_EXPR && code != LSHIFT_EXPR)
+     return false;
+@@ -377,7 +392,9 @@
+ 
+   if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
+       || !gimple_bb (def_stmt)
+-      || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
++      || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
++      || (!loop && gimple_bb (def_stmt) != BB_VINFO_BB (bb_vinfo)
++          && gimple_code (def_stmt) != GIMPLE_PHI)
+       || !vinfo_for_stmt (def_stmt))
+     return false;
+ 
+@@ -774,9 +791,14 @@
+   tree type, half_type;
+   gimple pattern_stmt;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+-  struct loop *loop = LOOP_VINFO_LOOP (loop_info);
++  struct loop *loop;
+   tree var;
+ 
++  if (!loop_info)
++    return NULL;
++
++  loop = LOOP_VINFO_LOOP (loop_info);
++
+   if (!is_gimple_assign (last_stmt))
+     return NULL;
+ 
+@@ -877,7 +899,11 @@
+   gimple def_stmt, new_stmt;
+   bool first = false;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
+-  struct loop *loop = LOOP_VINFO_LOOP (loop_info);
++  bb_vec_info bb_info = STMT_VINFO_BB_VINFO (vinfo_for_stmt (stmt));
++  struct loop *loop = NULL;
++
++  if (loop_info)
++    loop = LOOP_VINFO_LOOP (loop_info);
+ 
+   *new_def_stmt = NULL;
+ 
+@@ -909,7 +935,9 @@
+       first = true;
+       if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
+           || !gimple_bb (def_stmt)
+-          || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
++          || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
++	  || (!loop && gimple_bb (def_stmt) != BB_VINFO_BB (bb_info)
++	      && gimple_code (def_stmt) != GIMPLE_PHI)
+           || !vinfo_for_stmt (def_stmt))
+         return false;
+     }
+@@ -1087,7 +1115,16 @@
+   int nuses = 0;
+   tree var = NULL_TREE, new_type = NULL_TREE, tmp, new_oprnd;
+   bool first;
+-  struct loop *loop = (gimple_bb (stmt))->loop_father;
++  loop_vec_info loop_vinfo;
++  struct loop *loop = NULL;
++  bb_vec_info bb_vinfo;
++  stmt_vec_info stmt_vinfo;
++
++  stmt_vinfo = vinfo_for_stmt (stmt);
++  loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
++  bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
++  if (loop_vinfo)
++    loop = LOOP_VINFO_LOOP (loop_vinfo);
+ 
+   first = true;
+   while (1)
+@@ -1120,7 +1157,8 @@
+ 
+       if (nuses != 1 || !is_gimple_assign (use_stmt)
+           || !gimple_bb (use_stmt)
+-          || !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
++          || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
++	  || (!loop && gimple_bb (use_stmt) != BB_VINFO_BB (bb_vinfo)))
+         return NULL;
+ 
+       /* Create pattern statement for STMT.  */
+@@ -1485,6 +1523,7 @@
+   enum machine_mode cmpmode;
+   gimple pattern_stmt, def_stmt;
+   loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
++  bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
+ 
+   if (!is_gimple_assign (last_stmt)
+       || gimple_assign_rhs_code (last_stmt) != COND_EXPR
+@@ -1538,7 +1577,8 @@
+   tmp = build3 (COND_EXPR, comp_type, unshare_expr (cond_expr),
+ 		fold_convert (comp_type, then_clause),
+ 	       	fold_convert (comp_type, else_clause));
+-  def_stmt = gimple_build_assign (vect_recog_temp_ssa_var (comp_type, NULL), tmp);
++  def_stmt = gimple_build_assign (vect_recog_temp_ssa_var (comp_type, NULL),
++				  tmp);
+ 
+   pattern_stmt
+     = gimple_build_assign_with_ops (NOP_EXPR,
+@@ -1546,12 +1586,15 @@
+ 				    gimple_assign_lhs (def_stmt), NULL_TREE);
+ 
+   STMT_VINFO_PATTERN_DEF_STMT (stmt_vinfo) = def_stmt;
+-  def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
++  def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, bb_vinfo);
+   set_vinfo_for_stmt (def_stmt, def_stmt_info);
+   STMT_VINFO_VECTYPE (def_stmt_info) = comp_vectype;
+   *type_in = vectype;
+   *type_out = vectype;
+ 
++  if (vect_print_dump_info (REPORT_DETAILS))
++    fprintf (vect_dump, "vect_recog_mixed_size_cond_pattern: detected: ");
++
+   return pattern_stmt;
+ }
+ 
+@@ -1565,10 +1608,11 @@
+   stmt_vec_info pattern_stmt_info, def_stmt_info;
+   stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
+   loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (orig_stmt_info);
++  bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (orig_stmt_info);
+   gimple def_stmt;
+ 
+   set_vinfo_for_stmt (pattern_stmt,
+-                      new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
++                      new_stmt_vec_info (pattern_stmt, loop_vinfo, bb_vinfo));
+   gimple_set_bb (pattern_stmt, gimple_bb (orig_stmt));
+   pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
+ 
+@@ -1586,7 +1630,7 @@
+       def_stmt_info = vinfo_for_stmt (def_stmt);
+       if (def_stmt_info == NULL)
+ 	{
+-	  def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
++	  def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, bb_vinfo);
+ 	  set_vinfo_for_stmt (def_stmt, def_stmt_info);
+ 	}
+       gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
+@@ -1697,9 +1741,10 @@
+ 
+   /* Patterns cannot be vectorized using SLP, because they change the order of
+      computation.  */
+-  FOR_EACH_VEC_ELT (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, next)
+-    if (next == stmt)
+-      VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i); 
++  if (loop_vinfo)
++    FOR_EACH_VEC_ELT (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, next)
++      if (next == stmt)
++        VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i);
+ 
+   /* It is possible that additional pattern stmts are created and inserted in
+      STMTS_TO_REPLACE.  We create a stmt_info for each of them, and mark the
+@@ -1799,26 +1844,46 @@
+    be recorded in S3.  */
+ 
+ void
+-vect_pattern_recog (loop_vec_info loop_vinfo)
++vect_pattern_recog (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo)
+ {
+-  struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
+-  basic_block *bbs = LOOP_VINFO_BBS (loop_vinfo);
+-  unsigned int nbbs = loop->num_nodes;
++  struct loop *loop;
++  basic_block *bbs, bb;
++  unsigned int nbbs;
+   gimple_stmt_iterator si;
+   unsigned int i, j;
+   gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+   VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
++  gimple stmt;
+ 
+   if (vect_print_dump_info (REPORT_DETAILS))
+     fprintf (vect_dump, "=== vect_pattern_recog ===");
+ 
+-  /* Scan through the loop stmts, applying the pattern recognition
++  if (loop_vinfo)
++    {
++      loop = LOOP_VINFO_LOOP (loop_vinfo);
++      bbs = LOOP_VINFO_BBS (loop_vinfo);
++      nbbs = loop->num_nodes;
++    }
++  else
++    {
++      bb = BB_VINFO_BB (bb_vinfo);
++      nbbs = 1;
++      bbs = XNEW (basic_block);
++      bbs[0] = bb;
++    }
++
++  /* Scan through the stmts, applying the pattern recognition
+      functions starting at each stmt visited:  */
+   for (i = 0; i < nbbs; i++)
+     {
+       basic_block bb = bbs[i];
+       for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
+         {
++	  if (bb_vinfo && (stmt = gsi_stmt (si))
++	      && vinfo_for_stmt (stmt)
++	      && !STMT_VINFO_VECTORIZABLE (vinfo_for_stmt (stmt)))
++	   continue;
++
+           /* Scan over all generic vect_recog_xxx_pattern functions.  */
+           for (j = 0; j < NUM_PATTERNS; j++)
+             {
+@@ -1830,4 +1895,6 @@
+     }
+ 
+   VEC_free (gimple, heap, stmts_to_replace);
++  if (bb_vinfo)
++    free (bbs);
+ }
+
+=== modified file 'gcc/tree-vect-slp.c'
+--- old/gcc/tree-vect-slp.c	2011-11-21 06:58:40 +0000
++++ new/gcc/tree-vect-slp.c	2011-11-23 06:47:35 +0000
+@@ -255,12 +255,14 @@
+       /* Check if DEF_STMT is a part of a pattern in LOOP and get the def stmt
+          from the pattern.  Check that all the stmts of the node are in the
+          pattern.  */
+-      if (loop && def_stmt && gimple_bb (def_stmt)
+-          && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
++      if (def_stmt && gimple_bb (def_stmt)
++          && ((loop && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
++	      || (!loop && gimple_bb (def_stmt) == BB_VINFO_BB (bb_vinfo)
++		  && gimple_code (def_stmt) != GIMPLE_PHI))
+           && vinfo_for_stmt (def_stmt)
+           && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (def_stmt))
+-          && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
+-          && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
++	  && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
++	  && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
+         {
+           pattern = true;
+           if (!first && !oprnd_info->first_pattern)
+@@ -1972,6 +1974,8 @@
+       return NULL;
+     }
+ 
++   vect_pattern_recog (NULL, bb_vinfo);
++
+    if (!vect_analyze_data_ref_dependences (NULL, bb_vinfo, &max_vf, 
+                                            &data_dependence_in_bb)
+        || min_vf > max_vf
+
+=== modified file 'gcc/tree-vect-stmts.c'
+--- old/gcc/tree-vect-stmts.c	2011-11-22 17:10:17 +0000
++++ new/gcc/tree-vect-stmts.c	2011-11-23 06:47:35 +0000
+@@ -3451,11 +3451,11 @@
+ 	  /* For WIDEN_MULT_EXPR, if OP0 is a constant, use the type of
+ 	     OP1.  */
+           if (CONSTANT_CLASS_P (op0))
+-            ok = vect_is_simple_use_1 (op1, loop_vinfo, NULL,
++            ok = vect_is_simple_use_1 (op1, loop_vinfo, bb_vinfo,
+                              &def_stmt, &def, &dt[1], &vectype_in);
+           else
+-            ok = vect_is_simple_use (op1, loop_vinfo, NULL, &def_stmt, &def,
+-                                     &dt[1]);
++            ok = vect_is_simple_use (op1, loop_vinfo, bb_vinfo, &def_stmt,
++				     &def, &dt[1]);
+ 
+           if (!ok)
+             {
+
+=== modified file 'gcc/tree-vectorizer.h'
+--- old/gcc/tree-vectorizer.h	2011-11-22 17:10:17 +0000
++++ new/gcc/tree-vectorizer.h	2011-11-23 06:47:35 +0000
+@@ -918,7 +918,7 @@
+    in the future.  */
+ typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
+ #define NUM_PATTERNS 7 
+-void vect_pattern_recog (loop_vec_info);
++void vect_pattern_recog (loop_vec_info, bb_vec_info);
+ 
+ /* In tree-vectorizer.c.  */
+ unsigned vectorize_loops (void);
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch
new file mode 100644
index 0000000000..17cfd10682
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch
@@ -0,0 +1,1818 @@
+2011-11-28  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	Backport from mainline (svn r19983):
+
+	2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	gcc/testsuite/
+	* gcc.dg/di-longlong64-sync-1.c: New test.
+	* gcc.dg/di-sync-multithread.c: New test.
+	* gcc.target/arm/di-longlong64-sync-withhelpers.c: New test.
+	* gcc.target/arm/di-longlong64-sync-withldrexd.c: New test.
+	* lib/target-supports.exp: (arm_arch_*_ok): Series of effective-target
+	tests for v5, v6, v6k, and v7-a, and add-options helpers.
+	(check_effective_target_arm_arm_ok): New helper.
+	(check_effective_target_sync_longlong): New helper.
+
+2011-11-28  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	Backport from mainline (svn r19982):
+
+	2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	gcc/
+	* config/arm/linux-atomic-64bit.c: New (based on linux-atomic.c).
+	* config/arm/linux-atomic.c: Change comment to point to 64bit version.
+	(SYNC_LOCK_RELEASE): Instantiate 64bit version.
+	* config/arm/t-linux-eabi: Pull in linux-atomic-64bit.c.
+
+2011-11-28  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	Backport from mainline (svn r19981):
+
+	2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (arm_output_ldrex): Support ldrexd.
+	(arm_output_strex): Support strexd.
+	(arm_output_it): New helper to output it in Thumb2 mode only.
+	(arm_output_sync_loop): Support DI mode.  Change comment to
+	not support const_int.
+	(arm_expand_sync): Support DI mode.
+	* config/arm/arm.h (TARGET_HAVE_LDREXBHD): Split into LDREXBH
+	and LDREXD.
+	* config/arm/iterators.md (NARROW): move from sync.md.
+	(QHSD): New iterator for all current ARM integer modes.
+	(SIDI): New iterator for SI and DI modes only.
+	* config/arm/sync.md (sync_predtab): New mode_attr.
+	(sync_compare_and_swapsi): Fold into sync_compare_and_swap<mode>.
+	(sync_lock_test_and_setsi): Fold into sync_lock_test_and_setsi<mode>.
+	(sync_<sync_optab>si): Fold into sync_<sync_optab><mode>.
+	(sync_nandsi): Fold into sync_nand<mode>.
+	(sync_new_<sync_optab>si): Fold into sync_new_<sync_optab><mode>.
+	(sync_new_nandsi): Fold into sync_new_nand<mode>.
+	(sync_old_<sync_optab>si): Fold into sync_old_<sync_optab><mode>.
+	(sync_old_nandsi): Fold into sync_old_nand<mode>.
+	(sync_compare_and_swap<mode>): Support SI & DI.
+	(sync_lock_test_and_set<mode>): Likewise.
+	(sync_<sync_optab><mode>): Likewise.
+	(sync_nand<mode>): Likewise.
+	(sync_new_<sync_optab><mode>): Likewise.
+	(sync_new_nand<mode>): Likewise.
+	(sync_old_<sync_optab><mode>): Likewise.
+	(sync_old_nand<mode>): Likewise.
+	(arm_sync_compare_and_swapsi): Turn into iterator on SI & DI.
+	(arm_sync_lock_test_and_setsi): Likewise.
+	(arm_sync_new_<sync_optab>si): Likewise.
+	(arm_sync_new_nandsi): Likewise.
+	(arm_sync_old_<sync_optab>si): Likewise.
+	(arm_sync_old_nandsi): Likewise.
+	(arm_sync_compare_and_swap<mode> NARROW): use sync_predtab, fix indent.
+	(arm_sync_lock_test_and_setsi<mode> NARROW): Likewise.
+	(arm_sync_new_<sync_optab><mode> NARROW): Likewise.
+	(arm_sync_new_nand<mode> NARROW): Likewise.
+	(arm_sync_old_<sync_optab><mode> NARROW): Likewise.
+	(arm_sync_old_nand<mode> NARROW): Likewise.
+
+2011-11-28  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	Backport from mainline (svn r19980):
+
+	2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	PR target/48126
+
+	gcc/
+	* config/arm/arm.c (arm_output_sync_loop): Move label before barrier.
+
+2011-11-28  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	Backport from mainline (svn r19979):
+
+	2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>
+
+	gcc/
+	* config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-11-21 01:45:54 +0000
++++ new/gcc/config/arm/arm.c	2011-11-28 15:07:01 +0000
+@@ -24307,12 +24307,26 @@
+ 		  rtx target,
+ 		  rtx memory)
+ {
+-  const char *suffix = arm_ldrex_suffix (mode);
+-  rtx operands[2];
++  rtx operands[3];
+ 
+   operands[0] = target;
+-  operands[1] = memory;
+-  arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
++  if (mode != DImode)
++    {
++      const char *suffix = arm_ldrex_suffix (mode);
++      operands[1] = memory;
++      arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
++    }
++  else
++    {
++      /* The restrictions on target registers in ARM mode are that the two
++	 registers are consecutive and the first one is even; Thumb is
++	 actually more flexible, but DI should give us this anyway.
++	 Note that the 1st register always gets the lowest word in memory.  */
++      gcc_assert ((REGNO (target) & 1) == 0);
++      operands[1] = gen_rtx_REG (SImode, REGNO (target) + 1);
++      operands[2] = memory;
++      arm_output_asm_insn (emit, 0, operands, "ldrexd\t%%0, %%1, %%C2");
++    }
+ }
+ 
+ /* Emit a strex{b,h,d, } instruction appropriate for the specified
+@@ -24325,14 +24339,41 @@
+ 		  rtx value,
+ 		  rtx memory)
+ {
+-  const char *suffix = arm_ldrex_suffix (mode);
+-  rtx operands[3];
++  rtx operands[4];
+ 
+   operands[0] = result;
+   operands[1] = value;
+-  operands[2] = memory;
+-  arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix,
+-		       cc);
++  if (mode != DImode)
++    {
++      const char *suffix = arm_ldrex_suffix (mode);
++      operands[2] = memory;
++      arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2",
++			  suffix, cc);
++    }
++  else
++    {
++      /* The restrictions on target registers in ARM mode are that the two
++	 registers are consecutive and the first one is even; Thumb is
++	 actually more flexible, but DI should give us this anyway.
++	 Note that the 1st register always gets the lowest word in memory.  */
++      gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
++      operands[2] = gen_rtx_REG (SImode, REGNO (value) + 1);
++      operands[3] = memory;
++      arm_output_asm_insn (emit, 0, operands, "strexd%s\t%%0, %%1, %%2, %%C3",
++			   cc);
++    }
++}
++
++/* Helper to emit an it instruction in Thumb2 mode only; although the assembler
++   will ignore it in ARM mode, emitting it will mess up instruction counts we
++   sometimes keep 'flags' are the extra t's and e's if it's more than one
++   instruction that is conditional.  */
++static void
++arm_output_it (emit_f emit, const char *flags, const char *cond)
++{
++  rtx operands[1]; /* Don't actually use the operand.  */
++  if (TARGET_THUMB2)
++    arm_output_asm_insn (emit, 0, operands, "it%s\t%s", flags, cond);
+ }
+ 
+ /* Helper to emit a two operand instruction.  */
+@@ -24374,7 +24415,7 @@
+ 
+    required_value:
+ 
+-   RTX register or const_int representing the required old_value for
++   RTX register representing the required old_value for
+    the modify to continue, if NULL no comparsion is performed.  */
+ static void
+ arm_output_sync_loop (emit_f emit,
+@@ -24388,7 +24429,13 @@
+ 		      enum attr_sync_op sync_op,
+ 		      int early_barrier_required)
+ {
+-  rtx operands[1];
++  rtx operands[2];
++  /* We'll use the lo for the normal rtx in the none-DI case
++     as well as the least-sig word in the DI case.  */
++  rtx old_value_lo, required_value_lo, new_value_lo, t1_lo;
++  rtx old_value_hi, required_value_hi, new_value_hi, t1_hi;
++
++  bool is_di = mode == DImode;
+ 
+   gcc_assert (t1 != t2);
+ 
+@@ -24399,82 +24446,142 @@
+ 
+   arm_output_ldrex (emit, mode, old_value, memory);
+ 
++  if (is_di)
++    {
++      old_value_lo = gen_lowpart (SImode, old_value);
++      old_value_hi = gen_highpart (SImode, old_value);
++      if (required_value)
++	{
++	  required_value_lo = gen_lowpart (SImode, required_value);
++	  required_value_hi = gen_highpart (SImode, required_value);
++	}
++      else
++	{
++	  /* Silence false potentially unused warning.  */
++	  required_value_lo = NULL_RTX;
++	  required_value_hi = NULL_RTX;
++	}
++      new_value_lo = gen_lowpart (SImode, new_value);
++      new_value_hi = gen_highpart (SImode, new_value);
++      t1_lo = gen_lowpart (SImode, t1);
++      t1_hi = gen_highpart (SImode, t1);
++    }
++  else
++    {
++      old_value_lo = old_value;
++      new_value_lo = new_value;
++      required_value_lo = required_value;
++      t1_lo = t1;
++
++      /* Silence false potentially unused warning.  */
++      t1_hi = NULL_RTX;
++      new_value_hi = NULL_RTX;
++      required_value_hi = NULL_RTX;
++      old_value_hi = NULL_RTX;
++    }
++
+   if (required_value)
+     {
+-      rtx operands[2];
++      operands[0] = old_value_lo;
++      operands[1] = required_value_lo;
+ 
+-      operands[0] = old_value;
+-      operands[1] = required_value;
+       arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1");
++      if (is_di)
++        {
++          arm_output_it (emit, "", "eq");
++          arm_output_op2 (emit, "cmpeq", old_value_hi, required_value_hi);
++        }
+       arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX);
+     }
+ 
+   switch (sync_op)
+     {
+     case SYNC_OP_ADD:
+-      arm_output_op3 (emit, "add", t1, old_value, new_value);
++      arm_output_op3 (emit, is_di ? "adds" : "add",
++		      t1_lo, old_value_lo, new_value_lo);
++      if (is_di)
++	arm_output_op3 (emit, "adc", t1_hi, old_value_hi, new_value_hi);
+       break;
+ 
+     case SYNC_OP_SUB:
+-      arm_output_op3 (emit, "sub", t1, old_value, new_value);
++      arm_output_op3 (emit, is_di ? "subs" : "sub",
++		      t1_lo, old_value_lo, new_value_lo);
++      if (is_di)
++	arm_output_op3 (emit, "sbc", t1_hi, old_value_hi, new_value_hi);
+       break;
+ 
+     case SYNC_OP_IOR:
+-      arm_output_op3 (emit, "orr", t1, old_value, new_value);
++      arm_output_op3 (emit, "orr", t1_lo, old_value_lo, new_value_lo);
++      if (is_di)
++	arm_output_op3 (emit, "orr", t1_hi, old_value_hi, new_value_hi);
+       break;
+ 
+     case SYNC_OP_XOR:
+-      arm_output_op3 (emit, "eor", t1, old_value, new_value);
++      arm_output_op3 (emit, "eor", t1_lo, old_value_lo, new_value_lo);
++      if (is_di)
++	arm_output_op3 (emit, "eor", t1_hi, old_value_hi, new_value_hi);
+       break;
+ 
+     case SYNC_OP_AND:
+-      arm_output_op3 (emit,"and", t1, old_value, new_value);
++      arm_output_op3 (emit,"and", t1_lo, old_value_lo, new_value_lo);
++      if (is_di)
++	arm_output_op3 (emit, "and", t1_hi, old_value_hi, new_value_hi);
+       break;
+ 
+     case SYNC_OP_NAND:
+-      arm_output_op3 (emit, "and", t1, old_value, new_value);
+-      arm_output_op2 (emit, "mvn", t1, t1);
++      arm_output_op3 (emit, "and", t1_lo, old_value_lo, new_value_lo);
++      if (is_di)
++	arm_output_op3 (emit, "and", t1_hi, old_value_hi, new_value_hi);
++      arm_output_op2 (emit, "mvn", t1_lo, t1_lo);
++      if (is_di)
++	arm_output_op2 (emit, "mvn", t1_hi, t1_hi);
+       break;
+ 
+     case SYNC_OP_NONE:
+       t1 = new_value;
++      t1_lo = new_value_lo;
++      if (is_di)
++	t1_hi = new_value_hi;
+       break;
+     }
+ 
++  /* Note that the result of strex is a 0/1 flag that's always 1 register.  */
+   if (t2)
+     {
+-       arm_output_strex (emit, mode, "", t2, t1, memory);
+-       operands[0] = t2;
+-       arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
+-       arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
+-			    LOCAL_LABEL_PREFIX);
++      arm_output_strex (emit, mode, "", t2, t1, memory);
++      operands[0] = t2;
++      arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
++      arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
++			   LOCAL_LABEL_PREFIX);
+     }
+   else
+     {
+       /* Use old_value for the return value because for some operations
+ 	 the old_value can easily be restored.  This saves one register.  */
+-      arm_output_strex (emit, mode, "", old_value, t1, memory);
+-      operands[0] = old_value;
++      arm_output_strex (emit, mode, "", old_value_lo, t1, memory);
++      operands[0] = old_value_lo;
+       arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
+       arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
+ 			   LOCAL_LABEL_PREFIX);
+ 
++      /* Note that we only used the _lo half of old_value as a temporary
++	 so in DI we don't have to restore the _hi part.  */
+       switch (sync_op)
+ 	{
+ 	case SYNC_OP_ADD:
+-	  arm_output_op3 (emit, "sub", old_value, t1, new_value);
++	  arm_output_op3 (emit, "sub", old_value_lo, t1_lo, new_value_lo);
+ 	  break;
+ 
+ 	case SYNC_OP_SUB:
+-	  arm_output_op3 (emit, "add", old_value, t1, new_value);
++	  arm_output_op3 (emit, "add", old_value_lo, t1_lo, new_value_lo);
+ 	  break;
+ 
+ 	case SYNC_OP_XOR:
+-	  arm_output_op3 (emit, "eor", old_value, t1, new_value);
++	  arm_output_op3 (emit, "eor", old_value_lo, t1_lo, new_value_lo);
+ 	  break;
+ 
+ 	case SYNC_OP_NONE:
+-	  arm_output_op2 (emit, "mov", old_value, required_value);
++	  arm_output_op2 (emit, "mov", old_value_lo, required_value_lo);
+ 	  break;
+ 
+ 	default:
+@@ -24482,8 +24589,11 @@
+ 	}
+     }
+ 
++  /* Note: label is before barrier so that in cmp failure case we still get
++     a barrier to stop subsequent loads floating upwards past the ldrex
++     PR target/48126.  */
++  arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
+   arm_process_output_memory_barrier (emit, NULL);
+-  arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
+ }
+ 
+ static rtx
+@@ -24577,7 +24687,7 @@
+     target = gen_reg_rtx (mode);
+ 
+   memory = arm_legitimize_sync_memory (memory);
+-  if (mode != SImode)
++  if (mode != SImode && mode != DImode)
+     {
+       rtx load_temp = gen_reg_rtx (SImode);
+ 
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h	2011-11-21 01:45:54 +0000
++++ new/gcc/config/arm/arm.h	2011-11-28 15:07:01 +0000
+@@ -300,7 +300,8 @@
+ #define TARGET_HAVE_DMB		(arm_arch7)
+ 
+ /* Nonzero if this chip implements a memory barrier via CP15.  */
+-#define TARGET_HAVE_DMB_MCR	(arm_arch6k && ! TARGET_HAVE_DMB)
++#define TARGET_HAVE_DMB_MCR	(arm_arch6 && ! TARGET_HAVE_DMB \
++				 && ! TARGET_THUMB1)
+ 
+ /* Nonzero if this chip implements a memory barrier instruction.  */
+ #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
+@@ -308,8 +309,12 @@
+ /* Nonzero if this chip supports ldrex and strex */
+ #define TARGET_HAVE_LDREX	((arm_arch6 && TARGET_ARM) || arm_arch7)
+ 
+-/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}.  */
+-#define TARGET_HAVE_LDREXBHD	((arm_arch6k && TARGET_ARM) || arm_arch7)
++/* Nonzero if this chip supports ldrex{bh} and strex{bh}.  */
++#define TARGET_HAVE_LDREXBH	((arm_arch6k && TARGET_ARM) || arm_arch7)
++
++/* Nonzero if this chip supports ldrexd and strexd.  */
++#define TARGET_HAVE_LDREXD	(((arm_arch6k && TARGET_ARM) || arm_arch7) \
++				 && arm_arch_notm)
+ 
+ /* Nonzero if integer division instructions supported.  */
+ #define TARGET_IDIV		((TARGET_ARM && arm_arch_arm_hwdiv) \
+
+=== modified file 'gcc/config/arm/iterators.md'
+--- old/gcc/config/arm/iterators.md	2011-10-23 13:33:07 +0000
++++ new/gcc/config/arm/iterators.md	2011-11-28 15:07:01 +0000
+@@ -33,6 +33,15 @@
+ ;; A list of integer modes that are up to one word long
+ (define_mode_iterator QHSI [QI HI SI])
+ 
++;; A list of integer modes that are less than a word
++(define_mode_iterator NARROW [QI HI])
++
++;; A list of all the integer modes upto 64bit
++(define_mode_iterator QHSD [QI HI SI DI])
++
++;; A list of the 32bit and 64bit integer modes
++(define_mode_iterator SIDI [SI DI])
++
+ ;; Integer element sizes implemented by IWMMXT.
+ (define_mode_iterator VMMX [V2SI V4HI V8QI])
+ 
+
+=== added file 'gcc/config/arm/linux-atomic-64bit.c'
+--- old/gcc/config/arm/linux-atomic-64bit.c	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/linux-atomic-64bit.c	2011-10-14 15:50:44 +0000
+@@ -0,0 +1,166 @@
++/* 64bit Linux-specific atomic operations for ARM EABI.
++   Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
++   Based on linux-atomic.c
++
++   64 bit additions david.gilbert@linaro.org
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++Under Section 7 of GPL version 3, you are granted additional
++permissions described in the GCC Runtime Library Exception, version
++3.1, as published by the Free Software Foundation.
++
++You should have received a copy of the GNU General Public License and
++a copy of the GCC Runtime Library Exception along with this program;
++see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++<http://www.gnu.org/licenses/>.  */
++
++/* 64bit helper functions for atomic operations; the compiler will
++   call these when the code is compiled for a CPU without ldrexd/strexd.
++   (If the CPU had those then the compiler inlines the operation).
++
++   These helpers require a kernel helper that's only present on newer
++   kernels; we check for that in an init section and bail out rather
++   unceremoneously.  */
++
++extern unsigned int __write (int fd, const void *buf, unsigned int count);
++extern void abort (void);
++
++/* Kernel helper for compare-and-exchange.  */
++typedef int (__kernel_cmpxchg64_t) (const long long* oldval,
++					const long long* newval,
++					long long *ptr);
++#define __kernel_cmpxchg64 (*(__kernel_cmpxchg64_t *) 0xffff0f60)
++
++/* Kernel helper page version number.  */
++#define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
++
++/* Check that the kernel has a new enough version at load.  */
++static void __check_for_sync8_kernelhelper (void)
++{
++  if (__kernel_helper_version < 5)
++    {
++      const char err[] = "A newer kernel is required to run this binary. "
++				"(__kernel_cmpxchg64 helper)\n";
++      /* At this point we need a way to crash with some information
++	 for the user - I'm not sure I can rely on much else being
++	 available at this point, so do the same as generic-morestack.c
++	 write () and abort ().  */
++      __write (2 /* stderr.  */, err, sizeof (err));
++      abort ();
++    }
++};
++
++static void (*__sync8_kernelhelper_inithook[]) (void)
++		__attribute__ ((used, section (".init_array"))) = {
++  &__check_for_sync8_kernelhelper
++};
++
++#define HIDDEN __attribute__ ((visibility ("hidden")))
++
++#define FETCH_AND_OP_WORD64(OP, PFX_OP, INF_OP)			\
++  long long HIDDEN						\
++  __sync_fetch_and_##OP##_8 (long long *ptr, long long val)	\
++  {								\
++    int failure;						\
++    long long tmp,tmp2;						\
++								\
++    do {							\
++      tmp = *ptr;						\
++      tmp2 = PFX_OP (tmp INF_OP val);				\
++      failure = __kernel_cmpxchg64 (&tmp, &tmp2, ptr);		\
++    } while (failure != 0);					\
++								\
++    return tmp;							\
++  }
++
++FETCH_AND_OP_WORD64 (add,   , +)
++FETCH_AND_OP_WORD64 (sub,   , -)
++FETCH_AND_OP_WORD64 (or,    , |)
++FETCH_AND_OP_WORD64 (and,   , &)
++FETCH_AND_OP_WORD64 (xor,   , ^)
++FETCH_AND_OP_WORD64 (nand, ~, &)
++
++#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH
++#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH
++
++/* Implement both __sync_<op>_and_fetch and __sync_fetch_and_<op> for
++   subword-sized quantities.  */
++
++#define OP_AND_FETCH_WORD64(OP, PFX_OP, INF_OP)			\
++  long long HIDDEN						\
++  __sync_##OP##_and_fetch_8 (long long *ptr, long long val)	\
++  {								\
++    int failure;						\
++    long long tmp,tmp2;						\
++								\
++    do {							\
++      tmp = *ptr;						\
++      tmp2 = PFX_OP (tmp INF_OP val);				\
++      failure = __kernel_cmpxchg64 (&tmp, &tmp2, ptr);		\
++    } while (failure != 0);					\
++								\
++    return tmp2;						\
++  }
++
++OP_AND_FETCH_WORD64 (add,   , +)
++OP_AND_FETCH_WORD64 (sub,   , -)
++OP_AND_FETCH_WORD64 (or,    , |)
++OP_AND_FETCH_WORD64 (and,   , &)
++OP_AND_FETCH_WORD64 (xor,   , ^)
++OP_AND_FETCH_WORD64 (nand, ~, &)
++
++long long HIDDEN
++__sync_val_compare_and_swap_8 (long long *ptr, long long oldval,
++				long long newval)
++{
++  int failure;
++  long long actual_oldval;
++
++  while (1)
++    {
++      actual_oldval = *ptr;
++
++      if (__builtin_expect (oldval != actual_oldval, 0))
++	return actual_oldval;
++
++      failure = __kernel_cmpxchg64 (&actual_oldval, &newval, ptr);
++
++      if (__builtin_expect (!failure, 1))
++	return oldval;
++    }
++}
++
++typedef unsigned char bool;
++
++bool HIDDEN
++__sync_bool_compare_and_swap_8 (long long *ptr, long long oldval,
++				 long long newval)
++{
++  int failure = __kernel_cmpxchg64 (&oldval, &newval, ptr);
++  return (failure == 0);
++}
++
++long long HIDDEN
++__sync_lock_test_and_set_8 (long long *ptr, long long val)
++{
++  int failure;
++  long long oldval;
++
++  do {
++    oldval = *ptr;
++    failure = __kernel_cmpxchg64 (&oldval, &val, ptr);
++  } while (failure != 0);
++
++  return oldval;
++}
+
+=== modified file 'gcc/config/arm/linux-atomic.c'
+--- old/gcc/config/arm/linux-atomic.c	2011-01-03 20:52:22 +0000
++++ new/gcc/config/arm/linux-atomic.c	2011-10-14 15:50:44 +0000
+@@ -32,8 +32,8 @@
+ #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
+ 
+ /* Note: we implement byte, short and int versions of atomic operations using
+-   the above kernel helpers, but there is no support for "long long" (64-bit)
+-   operations as yet.  */
++   the above kernel helpers; see linux-atomic-64bit.c for "long long" (64-bit)
++   operations.  */
+ 
+ #define HIDDEN __attribute__ ((visibility ("hidden")))
+ 
+@@ -273,6 +273,7 @@
+     *ptr = 0;								\
+   }
+ 
++SYNC_LOCK_RELEASE (long long,   8)
+ SYNC_LOCK_RELEASE (int,   4)
+ SYNC_LOCK_RELEASE (short, 2)
+ SYNC_LOCK_RELEASE (char,  1)
+
+=== modified file 'gcc/config/arm/sync.md'
+--- old/gcc/config/arm/sync.md	2010-12-31 13:25:33 +0000
++++ new/gcc/config/arm/sync.md	2011-10-14 15:47:15 +0000
+@@ -1,6 +1,7 @@
+ ;; Machine description for ARM processor synchronization primitives.
+ ;; Copyright (C) 2010 Free Software Foundation, Inc.
+ ;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com)
++;; 64bit Atomics by Dave Gilbert (david.gilbert@linaro.org)
+ ;;
+ ;; This file is part of GCC.
+ ;;
+@@ -33,31 +34,24 @@
+   MEM_VOLATILE_P (operands[0]) = 1;
+ })
+ 
+-(define_expand "sync_compare_and_swapsi"
+-  [(set (match_operand:SI 0 "s_register_operand")
+-        (unspec_volatile:SI [(match_operand:SI 1 "memory_operand")
+-			     (match_operand:SI 2 "s_register_operand")
+-			     (match_operand:SI 3 "s_register_operand")]
+-			     VUNSPEC_SYNC_COMPARE_AND_SWAP))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omrn;
+-    generator.u.omrn = gen_arm_sync_compare_and_swapsi;
+-    arm_expand_sync (SImode, &generator, operands[0], operands[1], operands[2],
+-                     operands[3]);
+-    DONE;
+-  })
+ 
+-(define_mode_iterator NARROW [QI HI])
++(define_mode_attr sync_predtab [(SI "TARGET_HAVE_LDREX &&
++					TARGET_HAVE_MEMORY_BARRIER")
++				(QI "TARGET_HAVE_LDREXBH &&
++					TARGET_HAVE_MEMORY_BARRIER")
++				(HI "TARGET_HAVE_LDREXBH &&
++					TARGET_HAVE_MEMORY_BARRIER")
++				(DI "TARGET_HAVE_LDREXD &&
++					ARM_DOUBLEWORD_ALIGN &&
++					TARGET_HAVE_MEMORY_BARRIER")])
+ 
+ (define_expand "sync_compare_and_swap<mode>"
+-  [(set (match_operand:NARROW 0 "s_register_operand")
+-        (unspec_volatile:NARROW [(match_operand:NARROW 1 "memory_operand")
+-			     (match_operand:NARROW 2 "s_register_operand")
+-			     (match_operand:NARROW 3 "s_register_operand")]
++  [(set (match_operand:QHSD 0 "s_register_operand")
++        (unspec_volatile:QHSD [(match_operand:QHSD 1 "memory_operand")
++			     (match_operand:QHSD 2 "s_register_operand")
++			     (match_operand:QHSD 3 "s_register_operand")]
+ 			     VUNSPEC_SYNC_COMPARE_AND_SWAP))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omrn;
+@@ -67,25 +61,11 @@
+     DONE;
+   })
+ 
+-(define_expand "sync_lock_test_and_setsi"
+-  [(match_operand:SI 0 "s_register_operand")
+-   (match_operand:SI 1 "memory_operand")
+-   (match_operand:SI 2 "s_register_operand")]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_lock_test_and_setsi;
+-    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
+-                     operands[2]);
+-    DONE;
+-  })
+-
+ (define_expand "sync_lock_test_and_set<mode>"
+-  [(match_operand:NARROW 0 "s_register_operand")
+-   (match_operand:NARROW 1 "memory_operand")
+-   (match_operand:NARROW 2 "s_register_operand")]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "s_register_operand")
++   (match_operand:QHSD 1 "memory_operand")
++   (match_operand:QHSD 2 "s_register_operand")]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+@@ -115,51 +95,25 @@
+ 				(plus "*")
+ 				(minus "*")])
+ 
+-(define_expand "sync_<sync_optab>si"
+-  [(match_operand:SI 0 "memory_operand")
+-   (match_operand:SI 1 "s_register_operand")
+-   (syncop:SI (match_dup 0) (match_dup 1))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_new_<sync_optab>si;
+-    arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]);
+-    DONE;
+-  })
+-
+-(define_expand "sync_nandsi"
+-  [(match_operand:SI 0 "memory_operand")
+-   (match_operand:SI 1 "s_register_operand")
+-   (not:SI (and:SI (match_dup 0) (match_dup 1)))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_new_nandsi;
+-    arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]);
+-    DONE;
+-  })
+-
+ (define_expand "sync_<sync_optab><mode>"
+-  [(match_operand:NARROW 0 "memory_operand")
+-   (match_operand:NARROW 1 "s_register_operand")
+-   (syncop:NARROW (match_dup 0) (match_dup 1))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "memory_operand")
++   (match_operand:QHSD 1 "s_register_operand")
++   (syncop:QHSD (match_dup 0) (match_dup 1))]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+     generator.u.omn = gen_arm_sync_new_<sync_optab><mode>;
+     arm_expand_sync (<MODE>mode, &generator, NULL, operands[0], NULL,
+-    		     operands[1]);
++		     operands[1]);
+     DONE;
+   })
+ 
+ (define_expand "sync_nand<mode>"
+-  [(match_operand:NARROW 0 "memory_operand")
+-   (match_operand:NARROW 1 "s_register_operand")
+-   (not:NARROW (and:NARROW (match_dup 0) (match_dup 1)))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "memory_operand")
++   (match_operand:QHSD 1 "s_register_operand")
++   (not:QHSD (and:QHSD (match_dup 0) (match_dup 1)))]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+@@ -169,57 +123,27 @@
+     DONE;
+   })
+ 
+-(define_expand "sync_new_<sync_optab>si"
+-  [(match_operand:SI 0 "s_register_operand")
+-   (match_operand:SI 1 "memory_operand")
+-   (match_operand:SI 2 "s_register_operand")
+-   (syncop:SI (match_dup 1) (match_dup 2))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_new_<sync_optab>si;
+-    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
+-                     operands[2]);
+-    DONE;
+-  })
+-
+-(define_expand "sync_new_nandsi"
+-  [(match_operand:SI 0 "s_register_operand")
+-   (match_operand:SI 1 "memory_operand")
+-   (match_operand:SI 2 "s_register_operand")
+-   (not:SI (and:SI (match_dup 1) (match_dup 2)))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_new_nandsi;
+-    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
+-    		     operands[2]);
+-    DONE;
+-  })
+-
+ (define_expand "sync_new_<sync_optab><mode>"
+-  [(match_operand:NARROW 0 "s_register_operand")
+-   (match_operand:NARROW 1 "memory_operand")
+-   (match_operand:NARROW 2 "s_register_operand")
+-   (syncop:NARROW (match_dup 1) (match_dup 2))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "s_register_operand")
++   (match_operand:QHSD 1 "memory_operand")
++   (match_operand:QHSD 2 "s_register_operand")
++   (syncop:QHSD (match_dup 1) (match_dup 2))]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+     generator.u.omn = gen_arm_sync_new_<sync_optab><mode>;
+     arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
+-    		     NULL, operands[2]);
++		     NULL, operands[2]);
+     DONE;
+   })
+ 
+ (define_expand "sync_new_nand<mode>"
+-  [(match_operand:NARROW 0 "s_register_operand")
+-   (match_operand:NARROW 1 "memory_operand")
+-   (match_operand:NARROW 2 "s_register_operand")
+-   (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "s_register_operand")
++   (match_operand:QHSD 1 "memory_operand")
++   (match_operand:QHSD 2 "s_register_operand")
++   (not:QHSD (and:QHSD (match_dup 1) (match_dup 2)))]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+@@ -229,57 +153,27 @@
+     DONE;
+   });
+ 
+-(define_expand "sync_old_<sync_optab>si"
+-  [(match_operand:SI 0 "s_register_operand")
+-   (match_operand:SI 1 "memory_operand")
+-   (match_operand:SI 2 "s_register_operand")
+-   (syncop:SI (match_dup 1) (match_dup 2))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_old_<sync_optab>si;
+-    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
+-                     operands[2]);
+-    DONE;
+-  })
+-
+-(define_expand "sync_old_nandsi"
+-  [(match_operand:SI 0 "s_register_operand")
+-   (match_operand:SI 1 "memory_operand")
+-   (match_operand:SI 2 "s_register_operand")
+-   (not:SI (and:SI (match_dup 1) (match_dup 2)))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    struct arm_sync_generator generator;
+-    generator.op = arm_sync_generator_omn;
+-    generator.u.omn = gen_arm_sync_old_nandsi;
+-    arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
+-                     operands[2]);
+-    DONE;
+-  })
+-
+ (define_expand "sync_old_<sync_optab><mode>"
+-  [(match_operand:NARROW 0 "s_register_operand")
+-   (match_operand:NARROW 1 "memory_operand")
+-   (match_operand:NARROW 2 "s_register_operand")
+-   (syncop:NARROW (match_dup 1) (match_dup 2))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "s_register_operand")
++   (match_operand:QHSD 1 "memory_operand")
++   (match_operand:QHSD 2 "s_register_operand")
++   (syncop:QHSD (match_dup 1) (match_dup 2))]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+     generator.u.omn = gen_arm_sync_old_<sync_optab><mode>;
+     arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
+-    		     NULL, operands[2]);
++		     NULL, operands[2]);
+     DONE;
+   })
+ 
+ (define_expand "sync_old_nand<mode>"
+-  [(match_operand:NARROW 0 "s_register_operand")
+-   (match_operand:NARROW 1 "memory_operand")
+-   (match_operand:NARROW 2 "s_register_operand")
+-   (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  [(match_operand:QHSD 0 "s_register_operand")
++   (match_operand:QHSD 1 "memory_operand")
++   (match_operand:QHSD 2 "s_register_operand")
++   (not:QHSD (and:QHSD (match_dup 1) (match_dup 2)))]
++  "<sync_predtab>"
+   {
+     struct arm_sync_generator generator;
+     generator.op = arm_sync_generator_omn;
+@@ -289,22 +183,22 @@
+     DONE;
+   })
+ 
+-(define_insn "arm_sync_compare_and_swapsi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (unspec_volatile:SI
+-	  [(match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+-   	   (match_operand:SI 2 "s_register_operand" "r")
+-	   (match_operand:SI 3 "s_register_operand" "r")]
+-	  VUNSPEC_SYNC_COMPARE_AND_SWAP))
+-   (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)]
++(define_insn "arm_sync_compare_and_swap<mode>"
++  [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SIDI
++	 [(match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
++	  (match_operand:SIDI 2 "s_register_operand" "r")
++	  (match_operand:SIDI 3 "s_register_operand" "r")]
++	 VUNSPEC_SYNC_COMPARE_AND_SWAP))
++   (set (match_dup 1) (unspec_volatile:SIDI [(match_dup 2)]
+                                           VUNSPEC_SYNC_COMPARE_AND_SWAP))
+    (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
+                                                 VUNSPEC_SYNC_COMPARE_AND_SWAP))
+    ]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+-  } 
++  }
+   [(set_attr "sync_result"          "0")
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_required_value"  "2")
+@@ -318,7 +212,7 @@
+         (zero_extend:SI
+ 	  (unspec_volatile:NARROW
+ 	    [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")
+-   	     (match_operand:SI 2 "s_register_operand" "r")
++	     (match_operand:SI 2 "s_register_operand" "r")
+ 	     (match_operand:SI 3 "s_register_operand" "r")]
+ 	    VUNSPEC_SYNC_COMPARE_AND_SWAP)))
+    (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)]
+@@ -326,10 +220,10 @@
+    (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
+                                                 VUNSPEC_SYNC_COMPARE_AND_SWAP))
+    ]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+-  } 
++  }
+   [(set_attr "sync_result"          "0")
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_required_value"  "2")
+@@ -338,18 +232,18 @@
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+-(define_insn "arm_sync_lock_test_and_setsi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (match_operand:SI 1 "arm_sync_memory_operand" "+Q"))
++(define_insn "arm_sync_lock_test_and_set<mode>"
++  [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
++	(match_operand:SIDI 1 "arm_sync_memory_operand" "+Q"))
+    (set (match_dup 1)
+-        (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")]
+-	                    VUNSPEC_SYNC_LOCK))
++	(unspec_volatile:SIDI [(match_operand:SIDI 2 "s_register_operand" "r")]
++	VUNSPEC_SYNC_LOCK))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+-  } 
++  }
+   [(set_attr "sync_release_barrier" "no")
+    (set_attr "sync_result"          "0")
+    (set_attr "sync_memory"          "1")
+@@ -364,10 +258,10 @@
+         (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")))
+    (set (match_dup 1)
+         (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")]
+-	                        VUNSPEC_SYNC_LOCK))
++				VUNSPEC_SYNC_LOCK))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+   } 
+@@ -380,22 +274,48 @@
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+-(define_insn "arm_sync_new_<sync_optab>si"
++(define_insn "arm_sync_new_<sync_optab><mode>"
++  [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SIDI [(syncop:SIDI
++			       (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
++			       (match_operand:SIDI 2 "s_register_operand" "r"))
++			    ]
++			    VUNSPEC_SYNC_NEW_OP))
++   (set (match_dup 1)
++	(unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
++			    VUNSPEC_SYNC_NEW_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SI 3 "=&r"))]
++  "<sync_predtab>"
++  {
++    return arm_output_sync_insn (insn, operands);
++  }
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "0")
++   (set_attr "sync_t2"              "3")
++   (set_attr "sync_op"              "<sync_optab>")
++   (set_attr "conds" "clob")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_new_<sync_optab><mode>"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(syncop:SI
+-                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+-                               (match_operand:SI 2 "s_register_operand" "r"))
+-	                    ]
+-	                    VUNSPEC_SYNC_NEW_OP))
++			       (zero_extend:SI
++				 (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
++			       (match_operand:SI 2 "s_register_operand" "r"))
++			    ]
++			    VUNSPEC_SYNC_NEW_OP))
+    (set (match_dup 1)
+-        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
+-	                    VUNSPEC_SYNC_NEW_OP))
++	(unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++				VUNSPEC_SYNC_NEW_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+-  } 
++  }
+   [(set_attr "sync_result"          "0")
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_new_value"       "2")
+@@ -405,22 +325,22 @@
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+-(define_insn "arm_sync_new_nandsi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (unspec_volatile:SI [(not:SI (and:SI
+-                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+-                               (match_operand:SI 2 "s_register_operand" "r")))
+-	                    ]
+-	                    VUNSPEC_SYNC_NEW_OP))
++(define_insn "arm_sync_new_nand<mode>"
++  [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
++        (unspec_volatile:SIDI [(not:SIDI (and:SIDI
++			       (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
++			       (match_operand:SIDI 2 "s_register_operand" "r")))
++			    ]
++			    VUNSPEC_SYNC_NEW_OP))
+    (set (match_dup 1)
+-        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
+-	                    VUNSPEC_SYNC_NEW_OP))
++	(unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
++			    VUNSPEC_SYNC_NEW_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+-  } 
++  }
+   [(set_attr "sync_result"          "0")
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_new_value"       "2")
+@@ -430,50 +350,24 @@
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+-(define_insn "arm_sync_new_<sync_optab><mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (unspec_volatile:SI [(syncop:SI
+-                               (zero_extend:SI
+-			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+-                               (match_operand:SI 2 "s_register_operand" "r"))
+-	                    ]
+-	                    VUNSPEC_SYNC_NEW_OP))
+-   (set (match_dup 1)
+-        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
+-	                        VUNSPEC_SYNC_NEW_OP))
+-   (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 3 "=&r"))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    return arm_output_sync_insn (insn, operands);
+-  } 
+-  [(set_attr "sync_result"          "0")
+-   (set_attr "sync_memory"          "1")
+-   (set_attr "sync_new_value"       "2")
+-   (set_attr "sync_t1"              "0")
+-   (set_attr "sync_t2"              "3")
+-   (set_attr "sync_op"              "<sync_optab>")
+-   (set_attr "conds" "clob")
+-   (set_attr "predicable" "no")])
+-
+ (define_insn "arm_sync_new_nand<mode>"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI
+ 	  [(not:SI
+ 	     (and:SI
+-               (zero_extend:SI	  
+-	         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+-               (match_operand:SI 2 "s_register_operand" "r")))
++	       (zero_extend:SI
++		 (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
++	       (match_operand:SI 2 "s_register_operand" "r")))
+ 	  ] VUNSPEC_SYNC_NEW_OP))
+    (set (match_dup 1)
+         (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
+-	                        VUNSPEC_SYNC_NEW_OP))
++				VUNSPEC_SYNC_NEW_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+-  } 
++  }
+   [(set_attr "sync_result"          "0")
+    (set_attr "sync_memory"          "1")
+    (set_attr "sync_new_value"       "2")
+@@ -483,20 +377,20 @@
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+-(define_insn "arm_sync_old_<sync_optab>si"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (unspec_volatile:SI [(syncop:SI
+-                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+-                               (match_operand:SI 2 "s_register_operand" "r"))
+-	                    ]
+-	                    VUNSPEC_SYNC_OLD_OP))
++(define_insn "arm_sync_old_<sync_optab><mode>"
++  [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
++	(unspec_volatile:SIDI [(syncop:SIDI
++			       (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
++			       (match_operand:SIDI 2 "s_register_operand" "r"))
++			    ]
++			    VUNSPEC_SYNC_OLD_OP))
+    (set (match_dup 1)
+-        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
+-	                    VUNSPEC_SYNC_OLD_OP))
++        (unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
++			      VUNSPEC_SYNC_OLD_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 3 "=&r"))
++   (clobber (match_scratch:SIDI 3 "=&r"))
+    (clobber (match_scratch:SI 4 "<sync_clobber>"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+   } 
+@@ -509,47 +403,21 @@
+    (set_attr "conds" "clob")
+    (set_attr "predicable" "no")])
+ 
+-(define_insn "arm_sync_old_nandsi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (unspec_volatile:SI [(not:SI (and:SI
+-                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
+-                               (match_operand:SI 2 "s_register_operand" "r")))
+-	                    ]
+-	                    VUNSPEC_SYNC_OLD_OP))
+-   (set (match_dup 1)
+-        (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
+-	                    VUNSPEC_SYNC_OLD_OP))
+-   (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
+-  "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
+-  {
+-    return arm_output_sync_insn (insn, operands);
+-  } 
+-  [(set_attr "sync_result"          "0")
+-   (set_attr "sync_memory"          "1")
+-   (set_attr "sync_new_value"       "2")
+-   (set_attr "sync_t1"              "3")
+-   (set_attr "sync_t2"              "4")
+-   (set_attr "sync_op"              "nand")
+-   (set_attr "conds" 		    "clob")
+-   (set_attr "predicable" "no")])
+-
+ (define_insn "arm_sync_old_<sync_optab><mode>"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+         (unspec_volatile:SI [(syncop:SI
+-                               (zero_extend:SI
+-			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+-                               (match_operand:SI 2 "s_register_operand" "r"))
+-	                    ]
+-	                    VUNSPEC_SYNC_OLD_OP))
++			       (zero_extend:SI
++				 (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
++			       (match_operand:SI 2 "s_register_operand" "r"))
++			    ]
++			    VUNSPEC_SYNC_OLD_OP))
+    (set (match_dup 1)
+-        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
+-	                    VUNSPEC_SYNC_OLD_OP))
++	(unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++			    VUNSPEC_SYNC_OLD_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))
+    (clobber (match_scratch:SI 4 "<sync_clobber>"))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+   } 
+@@ -563,20 +431,46 @@
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "arm_sync_old_nand<mode>"
++  [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
++	(unspec_volatile:SIDI [(not:SIDI (and:SIDI
++			       (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
++			       (match_operand:SIDI 2 "s_register_operand" "r")))
++			    ]
++			    VUNSPEC_SYNC_OLD_OP))
++   (set (match_dup 1)
++        (unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
++	                    VUNSPEC_SYNC_OLD_OP))
++   (clobber (reg:CC CC_REGNUM))
++   (clobber (match_scratch:SIDI 3 "=&r"))
++   (clobber (match_scratch:SI 4 "=&r"))]
++  "<sync_predtab>"
++  {
++    return arm_output_sync_insn (insn, operands);
++  } 
++  [(set_attr "sync_result"          "0")
++   (set_attr "sync_memory"          "1")
++   (set_attr "sync_new_value"       "2")
++   (set_attr "sync_t1"              "3")
++   (set_attr "sync_t2"              "4")
++   (set_attr "sync_op"              "nand")
++   (set_attr "conds" 		    "clob")
++   (set_attr "predicable" "no")])
++
++(define_insn "arm_sync_old_nand<mode>"
+   [(set (match_operand:SI 0 "s_register_operand" "=&r")
+-        (unspec_volatile:SI [(not:SI (and:SI
+-                               (zero_extend:SI
+-			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
+-                               (match_operand:SI 2 "s_register_operand" "r")))
+-	                    ]
+-	                    VUNSPEC_SYNC_OLD_OP))
++	(unspec_volatile:SI [(not:SI (and:SI
++			       (zero_extend:SI
++				 (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
++			       (match_operand:SI 2 "s_register_operand" "r")))
++			    ]
++			    VUNSPEC_SYNC_OLD_OP))
+    (set (match_dup 1)
+-        (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
+-	                    VUNSPEC_SYNC_OLD_OP))
++	(unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
++			    VUNSPEC_SYNC_OLD_OP))
+    (clobber (reg:CC CC_REGNUM))
+    (clobber (match_scratch:SI 3 "=&r"))
+    (clobber (match_scratch:SI 4 "=&r"))]
+-  "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
++  "<sync_predtab>"
+   {
+     return arm_output_sync_insn (insn, operands);
+   } 
+
+=== modified file 'gcc/config/arm/t-linux-eabi'
+--- old/gcc/config/arm/t-linux-eabi	2011-01-03 20:52:22 +0000
++++ new/gcc/config/arm/t-linux-eabi	2011-10-14 15:50:44 +0000
+@@ -36,3 +36,4 @@
+ EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
+ 
+ LIB2FUNCS_STATIC_EXTRA += $(srcdir)/config/arm/linux-atomic.c
++LIB2FUNCS_STATIC_EXTRA += $(srcdir)/config/arm/linux-atomic-64bit.c
+
+=== added file 'gcc/testsuite/gcc.dg/di-longlong64-sync-1.c'
+--- old/gcc/testsuite/gcc.dg/di-longlong64-sync-1.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/di-longlong64-sync-1.c	2011-10-14 15:56:32 +0000
+@@ -0,0 +1,164 @@
++/* { dg-do run } */
++/* { dg-require-effective-target sync_longlong } */
++/* { dg-options "-std=gnu99" } */
++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
++/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
++
++
++/* Test basic functionality of the intrinsics.  The operations should
++   not be optimized away if no one checks the return values.  */
++
++/* Based on ia64-sync-[12].c, but 1) long on ARM is 32 bit so use long long
++   (an explicit 64bit type maybe a better bet) and 2) Use values that cross
++   the 32bit boundary and cause carries since the actual maths are done as
++   pairs of 32 bit instructions.  */
++
++/* Note: This file is #included by some of the ARM tests.  */
++
++__extension__ typedef __SIZE_TYPE__ size_t;
++
++extern void abort (void);
++extern void *memcpy (void *, const void *, size_t);
++extern int memcmp (const void *, const void *, size_t);
++
++/* Temporary space where the work actually gets done.  */
++static long long AL[24];
++/* Values copied into AL before we start.  */
++static long long init_di[24] = { 0x100000002ll, 0x200000003ll, 0, 1,
++
++				 0x100000002ll, 0x100000002ll,
++				 0x100000002ll, 0x100000002ll,
++
++				 0, 0x1000e0de0000ll,
++				 42 , 0xc001c0de0000ll,
++
++				 -1ll, 0, 0xff00ff0000ll, -1ll,
++
++				 0, 0x1000e0de0000ll,
++				 42 , 0xc001c0de0000ll,
++
++				 -1ll, 0, 0xff00ff0000ll, -1ll};
++/* This is what should be in AL at the end.  */
++static long long test_di[24] = { 0x1234567890ll, 0x1234567890ll, 1, 0,
++
++				 0x100000002ll, 0x100000002ll,
++				 0x100000002ll, 0x100000002ll,
++
++				 1, 0xc001c0de0000ll,
++				 20, 0x1000e0de0000ll,
++
++				 0x300000007ll , 0x500000009ll,
++				 0xf100ff0001ll, ~0xa00000007ll,
++
++				 1, 0xc001c0de0000ll,
++				 20, 0x1000e0de0000ll,
++
++				 0x300000007ll , 0x500000009ll,
++				 0xf100ff0001ll, ~0xa00000007ll };
++
++/* First check they work in terms of what they do to memory.  */
++static void
++do_noret_di (void)
++{
++  __sync_val_compare_and_swap (AL+0, 0x100000002ll, 0x1234567890ll);
++  __sync_bool_compare_and_swap (AL+1, 0x200000003ll, 0x1234567890ll);
++  __sync_lock_test_and_set (AL+2, 1);
++  __sync_lock_release (AL+3);
++
++  /* The following tests should not change the value since the
++     original does NOT match.  */
++  __sync_val_compare_and_swap (AL+4, 0x000000002ll, 0x1234567890ll);
++  __sync_val_compare_and_swap (AL+5, 0x100000000ll, 0x1234567890ll);
++  __sync_bool_compare_and_swap (AL+6, 0x000000002ll, 0x1234567890ll);
++  __sync_bool_compare_and_swap (AL+7, 0x100000000ll, 0x1234567890ll);
++
++  __sync_fetch_and_add (AL+8, 1);
++  __sync_fetch_and_add (AL+9, 0xb000e0000000ll); /* + to both halves & carry.  */
++  __sync_fetch_and_sub (AL+10, 22);
++  __sync_fetch_and_sub (AL+11, 0xb000e0000000ll);
++
++  __sync_fetch_and_and (AL+12, 0x300000007ll);
++  __sync_fetch_and_or (AL+13, 0x500000009ll);
++  __sync_fetch_and_xor (AL+14, 0xe00000001ll);
++  __sync_fetch_and_nand (AL+15, 0xa00000007ll);
++
++  /* These should be the same as the fetch_and_* cases except for
++     return value.  */
++  __sync_add_and_fetch (AL+16, 1);
++  /* add to both halves & carry.  */
++  __sync_add_and_fetch (AL+17, 0xb000e0000000ll);
++  __sync_sub_and_fetch (AL+18, 22);
++  __sync_sub_and_fetch (AL+19, 0xb000e0000000ll);
++
++  __sync_and_and_fetch (AL+20, 0x300000007ll);
++  __sync_or_and_fetch (AL+21, 0x500000009ll);
++  __sync_xor_and_fetch (AL+22, 0xe00000001ll);
++  __sync_nand_and_fetch (AL+23, 0xa00000007ll);
++}
++
++/* Now check return values.  */
++static void
++do_ret_di (void)
++{
++  if (__sync_val_compare_and_swap (AL+0, 0x100000002ll, 0x1234567890ll) !=
++	0x100000002ll) abort ();
++  if (__sync_bool_compare_and_swap (AL+1, 0x200000003ll, 0x1234567890ll) !=
++	1) abort ();
++  if (__sync_lock_test_and_set (AL+2, 1) != 0) abort ();
++  __sync_lock_release (AL+3); /* no return value, but keep to match results.  */
++
++  /* The following tests should not change the value since the
++     original does NOT match.  */
++  if (__sync_val_compare_and_swap (AL+4, 0x000000002ll, 0x1234567890ll) !=
++	0x100000002ll) abort ();
++  if (__sync_val_compare_and_swap (AL+5, 0x100000000ll, 0x1234567890ll) !=
++	0x100000002ll) abort ();
++  if (__sync_bool_compare_and_swap (AL+6, 0x000000002ll, 0x1234567890ll) !=
++	0) abort ();
++  if (__sync_bool_compare_and_swap (AL+7, 0x100000000ll, 0x1234567890ll) !=
++	0) abort ();
++
++  if (__sync_fetch_and_add (AL+8, 1) != 0) abort ();
++  if (__sync_fetch_and_add (AL+9, 0xb000e0000000ll) != 0x1000e0de0000ll) abort ();
++  if (__sync_fetch_and_sub (AL+10, 22) != 42) abort ();
++  if (__sync_fetch_and_sub (AL+11, 0xb000e0000000ll) != 0xc001c0de0000ll)
++	abort ();
++
++  if (__sync_fetch_and_and (AL+12, 0x300000007ll) != -1ll) abort ();
++  if (__sync_fetch_and_or (AL+13, 0x500000009ll) != 0) abort ();
++  if (__sync_fetch_and_xor (AL+14, 0xe00000001ll) != 0xff00ff0000ll) abort ();
++  if (__sync_fetch_and_nand (AL+15, 0xa00000007ll) != -1ll) abort ();
++
++  /* These should be the same as the fetch_and_* cases except for
++     return value.  */
++  if (__sync_add_and_fetch (AL+16, 1) != 1) abort ();
++  if (__sync_add_and_fetch (AL+17, 0xb000e0000000ll) != 0xc001c0de0000ll)
++	abort ();
++  if (__sync_sub_and_fetch (AL+18, 22) != 20) abort ();
++  if (__sync_sub_and_fetch (AL+19, 0xb000e0000000ll) != 0x1000e0de0000ll)
++	abort ();
++
++  if (__sync_and_and_fetch (AL+20, 0x300000007ll) != 0x300000007ll) abort ();
++  if (__sync_or_and_fetch (AL+21, 0x500000009ll) != 0x500000009ll) abort ();
++  if (__sync_xor_and_fetch (AL+22, 0xe00000001ll) != 0xf100ff0001ll) abort ();
++  if (__sync_nand_and_fetch (AL+23, 0xa00000007ll) != ~0xa00000007ll) abort ();
++}
++
++int main ()
++{
++  memcpy (AL, init_di, sizeof (init_di));
++
++  do_noret_di ();
++
++  if (memcmp (AL, test_di, sizeof (test_di)))
++    abort ();
++
++  memcpy (AL, init_di, sizeof (init_di));
++
++  do_ret_di ();
++
++  if (memcmp (AL, test_di, sizeof (test_di)))
++    abort ();
++
++  return 0;
++}
+
+=== added file 'gcc/testsuite/gcc.dg/di-sync-multithread.c'
+--- old/gcc/testsuite/gcc.dg/di-sync-multithread.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/di-sync-multithread.c	2011-10-14 15:56:32 +0000
+@@ -0,0 +1,205 @@
++/* { dg-do run } */
++/* { dg-require-effective-target sync_longlong } */
++/* { dg-require-effective-target pthread_h } */
++/* { dg-require-effective-target pthread } */
++/* { dg-options "-pthread -std=gnu99" } */
++
++/* test of long long atomic ops performed in parallel in 3 pthreads
++   david.gilbert@linaro.org */
++
++#include <pthread.h>
++#include <unistd.h>
++
++/*#define DEBUGIT 1 */
++
++#ifdef DEBUGIT
++#include <stdio.h>
++
++#define DOABORT(x,...) {\
++	 fprintf (stderr, x, __VA_ARGS__); fflush (stderr); abort ();\
++	 }
++
++#else
++
++#define DOABORT(x,...) abort ();
++
++#endif
++
++/* Passed to each thread to describe which bits it is going to work on.  */
++struct threadwork {
++  unsigned long long count; /* incremented each time the worker loops.  */
++  unsigned int thread;    /* ID */
++  unsigned int addlsb;    /* 8 bit */
++  unsigned int logic1lsb; /* 5 bit */
++  unsigned int logic2lsb; /* 8 bit */
++};
++
++/* The shared word where all the atomic work is done.  */
++static volatile long long workspace;
++
++/* A shared word to tell the workers to quit when non-0.  */
++static long long doquit;
++
++extern void abort (void);
++
++/* Note this test doesn't test the return values much.  */
++void*
++worker (void* data)
++{
++  struct threadwork *tw = (struct threadwork*)data;
++  long long add1bit = 1ll << tw->addlsb;
++  long long logic1bit = 1ll << tw->logic1lsb;
++  long long logic2bit = 1ll << tw->logic2lsb;
++
++  /* Clear the bits we use.  */
++  __sync_and_and_fetch (&workspace, ~(0xffll * add1bit));
++  __sync_fetch_and_and (&workspace, ~(0x1fll * logic1bit));
++  __sync_fetch_and_and (&workspace, ~(0xffll * logic2bit));
++
++  do
++    {
++      long long tmp1, tmp2, tmp3;
++      /* OK, lets try and do some stuff to the workspace - by the end
++         of the main loop our area should be the same as it is now - i.e. 0.  */
++
++      /* Push the arithmetic section upto 128 - one of the threads will
++         case this to carry accross the 32bit boundary.  */
++      for (tmp2 = 0; tmp2 < 64; tmp2++)
++	{
++	  /* Add 2 using the two different adds.  */
++	  tmp1 = __sync_add_and_fetch (&workspace, add1bit);
++	  tmp3 = __sync_fetch_and_add (&workspace, add1bit);
++
++	  /* The value should be the intermediate add value in both cases.  */
++	  if ((tmp1 & (add1bit * 0xff)) != (tmp3 & (add1bit * 0xff)))
++	    DOABORT ("Mismatch of add intermediates on thread %d "
++			"workspace=0x%llx tmp1=0x%llx "
++			"tmp2=0x%llx tmp3=0x%llx\n",
++			 tw->thread, workspace, tmp1, tmp2, tmp3);
++	}
++
++      /* Set the logic bits.  */
++      tmp2=__sync_or_and_fetch (&workspace,
++			  0x1fll * logic1bit | 0xffll * logic2bit);
++
++      /* Check the logic bits are set and the arithmetic value is correct.  */
++      if ((tmp2 & (0x1fll * logic1bit | 0xffll * logic2bit
++			| 0xffll * add1bit))
++	  != (0x1fll * logic1bit | 0xffll * logic2bit | 0x80ll * add1bit))
++	DOABORT ("Midloop check failed on thread %d "
++			"workspace=0x%llx tmp2=0x%llx "
++			"masktmp2=0x%llx expected=0x%llx\n",
++		tw->thread, workspace, tmp2,
++		tmp2 & (0x1fll * logic1bit | 0xffll * logic2bit |
++			 0xffll * add1bit),
++		(0x1fll * logic1bit | 0xffll * logic2bit | 0x80ll * add1bit));
++
++      /* Pull the arithmetic set back down to 0 - again this should cause a
++	 carry across the 32bit boundary in one thread.  */
++
++      for (tmp2 = 0; tmp2 < 64; tmp2++)
++	{
++	  /* Subtract 2 using the two different subs.  */
++	  tmp1=__sync_sub_and_fetch (&workspace, add1bit);
++	  tmp3=__sync_fetch_and_sub (&workspace, add1bit);
++
++	  /* The value should be the intermediate sub value in both cases.  */
++	  if ((tmp1 & (add1bit * 0xff)) != (tmp3 & (add1bit * 0xff)))
++	    DOABORT ("Mismatch of sub intermediates on thread %d "
++			"workspace=0x%llx tmp1=0x%llx "
++			"tmp2=0x%llx tmp3=0x%llx\n",
++			tw->thread, workspace, tmp1, tmp2, tmp3);
++	}
++
++
++      /* Clear the logic bits.  */
++      __sync_fetch_and_xor (&workspace, 0x1fll * logic1bit);
++      tmp3=__sync_and_and_fetch (&workspace, ~(0xffll * logic2bit));
++
++      /* The logic bits and the arithmetic bits should be zero again.  */
++      if (tmp3 & (0x1fll * logic1bit | 0xffll * logic2bit | 0xffll * add1bit))
++	DOABORT ("End of worker loop; bits none 0 on thread %d "
++			"workspace=0x%llx tmp3=0x%llx "
++			"mask=0x%llx maskedtmp3=0x%llx\n",
++		tw->thread, workspace, tmp3, (0x1fll * logic1bit |
++			0xffll * logic2bit | 0xffll * add1bit),
++		tmp3 & (0x1fll * logic1bit | 0xffll * logic2bit | 0xffll * add1bit));
++
++      __sync_add_and_fetch (&tw->count, 1);
++    }
++  while (!__sync_bool_compare_and_swap (&doquit, 1, 1));
++
++  pthread_exit (0);
++}
++
++int
++main ()
++{
++  /* We have 3 threads doing three sets of operations, an 8 bit
++     arithmetic field, a 5 bit logic field and an 8 bit logic
++     field (just to pack them all in).
++
++  6      5       4       4       3       2       1
++  3      6       8       0       2       4       6       8       0
++  |...,...|...,...|...,...|...,...|...,...|...,...|...,...|...,...
++  - T0   --  T1  -- T2   --T2 --  T0  -*- T2-- T1-- T1   -***- T0-
++   logic2  logic2  arith   log2  arith  log1 log1  arith     log1
++
++  */
++  unsigned int t;
++  long long tmp;
++  int err;
++
++  struct threadwork tw[3]={
++    { 0ll, 0, 27, 0, 56 },
++    { 0ll, 1,  8,16, 48 },
++    { 0ll, 2, 40,21, 35 }
++  };
++
++  pthread_t threads[3];
++
++  __sync_lock_release (&doquit);
++
++  /* Get the work space into a known value - All 1's.  */
++  __sync_lock_release (&workspace); /* Now all 0.  */
++  tmp = __sync_val_compare_and_swap (&workspace, 0, -1ll);
++  if (tmp!=0)
++    DOABORT ("Initial __sync_val_compare_and_swap wasn't 0 workspace=0x%llx "
++		"tmp=0x%llx\n", workspace,tmp);
++
++  for (t = 0; t < 3; t++)
++  {
++    err=pthread_create (&threads[t], NULL , worker, &tw[t]);
++    if (err) DOABORT ("pthread_create failed on thread %d with error %d\n",
++	t, err);
++  };
++
++  sleep (5);
++
++  /* Stop please.  */
++  __sync_lock_test_and_set (&doquit, 1ll);
++
++  for (t = 0; t < 3; t++)
++    {
++      err=pthread_join (threads[t], NULL);
++      if (err)
++	DOABORT ("pthread_join failed on thread %d with error %d\n", t, err);
++    };
++
++  __sync_synchronize ();
++
++  /* OK, so all the workers have finished -
++     the workers should have zero'd their workspace, the unused areas
++     should still be 1.  */
++  if (!__sync_bool_compare_and_swap (&workspace, 0x040000e0ll, 0))
++    DOABORT ("End of run workspace mismatch, got %llx\n", workspace);
++
++  /* All the workers should have done some work.  */
++  for (t = 0; t < 3; t++)
++    {
++      if (tw[t].count == 0) DOABORT ("Worker %d gave 0 count\n", t);
++    };
++
++  return 0;
++}
++
+
+=== added file 'gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c'
+--- old/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c	2011-10-14 15:56:32 +0000
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v5_ok } */
++/* { dg-options "-std=gnu99" } */
++/* { dg-add-options arm_arch_v5 } */
++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
++/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
++/* { dg-message "file included" "In file included" { target *-*-* } 0 } */
++
++#include "../../gcc.dg/di-longlong64-sync-1.c"
++
++/* On an old ARM we have no ldrexd or strexd so we have to use helpers.  */
++/* { dg-final { scan-assembler-not "ldrexd" } } */
++/* { dg-final { scan-assembler-not "strexd" } } */
++/* { dg-final { scan-assembler "__sync_" } } */
+
+=== added file 'gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c'
+--- old/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c	2011-10-14 15:56:32 +0000
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arm_ok } */
++/* { dg-options "-marm -std=gnu99" } */
++/* { dg-require-effective-target arm_arch_v6k_ok } */
++/* { dg-add-options arm_arch_v6k } */
++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
++/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
++/* { dg-message "file included" "In file included" { target *-*-* } 0 } */
++
++#include "../../gcc.dg/di-longlong64-sync-1.c"
++
++/* We should be using ldrexd, strexd and no helpers or shorter ldrex.  */
++/* { dg-final { scan-assembler-times "\tldrexd" 46 } } */
++/* { dg-final { scan-assembler-times "\tstrexd" 46 } } */
++/* { dg-final { scan-assembler-not "__sync_" } } */
++/* { dg-final { scan-assembler-not "ldrex\t" } } */
++/* { dg-final { scan-assembler-not "strex\t" } } */
+
+=== modified file 'gcc/testsuite/lib/target-supports.exp'
+--- old/gcc/testsuite/lib/target-supports.exp	2011-11-22 17:10:17 +0000
++++ new/gcc/testsuite/lib/target-supports.exp	2011-11-28 15:07:01 +0000
+@@ -2000,6 +2000,47 @@
+ 		check_effective_target_arm_fp16_ok_nocache]
+ }
+ 
++# Creates a series of routines that return 1 if the given architecture
++# can be selected and a routine to give the flags to select that architecture
++# Note: Extra flags may be added to disable options from newer compilers
++# (Thumb in particular - but others may be added in the future)
++# Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
++#        /* { dg-add-options arm_arch_v5 } */
++foreach { armfunc armflag armdef } { v5 "-march=armv5 -marm" __ARM_ARCH_5__
++				     v6 "-march=armv6" __ARM_ARCH_6__
++				     v6k "-march=armv6k" __ARM_ARCH_6K__
++				     v7a "-march=armv7-a" __ARM_ARCH_7A__ } {
++    eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
++	proc check_effective_target_arm_arch_FUNC_ok { } {
++	    if { [ string match "*-marm*" "FLAG" ] &&
++		![check_effective_target_arm_arm_ok] } {
++		return 0
++	    }
++	    return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
++		#if !defined (DEF)
++		#error FOO
++		#endif
++	    } "FLAG" ]
++	}
++
++	proc add_options_for_arm_arch_FUNC { flags } {
++	    return "$flags FLAG"
++	}
++    }]
++}
++
++# Return 1 if this is an ARM target where -marm causes ARM to be
++# used (not Thumb)
++
++proc check_effective_target_arm_arm_ok { } {
++    return [check_no_compiler_messages arm_arm_ok assembly {
++	#if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
++	#error FOO
++	#endif
++    } "-marm"]
++}
++
++
+ # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
+ # used.
+ 
+@@ -3384,6 +3425,31 @@
+     return $et_sync_int_long_saved
+ }
+ 
++# Return 1 if the target supports atomic operations on "long long" and can
++# execute them
++# So far only put checks in for ARM, others may want to add their own
++proc check_effective_target_sync_longlong { } {
++    return [check_runtime sync_longlong_runtime {
++      #include <stdlib.h>
++      int main ()
++      {
++	long long l1;
++
++	if (sizeof (long long) != 8)
++	  exit (1);
++
++      #ifdef __arm__
++	/* Just check for native; checking for kernel fallback is tricky.  */
++	asm volatile ("ldrexd r0,r1, [%0]" : : "r" (&l1) : "r0", "r1");
++      #else
++      # error "Add other suitable archs here"
++      #endif
++
++	exit (0);
++      }
++    } "" ]
++}
++
+ # Return 1 if the target supports atomic operations on "char" and "short".
+ 
+ proc check_effective_target_sync_char_short { } {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch
new file mode 100644
index 0000000000..88d74c72f3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch
@@ -0,0 +1,487 @@
+2011-11-27  Ira Rosen  <ira.rosen@linaro.org>
+
+	Needs to be merged upstream:
+
+	gcc/
+	* tree-vect-patterns.c (widened_name_p): Rename to ...
+	(type_conversion_p): ... this.  Add new argument to determine
+	if it's a promotion or demotion operation.  Check for
+	CONVERT_EXPR_CODE_P instead of NOP_EXPR.
+	(vect_recog_dot_prod_pattern): Call type_conversion_p instead
+	widened_name_p.
+	(vect_recog_widen_mult_pattern, vect_recog_widen_sum_pattern,
+	vect_operation_fits_smaller_type, vect_recog_widen_shift_pattern):
+	Likewise.
+	(vect_recog_mixed_size_cond_pattern): Likewise and allow
+	non-constant then and else clauses.
+
+	gcc/testsuite/
+	* gcc.dg/vect/bb-slp-cond-3.c: New test.
+	* gcc.dg/vect/bb-slp-cond-4.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-cond-3.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-cond-3.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-cond-3.c	2011-11-27 11:29:32 +0000
+@@ -0,0 +1,85 @@
++/* { dg-require-effective-target vect_condition } */
++
++#include "tree-vect.h"
++
++#define N 64 
++
++/* Comparison in int, then/else and result in unsigned char.  */ 
++
++static inline unsigned char
++foo (int x, int y, int a, int b)
++{
++  if (x >= y)
++    return a;
++  else
++    return b;
++}
++
++__attribute__((noinline, noclone)) void
++bar (unsigned char * __restrict__ a, unsigned char * __restrict__ b,
++     unsigned char * __restrict__ c, unsigned char * __restrict__ d,
++     unsigned char * __restrict__ e, int stride, int w)
++{
++  int i;
++  for (i = 0; i < N/stride; i++, a += stride, b += stride, c += stride,
++				d += stride, e += stride)
++    {
++      e[0] = foo (c[0], d[0], a[0] * w, b[0] * w);
++      e[1] = foo (c[1], d[1], a[1] * w, b[1] * w);
++      e[2] = foo (c[2], d[2], a[2] * w, b[2] * w);
++      e[3] = foo (c[3], d[3], a[3] * w, b[3] * w);
++      e[4] = foo (c[4], d[4], a[4] * w, b[4] * w);
++      e[5] = foo (c[5], d[5], a[5] * w, b[5] * w);
++      e[6] = foo (c[6], d[6], a[6] * w, b[6] * w);
++      e[7] = foo (c[7], d[7], a[7] * w, b[7] * w);
++      e[8] = foo (c[8], d[8], a[8] * w, b[8] * w);
++      e[9] = foo (c[9], d[9], a[9] * w, b[9] * w);
++      e[10] = foo (c[10], d[10], a[10] * w, b[10] * w);
++      e[11] = foo (c[11], d[11], a[11] * w, b[11] * w);
++      e[12] = foo (c[12], d[12], a[12] * w, b[12] * w);
++      e[13] = foo (c[13], d[13], a[13] * w, b[13] * w);
++      e[14] = foo (c[14], d[14], a[14] * w, b[14] * w);
++      e[15] = foo (c[15], d[15], a[15] * w, b[15] * w);
++    }
++}
++
++
++unsigned char a[N], b[N], c[N], d[N], e[N];
++
++int main ()
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      a[i] = i;
++      b[i] = 5;
++      e[i] = 0;
++
++      switch (i % 9)
++        {
++        case 0: asm (""); c[i] = i; d[i] = i + 1; break;
++        case 1: c[i] = 0; d[i] = 0; break;
++        case 2: c[i] = i + 1; d[i] = i - 1; break;
++        case 3: c[i] = i; d[i] = i + 7; break;
++        case 4: c[i] = i; d[i] = i; break;
++        case 5: c[i] = i + 16; d[i] = i + 3; break;
++        case 6: c[i] = i - 5; d[i] = i; break;
++        case 7: c[i] = i; d[i] = i; break;
++        case 8: c[i] = i; d[i] = i - 7; break;
++        }
++    }
++
++  bar (a, b, c, d, e, 16, 2);
++  for (i = 0; i < N; i++)
++    if (e[i] != ((i % 3) == 0 ? 10 : 2 * i))
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_element_align && vect_int_mult } } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-cond-4.c'
+--- old/gcc/testsuite/gcc.dg/vect/bb-slp-cond-4.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/bb-slp-cond-4.c	2011-11-27 11:29:32 +0000
+@@ -0,0 +1,85 @@
++/* { dg-require-effective-target vect_condition } */
++
++#include "tree-vect.h"
++
++#define N 64 
++
++/* Comparison in short, then/else and result in int.  */
++static inline int
++foo (short x, short y, int a, int b)
++{
++  if (x >= y)
++    return a;
++  else
++    return b;
++}
++
++__attribute__((noinline, noclone)) void
++bar (short * __restrict__ a, short * __restrict__ b,
++     short * __restrict__ c, short * __restrict__ d,
++     int * __restrict__ e, int stride, int w)
++{
++  int i;
++  for (i = 0; i < N/stride; i++, a += stride, b += stride, c += stride,
++				d += stride, e += stride)
++    {
++      e[0] = foo (c[0], d[0], a[0], b[0]);
++      e[1] = foo (c[1], d[1], a[1], b[1]);
++      e[2] = foo (c[2], d[2], a[2], b[2]);
++      e[3] = foo (c[3], d[3], a[3], b[3]);
++      e[4] = foo (c[4], d[4], a[4], b[4]);
++      e[5] = foo (c[5], d[5], a[5], b[5]);
++      e[6] = foo (c[6], d[6], a[6], b[6]);
++      e[7] = foo (c[7], d[7], a[7], b[7]);
++      e[8] = foo (c[8], d[8], a[8], b[8]);
++      e[9] = foo (c[9], d[9], a[9], b[9]);
++      e[10] = foo (c[10], d[10], a[10], b[10]);
++      e[11] = foo (c[11], d[11], a[11], b[11]);
++      e[12] = foo (c[12], d[12], a[12], b[12]);
++      e[13] = foo (c[13], d[13], a[13], b[13]);
++      e[14] = foo (c[14], d[14], a[14], b[14]);
++      e[15] = foo (c[15], d[15], a[15], b[15]);
++    }
++}
++
++
++short a[N], b[N], c[N], d[N];
++int e[N];
++
++int main ()
++{
++  int i;
++
++  check_vect ();
++
++  for (i = 0; i < N; i++)
++    {
++      a[i] = i;
++      b[i] = 5;
++      e[i] = 0;
++
++      switch (i % 9)
++        {
++        case 0: asm (""); c[i] = - i - 1; d[i] = i + 1; break;
++        case 1: c[i] = 0; d[i] = 0; break;
++        case 2: c[i] = i + 1; d[i] = - i - 1; break;
++        case 3: c[i] = i; d[i] = i + 7; break;
++        case 4: c[i] = i; d[i] = i; break;
++        case 5: c[i] = i + 16; d[i] = i + 3; break;
++        case 6: c[i] = - i - 5; d[i] = - i; break;
++        case 7: c[i] = - i; d[i] = - i; break;
++        case 8: c[i] = - i; d[i] = - i - 7; break;
++        }
++    }
++
++  bar (a, b, c, d, e, 16, 2);
++  for (i = 0; i < N; i++)
++    if (e[i] != ((i % 3) == 0 ? 5 : i))
++      abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
++/* { dg-final { cleanup-tree-dump "slp" } } */
++
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2011-11-23 07:49:33 +0000
++++ new/gcc/tree-vect-patterns.c	2011-11-27 12:17:31 +0000
+@@ -62,18 +62,16 @@
+ 	vect_recog_mixed_size_cond_pattern};
+ 
+ 
+-/* Function widened_name_p
+-
+-   Check whether NAME, an ssa-name used in USE_STMT,
+-   is a result of a type-promotion, such that:
+-     DEF_STMT: NAME = NOP (name0)
+-   where the type of name0 (HALF_TYPE) is smaller than the type of NAME.
++/* Check whether NAME, an ssa-name used in USE_STMT,
++   is a result of a type promotion or demotion, such that:
++      DEF_STMT: NAME = NOP (name0)
++   where the type of name0 (ORIG_TYPE) is smaller/bigger than the type of NAME.
+    If CHECK_SIGN is TRUE, check that either both types are signed or both are
+    unsigned.  */
+ 
+ static bool
+-widened_name_p (tree name, gimple use_stmt, tree *half_type, gimple *def_stmt,
+-		bool check_sign)
++type_conversion_p (tree name, gimple use_stmt, bool check_sign,
++                   tree *orig_type, gimple *def_stmt, bool *promotion)
+ {
+   tree dummy;
+   gimple dummy_gimple;
+@@ -96,21 +94,27 @@
+       && dt != vect_external_def && dt != vect_constant_def)
+     return false;
+ 
+-  if (! *def_stmt)
++  if (!*def_stmt)
+     return false;
+ 
+   if (!is_gimple_assign (*def_stmt))
+     return false;
+ 
+-  if (gimple_assign_rhs_code (*def_stmt) != NOP_EXPR)
++  if (!CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (*def_stmt)))
+     return false;
+ 
+   oprnd0 = gimple_assign_rhs1 (*def_stmt);
+ 
+-  *half_type = TREE_TYPE (oprnd0);
+-  if (!INTEGRAL_TYPE_P (type) || !INTEGRAL_TYPE_P (*half_type)
+-      || ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*half_type)) && check_sign)
+-      || (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 2)))
++  *orig_type = TREE_TYPE (oprnd0);
++  if (!INTEGRAL_TYPE_P (type) || !INTEGRAL_TYPE_P (*orig_type)
++      || ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*orig_type)) && check_sign))
++    return false;
++
++  if (TYPE_PRECISION (type) >= (TYPE_PRECISION (*orig_type) * 2))
++    *promotion = true;
++  else if (TYPE_PRECISION (*orig_type) >= (TYPE_PRECISION (type) * 2))
++    *promotion = false;
++  else
+     return false;
+ 
+   if (!vect_is_simple_use (oprnd0, loop_vinfo, bb_vinfo, &dummy_gimple, &dummy,
+@@ -192,6 +196,7 @@
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+   struct loop *loop;
+   tree var, rhs;
++  bool promotion;
+ 
+   if (!loop_info)
+     return NULL;
+@@ -255,7 +260,9 @@
+         return NULL;
+       stmt = last_stmt;
+ 
+-      if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt, true))
++      if (type_conversion_p (oprnd0, stmt, true, &half_type, &def_stmt,
++                             &promotion)
++          && promotion)
+         {
+           stmt = def_stmt;
+           oprnd0 = gimple_assign_rhs1 (stmt);
+@@ -310,10 +317,14 @@
+       if (!types_compatible_p (TREE_TYPE (oprnd0), prod_type)
+           || !types_compatible_p (TREE_TYPE (oprnd1), prod_type))
+         return NULL;
+-      if (!widened_name_p (oprnd0, stmt, &half_type0, &def_stmt, true))
++      if (!type_conversion_p (oprnd0, stmt, true, &half_type0, &def_stmt,
++                              &promotion)
++          || !promotion)
+         return NULL;
+       oprnd00 = gimple_assign_rhs1 (def_stmt);
+-      if (!widened_name_p (oprnd1, stmt, &half_type1, &def_stmt, true))
++      if (!type_conversion_p (oprnd0, stmt, true, &half_type1, &def_stmt,
++                              &promotion)
++          || !promotion)
+         return NULL;
+       oprnd01 = gimple_assign_rhs1 (def_stmt);
+       if (!types_compatible_p (half_type0, half_type1))
+@@ -526,7 +537,7 @@
+   enum tree_code dummy_code;
+   int dummy_int;
+   VEC (tree, heap) *dummy_vec;
+-  bool op1_ok;
++  bool op1_ok, promotion;
+ 
+   if (!is_gimple_assign (last_stmt))
+     return NULL;
+@@ -546,12 +557,14 @@
+     return NULL;
+ 
+   /* Check argument 0.  */
+-  if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
++  if (!type_conversion_p (oprnd0, last_stmt, false, &half_type0, &def_stmt0,
++                          &promotion)
++      || !promotion)
+     return NULL;
+-  /* Check argument 1.  */
+-  op1_ok = widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1, false);
+-
+-  if (op1_ok)
++   /* Check argument 1.  */
++  op1_ok = type_conversion_p (oprnd1, last_stmt, false, &half_type1,
++                              &def_stmt1, &promotion);
++  if (op1_ok && promotion)
+     {
+       oprnd0 = gimple_assign_rhs1 (def_stmt0);
+       oprnd1 = gimple_assign_rhs1 (def_stmt1);
+@@ -793,6 +806,7 @@
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+   struct loop *loop;
+   tree var;
++  bool promotion;
+ 
+   if (!loop_info)
+     return NULL;
+@@ -832,8 +846,10 @@
+      Left to check that oprnd0 is defined by a cast from type 'type' to type
+      'TYPE'.  */
+ 
+-  if (!widened_name_p (oprnd0, last_stmt, &half_type, &stmt, true))
+-    return NULL;
++  if (!type_conversion_p (oprnd0, last_stmt, true, &half_type, &stmt,
++                          &promotion)
++      || !promotion)
++     return NULL;
+ 
+   oprnd0 = gimple_assign_rhs1 (stmt);
+   *type_in = half_type;
+@@ -899,6 +915,7 @@
+   gimple def_stmt, new_stmt;
+   bool first = false;
+   loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
++  bool promotion;
+   bb_vec_info bb_info = STMT_VINFO_BB_VINFO (vinfo_for_stmt (stmt));
+   struct loop *loop = NULL;
+ 
+@@ -933,7 +950,9 @@
+   else
+     {
+       first = true;
+-      if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
++      if (!type_conversion_p (oprnd, stmt, false, &half_type, &def_stmt,
++                               &promotion)
++         || !promotion
+           || !gimple_bb (def_stmt)
+           || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
+ 	  || (!loop && gimple_bb (def_stmt) != BB_VINFO_BB (bb_info)
+@@ -1327,6 +1346,7 @@
+   VEC (tree, heap) * dummy_vec;
+   gimple use_stmt = NULL;
+   bool over_widen = false;
++  bool promotion;
+ 
+   if (!is_gimple_assign (last_stmt) || !vinfo_for_stmt (last_stmt))
+     return NULL;
+@@ -1381,8 +1401,10 @@
+     return NULL;
+ 
+   /* Check operand 0: it has to be defined by a type promotion.  */
+-  if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
+-    return NULL;
++  if (!type_conversion_p (oprnd0, last_stmt, false, &half_type0, &def_stmt0,
++                          &promotion)
++      || !promotion)
++     return NULL;
+ 
+   /* Check operand 1: has to be positive.  We check that it fits the type
+      in vect_handle_widen_op_by_const ().  */
+@@ -1492,9 +1514,9 @@
+      S1  a_T = x_t CMP y_t ? b_T : c_T;
+ 
+    where type 'TYPE' is an integral type which has different size
+-   from 'type'.  b_T and c_T are constants and if 'TYPE' is wider
++   from 'type'.  b_T and c_T are either constants (and if 'TYPE' is wider
+    than 'type', the constants need to fit into an integer type
+-   with the same width as 'type'.
++   with the same width as 'type') or results of conversion from 'type'.
+ 
+    Input:
+ 
+@@ -1523,6 +1545,9 @@
+   enum machine_mode cmpmode;
+   gimple pattern_stmt, def_stmt;
+   loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
++  tree orig_type0 = NULL_TREE, orig_type1 = NULL_TREE;
++  gimple def_stmt0 = NULL, def_stmt1 = NULL;
++  bool promotion;
+   bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
+ 
+   if (!is_gimple_assign (last_stmt)
+@@ -1535,25 +1560,40 @@
+   then_clause = TREE_OPERAND (op, 1);
+   else_clause = TREE_OPERAND (op, 2);
+ 
+-  if (TREE_CODE (then_clause) != INTEGER_CST
+-      || TREE_CODE (else_clause) != INTEGER_CST)
+-    return NULL;
+-
+   if (!COMPARISON_CLASS_P (cond_expr))
+     return NULL;
+ 
+   type = gimple_expr_type (last_stmt);
+   comp_type = TREE_TYPE (TREE_OPERAND (cond_expr, 0));
+-  if (!INTEGRAL_TYPE_P (comp_type)
+-      || !INTEGRAL_TYPE_P (type))
+-    return NULL;
+-
+   comp_vectype = get_vectype_for_scalar_type (comp_type);
+   if (comp_vectype == NULL_TREE)
+     return NULL;
+ 
++  if (types_compatible_p (type, comp_type)
++      || !INTEGRAL_TYPE_P (comp_type)
++      || !INTEGRAL_TYPE_P (type))
++    return NULL;
++
++  if ((TREE_CODE (then_clause) != INTEGER_CST
++       && !type_conversion_p (then_clause, last_stmt, false, &orig_type0,
++			      &def_stmt0, &promotion))
++      || (TREE_CODE (else_clause) != INTEGER_CST
++	  && !type_conversion_p (else_clause, last_stmt, false, &orig_type1,
++				 &def_stmt1, &promotion)))
++    return NULL;
++
++  if (orig_type0 && orig_type1
++      && (!types_compatible_p (orig_type0, orig_type1)
++	  || !types_compatible_p (orig_type0, comp_type)))
++    return NULL;
++
++  if (orig_type0)
++    then_clause = gimple_assign_rhs1 (def_stmt0);
++
++  if (orig_type1)
++    else_clause = gimple_assign_rhs1 (def_stmt1);
++
+   cmpmode = GET_MODE_INNER (TYPE_MODE (comp_vectype));
+-
+   if (GET_MODE_BITSIZE (TYPE_MODE (type)) == GET_MODE_BITSIZE (cmpmode))
+     return NULL;
+ 
+@@ -1561,18 +1601,15 @@
+   if (vectype == NULL_TREE)
+     return NULL;
+ 
+-  if (types_compatible_p (vectype, comp_vectype))
+-    return NULL;
+-
+   if (!expand_vec_cond_expr_p (comp_vectype, TYPE_MODE (comp_vectype)))
+     return NULL;
+ 
+-  if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode))
+-    {
+-      if (!int_fits_type_p (then_clause, comp_type)
+-	  || !int_fits_type_p (else_clause, comp_type))
+-	return NULL;
+-    }
++  if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode)
++      && ((TREE_CODE (then_clause) == INTEGER_CST
++           && !int_fits_type_p (then_clause, comp_type))
++          || (TREE_CODE (else_clause) == INTEGER_CST
++              && !int_fits_type_p (else_clause, comp_type))))
++    return NULL;
+ 
+   tmp = build3 (COND_EXPR, comp_type, unshare_expr (cond_expr),
+ 		fold_convert (comp_type, then_clause),
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch
new file mode 100644
index 0000000000..43a2a4da96
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch
@@ -0,0 +1,276 @@
+2011-12-05  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline -A15 tuning.
+	2011-11-30  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* config/arm/arm.c (arm_issue_rate): Cortex-A15 can triple issue.
+	* config/arm/arm.md (mul64): New attribute.
+	(generic_sched): Cortex-A15 is not scheduled generically.
+	(cortex-a15.md): Include.
+	* config/arm/cortex-a15.md: New machine description.
+	* config/arm/t-arm (MD_INCLUDES): Add cortex-a15.md.
+
+        2011-11-30  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+	* config/arm/t-arm (MD_INCLUDES): Ensure all md files are listed.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2011-12-05 10:55:48 +0000
++++ new/gcc/config/arm/arm.c	2011-12-05 12:33:25 +0000
+@@ -24056,6 +24056,9 @@
+ {
+   switch (arm_tune)
+     {
++    case cortexa15:
++      return 3;
++
+     case cortexr4:
+     case cortexr4f:
+     case cortexr5:
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2011-10-26 11:38:30 +0000
++++ new/gcc/config/arm/arm.md	2011-12-02 00:38:59 +0000
+@@ -345,6 +345,13 @@
+ 	 (const_string "mult")
+ 	 (const_string "alu")))
+ 
++; Is this an (integer side) multiply with a 64-bit result?
++(define_attr "mul64" "no,yes"
++	     (if_then_else
++	       (eq_attr "insn" "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
++	       (const_string "yes")
++	       (const_string "no")))
++
+ ; Load scheduling, set from the arm_ld_sched variable
+ ; initialized by arm_option_override()
+ (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
+@@ -511,7 +518,7 @@
+ 
+ (define_attr "generic_sched" "yes,no"
+   (const (if_then_else
+-          (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4")
++          (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexa15,cortexm4")
+ 	       (eq_attr "tune_cortexr4" "yes"))
+           (const_string "no")
+           (const_string "yes"))))
+@@ -537,6 +544,7 @@
+ (include "cortex-a5.md")
+ (include "cortex-a8.md")
+ (include "cortex-a9.md")
++(include "cortex-a15.md")
+ (include "cortex-r4.md")
+ (include "cortex-r4f.md")
+ (include "cortex-m4.md")
+
+=== added file 'gcc/config/arm/cortex-a15.md'
+--- old/gcc/config/arm/cortex-a15.md	1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/cortex-a15.md	2011-12-02 00:38:59 +0000
+@@ -0,0 +1,186 @@
++;; ARM Cortex-A15 pipeline description
++;; Copyright (C) 2011 Free Software Foundation, Inc.
++;;
++;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
++
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++
++(define_automaton "cortex_a15")
++
++;; The Cortex-A15 core is modelled as a triple issue pipeline that has
++;; the following dispatch units.
++;; 1. Two pipelines for simple integer operations: SX1, SX2
++;; 2. Two pipelines for Neon and FP data-processing operations: CX1, CX2
++;; 3. One pipeline for branch operations: BX
++;; 4. One pipeline for integer multiply and divide operations: MX
++;; 5. Two pipelines for load and store operations: LS1, LS2
++;;
++;; We can issue into three pipelines per-cycle.
++;;
++;; We assume that where we have unit pairs xx1 is always filled before xx2.
++
++;; The three issue units
++(define_cpu_unit "ca15_i0, ca15_i1, ca15_i2" "cortex_a15")
++
++(define_reservation "ca15_issue1" "(ca15_i0|ca15_i1|ca15_i2)")
++(define_reservation "ca15_issue2" "((ca15_i0+ca15_i1)|(ca15_i1+ca15_i2))")
++(define_reservation "ca15_issue3" "(ca15_i0+ca15_i1+ca15_i2)")
++(final_presence_set "ca15_i1" "ca15_i0")
++(final_presence_set "ca15_i2" "ca15_i1")
++
++;; The main dispatch units
++(define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15")
++(define_cpu_unit "ca15_cx1, ca15_cx2" "cortex_a15")
++(define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15")
++(define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15")
++
++(define_reservation "ca15_ls" "(ca15_ls1|ca15_ls2)")
++
++;; The extended load-store pipeline
++(define_cpu_unit "ca15_ldr, ca15_str" "cortex_a15")
++
++;; The extended ALU pipeline
++(define_cpu_unit "ca15_sx1_alu, ca15_sx1_shf, ca15_sx1_sat" "cortex_a15")
++(define_cpu_unit "ca15_sx2_alu, ca15_sx2_shf, ca15_sx2_sat" "cortex_a15")
++
++;; Simple Execution Unit:
++;;
++;; Simple ALU without shift
++(define_insn_reservation "cortex_a15_alu" 2
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "alu")
++            (eq_attr "neon_type" "none")))
++  "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
++
++;; ALU ops with immediate shift
++(define_insn_reservation "cortex_a15_alu_shift" 3
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "alu_shift")
++            (eq_attr "neon_type" "none")))
++  "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
++	       |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
++
++;; ALU ops with register controlled shift
++(define_insn_reservation "cortex_a15_alu_shift_reg" 3
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "alu_shift_reg")
++	    (eq_attr "neon_type" "none")))
++  "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
++   |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
++   |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
++
++;; Multiply Execution Unit:
++;;
++;; 32-bit multiplies
++(define_insn_reservation "cortex_a15_mult32" 3
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "mult")
++	    (and (eq_attr "neon_type" "none")
++		 (eq_attr "mul64" "no"))))
++  "ca15_issue1,ca15_mx")
++
++;; 64-bit multiplies
++(define_insn_reservation "cortex_a15_mult64" 4
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "mult")
++	    (and (eq_attr "neon_type" "none")
++		 (eq_attr "mul64" "yes"))))
++  "ca15_issue1,ca15_mx*2")
++
++;; Integer divide
++(define_insn_reservation "cortex_a15_udiv" 9
++  (and (eq_attr "tune" "cortexa15")
++       (eq_attr "insn" "udiv"))
++  "ca15_issue1,ca15_mx")
++
++(define_insn_reservation "cortex_a15_sdiv" 10
++  (and (eq_attr "tune" "cortexa15")
++       (eq_attr "insn" "sdiv"))
++  "ca15_issue1,ca15_mx")
++
++;; Block all issue pipes for a cycle
++(define_insn_reservation "cortex_a15_block" 1
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "block")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue3")
++
++;; Branch execution Unit
++;;
++;; Branches take one issue slot.
++;; No latency as there is no result
++(define_insn_reservation "cortex_a15_branch" 0
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "branch")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue1,ca15_bx")
++
++
++;; We lie with calls.  They take up all issue slots, and form a block in the
++;; pipeline.  The result however is available the next cycle.
++;;
++;; Addition of new units requires this to be updated.
++(define_insn_reservation "cortex_a15_call" 1
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "call")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue3,\
++   ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx1+ca15_cx2+ca15_ls1+ca15_ls2,\
++   ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+ca15_sx2_shf\
++    +ca15_sx2_sat+ca15_ldr+ca15_str")
++
++;; Load-store execution Unit
++;;
++;; Loads of up to two words.
++(define_insn_reservation "cortex_a15_load1" 4
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "load_byte,load1,load2")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue1,ca15_ls,ca15_ldr,nothing")
++
++;; Loads of three or four words.
++(define_insn_reservation "cortex_a15_load3" 5
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "load3,load4")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
++
++;; Stores of up to two words.
++(define_insn_reservation "cortex_a15_store1" 0
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "store1,store2")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue1,ca15_ls,ca15_str")
++
++;; Stores of three or four words.
++(define_insn_reservation "cortex_a15_store3" 0
++  (and (eq_attr "tune" "cortexa15")
++       (and (eq_attr "type" "store3,store4")
++	    (eq_attr "neon_type" "none")))
++  "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
++
++;; Simple execution unit bypasses
++(define_bypass 1 "cortex_a15_alu"
++	       "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
++(define_bypass 2 "cortex_a15_alu_shift"
++	       "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
++(define_bypass 2 "cortex_a15_alu_shift_reg"
++	       "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
++(define_bypass 1 "cortex_a15_alu" "cortex_a15_load1,cortex_a15_load3")
++(define_bypass 2 "cortex_a15_alu_shift" "cortex_a15_load1,cortex_a15_load3")
++(define_bypass 2 "cortex_a15_alu_shift_reg"
++	       "cortex_a15_load1,cortex_a15_load3")
+
+=== modified file 'gcc/config/arm/t-arm'
+--- old/gcc/config/arm/t-arm	2011-01-03 20:52:22 +0000
++++ new/gcc/config/arm/t-arm	2011-12-02 00:38:59 +0000
+@@ -31,6 +31,16 @@
+ 		$(srcdir)/config/arm/fmp626.md \
+ 		$(srcdir)/config/arm/fa726te.md \
+ 		$(srcdir)/config/arm/arm926ejs.md \
++		$(srcdir)/config/arm/cortex-a15.md \
++		$(srcdir)/config/arm/cortex-a5.md \
++		$(srcdir)/config/arm/cortex-a8.md \
++		$(srcdir)/config/arm/cortex-a8-neon.md \
++		$(srcdir)/config/arm/cortex-a9.md \
++		$(srcdir)/config/arm/cortex-a9-neon.md \
++		$(srcdir)/config/arm/cortex-m4-fpu.md \
++		$(srcdir)/config/arm/cortex-m4.md \
++		$(srcdir)/config/arm/cortex-r4f.md \
++		$(srcdir)/config/arm/cortex-r4.md \
+ 		$(srcdir)/config/arm/cirrus.md \
+ 		$(srcdir)/config/arm/fpa.md \
+ 		$(srcdir)/config/arm/vec-common.md \
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch
new file mode 100644
index 0000000000..8c51c1d1f3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch
@@ -0,0 +1,69 @@
+2011-12-20  Ira Rosen  <ira.rosen@linaro.org>
+
+	Backport from mainline:
+
+	2011-11-29  Ira Rosen  <ira.rosen@linaro.org>
+
+	PR tree-optimization/51301
+	gcc/
+	* tree-vect-patterns.c (vect_recog_over_widening_pattern): Check that
+	the last statement doesn't convert to a bigger type than the original
+	type of the computation.
+
+	gcc/testsuite/
+	* gcc.dg/vect/pr51301.c: New test.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/pr51301.c'
+--- old/gcc/testsuite/gcc.dg/vect/pr51301.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/pr51301.c	2011-11-30 17:54:51 +0000
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++
++typedef signed char int8_t;
++typedef signed long long int64_t;
++int64_t
++f0a (int8_t * __restrict__ arg1)
++{
++  int idx;
++  int64_t result = 0;
++  for (idx = 0; idx < 416; idx += 1)
++    result += arg1[idx] << (arg1[idx] == arg1[idx]);
++  return result;
++}
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2011-11-27 12:17:31 +0000
++++ new/gcc/tree-vect-patterns.c	2011-12-20 07:47:44 +0000
+@@ -1138,6 +1138,7 @@
+   struct loop *loop = NULL;
+   bb_vec_info bb_vinfo;
+   stmt_vec_info stmt_vinfo;
++  tree type = NULL;
+ 
+   stmt_vinfo = vinfo_for_stmt (stmt);
+   loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
+@@ -1207,6 +1208,7 @@
+           print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
+         }
+ 
++      type = gimple_expr_type (stmt);
+       prev_stmt = stmt;
+       stmt = use_stmt;
+ 
+@@ -1222,9 +1224,11 @@
+     {
+       use_lhs = gimple_assign_lhs (use_stmt);
+       use_type = TREE_TYPE (use_lhs);
+-      /* Support only type promotion or signedess change.  */
++      /* Support only type promotion or signedess change.  Check that USE_TYPE
++        is not bigger than the original type.  */
+       if (!INTEGRAL_TYPE_P (use_type)
+-          || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
++          || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type)
++         || TYPE_PRECISION (type) < TYPE_PRECISION (use_type))
+         return NULL;
+ 
+       if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch
new file mode 100644
index 0000000000..c433fc73f1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch
@@ -0,0 +1,22 @@
+2012-01-05  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r182271:
+
+	2011-12-13  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	* modulo-sched.c (mark_loop_unsched): Free bbs.
+
+=== modified file 'gcc/modulo-sched.c'
+--- old/gcc/modulo-sched.c	2011-10-30 05:31:00 +0000
++++ new/gcc/modulo-sched.c	2012-01-05 02:45:23 +0000
+@@ -1204,6 +1204,8 @@
+ 
+   for (i = 0; i < loop->num_nodes; i++)
+     bbs[i]->flags |= BB_DISABLE_SCHEDULE;
++
++  free (bbs);
+ }
+ 
+ /* Return true if all the BBs of the loop are empty except the
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch
new file mode 100644
index 0000000000..895d6a6cff
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch
@@ -0,0 +1,104 @@
+2012-01-12  Ulrich Weigand  <ulrich.weigand@linaro.org>
+
+	LP 879725
+	Backport from mainline:
+
+	2012-01-02  Revital Eres  <revital.eres@linaro.org>
+
+	gcc/
+	* ddg.c (def_has_ccmode_p): New function.
+	(add_cross_iteration_register_deps,
+	create_ddg_dep_from_intra_loop_link): Call it.
+
+	gcc/testsuite/
+	* gcc.dg/sms-11.c: New file.
+
+=== modified file 'gcc/ddg.c'
+--- old/gcc/ddg.c	2011-10-02 06:56:53 +0000
++++ new/gcc/ddg.c	2012-01-10 16:05:14 +0000
+@@ -166,6 +166,24 @@
+   return false;
+ }
+ 
++/* Return true if one of the definitions in INSN has MODE_CC.  Otherwise
++   return false.  */
++static bool
++def_has_ccmode_p (rtx insn)
++{
++  df_ref *def;
++
++  for (def = DF_INSN_DEFS (insn); *def; def++)
++    {
++      enum machine_mode mode = GET_MODE (DF_REF_REG (*def));
++
++      if (GET_MODE_CLASS (mode) == MODE_CC)
++	return true;
++    }
++
++  return false;
++}
++
+ /* Computes the dependence parameters (latency, distance etc.), creates
+    a ddg_edge and adds it to the given DDG.  */
+ static void
+@@ -202,6 +220,7 @@
+      whose register has multiple defs in the loop.  */
+   if (flag_modulo_sched_allow_regmoves 
+       && (t == ANTI_DEP && dt == REG_DEP)
++      && !def_has_ccmode_p (dest_node->insn)
+       && !autoinc_var_is_used_p (dest_node->insn, src_node->insn))
+     {
+       rtx set;
+@@ -335,7 +354,8 @@
+           if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
+               || !flag_modulo_sched_allow_regmoves
+ 	      || JUMP_P (use_node->insn)
+-              || autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn))
++              || autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn)
++	      || def_has_ccmode_p (DF_REF_INSN (last_def)))
+             create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
+                                     REG_DEP, 1);
+ 
+
+=== added file 'gcc/testsuite/gcc.dg/sms-11.c'
+--- old/gcc/testsuite/gcc.dg/sms-11.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/sms-11.c	2012-01-10 16:05:14 +0000
+@@ -0,0 +1,37 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fmodulo-sched -fmodulo-sched-allow-regmoves -fdump-rtl-sms" } */
++
++extern void abort (void);
++
++float out[4][4] = { 6, 6, 7, 5, 6, 7, 5, 5, 6, 4, 4, 4, 6, 2, 3, 4 };
++
++void
++invert (void)
++{
++  int i, j, k = 0, swap;
++  float tmp[4][4] = { 5, 6, 7, 5, 6, 7, 5, 5, 4, 4, 4, 4, 3, 2, 3, 4 };
++
++  for (i = 0; i < 4; i++)
++    {
++      for (j = i + 1; j < 4; j++)
++	if (tmp[j][i] > tmp[i][i])
++	  swap = j;
++
++      if (swap != i)
++	tmp[i][k] = tmp[swap][k];
++    }
++
++  for (i = 0; i < 4; i++)
++    for (j = 0; j < 4; j++)
++      if (tmp[i][j] != out[i][j])
++	abort ();
++}
++
++int
++main ()
++{
++  invert ();
++  return 0;
++}
++
++/* { dg-final { cleanup-rtl-dump "sms" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch
new file mode 100644
index 0000000000..0199f7b89b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch
@@ -0,0 +1,76 @@
+2012-01-18  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r183126:
+
+	2012-01-12  Ira Rosen  <irar@il.ibm.com>
+
+	gcc/
+	PR tree-optimization/51799
+	* tree-vect-patterns.c (vect_recog_over_widening_pattern): Check
+	that the last operation is a type demotion.
+
+	gcc/testsuite/
+	* gcc.dg/vect/pr51799.c: New test.
+	* gcc.dg/vect/vect-widen-shift-u8.c: Expect two widening shift
+	patterns.
+
+=== added file 'gcc/testsuite/gcc.dg/vect/pr51799.c'
+--- old/gcc/testsuite/gcc.dg/vect/pr51799.c	1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/vect/pr51799.c	2012-01-18 01:53:19 +0000
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++
++typedef signed char int8_t;
++typedef unsigned char uint8_t;
++typedef signed short int16_t;
++typedef unsigned long uint32_t;
++void
++f0a (uint32_t * __restrict__ result, int8_t * __restrict__ arg1,
++     uint32_t * __restrict__ arg4, int8_t temp_6)
++{
++  int idx;
++  for (idx = 0; idx < 416; idx += 1)
++    {
++      result[idx] = (uint8_t)(((arg1[idx] << 7) + arg4[idx]) * temp_6);
++    }
++}
++
++/* { dg-final { cleanup-tree-dump "vect" } } */
+
+=== modified file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c'
+--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c	2011-10-23 13:33:07 +0000
++++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c	2012-01-18 01:53:19 +0000
+@@ -59,7 +59,6 @@
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
++/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 2 "vect" { target vect_widen_shift } } } */
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+ /* { dg-final { cleanup-tree-dump "vect" } } */
+-
+
+=== modified file 'gcc/tree-vect-patterns.c'
+--- old/gcc/tree-vect-patterns.c	2011-12-20 07:47:44 +0000
++++ new/gcc/tree-vect-patterns.c	2012-01-18 01:53:19 +0000
+@@ -1224,13 +1224,15 @@
+     {
+       use_lhs = gimple_assign_lhs (use_stmt);
+       use_type = TREE_TYPE (use_lhs);
+-      /* Support only type promotion or signedess change.  Check that USE_TYPE
+-        is not bigger than the original type.  */
++      /* Support only type demotion or signedess change.  */
+       if (!INTEGRAL_TYPE_P (use_type)
+-          || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type)
+-         || TYPE_PRECISION (type) < TYPE_PRECISION (use_type))
++	  || TYPE_PRECISION (type) <= TYPE_PRECISION (use_type))
+         return NULL;
+ 
++      /* Check that NEW_TYPE is not bigger than the conversion result.  */
++      if (TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
++	return NULL;
++
+       if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
+           || TYPE_PRECISION (new_type) != TYPE_PRECISION (use_type))
+         {
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch
new file mode 100644
index 0000000000..a20d889a56
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch
@@ -0,0 +1,45 @@
+2012-01-16  Michael Hope  <michael.hope@linaro.org>
+
+	Backport from mainline r183011:
+
+	2012-01-09  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* config/arm/arm-cores.def (cortex-a15): Use cortex_a15_tune for
+	tuning parameters.
+	* config/arm/arm.c (arm_cortex_a15_tune): New static variable.
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2011-10-19 16:46:51 +0000
++++ new/gcc/config/arm/arm-cores.def	2012-01-15 22:02:31 +0000
+@@ -128,7 +128,7 @@
+ ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
+ ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
+-ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
++ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
+ ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-r5",	  cortexr5,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2012-01-05 15:35:39 +0000
++++ new/gcc/config/arm/arm.c	2012-01-15 22:02:31 +0000
+@@ -983,6 +983,17 @@
+   arm_default_branch_cost
+ };
+ 
++const struct tune_params arm_cortex_a15_tune =
++{
++  arm_9e_rtx_costs,
++  NULL,
++  1,						/* Constant limit.  */
++  1,						/* Max cond insns.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,			/* TODO: Calculate correct values.  */
++  false,					/* Prefer constant pool.  */
++  arm_cortex_a5_branch_cost
++};
++
+ const struct tune_params arm_fa726te_tune =
+ {
+   arm_9e_rtx_costs,
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch
new file mode 100644
index 0000000000..e93493f17f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch
@@ -0,0 +1,47 @@
+ 2012-01-16  Michael Hope  <michael.hope@linaro.org>
+ 
+	Backport from mainline r182561:
+
+	2011-12-20  Richard Henderson  <rth@redhat.com>
+
+	gcc/
+	* config/arm/arm.md (*arm_cmpdi_unsigned): Enable for thumb2.
+	* config/arm/arm.c (arm_select_cc_mode): Use it.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2012-01-15 22:02:31 +0000
++++ new/gcc/config/arm/arm.c	2012-01-23 00:06:27 +0000
+@@ -11602,7 +11602,7 @@
+ 	    return CC_Zmode;
+ 
+ 	  /* We can do an equality test in three Thumb instructions.  */
+-	  if (!TARGET_ARM)
++	  if (!TARGET_32BIT)
+ 	    return CC_Zmode;
+ 
+ 	  /* FALLTHROUGH */
+@@ -11614,7 +11614,7 @@
+ 	  /* DImode unsigned comparisons can be implemented by cmp +
+ 	     cmpeq without a scratch register.  Not worth doing in
+ 	     Thumb-2.  */
+-	  if (TARGET_ARM)
++	  if (TARGET_32BIT)
+ 	    return CC_CZmode;
+ 
+ 	  /* FALLTHROUGH */
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2012-01-05 15:35:39 +0000
++++ new/gcc/config/arm/arm.md	2012-01-15 21:02:00 +0000
+@@ -7515,8 +7515,8 @@
+   [(set (reg:CC_CZ CC_REGNUM)
+ 	(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
+ 		       (match_operand:DI 1 "arm_di_operand"	"rDi")))]
+-  "TARGET_ARM"
+-  "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1"
++  "TARGET_32BIT"
++  "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
+   [(set_attr "conds" "set")
+    (set_attr "length" "8")]
+ )
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch
new file mode 100644
index 0000000000..f15f37a583
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch
@@ -0,0 +1,63 @@
+ 2012-01-16  Michael Hope  <michael.hope@linaro.org>
+ 
+	Backport from mainline r181210:
+
+	gcc/
+	2011-11-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* config/arm/arm-cores.def: Add -mcpu=cortex-a7.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Likewise.
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex A-7.
+	* doc/invoke.texi: Document -mcpu=cortex-a7.
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2012-01-15 22:02:31 +0000
++++ new/gcc/config/arm/arm-cores.def	2012-01-23 00:36:02 +0000
+@@ -126,6 +126,7 @@
+ ARM_CORE("arm1156t2f-s",  arm1156t2fs,  6T2,				 FL_LDSCHED | FL_VFPV2, v6t2)
+ ARM_CORE("generic-armv7-a", genericv7a,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
++ARM_CORE("cortex-a7",	  cortexa7,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
+ ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
+ ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
+
+=== modified file 'gcc/config/arm/arm-tune.md'
+--- old/gcc/config/arm/arm-tune.md	2011-10-19 16:46:51 +0000
++++ new/gcc/config/arm/arm-tune.md	2012-01-15 22:43:29 +0000
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from arm-cores.def
+ (define_attr "tune"
+-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
++	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+
+=== modified file 'gcc/config/arm/bpabi.h'
+--- old/gcc/config/arm/bpabi.h	2011-11-02 21:02:53 +0000
++++ new/gcc/config/arm/bpabi.h	2012-01-15 22:43:29 +0000
+@@ -56,6 +56,7 @@
+   "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
+ 
+ #define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5"\
++  "|mcpu=cortex-a7"\
+   "|mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15|mcpu=generic-armv7-a"\
+   ":%{!r:--be8}}}"
+ 
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi	2012-01-05 15:35:39 +0000
++++ new/gcc/doc/invoke.texi	2012-01-15 22:43:29 +0000
+@@ -10202,8 +10202,8 @@
+ @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
+ @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
+ @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
+-@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
+-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
++@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, 
++@samp{cortex-a15}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
+ @samp{cortex-m4}, @samp{cortex-m3},
+ @samp{cortex-m1},
+ @samp{cortex-m0},
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch
new file mode 100644
index 0000000000..5b0735b004
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch
@@ -0,0 +1,25 @@
+2012-01-20  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline
+        2012-01-20  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/51819
+	* config/arm/arm.c (arm_print_operand): Correct output of alignment
+	hints for neon loads and stores.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2012-01-23 00:06:27 +0000
++++ new/gcc/config/arm/arm.c	2012-01-23 18:54:21 +0000
+@@ -17463,9 +17463,9 @@
+ 	/* Only certain alignment specifiers are supported by the hardware.  */
+ 	if (memsize == 16 && (align % 32) == 0)
+ 	  align_bits = 256;
+-	else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
++	else if (memsize == 16 && (align % 16) == 0)
+ 	  align_bits = 128;
+-	else if ((align % 8) == 0)
++	else if (memsize >= 8 && (align % 8) == 0)
+ 	  align_bits = 64;
+ 	else
+ 	  align_bits = 0;
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch
new file mode 100644
index 0000000000..de3d2ff4cf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch
@@ -0,0 +1,2389 @@
+2012-02-08  Ulrich Weigand  <ulrich.weigand@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (arm_option_optimization_table): Enable
+	-fsched-pressure using -fsched-pressure-algorithm=model by
+	default when optimizing.
+
+2012-02-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* sched-deps.c (fixup_sched_groups): Rename to...
+	(chain_to_prev_insn): ...this.
+	(chain_to_prev_insn_p): New function.
+	(deps_analyze_insn): Use it instead of SCHED_GROUP_P.
+
+2012-02-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* sched-int.h (_haifa_insn_data): Move priority_status.
+	Add model_index.
+	(INSN_MODEL_INDEX): New macro.
+	* haifa-sched.c (insn_delay): New function.
+	(sched_regno_pressure_class): Update commentary.
+	(mark_regno_birth_or_death): Pass the liveness bitmap and
+	pressure array as arguments, instead of using curr_reg_live and
+	curr_reg_pressure.  Only update the pressure if the bit in the
+	liveness set has changed.
+	(initiate_reg_pressure_info): Always trust the live-in set for
+	SCHED_PRESSURE_MODEL.
+	(initiate_bb_reg_pressure_info): Update call to
+	mark_regno_birth_or_death.
+	(dep_list_size): Take the list as argument.
+	(calculate_reg_deaths): New function, extracted from...
+	(setup_insn_reg_pressure_info): ...here.
+	(MODEL_BAR): New macro.
+	(model_pressure_data, model_insn_info, model_pressure_limit)
+	(model_pressure_group): New structures.
+	(model_schedule, model_worklist, model_insns, model_num_insns)
+	(model_curr_point, model_before_pressure, model_next_priority):
+	New variables.
+	(MODEL_PRESSURE_DATA, MODEL_MAX_PRESSURE, MODEL_REF_PRESSURE)
+	(MODEL_INSN_INFO, MODEL_INSN): New macros.
+	(model_index, model_update_limit_points_in_group): New functions.
+	(model_update_limit_points, model_last_use_except): Likewise.
+	(model_start_update_pressure, model_update_pressure): Likewise.
+	(model_recompute, model_spill_cost, model_excess_group_cost): Likewise.
+	(model_excess_cost, model_dump_pressure_points): Likewise.
+	(model_set_excess_costs): Likewise.
+	(rank_for_schedule): Extend SCHED_PRIORITY_WEIGHTED ordering to
+	SCHED_PRIORITY_MODEL.  Use insn_delay.  Use the order in the model
+	schedule as an alternative tie-breaker.  Update the call to
+	dep_list_size.
+	(ready_sort): Call model_set_excess_costs.
+	(update_register_pressure): Update call to mark_regno_birth_or_death.
+	Rely on that function to check liveness rather than doing it here.
+	(model_classify_pressure, model_order_p, model_add_to_worklist_at)
+	(model_remove_from_worklist, model_add_to_worklist, model_promote_insn)
+	(model_add_to_schedule, model_analyze_insns, model_init_pressure_group)
+	(model_record_pressure, model_record_pressures): New functions.
+	(model_record_final_pressures, model_add_successors_to_worklist)
+	(model_promote_predecessors, model_choose_insn): Likewise.
+	(model_reset_queue_indices, model_dump_pressure_summary): Likewise.
+	(model_start_schedule, model_finalize_pressure_group): Likewise.
+	(model_end_schedule): Likewise.
+	(schedule_insn): Say when we're scheduling the next instruction
+	in the model schedule.
+	(schedule_insn): Handle SCHED_PRESSURE_MODEL.
+	(queue_to_ready): Do not add instructions that are
+	MAX_SCHED_READY_INSNS beyond the current point of the model schedule.
+	Always allow the next instruction in the model schedule to be added.
+	(debug_ready_list): Print the INSN_REG_PRESSURE_EXCESS_COST_CHANGE
+	and delay for SCHED_PRESSURE_MODEL too.
+	(prune_ready_list): Extend SCHED_PRIORITY_WEIGHTED handling to
+	SCHED_PRIORITY_MODEL, but also take the DFA into account.
+	(schedule_block): Call model_start_schedule and model_end_schedule.
+	Extend SCHED_PRIORITY_WEIGHTED stall handling to SCHED_PRIORITY_MODEL.
+	(sched_init): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE handling
+	to SCHED_PRESSURE_MODEL, but don't allocate saved_reg_live or
+	region_ref_regs.
+	(sched_finish): Update accordingly.
+	(fix_tick_ready): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE handling
+	to SCHED_PRESSURE_MODEL.
+	(add_jump_dependencies): Update call to dep_list_size.
+	(haifa_finish_h_i_d): Fix leak of max_reg_pressure.
+	(haifa_init_insn): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE handling
+	to SCHED_PRESSURE_MODEL.
+	* sched-deps.c (init_insn_reg_pressure_info): Likewise, but don't
+	allocate INSN_MAX_REG_PRESSURE for SCHED_PRESSURE_MODEL.
+	(sched_analyze_insn): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE
+	handling to SCHED_PRESSURE_MODEL.
+
+2012-02-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	* common.opt (fsched-pressure-algorithm=): New option.
+	* flag-types.h (sched_pressure_algorithm): New enum.
+	* sched-int.h (sched_pressure_p): Replace with...
+	(sched_pressure): ...this new variable.
+	* haifa-sched.c (sched_pressure_p): Replace with...
+	(sched_pressure): ...this new variable.
+	(sched_regno_pressure_class, rank_for_schedule, ready_sort)
+	(update_reg_and_insn_max_reg_pressure, schedule_insn)
+	(debug_ready_list, schedule_block, sched_init, sched_finish)
+	(fix_tick_ready, haifa_init_insn): Update accordingly.
+	* sched-deps.c (init_insn_reg_pressure_info): Likewise.
+	* sched-rgn.c (schedule_region): Likewise.
+
+2012-02-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	gcc/
+	Backport from mainline:
+
+	2011-04-01  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* haifa-sched.c (prune_ready_list): New function, broken out of
+	schedule_block.
+	(schedule_block): Use it.
+
+=== modified file 'gcc/common.opt'
+--- old/gcc/common.opt	2011-04-11 15:26:47 +0000
++++ new/gcc/common.opt	2012-02-08 23:38:13 +0000
+@@ -1614,6 +1614,19 @@
+ Common Report Var(flag_sched_pressure) Init(0) Optimization
+ Enable register pressure sensitive insn scheduling
+ 
++fsched-pressure-algorithm=
++Common Joined RejectNegative Enum(sched_pressure_algorithm) Var(flag_sched_pressure_algorithm) Init(SCHED_PRESSURE_WEIGHTED)
++-fira-algorithm=[CB|priority] Set the used IRA algorithm
++
++Enum
++Name(sched_pressure_algorithm) Type(enum sched_pressure_algorithm) UnknownError(unknown %<fsched-pressure%> algorithm %qs)
++
++EnumValue
++Enum(sched_pressure_algorithm) String(weighted) Value(SCHED_PRESSURE_WEIGHTED)
++
++EnumValue
++Enum(sched_pressure_algorithm) String(model) Value(SCHED_PRESSURE_MODEL)
++
+ fsched-spec
+ Common Report Var(flag_schedule_speculative) Init(1) Optimization
+ Allow speculative motion of non-loads
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2012-02-01 14:13:07 +0000
++++ new/gcc/config/arm/arm.c	2012-02-09 00:47:59 +0000
+@@ -311,6 +311,11 @@
+ /* Set default optimization options.  */
+ static const struct default_options arm_option_optimization_table[] =
+   {
++    /* Enable -fsched-pressure using -fsched-pressure-algorithm=model
++       by default when optimizing.  */
++    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
++    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure_algorithm_,
++      NULL, SCHED_PRESSURE_MODEL },
+     /* Enable section anchors by default at -O1 or higher.  */
+     { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+     { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+
+=== modified file 'gcc/flag-types.h'
+--- old/gcc/flag-types.h	2010-11-24 13:28:38 +0000
++++ new/gcc/flag-types.h	2012-02-08 23:38:13 +0000
+@@ -106,6 +106,14 @@
+ };
+ #endif
+ 
++/* The algorithm used to implement -fsched-pressure.  */
++enum sched_pressure_algorithm
++{
++  SCHED_PRESSURE_NONE,
++  SCHED_PRESSURE_WEIGHTED,
++  SCHED_PRESSURE_MODEL
++};
++
+ /* The algorithm used for the integrated register allocator (IRA).  */
+ enum ira_algorithm
+ {
+
+=== modified file 'gcc/haifa-sched.c'
+--- old/gcc/haifa-sched.c	2011-02-19 20:59:23 +0000
++++ new/gcc/haifa-sched.c	2012-02-08 23:39:02 +0000
+@@ -348,6 +348,14 @@
+ /* Create empty basic block after the specified block.  */
+ basic_block (* sched_create_empty_bb) (basic_block);
+ 
++/* Return the number of cycles until INSN is expected to be ready.
++   Return zero if it already is.  */
++static int
++insn_delay (rtx insn)
++{
++  return MAX (INSN_TICK (insn) - clock_var, 0);
++}
++
+ static int
+ may_trap_exp (const_rtx x, int is_store)
+ {
+@@ -571,10 +579,10 @@
+ 
+ /* Do register pressure sensitive insn scheduling if the flag is set
+    up.  */
+-bool sched_pressure_p;
++enum sched_pressure_algorithm sched_pressure;
+ 
+ /* Map regno -> its cover class.  The map defined only when
+-   SCHED_PRESSURE_P is true.  */
++   SCHED_PRESSURE != SCHED_PRESSURE_NONE.  */
+ enum reg_class *sched_regno_cover_class;
+ 
+ /* The current register pressure.  Only elements corresponding cover
+@@ -602,10 +610,12 @@
+   bitmap_clear (region_ref_regs);
+ }
+ 
+-/* Update current register pressure related info after birth (if
+-   BIRTH_P) or death of register REGNO.  */
+-static void
+-mark_regno_birth_or_death (int regno, bool birth_p)
++/* PRESSURE[CL] describes the pressure on register class CL.  Update it
++   for the birth (if BIRTH_P) or death (if !BIRTH_P) of register REGNO.
++   LIVE tracks the set of live registers; if it is null, assume that
++   every birth or death is genuine.  */
++static inline void
++mark_regno_birth_or_death (bitmap live, int *pressure, int regno, bool birth_p)
+ {
+   enum reg_class cover_class;
+ 
+@@ -616,15 +626,17 @@
+ 	{
+ 	  if (birth_p)
+ 	    {
+-	      bitmap_set_bit (curr_reg_live, regno);
+-	      curr_reg_pressure[cover_class]
+-		+= ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
++	      if (!live || bitmap_set_bit (live, regno))
++		pressure[cover_class]
++		  += (ira_reg_class_nregs
++		      [cover_class][PSEUDO_REGNO_MODE (regno)]);
+ 	    }
+ 	  else
+ 	    {
+-	      bitmap_clear_bit (curr_reg_live, regno);
+-	      curr_reg_pressure[cover_class]
+-		-= ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
++	      if (!live || bitmap_clear_bit (live, regno))
++		pressure[cover_class]
++		  -= (ira_reg_class_nregs
++		      [cover_class][PSEUDO_REGNO_MODE (regno)]);
+ 	    }
+ 	}
+     }
+@@ -633,13 +645,13 @@
+     {
+       if (birth_p)
+ 	{
+-	  bitmap_set_bit (curr_reg_live, regno);
+-	  curr_reg_pressure[cover_class]++;
++	  if (!live || bitmap_set_bit (live, regno))
++	    pressure[cover_class]++;
+ 	}
+       else
+ 	{
+-	  bitmap_clear_bit (curr_reg_live, regno);
+-	  curr_reg_pressure[cover_class]--;
++	  if (!live || bitmap_clear_bit (live, regno))
++	    pressure[cover_class]--;
+ 	}
+     }
+ }
+@@ -657,8 +669,10 @@
+     curr_reg_pressure[ira_reg_class_cover[i]] = 0;
+   bitmap_clear (curr_reg_live);
+   EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi)
+-    if (current_nr_blocks == 1 || bitmap_bit_p (region_ref_regs, j))
+-      mark_regno_birth_or_death (j, true);
++    if (sched_pressure == SCHED_PRESSURE_MODEL
++	|| current_nr_blocks == 1
++	|| bitmap_bit_p (region_ref_regs, j))
++      mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, j, true);
+ }
+ 
+ /* Mark registers in X as mentioned in the current region.  */
+@@ -712,7 +726,8 @@
+ 	if (regno == INVALID_REGNUM)
+ 	  break;
+ 	if (! bitmap_bit_p (df_get_live_in (bb), regno))
+-	  mark_regno_birth_or_death (regno, true);
++	  mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
++				     regno, true);
+       }
+ #endif
+ }
+@@ -956,19 +971,19 @@
+   return true;
+ }
+ 
+-/* Compute the number of nondebug forward deps of an insn.  */
++/* Compute the number of nondebug deps in list LIST for INSN.  */
+ 
+ static int
+-dep_list_size (rtx insn)
++dep_list_size (rtx insn, sd_list_types_def list)
+ {
+   sd_iterator_def sd_it;
+   dep_t dep;
+   int dbgcount = 0, nodbgcount = 0;
+ 
+   if (!MAY_HAVE_DEBUG_INSNS)
+-    return sd_lists_size (insn, SD_LIST_FORW);
++    return sd_lists_size (insn, list);
+ 
+-  FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
++  FOR_EACH_DEP (insn, list, sd_it, dep)
+     {
+       if (DEBUG_INSN_P (DEP_CON (dep)))
+ 	dbgcount++;
+@@ -976,7 +991,7 @@
+ 	nodbgcount++;
+     }
+ 
+-  gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, SD_LIST_FORW));
++  gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, list));
+ 
+   return nodbgcount;
+ }
+@@ -995,7 +1010,7 @@
+     {
+       int this_priority = -1;
+ 
+-      if (dep_list_size (insn) == 0)
++      if (dep_list_size (insn, SD_LIST_FORW) == 0)
+ 	/* ??? We should set INSN_PRIORITY to insn_cost when and insn has
+ 	   some forward deps but all of them are ignored by
+ 	   contributes_to_priority hook.  At the moment we set priority of
+@@ -1091,6 +1106,22 @@
+          qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); }  \
+ while (0)
+ 
++/* For each cover class CL, set DEATH[CL] to the number of registers
++   in that class that die in INSN.  */
++
++static void
++calculate_reg_deaths (rtx insn, int *death)
++{
++  int i;
++  struct reg_use_data *use;
++
++  for (i = 0; i < ira_reg_class_cover_size; i++)
++    death[ira_reg_class_cover[i]] = 0;
++  for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
++    if (dying_use_p (use))
++      mark_regno_birth_or_death (0, death, use->regno, true);
++}
++
+ /* Setup info about the current register pressure impact of scheduling
+    INSN at the current scheduling point.  */
+ static void
+@@ -1102,23 +1133,12 @@
+   enum reg_class cl;
+   struct reg_pressure_data *pressure_info;
+   int *max_reg_pressure;
+-  struct reg_use_data *use;
+   static int death[N_REG_CLASSES];
+ 
+   gcc_checking_assert (!DEBUG_INSN_P (insn));
+ 
+   excess_cost_change = 0;
+-  for (i = 0; i < ira_reg_class_cover_size; i++)
+-    death[ira_reg_class_cover[i]] = 0;
+-  for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
+-    if (dying_use_p (use))
+-      {
+-	cl = sched_regno_cover_class[use->regno];
+-	if (use->regno < FIRST_PSEUDO_REGISTER)
+-	  death[cl]++;
+-	else
+-	  death[cl] += ira_reg_class_nregs[cl][PSEUDO_REGNO_MODE (use->regno)];
+-      }
++  calculate_reg_deaths (insn, death);
+   pressure_info = INSN_REG_PRESSURE (insn);
+   max_reg_pressure = INSN_MAX_REG_PRESSURE (insn);
+   gcc_assert (pressure_info != NULL && max_reg_pressure != NULL);
+@@ -1139,7 +1159,765 @@
+     }
+   INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insn) = excess_cost_change;
+ }
+-
++
++/* This is the first page of code related to SCHED_PRESSURE_MODEL.
++   It tries to make the scheduler take register pressure into account
++   without introducing too many unnecessary stalls.  It hooks into the
++   main scheduling algorithm at several points:
++
++    - Before scheduling starts, model_start_schedule constructs a
++      "model schedule" for the current block.  This model schedule is
++      chosen solely to keep register pressure down.  It does not take the
++      target's pipeline or the original instruction order into account,
++      except as a tie-breaker.  It also doesn't work to a particular
++      pressure limit.
++
++      This model schedule gives us an idea of what pressure can be
++      achieved for the block gives us an example of a schedule that
++      keeps to that pressure.  It also makes the final schedule less
++      dependent on the original instruction order.  This is important
++      because the original order can either be "wide" (many values live
++      at once, such as in user-scheduled code) or "narrow" (few values
++      live at once, such as after loop unrolling, where several
++      iterations are executed sequentially).
++
++      We do not apply this model schedule to the rtx stream.  We simply
++      record it in model_schedule.  We also compute the maximum pressure,
++      MP, that was seen during this schedule.
++
++    - Instructions are added to the ready queue even if they require
++      a stall.  The length of the stall is instead computed as:
++
++	 MAX (INSN_TICK (INSN) - clock_var, 0)
++
++      (= insn_delay).  This allows rank_for_schedule to choose between
++      introducing a deliberate stall or increasing pressure.
++
++    - Before sorting the ready queue, model_set_excess_costs assigns
++      a pressure-based cost to each ready instruction in the queue.
++      This is the instruction's INSN_REG_PRESSURE_EXCESS_COST_CHANGE
++      (ECC for short) and is effectively measured in cycles.
++
++    - rank_for_schedule ranks instructions based on:
++
++	ECC (insn) + insn_delay (insn)
++
++      then as:
++
++	insn_delay (insn)
++
++      So, for example, an instruction X1 with an ECC of 1 that can issue
++      now will win over an instruction X0 with an ECC of zero that would
++      introduce a stall of one cycle.  However, an instruction X2 with an
++      ECC of 2 that can issue now will lose to X0.
++
++    - When an instruction is scheduled, model_recompute updates the model
++      schedule with the new pressures (some of which might now exceed the
++      original maximum pressure MP).  model_update_limit_points then searches
++      for the new point of maximum pressure, if not already known.  */
++
++/* Used to separate high-verbosity debug information for SCHED_PRESSURE_MODEL
++   from surrounding debug information.  */
++#define MODEL_BAR \
++  ";;\t\t+------------------------------------------------------\n"
++
++/* Information about the pressure on a particular register class at a
++   particular point of the model schedule.  */
++struct model_pressure_data {
++  /* The pressure at this point of the model schedule, or -1 if the
++     point is associated with an instruction that has already been
++     scheduled.  */
++  int ref_pressure;
++
++  /* The maximum pressure during or after this point of the model schedule.  */
++  int max_pressure;
++};
++
++/* Per-instruction information that is used while building the model
++   schedule.  Here, "schedule" refers to the model schedule rather
++   than the main schedule.  */
++struct model_insn_info {
++  /* The instruction itself.  */
++  rtx insn;
++
++  /* If this instruction is in model_worklist, these fields link to the
++     previous (higher-priority) and next (lower-priority) instructions
++     in the list.  */
++  struct model_insn_info *prev;
++  struct model_insn_info *next;
++
++  /* While constructing the schedule, QUEUE_INDEX describes whether an
++     instruction has already been added to the schedule (QUEUE_SCHEDULED),
++     is in model_worklist (QUEUE_READY), or neither (QUEUE_NOWHERE).
++     old_queue records the value that QUEUE_INDEX had before scheduling
++     started, so that we can restore it once the schedule is complete.  */
++  int old_queue;
++
++  /* The relative importance of an unscheduled instruction.  Higher
++     values indicate greater importance.  */
++  unsigned int model_priority;
++
++  /* The length of the longest path of satisfied true dependencies
++     that leads to this instruction.  */
++  unsigned int depth;
++
++  /* The length of the longest path of dependencies of any kind
++     that leads from this instruction.  */
++  unsigned int alap;
++
++  /* The number of predecessor nodes that must still be scheduled.  */
++  int unscheduled_preds;
++};
++
++/* Information about the pressure limit for a particular register class.
++   This structure is used when applying a model schedule to the main
++   schedule.  */
++struct model_pressure_limit {
++  /* The maximum register pressure seen in the original model schedule.  */
++  int orig_pressure;
++
++  /* The maximum register pressure seen in the current model schedule
++     (which excludes instructions that have already been scheduled).  */
++  int pressure;
++
++  /* The point of the current model schedule at which PRESSURE is first
++     reached.  It is set to -1 if the value needs to be recomputed.  */
++  int point;
++};
++
++/* Describes a particular way of measuring register pressure.  */
++struct model_pressure_group {
++  /* Index CCI describes the maximum pressure on ira_reg_class_cover[CCI].  */
++  struct model_pressure_limit limits[N_REG_CLASSES];
++
++  /* Index (POINT * ira_num_pressure_classes + CCI) describes the pressure
++     on register class ira_reg_class_cover[CCI] at point POINT of the
++     current model schedule.  A POINT of model_num_insns describes the
++     pressure at the end of the schedule.  */
++  struct model_pressure_data *model;
++};
++
++/* Index POINT gives the instruction at point POINT of the model schedule.
++   This array doesn't change during main scheduling.  */
++static VEC (rtx, heap) *model_schedule;
++
++/* The list of instructions in the model worklist, sorted in order of
++   decreasing priority.  */
++static struct model_insn_info *model_worklist;
++
++/* Index I describes the instruction with INSN_LUID I.  */
++static struct model_insn_info *model_insns;
++
++/* The number of instructions in the model schedule.  */
++static int model_num_insns;
++
++/* The index of the first instruction in model_schedule that hasn't yet been
++   added to the main schedule, or model_num_insns if all of them have.  */
++static int model_curr_point;
++
++/* Describes the pressure before each instruction in the model schedule.  */
++static struct model_pressure_group model_before_pressure;
++
++/* The first unused model_priority value (as used in model_insn_info).  */
++static unsigned int model_next_priority;
++
++
++/* The model_pressure_data for ira_reg_class_cover[CCI] in GROUP
++   at point POINT of the model schedule.  */
++#define MODEL_PRESSURE_DATA(GROUP, POINT, CCI) \
++  (&(GROUP)->model[(POINT) * ira_reg_class_cover_size + (CCI)])
++
++/* The maximum pressure on ira_reg_class_cover[CCI] in GROUP at or
++   after point POINT of the model schedule.  */
++#define MODEL_MAX_PRESSURE(GROUP, POINT, CCI) \
++  (MODEL_PRESSURE_DATA (GROUP, POINT, CCI)->max_pressure)
++
++/* The pressure on ira_reg_class_cover[CCI] in GROUP at point POINT
++   of the model schedule.  */
++#define MODEL_REF_PRESSURE(GROUP, POINT, CCI) \
++  (MODEL_PRESSURE_DATA (GROUP, POINT, CCI)->ref_pressure)
++
++/* Information about INSN that is used when creating the model schedule.  */
++#define MODEL_INSN_INFO(INSN) \
++  (&model_insns[INSN_LUID (INSN)])
++
++/* The instruction at point POINT of the model schedule.  */
++#define MODEL_INSN(POINT) \
++  (VEC_index (rtx, model_schedule, POINT))
++
++
++/* Return INSN's index in the model schedule, or model_num_insns if it
++   doesn't belong to that schedule.  */
++
++static int
++model_index (rtx insn)
++{
++  if (INSN_MODEL_INDEX (insn) == 0)
++    return model_num_insns;
++  return INSN_MODEL_INDEX (insn) - 1;
++}
++
++/* Make sure that GROUP->limits is up-to-date for the current point
++   of the model schedule.  */
++
++static void
++model_update_limit_points_in_group (struct model_pressure_group *group)
++{
++  int cci, max_pressure, point;
++
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      /* We may have passed the final point at which the pressure in
++	 group->limits[cci].pressure was reached.  Update the limit if so.  */
++      max_pressure = MODEL_MAX_PRESSURE (group, model_curr_point, cci);
++      group->limits[cci].pressure = max_pressure;
++
++      /* Find the point at which MAX_PRESSURE is first reached.  We need
++	 to search in three cases:
++
++	 - We've already moved past the previous pressure point.
++	   In this case we search forward from model_curr_point.
++
++	 - We scheduled the previous point of maximum pressure ahead of
++	   its position in the model schedule, but doing so didn't bring
++	   the pressure point earlier.  In this case we search forward
++	   from that previous pressure point.
++
++	 - Scheduling an instruction early caused the maximum pressure
++	   to decrease.  In this case we will have set the pressure
++	   point to -1, and we search forward from model_curr_point.  */
++      point = MAX (group->limits[cci].point, model_curr_point);
++      while (point < model_num_insns
++	     && MODEL_REF_PRESSURE (group, point, cci) < max_pressure)
++	point++;
++      group->limits[cci].point = point;
++
++      gcc_assert (MODEL_REF_PRESSURE (group, point, cci) == max_pressure);
++      gcc_assert (MODEL_MAX_PRESSURE (group, point, cci) == max_pressure);
++    }
++}
++
++/* Make sure that all register-pressure limits are up-to-date for the
++   current position in the model schedule.  */
++
++static void
++model_update_limit_points (void)
++{
++  model_update_limit_points_in_group (&model_before_pressure);
++}
++
++/* Return the model_index of the last unscheduled use in chain USE
++   outside of USE's instruction.  Return -1 if there are no other uses,
++   or model_num_insns if the register is live at the end of the block.  */
++
++static int
++model_last_use_except (struct reg_use_data *use)
++{
++  struct reg_use_data *next;
++  int last, index;
++
++  last = -1;
++  for (next = use->next_regno_use; next != use; next = next->next_regno_use)
++    if (NONDEBUG_INSN_P (next->insn)
++	&& QUEUE_INDEX (next->insn) != QUEUE_SCHEDULED)
++      {
++	index = model_index (next->insn);
++	if (index == model_num_insns)
++	  return model_num_insns;
++	if (last < index)
++	  last = index;
++      }
++  return last;
++}
++
++/* An instruction with model_index POINT has just been scheduled, and it
++   adds DELTA to the pressure on ira_reg_class_cover[CCI] after POINT - 1.
++   Update MODEL_REF_PRESSURE (GROUP, POINT, CCI) and
++   MODEL_MAX_PRESSURE (GROUP, POINT, CCI) accordingly.  */
++
++static void
++model_start_update_pressure (struct model_pressure_group *group,
++			     int point, int cci, int delta)
++{
++  int next_max_pressure;
++
++  if (point == model_num_insns)
++    {
++      /* The instruction wasn't part of the model schedule; it was moved
++	 from a different block.  Update the pressure for the end of
++	 the model schedule.  */
++      MODEL_REF_PRESSURE (group, point, cci) += delta;
++      MODEL_MAX_PRESSURE (group, point, cci) += delta;
++    }
++  else
++    {
++      /* Record that this instruction has been scheduled.  Nothing now
++	 changes between POINT and POINT + 1, so get the maximum pressure
++	 from the latter.  If the maximum pressure decreases, the new
++	 pressure point may be before POINT.  */
++      MODEL_REF_PRESSURE (group, point, cci) = -1;
++      next_max_pressure = MODEL_MAX_PRESSURE (group, point + 1, cci);
++      if (MODEL_MAX_PRESSURE (group, point, cci) > next_max_pressure)
++	{
++	  MODEL_MAX_PRESSURE (group, point, cci) = next_max_pressure;
++	  if (group->limits[cci].point == point)
++	    group->limits[cci].point = -1;
++	}
++    }
++}
++
++/* Record that scheduling a later instruction has changed the pressure
++   at point POINT of the model schedule by DELTA (which might be 0).
++   Update GROUP accordingly.  Return nonzero if these changes might
++   trigger changes to previous points as well.  */
++
++static int
++model_update_pressure (struct model_pressure_group *group,
++		       int point, int cci, int delta)
++{
++  int ref_pressure, max_pressure, next_max_pressure;
++
++  /* If POINT hasn't yet been scheduled, update its pressure.  */
++  ref_pressure = MODEL_REF_PRESSURE (group, point, cci);
++  if (ref_pressure >= 0 && delta != 0)
++    {
++      ref_pressure += delta;
++      MODEL_REF_PRESSURE (group, point, cci) = ref_pressure;
++
++      /* Check whether the maximum pressure in the overall schedule
++	 has increased.  (This means that the MODEL_MAX_PRESSURE of
++	 every point <= POINT will need to increae too; see below.)  */
++      if (group->limits[cci].pressure < ref_pressure)
++	group->limits[cci].pressure = ref_pressure;
++
++      /* If we are at maximum pressure, and the maximum pressure
++	 point was previously unknown or later than POINT,
++	 bring it forward.  */
++      if (group->limits[cci].pressure == ref_pressure
++	  && !IN_RANGE (group->limits[cci].point, 0, point))
++	group->limits[cci].point = point;
++
++      /* If POINT used to be the point of maximum pressure, but isn't
++	 any longer, we need to recalculate it using a forward walk.  */
++      if (group->limits[cci].pressure > ref_pressure
++	  && group->limits[cci].point == point)
++	group->limits[cci].point = -1;
++    }
++
++  /* Update the maximum pressure at POINT.  Changes here might also
++     affect the maximum pressure at POINT - 1.  */
++  next_max_pressure = MODEL_MAX_PRESSURE (group, point + 1, cci);
++  max_pressure = MAX (ref_pressure, next_max_pressure);
++  if (MODEL_MAX_PRESSURE (group, point, cci) != max_pressure)
++    {
++      MODEL_MAX_PRESSURE (group, point, cci) = max_pressure;
++      return 1;
++    }
++  return 0;
++}
++
++/* INSN has just been scheduled.  Update the model schedule accordingly.  */
++
++static void
++model_recompute (rtx insn)
++{
++  struct {
++    int last_use;
++    int regno;
++  } uses[FIRST_PSEUDO_REGISTER + MAX_RECOG_OPERANDS];
++  struct reg_use_data *use;
++  struct reg_pressure_data *reg_pressure;
++  int delta[N_REG_CLASSES];
++  int cci, point, mix, new_last, cl, ref_pressure, queue;
++  unsigned int i, num_uses, num_pending_births;
++  bool print_p;
++
++  /* The destinations of INSN were previously live from POINT onwards, but are
++     now live from model_curr_point onwards.  Set up DELTA accordingly.  */
++  point = model_index (insn);
++  reg_pressure = INSN_REG_PRESSURE (insn);
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      delta[cl] = reg_pressure[cci].set_increase;
++    }
++
++  /* Record which registers previously died at POINT, but which now die
++     before POINT.  Adjust DELTA so that it represents the effect of
++     this change after POINT - 1.  Set NUM_PENDING_BIRTHS to the number of
++     registers that will be born in the range [model_curr_point, POINT).  */
++  num_uses = 0;
++  num_pending_births = 0;
++  for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
++    {
++      new_last = model_last_use_except (use);
++      if (new_last < point)
++	{
++	  gcc_assert (num_uses < ARRAY_SIZE (uses));
++	  uses[num_uses].last_use = new_last;
++	  uses[num_uses].regno = use->regno;
++	  /* This register is no longer live after POINT - 1.  */
++	  mark_regno_birth_or_death (NULL, delta, use->regno, false);
++	  num_uses++;
++	  if (new_last >= 0)
++	    num_pending_births++;
++	}
++    }
++
++  /* Update the MODEL_REF_PRESSURE and MODEL_MAX_PRESSURE for POINT.
++     Also set each group pressure limit for POINT.  */
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      model_start_update_pressure (&model_before_pressure,
++				   point, cci, delta[cl]);
++    }
++
++  /* Walk the model schedule backwards, starting immediately before POINT.  */
++  print_p = false;
++  if (point != model_curr_point)
++    do
++      {
++	point--;
++	insn = MODEL_INSN (point);
++	queue = QUEUE_INDEX (insn);
++
++	if (queue != QUEUE_SCHEDULED)
++	  {
++	    /* DELTA describes the effect of the move on the register pressure
++	       after POINT.  Make it describe the effect on the pressure
++	       before POINT.  */
++	    i = 0;
++	    while (i < num_uses)
++	      {
++		if (uses[i].last_use == point)
++		  {
++		    /* This register is now live again.  */
++		    mark_regno_birth_or_death (NULL, delta,
++					       uses[i].regno, true);
++
++		    /* Remove this use from the array.  */
++		    uses[i] = uses[num_uses - 1];
++		    num_uses--;
++		    num_pending_births--;
++		  }
++		else
++		  i++;
++	      }
++
++	    if (sched_verbose >= 5)
++	      {
++		char buf[2048];
++
++		if (!print_p)
++		  {
++		    fprintf (sched_dump, MODEL_BAR);
++		    fprintf (sched_dump, ";;\t\t| New pressure for model"
++			     " schedule\n");
++		    fprintf (sched_dump, MODEL_BAR);
++		    print_p = true;
++		  }
++
++		print_pattern (buf, PATTERN (insn), 0);
++		fprintf (sched_dump, ";;\t\t| %3d %4d %-30s ",
++			 point, INSN_UID (insn), buf);
++		for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++		  {
++		    cl = ira_reg_class_cover[cci];
++		    ref_pressure = MODEL_REF_PRESSURE (&model_before_pressure,
++						       point, cci);
++		    fprintf (sched_dump, " %s:[%d->%d]",
++			     reg_class_names[ira_reg_class_cover[cci]],
++			     ref_pressure, ref_pressure + delta[cl]);
++		  }
++		fprintf (sched_dump, "\n");
++	      }
++	  }
++
++	/* Adjust the pressure at POINT.  Set MIX to nonzero if POINT - 1
++	   might have changed as well.  */
++	mix = num_pending_births;
++	for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++	  {
++	    cl = ira_reg_class_cover[cci];
++	    mix |= delta[cl];
++	    mix |= model_update_pressure (&model_before_pressure,
++					  point, cci, delta[cl]);
++	  }
++      }
++    while (mix && point > model_curr_point);
++
++  if (print_p)
++    fprintf (sched_dump, MODEL_BAR);
++}
++
++/* model_spill_cost (CL, P, P') returns the cost of increasing the
++   pressure on CL from P to P'.  We use this to calculate a "base ECC",
++   baseECC (CL, X), for each cover class CL and each instruction X.
++   Supposing X changes the pressure on CL from P to P', and that the
++   maximum pressure on CL in the current model schedule is MP', then:
++
++   * if X occurs before or at the next point of maximum pressure in
++     the model schedule and P' > MP', then:
++
++       baseECC (CL, X) = model_spill_cost (CL, MP, P')
++
++     The idea is that the pressure after scheduling a fixed set of
++     instructions -- in this case, the set up to and including the
++     next maximum pressure point -- is going to be the same regardless
++     of the order; we simply want to keep the intermediate pressure
++     under control.  Thus X has a cost of zero unless scheduling it
++     now would exceed MP'.
++
++     If all increases in the set are by the same amount, no zero-cost
++     instruction will ever cause the pressure to exceed MP'.  However,
++     if X is instead moved past an instruction X' with pressure in the
++     range (MP' - (P' - P), MP'), the pressure at X' will increase
++     beyond MP'.  Since baseECC is very much a heuristic anyway,
++     it doesn't seem worth the overhead of tracking cases like these.
++
++     The cost of exceeding MP' is always based on the original maximum
++     pressure MP.  This is so that going 2 registers over the original
++     limit has the same cost regardless of whether it comes from two
++     separate +1 deltas or from a single +2 delta.
++
++   * if X occurs after the next point of maximum pressure in the model
++     schedule and P' > P, then:
++
++       baseECC (CL, X) = model_spill_cost (CL, MP, MP' + (P' - P))
++
++     That is, if we move X forward across a point of maximum pressure,
++     and if X increases the pressure by P' - P, then we conservatively
++     assume that scheduling X next would increase the maximum pressure
++     by P' - P.  Again, the cost of doing this is based on the original
++     maximum pressure MP, for the same reason as above.
++
++   * if P' < P, P > MP, and X occurs at or after the next point of
++     maximum pressure, then:
++
++       baseECC (CL, X) = -model_spill_cost (CL, MAX (MP, P'), P)
++
++     That is, if we have already exceeded the original maximum pressure MP,
++     and if X might reduce the maximum pressure again -- or at least push
++     it further back, and thus allow more scheduling freedom -- it is given
++     a negative cost to reflect the improvement.
++
++   * otherwise,
++
++       baseECC (CL, X) = 0
++
++     In this case, X is not expected to affect the maximum pressure MP',
++     so it has zero cost.
++
++   We then create a combined value baseECC (X) that is the sum of
++   baseECC (CL, X) for each cover class CL.
++
++   baseECC (X) could itself be used as the ECC value described above.
++   However, this is often too conservative, in the sense that it
++   tends to make high-priority instructions that increase pressure
++   wait too long in cases where introducing a spill would be better.
++   For this reason the final ECC is a priority-adjusted form of
++   baseECC (X).  Specifically, we calculate:
++
++     P (X) = INSN_PRIORITY (X) - insn_delay (X) - baseECC (X)
++     baseP = MAX { P (X) | baseECC (X) <= 0 }
++
++   Then:
++
++     ECC (X) = MAX (MIN (baseP - P (X), baseECC (X)), 0)
++
++   Thus an instruction's effect on pressure is ignored if it has a high
++   enough priority relative to the ones that don't increase pressure.
++   Negative values of baseECC (X) do not increase the priority of X
++   itself, but they do make it harder for other instructions to
++   increase the pressure further.
++
++   This pressure cost is deliberately timid.  The intention has been
++   to choose a heuristic that rarely interferes with the normal list
++   scheduler in cases where that scheduler would produce good code.
++   We simply want to curb some of its worst excesses.  */
++
++/* Return the cost of increasing the pressure in class CL from FROM to TO.
++
++   Here we use the very simplistic cost model that every register above
++   ira_available_class_regs[CL] has a spill cost of 1.  We could use other
++   measures instead, such as one based on MEMORY_MOVE_COST.  However:
++
++      (1) In order for an instruction to be scheduled, the higher cost
++	  would need to be justified in a single saving of that many stalls.
++	  This is overly pessimistic, because the benefit of spilling is
++	  often to avoid a sequence of several short stalls rather than
++	  a single long one.
++
++      (2) The cost is still arbitrary.  Because we are not allocating
++	  registers during scheduling, we have no way of knowing for
++	  sure how many memory accesses will be required by each spill,
++	  where the spills will be placed within the block, or even
++	  which block(s) will contain the spills.
++
++   So a higher cost than 1 is often too conservative in practice,
++   forcing blocks to contain unnecessary stalls instead of spill code.
++   The simple cost below seems to be the best compromise.  It reduces
++   the interference with the normal list scheduler, which helps make
++   it more suitable for a default-on option.  */
++
++static int
++model_spill_cost (int cl, int from, int to)
++{
++  from = MAX (from, ira_available_class_regs[cl]);
++  return MAX (to, from) - from;
++}
++
++/* Return baseECC (ira_reg_class_cover[CCI], POINT), given that
++   P = curr_reg_pressure[ira_reg_class_cover[CCI]] and that
++   P' = P + DELTA.  */
++
++static int
++model_excess_group_cost (struct model_pressure_group *group,
++			 int point, int cci, int delta)
++{
++  int pressure, cl;
++
++  cl = ira_reg_class_cover[cci];
++  if (delta < 0 && point >= group->limits[cci].point)
++    {
++      pressure = MAX (group->limits[cci].orig_pressure,
++		      curr_reg_pressure[cl] + delta);
++      return -model_spill_cost (cl, pressure, curr_reg_pressure[cl]);
++    }
++
++  if (delta > 0)
++    {
++      if (point > group->limits[cci].point)
++	pressure = group->limits[cci].pressure + delta;
++      else
++	pressure = curr_reg_pressure[cl] + delta;
++
++      if (pressure > group->limits[cci].pressure)
++	return model_spill_cost (cl, group->limits[cci].orig_pressure,
++				 pressure);
++    }
++
++  return 0;
++}
++
++/* Return baseECC (MODEL_INSN (INSN)).  Dump the costs to sched_dump
++   if PRINT_P.  */
++
++static int
++model_excess_cost (rtx insn, bool print_p)
++{
++  int point, cci, cl, cost, this_cost, delta;
++  struct reg_pressure_data *insn_reg_pressure;
++  int insn_death[N_REG_CLASSES];
++
++  calculate_reg_deaths (insn, insn_death);
++  point = model_index (insn);
++  insn_reg_pressure = INSN_REG_PRESSURE (insn);
++  cost = 0;
++
++  if (print_p)
++    fprintf (sched_dump, ";;\t\t| %3d %4d | %4d %+3d |", point,
++	     INSN_UID (insn), INSN_PRIORITY (insn), insn_delay (insn));
++
++  /* Sum up the individual costs for each register class.  */
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      delta = insn_reg_pressure[cci].set_increase - insn_death[cl];
++      this_cost = model_excess_group_cost (&model_before_pressure,
++					   point, cci, delta);
++      cost += this_cost;
++      if (print_p)
++	fprintf (sched_dump, " %s:[%d base cost %d]",
++		 reg_class_names[cl], delta, this_cost);
++    }
++
++  if (print_p)
++    fprintf (sched_dump, "\n");
++
++  return cost;
++}
++
++/* Dump the next points of maximum pressure for GROUP.  */
++
++static void
++model_dump_pressure_points (struct model_pressure_group *group)
++{
++  int cci, cl;
++
++  fprintf (sched_dump, ";;\t\t|  pressure points");
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      fprintf (sched_dump, " %s:[%d->%d at ", reg_class_names[cl],
++	       curr_reg_pressure[cl], group->limits[cci].pressure);
++      if (group->limits[cci].point < model_num_insns)
++	fprintf (sched_dump, "%d:%d]", group->limits[cci].point,
++		 INSN_UID (MODEL_INSN (group->limits[cci].point)));
++      else
++	fprintf (sched_dump, "end]");
++    }
++  fprintf (sched_dump, "\n");
++}
++
++/* Set INSN_REG_PRESSURE_EXCESS_COST_CHANGE for INSNS[0...COUNT-1].  */
++
++static void
++model_set_excess_costs (rtx *insns, int count)
++{
++  int i, cost, priority_base, priority;
++  bool print_p;
++
++  /* Record the baseECC value for each instruction in the model schedule,
++     except that negative costs are converted to zero ones now rather thatn
++     later.  Do not assign a cost to debug instructions, since they must
++     not change code-generation decisions.  Experiments suggest we also
++     get better results by not assigning a cost to instructions from
++     a different block.
++
++     Set PRIORITY_BASE to baseP in the block comment above.  This is the
++     maximum priority of the "cheap" instructions, which should always
++     include the next model instruction.  */
++  priority_base = 0;
++  print_p = false;
++  for (i = 0; i < count; i++)
++    if (INSN_MODEL_INDEX (insns[i]))
++      {
++	if (sched_verbose >= 6 && !print_p)
++	  {
++	    fprintf (sched_dump, MODEL_BAR);
++	    fprintf (sched_dump, ";;\t\t| Pressure costs for ready queue\n");
++	    model_dump_pressure_points (&model_before_pressure);
++	    fprintf (sched_dump, MODEL_BAR);
++	    print_p = true;
++	  }
++	cost = model_excess_cost (insns[i], print_p);
++	if (cost <= 0)
++	  {
++	    priority = INSN_PRIORITY (insns[i]) - insn_delay (insns[i]) - cost;
++	    priority_base = MAX (priority_base, priority);
++	    cost = 0;
++	  }
++	INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i]) = cost;
++      }
++  if (print_p)
++    fprintf (sched_dump, MODEL_BAR);
++
++  /* Use MAX (baseECC, 0) and baseP to calculcate ECC for each
++     instruction.  */
++  for (i = 0; i < count; i++)
++    {
++      cost = INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i]);
++      priority = INSN_PRIORITY (insns[i]) - insn_delay (insns[i]);
++      if (cost > 0 && priority > priority_base)
++	{
++	  cost += priority_base - priority;
++	  INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i]) = MAX (cost, 0);
++	}
++    }
++}
++
+ /* Returns a positive value if x is preferred; returns a negative value if
+    y is preferred.  Should never return 0, since that will make the sort
+    unstable.  */
+@@ -1170,23 +1948,20 @@
+   /* Make sure that priority of TMP and TMP2 are initialized.  */
+   gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2));
+ 
+-  if (sched_pressure_p)
++  if (sched_pressure != SCHED_PRESSURE_NONE)
+     {
+       int diff;
+ 
+       /* Prefer insn whose scheduling results in the smallest register
+ 	 pressure excess.  */
+       if ((diff = (INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp)
+-		   + (INSN_TICK (tmp) > clock_var
+-		      ? INSN_TICK (tmp) - clock_var : 0)
++		   + insn_delay (tmp)
+ 		   - INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp2)
+-		   - (INSN_TICK (tmp2) > clock_var
+-		      ? INSN_TICK (tmp2) - clock_var : 0))) != 0)
++		   - insn_delay (tmp2))))
+ 	return diff;
+     }
+ 
+-
+-  if (sched_pressure_p
++  if (sched_pressure != SCHED_PRESSURE_NONE
+       && (INSN_TICK (tmp2) > clock_var || INSN_TICK (tmp) > clock_var))
+     {
+       if (INSN_TICK (tmp) <= clock_var)
+@@ -1277,11 +2052,22 @@
+ 	return val;
+     }
+ 
++  /* Prefer instructions that occur earlier in the model schedule.  */
++  if (sched_pressure == SCHED_PRESSURE_MODEL)
++    {
++      int diff;
++
++      diff = model_index (tmp) - model_index (tmp2);
++      if (diff != 0)
++	return diff;
++    }
++
+   /* Prefer the insn which has more later insns that depend on it.
+      This gives the scheduler more freedom when scheduling later
+      instructions at the expense of added register pressure.  */
+ 
+-  val = (dep_list_size (tmp2) - dep_list_size (tmp));
++  val = (dep_list_size (tmp2, SD_LIST_FORW)
++	 - dep_list_size (tmp, SD_LIST_FORW));
+ 
+   if (flag_sched_dep_count_heuristic && val != 0)
+     return val;
+@@ -1480,12 +2266,15 @@
+   int i;
+   rtx *first = ready_lastpos (ready);
+ 
+-  if (sched_pressure_p)
++  if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
+     {
+       for (i = 0; i < ready->n_ready; i++)
+ 	if (!DEBUG_INSN_P (first[i]))
+ 	  setup_insn_reg_pressure_info (first[i]);
+     }
++  if (sched_pressure == SCHED_PRESSURE_MODEL
++      && model_curr_point < model_num_insns)
++    model_set_excess_costs (first, ready->n_ready);
+   SCHED_SORT (first, ready->n_ready);
+ }
+ 
+@@ -1551,10 +2340,12 @@
+   gcc_checking_assert (!DEBUG_INSN_P (insn));
+ 
+   for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
+-    if (dying_use_p (use) && bitmap_bit_p (curr_reg_live, use->regno))
+-      mark_regno_birth_or_death (use->regno, false);
++    if (dying_use_p (use))
++      mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
++				 use->regno, false);
+   for (set = INSN_REG_SET_LIST (insn); set != NULL; set = set->next_insn_set)
+-    mark_regno_birth_or_death (set->regno, true);
++    mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
++			       set->regno, true);
+ }
+ 
+ /* Set up or update (if UPDATE_P) max register pressure (see its
+@@ -1626,11 +2417,618 @@
+ void
+ sched_setup_bb_reg_pressure_info (basic_block bb, rtx after)
+ {
+-  gcc_assert (sched_pressure_p);
++  gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
+   initiate_bb_reg_pressure_info (bb);
+   setup_insn_max_reg_pressure (after, false);
+ }
+-
++
++/* Return (in order):
++
++   - positive if INSN adversely affects the pressure on one
++     register class
++
++   - negative if INSN reduces the pressure on one register class
++
++   - 0 if INSN doesn't affect the pressure on any register class.  */
++
++static int
++model_classify_pressure (struct model_insn_info *insn)
++{
++  struct reg_pressure_data *reg_pressure;
++  int death[N_REG_CLASSES];
++  int cci, cl, sum;
++
++  calculate_reg_deaths (insn->insn, death);
++  reg_pressure = INSN_REG_PRESSURE (insn->insn);
++  sum = 0;
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      if (death[cl] < reg_pressure[cci].set_increase)
++	return 1;
++      sum += reg_pressure[cci].set_increase - death[cl];
++    }
++  return sum;
++}
++
++/* Return true if INSN1 should come before INSN2 in the model schedule.  */
++
++static int
++model_order_p (struct model_insn_info *insn1, struct model_insn_info *insn2)
++{
++  unsigned int height1, height2;
++  unsigned int priority1, priority2;
++
++  /* Prefer instructions with a higher model priority.  */
++  if (insn1->model_priority != insn2->model_priority)
++    return insn1->model_priority > insn2->model_priority;
++
++  /* Combine the length of the longest path of satisfied true dependencies
++     that leads to each instruction (depth) with the length of the longest
++     path of any dependencies that leads from the instruction (alap).
++     Prefer instructions with the greatest combined length.  If the combined
++     lengths are equal, prefer instructions with the greatest depth.
++
++     The idea is that, if we have a set S of "equal" instructions that each
++     have ALAP value X, and we pick one such instruction I, any true-dependent
++     successors of I that have ALAP value X - 1 should be preferred over S.
++     This encourages the schedule to be "narrow" rather than "wide".
++     However, if I is a low-priority instruction that we decided to
++     schedule because of its model_classify_pressure, and if there
++     is a set of higher-priority instructions T, the aforementioned
++     successors of I should not have the edge over T.  */
++  height1 = insn1->depth + insn1->alap;
++  height2 = insn2->depth + insn2->alap;
++  if (height1 != height2)
++    return height1 > height2;
++  if (insn1->depth != insn2->depth)
++    return insn1->depth > insn2->depth;
++
++  /* We have no real preference between INSN1 an INSN2 as far as attempts
++     to reduce pressure go.  Prefer instructions with higher priorities.  */
++  priority1 = INSN_PRIORITY (insn1->insn);
++  priority2 = INSN_PRIORITY (insn2->insn);
++  if (priority1 != priority2)
++    return priority1 > priority2;
++
++  /* Use the original rtl sequence as a tie-breaker.  */
++  return insn1 < insn2;
++}
++
++/* Add INSN to the model worklist immediately after PREV.  Add it to the
++   beginning of the list if PREV is null.  */
++
++static void
++model_add_to_worklist_at (struct model_insn_info *insn,
++			  struct model_insn_info *prev)
++{
++  gcc_assert (QUEUE_INDEX (insn->insn) == QUEUE_NOWHERE);
++  QUEUE_INDEX (insn->insn) = QUEUE_READY;
++
++  insn->prev = prev;
++  if (prev)
++    {
++      insn->next = prev->next;
++      prev->next = insn;
++    }
++  else
++    {
++      insn->next = model_worklist;
++      model_worklist = insn;
++    }
++  if (insn->next)
++    insn->next->prev = insn;
++}
++
++/* Remove INSN from the model worklist.  */
++
++static void
++model_remove_from_worklist (struct model_insn_info *insn)
++{
++  gcc_assert (QUEUE_INDEX (insn->insn) == QUEUE_READY);
++  QUEUE_INDEX (insn->insn) = QUEUE_NOWHERE;
++
++  if (insn->prev)
++    insn->prev->next = insn->next;
++  else
++    model_worklist = insn->next;
++  if (insn->next)
++    insn->next->prev = insn->prev;
++}
++
++/* Add INSN to the model worklist.  Start looking for a suitable position
++   between neighbors PREV and NEXT, testing at most MAX_SCHED_READY_INSNS
++   insns either side.  A null PREV indicates the beginning of the list and
++   a null NEXT indicates the end.  */
++
++static void
++model_add_to_worklist (struct model_insn_info *insn,
++		       struct model_insn_info *prev,
++		       struct model_insn_info *next)
++{
++  int count;
++
++  count = MAX_SCHED_READY_INSNS;
++  if (count > 0 && prev && model_order_p (insn, prev))
++    do
++      {
++	count--;
++	prev = prev->prev;
++      }
++    while (count > 0 && prev && model_order_p (insn, prev));
++  else
++    while (count > 0 && next && model_order_p (next, insn))
++      {
++	count--;
++	prev = next;
++	next = next->next;
++      }
++  model_add_to_worklist_at (insn, prev);
++}
++
++/* INSN may now have a higher priority (in the model_order_p sense)
++   than before.  Move it up the worklist if necessary.  */
++
++static void
++model_promote_insn (struct model_insn_info *insn)
++{
++  struct model_insn_info *prev;
++  int count;
++
++  prev = insn->prev;
++  count = MAX_SCHED_READY_INSNS;
++  while (count > 0 && prev && model_order_p (insn, prev))
++    {
++      count--;
++      prev = prev->prev;
++    }
++  if (prev != insn->prev)
++    {
++      model_remove_from_worklist (insn);
++      model_add_to_worklist_at (insn, prev);
++    }
++}
++
++/* Add INSN to the end of the model schedule.  */
++
++static void
++model_add_to_schedule (rtx insn)
++{
++  unsigned int point;
++
++  gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE);
++  QUEUE_INDEX (insn) = QUEUE_SCHEDULED;
++
++  point = VEC_length (rtx, model_schedule);
++  VEC_quick_push (rtx, model_schedule, insn);
++  INSN_MODEL_INDEX (insn) = point + 1;
++}
++
++/* Analyze the instructions that are to be scheduled, setting up
++   MODEL_INSN_INFO (...) and model_num_insns accordingly.  Add ready
++   instructions to model_worklist.  */
++
++static void
++model_analyze_insns (void)
++{
++  rtx start, end, iter;
++  sd_iterator_def sd_it;
++  dep_t dep;
++  struct model_insn_info *insn, *con;
++
++  model_num_insns = 0;
++  start = PREV_INSN (current_sched_info->next_tail);
++  end = current_sched_info->prev_head;
++  for (iter = start; iter != end; iter = PREV_INSN (iter))
++    if (NONDEBUG_INSN_P (iter))
++      {
++	insn = MODEL_INSN_INFO (iter);
++	insn->insn = iter;
++	FOR_EACH_DEP (iter, SD_LIST_FORW, sd_it, dep)
++	  {
++	    con = MODEL_INSN_INFO (DEP_CON (dep));
++	    if (con->insn && insn->alap < con->alap + 1)
++	      insn->alap = con->alap + 1;
++	  }
++
++	insn->old_queue = QUEUE_INDEX (iter);
++	QUEUE_INDEX (iter) = QUEUE_NOWHERE;
++
++	insn->unscheduled_preds = dep_list_size (iter, SD_LIST_HARD_BACK);
++	if (insn->unscheduled_preds == 0)
++	  model_add_to_worklist (insn, NULL, model_worklist);
++
++	model_num_insns++;
++      }
++}
++
++/* The global state describes the register pressure at the start of the
++   model schedule.  Initialize GROUP accordingly.  */
++
++static void
++model_init_pressure_group (struct model_pressure_group *group)
++{
++  int cci, cl;
++
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      group->limits[cci].pressure = curr_reg_pressure[cl];
++      group->limits[cci].point = 0;
++    }
++  /* Use index model_num_insns to record the state after the last
++     instruction in the model schedule.  */
++  group->model = XNEWVEC (struct model_pressure_data,
++			  (model_num_insns + 1) * ira_reg_class_cover_size);
++}
++
++/* Record that MODEL_REF_PRESSURE (GROUP, POINT, CCI) is PRESSURE.
++   Update the maximum pressure for the whole schedule.  */
++
++static void
++model_record_pressure (struct model_pressure_group *group,
++		       int point, int cci, int pressure)
++{
++  MODEL_REF_PRESSURE (group, point, cci) = pressure;
++  if (group->limits[cci].pressure < pressure)
++    {
++      group->limits[cci].pressure = pressure;
++      group->limits[cci].point = point;
++    }
++}
++
++/* INSN has just been added to the end of the model schedule.  Record its
++   register-pressure information.  */
++
++static void
++model_record_pressures (struct model_insn_info *insn)
++{
++  struct reg_pressure_data *reg_pressure;
++  int point, cci, cl, delta;
++  int death[N_REG_CLASSES];
++
++  point = model_index (insn->insn);
++  if (sched_verbose >= 2)
++    {
++      char buf[2048];
++
++      if (point == 0)
++	{
++	  fprintf (sched_dump, "\n;;\tModel schedule:\n;;\n");
++	  fprintf (sched_dump, ";;\t| idx insn | mpri hght dpth prio |\n");
++	}
++      print_pattern (buf, PATTERN (insn->insn), 0);
++      fprintf (sched_dump, ";;\t| %3d %4d | %4d %4d %4d %4d | %-30s ",
++	       point, INSN_UID (insn->insn), insn->model_priority,
++	       insn->depth + insn->alap, insn->depth,
++	       INSN_PRIORITY (insn->insn), buf);
++    }
++  calculate_reg_deaths (insn->insn, death);
++  reg_pressure = INSN_REG_PRESSURE (insn->insn);
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      delta = reg_pressure[cci].set_increase - death[cl];
++      if (sched_verbose >= 2)
++	fprintf (sched_dump, " %s:[%d,%+d]", reg_class_names[cl],
++		 curr_reg_pressure[cl], delta);
++      model_record_pressure (&model_before_pressure, point, cci,
++			     curr_reg_pressure[cl]);
++    }
++  if (sched_verbose >= 2)
++    fprintf (sched_dump, "\n");
++}
++
++/* All instructions have been added to the model schedule.  Record the
++   final register pressure in GROUP and set up all MODEL_MAX_PRESSUREs.  */
++
++static void
++model_record_final_pressures (struct model_pressure_group *group)
++{
++  int point, cci, max_pressure, ref_pressure, cl;
++
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      /* Record the final pressure for this class.  */
++      cl = ira_reg_class_cover[cci];
++      point = model_num_insns;
++      ref_pressure = curr_reg_pressure[cl];
++      model_record_pressure (group, point, cci, ref_pressure);
++
++      /* Record the original maximum pressure.  */
++      group->limits[cci].orig_pressure = group->limits[cci].pressure;
++
++      /* Update the MODEL_MAX_PRESSURE for every point of the schedule.  */
++      max_pressure = ref_pressure;
++      MODEL_MAX_PRESSURE (group, point, cci) = max_pressure;
++      while (point > 0)
++	{
++	  point--;
++	  ref_pressure = MODEL_REF_PRESSURE (group, point, cci);
++	  max_pressure = MAX (max_pressure, ref_pressure);
++	  MODEL_MAX_PRESSURE (group, point, cci) = max_pressure;
++	}
++    }
++}
++
++/* Update all successors of INSN, given that INSN has just been scheduled.  */
++
++static void
++model_add_successors_to_worklist (struct model_insn_info *insn)
++{
++  sd_iterator_def sd_it;
++  struct model_insn_info *con;
++  dep_t dep;
++
++  FOR_EACH_DEP (insn->insn, SD_LIST_FORW, sd_it, dep)
++    {
++      con = MODEL_INSN_INFO (DEP_CON (dep));
++      /* Ignore debug instructions, and instructions from other blocks.  */
++      if (con->insn)
++	{
++	  con->unscheduled_preds--;
++
++	  /* Update the depth field of each true-dependent successor.
++	     Increasing the depth gives them a higher priority than
++	     before.  */
++	  if (DEP_TYPE (dep) == REG_DEP_TRUE && con->depth < insn->depth + 1)
++	    {
++	      con->depth = insn->depth + 1;
++	      if (QUEUE_INDEX (con->insn) == QUEUE_READY)
++		model_promote_insn (con);
++	    }
++
++	  /* If this is a true dependency, or if there are no remaining
++	     dependencies for CON (meaning that CON only had non-true
++	     dependencies), make sure that CON is on the worklist.
++	     We don't bother otherwise because it would tend to fill the
++	     worklist with a lot of low-priority instructions that are not
++	     yet ready to issue.  */
++	  if ((con->depth > 0 || con->unscheduled_preds == 0)
++	      && QUEUE_INDEX (con->insn) == QUEUE_NOWHERE)
++	    model_add_to_worklist (con, insn, insn->next);
++	}
++    }
++}
++
++/* Give INSN a higher priority than any current instruction, then give
++   unscheduled predecessors of INSN a higher priority still.  If any of
++   those predecessors are not on the model worklist, do the same for its
++   predecessors, and so on.  */
++
++static void
++model_promote_predecessors (struct model_insn_info *insn)
++{
++  struct model_insn_info *pro, *first;
++  sd_iterator_def sd_it;
++  dep_t dep;
++
++  if (sched_verbose >= 7)
++    fprintf (sched_dump, ";;\t+--- priority of %d = %d, priority of",
++	     INSN_UID (insn->insn), model_next_priority);
++  insn->model_priority = model_next_priority++;
++  model_remove_from_worklist (insn);
++  model_add_to_worklist_at (insn, NULL);
++
++  first = NULL;
++  for (;;)
++    {
++      FOR_EACH_DEP (insn->insn, SD_LIST_HARD_BACK, sd_it, dep)
++	{
++	  pro = MODEL_INSN_INFO (DEP_PRO (dep));
++	  /* The first test is to ignore debug instructions, and instructions
++	     from other blocks.  */
++	  if (pro->insn
++	      && pro->model_priority != model_next_priority
++	      && QUEUE_INDEX (pro->insn) != QUEUE_SCHEDULED)
++	    {
++	      pro->model_priority = model_next_priority;
++	      if (sched_verbose >= 7)
++		fprintf (sched_dump, " %d", INSN_UID (pro->insn));
++	      if (QUEUE_INDEX (pro->insn) == QUEUE_READY)
++		{
++		  /* PRO is already in the worklist, but it now has
++		     a higher priority than before.  Move it at the
++		     appropriate place.  */
++		  model_remove_from_worklist (pro);
++		  model_add_to_worklist (pro, NULL, model_worklist);
++		}
++	      else
++		{
++		  /* PRO isn't in the worklist.  Recursively process
++		     its predecessors until we find one that is.  */
++		  pro->next = first;
++		  first = pro;
++		}
++	    }
++	}
++      if (!first)
++	break;
++      insn = first;
++      first = insn->next;
++    }
++  if (sched_verbose >= 7)
++    fprintf (sched_dump, " = %d\n", model_next_priority);
++  model_next_priority++;
++}
++
++/* Pick one instruction from model_worklist and process it.  */
++
++static void
++model_choose_insn (void)
++{
++  struct model_insn_info *insn, *fallback;
++  int count;
++
++  if (sched_verbose >= 7)
++    {
++      fprintf (sched_dump, ";;\t+--- worklist:\n");
++      insn = model_worklist;
++      count = MAX_SCHED_READY_INSNS;
++      while (count > 0 && insn)
++	{
++	  fprintf (sched_dump, ";;\t+---   %d [%d, %d, %d, %d]\n",
++		   INSN_UID (insn->insn), insn->model_priority,
++		   insn->depth + insn->alap, insn->depth,
++		   INSN_PRIORITY (insn->insn));
++	  count--;
++	  insn = insn->next;
++	}
++    }
++
++  /* Look for a ready instruction whose model_classify_priority is zero
++     or negative, picking the highest-priority one.  Adding such an
++     instruction to the schedule now should do no harm, and may actually
++     do some good.
++
++     Failing that, see whether there is an instruction with the highest
++     extant model_priority that is not yet ready, but which would reduce
++     pressure if it became ready.  This is designed to catch cases like:
++
++       (set (mem (reg R1)) (reg R2))
++
++     where the instruction is the last remaining use of R1 and where the
++     value of R2 is not yet available (or vice versa).  The death of R1
++     means that this instruction already reduces pressure.  It is of
++     course possible that the computation of R2 involves other registers
++     that are hard to kill, but such cases are rare enough for this
++     heuristic to be a win in general.
++
++     Failing that, just pick the highest-priority instruction in the
++     worklist.  */
++  count = MAX_SCHED_READY_INSNS;
++  insn = model_worklist;
++  fallback = 0;
++  for (;;)
++    {
++      if (count == 0 || !insn)
++	{
++	  insn = fallback ? fallback : model_worklist;
++	  break;
++	}
++      if (insn->unscheduled_preds)
++	{
++	  if (model_worklist->model_priority == insn->model_priority
++	      && !fallback
++	      && model_classify_pressure (insn) < 0)
++	    fallback = insn;
++	}
++      else
++	{
++	  if (model_classify_pressure (insn) <= 0)
++	    break;
++	}
++      count--;
++      insn = insn->next;
++    }
++
++  if (sched_verbose >= 7 && insn != model_worklist)
++    {
++      if (insn->unscheduled_preds)
++	fprintf (sched_dump, ";;\t+--- promoting insn %d, with dependencies\n",
++		 INSN_UID (insn->insn));
++      else
++	fprintf (sched_dump, ";;\t+--- promoting insn %d, which is ready\n",
++		 INSN_UID (insn->insn));
++    }
++  if (insn->unscheduled_preds)
++    /* INSN isn't yet ready to issue.  Give all its predecessors the
++       highest priority.  */
++    model_promote_predecessors (insn);
++  else
++    {
++      /* INSN is ready.  Add it to the end of model_schedule and
++	 process its successors.  */
++      model_add_successors_to_worklist (insn);
++      model_remove_from_worklist (insn);
++      model_add_to_schedule (insn->insn);
++      model_record_pressures (insn);
++      update_register_pressure (insn->insn);
++    }
++}
++
++/* Restore all QUEUE_INDEXs to the values that they had before
++   model_start_schedule was called.  */
++
++static void
++model_reset_queue_indices (void)
++{
++  unsigned int i;
++  rtx insn;
++
++  FOR_EACH_VEC_ELT (rtx, model_schedule, i, insn)
++    QUEUE_INDEX (insn) = MODEL_INSN_INFO (insn)->old_queue;
++}
++
++/* We have calculated the model schedule and spill costs.  Print a summary
++   to sched_dump.  */
++
++static void
++model_dump_pressure_summary (void)
++{
++  int cci, cl;
++
++  fprintf (sched_dump, ";; Pressure summary:");
++  for (cci = 0; cci < ira_reg_class_cover_size; cci++)
++    {
++      cl = ira_reg_class_cover[cci];
++      fprintf (sched_dump, " %s:%d", reg_class_names[cl],
++	       model_before_pressure.limits[cci].pressure);
++    }
++  fprintf (sched_dump, "\n\n");
++}
++
++/* Initialize the SCHED_PRESSURE_MODEL information for the current
++   scheduling region.  */
++
++static void
++model_start_schedule (void)
++{
++  basic_block bb;
++
++  model_next_priority = 1;
++  model_schedule = VEC_alloc (rtx, heap, sched_max_luid);
++  model_insns = XCNEWVEC (struct model_insn_info, sched_max_luid);
++
++  bb = BLOCK_FOR_INSN (NEXT_INSN (current_sched_info->prev_head));
++  initiate_reg_pressure_info (df_get_live_in (bb));
++
++  model_analyze_insns ();
++  model_init_pressure_group (&model_before_pressure);
++  while (model_worklist)
++    model_choose_insn ();
++  gcc_assert (model_num_insns == (int) VEC_length (rtx, model_schedule));
++  if (sched_verbose >= 2)
++    fprintf (sched_dump, "\n");
++
++  model_record_final_pressures (&model_before_pressure);
++  model_reset_queue_indices ();
++
++  XDELETEVEC (model_insns);
++
++  model_curr_point = 0;
++  initiate_reg_pressure_info (df_get_live_in (bb));
++  if (sched_verbose >= 1)
++    model_dump_pressure_summary ();
++}
++
++/* Free the information associated with GROUP.  */
++
++static void
++model_finalize_pressure_group (struct model_pressure_group *group)
++{
++  XDELETEVEC (group->model);
++}
++
++/* Free the information created by model_start_schedule.  */
++
++static void
++model_end_schedule (void)
++{
++  model_finalize_pressure_group (&model_before_pressure);
++  VEC_free (rtx, heap, model_schedule);
++}
++
+ /* INSN is the "currently executing insn".  Launch each insn which was
+    waiting on INSN.  READY is the ready list which contains the insns
+    that are ready to fire.  CLOCK is the current cycle.  The function
+@@ -1667,10 +3065,14 @@
+ 		     reg_class_names[ira_reg_class_cover[i]],
+ 		     pressure_info[i].set_increase, pressure_info[i].change);
+ 	}
++      if (sched_pressure == SCHED_PRESSURE_MODEL
++	  && model_curr_point < model_num_insns
++	  && model_index (insn) == model_curr_point)
++	fprintf (sched_dump, ":model %d", model_curr_point);
+       fputc ('\n', sched_dump);
+     }
+ 
+-  if (sched_pressure_p && !DEBUG_INSN_P (insn))
++  if (sched_pressure == SCHED_PRESSURE_WEIGHTED && !DEBUG_INSN_P (insn))
+     update_reg_and_insn_max_reg_pressure (insn);
+ 
+   /* Scheduling instruction should have all its dependencies resolved and
+@@ -1728,6 +3130,24 @@
+   gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE);
+   QUEUE_INDEX (insn) = QUEUE_SCHEDULED;
+ 
++  if (sched_pressure == SCHED_PRESSURE_MODEL
++      && model_curr_point < model_num_insns
++      && NONDEBUG_INSN_P (insn))
++    {
++      if (model_index (insn) == model_curr_point)
++	do
++	  model_curr_point++;
++	while (model_curr_point < model_num_insns
++	       && (QUEUE_INDEX (MODEL_INSN (model_curr_point))
++		   == QUEUE_SCHEDULED));
++      else
++	model_recompute (insn);
++      model_update_limit_points ();
++      update_register_pressure (insn);
++      if (sched_verbose >= 2)
++	print_curr_reg_pressure ();
++    }
++
+   gcc_assert (INSN_TICK (insn) >= MIN_TICK);
+   if (INSN_TICK (insn) > clock_var)
+     /* INSN has been prematurely moved from the queue to the ready list.
+@@ -2056,7 +3476,16 @@
+       /* If the ready list is full, delay the insn for 1 cycle.
+ 	 See the comment in schedule_block for the rationale.  */
+       if (!reload_completed
+-	  && ready->n_ready - ready->n_debug > MAX_SCHED_READY_INSNS
++	  && (ready->n_ready - ready->n_debug > MAX_SCHED_READY_INSNS
++	      || (sched_pressure == SCHED_PRESSURE_MODEL
++		  /* Limit pressure recalculations to MAX_SCHED_READY_INSNS
++		     instructions too.  */
++		  && model_index (insn) > (model_curr_point
++					   + MAX_SCHED_READY_INSNS)))
++	  && !(sched_pressure == SCHED_PRESSURE_MODEL
++	       && model_curr_point < model_num_insns
++	       /* Always allow the next model instruction to issue.  */
++	       && model_index (insn) == model_curr_point)
+ 	  && !SCHED_GROUP_P (insn)
+ 	  && insn != skip_insn)
+ 	{
+@@ -2293,12 +3722,12 @@
+       fprintf (sched_dump, "  %s:%d",
+ 	       (*current_sched_info->print_insn) (p[i], 0),
+ 	       INSN_LUID (p[i]));
+-      if (sched_pressure_p)
++      if (sched_pressure != SCHED_PRESSURE_NONE)
+ 	fprintf (sched_dump, "(cost=%d",
+ 		 INSN_REG_PRESSURE_EXCESS_COST_CHANGE (p[i]));
+       if (INSN_TICK (p[i]) > clock_var)
+ 	fprintf (sched_dump, ":delay=%d", INSN_TICK (p[i]) - clock_var);
+-      if (sched_pressure_p)
++      if (sched_pressure != SCHED_PRESSURE_NONE)
+ 	fprintf (sched_dump, ")");
+     }
+   fprintf (sched_dump, "\n");
+@@ -2609,8 +4038,8 @@
+ 	    {
+ 	      if (state_dead_lock_p (state)
+ 		  || insn_finishes_cycle_p (insn))
+- 		/* We won't issue any more instructions in the next
+- 		   choice_state.  */
++		/* We won't issue any more instructions in the next
++		   choice_state.  */
+ 		top->rest = 0;
+ 	      else
+ 		top->rest--;
+@@ -2813,6 +4242,59 @@
+     }
+ }
+ 
++/* Examine all insns on the ready list and queue those which can't be
++   issued in this cycle.  TEMP_STATE is temporary scheduler state we
++   can use as scratch space.  If FIRST_CYCLE_INSN_P is true, no insns
++   have been issued for the current cycle, which means it is valid to
++   issue an asm statement.  */
++
++static void
++prune_ready_list (state_t temp_state, bool first_cycle_insn_p)
++{
++  int i;
++
++ restart:
++  for (i = 0; i < ready.n_ready; i++)
++    {
++      rtx insn = ready_element (&ready, i);
++      int cost = 0;
++
++      if (recog_memoized (insn) < 0)
++	{
++	  if (!first_cycle_insn_p
++	      && (GET_CODE (PATTERN (insn)) == ASM_INPUT
++		  || asm_noperands (PATTERN (insn)) >= 0))
++	    cost = 1;
++	}
++      else if (sched_pressure != SCHED_PRESSURE_NONE)
++	{
++	  if (sched_pressure == SCHED_PRESSURE_MODEL
++	      && INSN_TICK (insn) <= clock_var)
++	    {
++	      memcpy (temp_state, curr_state, dfa_state_size);
++	      if (state_transition (temp_state, insn) >= 0)
++		INSN_TICK (insn) = clock_var + 1;
++	    }
++	  cost = 0;
++	}
++      else
++	{
++	  memcpy (temp_state, curr_state, dfa_state_size);
++	  cost = state_transition (temp_state, insn);
++	  if (cost < 0)
++	    cost = 0;
++	  else if (cost == 0)
++	    cost = 1;
++	}
++      if (cost >= 1)
++	{
++	  ready_remove (&ready, i);
++	  queue_insn (insn, cost);
++	  goto restart;
++	}
++    }
++}
++
+ /* Use forward list scheduling to rearrange insns of block pointed to by
+    TARGET_BB, possibly bringing insns from subsequent blocks in the same
+    region.  */
+@@ -2882,6 +4364,9 @@
+      in try_ready () (which is called through init_ready_list ()).  */
+   (*current_sched_info->init_ready_list) ();
+ 
++  if (sched_pressure == SCHED_PRESSURE_MODEL)
++    model_start_schedule ();
++
+   /* The algorithm is O(n^2) in the number of ready insns at any given
+      time in the worst case.  Before reload we are more likely to have
+      big lists so truncate them to a reasonable size.  */
+@@ -2963,6 +4448,10 @@
+ 	}
+       while (advance > 0);
+ 
++      prune_ready_list (temp_state, true);
++      if (ready.n_ready == 0)
++        continue;
++
+       if (sort_p)
+ 	{
+ 	  /* Sort the ready list based on priority.  */
+@@ -3040,7 +4529,7 @@
+ 	      fprintf (sched_dump, ";;\tReady list (t = %3d):  ",
+ 		       clock_var);
+ 	      debug_ready_list (&ready);
+-	      if (sched_pressure_p)
++	      if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
+ 		print_curr_reg_pressure ();
+ 	    }
+ 
+@@ -3084,7 +4573,8 @@
+ 	  else
+ 	    insn = ready_remove_first (&ready);
+ 
+-	  if (sched_pressure_p && INSN_TICK (insn) > clock_var)
++	  if (sched_pressure != SCHED_PRESSURE_NONE
++	      && INSN_TICK (insn) > clock_var)
+ 	    {
+ 	      ready_add (&ready, insn, true);
+ 	      advance = 1;
+@@ -3112,44 +4602,6 @@
+ 	    }
+ 
+ 	  sort_p = TRUE;
+-	  memcpy (temp_state, curr_state, dfa_state_size);
+-	  if (recog_memoized (insn) < 0)
+-	    {
+-	      asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
+-		       || asm_noperands (PATTERN (insn)) >= 0);
+-	      if (!first_cycle_insn_p && asm_p)
+-		/* This is asm insn which is tried to be issued on the
+-		   cycle not first.  Issue it on the next cycle.  */
+-		cost = 1;
+-	      else
+-		/* A USE insn, or something else we don't need to
+-		   understand.  We can't pass these directly to
+-		   state_transition because it will trigger a
+-		   fatal error for unrecognizable insns.  */
+-		cost = 0;
+-	    }
+-	  else if (sched_pressure_p)
+-	    cost = 0;
+-	  else
+-	    {
+-	      cost = state_transition (temp_state, insn);
+-	      if (cost < 0)
+-		cost = 0;
+-	      else if (cost == 0)
+-		cost = 1;
+-	    }
+-
+-	  if (cost >= 1)
+-	    {
+-	      queue_insn (insn, cost);
+- 	      if (SCHED_GROUP_P (insn))
+- 		{
+- 		  advance = cost;
+- 		  break;
+- 		}
+-
+-	      continue;
+-	    }
+ 
+ 	  if (current_sched_info->can_schedule_ready_p
+ 	      && ! (*current_sched_info->can_schedule_ready_p) (insn))
+@@ -3200,11 +4652,17 @@
+ 	  reemit_notes (insn);
+ 	  last_scheduled_insn = insn;
+ 
+-	  if (memcmp (curr_state, temp_state, dfa_state_size) != 0)
+-            {
+-              cycle_issued_insns++;
+-              memcpy (curr_state, temp_state, dfa_state_size);
+-            }
++	  if (recog_memoized (insn) >= 0)
++	    {
++	      cost = state_transition (curr_state, insn);
++	      if (sched_pressure != SCHED_PRESSURE_WEIGHTED)
++		gcc_assert (cost < 0);
++	      cycle_issued_insns++;
++	      asm_p = false;
++	    }
++	  else
++	    asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
++		     || asm_noperands (PATTERN (insn)) >= 0);
+ 
+ 	  if (targetm.sched.variable_issue)
+ 	    can_issue_more =
+@@ -3225,6 +4683,9 @@
+ 
+ 	  first_cycle_insn_p = false;
+ 
++	  if (ready.n_ready > 0)
++            prune_ready_list (temp_state, false);
++
+ 	  /* Sort the ready list based on priority.  This must be
+ 	     redone here, as schedule_insn may have readied additional
+ 	     insns that will not be sorted correctly.  */
+@@ -3321,6 +4782,9 @@
+ 	  }
+     }
+ 
++  if (sched_pressure == SCHED_PRESSURE_MODEL)
++    model_end_schedule ();
++
+   if (sched_verbose)
+     fprintf (sched_dump, ";;   total time = %d\n", clock_var);
+ 
+@@ -3424,10 +4888,14 @@
+   if (targetm.sched.dispatch (NULL_RTX, IS_DISPATCH_ON))
+     targetm.sched.dispatch_do (NULL_RTX, DISPATCH_INIT);
+ 
+-  sched_pressure_p = (flag_sched_pressure && ! reload_completed
+-		      && common_sched_info->sched_pass_id == SCHED_RGN_PASS);
++  if (flag_sched_pressure
++      && !reload_completed
++      && common_sched_info->sched_pass_id == SCHED_RGN_PASS)
++    sched_pressure = flag_sched_pressure_algorithm;
++  else
++    sched_pressure = SCHED_PRESSURE_NONE;
+ 
+-  if (sched_pressure_p)
++  if (sched_pressure != SCHED_PRESSURE_NONE)
+     ira_setup_eliminable_regset ();
+ 
+   /* Initialize SPEC_INFO.  */
+@@ -3504,7 +4972,7 @@
+   if (targetm.sched.init_global)
+     targetm.sched.init_global (sched_dump, sched_verbose, get_max_uid () + 1);
+ 
+-  if (sched_pressure_p)
++  if (sched_pressure != SCHED_PRESSURE_NONE)
+     {
+       int i, max_regno = max_reg_num ();
+ 
+@@ -3517,8 +4985,11 @@
+ 	     ? ira_class_translate[REGNO_REG_CLASS (i)]
+ 	     : reg_cover_class (i));
+       curr_reg_live = BITMAP_ALLOC (NULL);
+-      saved_reg_live = BITMAP_ALLOC (NULL);
+-      region_ref_regs = BITMAP_ALLOC (NULL);
++      if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
++	{
++	  saved_reg_live = BITMAP_ALLOC (NULL);
++	  region_ref_regs = BITMAP_ALLOC (NULL);
++	}
+     }
+ 
+   curr_state = xmalloc (dfa_state_size);
+@@ -3618,12 +5089,15 @@
+ sched_finish (void)
+ {
+   haifa_finish_h_i_d ();
+-  if (sched_pressure_p)
++  if (sched_pressure != SCHED_PRESSURE_NONE)
+     {
++      if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
++	{
++	  BITMAP_FREE (region_ref_regs);
++	  BITMAP_FREE (saved_reg_live);
++	}
++      BITMAP_FREE (curr_reg_live);
+       free (sched_regno_cover_class);
+-      BITMAP_FREE (region_ref_regs);
+-      BITMAP_FREE (saved_reg_live);
+-      BITMAP_FREE (curr_reg_live);
+     }
+   free (curr_state);
+ 
+@@ -3936,7 +5410,7 @@
+   INSN_TICK (next) = tick;
+ 
+   delay = tick - clock_var;
+-  if (delay <= 0 || sched_pressure_p)
++  if (delay <= 0 || sched_pressure != SCHED_PRESSURE_NONE)
+     delay = QUEUE_READY;
+ 
+   change_queue_index (next, delay);
+@@ -5185,7 +6659,7 @@
+       if (insn == jump)
+ 	break;
+ 
+-      if (dep_list_size (insn) == 0)
++      if (dep_list_size (insn, SD_LIST_FORW) == 0)
+ 	{
+ 	  dep_def _new_dep, *new_dep = &_new_dep;
+ 
+@@ -5556,6 +7030,7 @@
+ 
+   FOR_EACH_VEC_ELT (haifa_insn_data_def, h_i_d, i, data)
+     {
++      free (data->max_reg_pressure);
+       if (data->reg_pressure != NULL)
+ 	free (data->reg_pressure);
+       for (use = data->reg_use_list; use != NULL; use = next)
+
+=== modified file 'gcc/sched-deps.c'
+--- old/gcc/sched-deps.c	2011-12-08 13:33:58 +0000
++++ new/gcc/sched-deps.c	2012-02-08 23:39:45 +0000
+@@ -450,7 +450,7 @@
+ static void add_dependence_list_and_free (struct deps_desc *, rtx,
+ 					  rtx *, int, enum reg_note);
+ static void delete_all_dependences (rtx);
+-static void fixup_sched_groups (rtx);
++static void chain_to_prev_insn (rtx);
+ 
+ static void flush_pending_lists (struct deps_desc *, rtx, int, int);
+ static void sched_analyze_1 (struct deps_desc *, rtx, rtx);
+@@ -1490,7 +1490,7 @@
+    the previous nonnote insn.  */
+ 
+ static void
+-fixup_sched_groups (rtx insn)
++chain_to_prev_insn (rtx insn)
+ {
+   sd_iterator_def sd_it;
+   dep_t dep;
+@@ -1999,7 +1999,7 @@
+   static struct reg_pressure_data *pressure_info;
+   rtx link;
+ 
+-  gcc_assert (sched_pressure_p);
++  gcc_assert (sched_pressure != SCHED_PRESSURE_NONE);
+ 
+   if (! INSN_P (insn))
+     return;
+@@ -2030,8 +2030,9 @@
+   len = sizeof (struct reg_pressure_data) * ira_reg_class_cover_size;
+   pressure_info
+     = INSN_REG_PRESSURE (insn) = (struct reg_pressure_data *) xmalloc (len);
+-  INSN_MAX_REG_PRESSURE (insn) = (int *) xcalloc (ira_reg_class_cover_size
+-						  * sizeof (int), 1);
++  if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
++    INSN_MAX_REG_PRESSURE (insn) = (int *) xcalloc (ira_reg_class_cover_size
++						    * sizeof (int), 1);
+   for (i = 0; i < ira_reg_class_cover_size; i++)
+     {
+       cl = ira_reg_class_cover[i];
+@@ -2775,7 +2776,7 @@
+       || (NONJUMP_INSN_P (insn) && control_flow_insn_p (insn)))
+     reg_pending_barrier = MOVE_BARRIER;
+ 
+-  if (sched_pressure_p)
++  if (sched_pressure != SCHED_PRESSURE_NONE)
+     {
+       setup_insn_reg_uses (deps, insn);
+       setup_insn_reg_pressure_info (insn);
+@@ -3076,7 +3077,7 @@
+ 	       instructions that follow seem like they should be part
+ 	       of the call group.
+ 
+-	       Also, if we did, fixup_sched_groups() would move the
++	       Also, if we did, chain_to_prev_insn would move the
+ 	       deps of the debug insn to the call insn, modifying
+ 	       non-debug post-dependency counts of the debug insn
+ 	       dependencies and otherwise messing with the scheduling
+@@ -3222,6 +3223,37 @@
+   return true;
+ }
+ 
++/* Return true if INSN should be made dependent on the previous instruction
++   group, and if all INSN's dependencies should be moved to the first
++   instruction of that group.  */
++
++static bool
++chain_to_prev_insn_p (rtx insn)
++{
++  rtx prev, x;
++
++  /* INSN forms a group with the previous instruction.  */
++  if (SCHED_GROUP_P (insn))
++    return true;
++
++  /* If the previous instruction clobbers a register R and this one sets
++     part of R, the clobber was added specifically to help us track the
++     liveness of R.  There's no point scheduling the clobber and leaving
++     INSN behind, especially if we move the clobber to another block.  */
++  prev = prev_nonnote_nondebug_insn (insn);
++  if (prev
++      && INSN_P (prev)
++      && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
++      && GET_CODE (PATTERN (prev)) == CLOBBER)
++    {
++      x = XEXP (PATTERN (prev), 0);
++      if (set_of (x, insn))
++	return true;
++    }
++
++  return false;
++}
++
+ /* Analyze INSN with DEPS as a context.  */
+ void
+ deps_analyze_insn (struct deps_desc *deps, rtx insn)
+@@ -3358,8 +3390,9 @@
+ 
+   /* Fixup the dependencies in the sched group.  */
+   if ((NONJUMP_INSN_P (insn) || JUMP_P (insn))
+-      && SCHED_GROUP_P (insn) && !sel_sched_p ())
+-    fixup_sched_groups (insn);
++      && chain_to_prev_insn_p (insn)
++      && !sel_sched_p ())
++    chain_to_prev_insn (insn);
+ }
+ 
+ /* Initialize DEPS for the new block beginning with HEAD.  */
+
+=== modified file 'gcc/sched-int.h'
+--- old/gcc/sched-int.h	2011-02-02 04:31:35 +0000
++++ new/gcc/sched-int.h	2012-02-08 23:39:02 +0000
+@@ -651,7 +651,7 @@
+ 
+ /* Do register pressure sensitive insn scheduling if the flag is set
+    up.  */
+-extern bool sched_pressure_p;
++extern enum sched_pressure_algorithm sched_pressure;
+ 
+ /* Map regno -> its cover class.  The map defined only when
+    SCHED_PRESSURE_P is true.  */
+@@ -773,16 +773,16 @@
+ 
+   short cost;
+ 
++  /* '> 0' if priority is valid,
++     '== 0' if priority was not yet computed,
++     '< 0' if priority in invalid and should be recomputed.  */
++  signed char priority_status;
++
+   /* Set if there's DEF-USE dependence between some speculatively
+      moved load insn and this one.  */
+   unsigned int fed_by_spec_load : 1;
+   unsigned int is_load_insn : 1;
+ 
+-  /* '> 0' if priority is valid,
+-     '== 0' if priority was not yet computed,
+-     '< 0' if priority in invalid and should be recomputed.  */
+-  signed char priority_status;
+-
+   /* What speculations are necessary to apply to schedule the instruction.  */
+   ds_t todo_spec;
+ 
+@@ -817,6 +817,7 @@
+   /* Info about how scheduling the insn changes cost of register
+      pressure excess (between source and target).  */
+   int reg_pressure_excess_cost_change;
++  int model_index;
+ };
+ 
+ typedef struct _haifa_insn_data haifa_insn_data_def;
+@@ -839,6 +840,7 @@
+ #define INSN_REG_PRESSURE_EXCESS_COST_CHANGE(INSN) \
+   (HID (INSN)->reg_pressure_excess_cost_change)
+ #define INSN_PRIORITY_STATUS(INSN) (HID (INSN)->priority_status)
++#define INSN_MODEL_INDEX(INSN) (HID (INSN)->model_index)
+ 
+ typedef struct _haifa_deps_insn_data haifa_deps_insn_data_def;
+ typedef haifa_deps_insn_data_def *haifa_deps_insn_data_t;
+
+=== modified file 'gcc/sched-rgn.c'
+--- old/gcc/sched-rgn.c	2011-06-04 10:15:48 +0000
++++ new/gcc/sched-rgn.c	2012-02-08 23:38:13 +0000
+@@ -2943,7 +2943,7 @@
+ 
+   sched_extend_ready_list (rgn_n_insns);
+ 
+-  if (sched_pressure_p)
++  if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
+     {
+       sched_init_region_reg_pressure_info ();
+       for (bb = 0; bb < current_nr_blocks; bb++)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch
new file mode 100644
index 0000000000..1a5448403e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch
@@ -0,0 +1,28 @@
+2012-02-20  Andrew Stubbs  <ams@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_print_operand): Avoid null-pointer
+	dereference from MEM_SIZE.
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2012-02-09 00:47:59 +0000
++++ new/gcc/config/arm/arm.c	2012-02-20 15:32:26 +0000
+@@ -17446,6 +17446,7 @@
+ 	rtx addr;
+ 	bool postinc = FALSE;
+ 	unsigned align, memsize, align_bits;
++	rtx memsize_rtx;
+ 
+ 	gcc_assert (GET_CODE (x) == MEM);
+ 	addr = XEXP (x, 0);
+@@ -17460,7 +17461,8 @@
+ 	   instruction (for some alignments) as an aid to the memory subsystem
+ 	   of the target.  */
+ 	align = MEM_ALIGN (x) >> 3;
+-	memsize = INTVAL (MEM_SIZE (x));
++	memsize_rtx = MEM_SIZE (x);
++	memsize = memsize_rtx ? INTVAL (memsize_rtx) : 0;
+ 	
+ 	/* Only certain alignment specifiers are supported by the hardware.  */
+ 	if (memsize == 16 && (align % 32) == 0)
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch
new file mode 100644
index 0000000000..9bfd969df6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch
@@ -0,0 +1,126 @@
+2012-02-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	Backport from mainline.
+        2011-12-05  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (vfp3_const_double_for_fract_bits): Define.
+	* config/arm/arm-protos.h (vfp3_const_double_for_fract_bits): Declare.
+	* config/arm/constraints.md ("Dt"): New constraint.
+	* config/arm/predicates.md (const_double_vcvt_power_of_two_reciprocal):
+	New.
+	* config/arm/vfp.md (*arm_combine_vcvt_f32_s32): New.
+	(*arm_combine_vcvt_f32_u32): New.
+
+	LP:#900426
+
+	2011-12-06  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+        * config/arm/vfp.md (*combine_vcvt_f64_<FCVTI32typename>): Fix
+       formatting character for vmov.f64 case.
+
+2012-02-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	gcc/
+	* config/arm/arm.c (arm_print_operand): Remove wrongly merged code.
+	 (vfp3_const_double_for_fract_bits): Likewise.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h	2011-12-06 10:42:29 +0000
++++ new/gcc/config/arm/arm-protos.h	2012-02-22 13:31:54 +0000
+@@ -238,6 +238,7 @@
+ };
+ 
+ extern const struct tune_params *current_tune;
++extern int vfp3_const_double_for_fract_bits (rtx);
+ #endif /* RTX_CODE */
+ 
+ #endif /* ! GCC_ARM_PROTOS_H */
+
+=== modified file 'gcc/config/arm/constraints.md'
+--- old/gcc/config/arm/constraints.md	2011-12-06 10:42:29 +0000
++++ new/gcc/config/arm/constraints.md	2012-02-22 13:31:54 +0000
+@@ -29,7 +29,7 @@
+ ;; in Thumb-1 state: I, J, K, L, M, N, O
+ 
+ ;; The following multi-letter normal constraints have been used:
+-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
++;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
+ ;; in Thumb-1 state: Pa, Pb, Pc, Pd
+ ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
+ 
+@@ -291,6 +291,12 @@
+  (and (match_code "const_double")
+       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
+ 
++(define_constraint "Dt" 
++ "@internal
++  In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
++  (and (match_code "const_double")
++       (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
++
+ (define_memory_constraint "Ut"
+  "@internal
+   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md	2011-12-06 10:42:29 +0000
++++ new/gcc/config/arm/predicates.md	2012-02-22 13:31:54 +0000
+@@ -725,6 +725,11 @@
+   return true; 
+ })
+ 
++(define_predicate "const_double_vcvt_power_of_two_reciprocal"
++  (and (match_code "const_double")
++       (match_test "TARGET_32BIT && TARGET_VFP 
++       		    && vfp3_const_double_for_fract_bits (op)")))
++
+ (define_special_predicate "neon_struct_operand"
+   (and (match_code "mem")
+        (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
+
+=== modified file 'gcc/config/arm/vfp.md'
+--- old/gcc/config/arm/vfp.md	2011-12-06 10:42:29 +0000
++++ new/gcc/config/arm/vfp.md	2012-02-22 13:31:54 +0000
+@@ -1131,9 +1131,40 @@
+    (set_attr "type" "fcmpd")]
+ )
+ 
++;; Fixed point to floating point conversions. 
++(define_code_iterator FCVT [unsigned_float float])
++(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
++
++(define_insn "*combine_vcvt_f32_<FCVTI32typename>"
++  [(set (match_operand:SF 0 "s_register_operand" "=t")
++	(mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
++		 (match_operand 2 
++			"const_double_vcvt_power_of_two_reciprocal" "Dt")))]
++  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
++  "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
++ [(set_attr "predicable" "no")
++  (set_attr "type" "f_cvt")]
++)
++
++;; Not the ideal way of implementing this. Ideally we would be able to split
++;; this into a move to a DP register and then a vcvt.f64.i32
++(define_insn "*combine_vcvt_f64_<FCVTI32typename>"
++  [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
++	(mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
++		 (match_operand 2 
++		     "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
++  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math 
++  && !TARGET_VFP_SINGLE"
++  "@
++  vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
++  vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
++  vmov.f64\\t%P0, %1, %1\; vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
++ [(set_attr "predicable" "no")
++  (set_attr "type" "f_cvt")
++  (set_attr "length" "8")]
++)
+ 
+ ;; Store multiple insn used in function prologue.
+-
+ (define_insn "*push_multi_vfp"
+   [(match_parallel 2 "multi_register_push"
+     [(set (match_operand:BLK 0 "memory_operand" "=m")
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch
new file mode 100644
index 0000000000..5ce71a5138
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch
@@ -0,0 +1,80 @@
+ 2012-02-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+ 
+	LP:#922474
+	gcc/
+	* config/arm/sync.md (sync_lock_releasedi): Define.
+	(arm_sync_lock_releasedi): Likewise.
+	gcc/testsuite
+ 	Backport from mainline.
+        2012-01-30  Greta Yorsh  <Greta.Yorsh@arm.com>
+	* gcc.target/arm/di-longlong64-sync-withldrexd.c: Accept
+	new code generated for __sync_lock_release.
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md	2012-02-01 14:13:07 +0000
++++ new/gcc/config/arm/arm.md	2012-02-22 18:37:56 +0000
+@@ -157,6 +157,7 @@
+    (VUNSPEC_SYNC_OP               23)	; Represent a sync_<op>
+    (VUNSPEC_SYNC_NEW_OP           24)	; Represent a sync_new_<op>
+    (VUNSPEC_SYNC_OLD_OP           25)	; Represent a sync_old_<op>
++   (VUNSPEC_SYNC_RELEASE 	  26)	; Represent a sync_lock_release.
+   ]
+ )
+ 
+
+=== modified file 'gcc/config/arm/sync.md'
+--- old/gcc/config/arm/sync.md	2011-10-14 15:47:15 +0000
++++ new/gcc/config/arm/sync.md	2012-02-22 18:37:56 +0000
+@@ -494,3 +494,36 @@
+    (set_attr "conds" "unconditional")
+    (set_attr "predicable" "no")])
+ 
++(define_expand "sync_lock_releasedi"
++ [(match_operand:DI 0 "memory_operand")
++  (match_operand:DI 1 "s_register_operand")]
++ "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_MEMORY_BARRIER"
++ { 
++   struct arm_sync_generator generator;
++   rtx tmp1 = gen_reg_rtx (DImode);
++   generator.op = arm_sync_generator_omn;
++   generator.u.omn = gen_arm_sync_lock_releasedi;
++   arm_expand_sync (DImode, &generator, operands[1], operands[0], NULL, tmp1);
++   DONE;
++ }
++)
++
++(define_insn "arm_sync_lock_releasedi"
++ [(set (match_operand:DI 2 "s_register_operand" "=&r")
++       (unspec_volatile:DI [(match_operand:DI 1 "arm_sync_memory_operand" "+Q")
++       			    (match_operand:DI 0 "s_register_operand" "r")]
++			    VUNSPEC_SYNC_RELEASE))
++  (clobber (reg:CC CC_REGNUM))
++  (clobber (match_scratch:SI 3 "=&r"))]
++  "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_MEMORY_BARRIER"
++ {
++  return arm_output_sync_insn (insn, operands);
++ }
++ [(set_attr "sync_memory"          "1")
++  (set_attr "sync_result" 	   "2")
++  (set_attr "sync_t1" 		   "2")
++  (set_attr "sync_t2" 		   "3")
++  (set_attr "sync_new_value" 	   "0")
++  (set_attr "conds"             "clob")
++  (set_attr "predicable"          "no")]
++)
+
+=== modified file 'gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c'
+--- old/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c	2011-10-14 15:56:32 +0000
++++ new/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c	2012-02-22 18:37:56 +0000
+@@ -10,8 +10,8 @@
+ #include "../../gcc.dg/di-longlong64-sync-1.c"
+ 
+ /* We should be using ldrexd, strexd and no helpers or shorter ldrex.  */
+-/* { dg-final { scan-assembler-times "\tldrexd" 46 } } */
+-/* { dg-final { scan-assembler-times "\tstrexd" 46 } } */
++/* { dg-final { scan-assembler-times "\tldrexd" 48 } } */
++/* { dg-final { scan-assembler-times "\tstrexd" 48 } } */
+ /* { dg-final { scan-assembler-not "__sync_" } } */
+ /* { dg-final { scan-assembler-not "ldrex\t" } } */
+ /* { dg-final { scan-assembler-not "strex\t" } } */
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch
new file mode 100644
index 0000000000..092650dc9d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch
@@ -0,0 +1,46 @@
+ 2012-02-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+ 
+	Backport from mainline.
+	gcc/
+        2012-02-21  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+        Revert r183011
+        * config/arm/arm-cores.def (cortex-a15): Use generic Cortex tuning
+        parameters.
+        * config/arm/arm.c (arm_cortex_a15_tune): Remove.
+
+=== modified file 'gcc/config/arm/arm-cores.def'
+--- old/gcc/config/arm/arm-cores.def	2012-01-23 00:36:02 +0000
++++ new/gcc/config/arm/arm-cores.def	2012-02-22 15:53:56 +0000
+@@ -129,7 +129,7 @@
+ ARM_CORE("cortex-a7",	  cortexa7,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
+ ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
+-ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
++ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
+ ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, cortex)
+ ARM_CORE("cortex-r5",	  cortexr5,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c	2012-02-24 16:20:29 +0000
++++ new/gcc/config/arm/arm.c	2012-02-24 17:33:58 +0000
+@@ -988,17 +988,6 @@
+   arm_default_branch_cost
+ };
+ 
+-const struct tune_params arm_cortex_a15_tune =
+-{
+-  arm_9e_rtx_costs,
+-  NULL,
+-  1,						/* Constant limit.  */
+-  1,						/* Max cond insns.  */
+-  ARM_PREFETCH_NOT_BENEFICIAL,			/* TODO: Calculate correct values.  */
+-  false,					/* Prefer constant pool.  */
+-  arm_cortex_a5_branch_cost
+-};
+-
+ const struct tune_params arm_fa726te_tune =
+ {
+   arm_9e_rtx_costs,
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc b/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
new file mode 100644
index 0000000000..2434fb3a45
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
@@ -0,0 +1,96 @@
+GCC-4_6-BRANCH-LINARO-BACKPORTS ?= "        \
+file://linaro/gcc-4.6-linaro-r106720.patch \
+file://linaro/gcc-4.6-linaro-r106733.patch \
+file://linaro/gcc-4.6-linaro-r106737.patch \
+file://linaro/gcc-4.6-linaro-r106738.patch \
+file://linaro/gcc-4.6-linaro-r106739.patch \
+file://linaro/gcc-4.6-linaro-r106741.patch \
+file://linaro/gcc-4.6-linaro-r106742.patch \
+file://linaro/gcc-4.6-linaro-r106744.patch \
+file://linaro/gcc-4.6-linaro-r106746.patch \
+file://linaro/gcc-4.6-linaro-r106747.patch \
+file://linaro/gcc-4.6-linaro-r106750.patch \
+file://linaro/gcc-4.6-linaro-r106751.patch \
+file://linaro/gcc-4.6-linaro-r106753.patch \
+file://linaro/gcc-4.6-linaro-r106754.patch \
+file://linaro/gcc-4.6-linaro-r106755.patch \
+file://linaro/gcc-4.6-linaro-r106759.patch \
+file://linaro/gcc-4.6-linaro-r106762.patch \
+file://linaro/gcc-4.6-linaro-r106763.patch \
+file://linaro/gcc-4.6-linaro-r106764.patch \
+file://linaro/gcc-4.6-linaro-r106766.patch \
+file://linaro/gcc-4.6-linaro-r106768.patch \
+file://linaro/gcc-4.6-linaro-r106769.patch \
+file://linaro/gcc-4.6-linaro-r106770.patch \
+file://linaro/gcc-4.6-linaro-r106771.patch \
+file://linaro/gcc-4.6-linaro-r106772.patch \
+file://linaro/gcc-4.6-linaro-r106773.patch \
+file://linaro/gcc-4.6-linaro-r106775.patch \
+file://linaro/gcc-4.6-linaro-r106776.patch \
+file://linaro/gcc-4.6-linaro-r106777.patch \
+file://linaro/gcc-4.6-linaro-r106778.patch \
+file://linaro/gcc-4.6-linaro-r106781.patch \
+file://linaro/gcc-4.6-linaro-r106782.patch \
+file://linaro/gcc-4.6-linaro-r106783.patch \
+file://linaro/gcc-4.6-linaro-r106784.patch \
+file://linaro/gcc-4.6-linaro-r106785.patch \
+file://linaro/gcc-4.6-linaro-r106786.patch \
+file://linaro/gcc-4.6-linaro-r106787.patch \
+file://linaro/gcc-4.6-linaro-r106789.patch \
+file://linaro/gcc-4.6-linaro-r106792.patch \
+file://linaro/gcc-4.6-linaro-r106794.patch \
+file://linaro/gcc-4.6-linaro-r106796.patch \
+file://linaro/gcc-4.6-linaro-r106797.patch \
+file://linaro/gcc-4.6-linaro-r106798.patch \
+file://linaro/gcc-4.6-linaro-r106799.patch \
+file://linaro/gcc-4.6-linaro-r106800.patch \
+file://linaro/gcc-4.6-linaro-r106802.patch \
+file://linaro/gcc-4.6-linaro-r106803.patch \
+file://linaro/gcc-4.6-linaro-r106804.patch \
+file://linaro/gcc-4.6-linaro-r106805.patch \
+file://linaro/gcc-4.6-linaro-r106806.patch \
+file://linaro/gcc-4.6-linaro-r106807.patch \
+file://linaro/gcc-4.6-linaro-r106811.patch \
+file://linaro/gcc-4.6-linaro-r106814.patch \
+file://linaro/gcc-4.6-linaro-r106815.patch \
+file://linaro/gcc-4.6-linaro-r106816.patch \
+file://linaro/gcc-4.6-linaro-r106817.patch \
+file://linaro/gcc-4.6-linaro-r106818.patch \
+file://linaro/gcc-4.6-linaro-r106819.patch \
+file://linaro/gcc-4.6-linaro-r106820.patch \
+file://linaro/gcc-4.6-linaro-r106821.patch \
+file://linaro/gcc-4.6-linaro-r106825.patch \
+file://linaro/gcc-4.6-linaro-r106826.patch \
+file://linaro/gcc-4.6-linaro-r106827.patch \
+file://linaro/gcc-4.6-linaro-r106828.patch \
+file://linaro/gcc-4.6-linaro-r106829.patch \
+file://linaro/gcc-4.6-linaro-r106830.patch \
+file://linaro/gcc-4.6-linaro-r106831.patch \
+file://linaro/gcc-4.6-linaro-r106832.patch \
+file://linaro/gcc-4.6-linaro-r106833.patch \
+file://linaro/gcc-4.6-linaro-r106834.patch \
+file://linaro/gcc-4.6-linaro-r106836.patch \
+file://linaro/gcc-4.6-linaro-r106839.patch \
+file://linaro/gcc-4.6-linaro-r106840.patch \
+file://linaro/gcc-4.6-linaro-r106841.patch \
+file://linaro/gcc-4.6-linaro-r106842.patch \
+file://linaro/gcc-4.6-linaro-r106843.patch \
+file://linaro/gcc-4.6-linaro-r106844.patch \
+file://linaro/gcc-4.6-linaro-r106845.patch \
+file://linaro/gcc-4.6-linaro-r106846.patch \
+file://linaro/gcc-4.6-linaro-r106848.patch \
+file://linaro/gcc-4.6-linaro-r106853.patch \
+file://linaro/gcc-4.6-linaro-r106855.patch \
+file://linaro/gcc-4.6-linaro-r106860.patch \
+file://linaro/gcc-4.6-linaro-r106861.patch \
+file://linaro/gcc-4.6-linaro-r106862.patch \
+file://linaro/gcc-4.6-linaro-r106863.patch \
+file://linaro/gcc-4.6-linaro-r106864.patch \
+file://linaro/gcc-4.6-linaro-r106865.patch \
+file://linaro/gcc-4.6-linaro-r106869.patch \
+file://linaro/gcc-4.6-linaro-r106870.patch \
+file://linaro/gcc-4.6-linaro-r106872.patch \
+file://linaro/gcc-4.6-linaro-r106873.patch \
+file://linaro/gcc-4.6-linaro-r106874.patch \
+file://linaro/fix_linaro_106872.patch \
+"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc b/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc
new file mode 100644
index 0000000000..695079772e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc
@@ -0,0 +1,4 @@
+# this will prepend this layer to FILESPATH
+FILESEXTRAPATHS := "${THISDIR}/gcc-4.6"
+PRINC = "5"
+ARM_INSTRUCTION_SET = "arm"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.5.bb
new file mode 100644
index 0000000000..97e1a2bcbb
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.5.bb
@@ -0,0 +1,24 @@
+inherit cross-canadian
+
+require recipes-devtools/gcc/gcc-${PV}.inc
+require recipes-devtools/gcc/gcc-cross-canadian.inc
+require recipes-devtools/gcc/gcc-configure-sdk.inc
+require recipes-devtools/gcc/gcc-package-sdk.inc
+
+
+DEPENDS += "gmp-nativesdk mpfr-nativesdk libmpc-nativesdk elfutils-nativesdk"
+RDEPENDS_${PN} += "mpfr-nativesdk libmpc-nativesdk elfutils-nativesdk"
+
+SYSTEMHEADERS = "/usr/include"
+SYSTEMLIBS = "/lib/"
+SYSTEMLIB. = "/usr/lib/"
+
+EXTRA_OECONF += "--disable-libunwind-exceptions --disable-libssp \
+		--disable-libgomp --disable-libmudflap \
+		--with-mpfr=${STAGING_DIR_HOST}${layout_exec_prefix} \
+		--with-mpc=${STAGING_DIR_HOST}${layout_exec_prefix}"
+
+# to find libmpfr
+# export LD_LIBRARY_PATH = "{STAGING_DIR_HOST}${layout_exec_prefix}"
+
+PARALLEL_MAKE = ""
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.5.bb
new file mode 100644
index 0000000000..65ed3b4ba3
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.5.bb
@@ -0,0 +1,4 @@
+require recipes-devtools/gcc/gcc-cross_${PV}.bb
+require recipes-devtools/gcc/gcc-cross-initial.inc
+
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.5.bb
new file mode 100644
index 0000000000..8892288385
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.5.bb
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-cross_${PV}.bb
+require recipes-devtools/gcc/gcc-cross-intermediate.inc
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.5.bb
new file mode 100644
index 0000000000..fde78981f0
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.5.bb
@@ -0,0 +1,9 @@
+
+require recipes-devtools/gcc/gcc-${PV}.inc
+require recipes-devtools/gcc/gcc-cross4.inc
+
+EXTRA_OECONF += "--disable-libunwind-exceptions \
+                 --with-mpfr=${STAGING_DIR_NATIVE}${prefix_native} \
+                 --with-system-zlib "
+
+ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_DIR_TARGET}${target_includedir}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.5.bb
new file mode 100644
index 0000000000..c0b662677f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.5.bb
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-cross-initial_${PV}.bb
+require recipes-devtools/gcc/gcc-crosssdk-initial.inc
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.5.bb
new file mode 100644
index 0000000000..971f3ba0d6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.5.bb
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-cross-intermediate_${PV}.bb
+require recipes-devtools/gcc/gcc-crosssdk-intermediate.inc
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.5.bb
new file mode 100644
index 0000000000..40bdbf119f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.5.bb
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-cross_${PV}.bb
+require recipes-devtools/gcc/gcc-crosssdk.inc
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.5.bb
new file mode 100644
index 0000000000..e3b2d4ef76
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.5.bb
@@ -0,0 +1,8 @@
+
+require recipes-devtools/gcc/gcc-${PV}.inc
+require recipes-devtools/gcc/gcc-configure-runtime.inc
+require recipes-devtools/gcc/gcc-package-runtime.inc
+
+ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}"
+
+EXTRA_OECONF += "--disable-libunwind-exceptions"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc_4.5.bb
new file mode 100644
index 0000000000..19e8a25d0e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc_4.5.bb
@@ -0,0 +1,7 @@
+
+require recipes-devtools/gcc/gcc-${PV}.inc
+require recipes-devtools/gcc/gcc-configure-target.inc
+require recipes-devtools/gcc/gcc-package-target.inc
+
+ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/libgcc_4.5.bb b/toolchain-layer/recipes-devtools/gcc/libgcc_4.5.bb
new file mode 100644
index 0000000000..1579c8b962
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/libgcc_4.5.bb
@@ -0,0 +1,42 @@
+require recipes-devtools/gcc/gcc-${PV}.inc
+
+
+INHIBIT_DEFAULT_DEPS = "1"
+DEPENDS = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++"
+
+PACKAGES = "\
+  ${PN} \
+  ${PN}-dev \
+  "
+
+FILES_${PN} = "${base_libdir}/libgcc*.so.*"
+FILES_${PN}-dev = " \
+  ${base_libdir}/libgcc*.so \
+  ${libdir}/${TARGET_SYS}/${BINV}/crt* \
+  ${libdir}/${TARGET_SYS}/${BINV}/libgcov.a \
+  ${libdir}/${TARGET_SYS}/${BINV}/libgcc*"
+
+do_fetch[noexec] = "1"
+do_unpack[noexec] = "1"
+do_patch[noexec] = "1"
+do_configure[noexec] = "1"
+do_compile[noexec] = "1"
+
+do_install () {
+	target=`echo ${MULTIMACH_TARGET_SYS} | sed -e s#-nativesdk##`
+
+	# Install libgcc from our gcc-cross saved data
+	install -d ${D}${base_libdir} ${D}${libdir}
+	cp -fpPR ${STAGING_INCDIR_NATIVE}/gcc-build-internal-$target/* ${D}
+
+	# Move libgcc_s into /lib
+	mkdir -p ${D}${base_libdir}
+	if [ -f ${D}${libdir}/nof/libgcc_s.so ]; then
+		mv ${D}${libdir}/nof/libgcc* ${D}${base_libdir}
+	else
+		mv ${D}${libdir}/libgcc* ${D}${base_libdir} || true
+	fi
+}
+
+BBCLASSEXTEND = "nativesdk"
+
diff --git a/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend
new file mode 100644
index 0000000000..fc419b62bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend
@@ -0,0 +1,3 @@
+require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+require recipes-devtools/gcc/gcc-common-4.6.inc
+SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"