From aaae1616a09d359b52e929f944ca0ceb4bb7f831 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sun, 14 Aug 2011 21:55:09 +0200 Subject: [PATCH 3/4] Revert "fixed:[ios] Add memory barriers to cas() assembly to ensure alignment of memory accesses." This reverts commit 92bab651e2253d172879995b50985645b77fecd2. The build (OpenEmbedded `angstrom-2010.x` for `MACHINE = "beagleboard") fails with the following error. CPP Atomics.o make[1]: Entering directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+92bab651e2253d172879995b50985645b77fecd2/git/xbmc/windows' CPP GUIMediaWindow.o /tmp/ccrsywuV.s: Assembler messages: /tmp/ccrsywuV.s:40: Error: garbage following instruction -- `dmb ish' /tmp/ccrsywuV.s:48: Error: garbage following instruction -- `dmb ish' make[1]: *** [Atomics.o] Error 1 make[1]: Leaving directory `/oe/build-angstrom-next/angstrom-dev/work/armv7a-angstrom-linux-gnueabi/xbmc-10.05-r11+gitr0+92bab651e2253d172879995b50985645b77fecd2/git/xbmc/threads' make: *** [xbmc/threads/threads.a] Error 2 --- xbmc/threads/Atomics.cpp | 33 ++++++++++++++++----------------- 1 files changed, 16 insertions(+), 17 deletions(-) diff --git a/xbmc/threads/Atomics.cpp b/xbmc/threads/Atomics.cpp index 0a98a7e..0967eb2 100644 --- a/xbmc/threads/Atomics.cpp +++ b/xbmc/threads/Atomics.cpp @@ -49,23 +49,22 @@ long cas(volatile long *pAddr, long expectedVal, long swapVal) #elif defined(__arm__) long cas(volatile long* pAddr, long expectedVal, long swapVal) { - register long prev; - asm volatile ( - "dmb ish \n" // Memory barrier. Make sure all memory accesses appearing before this complete before any that appear after - "1: \n" - "ldrex %0, [%1] \n" // Load the current value of *pAddr(%1) into prev (%0) and lock pAddr, - "cmp %0, %2 \n" // Verify that the current value (%0) == old value (%2) - "bne 2f \n" // Bail if the two values are not equal [not as expected] - "strex r1, %3, [%1] \n" - "cmp r1, #0 \n" - "bne 1b \n" - "dmb ish \n" // Memory barrier. - "2: \n" - : "=&r" (prev) - : "r"(pAddr), "r"(expectedVal),"r"(swapVal) - : "r1" - ); - return prev; + return(__sync_val_compare_and_swap(pAddr, expectedVal, swapVal)); +// register long prev; +// asm volatile ( +// "1: \n" +// "ldrex %0, [%1] \n" /* Load the current value of *pAddr(%1) into prev (%0) and lock pAddr, */ +// "cmp %0, %2 \n" /* Verify that the current value (%0) == old value (%2) */ +// "bne 2f \n" /* Bail if the two values are not equal [not as expected] */ +// "strex r1, %3, [%1] \n" +// "cmp r1, #0 \n" +// "bne 1b \n" +// "2: " +// : "=&r" (prev) +// : "r"(pAddr), "r"(expectedVal),"r"(swapVal) +// : "r1" +// ); +// return prev; } #elif defined(__mips__) -- 1.7.2.5