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authorStefan Schmidt <stefan@datenfreihafen.org>2009-03-25 18:29:54 +0100
committerStefan Schmidt <stefan@datenfreihafen.org>2009-03-25 18:29:54 +0100
commit95e0882e2dfabe457550a885e0eb24893df31742 (patch)
treea34220ed25168022c53d9cb5697f3666a427b30c
parent451b1c687105655a4f2c9c477b05535041e25060 (diff)
parentac41ae95b1dbe54c05adf494c0fa44b3abbfeca3 (diff)
downloadopenembedded-95e0882e2dfabe457550a885e0eb24893df31742.tar.gz
openembedded-95e0882e2dfabe457550a885e0eb24893df31742.tar.bz2
openembedded-95e0882e2dfabe457550a885e0eb24893df31742.zip
Merge branch 'org.openembedded.dev' of git@git.openembedded.net:openembedded into org.openembedded.dev
-rw-r--r--classes/base.bbclass8
-rw-r--r--classes/cross.bbclass5
-rw-r--r--classes/distutils-base.bbclass26
-rw-r--r--classes/distutils-common-base.bbclass27
-rw-r--r--classes/distutils-native-base.bbclass3
-rw-r--r--classes/kernel.bbclass2
-rw-r--r--classes/qmake2.bbclass4
-rw-r--r--classes/qt4e.bbclass3
-rw-r--r--conf/bitbake.conf3
-rw-r--r--conf/checksums.ini12
-rw-r--r--conf/distro/include/angstrom-2008-preferred-versions.inc1
-rw-r--r--conf/distro/include/sane-srcrevs.inc4
-rw-r--r--conf/machine/wrap.conf3
-rw-r--r--docs/usermanual/chapters/common_use_cases.xml6
-rw-r--r--docs/usermanual/chapters/features.xml8
-rw-r--r--docs/usermanual/chapters/getting_oe.xml6
-rw-r--r--docs/usermanual/chapters/metadata.xml2
-rw-r--r--docs/usermanual/chapters/recipes.xml30
-rw-r--r--docs/usermanual/chapters/usage.xml50
-rw-r--r--docs/usermanual/reference/class_siteinfo.xml6
-rw-r--r--recipes/busybox/busybox.inc11
-rw-r--r--recipes/busybox/busybox_1.13.2.bb2
-rw-r--r--recipes/classpath/classpath-native_0.97.2.bb32
-rw-r--r--recipes/classpath/classpath-native_0.98.bb3
-rw-r--r--recipes/classpath/files/sun-security-getproperty_0.96.1.patch503
-rw-r--r--recipes/dsplink/ti-codec-engine_2.21.bb2
-rw-r--r--recipes/dsplink/ti-dmai_svn.bb (renamed from recipes/dsplink/ti-dmai_1.20.bb)29
-rw-r--r--recipes/gnome/epiphany_2.24.2.bb1
-rw-r--r--recipes/gnome/libsoup-2.4_2.26.0.bb6
-rw-r--r--recipes/gtk-webcore/midori.inc1
-rw-r--r--recipes/gtk-webcore/midori_git.bb2
-rw-r--r--recipes/hostap/hostap-daemon-0.6.9/defconfig144
-rw-r--r--recipes/hostap/hostap-daemon_0.6.9.bb45
-rw-r--r--recipes/libxml/libxml2-native.inc24
-rw-r--r--recipes/libxml/libxml2-native_2.7.2.bb2
-rw-r--r--recipes/linux-libc-headers/linux-libc-headers_2.6.29.bb49
-rw-r--r--recipes/linux/linux-2.6.27/boc01/005-090226-isl12024.patch (renamed from recipes/linux/linux-2.6.27/boc01/005-090217-isl12024.patch)356
-rw-r--r--recipes/linux/linux-2.6.27/boc01/012-090219-capsense.patch20
-rw-r--r--recipes/linux/linux-2.6.27/boc01/013-090306-lcd.patch (renamed from recipes/linux/linux-2.6.27/boc01/013-090209-lcd.patch)199
-rw-r--r--recipes/linux/linux-2.6.27/boc01/014-090209-pm-wakeup.patch195
-rw-r--r--recipes/linux/linux-2.6.27/boc01/defconfig31
-rw-r--r--recipes/linux/linux-omap-2.6.28/beagleboard/defconfig46
-rw-r--r--recipes/linux/linux-omap-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch206
-rw-r--r--recipes/linux/linux-omap-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch146
-rw-r--r--recipes/linux/linux-omap-2.6.29/DSS2.diff23964
-rw-r--r--recipes/linux/linux-omap-2.6.29/beagleboard/defconfig2238
-rw-r--r--recipes/linux/linux-omap-2.6.29/beagleboard/logo_linux_clut224.ppm73147
-rw-r--r--recipes/linux/linux-omap-2.6.29/cache-display-fix.patch238
-rw-r--r--recipes/linux/linux-omap-2.6.29/evm-mcspi-ts.diff132
-rw-r--r--recipes/linux/linux-omap-2.6.29/fix-install.patch23
-rw-r--r--recipes/linux/linux-omap-2.6.29/no-cortex-deadlock.patch77
-rw-r--r--recipes/linux/linux-omap-2.6.29/no-empty-flash-warnings.patch15
-rw-r--r--recipes/linux/linux-omap-2.6.29/no-harry-potter.diff11
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap-2430-lcd.patch11
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap1710h3/defconfig1224
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap2420h4/defconfig1119
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap2430sdp/defconfig1303
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap3-pandora/defconfig2186
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap3evm/defconfig2197
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap3evm/omap3evm-dss2.diff443
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap3evm/omap3evm-lcd-redtint.diff66
-rw-r--r--recipes/linux/linux-omap-2.6.29/omap5912osk/defconfig1098
-rw-r--r--recipes/linux/linux-omap-2.6.29/overo/defconfig1967
-rw-r--r--recipes/linux/linux-omap-2.6.29/read_die_ids.patch23
-rw-r--r--recipes/linux/linux-omap-2.6.29/timer-suppression.patch43
-rw-r--r--recipes/linux/linux-omap-2.6.29/touchscreen.patch22
-rw-r--r--recipes/linux/linux-omap-2.6.29/usbttyfix.patch29
-rw-r--r--recipes/linux/linux-omap/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch10365
-rw-r--r--recipes/linux/linux-omap/0001-Implement-downsampling-with-debugs.patch138
-rw-r--r--recipes/linux/linux-omap/0001-Removed-resolution-check-that-prevents-scaling-when.patch26
-rw-r--r--recipes/linux/linux-omap/0001-board-omap3beagle-set-i2c-3-to-100kHz.patch30
-rw-r--r--recipes/linux/linux-omap/0002-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch3809
-rw-r--r--recipes/linux/linux-omap/0003-DSS-Add-generic-DVI-panel.patch146
-rw-r--r--recipes/linux/linux-omap/0004-DSS-support-for-Beagle-Board.patch1605
-rw-r--r--recipes/linux/linux-omap/0005-DSS-Sharp-LS037V7DW01-LCD-Panel-driver.patch156
-rw-r--r--recipes/linux/linux-omap/0006-DSS-Support-for-OMAP3-SDP-board.patch1877
-rw-r--r--recipes/linux/linux-omap/0007-DSS-Support-for-OMAP3-EVM-board.patch255
-rw-r--r--recipes/linux/linux-omap/0008-DSS-Hacked-N810-support.patch1076
-rw-r--r--recipes/linux/linux-omap/0009-DSS-OMAPFB-allocate-fbmem-only-for-fb0-or-if-spes.patch121
-rw-r--r--recipes/linux/linux-omap/0010-DSS-OMAPFB-remove-extra-omapfb_setup_overlay-call.patch29
-rw-r--r--recipes/linux/linux-omap/0011-DSS-OMAPFB-fix-GFX_SYNC-to-be-compatible-with-DSS1.patch27
-rw-r--r--recipes/linux/linux-omap/0012-DSS-Add-comments-to-FAKE_VSYNC-to-make-things-more.patch27
-rw-r--r--recipes/linux/linux-omap/0013-DSS-OMAPFB-remove-extra-spaces.patch25
-rw-r--r--recipes/linux/linux-omap/0014-DSS-fix-clk_get_usecount.patch67
-rw-r--r--recipes/linux/linux-omap/0015-OMAPFB-remove-debug-print.patch25
-rw-r--r--recipes/linux/linux-omap/DSS2.diff23964
-rw-r--r--recipes/linux/linux-omap/beagleboard/defconfig188
-rw-r--r--recipes/linux/linux-omap/fix-clkrate-programming.diff57
-rw-r--r--recipes/linux/linux-omap/fix-dpll-m4.diff37
-rw-r--r--recipes/linux/linux-omap/fix-irq33.diff111
-rw-r--r--recipes/linux/linux-omap/mru-256MB.diff24
-rw-r--r--recipes/linux/linux-omap/mru-enable-overlay-optimalization.diff117
-rw-r--r--recipes/linux/linux-omap/mru-fix-display-panning.diff49
-rw-r--r--recipes/linux/linux-omap/mru-fix-timings.diff26
-rw-r--r--recipes/linux/linux-omap/mru-improve-pixclock-config.diff93
-rw-r--r--recipes/linux/linux-omap/mru-make-video-timings-selectable.diff312
-rw-r--r--recipes/linux/linux-omap/musb-support-high-bandwidth.patch.eml134
-rw-r--r--recipes/linux/linux-omap/oprofile-0.9.3.armv7.diff599
-rw-r--r--recipes/linux/linux-omap/strongly-ordered-memory.diff18
-rw-r--r--recipes/linux/linux-omap_2.6.28.bb2
-rw-r--r--recipes/linux/linux-omap_2.6.29.bb40
-rw-r--r--recipes/linux/linux-omap_git.bb37
-rw-r--r--recipes/linux/linux_2.6.27.bb7
-rw-r--r--recipes/llvm/llvm-2.5/fix-build.patch6
-rw-r--r--recipes/llvm/llvm_2.4.bb1
-rw-r--r--recipes/llvm/llvm_2.5.bb12
-rw-r--r--recipes/mpeg-encode/files/fixup.patch30
-rw-r--r--recipes/mpeg-encode/mpeg-encode_1.5b.bb2
-rw-r--r--recipes/netbase/netbase/qemuarm/interfaces13
-rw-r--r--recipes/netbase/netbase/qemux86/interfaces15
-rw-r--r--recipes/netbase/netbase_4.21.bb2
-rw-r--r--recipes/neuros-public/neuros-app-photoalbum_git.bb2
-rw-r--r--recipes/neuros-public/neuros-app-vplayer_git.bb2
-rw-r--r--recipes/neuros-public/neuros-lib-gui_git.bb2
-rw-r--r--recipes/neuros-public/neuros-lib-widgets_git.bb2
-rw-r--r--recipes/neuros-public/neuros-mainmenu_git.bb2
-rw-r--r--recipes/neuros-public/neuros-nwm_git.bb2
-rw-r--r--recipes/neuros-public/neuros-qt-plugins_git.bb2
-rw-r--r--recipes/python/python-pyrex_0.9.8.5.bb4
-rw-r--r--recipes/qmake/qmake2-native.inc15
-rw-r--r--recipes/qt4/files/0001-cross-compile.patch189
-rw-r--r--recipes/qt4/files/0002-fix-resinit-declaration.patch (renamed from recipes/qt4/qt4-x11-free-4.3.3/0002-fix-resinit-declaration.patch)0
-rw-r--r--recipes/qt4/files/0003-no-tools.patch41
-rw-r--r--recipes/qt4/files/0004-no-qmake.patch (renamed from recipes/qt4/qt-embedded-4.4.3/0004-no-qmake.patch)0
-rw-r--r--recipes/qt4/files/0005-fix-mkspecs.patch78
-rw-r--r--recipes/qt4/files/0006-freetype-host-includes.patch (renamed from recipes/qt4/qt-embedded-4.4.3/0006-freetype-host-includes.patch)0
-rw-r--r--recipes/qt4/files/0007-openssl-host-includes.patch (renamed from recipes/qt4/qt-embedded-4.4.3/0007-openssl-host-includes.patch)0
-rw-r--r--recipes/qt4/files/0008-backport-qt-lib-infix.patch166
-rw-r--r--recipes/qt4/files/0008-qt-lib-infix.patch (renamed from recipes/qt4/qt-embedded-4.4.3/qt-lib-infix.patch)0
-rw-r--r--recipes/qt4/qt-embedded-4.4.3/0001-cross-compile.patch32
-rw-r--r--recipes/qt4/qt-embedded-4.4.3/0003-no-tools.patch16
-rw-r--r--recipes/qt4/qt-embedded-4.4.3/0005-fix-mkspecs.patch101
-rw-r--r--recipes/qt4/qt-embedded-4.4.3/build-tools.patch28
-rw-r--r--recipes/qt4/qt-embedded-4.4.3/linux-oe-qmake.conf95
-rw-r--r--recipes/qt4/qt-embedded-4.4.3/qconfig-oe.h45
-rw-r--r--recipes/qt4/qt-embedded_4.4.3.bb2
-rw-r--r--recipes/qt4/qt4-embedded-4.4.3/0009-support-2bpp.patch (renamed from recipes/qt4/qt-embedded-4.4.3/support-2bpp.patch)0
-rw-r--r--recipes/qt4/qt4-embedded_4.4.3.bb (renamed from recipes/qt4/qt-embedded.inc)28
-rw-r--r--recipes/qt4/qt4-tools-native-4.4.3/qt-config.patch21
-rw-r--r--recipes/qt4/qt4-tools-native_4.4.3.bb69
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/configurable-cpu-extensions.patch34
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/cross-compile.patch159
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/fix-asm-constraints.patch16
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/fix-mkspecs.patch102
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/fix-resinit-declaration.patch16
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/gcc4_1.patch50
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/no-qmake.patch16
-rw-r--r--recipes/qt4/qt4-x11-free-4.1.2/no-tools.patch16
-rw-r--r--recipes/qt4/qt4-x11-free-4.3.3/0004-no-qmake.patch25
-rw-r--r--recipes/qt4/qt4-x11-free-4.3.3/0006-freetype-host-includes.patch23
-rw-r--r--recipes/qt4/qt4-x11-free-4.3.3/0007-openssl-host-includes.patch23
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0001-cross-compile.patch32
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0002-fix-resinit-declaration.patch25
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0003-no-tools.patch16
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0004-no-qmake.patch25
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0005-fix-mkspecs.patch101
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0006-freetype-host-includes.patch23
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/0007-openssl-host-includes.patch23
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/allow-configure-plugins.patch62
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/build-tools.patch28
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/linux-oe-qmake.conf95
-rw-r--r--recipes/qt4/qt4-x11-free-4.4.3/qconfig-oe.h45
-rw-r--r--recipes/qt4/qt4-x11-free.inc28
-rw-r--r--recipes/qt4/qt4-x11-free_4.1.2.bb141
-rw-r--r--recipes/qt4/qt4-x11-free_4.3.3.bb5
-rw-r--r--recipes/qt4/qt4-x11-free_4.4.3.bb31
-rw-r--r--recipes/qt4/qt4.inc (renamed from recipes/qt4/qt_packaging.inc)150
-rw-r--r--recipes/qt4/qt_configuration.inc82
-rw-r--r--recipes/qt4/qt_depends.inc3
-rw-r--r--recipes/qt4/qt_staging.inc58
-rw-r--r--recipes/rpm/rpm-4.4.2.3.inc96
-rw-r--r--recipes/rpm/rpm-native_4.4.2.3.bb5
-rw-r--r--recipes/rpm/rpm_4.4.2.3.bb100
-rw-r--r--recipes/strace/strace-4.5.14/strace-dont-include-linux-dirent-h.patch23
-rw-r--r--recipes/strace/strace-4.5.15/strace-dont-include-linux-dirent-h.patch23
-rw-r--r--recipes/strace/strace_4.5.14.bb3
-rw-r--r--recipes/strace/strace_4.5.15.bb2
-rw-r--r--recipes/uclibc/bfin-uclibc_svn.bb4
-rw-r--r--recipes/uclibc/files/ldso_use_arm_dl_linux_resolve_in_thumb_mode.patch21
-rw-r--r--recipes/uclibc/files/uclibc_ldso_use_O0.patch13
-rw-r--r--recipes/uclibc/uclibc-0.9.30.1/uClibc.distro1
-rw-r--r--recipes/uclibc/uclibc.inc7
-rw-r--r--recipes/uclibc/uclibc_0.9.29.bb4
-rw-r--r--recipes/uclibc/uclibc_0.9.30.1.bb6
-rw-r--r--recipes/uclibc/uclibc_0.9.30.bb6
-rw-r--r--recipes/uclibc/uclibc_nptl.bb3
-rw-r--r--recipes/uclibc/uclibc_svn.bb5
-rw-r--r--recipes/webkit/webkit-gtk_svn.bb2
-rw-r--r--recipes/zope/zope-3.3.1.inc45
-rw-r--r--recipes/zope/zope-native_3.3.1.bb7
-rw-r--r--recipes/zope/zope_3.3.1.bb48
191 files changed, 138090 insertions, 24271 deletions
diff --git a/classes/base.bbclass b/classes/base.bbclass
index f39059ecc0..9ec705bc1e 100644
--- a/classes/base.bbclass
+++ b/classes/base.bbclass
@@ -794,7 +794,9 @@ python base_do_unpack() {
try:
local = bb.data.expand(bb.fetch.localpath(url, localdata), localdata)
except bb.MalformedUrl, e:
- raise FuncFailed('Unable to generate local path for malformed uri: %s' % e)
+ raise bb.build.FuncFailed('Unable to generate local path for malformed uri: %s' % e)
+ if not local:
+ raise bb.build.FuncFailed('Unable to locate local file for %s' % url)
local = os.path.realpath(local)
ret = oe_unpack_file(local, localdata, url)
if not ret:
@@ -868,7 +870,7 @@ def base_get_metadata_svn_revision(path, d):
def base_get_metadata_git_branch(path, d):
import os
- branch = os.popen('cd %s; git symbolic-ref HEAD' % path).read()
+ branch = os.popen('cd %s; git symbolic-ref HEAD' % path).read().rstrip()
if len(branch) != 0:
return branch.replace("refs/heads/", "")
@@ -876,7 +878,7 @@ def base_get_metadata_git_branch(path, d):
def base_get_metadata_git_revision(path, d):
import os
- rev = os.popen("cd %s; git show-ref HEAD" % path).read().split(" ")[0]
+ rev = os.popen("cd %s; git show-ref HEAD" % path).read().split(" ")[0].rstrip()
if len(rev) != 0:
return rev
return "<unknown>"
diff --git a/classes/cross.bbclass b/classes/cross.bbclass
index 72a0fb7851..7debde6669 100644
--- a/classes/cross.bbclass
+++ b/classes/cross.bbclass
@@ -2,11 +2,6 @@
# no need for them to be a direct target of 'world'
EXCLUDE_FROM_WORLD = "1"
-# In order to keep TARGET_PREFIX decoupled from TARGET_SYS, let's force the
-# binary names to match the former, rather than relying on autoconf's implicit
-# prefixing based on the latter.
-EXTRA_OECONF_append = " --program-prefix=${TARGET_PREFIX}"
-
# Save PACKAGE_ARCH before changing HOST_ARCH
OLD_PACKAGE_ARCH := "${PACKAGE_ARCH}"
PACKAGE_ARCH = "${OLD_PACKAGE_ARCH}"
diff --git a/classes/distutils-base.bbclass b/classes/distutils-base.bbclass
index a08414aadf..2e151ded38 100644
--- a/classes/distutils-base.bbclass
+++ b/classes/distutils-base.bbclass
@@ -1,29 +1,5 @@
-EXTRA_OEMAKE = ""
DEPENDS += "${@["python-native python", ""][(bb.data.getVar('PACKAGES', d, 1) == '')]}"
RDEPENDS += "python-core"
-export STAGING_INCDIR
-export STAGING_LIBDIR
+inherit distutils-common-base
-def python_dir(d):
- import os, bb
- staging_incdir = bb.data.getVar( "STAGING_INCDIR", d, 1 )
- for majmin in "2.6 2.5 2.4 2.3".split():
- if os.path.exists( "%s/python%s" % ( staging_incdir, majmin ) ): return "python%s" % majmin
- raise "No Python in STAGING_INCDIR. Forgot to build python-native ?"
-
-PYTHON_DIR = "${@python_dir(d)}"
-
-PACKAGES = "${PN}-dev ${PN}-dbg ${PN}-doc ${PN}"
-
-FILES_${PN} = "${bindir}/* ${libdir}/* ${libdir}/${PYTHON_DIR}/*"
-
-FILES_${PN}-dev += "\
- ${libdir}/pkgconfig \
- ${libdir}/${PYTHON_DIR}/site-packages/*.la \
-"
-FILES_${PN}-dbg = "\
- ${libdir}/${PYTHON_DIR}/site-packages/.debug \
- ${libdir}/${PYTHON_DIR}/site-packages/*/.debug \
- ${libdir}/${PYTHON_DIR}/site-packages/*/*/.debug \
-"
diff --git a/classes/distutils-common-base.bbclass b/classes/distutils-common-base.bbclass
new file mode 100644
index 0000000000..068eac4de8
--- /dev/null
+++ b/classes/distutils-common-base.bbclass
@@ -0,0 +1,27 @@
+EXTRA_OEMAKE = ""
+
+export STAGING_INCDIR
+export STAGING_LIBDIR
+
+def python_dir(d):
+ import os, bb
+ staging_incdir = bb.data.getVar( "STAGING_INCDIR", d, 1 )
+ for majmin in "2.6 2.5 2.4 2.3".split():
+ if os.path.exists( "%s/python%s" % ( staging_incdir, majmin ) ): return "python%s" % majmin
+ raise "No Python in STAGING_INCDIR. Forgot to build python-native ?"
+
+PYTHON_DIR = "${@python_dir(d)}"
+
+PACKAGES = "${PN}-dev ${PN}-dbg ${PN}-doc ${PN}"
+
+FILES_${PN} = "${bindir}/* ${libdir}/* ${libdir}/${PYTHON_DIR}/*"
+
+FILES_${PN}-dev += "\
+ ${libdir}/pkgconfig \
+ ${libdir}/${PYTHON_DIR}/site-packages/*.la \
+"
+FILES_${PN}-dbg = "\
+ ${libdir}/${PYTHON_DIR}/site-packages/.debug \
+ ${libdir}/${PYTHON_DIR}/site-packages/*/.debug \
+ ${libdir}/${PYTHON_DIR}/site-packages/*/*/.debug \
+"
diff --git a/classes/distutils-native-base.bbclass b/classes/distutils-native-base.bbclass
new file mode 100644
index 0000000000..2703fe0740
--- /dev/null
+++ b/classes/distutils-native-base.bbclass
@@ -0,0 +1,3 @@
+DEPENDS += "${@["python-native", ""][(bb.data.getVar('PACKAGES', d, 1) == '')]}"
+
+inherit distutils-common-base
diff --git a/classes/kernel.bbclass b/classes/kernel.bbclass
index 4c1dbda35c..17e8941745 100644
--- a/classes/kernel.bbclass
+++ b/classes/kernel.bbclass
@@ -114,7 +114,7 @@ kernel_do_stage() {
mkdir -p ${STAGING_KERNEL_DIR}/include/pcmcia
cp -fR include/pcmcia/* ${STAGING_KERNEL_DIR}/include/pcmcia/
- for entry in drivers/crypto include/media include/acpi include/sound include/video include/scsi; do
+ for entry in drivers/crypto drivers/media include/media include/acpi include/sound include/video include/scsi; do
if [ -d $entry ]; then
mkdir -p ${STAGING_KERNEL_DIR}/$entry
cp -fR $entry/* ${STAGING_KERNEL_DIR}/$entry/
diff --git a/classes/qmake2.bbclass b/classes/qmake2.bbclass
index 8a443d062a..5ea31a976d 100644
--- a/classes/qmake2.bbclass
+++ b/classes/qmake2.bbclass
@@ -3,9 +3,9 @@
#
inherit qmake_base
-DEPENDS_prepend = "qmake2-native uicmoc4-native "
+DEPENDS_prepend = "qt4-tools-native "
-export QMAKESPEC = "${CROSS_DATADIR}/qt4/mkspecs/${TARGET_OS}-oe-g++"
+export QMAKESPEC = "${STAGING_DATADIR}/qt4/mkspecs/${TARGET_OS}-oe-g++"
export OE_QMAKE_UIC = "${STAGING_BINDIR_NATIVE}/uic4"
export OE_QMAKE_UIC3 = "${STAGING_BINDIR_NATIVE}/uic34"
export OE_QMAKE_MOC = "${STAGING_BINDIR_NATIVE}/moc4"
diff --git a/classes/qt4e.bbclass b/classes/qt4e.bbclass
index 8beef29df4..445ecbaa6a 100644
--- a/classes/qt4e.bbclass
+++ b/classes/qt4e.bbclass
@@ -1,9 +1,10 @@
-DEPENDS_prepend = "${@["qt-embedded ", ""][(bb.data.getVar('PN', d, 1) == 'qt-embedded')]}"
+DEPENDS_prepend = "${@["qt4-embedded ", ""][(bb.data.getVar('PN', d, 1) == 'qt4-embedded')]}"
inherit qmake2
QT_DIR_NAME = "qtopia"
# override variables set by qmake-base to compile Qt/Embedded apps
#
+export QMAKESPEC = "${STAGING_DATADIR}/qtopia/mkspecs/${TARGET_OS}-oe-g++"
export OE_QMAKE_INCDIR_QT = "${STAGING_INCDIR}/qtopia"
export OE_QMAKE_LIBDIR_QT = "${STAGING_LIBDIR}"
export OE_QMAKE_LIBS_QT = "qt"
diff --git a/conf/bitbake.conf b/conf/bitbake.conf
index 2d86f1ea07..7c159afcee 100644
--- a/conf/bitbake.conf
+++ b/conf/bitbake.conf
@@ -235,7 +235,8 @@ export MANIFEST = "${FILESDIR}/manifest"
FILE_DIRNAME = "${@os.path.dirname(bb.data.getVar('FILE', d))}"
FILESPATHBASE = "${FILE_DIRNAME}"
FILESPATHPKG = "${PF}:${P}:${PN}:${BP}:${BPN}:files:."
-FILESPATH = "${@':'.join([os.path.normpath(os.path.join(fp, p, o)) for fp in d.getVar('FILESPATHBASE', 1).split(':') for p in d.getVar('FILESPATHPKG', 1).split(':') for o in (d.getVar('OVERRIDES', 1) + ':').split(':') if os.path.exists(os.path.join(fp, p, o))])}:${FILESDIR}"
+FILESPATH = "${@':'.join([os.path.normpath(os.path.join(fp, p, o)) for fp in d.getVar('FILESPATHBASE', 1).split(':') for p in d.getVar('FILESPATHPKG', 1).split(':') for o in (d.getVar('OVERRIDES', 1) + ':').split(':') if os.path.exists(os.path.join(fp, p, o))])}"
+FILESDIR = "${@bb.which(d.getVar('FILESPATH', 1), '.')}"
##################################################################
# General work and output directories for the build system.
diff --git a/conf/checksums.ini b/conf/checksums.ini
index 914232926b..9ade7dfd5b 100644
--- a/conf/checksums.ini
+++ b/conf/checksums.ini
@@ -778,6 +778,10 @@ sha256=0f8f39a3c78a0d0ec947da1c19c7f8ecb41123755ff2bc31795a77946280f627
md5=3b3d8397c2c9a58fc59a90e2b49c651a
sha256=dd60bc66b1627d3cbd0950499017dfd57a0705bb12493bb0de2a7b9b5c0873bc
+[http://www.cosc.canterbury.ac.nz/greg.ewing/python/Pyrex/Pyrex-0.9.8.5.tar.gz]
+md5=3b3d8397c2c9a58fc59a90e2b49c651a
+sha256=dd60bc66b1627d3cbd0950499017dfd57a0705bb12493bb0de2a7b9b5c0873bc
+
[http://downloads.sourceforge.net/pyro/Pyro-3.8.1.tar.gz]
md5=8ab110b43f891c9664628133753c903a
sha256=d9e8073c7abb0fd9a94ec72c48f5bf4673de8e9333082dce6954d18a2fe35efd
@@ -10058,6 +10062,10 @@ sha256=f4754629eb70a63e9774ac97ebd28f3dea22fb5b422dd43d02ab5053d37ca61c
md5=ed669d96346dfc7d9f9fad079731853f
sha256=a99908d5765757ad6025b57d5ecf43b412aaaaf2ca379c02aafa33ca5c9d35c1
+[http://hostap.epitest.fi/releases/hostapd-0.6.9.tar.gz]
+md5=83630d11fa66ade9091f1b304fccd74c
+sha256=4430fe2c7a2176c6890ac3a726a8b3d234a77beb3ca987b4349c467331343e67
+
[http://kernel.org//pub/linux/utils/kernel/hotplug/hotplug-2004_03_29.tar.gz]
md5=167bd479a1ca30243c51ca088e0942b3
sha256=397e06eefc4639342e9f650cc47336ebc8c86a37fdcd9b857e55f99d37d8da9f
@@ -14694,6 +14702,10 @@ sha256=ae0d97c55efe7fce01273c97f8152af0deff5541e3bbf5b9ad98689112b54380
md5=d351e44709c9810b85e29b877f50968a
sha256=ae0d97c55efe7fce01273c97f8152af0deff5541e3bbf5b9ad98689112b54380
+[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.29.tar.bz2]
+md5=64921b5ff5cdadbccfcd3820f03be7d8
+sha256=58a5ea16d499fe06f90fcbf1d687d1235d2cb9bc28bf979867bd3faadf38fc3f
+
[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.9.tar.bz2]
md5=e921200f074ca97184e150ef5a4af825
sha256=f5dba6366e87e91234d1b0069cfea655b0a4cb37ea97f899226f16998e6ab9f1
diff --git a/conf/distro/include/angstrom-2008-preferred-versions.inc b/conf/distro/include/angstrom-2008-preferred-versions.inc
index b19794038c..a11c1d5691 100644
--- a/conf/distro/include/angstrom-2008-preferred-versions.inc
+++ b/conf/distro/include/angstrom-2008-preferred-versions.inc
@@ -13,7 +13,6 @@ PREFERRED_VERSION_gtk+ = "2.16.0"
PREFERRED_VERSION_gtkmm = "2.14.1"
PREFERRED_VERSION_libgemwidget = "1.0"
PREFERRED_VERSION_libgpephone = "0.4"
-PREFERRED_VERSION_libosip2 = "2.2.2"
PREFERRED_VERSION_libsdl-x11 = "1.2.11"
PREFERRED_VERSION_libtool = "2.2.4"
PREFERRED_VERSION_libtool-native = "2.2.4"
diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc
index 9eb5477401..1c01fbc43d 100644
--- a/conf/distro/include/sane-srcrevs.inc
+++ b/conf/distro/include/sane-srcrevs.inc
@@ -228,8 +228,8 @@ SRCREV_pn-tmut ?= "60"
SRCREV_pn-toscoterm ?= "f02add76f365a2fecd2dbefc230ceaab20244f96"
SRCREV_pn-u-boot-openmoko ?= "650149a53dbdd48bf6dfef90930c8ab182adb512"
SRCREV_pn-u-boot-openmoko-devel ?= "ba029a1426bfca169572bf80d50a8b190a6b0e19"
-SRCREV_pn-uclibc ?= "24279"
-SRCREV_pn-uclibc-initial ?= "24279"
+SRCREV_pn-uclibc ?= "25712"
+SRCREV_pn-uclibc-initial ?= "25712"
SRCREV_pn-usbpath ?= "3172"
SRCREV_pn-usbpath-native ?= "3172"
SRCREV_pn-vala-terminal ?= "94117f453ce884e9c30b611fae6fc19f85f98f2b"
diff --git a/conf/machine/wrap.conf b/conf/machine/wrap.conf
index 1fc75ebe94..8dbd6619d9 100644
--- a/conf/machine/wrap.conf
+++ b/conf/machine/wrap.conf
@@ -3,7 +3,8 @@
#@DESCRIPTION: Machine configuration for the PC Engines WRAP (Wireless Router Application Platform) boards.
TARGET_ARCH = "i486"
-PACKAGE_EXTRA_ARCHS = "i386 x86"
+
+require conf/machine/include/tune-x86.inc
PREFERRED_PROVIDER_virtual/kernel = "linux"
PREFERRED_PROVIDERS += "virtual/${TARGET_PREFIX}depmod:module-init-tools-cross"
diff --git a/docs/usermanual/chapters/common_use_cases.xml b/docs/usermanual/chapters/common_use_cases.xml
index 4497683fa9..143cbe0fe7 100644
--- a/docs/usermanual/chapters/common_use_cases.xml
+++ b/docs/usermanual/chapters/common_use_cases.xml
@@ -252,10 +252,10 @@ export LOCALDIR=$PWD/secret-isv
<screen>
DL_DIR = "${OEDIR}/sources"
-BBFILES := "${OEDIR}/openembedded/packages/*/*.bb ${LOCALDIR}/packages/*/*.bb"
+BBFILES := "${OEDIR}/openembedded/recipes/*/*.bb ${LOCALDIR}/recipes/*/*.bb"
BBFILE_COLLECTIONS = "upstream local"
-BBFILE_PATTERN_upstream = "^${OEDIR}/openembedded/packages/"
-BBFILE_PATTERN_local = "^${LOCALDIR}/packages/"
+BBFILE_PATTERN_upstream = "^${OEDIR}/openembedded/recipes/"
+BBFILE_PATTERN_local = "^${LOCALDIR}/recipes/"
BBFILE_PRIORITY_upstream = "5"
BBFILE_PRIORITY_local = "10"
BBMASK = ""
diff --git a/docs/usermanual/chapters/features.xml b/docs/usermanual/chapters/features.xml
index 8eecaa9ed4..3cbf1d8d1d 100644
--- a/docs/usermanual/chapters/features.xml
+++ b/docs/usermanual/chapters/features.xml
@@ -39,10 +39,10 @@
<para>This section is a stub, help us by expanding it</para>
<para><screen>
-BBFILES := "${OEDIR}/openembedded/packages/*/*.bb ${LOCALDIR}/packages/*/*.bb"
+BBFILES := "${OEDIR}/openembedded/recipes/*/*.bb ${LOCALDIR}/recipes/*/*.bb"
BBFILE_COLLECTIONS = "upstream local"
-BBFILE_PATTERN_upstream = "^${OEDIR}/openembedded/packages/"
-BBFILE_PATTERN_local = "^${LOCALDIR}/packages/"
+BBFILE_PATTERN_upstream = "^${OEDIR}/openembedded/recipes/"
+BBFILE_PATTERN_local = "^${LOCALDIR}/recipes/"
BBFILE_PRIORITY_upstream = "5"
BBFILE_PRIORITY_local = "10"
</screen></para>
@@ -75,4 +75,4 @@ MACHINE_FEATURES = "kernel26 apm alsa pcmcia bluetooth irda usbgadget"
<para>This section is a stub, help us by expanding it</para>
</section>
-</chapter> \ No newline at end of file
+</chapter>
diff --git a/docs/usermanual/chapters/getting_oe.xml b/docs/usermanual/chapters/getting_oe.xml
index d71ea71e72..ed7fd11005 100644
--- a/docs/usermanual/chapters/getting_oe.xml
+++ b/docs/usermanual/chapters/getting_oe.xml
@@ -232,7 +232,7 @@ $ vi build/conf/local.conf</screen>
distribution and the Openmoko gta01 machine:
<screen>
-BBFILES = "${OEBASE}/openembedded/packages/*/*.bb"
+BBFILES = "${OEBASE}/openembedded/recipes/*/*.bb"
DISTRO = "angstrom-2008.1"
MACHINE = "om-gta01"</screen>
</para>
@@ -297,11 +297,11 @@ MACHINE = "om-gta01"</screen>
<para>To build a single package, bypassing the long parse step (and
therefore its dependencies -- use with care):
- <screen>$ bitbake -b $OEBASE/openembedded/packages/blah/blah.bb</screen>
+ <screen>$ bitbake -b $OEBASE/openembedded/recipes/blah/blah.bb</screen>
</para>
<para>There are a few groups of special recipes located in subdirectories
- of the <filename>$OEBASE/openembedded/packages/</filename>
+ of the <filename>$OEBASE/openembedded/recipes/</filename>
directory. These groups are:
<variablelist>
diff --git a/docs/usermanual/chapters/metadata.xml b/docs/usermanual/chapters/metadata.xml
index 54fb523553..3e76b2ddbb 100644
--- a/docs/usermanual/chapters/metadata.xml
+++ b/docs/usermanual/chapters/metadata.xml
@@ -65,7 +65,7 @@
</varlistentry>
<varlistentry>
- <term><filename>packages/</filename></term>
+ <term><filename>recipes/</filename></term>
<listitem>
<para>Conatins all of the
<application>BitBake</application> <filename>.bb</filename>
diff --git a/docs/usermanual/chapters/recipes.xml b/docs/usermanual/chapters/recipes.xml
index c1ca456fa0..11078735eb 100644
--- a/docs/usermanual/chapters/recipes.xml
+++ b/docs/usermanual/chapters/recipes.xml
@@ -1081,9 +1081,9 @@ ${FILE_DIRNAME}/${PN}:${FILE_DIRNAME}/files:${FILE_DIRNAME}"</screen></para>
<para>First we'll create the myhelloworld.c file and a readme file.
We'll place this in the files subdirectory, which is one of the places
- that is searched for file:// URI's:<screen>mkdir packages/myhelloworld
-mkdir packages/myhelloworld/files
-cat &gt; packages/myhelloworld/files/myhelloworld.c
+ that is searched for file:// URI's:<screen>mkdir recipes/myhelloworld
+mkdir recipes/myhelloworld/files
+cat &gt; recipes/myhelloworld/files/myhelloworld.c
#include &lt;stdio.h&gt;
int main(int argc, char** argv)
@@ -1092,11 +1092,11 @@ int main(int argc, char** argv)
return 0;
}
^D
-cat &gt; packages/myhelloworld/files/README.txt
+cat &gt; recipes/myhelloworld/files/README.txt
Readme file for myhelloworld.
^D</screen></para>
- <para>Now we have a directory for our recipe, packages/myhelloworld, and
+ <para>Now we have a directory for our recipe, recipes/myhelloworld, and
we've created a files subdirectory in there to store our local files.
We've created two local files, the C source code for our helloworld
program and a readme file. Now we need to create the bitbake
@@ -1186,7 +1186,7 @@ PR = "r0"</screen></para>
</itemizedlist>
<para>We'll consider this release 0 and version 0.1 of a program called
- helloworld. So we'll name the recipe myhelloworld_0.1.bb:<screen>cat &gt; packages/myhelloworld/myhelloworld_0.1.bb
+ helloworld. So we'll name the recipe myhelloworld_0.1.bb:<screen>cat &gt; recipes/myhelloworld/myhelloworld_0.1.bb
DESCRIPTION = "Hello world program"
PR = "r0"
@@ -1203,13 +1203,13 @@ do_install() {
install -m 0644 ${WORKDIR}/README.txt ${D}${docdir}/myhelloworld
}
^D</screen>Now we are ready to build our package, hopefully it'll all work
- since it's such a simple example:<screen>~/oe%&gt; bitbake -b packages/myhelloworld/myhelloworld_0.1.bb
+ since it's such a simple example:<screen>~/oe%&gt; bitbake -b recipes/myhelloworld/myhelloworld_0.1.bb
NOTE: package myhelloworld-0.1: started
NOTE: package myhelloworld-0.1-r0: task do_fetch: started
NOTE: package myhelloworld-0.1-r0: task do_fetch: completed
NOTE: package myhelloworld-0.1-r0: task do_unpack: started
-NOTE: Unpacking /home/lenehan/devel/oe/local-packages/myhelloworld/files/helloworld.c to /home/lenehan/devel/oe/build/titan-glibc-25/tmp/work/myhelloworld-0.1-r0/
-NOTE: Unpacking /home/lenehan/devel/oe/local-packages/myhelloworld/files/README.txt to /home/lenehan/devel/oe/build/titan-glibc-25/tmp/work/myhelloworld-0.1-r0/
+NOTE: Unpacking /home/lenehan/devel/oe/local-recipes/myhelloworld/files/helloworld.c to /home/lenehan/devel/oe/build/titan-glibc-25/tmp/work/myhelloworld-0.1-r0/
+NOTE: Unpacking /home/lenehan/devel/oe/local-recipes/myhelloworld/files/README.txt to /home/lenehan/devel/oe/build/titan-glibc-25/tmp/work/myhelloworld-0.1-r0/
NOTE: package myhelloworld-0.1-r0: task do_unpack: completed
NOTE: package myhelloworld-0.1-r0: task do_patch: started
NOTE: package myhelloworld-0.1-r0: task do_patch: completed
@@ -1354,7 +1354,7 @@ tmp/work/myhelloworld-0.1-r0/install/myhelloworld/usr/bin/myhelloworld: ELF 32-b
of building an autotools based packages.</para>
<para>Let's take a look at the tuxnes recipe which is an example of a
- very simple autotools based recipe:<screen>%~oe&gt; cat packages/tuxnes/tuxnes_0.75.bb
+ very simple autotools based recipe:<screen>%~oe&gt; cat recipes/tuxnes/tuxnes_0.75.bb
DESCRIPTION = "Tuxnes Nintendo (8bit) Emulator"
HOMEPAGE = "http://prdownloads.sourceforge.net/tuxnes/tuxnes-0.75.tar.gz"
LICENSE = "GPLv2"
@@ -3366,7 +3366,7 @@ do_configure() {
via the <command>PV</command> variable).</para>
<para>For example if we were to ask bitbake to build procps and the
- following packages are available:<screen>~/oe%&gt; ls packages/procps
+ following packages are available:<screen>~/oe%&gt; ls recipes/procps
procps-3.1.15/ procps-3.2.1/ procps-3.2.5/ procps-3.2.7/ procps.inc
procps_3.1.15.bb procps_3.2.1.bb procps_3.2.5.bb procps_3.2.7.bb
~/oe%&gt;</screen>then we would expect it to select version
@@ -3397,7 +3397,7 @@ procps_3.1.15.bb procps_3.2.1.bb procps_3.2.5.bb procps_3.2.7.bb
version until it works. By adding:<screen>DEFAULT_PREFERENCE = "-1"</screen>to
the recipe this is what will happen. Bitbake will now ignore this version
(since all of the existing versions have a preference of 0). Note that you
- can still call bitbake directly on the recipe:<screen>bitbake -b packages/procps/procps_4.0.0.bb</screen>This
+ can still call bitbake directly on the recipe:<screen>bitbake -b recipes/procps/procps_4.0.0.bb</screen>This
enables you to test, and fix the package manually without having bitbake
automatically select normally.</para>
@@ -3406,7 +3406,7 @@ procps_3.1.15.bb procps_3.2.1.bb procps_3.2.5.bb procps_3.2.7.bb
example from glibc shows that this version has been disabled for the sh3
architecture because it doesn't support sh3. This will force bitbake to
try and select one of the other available versions of glibc
- instead:<screen>packages/glibc/glibc_2.3.2+cvs20040726.bb:DEFAULT_PREFERENCE_sh3 = "-99"</screen></para>
+ instead:<screen>recipes/glibc/glibc_2.3.2+cvs20040726.bb:DEFAULT_PREFERENCE_sh3 = "-99"</screen></para>
</section>
<section id="recipes_initscripts" xreflabel="initscripts">
@@ -3634,7 +3634,7 @@ which find
<listitem>
<para>The only directories that you can assume exist are those
listed in the default volatiles file:
- <command>packages/initscripts/initscripts-1.0/volatiles</command>.</para>
+ <command>recipes/initscripts/initscripts-1.0/volatiles</command>.</para>
</listitem>
<listitem>
@@ -3707,4 +3707,4 @@ which find
<para></para>
</section>
-</chapter> \ No newline at end of file
+</chapter>
diff --git a/docs/usermanual/chapters/usage.xml b/docs/usermanual/chapters/usage.xml
index 9fe20faf8c..5dd00d68e5 100644
--- a/docs/usermanual/chapters/usage.xml
+++ b/docs/usermanual/chapters/usage.xml
@@ -574,51 +574,51 @@ NOTE: Resolving missing task queue dependencies
NOTE: preferred version 2.5 of glibc not available (for item virtual/sh4-linux-libc-for-gcc)
NOTE: Preparing Runqueue
NOTE: Executing runqueue
-NOTE: Running task 208 of 226 (ID: 11, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 208 of 226 (ID: 11, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_fetch</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_fetch</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_fetch</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 209 of 226 (ID: 2, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 209 of 226 (ID: 2, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_unpack</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_unpack</emphasis>: started
NOTE: Unpacking /home/lenehan/devel/oe/sources/lzo-1.08.tar.gz to /home/lenehan/devel/oe/build/titan-glibc-25/tmp/work/lzo-1.08-r14/
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_unpack</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 216 of 226 (ID: 3, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 216 of 226 (ID: 3, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_patch</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_patch</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_patch</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 217 of 226 (ID: 4, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 217 of 226 (ID: 4, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_configure</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_configure</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_configure</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 218 of 226 (ID: 12, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 218 of 226 (ID: 12, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_qa_configure</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_qa_configure</emphasis>: started
NOTE: Checking sanity of the config.log file
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_qa_configure</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 219 of 226 (ID: 0, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 219 of 226 (ID: 0, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_compile</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_compile</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_compile</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 220 of 226 (ID: 1, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 220 of 226 (ID: 1, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_install</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_install</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_install</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 221 of 226 (ID: 5, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 221 of 226 (ID: 5, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_package</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_package</emphasis>: started
@@ -631,7 +631,7 @@ NOTE: Checking Package: lzo-locale
NOTE: DONE with PACKAGE QA
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_package</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 222 of 226 (ID: 8, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, <emphasis
+NOTE: Running task 222 of 226 (ID: 8, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, <emphasis
role="bold">do_package_write</emphasis>)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_package_write</emphasis>: started
@@ -642,23 +642,23 @@ Packaged contents of lzo-dev into /home/lenehan/devel/oe/build/titan-glibc-25/tm
NOTE: Not creating empty archive for lzo-locale-1.08-r14
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_package_write</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 223 of 226 (ID: 6, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, do_populate_staging)
+NOTE: Running task 223 of 226 (ID: 6, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, do_populate_staging)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_populate_staging</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_populate_staging</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 224 of 226 (ID: 9, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, do_qa_staging)
+NOTE: Running task 224 of 226 (ID: 9, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, do_qa_staging)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_qa_staging</emphasis>: started
NOTE: QA checking staging
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_qa_staging</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 225 of 226 (ID: 7, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, do_distribute_sources)
+NOTE: Running task 225 of 226 (ID: 7, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, do_distribute_sources)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_distribute_sources</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_distribute_sources</emphasis>: completed
NOTE: package lzo-1.08: completed
-NOTE: Running task 226 of 226 (ID: 10, /home/lenehan/devel/oe/build/titan-glibc-25/packages/lzo/lzo_1.08.bb, do_build)
+NOTE: Running task 226 of 226 (ID: 10, /home/lenehan/devel/oe/build/titan-glibc-25/recipes/lzo/lzo_1.08.bb, do_build)
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_build</emphasis>: started
NOTE: package lzo-1.08-r14: task <emphasis role="bold">do_build</emphasis>: completed
@@ -827,7 +827,7 @@ NOTE: build 200705041709: completed</screen><note>
<para>To determine the full list of tasks available for a specific recipe
you can run bitbake on the recipe and asking it for the full list of
- available tasks:<screen>~%&gt; bitbake -b packages/perl/perl_5.8.8.bb -c listtasks
+ available tasks:<screen>~%&gt; bitbake -b recipes/perl/perl_5.8.8.bb -c listtasks
NOTE: package perl-5.8.8: started
NOTE: package perl-5.8.8-r11: task do_listtasks: started
do_fetchall
@@ -1020,27 +1020,27 @@ NOTE: package perl-5.8.8: completed
<para>A typically development session might involve editing files in the
working directory and then recompiling until it all works:<screen>[<emphasis>... test ...</emphasis>]
-~%&gt; bitbake -b packages/testapp/testapp_4.3.bb -c compile -D
+~%&gt; bitbake -b recipes/testapp/testapp_4.3.bb -c compile -D
[<emphasis>... save a copy of main.c and make some changes ...</emphasis>]
~%&gt; vi tmp/work/testapp-4.3-r0/main.c
-~%&gt; bitbake -b packages/testapp/testapp_4.3.bb -c compile -D -f
+~%&gt; bitbake -b recipes/testapp/testapp_4.3.bb -c compile -D -f
[<emphasis>... create a patch and add it to the recipe ...</emphasis>]
-~%&gt; vi packages/testapp/testapp_4.3.bb
+~%&gt; vi recipes/testapp/testapp_4.3.bb
[<emphasis>... test from clean ...</emphasis>]
-~%&gt; bitbake -b packages/testapp/testapp_4.3.bb -c clean
-~%&gt; bitbake -b packages/testapp/testapp_4.3.bb
+~%&gt; bitbake -b recipes/testapp/testapp_4.3.bb -c clean
+~%&gt; bitbake -b recipes/testapp/testapp_4.3.bb
[<emphasis>... NOTE: How to create the patch is not covered at this point ...</emphasis>]</screen></para>
<para>Here's another example showing how you might go about fixing up the
- packaging in your recipe:<screen>~%&gt; bitbake -b packages/testapp/testapp_4.3.bb -c install -f
-~%&gt; bitbake -b packages/testapp/testapp_4.3.bb -c stage -f
+ packaging in your recipe:<screen>~%&gt; bitbake -b recipes/testapp/testapp_4.3.bb -c install -f
+~%&gt; bitbake -b recipes/testapp/testapp_4.3.bb -c stage -f
~%&gt; find tmp/work/testapp_4.3/install
...
-~%&gt; vi packages/testapp/testapp_4.3.bb</screen>At this stage you play with
+~%&gt; vi recipes/testapp/testapp_4.3.bb</screen>At this stage you play with
the <emphasis role="bold">PACKAGE_</emphasis> and <emphasis
role="bold">FILES_</emphasis> variables and then repeat the above
sequence.</para>
@@ -1103,7 +1103,7 @@ BB&gt;&gt; build net-snmp</screen>Note that you can use wildcards in the
role="bold">devshell</emphasis>"</screen></para>
<para>With the inclusion of this class you'll find that devshell is
- added as a new task that you can use on recipes:<screen>~%&gt; bitbake -b packages/lzo/lzo_1.08.bb -c listtasks
+ added as a new task that you can use on recipes:<screen>~%&gt; bitbake -b recipes/lzo/lzo_1.08.bb -c listtasks
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task do_listtasks: started
<emphasis role="bold">do_devshell</emphasis>
@@ -1130,7 +1130,7 @@ NOTE: package lzo-1.08-r14: task do_listtasks: completed
NOTE: package lzo-1.08: completed</screen></para>
<para>To bring up the devshell you call bitbake on a recipe and ask it
- for the devshell task:<screen>~%&gt; ./bb -b packages/lzo/lzo_1.08.bb -c devshell
+ for the devshell task:<screen>~%&gt; ./bb -b recipes/lzo/lzo_1.08.bb -c devshell
NOTE: package lzo-1.08: started
NOTE: package lzo-1.08-r14: task do_devshell: started
[<emphasis>... devshell will appear here ...</emphasis>]
@@ -1190,4 +1190,4 @@ bash: alias: `./configure': invalid alias name
<para>[To be done]</para>
</section>
-</chapter> \ No newline at end of file
+</chapter>
diff --git a/docs/usermanual/reference/class_siteinfo.xml b/docs/usermanual/reference/class_siteinfo.xml
index 4d66e85e7c..82dbd84f6e 100644
--- a/docs/usermanual/reference/class_siteinfo.xml
+++ b/docs/usermanual/reference/class_siteinfo.xml
@@ -148,7 +148,7 @@
<variablelist>
<varlistentry>
- <term>org.openembedded.dev/packages/&lt;packagename&gt;/site-&lt;version&gt;/</term>
+ <term>org.openembedded.dev/recipes/&lt;packagename&gt;/site-&lt;version&gt;/</term>
<listitem>
<para>This directory is for site files which are specific to a
@@ -158,7 +158,7 @@
</varlistentry>
<varlistentry>
- <term>org.openembedded.dev/packages/&lt;packagename&gt;/site/</term>
+ <term>org.openembedded.dev/recipes/&lt;packagename&gt;/site/</term>
<listitem>
<para>This directory is for site files which are specific to a
@@ -177,4 +177,4 @@
</varlistentry>
</variablelist>
</section>
-</section> \ No newline at end of file
+</section>
diff --git a/recipes/busybox/busybox.inc b/recipes/busybox/busybox.inc
index cb8eb53216..acf47f2178 100644
--- a/recipes/busybox/busybox.inc
+++ b/recipes/busybox/busybox.inc
@@ -142,10 +142,10 @@ pkg_postinst_${PN} () {
# so the update-alternatives script will get the utilities it needs
# (update-alternatives have no problem replacing links later anyway)
test -n 2> /dev/null || alias test='busybox test'
- if test "x$D" = "x"; then while read link; do if test ! -h "$link"; then case "$link" in /*/*/*) to="../../bin/busybox";; /bin/*) to="busybox";; /*/*) to="../bin/busybox";; esac; busybox ln -s $to $link; fi; done </etc/busybox.links; fi
+ if test "x$D" = "x"; then while read link; do if test ! -h "$link"; then case "$link" in /*/*/*) to="../../bin/busybox";; /bin/*) to="busybox";; /*/*) to="../bin/busybox";; /*) to="/bin/busybox";; esac; busybox ln -s $to $link; fi; done </etc/busybox.links; fi
# This adds the links, remember that this has to work when building an image too, hence the $D
- while read link; do case "$link" in /*/*/*) to="../../bin/busybox";; /bin/*) to="busybox";; /*/*) to="../bin/busybox";; esac; bn=`basename $link`; update-alternatives --install $link $bn $to 50; done <$D/etc/busybox.links
+ while read link; do case "$link" in /*/*/*) to="../../bin/busybox";; /bin/*) to="busybox";; /*/*) to="../bin/busybox";; /*) to="/bin/busybox";; esac; bn=`basename $link`; update-alternatives --install $link $bn $to 50; done <$D/etc/busybox.links
}
pkg_prerm_${PN} () {
@@ -173,6 +173,7 @@ pkg_prerm_${PN} () {
/*/*/*) to="../../bin/busybox";;
/bin/*) to="busybox";;
/*/*) to="../bin/busybox";;
+ /*) to="/bin/busybox";;
esac
bn=`basename $link`
sh /usr/bin/update-alternatives --remove $bn $to
@@ -183,6 +184,10 @@ PACKAGES =+ "${PN}-mdev"
FILES_${PN}-mdev = "${sysconfdir}/mdev ${sysconfdir}/mdev.conf ${sysconfdir}/init.d/mdev"
RDEPENDS_${PN}-mdev += "${PN}"
+PACKAGES =+ "${PN}-linuxrc"
+FILES_${PN}-linuxrc = "linuxrc"
+RDEPENDS_${PN}-linuxrc += "${PN}"
+
pkg_postinst_${PN}-mdev() {
if test "x$D" != "x"; then
OPT="-r $D"
@@ -192,5 +197,3 @@ fi
update-rc.d $OPT mdev start 06 S .
}
-
-
diff --git a/recipes/busybox/busybox_1.13.2.bb b/recipes/busybox/busybox_1.13.2.bb
index d3e7f9acde..8ecbc1e0e8 100644
--- a/recipes/busybox/busybox_1.13.2.bb
+++ b/recipes/busybox/busybox_1.13.2.bb
@@ -1,5 +1,5 @@
require busybox.inc
-PR = "r16"
+PR = "r17"
SRC_URI = "\
http://www.busybox.net/downloads/busybox-${PV}.tar.gz \
diff --git a/recipes/classpath/classpath-native_0.97.2.bb b/recipes/classpath/classpath-native_0.97.2.bb
new file mode 100644
index 0000000000..0024136b97
--- /dev/null
+++ b/recipes/classpath/classpath-native_0.97.2.bb
@@ -0,0 +1,32 @@
+require classpath-native.inc
+
+PR = "r4"
+
+# The code affected by the javanet-local patch
+# is usually not compiled. However if someone changes
+# to --enable-local-sockets it will.
+SRC_URI += "\
+ file://netif_16.patch;patch=1;pnum=0 \
+ file://SimpleName.diff;patch=1;pnum=0 \
+ file://javanet-local.patch;patch=1;pnum=0 \
+ file://sun-security-getproperty_0.96.1.patch;patch=1;pnum=0 \
+ file://ecj_java_dir.patch;patch=1 \
+ file://autotools.patch;patch=1 \
+ file://decimalformat.patch;patch=1 \
+ file://cp-byte-loophelper.patch;patch=1;pnum=0 \
+ file://miscompilation.patch;patch=1 \
+ "
+
+do_unpackpost() {
+ # Kind of patch: Moves package "org.w3c.dom.html2" to "org.w3c.dom.html"
+ mv external/w3c_dom/org/w3c/dom/html2 \
+ external/w3c_dom/org/w3c/dom/html
+
+ find examples/gnu/classpath/examples/html gnu/xml/dom/html2 external/w3c_dom/org/w3c/dom/html -name "*.java" \
+ -exec sed -i -e"s|org.w3c.dom.html2|org.w3c.dom.html|" {} \;
+
+ sed -i -e"s|org/w3c/dom/html2|org/w3c/dom/html|" external/w3c_dom/Makefile.am
+}
+
+addtask unpackpost after do_unpack before do_patch
+
diff --git a/recipes/classpath/classpath-native_0.98.bb b/recipes/classpath/classpath-native_0.98.bb
index dfbaad8369..710958a550 100644
--- a/recipes/classpath/classpath-native_0.98.bb
+++ b/recipes/classpath/classpath-native_0.98.bb
@@ -1,5 +1,8 @@
require classpath-native.inc
+# Deadlocks occur on at least amd64 hosts.
+DEFAULT_PREFERENCE = "-1"
+
PR = "r0"
# The code affected by the javanet-local patch
diff --git a/recipes/classpath/files/sun-security-getproperty_0.96.1.patch b/recipes/classpath/files/sun-security-getproperty_0.96.1.patch
new file mode 100644
index 0000000000..6af03e75ea
--- /dev/null
+++ b/recipes/classpath/files/sun-security-getproperty_0.96.1.patch
@@ -0,0 +1,503 @@
+Index: gnu/classpath/debug/Simple1LineFormatter.java
+===================================================================
+--- gnu/classpath/debug/Simple1LineFormatter.java.orig 2006-07-11 18:03:59.000000000 +0200
++++ gnu/classpath/debug/Simple1LineFormatter.java 2008-06-04 11:14:14.000000000 +0200
+@@ -38,8 +38,6 @@
+
+ package gnu.classpath.debug;
+
+-import gnu.java.security.action.GetPropertyAction;
+-
+ import java.io.PrintWriter;
+ import java.io.StringWriter;
+ import java.security.AccessController;
+@@ -51,6 +49,8 @@
+ import java.util.logging.Formatter;
+ import java.util.logging.LogRecord;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * A simple 1-line formatter to use instead of the 2-line SimpleFormatter used
+ * by default in the JDK logging handlers.
+Index: gnu/classpath/debug/SystemLogger.java
+===================================================================
+--- gnu/classpath/debug/SystemLogger.java.orig 2006-12-10 21:25:41.000000000 +0100
++++ gnu/classpath/debug/SystemLogger.java 2008-06-04 11:14:14.000000000 +0200
+@@ -38,13 +38,13 @@
+
+ package gnu.classpath.debug;
+
+-import gnu.java.security.action.GetPropertyAction;
+-
+ import java.security.AccessController;
+ import java.util.StringTokenizer;
+ import java.util.logging.Level;
+ import java.util.logging.Logger;
+
++import sun.security.action.GetPropertyAction;
++
+ public final class SystemLogger extends Logger
+ {
+ public static final SystemLogger SYSTEM = new SystemLogger();
+Index: gnu/java/security/PolicyFile.java
+===================================================================
+--- gnu/java/security/PolicyFile.java.orig 2006-07-11 18:03:59.000000000 +0200
++++ gnu/java/security/PolicyFile.java 2008-06-04 11:14:50.000000000 +0200
+@@ -39,7 +39,6 @@
+
+ import gnu.classpath.debug.Component;
+ import gnu.classpath.debug.SystemLogger;
+-import gnu.java.security.action.GetPropertyAction;
+
+ import java.io.File;
+ import java.io.IOException;
+@@ -72,6 +71,8 @@
+ import java.util.StringTokenizer;
+ import java.util.logging.Logger;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An implementation of a {@link java.security.Policy} object whose
+ * permissions are specified by a <em>policy file</em>.
+Index: gnu/java/security/action/GetPropertyAction.java
+===================================================================
+--- gnu/java/security/action/GetPropertyAction.java 2006-12-10 21:25:42.000000000 +0100
++++ /dev/null 1970-01-01 00:00:00.000000000 +0000
+@@ -1,89 +0,0 @@
+-/* GetPropertyAction.java
+- Copyright (C) 2004 Free Software Foundation, Inc.
+-
+-This file is part of GNU Classpath.
+-
+-GNU Classpath is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 2, or (at your option)
+-any later version.
+-
+-GNU Classpath is distributed in the hope that it will be useful, but
+-WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-General Public License for more details.
+-
+-You should have received a copy of the GNU General Public License
+-along with GNU Classpath; see the file COPYING. If not, write to the
+-Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-02110-1301 USA.
+-
+-Linking this library statically or dynamically with other modules is
+-making a combined work based on this library. Thus, the terms and
+-conditions of the GNU General Public License cover the whole
+-combination.
+-
+-As a special exception, the copyright holders of this library give you
+-permission to link this library with independent modules to produce an
+-executable, regardless of the license terms of these independent
+-modules, and to copy and distribute the resulting executable under
+-terms of your choice, provided that you also meet, for each linked
+-independent module, the terms and conditions of the license of that
+-module. An independent module is a module which is not derived from
+-or based on this library. If you modify this library, you may extend
+-this exception to your version of the library, but you are not
+-obligated to do so. If you do not wish to do so, delete this
+-exception statement from your version. */
+-
+-package gnu.java.security.action;
+-
+-import java.security.PrivilegedAction;
+-
+-/**
+- * PrivilegedAction implementation that calls System.getProperty() with
+- * the property name passed to its constructor.
+- *
+- * Example of use:
+- * <code>
+- * GetPropertyAction action = new GetPropertyAction("http.proxyPort");
+- * String port = AccessController.doPrivileged(action);
+- * </code>
+- */
+-public class GetPropertyAction implements PrivilegedAction<String>
+-{
+- String name;
+- String value = null;
+-
+- public GetPropertyAction()
+- {
+- }
+-
+- public GetPropertyAction(String propName)
+- {
+- setParameters(propName);
+- }
+-
+- public GetPropertyAction(String propName, String defaultValue)
+- {
+- setParameters(propName, defaultValue);
+- }
+-
+- public String run()
+- {
+- return System.getProperty(name, value);
+- }
+-
+- public GetPropertyAction setParameters(String propName)
+- {
+- this.name = propName;
+- this.value = null;
+- return this;
+- }
+-
+- public GetPropertyAction setParameters(String propName, String defaultValue)
+- {
+- this.name = propName;
+- this.value = defaultValue;
+- return this;
+- }
+-}
+Index: gnu/java/security/key/dss/DSSKey.java
+===================================================================
+--- gnu/java/security/key/dss/DSSKey.java.orig 2006-08-05 05:23:27.000000000 +0200
++++ gnu/java/security/key/dss/DSSKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.java.security.key.dss;
+
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.util.FormatUtil;
+
+ import java.math.BigInteger;
+@@ -49,6 +48,8 @@
+ import java.security.interfaces.DSAParams;
+ import java.security.spec.DSAParameterSpec;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * A base asbtract class for both public and private DSS (Digital Signature
+ * Standard) keys. It encapsulates the three DSS numbers: <code>p</code>,
+Index: gnu/java/security/key/dss/DSSPrivateKey.java
+===================================================================
+--- gnu/java/security/key/dss/DSSPrivateKey.java.orig 2006-07-11 18:04:00.000000000 +0200
++++ gnu/java/security/key/dss/DSSPrivateKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -40,7 +40,6 @@
+
+ import gnu.java.security.Configuration;
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.key.IKeyPairCodec;
+
+ import java.math.BigInteger;
+@@ -48,6 +47,8 @@
+ import java.security.PrivateKey;
+ import java.security.interfaces.DSAPrivateKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An object that embodies a DSS (Digital Signature Standard) private key.
+ *
+Index: gnu/java/security/key/dss/DSSPublicKey.java
+===================================================================
+--- gnu/java/security/key/dss/DSSPublicKey.java.orig 2006-07-11 18:04:00.000000000 +0200
++++ gnu/java/security/key/dss/DSSPublicKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.java.security.key.dss;
+
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.key.IKeyPairCodec;
+
+ import java.math.BigInteger;
+@@ -47,6 +46,8 @@
+ import java.security.PublicKey;
+ import java.security.interfaces.DSAPublicKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An object that embodies a DSS (Digital Signature Standard) public key.
+ *
+Index: gnu/java/security/key/rsa/GnuRSAKey.java
+===================================================================
+--- gnu/java/security/key/rsa/GnuRSAKey.java.orig 2006-07-11 18:04:00.000000000 +0200
++++ gnu/java/security/key/rsa/GnuRSAKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.java.security.key.rsa;
+
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.util.FormatUtil;
+
+ import java.math.BigInteger;
+@@ -47,6 +46,8 @@
+ import java.security.Key;
+ import java.security.interfaces.RSAKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * A base asbtract class for both public and private RSA keys.
+ */
+Index: gnu/java/security/key/rsa/GnuRSAPrivateKey.java
+===================================================================
+--- gnu/java/security/key/rsa/GnuRSAPrivateKey.java.orig 2006-07-11 18:04:00.000000000 +0200
++++ gnu/java/security/key/rsa/GnuRSAPrivateKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.java.security.key.rsa;
+
+ import gnu.java.security.Configuration;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.Registry;
+ import gnu.java.security.key.IKeyPairCodec;
+
+@@ -49,6 +48,8 @@
+ import java.security.interfaces.RSAPrivateCrtKey;
+ import java.security.interfaces.RSAPrivateKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An object that embodies an RSA private key.
+ * <p>
+Index: gnu/java/security/key/rsa/GnuRSAPublicKey.java
+===================================================================
+--- gnu/java/security/key/rsa/GnuRSAPublicKey.java.orig 2006-07-11 18:04:00.000000000 +0200
++++ gnu/java/security/key/rsa/GnuRSAPublicKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.java.security.key.rsa;
+
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.key.IKeyPairCodec;
+
+ import java.math.BigInteger;
+@@ -47,6 +46,8 @@
+ import java.security.PublicKey;
+ import java.security.interfaces.RSAPublicKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An object that encapsulates an RSA public key.
+ * <p>
+Index: gnu/javax/crypto/key/dh/GnuDHKey.java
+===================================================================
+--- gnu/javax/crypto/key/dh/GnuDHKey.java.orig 2006-07-11 18:03:59.000000000 +0200
++++ gnu/javax/crypto/key/dh/GnuDHKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.javax.crypto.key.dh;
+
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.util.FormatUtil;
+
+ import java.math.BigInteger;
+@@ -49,6 +48,8 @@
+ import javax.crypto.interfaces.DHKey;
+ import javax.crypto.spec.DHParameterSpec;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * A base asbtract class for both public and private Diffie-Hellman keys. It
+ * encapsulates the two DH numbers: <code>p</code>, and <code>g</code>.
+Index: gnu/javax/crypto/key/dh/GnuDHPrivateKey.java
+===================================================================
+--- gnu/javax/crypto/key/dh/GnuDHPrivateKey.java.orig 2006-07-11 18:03:59.000000000 +0200
++++ gnu/javax/crypto/key/dh/GnuDHPrivateKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -40,7 +40,6 @@
+
+ import gnu.java.security.Configuration;
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.key.IKeyPairCodec;
+
+ import java.math.BigInteger;
+@@ -48,6 +47,8 @@
+
+ import javax.crypto.interfaces.DHPrivateKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An implementation of the Diffie-Hellman private key.
+ * <p>
+Index: gnu/javax/crypto/key/dh/GnuDHPublicKey.java
+===================================================================
+--- gnu/javax/crypto/key/dh/GnuDHPublicKey.java.orig 2006-07-11 18:03:59.000000000 +0200
++++ gnu/javax/crypto/key/dh/GnuDHPublicKey.java 2008-06-04 11:14:14.000000000 +0200
+@@ -39,7 +39,6 @@
+ package gnu.javax.crypto.key.dh;
+
+ import gnu.java.security.Registry;
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.key.IKeyPairCodec;
+
+ import java.math.BigInteger;
+@@ -47,6 +46,8 @@
+
+ import javax.crypto.interfaces.DHPublicKey;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * An implementation of the Diffie-Hellman public key.
+ * <p>
+Index: gnu/javax/crypto/sasl/plain/PasswordFile.java
+===================================================================
+--- gnu/javax/crypto/sasl/plain/PasswordFile.java.orig 2006-07-11 18:03:59.000000000 +0200
++++ gnu/javax/crypto/sasl/plain/PasswordFile.java 2008-06-04 11:14:14.000000000 +0200
+@@ -38,7 +38,6 @@
+
+ package gnu.javax.crypto.sasl.plain;
+
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.javax.crypto.sasl.NoSuchUserException;
+ import gnu.javax.crypto.sasl.UserAlreadyExistsException;
+
+@@ -56,6 +55,8 @@
+ import java.util.NoSuchElementException;
+ import java.util.StringTokenizer;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * A representation of a Plain password file.
+ */
+Index: gnu/javax/net/ssl/provider/X509TrustManagerFactory.java
+===================================================================
+--- gnu/javax/net/ssl/provider/X509TrustManagerFactory.java.orig 2006-12-10 21:25:43.000000000 +0100
++++ gnu/javax/net/ssl/provider/X509TrustManagerFactory.java 2008-06-04 11:14:14.000000000 +0200
+@@ -66,11 +66,12 @@
+ import javax.net.ssl.TrustManagerFactorySpi;
+ import javax.net.ssl.X509TrustManager;
+
+-import gnu.java.security.action.GetPropertyAction;
+ import gnu.java.security.x509.X509CertPath;
+ import gnu.javax.net.ssl.NullManagerParameters;
+ import gnu.javax.net.ssl.StaticTrustAnchors;
+
++import sun.security.action.GetPropertyAction;
++
+ /**
+ * This class implements a {@link javax.net.ssl.TrustManagerFactory} engine
+ * for the ``JessieX509'' algorithm.
+Index: gnu/xml/aelfred2/XmlParser.java
+===================================================================
+--- gnu/xml/aelfred2/XmlParser.java.orig 2007-09-21 20:05:21.000000000 +0200
++++ gnu/xml/aelfred2/XmlParser.java 2008-06-04 11:14:14.000000000 +0200
+@@ -53,8 +53,6 @@
+
+ package gnu.xml.aelfred2;
+
+-import gnu.java.security.action.GetPropertyAction;
+-
+ import java.io.BufferedInputStream;
+ import java.io.CharConversionException;
+ import java.io.EOFException;
+@@ -74,6 +72,7 @@
+ import org.xml.sax.InputSource;
+ import org.xml.sax.SAXException;
+
++import sun.security.action.GetPropertyAction;
+
+ /**
+ * Parse XML documents and return parse events through call-backs.
+Index: sun/security/action/GetPropertyAction.java
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ sun/security/action/GetPropertyAction.java 2008-06-04 11:14:14.000000000 +0200
+@@ -0,0 +1,92 @@
++/* GetPropertyAction.java
++ Copyright (C) 2004, 2008 Free Software Foundation, Inc.
++
++This file is part of GNU Classpath.
++
++GNU Classpath is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 2, or (at your option)
++any later version.
++
++GNU Classpath is distributed in the hope that it will be useful, but
++WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GNU Classpath; see the file COPYING. If not, write to the
++Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
++02110-1301 USA.
++
++Linking this library statically or dynamically with other modules is
++making a combined work based on this library. Thus, the terms and
++conditions of the GNU General Public License cover the whole
++combination.
++
++As a special exception, the copyright holders of this library give you
++permission to link this library with independent modules to produce an
++executable, regardless of the license terms of these independent
++modules, and to copy and distribute the resulting executable under
++terms of your choice, provided that you also meet, for each linked
++independent module, the terms and conditions of the license of that
++module. An independent module is a module which is not derived from
++or based on this library. If you modify this library, you may extend
++this exception to your version of the library, but you are not
++obligated to do so. If you do not wish to do so, delete this
++exception statement from your version. */
++
++package sun.security.action;
++
++import java.security.PrivilegedAction;
++
++/**
++ * PrivilegedAction implementation that calls System.getProperty() with
++ * the property name passed to its constructor.
++ *
++ * Example of use:
++ * <code>
++ * GetPropertyAction action = new GetPropertyAction("http.proxyPort");
++ * String port = AccessController.doPrivileged(action);
++ * </code>
++ *
++ * Note: Usage of this class is discouraged as it is not a part of the
++ * J2SE API.
++ */
++public class GetPropertyAction implements PrivilegedAction<String>
++{
++ String name;
++ String value = null;
++
++ public GetPropertyAction()
++ {
++ }
++
++ public GetPropertyAction(String propName)
++ {
++ setParameters(propName);
++ }
++
++ public GetPropertyAction(String propName, String defaultValue)
++ {
++ setParameters(propName, defaultValue);
++ }
++
++ public String run()
++ {
++ return System.getProperty(name, value);
++ }
++
++ public GetPropertyAction setParameters(String propName)
++ {
++ this.name = propName;
++ this.value = null;
++ return this;
++ }
++
++ public GetPropertyAction setParameters(String propName, String defaultValue)
++ {
++ this.name = propName;
++ this.value = defaultValue;
++ return this;
++ }
++}
diff --git a/recipes/dsplink/ti-codec-engine_2.21.bb b/recipes/dsplink/ti-codec-engine_2.21.bb
index 8fcae851bb..f04c94fe45 100644
--- a/recipes/dsplink/ti-codec-engine_2.21.bb
+++ b/recipes/dsplink/ti-codec-engine_2.21.bb
@@ -8,7 +8,7 @@ RDEPENDS = "update-modules"
inherit module
# tconf from xdctools dislikes '.' in pwd :/
-PR = "r17"
+PR = "r18"
PV = "221"
# Get CE tarball from TI website, place in sources and calculate
diff --git a/recipes/dsplink/ti-dmai_1.20.bb b/recipes/dsplink/ti-dmai_svn.bb
index b95f241dd3..f6ff173a42 100644
--- a/recipes/dsplink/ti-dmai_1.20.bb
+++ b/recipes/dsplink/ti-dmai_svn.bb
@@ -4,23 +4,18 @@ LICENCE = "unknown"
require ti-paths.inc
-# https://www-a.ti.com/downloads/sds_support/applications_packages/dmai/dmai_1_20_00_06/dmai_setuplinux_1_20_00_06.bin
-# Install the above link and put the dmai_1_20_00_06.tar.gz file in the same directory as this recipe
-SRC_URI = "file://dmai_1_20_00_06.tar.gz \
- file://dmai-update-cpu-name.patch;patch=1 \
- file://dmai-update-fb-display.patch;patch=1 \
- file://dmai-update-v4l2-display.patch;patch=1 \
- file://dmai-do-not-panic-on-mixer-failure.patch;patch=1 \
- file://dmai-support-32bit-align.patch;patch=1 \
+SRC_URI = "svn://gforge.ti.com/svn/dmai/branches;module=BRIJESH_GIT_022309;proto=https;user=anonymous;pswd='' \
file://dmai-built-with-angstrom.patch;patch=1 \
file://loadmodules-ti-dmai-apps.sh \
file://unloadmodules-ti-dmai-apps.sh \
"
-S = "${WORKDIR}/dmai_1_20_00_06"
+SRCREV = "36"
+
+S = "${WORKDIR}/BRIJESH_GIT_022309/davinci_multimedia_application_interface/dmai"
# Yes, the xdc stuff still breaks with a '.' in PWD
-PV = "120"
-PR = "r14"
+PV = "120+svnr${SRCREV}"
+PR = "r15"
TARGET = "all"
TARGET_neuros-osd2 = " dm6446_al dm6446_db"
@@ -31,18 +26,6 @@ export CE_INSTALL_DIR="${STAGING_DIR}/${MULTIMACH_TARGET_SYS}/ti-codec-engine"
export FC_INSTALL_DIR="${STAGING_DIR}/${MULTIMACH_TARGET_SYS}/ti-codec-engine/cetools"
export CODEC_INSTALL_DIR="${STAGING_DIR}/${MULTIMACH_TARGET_SYS}/ti-codec-combos"
-do_compile_prepend_omap3evm() {
-
-#temp removal of sources that fail to build on evm3530
- if [ -e packages/ti/sdo/dmai/linux/omap3530/Resize.c ]; then
- rm packages/ti/sdo/dmai/linux/omap3530/Resize.c
- fi
-
- if [ -e packages/ti/sdo/dmai/linux/omap3530/Framecopy_accel.c ]; then
- rm packages/ti/sdo/dmai/linux/omap3530/Framecopy_accel.c
- fi
-}
-
do_compile() {
cd packages/ti/sdo/dmai
oe_runmake clean
diff --git a/recipes/gnome/epiphany_2.24.2.bb b/recipes/gnome/epiphany_2.24.2.bb
index d2d45475b7..a5ad6bef22 100644
--- a/recipes/gnome/epiphany_2.24.2.bb
+++ b/recipes/gnome/epiphany_2.24.2.bb
@@ -4,6 +4,7 @@ RDEPENDS = "gnome-vfs-plugin-http"
inherit gnome
+PR = "r1"
EXTRA_OECONF = "--with-engine=webkit --with-distributor-name=${DISTRO}"
diff --git a/recipes/gnome/libsoup-2.4_2.26.0.bb b/recipes/gnome/libsoup-2.4_2.26.0.bb
index 5f7fe4c6ca..5413d49bf8 100644
--- a/recipes/gnome/libsoup-2.4_2.26.0.bb
+++ b/recipes/gnome/libsoup-2.4_2.26.0.bb
@@ -3,6 +3,8 @@ SECTION = "x11/gnome/libs"
LICENSE = "GPL"
DEPENDS = "libproxy glib-2.0 gnutls libxml2"
+Pr = "r1"
+
inherit gnome
SRC_URI = "${GNOME_MIRROR}/libsoup/${@gnome_verdir("${PV}")}/libsoup-${PV}.tar.bz2"
@@ -12,6 +14,8 @@ do_stage() {
autotools_stage_all
}
-FILES_${PN} = "${libdir}/lib*.so.*"
+PACKAGES =+ "libsoup-gnome"
+FILES_libsoup-gnome = "${libdir}/libsoup-gnome*.so.*"
+FILES_${PN} = "${libdir}/libsoup-2*.so.*"
FILES_${PN}-dev = "${includedir}/ ${libdir}/"
FILES_${PN}-doc = "${datadir}/"
diff --git a/recipes/gtk-webcore/midori.inc b/recipes/gtk-webcore/midori.inc
index 793590babb..a241157c58 100644
--- a/recipes/gtk-webcore/midori.inc
+++ b/recipes/gtk-webcore/midori.inc
@@ -7,4 +7,5 @@ inherit autotools gtk-icon-cache pkgconfig
SRC_URI = "http://software.twotoasts.de/media/midori/midori-${PV}.tar.gz"
+EXTRA_OECONF = " --disable-hildon "
diff --git a/recipes/gtk-webcore/midori_git.bb b/recipes/gtk-webcore/midori_git.bb
index f4039a414f..5d08f1b6b7 100644
--- a/recipes/gtk-webcore/midori_git.bb
+++ b/recipes/gtk-webcore/midori_git.bb
@@ -3,7 +3,7 @@ require midori.inc
DEPENDS += "python-native python-docutils-native"
# increment PR every time SRCREV is updated!
-PR = "r0"
+PR = "r2"
PV = "0.1.2+${PR}+gitr${SRCREV}"
SRC_URI = "http://git.xfce.org/kalikiana/midori/snapshot/midori-${SRCREV}.tar.bz2"
diff --git a/recipes/hostap/hostap-daemon-0.6.9/defconfig b/recipes/hostap/hostap-daemon-0.6.9/defconfig
new file mode 100644
index 0000000000..0bf24782d1
--- /dev/null
+++ b/recipes/hostap/hostap-daemon-0.6.9/defconfig
@@ -0,0 +1,144 @@
+# Example hostapd build time configuration
+#
+# This file lists the configuration options that are used when building the
+# hostapd binary. All lines starting with # are ignored. Configuration option
+# lines must be commented out complete, if they are not to be included, i.e.,
+# just setting VARIABLE=n is not disabling that variable.
+#
+# This file is included in Makefile, so variables like CFLAGS and LIBS can also
+# be modified from here. In most cass, these lines should use += in order not
+# to override previous values of the variables.
+
+# Driver interface for Host AP driver
+CONFIG_DRIVER_HOSTAP=y
+
+# Driver interface for wired authenticator
+CONFIG_DRIVER_WIRED=y
+
+# Driver interface for madwifi driver
+#CONFIG_DRIVER_MADWIFI=y
+#CFLAGS += -I../../madwifi # change to the madwifi source directory
+
+# Driver interface for Prism54 driver
+CONFIG_DRIVER_PRISM54=y
+
+# Driver interface for drivers using the nl80211 kernel interface
+CONFIG_DRIVER_NL80211=y
+# driver_nl80211.c requires a rather new libnl (version 1.1) which may not be
+# shipped with your distribution yet. If that is the case, you need to build
+# newer libnl version and point the hostapd build to use it.
+#LIBNL=/usr/src/libnl
+#CFLAGS += -I$(LIBNL)/include
+#LIBS += -L$(LIBNL)/lib
+
+# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)
+#CONFIG_DRIVER_BSD=y
+#CFLAGS += -I/usr/local/include
+#LIBS += -L/usr/local/lib
+
+# Driver interface for no driver (e.g., RADIUS server only)
+#CONFIG_DRIVER_NONE=y
+
+# IEEE 802.11F/IAPP
+CONFIG_IAPP=y
+
+# WPA2/IEEE 802.11i RSN pre-authentication
+CONFIG_RSN_PREAUTH=y
+
+# PeerKey handshake for Station to Station Link (IEEE 802.11e DLS)
+CONFIG_PEERKEY=y
+
+# IEEE 802.11w (management frame protection)
+# This version is an experimental implementation based on IEEE 802.11w/D1.0
+# draft and is subject to change since the standard has not yet been finalized.
+# Driver support is also needed for IEEE 802.11w.
+#CONFIG_IEEE80211W=y
+
+# Integrated EAP server
+CONFIG_EAP=y
+
+# EAP-MD5 for the integrated EAP server
+CONFIG_EAP_MD5=y
+
+# EAP-TLS for the integrated EAP server
+CONFIG_EAP_TLS=y
+
+# EAP-MSCHAPv2 for the integrated EAP server
+CONFIG_EAP_MSCHAPV2=y
+
+# EAP-PEAP for the integrated EAP server
+CONFIG_EAP_PEAP=y
+
+# EAP-GTC for the integrated EAP server
+CONFIG_EAP_GTC=y
+
+# EAP-TTLS for the integrated EAP server
+CONFIG_EAP_TTLS=y
+
+# EAP-SIM for the integrated EAP server
+#CONFIG_EAP_SIM=y
+
+# EAP-AKA for the integrated EAP server
+#CONFIG_EAP_AKA=y
+
+# EAP-AKA' for the integrated EAP server
+# This requires CONFIG_EAP_AKA to be enabled, too.
+#CONFIG_EAP_AKA_PRIME=y
+
+# EAP-PAX for the integrated EAP server
+#CONFIG_EAP_PAX=y
+
+# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK)
+#CONFIG_EAP_PSK=y
+
+# EAP-SAKE for the integrated EAP server
+#CONFIG_EAP_SAKE=y
+
+# EAP-GPSK for the integrated EAP server
+#CONFIG_EAP_GPSK=y
+# Include support for optional SHA256 cipher suite in EAP-GPSK
+#CONFIG_EAP_GPSK_SHA256=y
+
+# EAP-FAST for the integrated EAP server
+# Note: Default OpenSSL package does not include support for all the
+# functionality needed for EAP-FAST. If EAP-FAST is enabled with OpenSSL,
+# the OpenSSL library must be patched (openssl-0.9.9-session-ticket.patch)
+# to add the needed functions.
+#CONFIG_EAP_FAST=y
+
+# Wi-Fi Protected Setup (WPS)
+CONFIG_WPS=y
+# Enable UPnP support for external WPS Registrars
+#CONFIG_WPS_UPNP=y
+
+# EAP-IKEv2
+#CONFIG_EAP_IKEV2=y
+
+# Trusted Network Connect (EAP-TNC)
+#CONFIG_EAP_TNC=y
+
+# PKCS#12 (PFX) support (used to read private key and certificate file from
+# a file that usually has extension .p12 or .pfx)
+CONFIG_PKCS12=y
+
+# RADIUS authentication server. This provides access to the integrated EAP
+# server from external hosts using RADIUS.
+CONFIG_RADIUS_SERVER=y
+
+# Build IPv6 support for RADIUS operations
+CONFIG_IPV6=y
+
+# IEEE Std 802.11r-2008 (Fast BSS Transition)
+#CONFIG_IEEE80211R=y
+
+# Use the hostapd's IEEE 802.11 authentication (ACL), but without
+# the IEEE 802.11 Management capability (e.g., madwifi or FreeBSD/net80211)
+CONFIG_DRIVER_RADIUS_ACL=y
+
+# IEEE 802.11n (High Throughput) support
+CONFIG_IEEE80211N=y
+
+# Remove debugging code that is printing out debug messages to stdout.
+# This can be used to reduce the size of the hostapd considerably if debugging
+# code is not needed.
+#CONFIG_NO_STDOUT_DEBUG=y
diff --git a/recipes/hostap/hostap-daemon_0.6.9.bb b/recipes/hostap/hostap-daemon_0.6.9.bb
new file mode 100644
index 0000000000..0b7a1925b3
--- /dev/null
+++ b/recipes/hostap/hostap-daemon_0.6.9.bb
@@ -0,0 +1,45 @@
+DESCRIPTION = "User space daemon for extended IEEE 802.11 management"
+HOMEPAGE = "http://hostap.epitest.fi"
+SECTION = "kernel/userland"
+PRIORITY = "optional"
+LICENSE = "GPL"
+DEPENDS = "libnl openssl ${@base_contains("COMBINED_FEATURES", "pci", "madwifi-ng", "",d)}"
+PR = "r0"
+
+DEFAULT_PREFERENCE = "-1"
+
+#we introduce MY_ARCH to get 'armv5te' as arch instead of the misleading 'arm' on armv5te builds
+MY_ARCH := "${PACKAGE_ARCH}"
+PACKAGE_ARCH = "${@base_contains('COMBINED_FEATURES', 'pci', '${MACHINE_ARCH}', '${MY_ARCH}', d)}"
+
+SRC_URI = "http://hostap.epitest.fi/releases/hostapd-${PV}.tar.gz \
+ file://defconfig \
+ file://init"
+
+S = "${WORKDIR}/hostapd-${PV}/hostapd"
+
+export HAS_PCI = "${@base_contains('COMBINED_FEATURES', 'pci', 1, 0,d)}"
+
+inherit update-rc.d
+INITSCRIPT_NAME=hostapd
+
+do_configure() {
+ install -m 0644 ${WORKDIR}/defconfig ${S}/.config
+ if [ "x$HAS_PCI" = "x1" ] ; then
+ echo "CONFIG_DRIVER_MADWIFI=y" >> .config
+ echo "CFLAGS += -I${STAGING_INCDIR}/madwifi-ng" >> .config
+ fi
+}
+
+do_compile() {
+ make
+}
+
+do_install() {
+ install -d ${D}${sbindir} ${D}${sysconfdir}/init.d
+ install -m 0644 ${S}/hostapd.conf ${D}${sysconfdir}
+ install -m 0755 ${S}/hostapd ${D}${sbindir}
+ install -m 0755 ${S}/hostapd_cli ${D}${sbindir}
+ install -m 755 ${WORKDIR}/init ${D}${sysconfdir}/init.d/hostapd
+}
+
diff --git a/recipes/libxml/libxml2-native.inc b/recipes/libxml/libxml2-native.inc
index b819f95fba..3f67152ca1 100644
--- a/recipes/libxml/libxml2-native.inc
+++ b/recipes/libxml/libxml2-native.inc
@@ -5,16 +5,22 @@ FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/libxml2-${PV}"
SRC_URI = "ftp://xmlsoft.org/libxml2/libxml2-${PV}.tar.gz"
S = "${WORKDIR}/libxml2-${PV}"
-inherit distutils-base autotools native pkgconfig
+inherit autotools native pkgconfig distutils-native-base
-EXTRA_OECONF = "\
- --with-python=${PYTHON_DIR} \
- --without-debug \
- --without-legacy \
- --with-catalog \
- --without-docbook \
- --with-c14n \
-"
+do_configure_prepend () {
+ EXTRA_LIBXML2_OECONF="\
+ --with-python=${PYTHON_DIR} \
+ --without-debug \
+ --without-legacy \
+ --with-catalog \
+ --without-docbook \
+ --with-c14n \
+ "
+}
+
+do_configure (){
+ autotools_do_configure ${EXTRA_LIBXML2_OECONF}
+}
do_stage () {
oe_runmake install
diff --git a/recipes/libxml/libxml2-native_2.7.2.bb b/recipes/libxml/libxml2-native_2.7.2.bb
index bcbfb6637b..24261d66f2 100644
--- a/recipes/libxml/libxml2-native_2.7.2.bb
+++ b/recipes/libxml/libxml2-native_2.7.2.bb
@@ -1,2 +1,2 @@
require libxml2-native.inc
-PR = "r1"
+PR = "r2"
diff --git a/recipes/linux-libc-headers/linux-libc-headers_2.6.29.bb b/recipes/linux-libc-headers/linux-libc-headers_2.6.29.bb
new file mode 100644
index 0000000000..6caddc0c2f
--- /dev/null
+++ b/recipes/linux-libc-headers/linux-libc-headers_2.6.29.bb
@@ -0,0 +1,49 @@
+require linux-libc-headers.inc
+
+INHIBIT_DEFAULT_DEPS = "1"
+DEPENDS += "unifdef-native"
+PR = "r0"
+
+SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.bz2 \
+ "
+
+S = "${WORKDIR}/linux-${PV}"
+
+set_arch() {
+ case ${TARGET_ARCH} in
+ alpha*) ARCH=alpha ;;
+ arm*) ARCH=arm ;;
+ cris*) ARCH=cris ;;
+ hppa*) ARCH=parisc ;;
+ i*86*) ARCH=i386 ;;
+ ia64*) ARCH=ia64 ;;
+ mips*) ARCH=mips ;;
+ m68k*) ARCH=m68k ;;
+ powerpc*) ARCH=powerpc ;;
+ s390*) ARCH=s390 ;;
+ sh*) ARCH=sh ;;
+ sparc64*) ARCH=sparc64 ;;
+ sparc*) ARCH=sparc ;;
+ x86_64*) ARCH=x86_64 ;;
+ avr32*) ARCH=avr32 ;;
+ bfin*) ARCH=blackfin ;;
+ esac
+}
+
+do_configure() {
+ set_arch
+ oe_runmake allnoconfig ARCH=$ARCH
+}
+
+do_compile () {
+}
+
+do_install() {
+ set_arch
+ oe_runmake headers_install INSTALL_HDR_PATH=${D}${exec_prefix} ARCH=$ARCH
+}
+
+do_stage () {
+ set_arch
+ oe_runmake headers_install INSTALL_HDR_PATH=${STAGING_DIR_HOST}${layout_prefix} ARCH=$ARCH
+}
diff --git a/recipes/linux/linux-2.6.27/boc01/005-090217-isl12024.patch b/recipes/linux/linux-2.6.27/boc01/005-090226-isl12024.patch
index 672e405de0..0c29cdc3de 100644
--- a/recipes/linux/linux-2.6.27/boc01/005-090217-isl12024.patch
+++ b/recipes/linux/linux-2.6.27/boc01/005-090226-isl12024.patch
@@ -1,3 +1,16 @@
+Index: linux-2.6.27/drivers/i2c/chips/at24.c
+===================================================================
+--- linux-2.6.27.orig/drivers/i2c/chips/at24.c
++++ linux-2.6.27/drivers/i2c/chips/at24.c
+@@ -114,6 +114,8 @@ static const struct i2c_device_id at24_i
+ { "spd", AT24_DEVICE_MAGIC(2048 / 8,
+ AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
+ { "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
++ /* Intersil RTC/Unique-ID isl12024 eeprom handled here */
++ { "isl12024",AT24_DEVICE_MAGIC(4096 / 8, AT24_FLAG_ADDR16) },
+ /* 24rf08 quirk is handled at i2c-core */
+ { "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
+ { "24c16", AT24_DEVICE_MAGIC(16384 / 8, 0) },
Index: linux-2.6.27/drivers/rtc/Kconfig
===================================================================
--- linux-2.6.27.orig/drivers/rtc/Kconfig
@@ -27,18 +40,124 @@ Index: linux-2.6.27/drivers/rtc/Makefile
obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o
obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o
obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o
+Index: linux-2.6.27/drivers/rtc/isl12024.h
+===================================================================
+--- /dev/null
++++ linux-2.6.27/drivers/rtc/isl12024.h
+@@ -0,0 +1,100 @@
++/*
++ * Intersil ISL12024 chip registers definitions
++ *
++ *
++ * Copyright (C) 2008, CenoSYS (www.cenosys.com).
++ * Guillaume Ligneul
++ * Guillaume.ligneul@gmail.com
++ *
++ * This software program is licensed subject to the GNU General Public License
++ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
++ */
++
++#ifndef ISL12024_H_
++#define ISL12024_H_
++
++#define ISL12024_REG_SR 0x3F /* status register */
++#define ISL12024_REG_Y2K 0x37
++#define ISL12024_REG_DW 0x36
++#define ISL12024_REG_YR 0x35
++#define ISL12024_REG_MO 0x34
++#define ISL12024_REG_DT 0x33
++#define ISL12024_REG_HR 0x32
++#define ISL12024_REG_MN 0x31
++#define ISL12024_REG_SC 0x30
++#define ISL12024_REG_DTR 0x13
++#define ISL12024_REG_ATR 0x12
++#define ISL12024_REG_INT 0x11
++#define ISL12024_REG_0 0x10
++#define ISL12024_REG_Y2K1 0x0F
++#define ISL12024_REG_DWA1 0x0E
++#define ISL12024_REG_YRA1 0x0D
++#define ISL12024_REG_MOA1 0x0C
++#define ISL12024_REG_DTA1 0x0B
++#define ISL12024_REG_HRA1 0x0A
++#define ISL12024_REG_MNA1 0x09
++#define ISL12024_REG_SCA1 0x08
++#define ISL12024_REG_Y2K0 0x07
++#define ISL12024_REG_DWA0 0x06
++#define ISL12024_REG_YRA0 0x05
++#define ISL12024_REG_MOA0 0x04
++#define ISL12024_REG_DTA0 0x03
++#define ISL12024_REG_HRA0 0x02
++#define ISL12024_REG_MNA0 0x01
++#define ISL12024_REG_SCA0 0x00
++
++#define ISL12024_CCR_BASE 0x30 /* Base address of CCR */
++#define ISL12024_ALM0_BASE 0x00 /* Base address of ALARM0 */
++
++#define ISL12024_SR_RTCF 0x01 /* Clock failure */
++#define ISL12024_SR_WEL 0x02 /* Write Enable Latch */
++#define ISL12024_SR_RWEL 0x04 /* Register Write Enable */
++#define ISL12024_SR_AL0 0x20 /* Alarm 0 match */
++
++#define ISL12024_DTR_DTR0 0x01
++#define ISL12024_DTR_DTR1 0x02
++#define ISL12024_DTR_DTR2 0x04
++
++#define ISL12024_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
++
++#define ISL12024_INT_AL0E 0x20 /* Alarm 0 enable */
++
++/* I2C ADDRESS */
++#define ISL12024_I2C_ADDR 0xDE
++#define ISL12024_I2C_EEPROM_ADDR 0x57
++
++/* device id section */
++#define ISL12024_REG_ID 0x20
++
++/* Register map */
++/* rtc section */
++#define ISL12024_REG_HR_MIL (1<<7) /* 24h/12h mode */
++#define ISL12024_REG_HR_PM (1<<5) /* PM/AM bit in 12h mode */
++//#define ISL12024_REG_DT 0x33 /* Date */
++//#define ISL12024_REG_MO 0x34 /* Month */
++//#define ISL12024_REG_YR 0x35 /* Year */
++//#define ISL12024_REG_DW 0x36
++//#define ISL12024_REG_Y2K 0x37
++#define ISL12024_RTC_SECTION_LEN 8
++
++/* control/status section */
++//#define ISL12024_REG_SR 0x3F
++//#define ISL12024_REG_SR_BAT (1<<7) /* battery */
++//#define ISL12024_REG_SR_AL1 (1<<6) /* alarm 0 */
++//#define ISL12024_REG_SR_AL0 (1<<5) /* alarm 1 */
++//#define ISL12024_REG_SR_OSCF (1<<4) /* oscillator fail */
++//#define ISL12024_REG_SR_RWEL (1<<2) /* register write enable latch */
++//#define ISL12024_REG_SR_WEL (1<<1) /* write enable latch */
++//#define ISL12024_REG_SR_RTCF (1<<0) /* rtc fail */
++//#define ISL12024_REG_INT 0x11
++
++#define CCR_SEC 0
++#define CCR_MIN 1
++#define CCR_HOUR 2
++#define CCR_MDAY 3
++#define CCR_MONTH 4
++#define CCR_YEAR 5
++#define CCR_WDAY 6
++#define CCR_Y2K 7
++
++#endif /*ISL12024_H_*/
Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
===================================================================
--- /dev/null
+++ linux-2.6.27/drivers/rtc/rtc-isl12024.c
-@@ -0,0 +1,517 @@
+@@ -0,0 +1,541 @@
+/*
+ * Intersil ISL12024 class driver
+ *
+ *
+ * Copyright (C) 2007, CenoSYS (www.cenosys.com).
-+ * Guillaume Ligneul
-+ * Guillaume.ligneul@gmail.com
++ *
++ * Guillaume Ligneul <guillaume.ligneul@gmail.com>
++ * Sylvain Giroudon <sylvain.giroudon@goobie.fr>
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
@@ -57,33 +176,30 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+#define DBG 1
+#undef DBG
+
-+static u8 buf_id[ISL12024_RTC_SECTION_LEN] = { 0 ,};
-+
+#define DRV_NAME "isl12024"
-+#define DRV_VERSION "0.1"
++#define DRV_VERSION "0.2"
+
+/* i2c configuration */
-+
+static const unsigned short normal_i2c[] = {
+ ISL12024_I2C_ADDR >>1, I2C_CLIENT_END
+};
+I2C_CLIENT_INSMOD;
+
-+/* Procfs management */
-+static struct proc_dir_entry * root_proc = NULL;
-+static struct proc_dir_entry * entry_proc = NULL;
-+static int read_proc (char * page, char ** start, off_t off, int count, int * eof, void * data);
-+
+static int isl12024_get_status(struct i2c_client *client, unsigned char *sr);
+static int isl12024_fix_osc(struct i2c_client *client);
+
-+
+static int isl12024_attach_adapter(struct i2c_adapter *adapter);
+static int isl12024_detach_client(struct i2c_client *client);
+
-+// To debug (may be add in includ/linux/i2c-id.h)
++
++/* Bufer to store unique identifier in */
++static u8 buf_id[ISL12024_RTC_SECTION_LEN] = { 0 };
++
++
++// To debug (may be added in include/linux/i2c-id.h)
+#define I2C_DRIVERID_ISL12024 97
+
++
+static struct i2c_driver isl12024_driver = {
+ .driver = {
+ .name = DRV_NAME,
@@ -93,6 +209,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ .detach_client = &isl12024_detach_client,
+};
+
++
+int
+isl12024_i2c_read_regs(struct i2c_client *client, u8 reg, u8 buf[],
+ unsigned len)
@@ -151,14 +268,16 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+
+ memcpy(&i2c_buf[2], &buf[0], len );
+
-+
+ ret = i2c_transfer(client->adapter, msgs, 1);
-+ printk(KERN_INFO "i2c_transfer %d\n",ret);
++ if ( ret < 0 )
++ printk(KERN_ERR DRV_NAME ": i2c_transfer failed (%d)\n", ret);
++
+ return ret;
+}
+
+EXPORT_SYMBOL(isl12024_i2c_set_regs);
+
++
+static int isl12024_i2c_validate_client(struct i2c_client *client)
+{
+ u8 regs[ISL12024_RTC_SECTION_LEN] = { 0, };
@@ -183,6 +302,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return 0;
+}
+
++
+static int isl12024_read_time(struct i2c_client *client,
+ struct rtc_time *tm)
+{
@@ -190,8 +310,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ int err;
+ u8 regs[ISL12024_RTC_SECTION_LEN] = { 0, };
+
-+ printk(KERN_INFO "%s\n ",__FUNCTION__ );
-+
++ //printk(KERN_INFO DRV_NAME "%s\n ",__FUNCTION__ );
+
+ if (isl12024_get_status(client, &sr) < 0) {
+ dev_err(&client->dev, "%s: reading SR failed\n", __func__);
@@ -203,7 +322,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+#ifdef DBG
+ int i;
+ for(i=0; i<ISL12024_RTC_SECTION_LEN; i++)
-+ printk(KERN_INFO "0x%2X\n", regs[i]);
++ printk(KERN_INFO DRV_NAME "0x%2X\n", regs[i]);
+#endif
+
+ if (err < 0) {
@@ -234,6 +353,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return rtc_valid_tm(tm);
+}
+
++
+static int isl12024_get_status(struct i2c_client *client, unsigned char *sr)
+{
+ static unsigned char sr_addr[2] = { 0, ISL12024_REG_SR };
@@ -252,6 +372,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return 0;
+}
+
++
+static int isl12024_set_datetime(struct i2c_client *client, struct rtc_time *tm,
+ int datetoo, u8 reg_base, unsigned char alm_enable)
+{
@@ -373,6 +494,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return 0;
+}
+
++
+static int isl12024_fix_osc(struct i2c_client *client)
+{
+ int err;
@@ -381,24 +503,27 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ tm.tm_hour = tm.tm_min = tm.tm_sec = 0;
+
+ err = isl12024_set_datetime(client, &tm, 0, ISL12024_CCR_BASE, 0);
-+ if (err < 0)
-+ printk(KERN_INFO "unable to restart the oscillator\n");
++ if ( err < 0 )
++ printk(KERN_ERR DRV_NAME ": Unable to restart the oscillator (%d)\n", err);
+
+ return err;
+}
+
++
+static int isl12024_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ return isl12024_read_time(to_i2c_client(dev), tm);
+
+}
+
++
+static int isl12024_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ return isl12024_set_datetime(to_i2c_client(dev),
+ tm, 1, ISL12024_CCR_BASE, 0);
+}
+
++
+static int
+isl12024_rtc_proc(struct device *dev, struct seq_file *seq)
+{
@@ -408,32 +533,48 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return 0;
+}
+
++
+static const struct rtc_class_ops isl12024_rtc_ops = {
+ .proc = isl12024_rtc_proc,
+ .read_time = isl12024_rtc_read_time,
+ .set_time = isl12024_rtc_set_time,
+};
+
-+static int read_proc (char * page, char ** start, off_t off, int count, int * eof, void * data)
++static int
++read_proc(char * page, char ** start, off_t off, int count, int * eof, void * data)
+{
-+ int i=0;
++ int len = 0;
++ int i;
+
-+ printk("id: 0x");
-+ for(i=0;i<ISL12024_RTC_SECTION_LEN;i++)
-+ printk("%02X",buf_id[i]);
-+ printk("\n");
-+ return 0;
++ for (i = 0; i < ISL12024_RTC_SECTION_LEN; i++)
++ len += sprintf(page+len, "%02X", buf_id[i]);
++ len += sprintf(page+len, "\n");
++
++ len -= off;
++ if ( len < count ) {
++ *eof = 1;
++ if ( len <= 0 )
++ return 0;
++ } else {
++ len = count;
++ }
++
++ *start = page + off;
++
++ return len;
+}
+
++
+static int
+isl12024_probe(struct i2c_adapter *adapter, int addr, int kind)
+{
-+
+ int rc = 0;
+ int err = 0;
+ unsigned char sr;
+ struct i2c_client *new_client = NULL;
+ struct rtc_device *rtc = NULL;
++ struct proc_dir_entry *proc_root;
++ struct proc_dir_entry *proc_entry;
+
+ if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
+ rc = -ENODEV;
@@ -467,7 +608,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ &isl12024_rtc_ops, THIS_MODULE);
+
+ if (IS_ERR(rtc)) {
-+ printk("Error during rtc registration\n");
++ printk(KERN_ERR DRV_NAME ": Error during rtc registration\n");
+ rc = PTR_ERR(rtc);
+ goto failout;
+ }
@@ -475,30 +616,28 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ i2c_set_clientdata(new_client, rtc);
+
+ /* Check for power failures and eventualy enable the osc */
-+ if ((err = isl12024_get_status(new_client, &sr)) == 0) {
-+ if (sr & ISL12024_SR_RTCF) {
-+ printk(KERN_INFO "power failure detected, "
-+ "please set the clock\n");
-+ udelay(50);
-+ isl12024_fix_osc(new_client);
-+ }
++ if ((err = isl12024_get_status(new_client, &sr)) == 0) {
++ if (sr & ISL12024_SR_RTCF) {
++ printk(KERN_INFO DRV_NAME ": Power failure detected, please set the clock\n");
++ udelay(50);
++ isl12024_fix_osc(new_client);
+ }
-+ else
-+ printk(KERN_INFO "couldn't read status\n");
-+
-+ root_proc = proc_mkdir( "isl12024", 0 );
-+ entry_proc = create_proc_entry("id", S_IFREG | S_IRUGO | S_IWUSR, root_proc);
++ }
++ else {
++ printk(KERN_ERR DRV_NAME ": Couldn't read status\n");
++ }
+
-+ if (entry_proc == NULL)
-+ return -1;
++ proc_root = proc_mkdir(DRV_NAME, 0);
++ proc_entry = create_proc_entry("id", S_IFREG | S_IRUGO, proc_root);
++ if (proc_entry == NULL)
++ return -1;
+
-+ entry_proc->owner = THIS_MODULE;
-+ entry_proc->read_proc = read_proc;
++ proc_entry->owner = THIS_MODULE;
++ proc_entry->read_proc = read_proc;
+
-+ /* read unique id from eeprom */
++ /* Read unique id from eeprom */
+ isl12024_i2c_read_regs(new_client, ISL12024_REG_ID, buf_id, sizeof(buf_id));
+
-+
+ return 0;
+
+ failout:
@@ -506,12 +645,14 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return rc;
+}
+
++
+static int
+isl12024_attach_adapter (struct i2c_adapter *adapter)
+{
+ return i2c_probe(adapter, &addr_data, isl12024_probe);
+}
+
++
+static int
+isl12024_detach_client(struct i2c_client *client)
+{
@@ -530,6 +671,7 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+ return 0;
+}
+
++
+/* module init/exit */
+
+static int __init isl12024_init(void)
@@ -549,121 +691,3 @@ Index: linux-2.6.27/drivers/rtc/rtc-isl12024.c
+
+module_init(isl12024_init);
+module_exit(isl12024_exit);
-Index: linux-2.6.27/drivers/i2c/chips/at24.c
-===================================================================
---- linux-2.6.27.orig/drivers/i2c/chips/at24.c
-+++ linux-2.6.27/drivers/i2c/chips/at24.c
-@@ -114,6 +114,8 @@ static const struct i2c_device_id at24_i
- { "spd", AT24_DEVICE_MAGIC(2048 / 8,
- AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
- { "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
-+ /* Intersil RTC/Unique-ID isl12024 eeprom handled here */
-+ { "isl12024",AT24_DEVICE_MAGIC(4096 / 8, AT24_FLAG_ADDR16) },
- /* 24rf08 quirk is handled at i2c-core */
- { "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
- { "24c16", AT24_DEVICE_MAGIC(16384 / 8, 0) },
-Index: linux-2.6.27/drivers/rtc/isl12024.h
-===================================================================
---- /dev/null
-+++ linux-2.6.27/drivers/rtc/isl12024.h
-@@ -0,0 +1,100 @@
-+/*
-+ * Intersil ISL12024 chip registers definitions
-+ *
-+ *
-+ * Copyright (C) 2008, CenoSYS (www.cenosys.com).
-+ * Guillaume Ligneul
-+ * Guillaume.ligneul@gmail.com
-+ *
-+ * This software program is licensed subject to the GNU General Public License
-+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
-+ */
-+
-+#ifndef ISL12024_H_
-+#define ISL12024_H_
-+
-+#define ISL12024_REG_SR 0x3F /* status register */
-+#define ISL12024_REG_Y2K 0x37
-+#define ISL12024_REG_DW 0x36
-+#define ISL12024_REG_YR 0x35
-+#define ISL12024_REG_MO 0x34
-+#define ISL12024_REG_DT 0x33
-+#define ISL12024_REG_HR 0x32
-+#define ISL12024_REG_MN 0x31
-+#define ISL12024_REG_SC 0x30
-+#define ISL12024_REG_DTR 0x13
-+#define ISL12024_REG_ATR 0x12
-+#define ISL12024_REG_INT 0x11
-+#define ISL12024_REG_0 0x10
-+#define ISL12024_REG_Y2K1 0x0F
-+#define ISL12024_REG_DWA1 0x0E
-+#define ISL12024_REG_YRA1 0x0D
-+#define ISL12024_REG_MOA1 0x0C
-+#define ISL12024_REG_DTA1 0x0B
-+#define ISL12024_REG_HRA1 0x0A
-+#define ISL12024_REG_MNA1 0x09
-+#define ISL12024_REG_SCA1 0x08
-+#define ISL12024_REG_Y2K0 0x07
-+#define ISL12024_REG_DWA0 0x06
-+#define ISL12024_REG_YRA0 0x05
-+#define ISL12024_REG_MOA0 0x04
-+#define ISL12024_REG_DTA0 0x03
-+#define ISL12024_REG_HRA0 0x02
-+#define ISL12024_REG_MNA0 0x01
-+#define ISL12024_REG_SCA0 0x00
-+
-+#define ISL12024_CCR_BASE 0x30 /* Base address of CCR */
-+#define ISL12024_ALM0_BASE 0x00 /* Base address of ALARM0 */
-+
-+#define ISL12024_SR_RTCF 0x01 /* Clock failure */
-+#define ISL12024_SR_WEL 0x02 /* Write Enable Latch */
-+#define ISL12024_SR_RWEL 0x04 /* Register Write Enable */
-+#define ISL12024_SR_AL0 0x20 /* Alarm 0 match */
-+
-+#define ISL12024_DTR_DTR0 0x01
-+#define ISL12024_DTR_DTR1 0x02
-+#define ISL12024_DTR_DTR2 0x04
-+
-+#define ISL12024_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
-+
-+#define ISL12024_INT_AL0E 0x20 /* Alarm 0 enable */
-+
-+/* I2C ADDRESS */
-+#define ISL12024_I2C_ADDR 0xDE
-+#define ISL12024_I2C_EEPROM_ADDR 0x57
-+
-+/* device id section */
-+#define ISL12024_REG_ID 0x20
-+
-+/* Register map */
-+/* rtc section */
-+#define ISL12024_REG_HR_MIL (1<<7) /* 24h/12h mode */
-+#define ISL12024_REG_HR_PM (1<<5) /* PM/AM bit in 12h mode */
-+//#define ISL12024_REG_DT 0x33 /* Date */
-+//#define ISL12024_REG_MO 0x34 /* Month */
-+//#define ISL12024_REG_YR 0x35 /* Year */
-+//#define ISL12024_REG_DW 0x36
-+//#define ISL12024_REG_Y2K 0x37
-+#define ISL12024_RTC_SECTION_LEN 8
-+
-+/* control/status section */
-+//#define ISL12024_REG_SR 0x3F
-+//#define ISL12024_REG_SR_BAT (1<<7) /* battery */
-+//#define ISL12024_REG_SR_AL1 (1<<6) /* alarm 0 */
-+//#define ISL12024_REG_SR_AL0 (1<<5) /* alarm 1 */
-+//#define ISL12024_REG_SR_OSCF (1<<4) /* oscillator fail */
-+//#define ISL12024_REG_SR_RWEL (1<<2) /* register write enable latch */
-+//#define ISL12024_REG_SR_WEL (1<<1) /* write enable latch */
-+//#define ISL12024_REG_SR_RTCF (1<<0) /* rtc fail */
-+//#define ISL12024_REG_INT 0x11
-+
-+#define CCR_SEC 0
-+#define CCR_MIN 1
-+#define CCR_HOUR 2
-+#define CCR_MDAY 3
-+#define CCR_MONTH 4
-+#define CCR_YEAR 5
-+#define CCR_WDAY 6
-+#define CCR_Y2K 7
-+
-+#endif /*ISL12024_H_*/
diff --git a/recipes/linux/linux-2.6.27/boc01/012-090219-capsense.patch b/recipes/linux/linux-2.6.27/boc01/012-090219-capsense.patch
index fed8218427..c70339defa 100644
--- a/recipes/linux/linux-2.6.27/boc01/012-090219-capsense.patch
+++ b/recipes/linux/linux-2.6.27/boc01/012-090219-capsense.patch
@@ -29,7 +29,7 @@ Index: linux-2.6.27/drivers/input/misc/capsense-btns.c
===================================================================
--- /dev/null
+++ linux-2.6.27/drivers/input/misc/capsense-btns.c
-@@ -0,0 +1,438 @@
+@@ -0,0 +1,456 @@
+/*
+ * CAPSENSE Interface driver
+ *
@@ -68,7 +68,21 @@ Index: linux-2.6.27/drivers/input/misc/capsense-btns.c
+
+#define BUTTONS_POLL_INTERVAL 30 /* msec */
+
++#define CAP_INPUT_PORT(port) (0x00+(port))
++#define CAP_STATUS_PORT(port) (0x02+(port))
+#define CAP_OUTPUT_PORT(port) (0x04+(port))
++#define CAP_CS_ENABLE(port) (0x06+(port))
++#define CAP_GPIO_ENABLE(port) (0x08+(port))
++#define CAP_INVERSION_MASK(port) (0x0A+(port))
++#define CAP_INT_MASK(port) (0x0C+(port))
++#define CAP_STATUS_HOLD_MSK(port) (0x0E+(port))
++#define CAP_DM_PULL_UP(port) (0x10+(4*(port)))
++#define CAP_DM_STRONG(port) (0x11+(4*(port)))
++#define CAP_DM_HIGHZ(port) (0x12+(4*(port)))
++#define CAP_OD_LOW(port) (0x13+(4*(port)))
++#define CAP_PWM_ENABLE(port) (0x18+(port))
++#define CAP_PWM_MODE_DC 0x1A
++#define CAP_PWM_DELAY 0x1B
+#define CAP_OP_SEL(port,bit) (0x1C+(25*(port))+(5*(bit)))
+#define CAP_READ_STATUS(port) (0x88+(port))
+
@@ -433,6 +447,8 @@ Index: linux-2.6.27/drivers/input/misc/capsense-btns.c
+{
+ struct capsense_ctx *capsense = i2c_get_clientdata(client);
+
++ printk(KERN_INFO DRIVER_NAME ": suspend\n");
++
+ capsense_led_suspend(capsense);
+
+ return 0;
@@ -442,6 +458,8 @@ Index: linux-2.6.27/drivers/input/misc/capsense-btns.c
+{
+ struct capsense_ctx *capsense = i2c_get_clientdata(client);
+
++ printk(KERN_INFO DRIVER_NAME ": resume\n");
++
+ capsense_led_resume(capsense);
+
+ return 0;
diff --git a/recipes/linux/linux-2.6.27/boc01/013-090209-lcd.patch b/recipes/linux/linux-2.6.27/boc01/013-090306-lcd.patch
index c867e2cf3a..cc53fe45f7 100644
--- a/recipes/linux/linux-2.6.27/boc01/013-090209-lcd.patch
+++ b/recipes/linux/linux-2.6.27/boc01/013-090306-lcd.patch
@@ -47,7 +47,7 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
===================================================================
--- /dev/null
+++ linux-2.6.27/drivers/video/nt7506fb.c
-@@ -0,0 +1,847 @@
+@@ -0,0 +1,880 @@
+/*
+ * linux/drivers/video/nt7506fb.c -- FB driver for NT7506 monochrome LCD board
+ *
@@ -154,6 +154,19 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+#define GRAY_BLACK_AB 6
+#define GRAY_BLACK_CD 7
+
++#define GRAY_INDEX_WHITE GRAY_WHITE_AB
++#define GRAY_INDEX_LIGHT GRAY_LIGHT_AB
++#define GRAY_INDEX_DARK GRAY_DARK_AB
++#define GRAY_INDEX_BLACK GRAY_BLACK_AB
++
++#define GRAY_LEVEL_WHITE 0
++#define GRAY_LEVEL_LIGHT 5
++#define GRAY_LEVEL_DARK 10
++#define GRAY_LEVEL_BLACK 15
++#define GRAY_LEVEL_MAX 15
++
++#define GRAY_VALUE(level) (((level)<<4)+(level))
++
+// Geometric settings
+#define LCD_WIDTH 128
+#define LCD_HEIGHT 128
@@ -469,7 +482,6 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+ NT7506_writeb_data(plane1);
+ NT7506_writeb_data(plane2);
+ }
-+ NT7506_writeb_data((unsigned char)0);
+ }
+
+ } else {
@@ -488,7 +500,6 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+ NT7506_writeb_data(plane1);
+ NT7506_writeb_data(plane2);
+ }
-+ NT7506_writeb_data((unsigned char)0);
+ }
+
+ }
@@ -526,7 +537,7 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+ unsigned int fbmemlength;
+ int err = 0;
+
-+ fbmemlength = (info->var.xres * info->var.yres)/8;
++ fbmemlength = (info->var.xres * info->var.yres) / (8 / info->var.bits_per_pixel);
+
+ if ( p > fbmemlength ) {
+ return -EFBIG;
@@ -633,6 +644,31 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+ nt7506fb_start_timer();
+}
+
++/*
++ * Grayscale levels adjustment
++ */
++
++#ifdef CONFIG_FB_NT7506_GRAYSCALE
++
++static void nt7506fb_set_gray_level(unsigned char index, unsigned char level)
++{
++ NT7506_writeb_ctl(NT_GRAY_SCALE | index);
++ NT7506_writeb_ctl(GRAY_VALUE(level));
++ NT7506_writeb_ctl(NT_GRAY_SCALE | (index+1));
++ NT7506_writeb_ctl(GRAY_VALUE(level));
++}
++
++#ifdef CONFIG_PROC_FS
++#include "nt7506fb-procfs.c"
++#endif
++
++#endif
++
++
++/*
++ * Device driver intialisation
++ */
++
+static int __init
+nt7506fb_probe(struct platform_device *dev)
+{
@@ -695,6 +731,13 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+ "fb%d: nt7506 frame buffer device, using %dK of video memory\n",
+ info->node, videomemorysize >> 10);
+
++ /* Create procfs entries for grayscale levels adjustment */
++#ifdef CONFIG_PROC_FS
++#ifdef CONFIG_FB_NT7506_GRAYSCALE
++ nt7506fb_proc_init(par);
++#endif
++#endif
++
+ /* Initialize backlight and contrast control (do not abort driver if it fails) */
+ nt7506fb_bl_init(par);
+ nt7506fb_lcd_init(par);
@@ -732,7 +775,7 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+{
+ struct fb_info *info = platform_get_drvdata(dev);
+
-+ printk(KERN_INFO DRIVER_NAME ": Switching to Power Save mode\n");
++ printk(KERN_INFO DRIVER_NAME ": suspend\n");
+
+ info->bl_dev->props.power = FB_BLANK_POWERDOWN;
+ nt7506fb_bl_update_status(info->bl_dev);
@@ -744,6 +787,8 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+{
+ struct fb_info *info = platform_get_drvdata(dev);
+
++ printk(KERN_INFO DRIVER_NAME ": resume\n");
++
+ info->bl_dev->props.power = FB_BLANK_UNBLANK;
+ nt7506fb_bl_update_status(info->bl_dev);
+
@@ -843,22 +888,10 @@ Index: linux-2.6.27/drivers/video/nt7506fb.c
+
+#ifdef CONFIG_FB_NT7506_GRAYSCALE
+ /* Feed grayscale palette */
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_WHITE_AB);
-+ NT7506_writeb_ctl(0x00);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_WHITE_CD);
-+ NT7506_writeb_ctl(0x00);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_LIGHT_AB);
-+ NT7506_writeb_ctl(0x55);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_LIGHT_CD);
-+ NT7506_writeb_ctl(0x55);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_DARK_AB);
-+ NT7506_writeb_ctl(0xAA);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_DARK_CD);
-+ NT7506_writeb_ctl(0xAA);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_BLACK_AB);
-+ NT7506_writeb_ctl(0xFF);
-+ NT7506_writeb_ctl(NT_GRAY_SCALE | GRAY_BLACK_CD);
-+ NT7506_writeb_ctl(0xFF);
++ nt7506fb_set_gray_level(GRAY_INDEX_WHITE, GRAY_LEVEL_WHITE);
++ nt7506fb_set_gray_level(GRAY_INDEX_LIGHT, GRAY_LEVEL_LIGHT);
++ nt7506fb_set_gray_level(GRAY_INDEX_DARK, GRAY_LEVEL_DARK);
++ nt7506fb_set_gray_level(GRAY_INDEX_BLACK, GRAY_LEVEL_BLACK);
+#endif
+
+ /* Select power circuit functions */
@@ -931,3 +964,127 @@ Index: linux-2.6.27/include/linux/nt7506fb.h
+#define FBIO_FRAMERATE _IOR('f', 1, char)
+
+#endif
+Index: linux-2.6.27/drivers/video/nt7506fb-procfs.c
+===================================================================
+--- /dev/null
++++ linux-2.6.27/drivers/video/nt7506fb-procfs.c
+@@ -0,0 +1,119 @@
++/*
++ * FB driver for NT7506 monochrome/grayscale LCD board
++ * Device setup using procfs
++ *
++ * Copyright (C) 2009, Goobie (www.goobie.fr).
++ *
++ * Sylvain Giroudon <sylvain.giroudon@goobie.fr>
++ *
++ * This software program is licensed subject to the GNU General Public License
++ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
++ */
++
++#include <linux/proc_fs.h>
++#include <linux/uaccess.h>
++
++struct nt7506fb_proc_entry {
++ char *name;
++ unsigned char index;
++ unsigned char level;
++ struct nt7506fb_par *par;
++};
++
++static struct nt7506fb_proc_entry nt7506fb_proc_entries[] = {
++ { "white", GRAY_INDEX_WHITE, GRAY_LEVEL_WHITE },
++ { "light", GRAY_INDEX_LIGHT, GRAY_LEVEL_LIGHT },
++ { "dark", GRAY_INDEX_DARK, GRAY_LEVEL_DARK },
++ { "black", GRAY_INDEX_BLACK, GRAY_LEVEL_BLACK },
++};
++
++static int nt7506fb_proc_read(char *page, char **start, off_t off, int count,
++ int *eof, void *data)
++{
++ struct nt7506fb_proc_entry *entry = data;
++ int len;
++
++ len = sprintf(page, "%d\n", entry->level);
++
++ len -= off;
++ if ( len < count ) {
++ *eof = 1;
++ if ( len <= 0 )
++ return 0;
++ } else {
++ len = count;
++ }
++
++ *start = page + off;
++
++ return len;
++}
++
++
++static int nt7506fb_proc_write(struct file *file, const char *buf,
++ unsigned long count, void *data)
++{
++ struct nt7506fb_proc_entry *entry = data;
++ char lbuf[count+1];
++
++ /* Only root can do this */
++ if ( !capable(CAP_SYS_ADMIN) )
++ return -EACCES;
++
++ memset(lbuf, 0, sizeof(lbuf));
++
++ if (copy_from_user(lbuf, buf, count))
++ return -EFAULT;
++
++ if ( sscanf(lbuf, "%hhi", &entry->level) == 1 ) {
++ if ( entry->level > GRAY_LEVEL_MAX )
++ entry->level = GRAY_LEVEL_MAX;
++
++ /* Set grayscale palette entry */
++ nt7506fb_set_gray_level(entry->index, entry->level);
++ }
++ else {
++ printk(KERN_INFO DRIVER_NAME ": [%s] Syntax error in expression\n", entry->name);
++ return -EINVAL;
++ }
++
++ return count;
++}
++
++
++static int nt7506fb_proc_init(struct nt7506fb_par *par)
++{
++ struct proc_dir_entry *root;
++ struct proc_dir_entry *ent;
++ int i;
++
++ /* Create nt7506fb proc directory */
++ printk(KERN_INFO DRIVER_NAME ": Creating setup entries in /proc/" DRIVER_NAME "/\n");
++
++ root = proc_mkdir(DRIVER_NAME, NULL);
++ if ( root == NULL ) {
++ printk(KERN_WARNING DRIVER_NAME ": Cannot create directory /proc/" DRIVER_NAME "\n");
++ return -1;
++ }
++
++ root->owner = THIS_MODULE;
++
++ /* Create gray level entries */
++ for (i = 0; i < ARRAY_SIZE(nt7506fb_proc_entries); i++) {
++ struct nt7506fb_proc_entry *entry = &nt7506fb_proc_entries[i];
++
++ entry->par = par;
++
++ ent = create_proc_entry(entry->name, S_IFREG|S_IWUSR, root);
++ if ( ent == NULL ) {
++ printk(KERN_WARNING DRIVER_NAME ": Cannot create entry /proc/" DRIVER_NAME "/%s\n", entry->name);
++ return -1;
++ }
++
++ ent->owner = THIS_MODULE;
++ ent->data = entry;
++ ent->write_proc = nt7506fb_proc_write;
++ ent->read_proc = nt7506fb_proc_read;
++ }
++ return 0;
++}
diff --git a/recipes/linux/linux-2.6.27/boc01/014-090209-pm-wakeup.patch b/recipes/linux/linux-2.6.27/boc01/014-090209-pm-wakeup.patch
deleted file mode 100644
index 3acbf40c32..0000000000
--- a/recipes/linux/linux-2.6.27/boc01/014-090209-pm-wakeup.patch
+++ /dev/null
@@ -1,195 +0,0 @@
-Index: linux-2.6.27/arch/powerpc/platforms/83xx/Kconfig
-===================================================================
---- linux-2.6.27.orig/arch/powerpc/platforms/83xx/Kconfig 2008-10-10 00:13:53.000000000 +0200
-+++ linux-2.6.27/arch/powerpc/platforms/83xx/Kconfig 2009-01-23 10:54:03.000000000 +0100
-@@ -104,6 +104,13 @@
-
- endif
-
-+
-+config WAKEUP_IT
-+ tristate "83xx interrupt for PM wakeup"
-+ help
-+ This enables a driver to be used as a wakeup source .
-+
-+
- # used for usb
- config PPC_MPC831x
- bool
-Index: linux-2.6.27/arch/powerpc/platforms/83xx/Makefile
-===================================================================
---- linux-2.6.27.orig/arch/powerpc/platforms/83xx/Makefile 2008-10-10 00:13:53.000000000 +0200
-+++ linux-2.6.27/arch/powerpc/platforms/83xx/Makefile 2009-01-23 10:54:03.000000000 +0100
-@@ -14,3 +14,4 @@
- obj-$(CONFIG_SBC834x) += sbc834x.o
- obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
- obj-$(CONFIG_ASP834x) += asp834x.o
-+obj-$(CONFIG_WAKEUP_IT) += wakeup-it.o
-Index: linux-2.6.27/arch/powerpc/platforms/83xx/wakeup-it.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.27/arch/powerpc/platforms/83xx/wakeup-it.c 2009-01-23 10:49:09.000000000 +0100
-@@ -0,0 +1,163 @@
-+/*
-+ * This support a driver to be used as a wakeup source on the MPC8313.
-+ *
-+ * Copyright (c) 2008 Cenosys
-+ *
-+ * Alexandre Coffignal <alexandre.coffignal@censoys.com>
-+ * Sylvain Giroudon <sylvain.giroudon@goobie.fr>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/interrupt.h>
-+#include <linux/of_platform.h>
-+#include <linux/reboot.h>
-+#include <linux/irq.h>
-+
-+#include <sysdev/fsl_soc.h>
-+
-+#define DRIVER_NAME "wakeup-it"
-+
-+char suspend = 0;
-+
-+static char *wakeup_irq_ids[] = {
-+ "capsense",
-+ "rfid",
-+};
-+
-+struct wakeup_priv {
-+ int nirq;
-+ int irq[ARRAY_SIZE(wakeup_irq_ids)];
-+ spinlock_t lock;
-+};
-+
-+struct wakeup_irq_desc {
-+ char *name;
-+ int index;
-+};
-+
-+static irqreturn_t wakeup(int irq, void *dev_id)
-+{
-+ //printk(KERN_INFO "===== WAKEUP INTERRUPT %d !!\n", irq);
-+
-+// if ( suspend )
-+// kernel_restart(NULL);
-+ return IRQ_HANDLED ;
-+}
-+
-+
-+static void wakeup_free(struct wakeup_priv *priv)
-+{
-+ int i;
-+
-+ for (i = 0; i < priv->nirq; i++) {
-+ free_irq(priv->irq[i], priv);
-+ }
-+
-+ kfree(priv);
-+}
-+
-+
-+static int __devinit wakeup_probe(struct of_device *dev, const struct of_device_id *match)
-+{
-+ struct device_node *np = dev->node;
-+ struct resource res;
-+ int ret = 0;
-+ struct wakeup_priv *priv;
-+ int i;
-+
-+ priv = kmalloc(sizeof(struct wakeup_priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->nirq = 0;
-+ spin_lock_init(&priv->lock);
-+ dev_set_drvdata(&dev->dev, priv);
-+
-+ ret = of_address_to_resource(np, 0, &res);
-+ if (ret)
-+ goto out;
-+
-+ for (i = 0; i < ARRAY_SIZE(wakeup_irq_ids); i++) {
-+ char *id = wakeup_irq_ids[i];
-+ char it_name[32];
-+ int it_num;
-+
-+ it_num = irq_of_parse_and_map(np, i);
-+ if ( it_num == NO_IRQ ) {
-+ dev_err(&dev->dev, DRIVER_NAME ": interrupt #%d (%s) does not exist in device tree.\n", i, id);
-+ ret = -ENODEV;
-+ goto out;
-+ }
-+
-+ set_irq_type(it_num, IRQ_TYPE_EDGE_FALLING);
-+
-+ snprintf(it_name, sizeof(it_name), DRIVER_NAME ":%s", id);
-+
-+ ret = request_irq(it_num, wakeup, 0, it_name, priv);
-+ if ( ret ) {
-+ printk(KERN_WARNING DRIVER_NAME ": cannot request interrupt %d (%s)\n", it_num, id);
-+ goto out;
-+ }
-+
-+ printk(KERN_INFO DRIVER_NAME ": accepting wakeup event from %s (%d)\n", id, it_num);
-+
-+ priv->irq[priv->nirq++] = it_num;
-+ }
-+
-+ return 0;
-+
-+out:
-+ wakeup_free(priv);
-+ return ret;
-+}
-+
-+static int __devexit wakeup_remove(struct of_device *dev)
-+{
-+ struct wakeup_priv *priv = dev_get_drvdata(&dev->dev);
-+ wakeup_free(priv);
-+ return 0;
-+}
-+
-+static struct of_device_id wakeup_match[] = {
-+ {
-+ .compatible = "fsl,wakeup-it",
-+ },
-+ {},
-+};
-+
-+static int wakeup_suspend(struct of_device * dev, pm_message_t state)
-+{
-+ int ret = 0;
-+ printk(KERN_INFO DRIVER_NAME ": suspend\n");
-+ suspend=1;
-+ return ret;
-+}
-+
-+
-+static struct of_platform_driver wakeup_driver = {
-+ .name = DRIVER_NAME,
-+ .match_table = wakeup_match,
-+ .probe = wakeup_probe,
-+ .suspend = wakeup_suspend,
-+ .remove = __devexit_p(wakeup_remove)
-+
-+};
-+
-+static int __init wakeup_init(void)
-+{
-+ return of_register_platform_driver(&wakeup_driver);
-+}
-+
-+static void __exit wakeup_exit(void)
-+{
-+ of_unregister_platform_driver(&wakeup_driver);
-+}
-+
-+module_init(wakeup_init);
-+module_exit(wakeup_exit);
diff --git a/recipes/linux/linux-2.6.27/boc01/defconfig b/recipes/linux/linux-2.6.27/boc01/defconfig
index bb667bcd10..24b147baf8 100644
--- a/recipes/linux/linux-2.6.27/boc01/defconfig
+++ b/recipes/linux/linux-2.6.27/boc01/defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.27
-# Thu Feb 26 12:59:36 2009
+# Wed Mar 4 18:33:27 2009
#
# CONFIG_PPC64 is not set
@@ -40,6 +40,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
@@ -181,7 +182,6 @@ CONFIG_MPC831x_RDB=y
# CONFIG_MPC837x_RDB is not set
# CONFIG_SBC834x is not set
# CONFIG_ASP834x is not set
-CONFIG_WAKEUP_IT=y
CONFIG_PPC_MPC831x=y
# CONFIG_PPC_86xx is not set
# CONFIG_EMBEDDED6xx is not set
@@ -263,6 +263,7 @@ CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_FSL_SOC=y
CONFIG_FSL_PCI=y
+CONFIG_FSL_LBC=y
CONFIG_PPC_PCI_CHOICE=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
@@ -732,6 +733,7 @@ CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ALAUDA is not set
CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_NAND_FSL_UPM=y
# CONFIG_MTD_ONENAND is not set
#
@@ -739,6 +741,7 @@ CONFIG_MTD_NAND_FSL_ELBC=y
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
CONFIG_OF_I2C=y
CONFIG_OF_SPI=y
# CONFIG_PARPORT is not set
@@ -1087,6 +1090,7 @@ CONFIG_I2C_HELPER_AUTO=y
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
+# CONFIG_I2C_GPIO is not set
CONFIG_I2C_MPC=y
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
@@ -1119,6 +1123,7 @@ CONFIG_AT24=y
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
@@ -1141,7 +1146,26 @@ CONFIG_SPI_MPC83xx=y
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_GPIOLIB is not set
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
@@ -1502,6 +1526,7 @@ CONFIG_LEDS_CLASS=y
# LED drivers
#
# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_PCA955X is not set
#
diff --git a/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig b/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig
index 45958e0e07..7941542b4e 100644
--- a/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig
+++ b/recipes/linux/linux-omap-2.6.28/beagleboard/defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-omap1
-# Wed Jan 14 19:12:03 2009
+# Tue Mar 24 16:56:43 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -41,7 +41,10 @@ CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
@@ -726,7 +729,9 @@ CONFIG_P54_USB=y
CONFIG_HOSTAP=y
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-# CONFIG_B43 is not set
+CONFIG_B43=y
+CONFIG_B43_LEDS=y
+# CONFIG_B43_DEBUG is not set
# CONFIG_B43LEGACY is not set
CONFIG_ZD1211RW=y
# CONFIG_ZD1211RW_DEBUG is not set
@@ -743,21 +748,21 @@ CONFIG_RT2X00_LIB_LEDS=y
#
# USB Network Adapters
#
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_CDCETHER=y
-CONFIG_USB_NET_DM9601=m
-# CONFIG_USB_NET_SMSC95XX is not set
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_GL620A=y
+CONFIG_USB_NET_NET1080=y
+CONFIG_USB_NET_PLUSB=y
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=y
-CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_CDC_SUBSET=y
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
@@ -832,6 +837,12 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_UINPUT=y
#
@@ -1061,7 +1072,9 @@ CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
-# CONFIG_SSB is not set
+CONFIG_SSB=y
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
#
# Multifunction device drivers
@@ -1664,14 +1677,13 @@ CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_DUMMY_HCD is not set
CONFIG_USB_GADGET_DUALSPEED=y
# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=y
-CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_USB_CDC_COMPOSITE=y
#
# OTG and related infrastructure
diff --git a/recipes/linux/linux-omap-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch b/recipes/linux/linux-omap-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch
new file mode 100644
index 0000000000..a76e96e444
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.29/0001-ASoC-Add-support-for-OMAP3-EVM.patch
@@ -0,0 +1,206 @@
+From c1dad0b6b434300ae64c902d11611c54c513ea10 Mon Sep 17 00:00:00 2001
+From: Anuj Aggarwal <anuj.aggarwal@ti.com>
+Date: Fri, 21 Nov 2008 17:41:03 +0530
+Subject: [PATCH] ASoC: Add support for OMAP3 EVM
+
+This patch adds ALSA SoC support for OMAP3 EVM using TWL4030 audio codec.
+
+Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
+---
+ sound/soc/omap/Kconfig | 8 +++
+ sound/soc/omap/Makefile | 3 +-
+ sound/soc/omap/omap3evm.c | 147 +++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 157 insertions(+), 1 deletions(-)
+ create mode 100644 sound/soc/omap/omap3evm.c
+
+diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
+index 0daeee4..deb6ba9 100644
+--- a/sound/soc/omap/Kconfig
++++ b/sound/soc/omap/Kconfig
+@@ -22,6 +22,14 @@ config SND_OMAP_SOC_OMAP3_BEAGLE
+ help
+ Say Y if you want to add support for SoC audio on the Beagleboard.
+
++config SND_OMAP_SOC_OMAP3EVM
++ tristate "SoC Audio support for OMAP3EVM board"
++ depends on SND_OMAP_SOC && MACH_OMAP3EVM
++ select SND_OMAP_SOC_MCBSP
++ select SND_SOC_TWL4030
++ help
++ Say Y if you want to add support for SoC audio on the omap3evm board.
++
+ config SND_OMAP_SOC_OSK5912
+ tristate "SoC Audio support for omap osk5912"
+ depends on SND_OMAP_SOC && MACH_OMAP_OSK
+diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
+index 4bae404..ef31c25 100644
+--- a/sound/soc/omap/Makefile
++++ b/sound/soc/omap/Makefile
+@@ -10,9 +10,10 @@ snd-soc-n810-objs := n810.o
+ snd-soc-omap3beagle-objs := omap3beagle.o
+ snd-soc-osk5912-objs := osk5912.o
+ snd-soc-overo-objs := overo.o
++snd-soc-omap3evm-objs := omap3evm.o
+
+ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
+ obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
+ obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
+ obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
+-
++obj-$(CONFIG_MACH_OMAP3EVM) += snd-soc-omap3evm.o
+diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
+new file mode 100644
+index 0000000..570af55
+--- /dev/null
++++ b/sound/soc/omap/omap3evm.c
+@@ -0,0 +1,147 @@
++/*
++ * omap3evm.c -- ALSA SoC support for OMAP3 EVM
++ *
++ * Author: Anuj Aggarwal <anuj.aggarwal@ti.com>
++ *
++ * Based on sound/soc/omap/beagle.c by Steve Sakoman
++ *
++ * Copyright (C) 2008 Texas Instruments, Incorporated
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
++ * whether express or implied; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <mach/hardware.h>
++#include <mach/gpio.h>
++#include <mach/mcbsp.h>
++
++#include "omap-mcbsp.h"
++#include "omap-pcm.h"
++#include "../codecs/twl4030.h"
++
++static int omap3evm_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
++ int ret;
++
++ /* Set codec DAI configuration */
++ ret = snd_soc_dai_set_fmt(codec_dai,
++ SND_SOC_DAIFMT_I2S |
++ SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM);
++ if (ret < 0) {
++ printk(KERN_ERR "can't set codec DAI configuration\n");
++ return ret;
++ }
++
++ /* Set cpu DAI configuration */
++ ret = snd_soc_dai_set_fmt(cpu_dai,
++ SND_SOC_DAIFMT_I2S |
++ SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM);
++ if (ret < 0) {
++ printk(KERN_ERR "can't set cpu DAI configuration\n");
++ return ret;
++ }
++
++ /* Set the codec system clock for DAC and ADC */
++ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
++ SND_SOC_CLOCK_IN);
++ if (ret < 0) {
++ printk(KERN_ERR "can't set codec system clock\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static struct snd_soc_ops omap3evm_ops = {
++ .hw_params = omap3evm_hw_params,
++};
++
++/* Digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link omap3evm_dai = {
++ .name = "TWL4030",
++ .stream_name = "TWL4030",
++ .cpu_dai = &omap_mcbsp_dai[0],
++ .codec_dai = &twl4030_dai,
++ .ops = &omap3evm_ops,
++};
++
++/* Audio machine driver */
++static struct snd_soc_machine snd_soc_machine_omap3evm = {
++ .name = "omap3evm",
++ .dai_link = &omap3evm_dai,
++ .num_links = 1,
++};
++
++/* Audio subsystem */
++static struct snd_soc_device omap3evm_snd_devdata = {
++ .machine = &snd_soc_machine_omap3evm,
++ .platform = &omap_soc_platform,
++ .codec_dev = &soc_codec_dev_twl4030,
++};
++
++static struct platform_device *omap3evm_snd_device;
++
++static int __init omap3evm_soc_init(void)
++{
++ int ret;
++
++ if (!machine_is_omap3evm()) {
++ pr_debug("Not OMAP3 EVM!\n");
++ return -ENODEV;
++ }
++ pr_info("OMAP3 EVM SoC init\n");
++
++ omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
++ if (!omap3evm_snd_device) {
++ printk(KERN_ERR "Platform device allocation failed\n");
++ return -ENOMEM;
++ }
++
++ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata);
++ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev;
++ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */
++
++ ret = platform_device_add(omap3evm_snd_device);
++ if (ret)
++ goto err1;
++
++ return 0;
++
++err1:
++ printk(KERN_ERR "Unable to add platform device\n");
++ platform_device_put(omap3evm_snd_device);
++
++ return ret;
++}
++
++static void __exit omap3evm_soc_exit(void)
++{
++ platform_device_unregister(omap3evm_snd_device);
++}
++
++module_init(omap3evm_soc_init);
++module_exit(omap3evm_soc_exit);
++
++MODULE_AUTHOR("Anuj Aggarwal <anuj.aggarwal@ti.com>");
++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
++MODULE_LICENSE("GPL");
+--
+1.5.6.5
+
diff --git a/recipes/linux/linux-omap-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch b/recipes/linux/linux-omap-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch
new file mode 100644
index 0000000000..d590f8ffb9
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.29/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch
@@ -0,0 +1,146 @@
+From f8f10f496bce396416d7156da876222c6ce8c341 Mon Sep 17 00:00:00 2001
+From: Steven Kipisz <skipisz@beagleboard.org>
+Date: Wed, 9 Jan 2009 12:01:11 -0600
+Subject: [PATCH-USB] Omap3 beagleboard: add support for EHCI in revision C1 boards
+
+Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c | 10 +---------
+ arch/arm/mach-omap2/usb-ehci.c | 4 +---
+ drivers/usb/host/ehci-omap.c | 26 ++++++++++++++++++++++++++
+ 3 files changed, 28 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index fe97bab..de81153 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -140,15 +140,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ * power switch and overcurrent detect
+ */
+
+- gpio_request(gpio + 1, "EHCI_nOC");
+- gpio_direction_input(gpio + 1);
+-
+- /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
+- gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
+- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
+-
+- /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+- gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
++ /* TODO: This needs to be modified to not rely on u-boot */
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
+index 489439d..2c6305b 100644
+--- a/arch/arm/mach-omap2/usb-ehci.c
++++ b/arch/arm/mach-omap2/usb-ehci.c
+@@ -152,9 +152,7 @@ static void setup_ehci_io_mux(void)
+ void __init usb_ehci_init(void)
+ {
+ #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+- /* Setup Pin IO MUX for EHCI */
+- if (cpu_is_omap34xx())
+- setup_ehci_io_mux();
++ /* TODO: Setup Pin IO MUX for EHCI - moved this temporarily to U-boot */
+
+ if (platform_device_register(&ehci_device) < 0) {
+ printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
+
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 1b3266c..8472996 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -48,16 +48,26 @@
+ * to get the PHY state machine in working state
+ */
+ #define EXTERNAL_PHY_RESET
++#ifdef CONFIG_MACH_OMAP3_BEAGLE
++#define EXT_PHY_RESET_GPIO_PORT2 (147)
++#else
+ #define EXT_PHY_RESET_GPIO_PORT1 (57)
+ #define EXT_PHY_RESET_GPIO_PORT2 (61)
++#endif
+ #define EXT_PHY_RESET_DELAY (10)
+
++#define PHY_STP_PULLUP_ENABLE (0x10)
++#define PHY_STP_PULLUP_DISABLE (0x90)
++
++
+ /* ISSUE2:
+ * USBHOST supports External charge pump PHYs only
+ * Use the VBUS from Port1 to power VBUS of Port2 externally
+ * So use Port2 as the working ULPI port
+ */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ #define VBUS_INTERNAL_CHARGEPUMP_HACK
++#endif
+
+ #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+
+@@ -225,14 +235,43 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+
+ #ifdef EXTERNAL_PHY_RESET
+ /* Refer: ISSUE1 */
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ gpio_request(EXT_PHY_RESET_GPIO_PORT1, "USB1 PHY reset");
+ gpio_direction_output(EXT_PHY_RESET_GPIO_PORT1, 0);
++#endif
+ gpio_request(EXT_PHY_RESET_GPIO_PORT2, "USB2 PHY reset");
+ gpio_direction_output(EXT_PHY_RESET_GPIO_PORT2, 0);
++ gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 0);
+ /* Hold the PHY in RESET for enough time till DIR is high */
+ udelay(EXT_PHY_RESET_DELAY);
+ #endif
+
++ /*
++ * The PHY register 0x7 - Interface Control register is
++ * configured to disable the integrated STP pull-up resistor
++ * used for interface protection.
++ *
++ * May not need to be here.
++ */
++ omap_writel((0x7 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* interface reg */
++ (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/* Write */
++ (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++ (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++ (PHY_STP_PULLUP_DISABLE),
++ EHCI_INSNREG05_ULPI);
++
++ while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
++ /* Force PHY to HS */
++ omap_writel((0x4 << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* function ctrl */
++ (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/* Write */
++ (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
++ (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
++ (0x40),
++ EHCI_INSNREG05_ULPI);
++
++ while (!(omap_readl(EHCI_INSNREG05_ULPI) & (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
++
+ /* Configure TLL for 60Mhz clk for ULPI */
+ ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
+ if (IS_ERR(ehci_clocks->usbtll_fck_clk))
+@@ -307,7 +346,9 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+ * Hold the PHY in RESET for enough time till PHY is settled and ready
+ */
+ udelay(EXT_PHY_RESET_DELAY);
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ gpio_set_value(EXT_PHY_RESET_GPIO_PORT1, 1);
++#endif
+ gpio_set_value(EXT_PHY_RESET_GPIO_PORT2, 1);
+ #endif
+
+@@ -393,7 +434,9 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
+
+
+ #ifdef EXTERNAL_PHY_RESET
++#ifndef CONFIG_MACH_OMAP3_BEAGLE
+ gpio_free(EXT_PHY_RESET_GPIO_PORT1);
++#endif
+ gpio_free(EXT_PHY_RESET_GPIO_PORT2);
+ #endif
+
+--
+1.6.0.4.790.gaa14a
diff --git a/recipes/linux/linux-omap-2.6.29/DSS2.diff b/recipes/linux/linux-omap-2.6.29/DSS2.diff
new file mode 100644
index 0000000000..17617548ca
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.29/DSS2.diff
@@ -0,0 +1,23964 @@
+ arch/arm/plat-omap/include/mach/omapfb.h | 398 -
+ b/Documentation/arm/OMAP/DSS | 311 +
+ b/arch/arm/configs/dss_omap3_beagle_defconfig | 1369 ++++
+ b/arch/arm/configs/dss_overo_defconfig | 1826 +++++
+ b/arch/arm/mach-omap1/board-nokia770.c | 2
+ b/arch/arm/mach-omap2/board-3430sdp.c | 218
+ b/arch/arm/mach-omap2/board-n800.c | 217
+ b/arch/arm/mach-omap2/board-omap3beagle.c | 91
+ b/arch/arm/mach-omap2/board-omap3evm.c | 203
+ b/arch/arm/mach-omap2/board-overo.c | 98
+ b/arch/arm/mach-omap2/io.c | 2
+ b/arch/arm/plat-omap/Makefile | 2
+ b/arch/arm/plat-omap/fb.c | 30
+ b/arch/arm/plat-omap/include/mach/display.h | 520 +
+ b/arch/arm/plat-omap/include/mach/vram.h | 33
+ b/arch/arm/plat-omap/include/mach/vrfb.h | 47
+ b/arch/arm/plat-omap/vram.c | 615 +
+ b/arch/arm/plat-omap/vrfb.c | 159
+ b/drivers/video/Kconfig | 1
+ b/drivers/video/Makefile | 1
+ b/drivers/video/omap/Kconfig | 5
+ b/drivers/video/omap/blizzard.c | 2
+ b/drivers/video/omap/dispc.c | 2
+ b/drivers/video/omap/hwa742.c | 2
+ b/drivers/video/omap/lcd_2430sdp.c | 2
+ b/drivers/video/omap/lcd_ams_delta.c | 2
+ b/drivers/video/omap/lcd_apollon.c | 2
+ b/drivers/video/omap/lcd_h3.c | 2
+ b/drivers/video/omap/lcd_h4.c | 3
+ b/drivers/video/omap/lcd_inn1510.c | 2
+ b/drivers/video/omap/lcd_inn1610.c | 2
+ b/drivers/video/omap/lcd_ldp.c | 2
+ b/drivers/video/omap/lcd_mipid.c | 2
+ b/drivers/video/omap/lcd_omap2evm.c | 2
+ b/drivers/video/omap/lcd_omap3beagle.c | 2
+ b/drivers/video/omap/lcd_omap3evm.c | 2
+ b/drivers/video/omap/lcd_osk.c | 2
+ b/drivers/video/omap/lcd_overo.c | 2
+ b/drivers/video/omap/lcd_p2.c | 2
+ b/drivers/video/omap/lcd_palmte.c | 2
+ b/drivers/video/omap/lcd_palmtt.c | 2
+ b/drivers/video/omap/lcd_palmz71.c | 3
+ b/drivers/video/omap/lcdc.c | 2
+ b/drivers/video/omap/omapfb_main.c | 2
+ b/drivers/video/omap/rfbi.c | 3
+ b/drivers/video/omap/sossi.c | 2
+ b/drivers/video/omap2/Kconfig | 3
+ b/drivers/video/omap2/Makefile | 4
+ b/drivers/video/omap2/displays/Kconfig | 32
+ b/drivers/video/omap2/displays/Makefile | 6
+ b/drivers/video/omap2/displays/ctrl-blizzard.c | 279
+ b/drivers/video/omap2/displays/panel-generic.c | 96
+ b/drivers/video/omap2/displays/panel-n800.c | 435 +
+ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c | 108
+ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c | 112
+ b/drivers/video/omap2/dss/Kconfig | 89
+ b/drivers/video/omap2/dss/Makefile | 6
+ b/drivers/video/omap2/dss/core.c | 641 ++
+ b/drivers/video/omap2/dss/dispc.c | 2781 +++++++++
+ b/drivers/video/omap2/dss/display.c | 687 ++
+ b/drivers/video/omap2/dss/dpi.c | 379 +
+ b/drivers/video/omap2/dss/dsi.c | 3693 ++++++++++++
+ b/drivers/video/omap2/dss/dss.c | 345 +
+ b/drivers/video/omap2/dss/dss.h | 326 +
+ b/drivers/video/omap2/dss/manager.c | 463 +
+ b/drivers/video/omap2/dss/overlay.c | 587 +
+ b/drivers/video/omap2/dss/rfbi.c | 1304 ++++
+ b/drivers/video/omap2/dss/sdi.c | 245
+ b/drivers/video/omap2/dss/venc.c | 600 +
+ b/drivers/video/omap2/omapfb/Kconfig | 35
+ b/drivers/video/omap2/omapfb/Makefile | 2
+ b/drivers/video/omap2/omapfb/omapfb-ioctl.c | 656 ++
+ b/drivers/video/omap2/omapfb/omapfb-main.c | 1944 ++++++
+ b/drivers/video/omap2/omapfb/omapfb-sysfs.c | 371 +
+ b/drivers/video/omap2/omapfb/omapfb.h | 143
+ b/include/linux/omapfb.h | 418 +
+ 76 files changed, 22501 insertions(+), 490 deletions(-)
+diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
+new file mode 100644
+index 0000000..9e902a2
+--- /dev/null
++++ b/Documentation/arm/OMAP/DSS
+@@ -0,0 +1,311 @@
++OMAP2/3 Display Subsystem
++-------------------------
++
++This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
++(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
++TV-out and multiple display support, but there are lots of small improvements
++also.
++
++The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
++panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
++currently side by side, you can choose which one to use.
++
++Features
++--------
++
++Working and tested features include:
++
++- MIPI DPI (parallel) output
++- MIPI DSI output in command mode
++- MIPI DBI (RFBI) output
++- SDI output
++- TV output
++- All pieces can be compiled as a module or inside kernel
++- Use DISPC to update any of the outputs
++- Use CPU to update RFBI or DSI output
++- OMAP DISPC planes
++- RGB16, RGB24 packed, RGB24 unpacked
++- YUV2, UYVY
++- Scaling
++- Adjusting DSS FCK to find a good pixel clock
++- Use DSI DPLL to create DSS FCK
++
++Tested boards include:
++- OMAP3 SDP board
++- Beagle board
++- N810
++
++omapdss driver
++--------------
++
++The DSS driver does not itself have any support for Linux framebuffer, V4L or
++such like the current ones, but it has an internal kernel API that upper level
++drivers can use.
++
++The DSS driver models OMAP's overlays, overlay managers and displays in a
++flexible way to enable non-common multi-display configuration. In addition to
++modelling the hardware overlays, omapdss supports virtual overlays and overlay
++managers. These can be used when updating a display with CPU or system DMA.
++
++Panel and controller drivers
++----------------------------
++
++The drivers implement panel or controller specific functionality and are not
++usually visible to users except through omapfb driver. They register
++themselves to the DSS driver.
++
++omapfb driver
++-------------
++
++The omapfb driver implements arbitrary number of standard linux framebuffers.
++These framebuffers can be routed flexibly to any overlays, thus allowing very
++dynamic display architecture.
++
++The driver exports some omapfb specific ioctls, which are compatible with the
++ioctls in the old driver.
++
++The rest of the non standard features are exported via sysfs. Whether the final
++implementation will use sysfs, or ioctls, is still open.
++
++V4L2 drivers
++------------
++
++V4L2 is being implemented in TI.
++
++From omapdss point of view the V4L2 drivers should be similar to framebuffer
++driver.
++
++Architecture
++--------------------
++
++Some clarification what the different components do:
++
++ - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
++ pixel data for the image. Framebuffer has width and height and color
++ depth.
++ - Overlay defines where the pixels are read from and where they go on the
++ screen. The overlay may be smaller than framebuffer, thus displaying only
++ part of the framebuffer. The position of the overlay may be changed if
++ the overlay is smaller than the display.
++ - Overlay manager combines the overlays in to one image and feeds them to
++ display.
++ - Display is the actual physical display device.
++
++A framebuffer can be connected to multiple overlays to show the same pixel data
++on all of the overlays. Note that in this case the overlay input sizes must be
++the same, but, in case of video overlays, the output size can be different. Any
++framebuffer can be connected to any overlay.
++
++An overlay can be connected to one overlay manager. Also DISPC overlays can be
++connected only to DISPC overlay managers, and virtual overlays can be only
++connected to virtual overlays.
++
++An overlay manager can be connected to one display. There are certain
++restrictions which kinds of displays an overlay manager can be connected:
++
++ - DISPC TV overlay manager can be only connected to TV display.
++ - Virtual overlay managers can only be connected to DBI or DSI displays.
++ - DISPC LCD overlay manager can be connected to all displays, except TV
++ display.
++
++Sysfs
++-----
++The sysfs interface is mainly used for testing. I don't think sysfs
++interface is the best for this in the final version, but I don't quite know
++what would be the best interfaces for these things.
++
++The sysfs interface is divided to two parts: DSS and FB.
++
++/sys/class/graphics/fb? directory:
++mirror 0=off, 1=on
++rotate Rotation 0-3 for 0, 90, 180, 270 degrees
++rotate_type 0 = DMA rotation, 1 = VRFB rotation
++overlays List of overlay numbers to which framebuffer pixels go
++phys_addr Physical address of the framebuffer
++virt_addr Virtual address of the framebuffer
++size Size of the framebuffer
++
++/sys/devices/platform/omapdss/overlay? directory:
++enabled 0=off, 1=on
++input_size width,height (ie. the framebuffer size)
++manager Destination overlay manager name
++name
++output_size width,height
++position x,y
++screen_width width
++
++/sys/devices/platform/omapdss/manager? directory:
++display Destination display
++name
++
++/sys/devices/platform/omapdss/display? directory:
++ctrl_name Controller name
++mirror 0=off, 1=on
++update_mode 0=off, 1=auto, 2=manual
++enabled 0=off, 1=on
++name
++rotate Rotation 0-3 for 0, 90, 180, 270 degrees
++timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
++ When writing, two special timings are accepted for tv-out:
++ "pal" and "ntsc"
++panel_name
++tear_elim Tearing elimination 0=off, 1=on
++
++There are also some debugfs files at <debugfs>/omapdss/ which show information
++about clocks and registers.
++
++Examples
++--------
++
++The following definitions have been made for the examples below:
++
++ovl0=/sys/devices/platform/omapdss/overlay0
++ovl1=/sys/devices/platform/omapdss/overlay1
++ovl2=/sys/devices/platform/omapdss/overlay2
++
++mgr0=/sys/devices/platform/omapdss/manager0
++mgr1=/sys/devices/platform/omapdss/manager1
++
++lcd=/sys/devices/platform/omapdss/display0
++dvi=/sys/devices/platform/omapdss/display1
++tv=/sys/devices/platform/omapdss/display2
++
++fb0=/sys/class/graphics/fb0
++fb1=/sys/class/graphics/fb1
++fb2=/sys/class/graphics/fb2
++
++Default setup on OMAP3 SDP
++--------------------------
++
++Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
++and TV-out are not in use. The columns from left to right are:
++framebuffers, overlays, overlay managers, displays. Framebuffers are
++handled by omapfb, and the rest by the DSS.
++
++FB0 --- GFX -\ DVI
++FB1 --- VID1 --+- LCD ---- LCD
++FB2 --- VID2 -/ TV ----- TV
++
++Example: Switch from LCD to DVI
++----------------------
++
++w=`cat $dvi/horizontal | cut -d "," -f 1`
++h=`cat $dvi/vertical | cut -d "," -f 1`
++
++echo "0" > $lcd/enabled
++echo "" > $mgr0/display
++fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
++# at this point you have to switch the dvi/lcd dip-switch from the omap board
++echo "dvi" > $mgr0/display
++echo "1" > $dvi/enabled
++
++After this the configuration looks like:
++
++FB0 --- GFX -\ -- DVI
++FB1 --- VID1 --+- LCD -/ LCD
++FB2 --- VID2 -/ TV ----- TV
++
++Example: Clone GFX overlay to LCD and TV
++-------------------------------
++
++w=`cat $tv/horizontal | cut -d "," -f 1`
++h=`cat $tv/vertical | cut -d "," -f 1`
++
++echo "0" > $ovl0/enabled
++echo "0" > $ovl1/enabled
++
++echo "" > $fb1/overlays
++echo "0,1" > $fb0/overlays
++
++echo "$w,$h" > $ovl1/output_size
++echo "tv" > $ovl1/manager
++
++echo "1" > $ovl0/enabled
++echo "1" > $ovl1/enabled
++
++echo "1" > $tv/enabled
++
++After this the configuration looks like (only relevant parts shown):
++
++FB0 +-- GFX ---- LCD ---- LCD
++ \- VID1 ---- TV ---- TV
++
++Misc notes
++----------
++
++OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
++
++Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
++of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
++
++Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
++does not support mirroring.
++
++VRFB rotation requires much more memory than non-rotated framebuffer, so you
++probably need to increase your vram setting before using VRFB rotation. Also,
++many applications may not work with VRFB if they do not pay attention to all
++framebuffer parameters.
++
++Kernel boot arguments
++---------------------
++
++vram=<size>
++ - Amount of total VRAM to preallocate. For example, "10M". omapfb
++ allocates memory for framebuffers from VRAM.
++
++omapfb.mode=<display>:<mode>[,...]
++ - Default video mode for specified displays. For example,
++ "dvi:800x400MR-24@60". See drivers/video/modedb.c.
++ There are also two special modes: "pal" and "ntsc" that
++ can be used to tv out.
++
++omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
++ - VRAM allocated for a framebuffer. Normally omapfb allocates vram
++ depending on the display size. With this you can manually allocate
++ more or define the physical address of each framebuffer. For example,
++ "1:4M" to allocate 4M for fb1.
++
++omapfb.debug=<y|n>
++ - Enable debug printing. You have to have OMAPFB debug support enabled
++ in kernel config.
++
++omapfb.test=<y|n>
++ - Draw test pattern to framebuffer whenever framebuffer settings change.
++ You need to have OMAPFB debug support enabled in kernel config.
++
++omapfb.vrfb=<y|n>
++ - Use VRFB rotation for all framebuffers.
++
++omapfb.rotate=<angle>
++ - Default rotation applied to all framebuffers.
++ 0 - 0 degree rotation
++ 1 - 90 degree rotation
++ 2 - 180 degree rotation
++ 3 - 270 degree rotation
++
++omapfb.mirror=<y|n>
++ - Default mirror for all framebuffers. Only works with DMA rotation.
++
++omapdss.def_disp=<display>
++ - Name of default display, to which all overlays will be connected.
++ Common examples are "lcd" or "tv".
++
++omapdss.debug=<y|n>
++ - Enable debug printing. You have to have DSS debug support enabled in
++ kernel config.
++
++TODO
++----
++
++DSS locking
++
++Error checking
++- Lots of checks are missing or implemented just as BUG()
++
++System DMA update for DSI
++- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
++ to skip the empty byte?)
++
++OMAP1 support
++- Not sure if needed
++
+diff --git a/arch/arm/configs/dss_omap3_beagle_defconfig b/arch/arm/configs/dss_omap3_beagle_defconfig
+new file mode 100644
+index 0000000..8a428db
+--- /dev/null
++++ b/arch/arm/configs/dss_omap3_beagle_defconfig
+@@ -0,0 +1,1369 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.29-rc3-omap1
++# Mon Feb 2 12:09:46 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_CLASSIC_RCU=y
++# CONFIG_TREE_RCU is not set
++# CONFIG_PREEMPT_RCU is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_PREEMPT_RCU_TRACE is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++# CONFIG_CGROUPS is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_COMPAT_BRK=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++# CONFIG_FREEZER is not set
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_W90X900 is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++# CONFIG_OMAP_SMARTREFLEX is not set
++# CONFIG_OMAP_RESET_CLOCKS is not set
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++# CONFIG_OMAP_MUX is not set
++# CONFIG_OMAP_MCBSP is not set
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_TICK_GPTIMER=12
++CONFIG_OMAP_DM_TIMER=y
++# CONFIG_OMAP_LL_DEBUG_UART1 is not set
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++CONFIG_OMAP_LL_DEBUG_UART3=y
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_NOKIA_RX51 is not set
++# CONFIG_MACH_OMAP_LDP is not set
++# CONFIG_MACH_OMAP_3430SDP is not set
++# CONFIG_MACH_OMAP3EVM is not set
++CONFIG_MACH_OMAP3_BEAGLE=y
++# CONFIG_MACH_OVERO is not set
++# CONFIG_MACH_OMAP3_PANDORA is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_FREQ is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++# CONFIG_NEON is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++CONFIG_PM_DEBUG=y
++# CONFIG_PM_VERBOSE is not set
++# CONFIG_SUSPEND is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_COMPAT_NET_DEV_OPS=y
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++CONFIG_WIRELESS_OLD_REGULATORY=y
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_LIB80211 is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_QINFO_PROBE is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MISC_DEVICES is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_NET_ETHERNET is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C2_OMAP_BEAGLE is not set
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TWL4030_MADC is not set
++# CONFIG_TWL4030_PWRBUTTON is not set
++# CONFIG_TWL4030_POWEROFF is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_LP5521 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++# CONFIG_SPI is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++# CONFIG_GPIO_SYSFS is not set
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_TPS65010 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_PCF50633 is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_VIDEO_MEDIA is not set
++
++#
++# Multimedia drivers
++#
++CONFIG_DAB=y
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_VRAM_SIZE=4
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++CONFIG_FB_OMAP2=m
++CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++# CONFIG_HID_SUPPORT is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++# CONFIG_USB is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++CONFIG_USB_MUSB_PERIPHERAL=y
++# CONFIG_USB_MUSB_OTG is not set
++CONFIG_USB_GADGET_MUSB_HDRC=y
++# CONFIG_MUSB_PIO_ONLY is not set
++CONFIG_USB_INVENTRA_DMA=y
++# CONFIG_USB_TI_CPPI_DMA is not set
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_IMX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_CI13XXX is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=y
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=y
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_NEW_LEDS is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++# CONFIG_REGULATOR is not set
++# CONFIG_UIO is not set
++# CONFIG_STAGING is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++CONFIG_QUOTA_TREE=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_TRACE_BRANCH_PROFILING is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_LRW is not set
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_FIND_LAST_BIT=y
++CONFIG_CRC_CCITT=y
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/dss_overo_defconfig b/arch/arm/configs/dss_overo_defconfig
+new file mode 100644
+index 0000000..bf7dbe1
+--- /dev/null
++++ b/arch/arm/configs/dss_overo_defconfig
+@@ -0,0 +1,1826 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.29-rc3-omap1
++# Sat Feb 14 12:23:43 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_MMU=y
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
++CONFIG_OPROFILE_ARMV7=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_CLASSIC_RCU=y
++# CONFIG_TREE_RCU is not set
++# CONFIG_PREEMPT_RCU is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_PREEMPT_RCU_TRACE is not set
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++CONFIG_USER_SCHED=y
++# CONFIG_CGROUP_SCHED is not set
++# CONFIG_CGROUPS is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++# CONFIG_SYSCTL_SYSCALL is not set
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++# CONFIG_ELF_CORE is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++CONFIG_PROFILING=y
++CONFIG_TRACEPOINTS=y
++# CONFIG_MARKERS is not set
++CONFIG_OPROFILE=y
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++CONFIG_BLOCK=y
++CONFIG_LBD=y
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++CONFIG_ARCH_OMAP=y
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_W90X900 is not set
++
++#
++# TI OMAP Implementations
++#
++CONFIG_ARCH_OMAP_OTG=y
++# CONFIG_ARCH_OMAP1 is not set
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_OMAP3=y
++
++#
++# OMAP Feature Selections
++#
++# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
++# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
++CONFIG_OMAP_SMARTREFLEX=y
++# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
++# CONFIG_OMAP_RESET_CLOCKS is not set
++CONFIG_OMAP_BOOT_TAG=y
++CONFIG_OMAP_BOOT_REASON=y
++# CONFIG_OMAP_COMPONENT_VERSION is not set
++# CONFIG_OMAP_GPIO_SWITCH is not set
++# CONFIG_OMAP_MUX is not set
++CONFIG_OMAP_MCBSP=y
++# CONFIG_OMAP_MBOX_FWK is not set
++# CONFIG_OMAP_MPU_TIMER is not set
++CONFIG_OMAP_32K_TIMER=y
++CONFIG_OMAP_32K_TIMER_HZ=128
++CONFIG_OMAP_TICK_GPTIMER=1
++CONFIG_OMAP_DM_TIMER=y
++# CONFIG_OMAP_LL_DEBUG_UART1 is not set
++# CONFIG_OMAP_LL_DEBUG_UART2 is not set
++CONFIG_OMAP_LL_DEBUG_UART3=y
++CONFIG_ARCH_OMAP34XX=y
++CONFIG_ARCH_OMAP3430=y
++
++#
++# OMAP Board Type
++#
++# CONFIG_MACH_NOKIA_RX51 is not set
++# CONFIG_MACH_OMAP_LDP is not set
++# CONFIG_MACH_OMAP_3430SDP is not set
++# CONFIG_MACH_OMAP3EVM is not set
++# CONFIG_MACH_OMAP3_BEAGLE is not set
++CONFIG_MACH_OVERO=y
++# CONFIG_MACH_OMAP3_PANDORA is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_IFAR=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++CONFIG_ARM_THUMBEE=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=128
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_ARCH_FLATMEM_HAS_HOLES=y
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
++CONFIG_LEDS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE=" debug "
++# CONFIG_XIP_KERNEL is not set
++CONFIG_KEXEC=y
++CONFIG_ATAGS_PROC=y
++
++#
++# CPU Power Management
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_TABLE=y
++# CONFIG_CPU_FREQ_DEBUG is not set
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_HAVE_AOUT=y
++CONFIG_BINFMT_AOUT=m
++CONFIG_BINFMT_MISC=y
++
++#
++# Power management options
++#
++CONFIG_PM=y
++CONFIG_PM_DEBUG=y
++# CONFIG_PM_VERBOSE is not set
++CONFIG_CAN_PM_TRACE=y
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++# CONFIG_PM_TEST_SUSPEND is not set
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_APM_EMULATION is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_COMPAT_NET_DEV_OPS=y
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=y
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=m
++# CONFIG_IPV6_PRIVACY is not set
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++CONFIG_IPV6_SIT=m
++CONFIG_IPV6_NDISC_NODETYPE=y
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++CONFIG_BT=y
++CONFIG_BT_L2CAP=y
++CONFIG_BT_SCO=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIBTSDIO is not set
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_H4=y
++CONFIG_BT_HCIUART_BCSP=y
++# CONFIG_BT_HCIUART_LL is not set
++# CONFIG_BT_HCIBRF6150 is not set
++# CONFIG_BT_HCIH4P is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
++CONFIG_CFG80211=y
++# CONFIG_CFG80211_REG_DEBUG is not set
++CONFIG_NL80211=y
++CONFIG_WIRELESS_OLD_REGULATORY=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_WIRELESS_EXT_SYSFS=y
++CONFIG_LIB80211=y
++CONFIG_LIB80211_CRYPT_WEP=m
++CONFIG_LIB80211_CRYPT_CCMP=m
++CONFIG_LIB80211_CRYPT_TKIP=m
++CONFIG_MAC80211=y
++
++#
++# Rate control algorithm selection
++#
++CONFIG_MAC80211_RC_PID=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT_PID=y
++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
++CONFIG_MAC80211_RC_DEFAULT="pid"
++# CONFIG_MAC80211_MESH is not set
++CONFIG_MAC80211_LEDS=y
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++CONFIG_MTD_CONCAT=y
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# CONFIG_MTD_QINFO_PROBE is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++# CONFIG_BLK_DEV_XIP is not set
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_CDROM_PKTCDVD_BUFFERS=8
++# CONFIG_CDROM_PKTCDVD_WCACHE is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_ICS932S401 is not set
++# CONFIG_OMAP_STI is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++CONFIG_EEPROM_93CX6=m
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_RAID_ATTRS=m
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=m
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++CONFIG_SCSI_MULTI_LUN=y
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_MD=m
++CONFIG_MD_LINEAR=m
++CONFIG_MD_RAID0=m
++CONFIG_MD_RAID1=m
++CONFIG_MD_RAID10=m
++CONFIG_MD_RAID456=m
++CONFIG_MD_RAID5_RESHAPE=y
++CONFIG_MD_MULTIPATH=m
++CONFIG_MD_FAULTY=m
++CONFIG_BLK_DEV_DM=m
++# CONFIG_DM_DEBUG is not set
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_ZERO=m
++CONFIG_DM_MULTIPATH=m
++CONFIG_DM_DELAY=m
++# CONFIG_DM_UEVENT is not set
++CONFIG_NETDEVICES=y
++CONFIG_DUMMY=m
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++CONFIG_TUN=m
++# CONFIG_VETH is not set
++# CONFIG_NET_ETHERNET is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++CONFIG_WLAN_80211=y
++CONFIG_LIBERTAS=y
++CONFIG_LIBERTAS_SDIO=y
++CONFIG_LIBERTAS_DEBUG=y
++# CONFIG_LIBERTAS_THINFIRM is not set
++# CONFIG_MAC80211_HWSIM is not set
++CONFIG_P54_COMMON=m
++# CONFIG_IWLWIFI_LEDS is not set
++CONFIG_HOSTAP=m
++CONFIG_HOSTAP_FIRMWARE=y
++CONFIG_HOSTAP_FIRMWARE_NVRAM=y
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_RT2X00 is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++CONFIG_PPP=m
++# CONFIG_PPP_MULTILINK is not set
++# CONFIG_PPP_FILTER is not set
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_MPPE=m
++CONFIG_PPPOE=m
++# CONFIG_PPPOL2TP is not set
++# CONFIG_SLIP is not set
++CONFIG_SLHC=m
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_TWL4030 is not set
++# CONFIG_KEYBOARD_LM8323 is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_OMAP=y
++# CONFIG_I2C_SIMTEC is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_PCF8575 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++CONFIG_TWL4030_MADC=m
++CONFIG_TWL4030_PWRBUTTON=y
++CONFIG_TWL4030_POWEROFF=y
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_TSL2563 is not set
++# CONFIG_LP5521 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_GPIO is not set
++CONFIG_SPI_OMAP24XX=y
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_TSC210X is not set
++# CONFIG_SPI_TSC2301 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++CONFIG_DEBUG_GPIO=y
++CONFIG_GPIO_SYSFS=y
++
++#
++# Memory mapped GPIO expanders:
++#
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++CONFIG_GPIO_TWL4030=y
++
++#
++# PCI GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=m
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_BATTERY_DS2760 is not set
++# CONFIG_TWL4030_BCI_BATTERY is not set
++# CONFIG_BATTERY_BQ27x00 is not set
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_AD7414 is not set
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADCXX is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7462 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ADT7473 is not set
++# CONFIG_SENSORS_ADT7475 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_LTC4245 is not set
++# CONFIG_SENSORS_MAX1111 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_ADS7828 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83L786NG is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_SENSORS_TSC210X is not set
++CONFIG_SENSORS_OMAP34XX=y
++# CONFIG_HWMON_DEBUG_CHIP is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_OMAP_WATCHDOG=y
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_TPS65010 is not set
++CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_PCF50633 is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++CONFIG_VIDEO_DEV=m
++CONFIG_VIDEO_V4L2_COMMON=m
++CONFIG_VIDEO_ALLOW_V4L1=y
++CONFIG_VIDEO_V4L1_COMPAT=y
++CONFIG_DVB_CORE=m
++CONFIG_VIDEO_MEDIA=m
++
++#
++# Multimedia drivers
++#
++CONFIG_MEDIA_ATTACH=y
++CONFIG_MEDIA_TUNER=m
++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
++CONFIG_MEDIA_TUNER_SIMPLE=m
++CONFIG_MEDIA_TUNER_TDA8290=m
++CONFIG_MEDIA_TUNER_TDA9887=m
++CONFIG_MEDIA_TUNER_TEA5761=m
++CONFIG_MEDIA_TUNER_TEA5767=m
++CONFIG_MEDIA_TUNER_MT20XX=m
++CONFIG_MEDIA_TUNER_XC2028=m
++CONFIG_MEDIA_TUNER_XC5000=m
++CONFIG_VIDEO_V4L2=m
++CONFIG_VIDEO_V4L1=m
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++# CONFIG_VIDEO_VIVI is not set
++# CONFIG_VIDEO_CPIA is not set
++# CONFIG_VIDEO_SAA5246A is not set
++# CONFIG_VIDEO_SAA5249 is not set
++# CONFIG_SOC_CAMERA is not set
++CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_TEA5764 is not set
++# CONFIG_DVB_DYNAMIC_MINORS is not set
++CONFIG_DVB_CAPTURE_DRIVERS=y
++# CONFIG_TTPCI_EEPROM is not set
++# CONFIG_DVB_B2C2_FLEXCOP is not set
++
++#
++# Supported DVB Frontends
++#
++
++#
++# Customise DVB Frontends
++#
++# CONFIG_DVB_FE_CUSTOMISE is not set
++
++#
++# Multistandard (satellite) frontends
++#
++# CONFIG_DVB_STB0899 is not set
++# CONFIG_DVB_STB6100 is not set
++
++#
++# DVB-S (satellite) frontends
++#
++CONFIG_DVB_CX24110=m
++CONFIG_DVB_CX24123=m
++CONFIG_DVB_MT312=m
++CONFIG_DVB_S5H1420=m
++# CONFIG_DVB_STV0288 is not set
++# CONFIG_DVB_STB6000 is not set
++CONFIG_DVB_STV0299=m
++CONFIG_DVB_TDA8083=m
++CONFIG_DVB_TDA10086=m
++# CONFIG_DVB_TDA8261 is not set
++CONFIG_DVB_VES1X93=m
++CONFIG_DVB_TUNER_ITD1000=m
++# CONFIG_DVB_TUNER_CX24113 is not set
++CONFIG_DVB_TDA826X=m
++CONFIG_DVB_TUA6100=m
++# CONFIG_DVB_CX24116 is not set
++# CONFIG_DVB_SI21XX is not set
++
++#
++# DVB-T (terrestrial) frontends
++#
++CONFIG_DVB_SP8870=m
++CONFIG_DVB_SP887X=m
++CONFIG_DVB_CX22700=m
++CONFIG_DVB_CX22702=m
++# CONFIG_DVB_DRX397XD is not set
++CONFIG_DVB_L64781=m
++CONFIG_DVB_TDA1004X=m
++CONFIG_DVB_NXT6000=m
++CONFIG_DVB_MT352=m
++CONFIG_DVB_ZL10353=m
++CONFIG_DVB_DIB3000MB=m
++CONFIG_DVB_DIB3000MC=m
++CONFIG_DVB_DIB7000M=m
++CONFIG_DVB_DIB7000P=m
++CONFIG_DVB_TDA10048=m
++
++#
++# DVB-C (cable) frontends
++#
++CONFIG_DVB_VES1820=m
++CONFIG_DVB_TDA10021=m
++CONFIG_DVB_TDA10023=m
++CONFIG_DVB_STV0297=m
++
++#
++# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
++#
++CONFIG_DVB_NXT200X=m
++# CONFIG_DVB_OR51211 is not set
++# CONFIG_DVB_OR51132 is not set
++CONFIG_DVB_BCM3510=m
++CONFIG_DVB_LGDT330X=m
++# CONFIG_DVB_LGDT3304 is not set
++CONFIG_DVB_S5H1409=m
++CONFIG_DVB_AU8522=m
++CONFIG_DVB_S5H1411=m
++
++#
++# ISDB-T (terrestrial) frontends
++#
++# CONFIG_DVB_S921 is not set
++
++#
++# Digital terrestrial only tuners/PLL
++#
++CONFIG_DVB_PLL=m
++CONFIG_DVB_TUNER_DIB0070=m
++
++#
++# SEC control devices for DVB-S
++#
++CONFIG_DVB_LNBP21=m
++# CONFIG_DVB_ISL6405 is not set
++CONFIG_DVB_ISL6421=m
++# CONFIG_DVB_LGS8GL5 is not set
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++# CONFIG_DVB_AF9013 is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=m
++CONFIG_FB_CFB_COPYAREA=m
++CONFIG_FB_CFB_IMAGEBLIT=m
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_VRAM_SIZE=8
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=m
++CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=m
++# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
++# CONFIG_PANEL_N800 is not set
++# CONFIG_CTRL_BLIZZARD is not set
++CONFIG_FB_OMAP2=m
++CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=y
++
++#
++# Display hardware drivers
++#
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# CONFIG_LOGO is not set
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++CONFIG_HID_DEBUG=y
++# CONFIG_HIDRAW is not set
++# CONFIG_HID_PID is not set
++
++#
++# Special HID drivers
++#
++CONFIG_HID_COMPAT=y
++# CONFIG_HID_APPLE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++# CONFIG_USB is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SOC=y
++
++#
++# OMAP 343x high speed USB support
++#
++# CONFIG_USB_MUSB_HOST is not set
++CONFIG_USB_MUSB_PERIPHERAL=y
++# CONFIG_USB_MUSB_OTG is not set
++CONFIG_USB_GADGET_MUSB_HDRC=y
++CONFIG_MUSB_PIO_ONLY=y
++# CONFIG_USB_MUSB_DEBUG is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_IMX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_CI13XXX is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=y
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_ISP1301_OMAP is not set
++CONFIG_TWL4030_USB=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++CONFIG_SDIO_UART=y
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_SDHCI is not set
++CONFIG_MMC_OMAP_HS=y
++# CONFIG_MMC_SPI is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++
++#
++# LED drivers
++#
++# CONFIG_LEDS_OMAP_DEBUG is not set
++# CONFIG_LEDS_OMAP is not set
++# CONFIG_LEDS_OMAP_PWM is not set
++# CONFIG_LEDS_PCA9532 is not set
++CONFIG_LEDS_GPIO=y
++# CONFIG_LEDS_PCA955X is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++CONFIG_RTC_DRV_TWL4030=y
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_DS3234 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_DMADEVICES is not set
++# CONFIG_REGULATOR is not set
++# CONFIG_UIO is not set
++# CONFIG_STAGING is not set
++
++#
++# CBUS support
++#
++# CONFIG_CBUS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++# CONFIG_EXT4_FS is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_FILE_LOCKING=y
++CONFIG_XFS_FS=m
++# CONFIG_XFS_QUOTA is not set
++# CONFIG_XFS_POSIX_ACL is not set
++# CONFIG_XFS_RT is not set
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_QUOTA=y
++# CONFIG_QUOTA_NETLINK_INTERFACE is not set
++CONFIG_PRINT_QUOTA_WARNING=y
++CONFIG_QUOTA_TREE=y
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++CONFIG_FUSE_FS=m
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_JFFS2_FS_XATTR=y
++CONFIG_JFFS2_FS_POSIX_ACL=y
++CONFIG_JFFS2_FS_SECURITY=y
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_LZO=y
++CONFIG_JFFS2_RTIME=y
++CONFIG_JFFS2_RUBIN=y
++# CONFIG_JFFS2_CMODE_NONE is not set
++CONFIG_JFFS2_CMODE_PRIORITY=y
++# CONFIG_JFFS2_CMODE_SIZE is not set
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_EXPORTFS=m
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_SCHED_DEBUG=y
++CONFIG_SCHEDSTATS=y
++CONFIG_TIMER_STATS=y
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++CONFIG_STACKTRACE=y
++# CONFIG_DEBUG_KOBJECT is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_NOP_TRACER=y
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_RING_BUFFER=y
++CONFIG_TRACING=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
++# CONFIG_IRQSOFF_TRACER is not set
++# CONFIG_SCHED_TRACER is not set
++# CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_TRACE_BRANCH_PROFILING is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_FTRACE_STARTUP_TEST is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_DEBUG_USER is not set
++# CONFIG_DEBUG_ERRORS is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_LL is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_XOR_BLOCKS=m
++CONFIG_ASYNC_CORE=m
++CONFIG_ASYNC_MEMCPY=m
++CONFIG_ASYNC_XOR=m
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++# CONFIG_CRYPTO_FIPS is not set
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++CONFIG_CRYPTO_GF128MUL=m
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_CRYPTD=m
++# CONFIG_CRYPTO_AUTHENC is not set
++CONFIG_CRYPTO_TEST=m
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=m
++CONFIG_CRYPTO_PCBC=m
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_HMAC=m
++CONFIG_CRYPTO_XCBC=m
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++CONFIG_CRYPTO_MD4=m
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++CONFIG_CRYPTO_SHA1=m
++CONFIG_CRYPTO_SHA256=m
++CONFIG_CRYPTO_SHA512=m
++CONFIG_CRYPTO_TGR192=m
++CONFIG_CRYPTO_WP512=m
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++CONFIG_CRYPTO_ANUBIS=m
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_BLOWFISH=m
++CONFIG_CRYPTO_CAMELLIA=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_CAST6=m
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_FCRYPT=m
++CONFIG_CRYPTO_KHAZAD=m
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++CONFIG_CRYPTO_SERPENT=m
++CONFIG_CRYPTO_TEA=m
++CONFIG_CRYPTO_TWOFISH=m
++CONFIG_CRYPTO_TWOFISH_COMMON=m
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=m
++# CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_FIND_LAST_BIT=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++CONFIG_CRC7=y
++CONFIG_LIBCRC32C=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
+index 8780ca6..ca4680a 100644
+--- a/arch/arm/mach-omap1/board-nokia770.c
++++ b/arch/arm/mach-omap1/board-nokia770.c
+@@ -18,6 +18,7 @@
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
+ #include <linux/workqueue.h>
++#include <linux/omapfb.h>
+ #include <linux/delay.h>
+
+ #include <mach/hardware.h>
+@@ -32,7 +33,6 @@
+ #include <mach/keypad.h>
+ #include <mach/common.h>
+ #include <mach/dsp_common.h>
+-#include <mach/omapfb.h>
+ #include <mach/lcd_mipid.h>
+ #include <mach/mmc.h>
+ #include <mach/usb.h>
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 0a1099e..2bba94d 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -255,8 +255,226 @@ static struct regulator_consumer_supply sdp3430_vdac_supply = {
+ static struct regulator_consumer_supply sdp3430_vdvi_supply = {
+ .supply = "vdvi",
+ .dev = &sdp3430_lcd_device.dev,
++
++#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
++#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
++#if 0
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 24
++#define SDP3430_LCD_PANEL_ENABLE_GPIO 28
++#else
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
++#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
++#endif
++
++#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
++#define ENABLE_VAUX2_DEDICATED 0x09
++#define ENABLE_VAUX2_DEV_GRP 0x20
++#define ENABLE_VAUX3_DEDICATED 0x03
++#define ENABLE_VAUX3_DEV_GRP 0x20
++
++#define ENABLE_VPLL2_DEDICATED 0x05
++#define ENABLE_VPLL2_DEV_GRP 0xE0
++#define TWL4030_VPLL2_DEV_GRP 0x33
++#define TWL4030_VPLL2_DEDICATED 0x36
++
++#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
++
++static unsigned backlight_gpio;
++static unsigned enable_gpio;
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void enable_vpll2(int enable)
++{
++ u8 ded_val, grp_val;
++
++ if (enable) {
++ ded_val = ENABLE_VPLL2_DEDICATED;
++ grp_val = ENABLE_VPLL2_DEV_GRP;
++ } else {
++ ded_val = 0;
++ grp_val = 0;
++ }
++
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ded_val, TWL4030_VPLL2_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ grp_val, TWL4030_VPLL2_DEV_GRP);
++}
++
++static int sdp3430_dsi_power_up(void)
++{
++ if (omap_rev() > OMAP3430_REV_ES1_0)
++ enable_vpll2(1);
++ return 0;
++}
++
++static void sdp3430_dsi_power_down(void)
++{
++ if (omap_rev() > OMAP3430_REV_ES1_0)
++ enable_vpll2(0);
++}
++
++static void __init sdp3430_display_init(void)
++{
++ int r;
++
++ enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
++ backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
++
++ r = gpio_request(enable_gpio, "LCD reset");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD reset GPIO\n");
++ goto err0;
++ }
++
++ r = gpio_request(backlight_gpio, "LCD Backlight");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD backlight GPIO\n");
++ goto err1;
++ }
++
++ gpio_direction_output(enable_gpio, 0);
++ gpio_direction_output(backlight_gpio, 0);
++
++ return;
++err1:
++ gpio_free(enable_gpio);
++err0:
++ return;
++}
++
++
++static int sdp3430_panel_enable_lcd(struct omap_display *display)
++{
++ u8 ded_val, ded_reg;
++ u8 grp_val, grp_reg;
++
++ if (dvi_enabled) {
++ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++ return -EINVAL;
++ }
++
++ ded_reg = TWL4030_VAUX3_DEDICATED;
++ ded_val = ENABLE_VAUX3_DEDICATED;
++ grp_reg = TWL4030_VAUX3_DEV_GRP;
++ grp_val = ENABLE_VAUX3_DEV_GRP;
++
++ gpio_direction_output(enable_gpio, 1);
++ gpio_direction_output(backlight_gpio, 1);
++
++ if (0 != t2_out(PM_RECEIVER, ded_val, ded_reg))
++ return -EIO;
++ if (0 != t2_out(PM_RECEIVER, grp_val, grp_reg))
++ return -EIO;
++
++ sdp3430_dsi_power_up();
++
++ lcd_enabled = 1;
++
++ return 0;
++}
++
++static void sdp3430_panel_disable_lcd(struct omap_display *display)
++{
++ lcd_enabled = 0;
++
++ sdp3430_dsi_power_down();
++
++ gpio_direction_output(enable_gpio, 0);
++ gpio_direction_output(backlight_gpio, 0);
++}
++
++static struct omap_dss_display_config sdp3430_display_data = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "lcd",
++ .panel_name = "sharp-ls037v7dw01",
++ .u.dpi.data_lines = 16,
++ .panel_enable = sdp3430_panel_enable_lcd,
++ .panel_disable = sdp3430_panel_disable_lcd,
+ };
+
++static int sdp3430_panel_enable_dvi(struct omap_display *display)
++{
++ if (lcd_enabled) {
++ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++ return -EINVAL;
++ }
++
++ sdp3430_dsi_power_up();
++
++ dvi_enabled = 1;
++
++ return 0;
++}
++
++static void sdp3430_panel_disable_dvi(struct omap_display *display)
++{
++ sdp3430_dsi_power_down();
++
++ dvi_enabled = 0;
++}
++
++
++static struct omap_dss_display_config sdp3430_display_data_dvi = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "dvi",
++ .panel_name = "panel-generic",
++ .u.dpi.data_lines = 24,
++ .panel_enable = sdp3430_panel_enable_dvi,
++ .panel_disable = sdp3430_panel_disable_dvi,
++};
++
++static int sdp3430_panel_enable_tv(struct omap_display *display)
++{
++#define ENABLE_VDAC_DEDICATED 0x03
++#define ENABLE_VDAC_DEV_GRP 0x20
++
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VDAC_DEDICATED,
++ TWL4030_VDAC_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++
++ return 0;
++}
++
++static void sdp3430_panel_disable_tv(struct omap_display *display)
++{
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++ TWL4030_VDAC_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++ TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_dss_display_config sdp3430_display_data_tv = {
++ .type = OMAP_DISPLAY_TYPE_VENC,
++ .name = "tv",
++ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++ .panel_enable = sdp3430_panel_enable_tv,
++ .panel_disable = sdp3430_panel_disable_tv,
++};
++
++static struct omap_dss_board_info sdp3430_dss_data = {
++ .dsi_power_up = sdp3430_dsi_power_up,
++ .dsi_power_down = sdp3430_dsi_power_down,
++ .num_displays = 3,
++ .displays = {
++ &sdp3430_display_data,
++ &sdp3430_display_data_dvi,
++ &sdp3430_display_data_tv,
++ }
++};
++
++static struct platform_device sdp3430_dss_device = {
++ .name = "omapdss",
++ .id = -1,
++ .dev = {
++ .platform_data = &sdp3430_dss_data,
++ },
++};
++
++
+ static struct platform_device *sdp3430_devices[] __initdata = {
+ &sdp3430_smc91x_device,
+ &sdp3430_lcd_device,
+diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
+index 60a414c..6abfdb4 100644
+--- a/arch/arm/mach-omap2/board-n800.c
++++ b/arch/arm/mach-omap2/board-n800.c
+@@ -27,6 +27,7 @@
+ #include <linux/i2c/lm8323.h>
+ #include <linux/i2c/menelaus.h>
+ #include <linux/i2c/lp5521.h>
++#include <linux/omapfb.h>
+ #include <mach/hardware.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -39,8 +40,8 @@
+ #include <mach/lcd_mipid.h>
+ #include <mach/clock.h>
+ #include <mach/gpio-switch.h>
+-#include <mach/omapfb.h>
+ #include <mach/blizzard.h>
++#include <mach/display.h>
+
+ #include <../drivers/cbus/tahvo.h>
+ #include <../drivers/media/video/tcm825x.h>
+@@ -161,23 +162,176 @@ static struct omap_uart_config n800_uart_config __initdata = {
+
+ #include "../../../drivers/cbus/retu.h"
+
+-static struct omap_fbmem_config n800_fbmem0_config __initdata = {
+- .size = 752 * 1024,
++static struct omap_tmp105_config n800_tmp105_config __initdata = {
++ .tmp105_irq_pin = 125,
++ .set_power = n800_tmp105_set_power,
+ };
+
+-static struct omap_fbmem_config n800_fbmem1_config __initdata = {
+- .size = 752 * 1024,
+-};
+
+-static struct omap_fbmem_config n800_fbmem2_config __initdata = {
+- .size = 752 * 1024,
++
++
++/* DISPLAY */
++static struct {
++ struct clk *sys_ck;
++} blizzard;
++
++static int blizzard_get_clocks(void)
++{
++ blizzard.sys_ck = clk_get(0, "osc_ck");
++ if (IS_ERR(blizzard.sys_ck)) {
++ printk(KERN_ERR "can't get Blizzard clock\n");
++ return PTR_ERR(blizzard.sys_ck);
++ }
++ return 0;
++}
++
++static unsigned long blizzard_get_clock_rate(void)
++{
++ return clk_get_rate(blizzard.sys_ck);
++}
++
++static int n800_pn800_enable(struct omap_display *display)
++{
++ if (display->hw_config.panel_reset_gpio != -1) {
++ printk("enabling panel gpio\n");
++ gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++ }
++
++ return 0;
++}
++
++static void n800_pn800_disable(struct omap_display *display)
++{
++ if (display->hw_config.panel_reset_gpio != -1) {
++ printk("disabling panel gpio\n");
++ gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++ msleep(120);
++ }
++}
++
++static int n800_blizzard_enable(struct omap_display *display)
++{
++ printk("enabling bliz powers\n");
++
++ /* Vcore to 1.475V */
++ tahvo_set_clear_reg_bits(0x07, 0, 0xf);
++ msleep(10);
++
++ clk_enable(blizzard.sys_ck);
++
++ if (display->hw_config.ctrl_reset_gpio != -1)
++ gpio_direction_output(display->hw_config.ctrl_reset_gpio, 1);
++
++ printk("osc_ck %lu\n", blizzard_get_clock_rate());
++
++ return 0;
++}
++
++static void n800_blizzard_disable(struct omap_display *display)
++{
++ printk("disabling bliz powers\n");
++
++ if (display->hw_config.ctrl_reset_gpio != -1)
++ gpio_direction_output(display->hw_config.ctrl_reset_gpio, 0);
++
++ clk_disable(blizzard.sys_ck);
++
++ /* Vcore to 1.005V */
++ tahvo_set_clear_reg_bits(0x07, 0xf, 0);
++}
++
++static int n800_set_backlight_level(struct omap_display *display, int level)
++{
++ return 0;
++}
++
++static struct omap_dss_display_config n800_dsi_display_data = {
++ .type = OMAP_DISPLAY_TYPE_DBI,
++ .name = "lcd",
++ .ctrl_name = "ctrl-blizzard",
++ .panel_name = "panel-pn800",
++ .panel_reset_gpio = -1,
++ .ctrl_reset_gpio = N800_BLIZZARD_POWERDOWN_GPIO,
++ .panel_enable = n800_pn800_enable,
++ .panel_disable = n800_pn800_disable,
++ .ctrl_enable = n800_blizzard_enable,
++ .ctrl_disable = n800_blizzard_disable,
++ .set_backlight = n800_set_backlight_level,
++ .u.rfbi = {
++ .channel = 0,
++ /* 8 for cmd mode, 16 for pixel data. ctrl-blizzard handles switching */
++ .data_lines = 8,
++ },
++ .panel_data = 0, // XXX used for panel datalines
++};
++static struct omap_dss_board_info n800_dss_data = {
++ .num_displays = 1,
++ .displays = {
++ &n800_dsi_display_data,
++ },
+ };
+
+-static struct omap_tmp105_config n800_tmp105_config __initdata = {
+- .tmp105_irq_pin = 125,
+- .set_power = n800_tmp105_set_power,
++static struct platform_device n800_dss_device = {
++ .name = "omapdss",
++ .id = -1,
++ .dev = {
++ .platform_data = &n800_dss_data,
++ },
+ };
+
++static void __init n800_display_init(void)
++{
++ int r;
++ const struct omap_lcd_config *conf;
++
++ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
++ if (conf != NULL) {
++ n800_dsi_display_data.panel_reset_gpio = conf->nreset_gpio;
++ n800_dsi_display_data.panel_data =
++ (void*)(u32)conf->data_lines; // XXX
++ //printk("\n\nTULI %d\n\n", conf->data_lines);
++ } else {
++ printk("\n\nEI TULLU MIOTÄÄÄ\n\n");
++ }
++
++ blizzard_get_clocks();
++ clk_enable(blizzard.sys_ck); // XXX always enable
++
++ //omapfb_set_ctrl_platform_data(&n800_blizzard_data);
++ //
++ if (n800_dsi_display_data.ctrl_reset_gpio != -1) {
++ r = gpio_request(n800_dsi_display_data.ctrl_reset_gpio,
++ "Blizzard pd");
++ if (r < 0) {
++ n800_dsi_display_data.ctrl_reset_gpio = -1;
++ printk(KERN_ERR "Unable to get Blizzard GPIO\n");
++ } else {
++ gpio_direction_output(n800_dsi_display_data.ctrl_reset_gpio,
++ 1);
++ // XXX always enable
++ }
++ }
++
++ if (n800_dsi_display_data.panel_reset_gpio != -1) {
++ r = gpio_request(n800_dsi_display_data.panel_reset_gpio,
++ "panel reset");
++ if (r < 0) {
++ n800_dsi_display_data.panel_reset_gpio = -1;
++ printk(KERN_ERR "Unable to get pn800 GPIO\n");
++ } else {
++ gpio_direction_output(n800_dsi_display_data.panel_reset_gpio,
++ 1);
++ // XXX always enable
++ }
++ }
++}
++
++/* DISPLAY END */
++
++
++
++
++
+ static void mipid_shutdown(struct mipid_platform_data *pdata)
+ {
+ if (pdata->nreset_gpio != -1) {
+@@ -191,6 +345,7 @@ static struct mipid_platform_data n800_mipid_platform_data = {
+ .shutdown = mipid_shutdown,
+ };
+
++#if 0
+ static void __init mipid_dev_init(void)
+ {
+ const struct omap_lcd_config *conf;
+@@ -201,26 +356,9 @@ static void __init mipid_dev_init(void)
+ n800_mipid_platform_data.data_lines = conf->data_lines;
+ }
+ }
++#endif
+
+-static struct {
+- struct clk *sys_ck;
+-} blizzard;
+-
+-static int blizzard_get_clocks(void)
+-{
+- blizzard.sys_ck = clk_get(0, "osc_ck");
+- if (IS_ERR(blizzard.sys_ck)) {
+- printk(KERN_ERR "can't get Blizzard clock\n");
+- return PTR_ERR(blizzard.sys_ck);
+- }
+- return 0;
+-}
+-
+-static unsigned long blizzard_get_clock_rate(struct device *dev)
+-{
+- return clk_get_rate(blizzard.sys_ck);
+-}
+-
++#if 0
+ static void blizzard_enable_clocks(int enable)
+ {
+ if (enable)
+@@ -265,14 +403,12 @@ static void __init blizzard_dev_init(void)
+ gpio_direction_output(N800_BLIZZARD_POWERDOWN_GPIO, 1);
+
+ blizzard_get_clocks();
+- omapfb_set_ctrl_platform_data(&n800_blizzard_data);
++ //omapfb_set_ctrl_platform_data(&n800_blizzard_data);
+ }
++#endif
+
+ static struct omap_board_config_kernel n800_config[] __initdata = {
+ { OMAP_TAG_UART, &n800_uart_config },
+- { OMAP_TAG_FBMEM, &n800_fbmem0_config },
+- { OMAP_TAG_FBMEM, &n800_fbmem1_config },
+- { OMAP_TAG_FBMEM, &n800_fbmem2_config },
+ { OMAP_TAG_TMP105, &n800_tmp105_config },
+ };
+
+@@ -379,7 +515,7 @@ static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
+
+ static struct spi_board_info n800_spi_board_info[] __initdata = {
+ {
+- .modalias = "lcd_mipid",
++ .modalias = "panel-n800",
+ .bus_num = 1,
+ .chip_select = 1,
+ .max_speed_hz = 4000000,
+@@ -404,7 +540,7 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
+
+ static struct spi_board_info n810_spi_board_info[] __initdata = {
+ {
+- .modalias = "lcd_mipid",
++ .modalias = "panel-n800",
+ .bus_num = 1,
+ .chip_select = 1,
+ .max_speed_hz = 4000000,
+@@ -572,6 +708,7 @@ static struct platform_device *n800_devices[] __initdata = {
+ #if defined(CONFIG_CBUS_RETU) && defined(CONFIG_LEDS_OMAP_PWM)
+ &n800_keypad_led_device,
+ #endif
++ &n800_dss_device,
+ };
+
+ #ifdef CONFIG_MENELAUS
+@@ -703,9 +840,10 @@ void __init nokia_n800_common_init(void)
+ if (machine_is_nokia_n810())
+ i2c_register_board_info(2, n810_i2c_board_info_2,
+ ARRAY_SIZE(n810_i2c_board_info_2));
+-
+- mipid_dev_init();
+- blizzard_dev_init();
++
++ //mipid_dev_init();
++ //blizzard_dev_init();
++ n800_display_init();
+ }
+
+ static void __init nokia_n800_init(void)
+@@ -726,6 +864,7 @@ void __init nokia_n800_map_io(void)
+ omap_board_config_size = ARRAY_SIZE(n800_config);
+
+ omap2_set_globals_242x();
++ omap2_set_sdram_vram(800 * 480 * 2 * 3, 0);
+ omap2_map_common_io();
+ }
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 346351e..7d2716b 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -30,6 +30,7 @@
+
+ #include <linux/regulator/machine.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/hardware.h>
+ #include <asm/mach-types.h>
+@@ -43,6 +44,7 @@
+ #include <mach/gpmc.h>
+ #include <mach/nand.h>
+ #include <mach/mux.h>
++#include <mach/display.h>
+
+ #include "twl4030-generic-scripts.h"
+ #include "mmc-twl4030.h"
+@@ -369,13 +371,94 @@ static struct platform_device keys_gpio = {
+ },
+ };
+
++/* DSS */
++
++static int beagle_enable_dvi(struct omap_display *display)
++{
++ if (display->hw_config.panel_reset_gpio != -1)
++ gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
++
++ return 0;
++}
++
++static void beagle_disable_dvi(struct omap_display *display)
++{
++ if (display->hw_config.panel_reset_gpio != -1)
++ gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
++}
++
++static struct omap_dss_display_config beagle_display_data_dvi = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "dvi",
++ .panel_name = "panel-generic",
++ .u.dpi.data_lines = 24,
++ .panel_reset_gpio = 170,
++ .panel_enable = beagle_enable_dvi,
++ .panel_disable = beagle_disable_dvi,
++};
++
++
++static int beagle_panel_enable_tv(struct omap_display *display)
++{
++#define ENABLE_VDAC_DEDICATED 0x03
++#define ENABLE_VDAC_DEV_GRP 0x20
++
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VDAC_DEDICATED,
++ TWL4030_VDAC_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++
++ return 0;
++}
++
++static void beagle_panel_disable_tv(struct omap_display *display)
++{
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++ TWL4030_VDAC_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++ TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_dss_display_config beagle_display_data_tv = {
++ .type = OMAP_DISPLAY_TYPE_VENC,
++ .name = "tv",
++ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++ .panel_enable = beagle_panel_enable_tv,
++ .panel_disable = beagle_panel_disable_tv,
++};
++
++static struct omap_dss_board_info beagle_dss_data = {
++ .num_displays = 2,
++ .displays = {
++ &beagle_display_data_dvi,
++ &beagle_display_data_tv,
++ }
++};
++
++static struct platform_device beagle_dss_device = {
++ .name = "omapdss",
++ .id = -1,
++ .dev = {
++ .platform_data = &beagle_dss_data,
++ },
++};
++
++static void __init beagle_display_init(void)
++{
++ int r;
++
++ r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
++ if (r < 0)
++ printk(KERN_ERR "Unable to get DVI reset GPIO\n");
++}
++
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+ { OMAP_TAG_UART, &omap3_beagle_uart_config },
+- { OMAP_TAG_LCD, &omap3_beagle_lcd_config },
+ };
+
+ static struct platform_device *omap3_beagle_devices[] __initdata = {
+- &omap3_beagle_lcd_device,
++ &beagle_dss_device,
+ &leds_gpio,
+ &keys_gpio,
+ };
+@@ -428,13 +511,11 @@ static void __init omap3_beagle_init(void)
+ omap_serial_init();
+
+ omap_cfg_reg(J25_34XX_GPIO170);
+- gpio_request(170, "DVI_nPD");
+- /* REVISIT leave DVI powered down until it's needed ... */
+- gpio_direction_output(170, true);
+
+ usb_musb_init();
+ usb_ehci_init();
+ omap3beagle_flash_init();
++ beagle_display_init();
+ }
+
+ static void __init omap3_beagle_map_io(void)
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 024d7c4..7a720ec 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -36,6 +36,7 @@
+ #include <mach/usb.h>
+ #include <mach/common.h>
+ #include <mach/mcspi.h>
++#include <mach/display.h>
+
+ #include "sdram-micron-mt46h32m32lf-6.h"
+ #include "twl4030-generic-scripts.h"
+@@ -216,13 +217,201 @@ static int __init omap3_evm_i2c_init(void)
+ return 0;
+ }
+
+-static struct platform_device omap3_evm_lcd_device = {
+- .name = "omap3evm_lcd",
+- .id = -1,
++#define LCD_PANEL_LR 2
++#define LCD_PANEL_UD 3
++#define LCD_PANEL_INI 152
++#define LCD_PANEL_ENABLE_GPIO 153
++#define LCD_PANEL_QVGA 154
++#define LCD_PANEL_RESB 155
++
++#define ENABLE_VDAC_DEDICATED 0x03
++#define ENABLE_VDAC_DEV_GRP 0x20
++#define ENABLE_VPLL2_DEDICATED 0x05
++#define ENABLE_VPLL2_DEV_GRP 0xE0
++
++#define TWL4030_GPIODATA_IN3 0x03
++#define TWL4030_GPIODATA_DIR3 0x06
++#define TWL4030_VPLL2_DEV_GRP 0x33
++#define TWL4030_VPLL2_DEDICATED 0x36
++
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init omap3_evm_display_init(void)
++{
++ int r;
++ r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
++ return;
++ }
++ r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
++ goto err_1;
++ }
++
++ r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
++ goto err_2;
++ }
++ r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
++ goto err_3;
++ }
++ r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
++ if (r) {
++ printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
++ goto err_4;
++ }
++
++ gpio_direction_output(LCD_PANEL_LR, 0);
++ gpio_direction_output(LCD_PANEL_UD, 0);
++ gpio_direction_output(LCD_PANEL_INI, 0);
++ gpio_direction_output(LCD_PANEL_RESB, 0);
++ gpio_direction_output(LCD_PANEL_QVGA, 0);
++
++#define TWL_LED_LEDEN 0x00
++#define TWL_PWMA_PWMAON 0x00
++#define TWL_PWMA_PWMAOFF 0x01
++
++ twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
++
++ gpio_direction_output(LCD_PANEL_RESB, 1);
++ gpio_direction_output(LCD_PANEL_INI, 1);
++ gpio_direction_output(LCD_PANEL_QVGA, 0);
++ gpio_direction_output(LCD_PANEL_LR, 1);
++ gpio_direction_output(LCD_PANEL_UD, 1);
++
++ return;
++
++err_4:
++ gpio_free(LCD_PANEL_RESB);
++err_3:
++ gpio_free(LCD_PANEL_INI);
++err_2:
++ gpio_free(LCD_PANEL_UD);
++err_1:
++ gpio_free(LCD_PANEL_LR);
++
++}
++
++static int omap3_evm_panel_enable_lcd(struct omap_display *display)
++{
++ if (dvi_enabled) {
++ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++ return -EINVAL;
++ }
++ if (omap_rev() > OMAP3430_REV_ES1_0) {
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
++ }
++ gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
++ lcd_enabled = 1;
++ return 0;
++}
++
++static void omap3_evm_panel_disable_lcd(struct omap_display *display)
++{
++ if (omap_rev() > OMAP3430_REV_ES1_0) {
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++ TWL4030_VPLL2_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
++ TWL4030_VPLL2_DEV_GRP);
++ }
++ gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
++ lcd_enabled = 0;
++}
++
++static struct omap_display_data omap3_evm_display_data = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "lcd",
++ .panel_name = "sharp-ls037v7dw01",
++ .u.dpi.data_lines = 18,
++ .panel_enable = omap3_evm_panel_enable_lcd,
++ .panel_disable = omap3_evm_panel_disable_lcd,
+ };
+
+-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
+- .ctrl_name = "internal",
++static int omap3_evm_panel_enable_tv(struct omap_display *display)
++{
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
++ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
++ return 0;
++}
++
++static void omap3_evm_panel_disable_tv(struct omap_display *display)
++{
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++ TWL4030_VDAC_DEDICATED);
++ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
++ TWL4030_VDAC_DEV_GRP);
++}
++
++static struct omap_display_data omap3_evm_display_data_tv = {
++ .type = OMAP_DISPLAY_TYPE_VENC,
++ .name = "tv",
++ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
++ .panel_enable = omap3_evm_panel_enable_tv,
++ .panel_disable = omap3_evm_panel_disable_tv,
++};
++
++
++static int omap3_evm_panel_enable_dvi(struct omap_display *display)
++{
++ if (lcd_enabled) {
++ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++ return -EINVAL;
++ }
++ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++ TWL4030_GPIODATA_IN3);
++ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
++ TWL4030_GPIODATA_DIR3);
++ dvi_enabled = 1;
++
++ return 0;
++}
++
++static void omap3_evm_panel_disable_dvi(struct omap_display *display)
++{
++ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++ TWL4030_GPIODATA_IN3);
++ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
++ TWL4030_GPIODATA_DIR3);
++ dvi_enabled = 0;
++}
++
++
++static struct omap_display_data omap3_evm_display_data_dvi = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "dvi",
++ .panel_name = "panel-generic",
++ .u.dpi.data_lines = 24,
++ .panel_enable = omap3_evm_panel_enable_dvi,
++ .panel_disable = omap3_evm_panel_disable_dvi,
++};
++
++static struct omap_dss_platform_data omap3_evm_dss_data = {
++ .num_displays = 3,
++ .displays = {
++ &omap3_evm_display_data,
++ &omap3_evm_display_data_dvi,
++ &omap3_evm_display_data_tv,
++ }
++};
++static struct platform_device omap3_evm_dss_device = {
++ .name = "omapdss",
++ .id = -1,
++ .dev = {
++ .platform_data = &omap3_evm_dss_data,
++ },
+ };
+
+ static void ads7846_dev_init(void)
+@@ -281,11 +470,10 @@ static void __init omap3_evm_init_irq(void)
+
+ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+ { OMAP_TAG_UART, &omap3_evm_uart_config },
+- { OMAP_TAG_LCD, &omap3_evm_lcd_config },
+ };
+
+ static struct platform_device *omap3_evm_devices[] __initdata = {
+- &omap3_evm_lcd_device,
++ &omap3_evm_dss_device,
+ &omap3evm_smc911x_device,
+ };
+
+@@ -305,6 +493,7 @@ static void __init omap3_evm_init(void)
+ usb_ehci_init();
+ omap3evm_flash_init();
+ ads7846_dev_init();
++ omap3_evm_display_init();
+ }
+
+ static void __init omap3_evm_map_io(void)
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index 071f4b0..267bb6b 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -41,6 +41,7 @@
+ #include <mach/board-overo.h>
+ #include <mach/board.h>
+ #include <mach/common.h>
++#include <mach/display.h>
+ #include <mach/gpio.h>
+ #include <mach/gpmc.h>
+ #include <mach/hardware.h>
+@@ -176,6 +177,9 @@ static void __init overo_ads7846_init(void)
+ static inline void __init overo_ads7846_init(void) { return; }
+ #endif
+
++static int lcd_enabled;
++static int dvi_enabled;
++
+ static struct mtd_partition overo_nand_partitions[] = {
+ {
+ .name = "xloader",
+@@ -360,22 +364,101 @@ static void __init overo_init_irq(void)
+ omap_gpio_init();
+ }
+
+-static struct platform_device overo_lcd_device = {
+- .name = "overo_lcd",
+- .id = -1,
++/* DSS */
++
++#define OVERO_GPIO_LCD_EN 144
++
++static void __init overo_display_init(void)
++{
++ int r;
++
++ r = gpio_request(OVERO_GPIO_LCD_EN, "display enable");
++ if (r)
++ printk("fail1\n");
++ r = gpio_direction_output(OVERO_GPIO_LCD_EN, 1);
++ if (r)
++ printk("fail2\n");
++ gpio_export(OVERO_GPIO_LCD_EN, 0);
++}
++
++static int overo_panel_enable_dvi(struct omap_display *display)
++{
++ if (lcd_enabled) {
++ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++ return -EINVAL;
++ }
++ dvi_enabled = 1;
++
++ gpio_set_value(OVERO_GPIO_LCD_EN, 1);
++
++ return 0;
++}
++
++static void overo_panel_disable_dvi(struct omap_display *display)
++{
++ gpio_set_value(OVERO_GPIO_LCD_EN, 0);
++
++ dvi_enabled = 0;
++}
++
++static struct omap_dss_display_config overo_display_data_dvi = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "dvi",
++ .panel_name = "panel-generic",
++ .u.dpi.data_lines = 24,
++ .panel_enable = overo_panel_enable_dvi,
++ .panel_disable = overo_panel_disable_dvi,
+ };
+
+-static struct omap_lcd_config overo_lcd_config __initdata = {
+- .ctrl_name = "internal",
++static int overo_panel_enable_lcd(struct omap_display *display)
++{
++ if (dvi_enabled) {
++ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++ return -EINVAL;
++ }
++
++ gpio_set_value(OVERO_GPIO_LCD_EN, 1);
++ lcd_enabled = 1;
++ return 0;
++}
++
++static void overo_panel_disable_lcd(struct omap_display *display)
++{
++ gpio_set_value(OVERO_GPIO_LCD_EN, 0);
++ lcd_enabled = 0;
++}
++
++static struct omap_dss_display_config overo_display_data_lcd = {
++ .type = OMAP_DISPLAY_TYPE_DPI,
++ .name = "lcd",
++ .panel_name = "samsung-lte430wq-f0c",
++ .u.dpi.data_lines = 24,
++ .panel_enable = overo_panel_enable_lcd,
++ .panel_disable = overo_panel_disable_lcd,
++ };
++
++static struct omap_dss_board_info overo_dss_data = {
++ .num_displays = 2,
++ .displays = {
++ &overo_display_data_dvi,
++ &overo_display_data_lcd,
++ }
++};
++
++static struct platform_device overo_dss_device = {
++ .name = "omapdss",
++ .id = -1,
++ .dev = {
++ .platform_data = &overo_dss_data,
++ },
+ };
+
+ static struct omap_board_config_kernel overo_config[] __initdata = {
+ { OMAP_TAG_UART, &overo_uart_config },
+- { OMAP_TAG_LCD, &overo_lcd_config },
+ };
+
+ static struct platform_device *overo_devices[] __initdata = {
+- &overo_lcd_device,
++ &overo_dss_device,
+ };
+
+ static void __init overo_init(void)
+@@ -390,6 +473,7 @@ static void __init overo_init(void)
+ overo_flash_init();
+ overo_init_smsc911x();
+ overo_ads7846_init();
++ overo_display_init();
+
+ if ((gpio_request(OVERO_GPIO_W2W_NRESET,
+ "OVERO_GPIO_W2W_NRESET") == 0) &&
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index adbe21f..a04e3ee 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -18,13 +18,13 @@
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
++#include <linux/omapfb.h>
+ #include <linux/io.h>
+
+ #include <asm/tlb.h>
+
+ #include <asm/mach/map.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <mach/sram.h>
+ #include <mach/sdrc.h>
+ #include <mach/gpmc.h>
+diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
+index 3ebc09e..e6146b2 100644
+--- a/arch/arm/plat-omap/Makefile
++++ b/arch/arm/plat-omap/Makefile
+@@ -4,7 +4,7 @@
+
+ # Common support
+ obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
+- usb.o fb.o io.o
++ usb.o fb.o vram.o vrfb.o io.o
+ obj-m :=
+ obj-n :=
+ obj- :=
+diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
+index 3746222..1dc3415 100644
+--- a/arch/arm/plat-omap/fb.c
++++ b/arch/arm/plat-omap/fb.c
+@@ -28,13 +28,13 @@
+ #include <linux/platform_device.h>
+ #include <linux/bootmem.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+
+ #include <mach/hardware.h>
+ #include <asm/mach/map.h>
+
+ #include <mach/board.h>
+ #include <mach/sram.h>
+-#include <mach/omapfb.h>
+
+ #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
+
+@@ -327,6 +327,34 @@ static inline int omap_init_fb(void)
+
+ arch_initcall(omap_init_fb);
+
++#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++static u64 omap_fb_dma_mask = ~(u32)0;
++static struct omapfb_platform_data omapfb_config;
++
++static struct platform_device omap_fb_device = {
++ .name = "omapfb",
++ .id = -1,
++ .dev = {
++ .dma_mask = &omap_fb_dma_mask,
++ .coherent_dma_mask = ~(u32)0,
++ .platform_data = &omapfb_config,
++ },
++ .num_resources = 0,
++};
++
++void omapfb_set_platform_data(struct omapfb_platform_data *data)
++{
++ omapfb_config = *data;
++}
++
++static inline int omap_init_fb(void)
++{
++ return platform_device_register(&omap_fb_device);
++}
++
++arch_initcall(omap_init_fb);
++
+ #else
+
+ void omapfb_reserve_sdram(void) {}
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+new file mode 100644
+index 0000000..6288353
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -0,0 +1,520 @@
++/*
++ * linux/include/asm-arm/arch-omap/display.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __ASM_ARCH_OMAP_DISPLAY_H
++#define __ASM_ARCH_OMAP_DISPLAY_H
++
++#include <linux/list.h>
++#include <linux/kobject.h>
++#include <asm/atomic.h>
++
++#define DISPC_IRQ_FRAMEDONE (1 << 0)
++#define DISPC_IRQ_VSYNC (1 << 1)
++#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
++#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
++#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
++#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
++#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
++#define DISPC_IRQ_GFX_END_WIN (1 << 7)
++#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
++#define DISPC_IRQ_OCP_ERR (1 << 9)
++#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
++#define DISPC_IRQ_VID1_END_WIN (1 << 11)
++#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
++#define DISPC_IRQ_VID2_END_WIN (1 << 13)
++#define DISPC_IRQ_SYNC_LOST (1 << 14)
++#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
++#define DISPC_IRQ_WAKEUP (1 << 16)
++
++enum omap_display_type {
++ OMAP_DISPLAY_TYPE_NONE = 0,
++ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
++ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
++ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
++ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
++ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
++};
++
++enum omap_plane {
++ OMAP_DSS_GFX = 0,
++ OMAP_DSS_VIDEO1 = 1,
++ OMAP_DSS_VIDEO2 = 2
++};
++
++enum omap_channel {
++ OMAP_DSS_CHANNEL_LCD = 0,
++ OMAP_DSS_CHANNEL_DIGIT = 1,
++};
++
++enum omap_color_mode {
++ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
++ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
++ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
++ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
++ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
++ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
++ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
++ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
++ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
++ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
++ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
++ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
++ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
++ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
++
++ OMAP_DSS_COLOR_GFX_OMAP3 =
++ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
++ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
++ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
++
++ OMAP_DSS_COLOR_VID_OMAP3 =
++ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
++ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
++};
++
++enum omap_lcd_display_type {
++ OMAP_DSS_LCD_DISPLAY_STN,
++ OMAP_DSS_LCD_DISPLAY_TFT,
++};
++
++enum omap_dss_load_mode {
++ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
++ OMAP_DSS_LOAD_CLUT_ONLY = 1,
++ OMAP_DSS_LOAD_FRAME_ONLY = 2,
++ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
++};
++
++enum omap_dss_color_key_type {
++ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
++ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
++};
++
++enum omap_rfbi_te_mode {
++ OMAP_DSS_RFBI_TE_MODE_1 = 1,
++ OMAP_DSS_RFBI_TE_MODE_2 = 2,
++};
++
++enum omap_panel_config {
++ OMAP_DSS_LCD_IVS = 1<<0,
++ OMAP_DSS_LCD_IHS = 1<<1,
++ OMAP_DSS_LCD_IPC = 1<<2,
++ OMAP_DSS_LCD_IEO = 1<<3,
++ OMAP_DSS_LCD_RF = 1<<4,
++ OMAP_DSS_LCD_ONOFF = 1<<5,
++
++ OMAP_DSS_LCD_TFT = 1<<20,
++};
++
++enum omap_dss_venc_type {
++ OMAP_DSS_VENC_TYPE_COMPOSITE,
++ OMAP_DSS_VENC_TYPE_SVIDEO,
++};
++
++struct omap_display;
++struct omap_panel;
++struct omap_ctrl;
++
++/* RFBI */
++
++struct rfbi_timings {
++ int cs_on_time;
++ int cs_off_time;
++ int we_on_time;
++ int we_off_time;
++ int re_on_time;
++ int re_off_time;
++ int we_cycle_time;
++ int re_cycle_time;
++ int cs_pulse_width;
++ int access_time;
++
++ int clk_div;
++
++ u32 tim[5]; /* set by rfbi_convert_timings() */
++
++ int converted;
++};
++
++void omap_rfbi_write_command(const void *buf, u32 len);
++void omap_rfbi_read_data(void *buf, u32 len);
++void omap_rfbi_write_data(const void *buf, u32 len);
++void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
++ u16 x, u16 y,
++ u16 w, u16 h);
++int omap_rfbi_enable_te(bool enable, unsigned line);
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++ unsigned hs_pulse_time, unsigned vs_pulse_time,
++ int hs_pol_inv, int vs_pol_inv, int extif_div);
++
++/* DSI */
++int dsi_vc_dcs_write(int channel, u8 *data, int len);
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
++int dsi_vc_send_null(int channel);
++
++/* Board specific data */
++struct omap_dss_display_config {
++ enum omap_display_type type;
++
++ union {
++ struct {
++ u8 data_lines;
++ } dpi;
++
++ struct {
++ u8 channel;
++ u8 data_lines;
++ } rfbi;
++
++ struct {
++ u8 datapairs;
++ } sdi;
++
++ struct {
++ u8 clk_lane;
++ u8 clk_pol;
++ u8 data1_lane;
++ u8 data1_pol;
++ u8 data2_lane;
++ u8 data2_pol;
++ unsigned long ddr_clk_hz;
++ } dsi;
++
++ struct {
++ enum omap_dss_venc_type type;
++ } venc;
++ } u;
++
++ int panel_reset_gpio;
++ int ctrl_reset_gpio;
++
++ const char *name; /* for debug */
++ const char *ctrl_name;
++ const char *panel_name;
++
++ void *panel_data;
++ void *ctrl_data;
++
++ /* platform specific enable/disable */
++ int (*panel_enable)(struct omap_display *display);
++ void (*panel_disable)(struct omap_display *display);
++ int (*ctrl_enable)(struct omap_display *display);
++ void (*ctrl_disable)(struct omap_display *display);
++ int (*set_backlight)(struct omap_display *display,
++ int level);
++};
++
++struct device;
++
++/* Board specific data */
++struct omap_dss_board_info {
++ unsigned (*get_last_off_on_transaction_id)(struct device *dev);
++ int (*dsi_power_up)(void);
++ void (*dsi_power_down)(void);
++ int num_displays;
++ struct omap_dss_display_config *displays[];
++};
++
++struct omap_ctrl {
++ struct module *owner;
++
++ const char *name;
++
++ int (*init)(struct omap_display *display);
++ void (*cleanup)(struct omap_display *display);
++ int (*enable)(struct omap_display *display);
++ void (*disable)(struct omap_display *display);
++ int (*suspend)(struct omap_display *display);
++ int (*resume)(struct omap_display *display);
++ void (*setup_update)(struct omap_display *display,
++ u16 x, u16 y, u16 w, u16 h);
++
++ int (*enable_te)(struct omap_display *display, bool enable);
++
++ u8 (*get_rotate)(struct omap_display *display);
++ int (*set_rotate)(struct omap_display *display, u8 rotate);
++
++ bool (*get_mirror)(struct omap_display *display);
++ int (*set_mirror)(struct omap_display *display, bool enable);
++
++ int (*run_test)(struct omap_display *display, int test);
++ int (*memory_read)(struct omap_display *display,
++ void *buf, size_t size,
++ u16 x, u16 y, u16 w, u16 h);
++
++ u8 pixel_size;
++
++ struct rfbi_timings timings;
++
++ void *priv;
++};
++
++struct omap_video_timings {
++ /* Unit: pixels */
++ u16 x_res;
++ /* Unit: pixels */
++ u16 y_res;
++ /* Unit: KHz */
++ u32 pixel_clock;
++ /* Unit: pixel clocks */
++ u16 hsw; /* Horizontal synchronization pulse width */
++ /* Unit: pixel clocks */
++ u16 hfp; /* Horizontal front porch */
++ /* Unit: pixel clocks */
++ u16 hbp; /* Horizontal back porch */
++ /* Unit: line clocks */
++ u16 vsw; /* Vertical synchronization pulse width */
++ /* Unit: line clocks */
++ u16 vfp; /* Vertical front porch */
++ /* Unit: line clocks */
++ u16 vbp; /* Vertical back porch */
++
++};
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++/* Hardcoded timings for tv modes. Venc only uses these to
++ * identify the mode, and does not actually use the configs
++ * itself. However, the configs should be something that
++ * a normal monitor can also show */
++const extern struct omap_video_timings omap_dss_pal_timings;
++const extern struct omap_video_timings omap_dss_ntsc_timings;
++#endif
++
++struct omap_panel {
++ struct module *owner;
++
++ const char *name;
++
++ int (*init)(struct omap_display *display);
++ void (*cleanup)(struct omap_display *display);
++ int (*remove)(struct omap_display *display);
++ int (*enable)(struct omap_display *display);
++ void (*disable)(struct omap_display *display);
++ int (*suspend)(struct omap_display *display);
++ int (*resume)(struct omap_display *display);
++ int (*run_test)(struct omap_display *display, int test);
++
++ struct omap_video_timings timings;
++
++ int acbi; /* ac-bias pin transitions per interrupt */
++ /* Unit: line clocks */
++ int acb; /* ac-bias pin frequency */
++
++ enum omap_panel_config config;
++
++ u8 recommended_bpp;
++
++ void *priv;
++};
++
++/* XXX perhaps this should be removed */
++enum omap_dss_overlay_managers {
++ OMAP_DSS_OVL_MGR_LCD,
++ OMAP_DSS_OVL_MGR_TV,
++};
++
++struct omap_overlay_manager;
++
++struct omap_overlay_info {
++ bool enabled;
++
++ u32 paddr;
++ void __iomem *vaddr;
++ u16 screen_width;
++ u16 width;
++ u16 height;
++ enum omap_color_mode color_mode;
++ u8 rotation;
++ bool mirror;
++
++ u16 pos_x;
++ u16 pos_y;
++ u16 out_width; /* if 0, out_width == width */
++ u16 out_height; /* if 0, out_height == height */
++};
++
++enum omap_overlay_caps {
++ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
++ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
++};
++
++struct omap_overlay {
++ struct kobject kobj;
++ struct list_head list;
++
++ const char *name;
++ int id;
++ struct omap_overlay_manager *manager;
++ enum omap_color_mode supported_modes;
++ struct omap_overlay_info info;
++ enum omap_overlay_caps caps;
++
++ int (*set_manager)(struct omap_overlay *ovl,
++ struct omap_overlay_manager *mgr);
++ int (*unset_manager)(struct omap_overlay *ovl);
++
++ int (*set_overlay_info)(struct omap_overlay *ovl,
++ struct omap_overlay_info *info);
++ void (*get_overlay_info)(struct omap_overlay *ovl,
++ struct omap_overlay_info *info);
++};
++
++enum omap_overlay_manager_caps {
++ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
++};
++
++struct omap_overlay_manager {
++ struct kobject kobj;
++ struct list_head list;
++
++ const char *name;
++ int id;
++ enum omap_overlay_manager_caps caps;
++ struct omap_display *display;
++ int num_overlays;
++ struct omap_overlay **overlays;
++ enum omap_display_type supported_displays;
++
++ int (*set_display)(struct omap_overlay_manager *mgr,
++ struct omap_display *display);
++ int (*unset_display)(struct omap_overlay_manager *mgr);
++
++ int (*apply)(struct omap_overlay_manager *mgr);
++
++ void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
++ void (*set_trans_key)(struct omap_overlay_manager *mgr,
++ enum omap_dss_color_key_type type,
++ u32 trans_key);
++ void (*enable_trans_key)(struct omap_overlay_manager *mgr,
++ bool enable);
++};
++
++enum omap_display_caps {
++ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
++};
++
++enum omap_dss_update_mode {
++ OMAP_DSS_UPDATE_DISABLED = 0,
++ OMAP_DSS_UPDATE_AUTO,
++ OMAP_DSS_UPDATE_MANUAL,
++};
++
++enum omap_dss_display_state {
++ OMAP_DSS_DISPLAY_DISABLED = 0,
++ OMAP_DSS_DISPLAY_ACTIVE,
++ OMAP_DSS_DISPLAY_SUSPENDED,
++};
++
++struct omap_display {
++ struct kobject kobj;
++ struct list_head list;
++
++ /*atomic_t ref_count;*/
++ int ref_count;
++ /* helper variable for driver suspend/resume */
++ int activate_after_resume;
++
++ enum omap_display_type type;
++ const char *name;
++
++ enum omap_display_caps caps;
++
++ struct omap_overlay_manager *manager;
++
++ enum omap_dss_display_state state;
++
++ struct omap_dss_display_config hw_config; /* board specific data */
++ struct omap_ctrl *ctrl; /* static common data */
++ struct omap_panel *panel; /* static common data */
++
++ int (*enable)(struct omap_display *display);
++ void (*disable)(struct omap_display *display);
++
++ int (*suspend)(struct omap_display *display);
++ int (*resume)(struct omap_display *display);
++
++ void (*get_resolution)(struct omap_display *display,
++ u16 *xres, u16 *yres);
++ int (*get_recommended_bpp)(struct omap_display *display);
++
++ int (*check_timings)(struct omap_display *display,
++ struct omap_video_timings *timings);
++ void (*set_timings)(struct omap_display *display,
++ struct omap_video_timings *timings);
++ void (*get_timings)(struct omap_display *display,
++ struct omap_video_timings *timings);
++ int (*update)(struct omap_display *display,
++ u16 x, u16 y, u16 w, u16 h);
++ int (*sync)(struct omap_display *display);
++ int (*wait_vsync)(struct omap_display *display);
++
++ int (*set_update_mode)(struct omap_display *display,
++ enum omap_dss_update_mode);
++ enum omap_dss_update_mode (*get_update_mode)
++ (struct omap_display *display);
++
++ int (*enable_te)(struct omap_display *display, bool enable);
++ int (*get_te)(struct omap_display *display);
++
++ u8 (*get_rotate)(struct omap_display *display);
++ int (*set_rotate)(struct omap_display *display, u8 rotate);
++
++ bool (*get_mirror)(struct omap_display *display);
++ int (*set_mirror)(struct omap_display *display, bool enable);
++
++ int (*run_test)(struct omap_display *display, int test);
++ int (*memory_read)(struct omap_display *display,
++ void *buf, size_t size,
++ u16 x, u16 y, u16 w, u16 h);
++
++ void (*configure_overlay)(struct omap_overlay *overlay);
++};
++
++int omap_dss_get_num_displays(void);
++struct omap_display *omap_dss_get_display(int no);
++void omap_dss_put_display(struct omap_display *display);
++
++void omap_dss_register_ctrl(struct omap_ctrl *ctrl);
++void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl);
++
++void omap_dss_register_panel(struct omap_panel *panel);
++void omap_dss_unregister_panel(struct omap_panel *panel);
++
++int omap_dss_get_num_overlay_managers(void);
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
++
++int omap_dss_get_num_overlays(void);
++struct omap_overlay *omap_dss_get_overlay(int num);
++
++typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++
++int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
++int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
++ unsigned long timeout);
++
++#endif
+diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
+deleted file mode 100644
+index b226bdf..0000000
+--- a/arch/arm/plat-omap/include/mach/omapfb.h
++++ /dev/null
+@@ -1,398 +0,0 @@
+-/*
+- * File: arch/arm/plat-omap/include/mach/omapfb.h
+- *
+- * Framebuffer driver for TI OMAP boards
+- *
+- * Copyright (C) 2004 Nokia Corporation
+- * Author: Imre Deak <imre.deak@nokia.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+- * General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License along
+- * with this program; if not, write to the Free Software Foundation, Inc.,
+- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- */
+-
+-#ifndef __OMAPFB_H
+-#define __OMAPFB_H
+-
+-#include <asm/ioctl.h>
+-#include <asm/types.h>
+-
+-/* IOCTL commands. */
+-
+-#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
+-#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
+-#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
+-#define OMAP_IO(num) _IO('O', num)
+-
+-#define OMAPFB_MIRROR OMAP_IOW(31, int)
+-#define OMAPFB_SYNC_GFX OMAP_IO(37)
+-#define OMAPFB_VSYNC OMAP_IO(38)
+-#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
+-#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
+-#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
+-#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
+-#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
+-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
+-#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
+-#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
+-#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
+-#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
+-#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
+-#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
+-#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
+-
+-#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
+-#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
+-#define OMAPFB_CAPS_PANEL_MASK 0xff000000
+-
+-#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
+-#define OMAPFB_CAPS_TEARSYNC 0x00002000
+-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
+-#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
+-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
+-#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
+-#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
+-#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
+-#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
+-
+-/* Values from DSP must map to lower 16-bits */
+-#define OMAPFB_FORMAT_MASK 0x00ff
+-#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
+-#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
+-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
+-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
+-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
+-
+-#define OMAPFB_EVENT_READY 1
+-#define OMAPFB_EVENT_DISABLED 2
+-
+-#define OMAPFB_MEMTYPE_SDRAM 0
+-#define OMAPFB_MEMTYPE_SRAM 1
+-#define OMAPFB_MEMTYPE_MAX 1
+-
+-enum omapfb_color_format {
+- OMAPFB_COLOR_RGB565 = 0,
+- OMAPFB_COLOR_YUV422,
+- OMAPFB_COLOR_YUV420,
+- OMAPFB_COLOR_CLUT_8BPP,
+- OMAPFB_COLOR_CLUT_4BPP,
+- OMAPFB_COLOR_CLUT_2BPP,
+- OMAPFB_COLOR_CLUT_1BPP,
+- OMAPFB_COLOR_RGB444,
+- OMAPFB_COLOR_YUY422,
+-};
+-
+-struct omapfb_update_window {
+- __u32 x, y;
+- __u32 width, height;
+- __u32 format;
+- __u32 out_x, out_y;
+- __u32 out_width, out_height;
+- __u32 reserved[8];
+-};
+-
+-struct omapfb_update_window_old {
+- __u32 x, y;
+- __u32 width, height;
+- __u32 format;
+-};
+-
+-enum omapfb_plane {
+- OMAPFB_PLANE_GFX = 0,
+- OMAPFB_PLANE_VID1,
+- OMAPFB_PLANE_VID2,
+-};
+-
+-enum omapfb_channel_out {
+- OMAPFB_CHANNEL_OUT_LCD = 0,
+- OMAPFB_CHANNEL_OUT_DIGIT,
+-};
+-
+-struct omapfb_plane_info {
+- __u32 pos_x;
+- __u32 pos_y;
+- __u8 enabled;
+- __u8 channel_out;
+- __u8 mirror;
+- __u8 reserved1;
+- __u32 out_width;
+- __u32 out_height;
+- __u32 reserved2[12];
+-};
+-
+-struct omapfb_mem_info {
+- __u32 size;
+- __u8 type;
+- __u8 reserved[3];
+-};
+-
+-struct omapfb_caps {
+- __u32 ctrl;
+- __u32 plane_color;
+- __u32 wnd_color;
+-};
+-
+-enum omapfb_color_key_type {
+- OMAPFB_COLOR_KEY_DISABLED = 0,
+- OMAPFB_COLOR_KEY_GFX_DST,
+- OMAPFB_COLOR_KEY_VID_SRC,
+-};
+-
+-struct omapfb_color_key {
+- __u8 channel_out;
+- __u32 background;
+- __u32 trans_key;
+- __u8 key_type;
+-};
+-
+-enum omapfb_update_mode {
+- OMAPFB_UPDATE_DISABLED = 0,
+- OMAPFB_AUTO_UPDATE,
+- OMAPFB_MANUAL_UPDATE
+-};
+-
+-#ifdef __KERNEL__
+-
+-#include <linux/completion.h>
+-#include <linux/interrupt.h>
+-#include <linux/fb.h>
+-#include <linux/mutex.h>
+-
+-#include <mach/board.h>
+-
+-#define OMAP_LCDC_INV_VSYNC 0x0001
+-#define OMAP_LCDC_INV_HSYNC 0x0002
+-#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
+-#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
+-#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
+-#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
+-
+-#define OMAP_LCDC_SIGNAL_MASK 0x003f
+-
+-#define OMAP_LCDC_PANEL_TFT 0x0100
+-
+-#define OMAPFB_PLANE_XRES_MIN 8
+-#define OMAPFB_PLANE_YRES_MIN 8
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-#define OMAPFB_PLANE_NUM 1
+-#else
+-#define OMAPFB_PLANE_NUM 3
+-#endif
+-
+-struct omapfb_device;
+-
+-struct lcd_panel {
+- const char *name;
+- int config; /* TFT/STN, signal inversion */
+- int bpp; /* Pixel format in fb mem */
+- int data_lines; /* Lines on LCD HW interface */
+-
+- int x_res, y_res;
+- int pixel_clock; /* In kHz */
+- int hsw; /* Horizontal synchronization
+- pulse width */
+- int hfp; /* Horizontal front porch */
+- int hbp; /* Horizontal back porch */
+- int vsw; /* Vertical synchronization
+- pulse width */
+- int vfp; /* Vertical front porch */
+- int vbp; /* Vertical back porch */
+- int acb; /* ac-bias pin frequency */
+- int pcd; /* pixel clock divider.
+- Obsolete use pixel_clock instead */
+-
+- int (*init) (struct lcd_panel *panel,
+- struct omapfb_device *fbdev);
+- void (*cleanup) (struct lcd_panel *panel);
+- int (*enable) (struct lcd_panel *panel);
+- void (*disable) (struct lcd_panel *panel);
+- unsigned long (*get_caps) (struct lcd_panel *panel);
+- int (*set_bklight_level)(struct lcd_panel *panel,
+- unsigned int level);
+- unsigned int (*get_bklight_level)(struct lcd_panel *panel);
+- unsigned int (*get_bklight_max) (struct lcd_panel *panel);
+- int (*run_test) (struct lcd_panel *panel, int test_num);
+-};
+-
+-struct extif_timings {
+- int cs_on_time;
+- int cs_off_time;
+- int we_on_time;
+- int we_off_time;
+- int re_on_time;
+- int re_off_time;
+- int we_cycle_time;
+- int re_cycle_time;
+- int cs_pulse_width;
+- int access_time;
+-
+- int clk_div;
+-
+- u32 tim[5]; /* set by extif->convert_timings */
+-
+- int converted;
+-};
+-
+-struct lcd_ctrl_extif {
+- int (*init) (struct omapfb_device *fbdev);
+- void (*cleanup) (void);
+- void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
+- unsigned long (*get_max_tx_rate)(void);
+- int (*convert_timings) (struct extif_timings *timings);
+- void (*set_timings) (const struct extif_timings *timings);
+- void (*set_bits_per_cycle)(int bpc);
+- void (*write_command) (const void *buf, unsigned int len);
+- void (*read_data) (void *buf, unsigned int len);
+- void (*write_data) (const void *buf, unsigned int len);
+- void (*transfer_area) (int width, int height,
+- void (callback)(void * data), void *data);
+- int (*setup_tearsync) (unsigned pin_cnt,
+- unsigned hs_pulse_time, unsigned vs_pulse_time,
+- int hs_pol_inv, int vs_pol_inv, int div);
+- int (*enable_tearsync) (int enable, unsigned line);
+-
+- unsigned long max_transmit_size;
+-};
+-
+-struct omapfb_notifier_block {
+- struct notifier_block nb;
+- void *data;
+- int plane_idx;
+-};
+-
+-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
+- unsigned long event,
+- void *fbi);
+-
+-struct omapfb_mem_region {
+- u32 paddr;
+- void __iomem *vaddr;
+- unsigned long size;
+- u8 type; /* OMAPFB_PLANE_MEM_* */
+- unsigned alloc:1; /* allocated by the driver */
+- unsigned map:1; /* kernel mapped by the driver */
+-};
+-
+-struct omapfb_mem_desc {
+- int region_cnt;
+- struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
+-};
+-
+-struct lcd_ctrl {
+- const char *name;
+- void *data;
+-
+- int (*init) (struct omapfb_device *fbdev,
+- int ext_mode,
+- struct omapfb_mem_desc *req_md);
+- void (*cleanup) (void);
+- void (*bind_client) (struct omapfb_notifier_block *nb);
+- void (*get_caps) (int plane, struct omapfb_caps *caps);
+- int (*set_update_mode)(enum omapfb_update_mode mode);
+- enum omapfb_update_mode (*get_update_mode)(void);
+- int (*setup_plane) (int plane, int channel_out,
+- unsigned long offset,
+- int screen_width,
+- int pos_x, int pos_y, int width,
+- int height, int color_mode);
+- int (*set_rotate) (int angle);
+- int (*setup_mem) (int plane, size_t size,
+- int mem_type, unsigned long *paddr);
+- int (*mmap) (struct fb_info *info,
+- struct vm_area_struct *vma);
+- int (*set_scale) (int plane,
+- int orig_width, int orig_height,
+- int out_width, int out_height);
+- int (*enable_plane) (int plane, int enable);
+- int (*update_window) (struct fb_info *fbi,
+- struct omapfb_update_window *win,
+- void (*callback)(void *),
+- void *callback_data);
+- void (*sync) (void);
+- void (*suspend) (void);
+- void (*resume) (void);
+- int (*run_test) (int test_num);
+- int (*setcolreg) (u_int regno, u16 red, u16 green,
+- u16 blue, u16 transp,
+- int update_hw_mem);
+- int (*set_color_key) (struct omapfb_color_key *ck);
+- int (*get_color_key) (struct omapfb_color_key *ck);
+-};
+-
+-enum omapfb_state {
+- OMAPFB_DISABLED = 0,
+- OMAPFB_SUSPENDED= 99,
+- OMAPFB_ACTIVE = 100
+-};
+-
+-struct omapfb_plane_struct {
+- int idx;
+- struct omapfb_plane_info info;
+- enum omapfb_color_format color_mode;
+- struct omapfb_device *fbdev;
+-};
+-
+-struct omapfb_device {
+- int state;
+- int ext_lcdc; /* Using external
+- LCD controller */
+- struct mutex rqueue_mutex;
+-
+- int palette_size;
+- u32 pseudo_palette[17];
+-
+- struct lcd_panel *panel; /* LCD panel */
+- const struct lcd_ctrl *ctrl; /* LCD controller */
+- const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
+- struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
+- interface */
+- struct device *dev;
+- struct fb_var_screeninfo new_var; /* for mode changes */
+-
+- struct omapfb_mem_desc mem_desc;
+- struct fb_info *fb_info[OMAPFB_PLANE_NUM];
+-};
+-
+-struct omapfb_platform_data {
+- struct omap_lcd_config lcd;
+- struct omapfb_mem_desc mem_desc;
+- void *ctrl_platform_data;
+-};
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-extern struct lcd_ctrl omap1_lcd_ctrl;
+-#else
+-extern struct lcd_ctrl omap2_disp_ctrl;
+-#endif
+-
+-extern void omapfb_reserve_sdram(void);
+-extern void omapfb_register_panel(struct lcd_panel *panel);
+-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
+-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
+- unsigned long event);
+-extern int omapfb_register_client(struct omapfb_notifier_block *nb,
+- omapfb_notifier_callback_t callback,
+- void *callback_data);
+-extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
+-extern int omapfb_update_window_async(struct fb_info *fbi,
+- struct omapfb_update_window *win,
+- void (*callback)(void *),
+- void *callback_data);
+-
+-/* in arch/arm/plat-omap/fb.c */
+-extern void omapfb_set_ctrl_platform_data(void *pdata);
+-
+-#endif /* __KERNEL__ */
+-
+-#endif /* __OMAPFB_H */
+diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
+new file mode 100644
+index 0000000..f176562
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/vram.h
+@@ -0,0 +1,33 @@
++/*
++ * File: arch/arm/plat-omap/include/mach/vram.h
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++#ifndef __OMAPVRAM_H
++#define __OMAPVRAM_H
++
++#include <asm/types.h>
++
++extern int omap_vram_free(unsigned long paddr, size_t size);
++extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
++extern int omap_vram_reserve(unsigned long paddr, size_t size);
++extern void omap2_set_sdram_vram(u32 size, u32 start);
++extern void omap2_set_sram_vram(u32 size, u32 start);
++
++#endif
+diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
+new file mode 100644
+index 0000000..2047862
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/vrfb.h
+@@ -0,0 +1,47 @@
++/*
++ * File: arch/arm/plat-omap/include/mach/vrfb.h
++ *
++ * VRFB
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++#ifndef __VRFB_H
++#define __VRFB_H
++
++#define OMAP_VRFB_LINE_LEN 2048
++
++struct vrfb
++{
++ u8 context;
++ void __iomem *vaddr[4];
++ unsigned long paddr[4];
++ u16 xoffset;
++ u16 yoffset;
++ u8 bytespp;
++};
++
++extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
++ u8 bytespp);
++extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
++ u16 width, u16 height,
++ u8 bytespp);
++
++#endif /* __VRFB_H */
+diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
+new file mode 100644
+index 0000000..f24a110
+--- /dev/null
++++ b/arch/arm/plat-omap/vram.c
+@@ -0,0 +1,615 @@
++/*
++ * linux/arch/arm/plat-omap/vram.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++/*#define DEBUG*/
++
++#include <linux/vmalloc.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/dma-mapping.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/bootmem.h>
++#include <linux/omapfb.h>
++
++#include <asm/setup.h>
++
++#include <mach/sram.h>
++#include <mach/vram.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define OMAP2_SRAM_START 0x40200000
++/* Maximum size, in reality this is smaller if SRAM is partially locked. */
++#define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
++
++#define REG_MAP_SIZE(_page_cnt) \
++ ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
++#define REG_MAP_PTR(_rg, _page_nr) \
++ (((_rg)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
++#define REG_MAP_MASK(_page_nr) \
++ (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
++
++#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++/* postponed regions are used to temporarily store region information at boot
++ * time when we cannot yet allocate the region list */
++#define MAX_POSTPONED_REGIONS 10
++
++static int postponed_cnt __initdata;
++static struct {
++ unsigned long paddr;
++ size_t size;
++} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
++
++struct vram_alloc {
++ struct list_head list;
++ unsigned long paddr;
++ unsigned pages;
++};
++
++struct vram_region {
++ struct list_head list;
++ struct list_head alloc_list;
++ unsigned long paddr;
++ unsigned pages;
++};
++
++static DEFINE_MUTEX(region_mutex);
++static LIST_HEAD(region_list);
++
++static inline int region_mem_type(unsigned long paddr)
++{
++ if (paddr >= OMAP2_SRAM_START &&
++ paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
++ return OMAPFB_MEMTYPE_SRAM;
++ else
++ return OMAPFB_MEMTYPE_SDRAM;
++}
++
++static struct vram_region *omap_vram_create_region(unsigned long paddr,
++ unsigned pages)
++{
++ struct vram_region *rm;
++
++ rm = kzalloc(sizeof(*rm), GFP_KERNEL);
++
++ if (rm) {
++ INIT_LIST_HEAD(&rm->alloc_list);
++ rm->paddr = paddr;
++ rm->pages = pages;
++ }
++
++ return rm;
++}
++
++#if 0
++static void omap_vram_free_region(struct vram_region *vr)
++{
++ list_del(&vr->list);
++ kfree(vr);
++}
++#endif
++
++static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
++ unsigned long paddr, unsigned pages)
++{
++ struct vram_alloc *va;
++ struct vram_alloc *new;
++
++ new = kzalloc(sizeof(*va), GFP_KERNEL);
++
++ if (!new)
++ return NULL;
++
++ new->paddr = paddr;
++ new->pages = pages;
++
++ list_for_each_entry(va, &vr->alloc_list, list) {
++ if (va->paddr > new->paddr)
++ break;
++ }
++
++ list_add_tail(&new->list, &va->list);
++
++ return new;
++}
++
++static void omap_vram_free_allocation(struct vram_alloc *va)
++{
++ list_del(&va->list);
++ kfree(va);
++}
++
++static __init int omap_vram_add_region_postponed(unsigned long paddr,
++ size_t size)
++{
++ if (postponed_cnt == MAX_POSTPONED_REGIONS)
++ return -ENOMEM;
++
++ postponed_regions[postponed_cnt].paddr = paddr;
++ postponed_regions[postponed_cnt].size = size;
++
++ ++postponed_cnt;
++
++ return 0;
++}
++
++/* add/remove_region can be exported if there's need to add/remove regions
++ * runtime */
++static int omap_vram_add_region(unsigned long paddr, size_t size)
++{
++ struct vram_region *rm;
++ unsigned pages;
++
++ DBG("adding region paddr %08lx size %d\n",
++ paddr, size);
++
++ size &= PAGE_MASK;
++ pages = size >> PAGE_SHIFT;
++
++ rm = omap_vram_create_region(paddr, pages);
++ if (rm == NULL)
++ return -ENOMEM;
++
++ list_add(&rm->list, &region_list);
++
++ return 0;
++}
++
++int omap_vram_free(unsigned long paddr, size_t size)
++{
++ struct vram_region *rm;
++ struct vram_alloc *alloc;
++ unsigned start, end;
++
++ DBG("free mem paddr %08lx size %d\n", paddr, size);
++
++ size = PAGE_ALIGN(size);
++
++ mutex_lock(&region_mutex);
++
++ list_for_each_entry(rm, &region_list, list) {
++ list_for_each_entry(alloc, &rm->alloc_list, list) {
++ start = alloc->paddr;
++ end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
++
++ if (start >= paddr && end < paddr + size)
++ goto found;
++ }
++ }
++
++ mutex_unlock(&region_mutex);
++ return -EINVAL;
++
++found:
++ omap_vram_free_allocation(alloc);
++
++ mutex_unlock(&region_mutex);
++ return 0;
++}
++EXPORT_SYMBOL(omap_vram_free);
++
++static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
++{
++ struct vram_region *rm;
++ struct vram_alloc *alloc;
++ size_t size;
++
++ size = pages << PAGE_SHIFT;
++
++ list_for_each_entry(rm, &region_list, list) {
++ unsigned long start, end;
++
++ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++ if (region_mem_type(rm->paddr) != region_mem_type(paddr))
++ continue;
++
++ start = rm->paddr;
++ end = start + (rm->pages << PAGE_SHIFT) - 1;
++ if (start > paddr || end < paddr + size - 1)
++ continue;
++
++ DBG("block ok, checking allocs\n");
++
++ list_for_each_entry(alloc, &rm->alloc_list, list) {
++ end = alloc->paddr - 1;
++
++ if (start <= paddr && end >= paddr + size - 1)
++ goto found;
++
++ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++ }
++
++ end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
++
++ if (!(start <= paddr && end >= paddr + size - 1))
++ continue;
++found:
++ DBG("FOUND area start %lx, end %lx\n", start, end);
++
++ if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
++ return -ENOMEM;
++
++ return 0;
++ }
++
++ return -ENOMEM;
++}
++
++int omap_vram_reserve(unsigned long paddr, size_t size)
++{
++ unsigned pages;
++ int r;
++
++ DBG("reserve mem paddr %08lx size %d\n", paddr, size);
++
++ size = PAGE_ALIGN(size);
++ pages = size >> PAGE_SHIFT;
++
++ mutex_lock(&region_mutex);
++
++ r = _omap_vram_reserve(paddr, pages);
++
++ mutex_unlock(&region_mutex);
++
++ return r;
++}
++EXPORT_SYMBOL(omap_vram_reserve);
++
++static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
++{
++ struct vram_region *rm;
++ struct vram_alloc *alloc;
++
++ list_for_each_entry(rm, &region_list, list) {
++ unsigned long start, end;
++
++ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++ if (region_mem_type(rm->paddr) != mtype)
++ continue;
++
++ start = rm->paddr;
++
++ list_for_each_entry(alloc, &rm->alloc_list, list) {
++ end = alloc->paddr;
++
++ if (end - start >= pages << PAGE_SHIFT)
++ goto found;
++
++ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++ }
++
++ end = rm->paddr + (rm->pages << PAGE_SHIFT);
++found:
++ if (end - start < pages << PAGE_SHIFT)
++ continue;
++
++ DBG("FOUND %lx, end %lx\n", start, end);
++
++ alloc = omap_vram_create_allocation(rm, start, pages);
++ if (alloc == NULL)
++ return -ENOMEM;
++
++ *paddr = start;
++
++ return 0;
++ }
++
++ return -ENOMEM;
++}
++
++int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
++{
++ unsigned pages;
++ int r;
++
++ BUG_ON(mtype > OMAPFB_MEMTYPE_MAX || !size);
++
++ DBG("alloc mem type %d size %d\n", mtype, size);
++
++ size = PAGE_ALIGN(size);
++ pages = size >> PAGE_SHIFT;
++
++ mutex_lock(&region_mutex);
++
++ r = _omap_vram_alloc(mtype, pages, paddr);
++
++ mutex_unlock(&region_mutex);
++
++ return r;
++}
++EXPORT_SYMBOL(omap_vram_alloc);
++
++#ifdef CONFIG_PROC_FS
++static void *r_next(struct seq_file *m, void *v, loff_t *pos)
++{
++ struct list_head *l = v;
++
++ (*pos)++;
++
++ if (list_is_last(l, &region_list))
++ return NULL;
++
++ return l->next;
++}
++
++static void *r_start(struct seq_file *m, loff_t *pos)
++{
++ loff_t p = *pos;
++ struct list_head *l = &region_list;
++
++ mutex_lock(&region_mutex);
++
++ do {
++ l = l->next;
++ if (l == &region_list)
++ return NULL;
++ } while (p--);
++
++ return l;
++}
++
++static void r_stop(struct seq_file *m, void *v)
++{
++ mutex_unlock(&region_mutex);
++}
++
++static int r_show(struct seq_file *m, void *v)
++{
++ struct vram_region *vr;
++ struct vram_alloc *va;
++ unsigned size;
++
++ vr = list_entry(v, struct vram_region, list);
++
++ size = vr->pages << PAGE_SHIFT;
++
++ seq_printf(m, "%08lx-%08lx (%d bytes)\n",
++ vr->paddr, vr->paddr + size - 1,
++ size);
++
++ list_for_each_entry(va, &vr->alloc_list, list) {
++ size = va->pages << PAGE_SHIFT;
++ seq_printf(m, " %08lx-%08lx (%d bytes)\n",
++ va->paddr, va->paddr + size - 1,
++ size);
++ }
++
++
++
++ return 0;
++}
++
++static const struct seq_operations resource_op = {
++ .start = r_start,
++ .next = r_next,
++ .stop = r_stop,
++ .show = r_show,
++};
++
++static int vram_open(struct inode *inode, struct file *file)
++{
++ return seq_open(file, &resource_op);
++}
++
++static const struct file_operations proc_vram_operations = {
++ .open = vram_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = seq_release,
++};
++
++static int __init omap_vram_create_proc(void)
++{
++ proc_create("omap-vram", 0, NULL, &proc_vram_operations);
++
++ return 0;
++}
++#endif
++
++static __init int omap_vram_init(void)
++{
++ int i, r;
++
++ for (i = 0; i < postponed_cnt; i++)
++ omap_vram_add_region(postponed_regions[i].paddr,
++ postponed_regions[i].size);
++
++#ifdef CONFIG_PROC_FS
++ r = omap_vram_create_proc();
++ if (r)
++ return -ENOMEM;
++#endif
++
++ return 0;
++}
++
++arch_initcall(omap_vram_init);
++
++/* boottime vram alloc stuff */
++
++/* set from board file */
++static u32 omapfb_sram_vram_start __initdata;
++static u32 omapfb_sram_vram_size __initdata;
++
++/* set from board file */
++static u32 omapfb_sdram_vram_start __initdata;
++static u32 omapfb_sdram_vram_size __initdata;
++
++/* set from kernel cmdline */
++static u32 omapfb_def_sdram_vram_size __initdata;
++static u32 omapfb_def_sdram_vram_start __initdata;
++
++static void __init omapfb_early_vram(char **p)
++{
++ omapfb_def_sdram_vram_size = memparse(*p, p);
++ if (**p == ',')
++ omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
++
++ printk("omapfb_early_vram, %d, 0x%x\n",
++ omapfb_def_sdram_vram_size,
++ omapfb_def_sdram_vram_start);
++}
++__early_param("vram=", omapfb_early_vram);
++
++/*
++ * Called from map_io. We need to call to this early enough so that we
++ * can reserve the fixed SDRAM regions before VM could get hold of them.
++ */
++void __init omapfb_reserve_sdram(void)
++{
++ struct bootmem_data *bdata;
++ unsigned long sdram_start, sdram_size;
++ u32 paddr;
++ u32 size = 0;
++
++ /* cmdline arg overrides the board file definition */
++ if (omapfb_def_sdram_vram_size) {
++ size = omapfb_def_sdram_vram_size;
++ paddr = omapfb_def_sdram_vram_start;
++ }
++
++ if (!size) {
++ size = omapfb_sdram_vram_size;
++ paddr = omapfb_sdram_vram_start;
++ }
++
++#ifdef CONFIG_OMAP2_DSS_VRAM_SIZE
++ if (!size) {
++ size = CONFIG_OMAP2_DSS_VRAM_SIZE * 1024 * 1024;
++ paddr = 0;
++ }
++#endif
++
++ if (!size)
++ return;
++
++ size = PAGE_ALIGN(size);
++
++ bdata = NODE_DATA(0)->bdata;
++ sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
++ sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
++
++ if (paddr) {
++ if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
++ paddr + size > sdram_start + sdram_size) {
++ printk(KERN_ERR "Illegal SDRAM region for VRAM\n");
++ return;
++ }
++
++ reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
++ } else {
++ if (size > sdram_size) {
++ printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
++ return;
++ }
++
++ paddr = virt_to_phys(alloc_bootmem_pages(size));
++ BUG_ON(paddr & ~PAGE_MASK);
++ }
++
++ omap_vram_add_region_postponed(paddr, size);
++
++ pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
++}
++
++/*
++ * Called at sram init time, before anything is pushed to the SRAM stack.
++ * Because of the stack scheme, we will allocate everything from the
++ * start of the lowest address region to the end of SRAM. This will also
++ * include padding for page alignment and possible holes between regions.
++ *
++ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
++ * this point, since the driver built as a module would have problem with
++ * freeing / reallocating the regions.
++ */
++unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
++ unsigned long sram_vstart,
++ unsigned long sram_size,
++ unsigned long pstart_avail,
++ unsigned long size_avail)
++{
++ unsigned long pend_avail;
++ unsigned long reserved;
++ u32 paddr;
++ u32 size;
++
++ paddr = omapfb_sram_vram_start;
++ size = omapfb_sram_vram_size;
++
++ if (!size)
++ return 0;
++
++ reserved = 0;
++ pend_avail = pstart_avail + size_avail;
++
++ if (!paddr) {
++ /* Dynamic allocation */
++ if ((size_avail & PAGE_MASK) < size) {
++ printk(KERN_ERR "Not enough SRAM for VRAM\n");
++ return 0;
++ }
++ size_avail = (size_avail - size) & PAGE_MASK;
++ paddr = pstart_avail + size_avail;
++ }
++
++ if (paddr < sram_pstart ||
++ paddr + size > sram_pstart + sram_size) {
++ printk(KERN_ERR "Illegal SRAM region for VRAM\n");
++ return 0;
++ }
++
++ /* Reserve everything above the start of the region. */
++ if (pend_avail - paddr > reserved)
++ reserved = pend_avail - paddr;
++ size_avail = pend_avail - reserved - pstart_avail;
++
++ omap_vram_add_region_postponed(paddr, size);
++
++ if (reserved)
++ pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
++
++ return reserved;
++}
++
++void __init omap2_set_sdram_vram(u32 size, u32 start)
++{
++ omapfb_sdram_vram_start = start;
++ omapfb_sdram_vram_size = size;
++}
++
++void __init omap2_set_sram_vram(u32 size, u32 start)
++{
++ omapfb_sram_vram_start = start;
++ omapfb_sram_vram_size = size;
++}
++
++#endif
++
+diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
+new file mode 100644
+index 0000000..7e0f8fc
+--- /dev/null
++++ b/arch/arm/plat-omap/vrfb.c
+@@ -0,0 +1,159 @@
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <asm/io.h>
++
++#include <mach/io.h>
++#include <mach/vrfb.h>
++
++/*#define DEBUG*/
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "VRFB: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define SMS_ROT_VIRT_BASE(context, rot) \
++ (((context >= 4) ? 0xD0000000 : 0x70000000) \
++ | 0x4000000 * (context) \
++ | 0x1000000 * (rot))
++
++#define OMAP_VRFB_SIZE (2048 * 2048 * 4)
++
++#define VRFB_PAGE_WIDTH_EXP 5 /* Assuming SDRAM pagesize= 1024 */
++#define VRFB_PAGE_HEIGHT_EXP 5 /* 1024 = 2^5 * 2^5 */
++#define VRFB_PAGE_WIDTH (1 << VRFB_PAGE_WIDTH_EXP)
++#define VRFB_PAGE_HEIGHT (1 << VRFB_PAGE_HEIGHT_EXP)
++#define SMS_IMAGEHEIGHT_OFFSET 16
++#define SMS_IMAGEWIDTH_OFFSET 0
++#define SMS_PH_OFFSET 8
++#define SMS_PW_OFFSET 4
++#define SMS_PS_OFFSET 0
++
++#define OMAP_SMS_BASE 0x6C000000
++#define SMS_ROT_CONTROL(context) (OMAP_SMS_BASE + 0x180 + 0x10 * context)
++#define SMS_ROT_SIZE(context) (OMAP_SMS_BASE + 0x184 + 0x10 * context)
++#define SMS_ROT_PHYSICAL_BA(context) (OMAP_SMS_BASE + 0x188 + 0x10 * context)
++
++#define VRFB_NUM_CTXS 12
++/* bitmap of reserved contexts */
++static unsigned ctx_map;
++
++void omap_vrfb_adjust_size(u16 *width, u16 *height,
++ u8 bytespp)
++{
++ *width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
++ *height = ALIGN(*height, VRFB_PAGE_HEIGHT);
++}
++EXPORT_SYMBOL(omap_vrfb_adjust_size);
++
++void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
++ u16 width, u16 height,
++ u8 bytespp)
++{
++ unsigned pixel_size_exp;
++ u16 vrfb_width;
++ u16 vrfb_height;
++ u8 ctx = vrfb->context;
++
++ DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
++ width, height, bytespp);
++
++ if (bytespp == 4)
++ pixel_size_exp = 2;
++ else if (bytespp == 2)
++ pixel_size_exp = 1;
++ else
++ BUG();
++
++ vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
++ vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
++
++ DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
++
++ omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
++ omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
++ (vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
++ SMS_ROT_SIZE(ctx));
++
++ omap_writel(pixel_size_exp << SMS_PS_OFFSET |
++ VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET |
++ VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
++ SMS_ROT_CONTROL(ctx));
++
++ DBG("vrfb offset pixels %d, %d\n",
++ vrfb_width - width, vrfb_height - height);
++
++ vrfb->xoffset = vrfb_width - width;
++ vrfb->yoffset = vrfb_height - height;
++ vrfb->bytespp = bytespp;
++}
++EXPORT_SYMBOL(omap_vrfb_setup);
++
++void omap_vrfb_release_ctx(struct vrfb *vrfb)
++{
++ int rot;
++
++ if (vrfb->context == 0xff)
++ return;
++
++ DBG("release ctx %d\n", vrfb->context);
++
++ ctx_map &= ~(1 << vrfb->context);
++
++ for (rot = 0; rot < 4; ++rot) {
++ if(vrfb->paddr[rot]) {
++ release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
++ vrfb->paddr[rot] = 0;
++ }
++ }
++
++ vrfb->context = 0xff;
++}
++EXPORT_SYMBOL(omap_vrfb_release_ctx);
++
++int omap_vrfb_request_ctx(struct vrfb *vrfb)
++{
++ int rot;
++ u32 paddr;
++ u8 ctx;
++
++ DBG("request ctx\n");
++
++ for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
++ if ((ctx_map & (1 << ctx)) == 0)
++ break;
++
++ if (ctx == VRFB_NUM_CTXS) {
++ printk(KERN_ERR "vrfb: no free contexts\n");
++ return -EBUSY;
++ }
++
++ DBG("found free ctx %d\n", ctx);
++
++ ctx_map |= 1 << ctx;
++
++ memset(vrfb, 0, sizeof(*vrfb));
++
++ vrfb->context = ctx;
++
++ for (rot = 0; rot < 4; ++rot) {
++ paddr = SMS_ROT_VIRT_BASE(ctx, rot);
++ if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
++ printk(KERN_ERR "vrfb: failed to reserve VRFB "
++ "area for ctx %d, rotation %d\n",
++ ctx, rot * 90);
++ omap_vrfb_release_ctx(vrfb);
++ return -ENOMEM;
++ }
++
++ vrfb->paddr[rot] = paddr;
++
++ DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(omap_vrfb_request_ctx);
++
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index fb19803..8b3752b 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -2132,6 +2132,7 @@ config FB_MX3
+ an LCD display with your i.MX31 system, say Y here.
+
+ source "drivers/video/omap/Kconfig"
++source "drivers/video/omap2/Kconfig"
+
+ source "drivers/video/backlight/Kconfig"
+ source "drivers/video/display/Kconfig"
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 2a998ca..1db8dd4 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_SM501) += sm501fb.o
+ obj-$(CONFIG_FB_XILINX) += xilinxfb.o
+ obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
+ obj-$(CONFIG_FB_OMAP) += omap/
++obj-$(CONFIG_OMAP2_DSS) += omap2/
+ obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
+ obj-$(CONFIG_FB_CARMINE) += carminefb.o
+ obj-$(CONFIG_FB_MB862XX) += mb862xx/
+diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
+index c355b59..a1c10de 100644
+--- a/drivers/video/omap/Kconfig
++++ b/drivers/video/omap/Kconfig
+@@ -1,6 +1,7 @@
+ config FB_OMAP
+ tristate "OMAP frame buffer support (EXPERIMENTAL)"
+- depends on FB && ARCH_OMAP
++ depends on FB && ARCH_OMAP && (OMAP2_DSS = "n")
++
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+@@ -72,7 +73,7 @@ config FB_OMAP_LCD_MIPID
+
+ config FB_OMAP_BOOTLOADER_INIT
+ bool "Check bootloader initialization"
+- depends on FB_OMAP
++ depends on FB_OMAP || FB_OMAP2
+ help
+ Say Y here if you want to enable checking if the bootloader has
+ already initialized the display controller. In this case the
+diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
+index f60a233..8121c09 100644
+--- a/drivers/video/omap/blizzard.c
++++ b/drivers/video/omap/blizzard.c
+@@ -25,9 +25,9 @@
+ #include <linux/fb.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ #include <mach/blizzard.h>
+
+ #include "dispc.h"
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index c140c21..1915af5 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -24,9 +24,9 @@
+ #include <linux/vmalloc.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+
+ #include <mach/sram.h>
+-#include <mach/omapfb.h>
+ #include <mach/board.h>
+
+ #include "dispc.h"
+diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
+index f24df0b..9b4c506 100644
+--- a/drivers/video/omap/hwa742.c
++++ b/drivers/video/omap/hwa742.c
+@@ -25,9 +25,9 @@
+ #include <linux/fb.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ #include <mach/hwa742.h>
+
+ #define HWA742_REV_CODE_REG 0x0
+diff --git a/drivers/video/omap/lcd_2430sdp.c b/drivers/video/omap/lcd_2430sdp.c
+index a22b452..1252cc3 100644
+--- a/drivers/video/omap/lcd_2430sdp.c
++++ b/drivers/video/omap/lcd_2430sdp.c
+@@ -26,9 +26,9 @@
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+
+ #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
+diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
+index 3fd5342..4d54725 100644
+--- a/drivers/video/omap/lcd_ams_delta.c
++++ b/drivers/video/omap/lcd_ams_delta.c
+@@ -24,13 +24,13 @@
+
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+
+ #include <asm/delay.h>
+ #include <asm/io.h>
+
+ #include <mach/board-ams-delta.h>
+ #include <mach/hardware.h>
+-#include <mach/omapfb.h>
+
+ #define AMS_DELTA_DEFAULT_CONTRAST 112
+
+diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c
+index beae5d9..e3b2224 100644
+--- a/drivers/video/omap/lcd_apollon.c
++++ b/drivers/video/omap/lcd_apollon.c
+@@ -23,10 +23,10 @@
+
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+
+ /* #define USE_35INCH_LCD 1 */
+
+diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
+index 2486237..f7264ea 100644
+--- a/drivers/video/omap/lcd_h3.c
++++ b/drivers/video/omap/lcd_h3.c
+@@ -22,9 +22,9 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c/tps65010.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+
+ #define MODULE_NAME "omapfb-lcd_h3"
+
+diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
+index 6ff5643..d72df0c 100644
+--- a/drivers/video/omap/lcd_h4.c
++++ b/drivers/video/omap/lcd_h4.c
+@@ -21,8 +21,7 @@
+
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+-
+-#include <mach/omapfb.h>
++#include <linux/omapfb.h>
+
+ static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
+ {
+diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
+index 6953ed4..f6e05d7 100644
+--- a/drivers/video/omap/lcd_inn1510.c
++++ b/drivers/video/omap/lcd_inn1510.c
+@@ -22,9 +22,9 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+
+ #include <mach/fpga.h>
+-#include <mach/omapfb.h>
+
+ static int innovator1510_panel_init(struct lcd_panel *panel,
+ struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
+index 4c4f7ee..c599e41 100644
+--- a/drivers/video/omap/lcd_inn1610.c
++++ b/drivers/video/omap/lcd_inn1610.c
+@@ -21,9 +21,9 @@
+
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+
+ #define MODULE_NAME "omapfb-lcd_h3"
+
+diff --git a/drivers/video/omap/lcd_ldp.c b/drivers/video/omap/lcd_ldp.c
+index 8925230..1c25186 100644
+--- a/drivers/video/omap/lcd_ldp.c
++++ b/drivers/video/omap/lcd_ldp.c
+@@ -25,10 +25,10 @@
+ #include <linux/platform_device.h>
+ #include <linux/delay.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+
+ #define LCD_PANEL_BACKLIGHT_GPIO (15 + OMAP_MAX_GPIO_LINES)
+diff --git a/drivers/video/omap/lcd_mipid.c b/drivers/video/omap/lcd_mipid.c
+index 1895997..4b28005 100644
+--- a/drivers/video/omap/lcd_mipid.c
++++ b/drivers/video/omap/lcd_mipid.c
+@@ -22,8 +22,8 @@
+ #include <linux/delay.h>
+ #include <linux/workqueue.h>
+ #include <linux/spi/spi.h>
++#include <linux/omapfb.h>
+
+-#include <mach/omapfb.h>
+ #include <mach/lcd_mipid.h>
+
+ #include "../../cbus/tahvo.h"
+diff --git a/drivers/video/omap/lcd_omap2evm.c b/drivers/video/omap/lcd_omap2evm.c
+index 2fc46c2..1908a2b 100644
+--- a/drivers/video/omap/lcd_omap2evm.c
++++ b/drivers/video/omap/lcd_omap2evm.c
+@@ -25,9 +25,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+
+ #define LCD_PANEL_ENABLE_GPIO 154
+diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
+index eae43e4..6be117e 100644
+--- a/drivers/video/omap/lcd_omap3beagle.c
++++ b/drivers/video/omap/lcd_omap3beagle.c
+@@ -24,9 +24,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+
+ #define LCD_PANEL_ENABLE_GPIO 170
+diff --git a/drivers/video/omap/lcd_omap3evm.c b/drivers/video/omap/lcd_omap3evm.c
+index 1c3d814..10ba48c 100644
+--- a/drivers/video/omap/lcd_omap3evm.c
++++ b/drivers/video/omap/lcd_omap3evm.c
+@@ -24,9 +24,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+
+ #define LCD_PANEL_ENABLE_GPIO 153
+diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
+index 379c96d..d6b193e 100644
+--- a/drivers/video/omap/lcd_osk.c
++++ b/drivers/video/omap/lcd_osk.c
+@@ -22,10 +22,10 @@
+
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+
+ static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
+ {
+diff --git a/drivers/video/omap/lcd_overo.c b/drivers/video/omap/lcd_overo.c
+index 2bc5c92..40c2026 100644
+--- a/drivers/video/omap/lcd_overo.c
++++ b/drivers/video/omap/lcd_overo.c
+@@ -22,10 +22,10 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c/twl4030.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <asm/mach-types.h>
+
+ #define LCD_ENABLE 144
+diff --git a/drivers/video/omap/lcd_p2.c b/drivers/video/omap/lcd_p2.c
+index dd40fd7..bc5abef 100644
+--- a/drivers/video/omap/lcd_p2.c
++++ b/drivers/video/omap/lcd_p2.c
+@@ -24,10 +24,10 @@
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
++#include <linux/omapfb.h>
+
+ #include <mach/mux.h>
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+
+ /*
+ * File: epson-md-tft.h
+diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
+index 2183173..dcb456c 100644
+--- a/drivers/video/omap/lcd_palmte.c
++++ b/drivers/video/omap/lcd_palmte.c
+@@ -22,9 +22,9 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+
+ #include <mach/fpga.h>
+-#include <mach/omapfb.h>
+
+ static int palmte_panel_init(struct lcd_panel *panel,
+ struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
+index 57b0f6c..e8adab8 100644
+--- a/drivers/video/omap/lcd_palmtt.c
++++ b/drivers/video/omap/lcd_palmtt.c
+@@ -28,9 +28,9 @@ GPIO13 - screen blanking
+ #include <linux/platform_device.h>
+ #include <linux/module.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
+
+ static int palmtt_panel_init(struct lcd_panel *panel,
+ struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
+index d33d78b..d5b3f82 100644
+--- a/drivers/video/omap/lcd_palmz71.c
++++ b/drivers/video/omap/lcd_palmz71.c
+@@ -23,8 +23,7 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+-
+-#include <mach/omapfb.h>
++#include <linux/omapfb.h>
+
+ static int palmz71_panel_init(struct lcd_panel *panel,
+ struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
+index ab39492..633e33c 100644
+--- a/drivers/video/omap/lcdc.c
++++ b/drivers/video/omap/lcdc.c
+@@ -28,9 +28,9 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/vmalloc.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+
+ #include <asm/mach-types.h>
+
+diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
+index 3bb4247..c6306af 100644
+--- a/drivers/video/omap/omapfb_main.c
++++ b/drivers/video/omap/omapfb_main.c
+@@ -27,9 +27,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/mm.h>
+ #include <linux/uaccess.h>
++#include <linux/omapfb.h>
+
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+
+ #include "lcdc.h"
+ #include "dispc.h"
+diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
+index 29fa368..118cfa9 100644
+--- a/drivers/video/omap/rfbi.c
++++ b/drivers/video/omap/rfbi.c
+@@ -26,8 +26,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
+-
+-#include <mach/omapfb.h>
++#include <linux/omapfb.h>
+
+ #include "dispc.h"
+
+diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
+index cc697cc..ff9dd71 100644
+--- a/drivers/video/omap/sossi.c
++++ b/drivers/video/omap/sossi.c
+@@ -23,9 +23,9 @@
+ #include <linux/clk.h>
+ #include <linux/irq.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+
+ #include "lcdc.h"
+
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+new file mode 100644
+index 0000000..89bf210
+--- /dev/null
++++ b/drivers/video/omap2/Kconfig
+@@ -0,0 +1,3 @@
++source "drivers/video/omap2/dss/Kconfig"
++source "drivers/video/omap2/displays/Kconfig"
++source "drivers/video/omap2/omapfb/Kconfig"
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+new file mode 100644
+index 0000000..72134db
+--- /dev/null
++++ b/drivers/video/omap2/Makefile
+@@ -0,0 +1,4 @@
++# OMAP2/3 Display Subsystem
++obj-y += dss/
++obj-y += displays/
++obj-y += omapfb/
+diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
+new file mode 100644
+index 0000000..35e4bee
+--- /dev/null
++++ b/drivers/video/omap2/displays/Kconfig
+@@ -0,0 +1,32 @@
++menu "OMAP2/3 Display Device Drivers"
++ depends on OMAP2_DSS
++
++config PANEL_GENERIC
++ tristate "Generic Panel"
++ help
++ Generic panel driver.
++ Used for DVI output for Beagle and OMAP3 SDP.
++
++config PANEL_SAMSUNG_LTE430WQ_F0C
++ tristate "Samsung LTE430WQ-F0C LCD Panel"
++ depends on OMAP2_DSS
++ help
++ LCD Panel used on Overo Palo43
++
++config PANEL_SHARP_LS037V7DW01
++ tristate "Sharp LS037V7DW01 LCD Panel"
++ depends on OMAP2_DSS
++ help
++ LCD Panel used in TI's SDP3430 and EVM boards
++
++config PANEL_N800
++ tristate "Panel N8x0"
++ help
++ N8x0 LCD (hack)
++
++config CTRL_BLIZZARD
++ tristate "Blizzard Controller"
++ help
++ Blizzard Controller (hack)
++
++endmenu
+diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
+new file mode 100644
+index 0000000..1b74b7e
+--- /dev/null
++++ b/drivers/video/omap2/displays/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
++obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
++obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
++
++obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
++obj-$(CONFIG_PANEL_N800) += panel-n800.o
+diff --git a/drivers/video/omap2/displays/ctrl-blizzard.c b/drivers/video/omap2/displays/ctrl-blizzard.c
+new file mode 100644
+index 0000000..6698e4d
+--- /dev/null
++++ b/drivers/video/omap2/displays/ctrl-blizzard.c
+@@ -0,0 +1,279 @@
++
++//#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "Blizzard: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define BLIZZARD_REV_CODE 0x00
++#define BLIZZARD_CONFIG 0x02
++#define BLIZZARD_PLL_DIV 0x04
++#define BLIZZARD_PLL_LOCK_RANGE 0x06
++#define BLIZZARD_PLL_CLOCK_SYNTH_0 0x08
++#define BLIZZARD_PLL_CLOCK_SYNTH_1 0x0a
++#define BLIZZARD_PLL_MODE 0x0c
++#define BLIZZARD_CLK_SRC 0x0e
++#define BLIZZARD_MEM_BANK0_ACTIVATE 0x10
++#define BLIZZARD_MEM_BANK0_STATUS 0x14
++#define BLIZZARD_PANEL_CONFIGURATION 0x28
++#define BLIZZARD_HDISP 0x2a
++#define BLIZZARD_HNDP 0x2c
++#define BLIZZARD_VDISP0 0x2e
++#define BLIZZARD_VDISP1 0x30
++#define BLIZZARD_VNDP 0x32
++#define BLIZZARD_HSW 0x34
++#define BLIZZARD_VSW 0x38
++#define BLIZZARD_DISPLAY_MODE 0x68
++#define BLIZZARD_INPUT_WIN_X_START_0 0x6c
++#define BLIZZARD_DATA_SOURCE_SELECT 0x8e
++#define BLIZZARD_DISP_MEM_DATA_PORT 0x90
++#define BLIZZARD_DISP_MEM_READ_ADDR0 0x92
++#define BLIZZARD_POWER_SAVE 0xE6
++#define BLIZZARD_NDISP_CTRL_STATUS 0xE8
++
++/* Data source select */
++/* For S1D13745 */
++#define BLIZZARD_SRC_WRITE_LCD_BACKGROUND 0x00
++#define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE 0x01
++#define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE 0x04
++#define BLIZZARD_SRC_DISABLE_OVERLAY 0x05
++/* For S1D13744 */
++#define BLIZZARD_SRC_WRITE_LCD 0x00
++#define BLIZZARD_SRC_BLT_LCD 0x06
++
++#define BLIZZARD_COLOR_RGB565 0x01
++#define BLIZZARD_COLOR_YUV420 0x09
++
++#define BLIZZARD_VERSION_S1D13745 0x01 /* Hailstorm */
++#define BLIZZARD_VERSION_S1D13744 0x02 /* Blizzard */
++
++#define BLIZZARD_AUTO_UPDATE_TIME (HZ / 20)
++
++
++
++static struct {
++ int version;
++} blizzard;
++
++
++static inline void blizzard_cmd(u8 cmd)
++{
++ omap_rfbi_write_command(&cmd, 1);
++}
++
++static inline void blizzard_write(u8 cmd, const u8 *buf, int len)
++{
++ omap_rfbi_write_command(&cmd, 1);
++ omap_rfbi_write_data(buf, len);
++}
++
++static inline void blizzard_read(u8 cmd, u8 *buf, int len)
++{
++ omap_rfbi_write_command(&cmd, 1);
++ omap_rfbi_read_data(buf, len);
++}
++
++static u8 blizzard_read_reg(u8 cmd)
++{
++ u8 data;
++ blizzard_read(cmd, &data, 1);
++ return data;
++}
++
++static int blizzard_ctrl_init(struct omap_display *display)
++{
++ DBG("blizzard_ctrl_init\n");
++
++ return 0;
++}
++
++
++static int blizzard_ctrl_enable(struct omap_display *display)
++{
++ int r = 0;
++ u8 rev, conf;
++
++ DBG("blizzard_ctrl_enable\n");
++
++ if (display->hw_config.ctrl_enable) {
++ r = display->hw_config.ctrl_enable(display);
++ if (r)
++ return r;
++ }
++
++ msleep(100);
++
++ rev = blizzard_read_reg(BLIZZARD_CLK_SRC);
++ printk("CLK_SRC %x\n", rev);
++
++ rev = blizzard_read_reg(BLIZZARD_PLL_DIV);
++ printk("PLLDIV %x\n", rev);
++
++ rev = blizzard_read_reg(BLIZZARD_REV_CODE);
++ conf = blizzard_read_reg(BLIZZARD_CONFIG);
++
++ printk("rev %x, conf %x\n", rev, conf);
++
++ switch (rev & 0xfc) {
++ case 0x9c:
++ blizzard.version = BLIZZARD_VERSION_S1D13744;
++ pr_info("omapfb: s1d13744 LCD controller rev %d "
++ "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
++ break;
++ case 0xa4:
++ blizzard.version = BLIZZARD_VERSION_S1D13745;
++ pr_info("omapfb: s1d13745 LCD controller rev %d "
++ "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
++ break;
++ default:
++ printk("invalid s1d1374x revision %02x\n",
++ rev);
++ r = -ENODEV;
++ }
++
++ return r;
++}
++
++static void blizzard_ctrl_disable(struct omap_display *display)
++{
++ DBG("blizzard_ctrl_disable\n");
++
++ if (display->hw_config.ctrl_disable)
++ display->hw_config.ctrl_disable(display);
++}
++
++int rfbi_configure(int rfbi_module, int bpp, int lines);
++
++static void blizzard_ctrl_setup_update(struct omap_display *display,
++ u16 x, u16 y, u16 w, u16 h)
++{
++ u8 tmp[18];
++ int x_end, y_end;
++
++ DBG("blizzard_ctrl_setup_update\n");
++
++ x_end = x + w - 1;
++ y_end = y + h - 1;
++
++ tmp[0] = x;
++ tmp[1] = x >> 8;
++ tmp[2] = y;
++ tmp[3] = y >> 8;
++ tmp[4] = x_end;
++ tmp[5] = x_end >> 8;
++ tmp[6] = y_end;
++ tmp[7] = y_end >> 8;
++
++ /* scaling? */
++ tmp[8] = x;
++ tmp[9] = x >> 8;
++ tmp[10] = y;
++ tmp[11] = y >> 8;
++ tmp[12] = x_end;
++ tmp[13] = x_end >> 8;
++ tmp[14] = y_end;
++ tmp[15] = y_end >> 8;
++
++ tmp[16] = BLIZZARD_COLOR_RGB565; //color_mode;
++
++ if (blizzard.version == BLIZZARD_VERSION_S1D13745)
++ tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
++ else
++ tmp[17] = blizzard.version == BLIZZARD_VERSION_S1D13744 ?
++ BLIZZARD_SRC_WRITE_LCD :
++ BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
++
++ rfbi_configure(display->hw_config.u.rfbi.channel,
++ 16,
++ 8);
++
++ blizzard_write(BLIZZARD_INPUT_WIN_X_START_0, tmp, 18);
++
++ rfbi_configure(display->hw_config.u.rfbi.channel,
++ 16,
++ 16);
++}
++
++static int blizzard_ctrl_enable_te(struct omap_display *display, bool enable)
++{
++ return 0;
++}
++
++static int blizzard_ctrl_rotate(struct omap_display *display, u8 rotate)
++{
++ return 0;
++}
++
++static int blizzard_ctrl_mirror(struct omap_display *display, bool enable)
++{
++ return 0;
++}
++
++static int blizzard_run_test(struct omap_display *display, int test_num)
++{
++ return 0;
++}
++
++static struct omap_ctrl blizzard_ctrl = {
++ .owner = THIS_MODULE,
++ .name = "ctrl-blizzard",
++ .init = blizzard_ctrl_init,
++ .enable = blizzard_ctrl_enable,
++ .disable = blizzard_ctrl_disable,
++ .setup_update = blizzard_ctrl_setup_update,
++ .enable_te = blizzard_ctrl_enable_te,
++ .set_rotate = blizzard_ctrl_rotate,
++ .set_mirror = blizzard_ctrl_mirror,
++ .run_test = blizzard_run_test,
++ .pixel_size = 16,
++
++ .timings = {
++ .cs_on_time = 0,
++
++ .we_on_time = 9000,
++ .we_off_time = 18000,
++ .we_cycle_time = 36000,
++
++ .re_on_time = 9000,
++ .re_off_time = 27000,
++ .re_cycle_time = 36000,
++
++ .access_time = 27000,
++ .cs_off_time = 36000,
++
++ .cs_pulse_width = 0,
++ },
++};
++
++
++static int __init blizzard_init(void)
++{
++ DBG("blizzard_init\n");
++ omap_dss_register_ctrl(&blizzard_ctrl);
++ return 0;
++}
++
++static void __exit blizzard_exit(void)
++{
++ DBG("blizzard_exit\n");
++
++ omap_dss_unregister_ctrl(&blizzard_ctrl);
++}
++
++module_init(blizzard_init);
++module_exit(blizzard_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("Blizzard Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c
+new file mode 100644
+index 0000000..8382acb
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-generic.c
+@@ -0,0 +1,96 @@
++/*
++ * Generic panel support
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int generic_panel_init(struct omap_display *display)
++{
++ return 0;
++}
++
++static int generic_panel_enable(struct omap_display *display)
++{
++ int r = 0;
++
++ if (display->hw_config.panel_enable)
++ r = display->hw_config.panel_enable(display);
++
++ return r;
++}
++
++static void generic_panel_disable(struct omap_display *display)
++{
++ if (display->hw_config.panel_disable)
++ display->hw_config.panel_disable(display);
++}
++
++static int generic_panel_suspend(struct omap_display *display)
++{
++ generic_panel_disable(display);
++ return 0;
++}
++
++static int generic_panel_resume(struct omap_display *display)
++{
++ return generic_panel_enable(display);
++}
++
++static struct omap_panel generic_panel = {
++ .owner = THIS_MODULE,
++ .name = "panel-generic",
++ .init = generic_panel_init,
++ .enable = generic_panel_enable,
++ .disable = generic_panel_disable,
++ .suspend = generic_panel_suspend,
++ .resume = generic_panel_resume,
++
++ .timings = {
++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
++ .x_res = 640,
++ .y_res = 480,
++ .pixel_clock = 23500,
++ .hfp = 48,
++ .hsw = 32,
++ .hbp = 80,
++ .vfp = 3,
++ .vsw = 4,
++ .vbp = 7,
++ },
++
++ .config = OMAP_DSS_LCD_TFT,
++};
++
++
++static int __init generic_panel_drv_init(void)
++{
++ omap_dss_register_panel(&generic_panel);
++ return 0;
++}
++
++static void __exit generic_panel_drv_exit(void)
++{
++ omap_dss_unregister_panel(&generic_panel);
++}
++
++module_init(generic_panel_drv_init);
++module_exit(generic_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-n800.c b/drivers/video/omap2/displays/panel-n800.c
+new file mode 100644
+index 0000000..91d3e37
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-n800.c
+@@ -0,0 +1,435 @@
++
++/*#define DEBUG*/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/spi/spi.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++
++#include <mach/display.h>
++#include <mach/dma.h>
++
++#define MIPID_CMD_READ_DISP_ID 0x04
++#define MIPID_CMD_READ_RED 0x06
++#define MIPID_CMD_READ_GREEN 0x07
++#define MIPID_CMD_READ_BLUE 0x08
++#define MIPID_CMD_READ_DISP_STATUS 0x09
++#define MIPID_CMD_RDDSDR 0x0F
++#define MIPID_CMD_SLEEP_IN 0x10
++#define MIPID_CMD_SLEEP_OUT 0x11
++#define MIPID_CMD_DISP_OFF 0x28
++#define MIPID_CMD_DISP_ON 0x29
++
++#define MIPID_VER_LPH8923 3
++#define MIPID_VER_LS041Y3 4
++
++#define MIPID_ESD_CHECK_PERIOD msecs_to_jiffies(5000)
++
++#ifdef DEBUG
++#define DBG(format, ...) printk(KERN_DEBUG "PN800: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++struct pn800_device {
++ struct backlight_device *bl_dev;
++ int enabled;
++ int model;
++ int revision;
++ u8 display_id[3];
++ unsigned int saved_bklight_level;
++ unsigned long hw_guard_end; /* next value of jiffies
++ when we can issue the
++ next sleep in/out command */
++ unsigned long hw_guard_wait; /* max guard time in jiffies */
++
++ struct spi_device *spi;
++ struct mutex mutex;
++ struct omap_panel panel;
++ struct omap_display *display;
++};
++
++
++static void pn800_transfer(struct pn800_device *md, int cmd,
++ const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
++{
++ struct spi_message m;
++ struct spi_transfer *x, xfer[4];
++ u16 w;
++ int r;
++
++ BUG_ON(md->spi == NULL);
++
++ spi_message_init(&m);
++
++ memset(xfer, 0, sizeof(xfer));
++ x = &xfer[0];
++
++ cmd &= 0xff;
++ x->tx_buf = &cmd;
++ x->bits_per_word = 9;
++ x->len = 2;
++ spi_message_add_tail(x, &m);
++
++ if (wlen) {
++ x++;
++ x->tx_buf = wbuf;
++ x->len = wlen;
++ x->bits_per_word = 9;
++ spi_message_add_tail(x, &m);
++ }
++
++ if (rlen) {
++ x++;
++ x->rx_buf = &w;
++ x->len = 1;
++ spi_message_add_tail(x, &m);
++
++ if (rlen > 1) {
++ /* Arrange for the extra clock before the first
++ * data bit.
++ */
++ x->bits_per_word = 9;
++ x->len = 2;
++
++ x++;
++ x->rx_buf = &rbuf[1];
++ x->len = rlen - 1;
++ spi_message_add_tail(x, &m);
++ }
++ }
++
++ r = spi_sync(md->spi, &m);
++ if (r < 0)
++ dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
++
++ if (rlen)
++ rbuf[0] = w & 0xff;
++}
++
++static inline void pn800_cmd(struct pn800_device *md, int cmd)
++{
++ pn800_transfer(md, cmd, NULL, 0, NULL, 0);
++}
++
++static inline void pn800_write(struct pn800_device *md,
++ int reg, const u8 *buf, int len)
++{
++ pn800_transfer(md, reg, buf, len, NULL, 0);
++}
++
++static inline void pn800_read(struct pn800_device *md,
++ int reg, u8 *buf, int len)
++{
++ pn800_transfer(md, reg, NULL, 0, buf, len);
++}
++
++static void set_data_lines(struct pn800_device *md, int data_lines)
++{
++ u16 par;
++
++ switch (data_lines) {
++ case 16:
++ par = 0x150;
++ break;
++ case 18:
++ par = 0x160;
++ break;
++ case 24:
++ par = 0x170;
++ break;
++ }
++ pn800_write(md, 0x3a, (u8 *)&par, 2);
++}
++
++static void send_init_string(struct pn800_device *md)
++{
++ u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
++ int data_lines;
++
++ pn800_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
++
++ data_lines = (int)md->display->hw_config.panel_data; // XXX
++
++ set_data_lines(md, data_lines);
++}
++
++static void hw_guard_start(struct pn800_device *md, int guard_msec)
++{
++ md->hw_guard_wait = msecs_to_jiffies(guard_msec);
++ md->hw_guard_end = jiffies + md->hw_guard_wait;
++}
++
++static void hw_guard_wait(struct pn800_device *md)
++{
++ unsigned long wait = md->hw_guard_end - jiffies;
++
++ if ((long)wait > 0 && wait <= md->hw_guard_wait) {
++ set_current_state(TASK_UNINTERRUPTIBLE);
++ schedule_timeout(wait);
++ }
++}
++
++static void set_sleep_mode(struct pn800_device *md, int on)
++{
++ int cmd, sleep_time = 50;
++
++ if (on)
++ cmd = MIPID_CMD_SLEEP_IN;
++ else
++ cmd = MIPID_CMD_SLEEP_OUT;
++ hw_guard_wait(md);
++ pn800_cmd(md, cmd);
++ hw_guard_start(md, 120);
++ /*
++ * When we enable the panel, it seems we _have_ to sleep
++ * 120 ms before sending the init string. When disabling the
++ * panel we'll sleep for the duration of 2 frames, so that the
++ * controller can still provide the PCLK,HS,VS signals. */
++ if (!on)
++ sleep_time = 120;
++ msleep(sleep_time);
++}
++
++static void set_display_state(struct pn800_device *md, int enabled)
++{
++ int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
++
++ pn800_cmd(md, cmd);
++}
++
++static int panel_enabled(struct pn800_device *md)
++{
++ u32 disp_status;
++ int enabled;
++
++ pn800_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
++ disp_status = __be32_to_cpu(disp_status);
++ enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
++ dev_dbg(&md->spi->dev,
++ "LCD panel %s enabled by bootloader (status 0x%04x)\n",
++ enabled ? "" : "not ", disp_status);
++ DBG("status %#08x\n", disp_status);
++ return enabled;
++}
++
++static int panel_detect(struct pn800_device *md)
++{
++ pn800_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
++ dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
++ md->display_id[0], md->display_id[1], md->display_id[2]);
++
++ switch (md->display_id[0]) {
++ case 0x45:
++ md->model = MIPID_VER_LPH8923;
++ md->panel.name = "lph8923";
++ break;
++ case 0x83:
++ md->model = MIPID_VER_LS041Y3;
++ md->panel.name = "ls041y3";
++ //md->esd_check = ls041y3_esd_check;
++ break;
++ default:
++ md->panel.name = "unknown";
++ dev_err(&md->spi->dev, "invalid display ID\n");
++ return -ENODEV;
++ }
++
++ md->revision = md->display_id[1];
++ pr_info("omapfb: %s rev %02x LCD detected\n",
++ md->panel.name, md->revision);
++
++ return 0;
++}
++
++
++
++static int pn800_panel_enable(struct omap_display *display)
++{
++ int r;
++ struct pn800_device *md =
++ (struct pn800_device *)display->panel->priv;
++
++ DBG("pn800_panel_enable\n");
++
++ mutex_lock(&md->mutex);
++
++ if (display->hw_config.panel_enable)
++ display->hw_config.panel_enable(display);
++
++ msleep(50); // wait for power up
++
++ r = panel_detect(md);
++ if (r) {
++ mutex_unlock(&md->mutex);
++ return r;
++ }
++
++ md->enabled = panel_enabled(md);
++
++ if (md->enabled) {
++ DBG("panel already enabled\n");
++ ; /*pn800_esd_start_check(md);*/
++ } else {
++ ; /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
++ }
++
++
++ if (md->enabled) {
++ mutex_unlock(&md->mutex);
++ return 0;
++ }
++
++ set_sleep_mode(md, 0);
++ md->enabled = 1;
++ send_init_string(md);
++ set_display_state(md, 1);
++ //mipid_set_bklight_level(panel, md->saved_bklight_level);
++ //mipid_esd_start_check(md);
++
++ mutex_unlock(&md->mutex);
++ return 0;
++}
++
++static void pn800_panel_disable(struct omap_display *display)
++{
++ struct pn800_device *md =
++ (struct pn800_device *)display->panel->priv;
++
++ DBG("pn800_panel_disable\n");
++
++ mutex_lock(&md->mutex);
++
++ if (!md->enabled) {
++ mutex_unlock(&md->mutex);
++ return;
++ }
++ /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
++ /*pn800_set_bklight_level(panel, 0);*/
++
++ set_display_state(md, 0);
++ set_sleep_mode(md, 1);
++ md->enabled = 0;
++
++
++ if (display->hw_config.panel_disable)
++ display->hw_config.panel_disable(display);
++
++ mutex_unlock(&md->mutex);
++}
++
++static int pn800_panel_init(struct omap_display *display)
++{
++ struct pn800_device *md =
++ (struct pn800_device *)display->panel->priv;
++
++ DBG("pn800_panel_init\n");
++
++ mutex_init(&md->mutex);
++ md->display = display;
++
++ return 0;
++}
++
++static int pn800_run_test(struct omap_display *display, int test_num)
++{
++ return 0;
++}
++
++static struct omap_panel pn800_panel = {
++ .owner = THIS_MODULE,
++ .name = "panel-pn800",
++ .init = pn800_panel_init,
++ /*.remove = pn800_cleanup,*/
++ .enable = pn800_panel_enable,
++ .disable = pn800_panel_disable,
++ //.set_mode = pn800_set_mode,
++ .run_test = pn800_run_test,
++
++ .timings = {
++ .x_res = 800,
++ .y_res = 480,
++
++ .pixel_clock = 21940,
++ .hsw = 50,
++ .hfp = 20,
++ .hbp = 15,
++
++ .vsw = 2,
++ .vfp = 1,
++ .vbp = 3,
++ },
++ .config = OMAP_DSS_LCD_TFT,
++};
++
++static int pn800_spi_probe(struct spi_device *spi)
++{
++ struct pn800_device *md;
++
++ DBG("pn800_spi_probe\n");
++
++ md = kzalloc(sizeof(*md), GFP_KERNEL);
++ if (md == NULL) {
++ dev_err(&spi->dev, "out of memory\n");
++ return -ENOMEM;
++ }
++
++ spi->mode = SPI_MODE_0;
++ md->spi = spi;
++ dev_set_drvdata(&spi->dev, md);
++ md->panel = pn800_panel;
++ pn800_panel.priv = md;
++
++ omap_dss_register_panel(&pn800_panel);
++
++ return 0;
++}
++
++static int pn800_spi_remove(struct spi_device *spi)
++{
++ struct pn800_device *md = dev_get_drvdata(&spi->dev);
++
++ DBG("pn800_spi_remove\n");
++
++ omap_dss_unregister_panel(&pn800_panel);
++
++ /*pn800_disable(&md->panel);*/
++ kfree(md);
++
++ return 0;
++}
++
++static struct spi_driver pn800_spi_driver = {
++ .driver = {
++ .name = "panel-n800",
++ .bus = &spi_bus_type,
++ .owner = THIS_MODULE,
++ },
++ .probe = pn800_spi_probe,
++ .remove = __devexit_p(pn800_spi_remove),
++};
++
++static int __init pn800_init(void)
++{
++ DBG("pn800_init\n");
++ return spi_register_driver(&pn800_spi_driver);
++}
++
++static void __exit pn800_exit(void)
++{
++ DBG("pn800_exit\n");
++ spi_unregister_driver(&pn800_spi_driver);
++}
++
++module_init(pn800_init);
++module_exit(pn800_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("N800 LCD Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+new file mode 100644
+index 0000000..e4bb781
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+@@ -0,0 +1,108 @@
++/*
++ * LCD panel driver for Samsung LTE430WQ-F0C
++ *
++ * Author: Steve Sakoman <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int samsung_lte_panel_init(struct omap_display *display)
++{
++ return 0;
++}
++
++static void samsung_lte_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int samsung_lte_panel_enable(struct omap_display *display)
++{
++ int r = 0;
++
++ /* wait couple of vsyncs until enabling the LCD */
++ msleep(50);
++
++ if (display->hw_config.panel_enable)
++ r = display->hw_config.panel_enable(display);
++
++ return r;
++}
++
++static void samsung_lte_panel_disable(struct omap_display *display)
++{
++ if (display->hw_config.panel_disable)
++ display->hw_config.panel_disable(display);
++
++ /* wait at least 5 vsyncs after disabling the LCD */
++ msleep(100);
++}
++
++static int samsung_lte_panel_suspend(struct omap_display *display)
++{
++ samsung_lte_panel_disable(display);
++ return 0;
++}
++
++static int samsung_lte_panel_resume(struct omap_display *display)
++{
++ return samsung_lte_panel_enable(display);
++}
++
++static struct omap_panel samsung_lte_panel = {
++ .owner = THIS_MODULE,
++ .name = "samsung-lte430wq-f0c",
++ .init = samsung_lte_panel_init,
++ .cleanup = samsung_lte_panel_cleanup,
++ .enable = samsung_lte_panel_enable,
++ .disable = samsung_lte_panel_disable,
++ .suspend = samsung_lte_panel_suspend,
++ .resume = samsung_lte_panel_resume,
++
++ .timings = {
++ .x_res = 480,
++ .y_res = 272,
++
++ .pixel_clock = 9200,
++
++ .hsw = 41,
++ .hfp = 8,
++ .hbp = 45-41,
++
++ .vsw = 10,
++ .vfp = 4,
++ .vbp = 12-10,
++ },
++
++ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS,
++};
++
++
++static int __init samsung_lte_panel_drv_init(void)
++{
++ omap_dss_register_panel(&samsung_lte_panel);
++ return 0;
++}
++
++static void __exit samsung_lte_panel_drv_exit(void)
++{
++ omap_dss_unregister_panel(&samsung_lte_panel);
++}
++
++module_init(samsung_lte_panel_drv_init);
++module_exit(samsung_lte_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+new file mode 100644
+index 0000000..1f99150
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+@@ -0,0 +1,112 @@
++/*
++ * LCD panel driver for Sharp LS037V7DW01
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static int sharp_ls_panel_init(struct omap_display *display)
++{
++ return 0;
++}
++
++static void sharp_ls_panel_cleanup(struct omap_display *display)
++{
++}
++
++static int sharp_ls_panel_enable(struct omap_display *display)
++{
++ int r = 0;
++
++ /* wait couple of vsyncs until enabling the LCD */
++ msleep(50);
++
++ if (display->hw_config.panel_enable)
++ r = display->hw_config.panel_enable(display);
++
++ return r;
++}
++
++static void sharp_ls_panel_disable(struct omap_display *display)
++{
++ if (display->hw_config.panel_disable)
++ display->hw_config.panel_disable(display);
++
++ /* wait at least 5 vsyncs after disabling the LCD */
++
++ msleep(100);
++}
++
++static int sharp_ls_panel_suspend(struct omap_display *display)
++{
++ sharp_ls_panel_disable(display);
++ return 0;
++}
++
++static int sharp_ls_panel_resume(struct omap_display *display)
++{
++ return sharp_ls_panel_enable(display);
++}
++
++static struct omap_panel sharp_ls_panel = {
++ .owner = THIS_MODULE,
++ .name = "sharp-ls037v7dw01",
++ .init = sharp_ls_panel_init,
++ .cleanup = sharp_ls_panel_cleanup,
++ .enable = sharp_ls_panel_enable,
++ .disable = sharp_ls_panel_disable,
++ .suspend = sharp_ls_panel_suspend,
++ .resume = sharp_ls_panel_resume,
++
++ .timings = {
++ .x_res = 480,
++ .y_res = 640,
++
++ .pixel_clock = 19200,
++
++ .hsw = 2,
++ .hfp = 1,
++ .hbp = 28,
++
++ .vsw = 1,
++ .vfp = 1,
++ .vbp = 1,
++ },
++
++ .acb = 0x28,
++
++ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS,
++};
++
++
++static int __init sharp_ls_panel_drv_init(void)
++{
++ omap_dss_register_panel(&sharp_ls_panel);
++ return 0;
++}
++
++static void __exit sharp_ls_panel_drv_exit(void)
++{
++ omap_dss_unregister_panel(&sharp_ls_panel);
++}
++
++module_init(sharp_ls_panel_drv_init);
++module_exit(sharp_ls_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
+new file mode 100644
+index 0000000..f2ce068
+--- /dev/null
++++ b/drivers/video/omap2/dss/Kconfig
+@@ -0,0 +1,89 @@
++menuconfig OMAP2_DSS
++ tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
++ depends on ARCH_OMAP2 || ARCH_OMAP3
++ help
++ OMAP2/3 Display Subsystem support.
++
++if OMAP2_DSS
++
++config OMAP2_DSS_VRAM_SIZE
++ int "VRAM size (MB)"
++ range 0 32
++ default 4
++ help
++ The amount of SDRAM to reserve at boot time for video RAM use.
++ This VRAM will be used by omapfb and other drivers that need
++ large continuous RAM area for video use.
++
++ You can also set this with "vram=<bytes>" kernel argument, or
++ in the board file.
++
++config OMAP2_DSS_DEBUG_SUPPORT
++ bool "Debug support"
++ default y
++ help
++ This enables debug messages. You need to enable printing
++ with 'debug' module parameter.
++
++config OMAP2_DSS_RFBI
++ bool "RFBI support"
++ default n
++ help
++ MIPI DBI, or RFBI (Remote Framebuffer Interface), support.
++
++config OMAP2_DSS_VENC
++ bool "VENC support"
++ default y
++ help
++ OMAP Video Encoder support.
++
++config OMAP2_DSS_SDI
++ bool "SDI support"
++ depends on ARCH_OMAP3
++ default n
++ help
++ SDI (Serial Display Interface) support.
++
++config OMAP2_DSS_DSI
++ bool "DSI support"
++ depends on ARCH_OMAP3
++ default n
++ help
++ MIPI DSI support.
++
++config OMAP2_DSS_USE_DSI_PLL
++ bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
++ default n
++ depends on OMAP2_DSS_DSI
++ help
++ Use DSI PLL to generate pixel clock. Currently only for DPI output.
++ DSI PLL can be used to generate higher and more precise pixel clocks.
++
++config OMAP2_DSS_FAKE_VSYNC
++ bool "Fake VSYNC irq from manual update displays"
++ default n
++ help
++ If this is selected, DSI will generate a fake DISPC VSYNC interrupt
++ when DSI has sent a frame. This is only needed with DSI or RFBI
++ displays using manual mode, and you want VSYNC to, for example,
++ time animation.
++
++config OMAP2_DSS_MIN_FCK_PER_PCK
++ int "Minimum FCK/PCK ratio (for scaling)"
++ range 0 32
++ default 0
++ help
++ This can be used to adjust the minimum FCK/PCK ratio.
++
++ With this you can make sure that DISPC FCK is at least
++ n x PCK. Video plane scaling requires higher FCK than
++ normally.
++
++ If this is set to 0, there's no extra constraint on the
++ DISPC FCK. However, the FCK will at minimum be
++ 2xPCK (if active matrix) or 3xPCK (if passive matrix).
++
++ Max FCK is 173MHz, so this doesn't work if your PCK
++ is very high.
++
++endif
+diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
+new file mode 100644
+index 0000000..980c72c
+--- /dev/null
++++ b/drivers/video/omap2/dss/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_OMAP2_DSS) += omapdss.o
++omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
++omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
++omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
++omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
++omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
+diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
+new file mode 100644
+index 0000000..ae7cd06
+--- /dev/null
++++ b/drivers/video/omap2/dss/core.c
+@@ -0,0 +1,641 @@
++/*
++ * linux/drivers/video/omap2/dss/core.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "CORE"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/seq_file.h>
++#include <linux/debugfs.h>
++#include <linux/io.h>
++
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++static struct {
++ struct platform_device *pdev;
++ unsigned ctx_id;
++
++ struct clk *dss_ick;
++ struct clk *dss1_fck;
++ struct clk *dss2_fck;
++ struct clk *dss_54m_fck;
++ struct clk *dss_96m_fck;
++ unsigned num_clks_enabled;
++} core;
++
++static void dss_clk_enable_all_no_ctx(void);
++static void dss_clk_disable_all_no_ctx(void);
++static void dss_clk_enable_no_ctx(enum dss_clock clks);
++static void dss_clk_disable_no_ctx(enum dss_clock clks);
++
++static char *def_disp_name;
++module_param_named(def_disp, def_disp_name, charp, 0);
++MODULE_PARM_DESC(def_disp_name, "default display name");
++
++#ifdef DEBUG
++unsigned int dss_debug;
++module_param_named(debug, dss_debug, bool, 0644);
++#endif
++
++/* CONTEXT */
++static unsigned dss_get_ctx_id(void)
++{
++ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++
++ if (!pdata->get_last_off_on_transaction_id)
++ return 0;
++
++ return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
++}
++
++int dss_need_ctx_restore(void)
++{
++ int id = dss_get_ctx_id();
++
++ if (id != core.ctx_id) {
++ DSSDBG("ctx id %u -> id %u\n",
++ core.ctx_id, id);
++ core.ctx_id = id;
++ return 1;
++ } else {
++ return 0;
++ }
++}
++
++static void save_all_ctx(void)
++{
++ DSSDBG("save context\n");
++
++ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ dss_save_context();
++ dispc_save_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++ dsi_save_context();
++#endif
++
++ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++static void restore_all_ctx(void)
++{
++ DSSDBG("restore context\n");
++
++ dss_clk_enable_all_no_ctx();
++
++ dss_restore_context();
++ dispc_restore_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++ dsi_restore_context();
++#endif
++
++ dss_clk_disable_all_no_ctx();
++}
++
++/* CLOCKS */
++void dss_dump_clocks(struct seq_file *s)
++{
++ int i;
++ struct clk *clocks[5] = {
++ core.dss_ick,
++ core.dss1_fck,
++ core.dss2_fck,
++ core.dss_54m_fck,
++ core.dss_96m_fck
++ };
++
++ seq_printf(s, "- dss -\n");
++
++ seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled);
++
++ for (i = 0; i < 5; i++) {
++ if (!clocks[i])
++ continue;
++ seq_printf(s, "%-15s\t%lu\t%d\n",
++ clocks[i]->name,
++ clk_get_rate(clocks[i]),
++ clocks[i]->usecount);
++ }
++}
++
++static int dss_get_clocks(void)
++{
++ const struct {
++ struct clk **clock;
++ char *omap2_name;
++ char *omap3_name;
++ } clocks[5] = {
++ { &core.dss_ick, "dss_ick", "dss_ick" }, /* L3 & L4 ick */
++ { &core.dss1_fck, "dss1_fck", "dss1_alwon_fck" },
++ { &core.dss2_fck, "dss2_fck", "dss2_alwon_fck" },
++ { &core.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" },
++ { &core.dss_96m_fck, NULL, "dss_96m_fck" },
++ };
++
++ int r = 0;
++ int i;
++ const int num_clocks = 5;
++
++ for (i = 0; i < num_clocks; i++)
++ *clocks[i].clock = NULL;
++
++ for (i = 0; i < num_clocks; i++) {
++ struct clk *clk;
++ const char *clk_name;
++
++ clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name
++ : clocks[i].omap2_name;
++
++ if (!clk_name)
++ continue;
++
++ clk = clk_get(NULL, clk_name);
++
++ if (IS_ERR(clk)) {
++ DSSERR("can't get clock %s", clk_name);
++ r = PTR_ERR(clk);
++ goto err;
++ }
++
++ DSSDBG("clk %s, rate %ld\n",
++ clk_name, clk_get_rate(clk));
++
++ *clocks[i].clock = clk;
++ }
++
++ return 0;
++
++err:
++ for (i = 0; i < num_clocks; i++) {
++ if (!IS_ERR(*clocks[i].clock))
++ clk_put(*clocks[i].clock);
++ }
++
++ return r;
++}
++
++static void dss_put_clocks(void)
++{
++ if (core.dss_96m_fck)
++ clk_put(core.dss_96m_fck);
++ clk_put(core.dss_54m_fck);
++ clk_put(core.dss1_fck);
++ clk_put(core.dss2_fck);
++ clk_put(core.dss_ick);
++}
++
++unsigned long dss_clk_get_rate(enum dss_clock clk)
++{
++ switch (clk) {
++ case DSS_CLK_ICK:
++ return clk_get_rate(core.dss_ick);
++ case DSS_CLK_FCK1:
++ return clk_get_rate(core.dss1_fck);
++ case DSS_CLK_FCK2:
++ return clk_get_rate(core.dss2_fck);
++ case DSS_CLK_54M:
++ return clk_get_rate(core.dss_54m_fck);
++ case DSS_CLK_96M:
++ return clk_get_rate(core.dss_96m_fck);
++ }
++
++ BUG();
++ return 0;
++}
++
++static unsigned count_clk_bits(enum dss_clock clks)
++{
++ unsigned num_clks = 0;
++
++ if (clks & DSS_CLK_ICK)
++ ++num_clks;
++ if (clks & DSS_CLK_FCK1)
++ ++num_clks;
++ if (clks & DSS_CLK_FCK2)
++ ++num_clks;
++ if (clks & DSS_CLK_54M)
++ ++num_clks;
++ if (clks & DSS_CLK_96M)
++ ++num_clks;
++
++ return num_clks;
++}
++
++static void dss_clk_enable_no_ctx(enum dss_clock clks)
++{
++ unsigned num_clks = count_clk_bits(clks);
++
++ if (clks & DSS_CLK_ICK)
++ clk_enable(core.dss_ick);
++ if (clks & DSS_CLK_FCK1)
++ clk_enable(core.dss1_fck);
++ if (clks & DSS_CLK_FCK2)
++ clk_enable(core.dss2_fck);
++ if (clks & DSS_CLK_54M)
++ clk_enable(core.dss_54m_fck);
++ if (clks & DSS_CLK_96M)
++ clk_enable(core.dss_96m_fck);
++
++ core.num_clks_enabled += num_clks;
++}
++
++void dss_clk_enable(enum dss_clock clks)
++{
++ dss_clk_enable_no_ctx(clks);
++
++ if (cpu_is_omap34xx() && dss_need_ctx_restore())
++ restore_all_ctx();
++}
++
++static void dss_clk_disable_no_ctx(enum dss_clock clks)
++{
++ unsigned num_clks = count_clk_bits(clks);
++
++ if (clks & DSS_CLK_ICK)
++ clk_disable(core.dss_ick);
++ if (clks & DSS_CLK_FCK1)
++ clk_disable(core.dss1_fck);
++ if (clks & DSS_CLK_FCK2)
++ clk_disable(core.dss2_fck);
++ if (clks & DSS_CLK_54M)
++ clk_disable(core.dss_54m_fck);
++ if (clks & DSS_CLK_96M)
++ clk_disable(core.dss_96m_fck);
++
++ core.num_clks_enabled -= num_clks;
++}
++
++void dss_clk_disable(enum dss_clock clks)
++{
++ if (cpu_is_omap34xx()) {
++ unsigned num_clks = count_clk_bits(clks);
++
++ BUG_ON(core.num_clks_enabled < num_clks);
++
++ if (core.num_clks_enabled == num_clks)
++ save_all_ctx();
++ }
++
++ dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_enable_all_no_ctx(void)
++{
++ enum dss_clock clks;
++
++ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++ if (cpu_is_omap34xx())
++ clks |= DSS_CLK_96M;
++ dss_clk_enable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all_no_ctx(void)
++{
++ enum dss_clock clks;
++
++ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++ if (cpu_is_omap34xx())
++ clks |= DSS_CLK_96M;
++ dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all(void)
++{
++ enum dss_clock clks;
++
++ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++ if (cpu_is_omap34xx())
++ clks |= DSS_CLK_96M;
++ dss_clk_disable(clks);
++}
++
++/* DEBUGFS */
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++static void dss_debug_dump_clocks(struct seq_file *s)
++{
++ dss_dump_clocks(s);
++ dispc_dump_clocks(s);
++#ifdef CONFIG_OMAP2_DSS_DSI
++ dsi_dump_clocks(s);
++#endif
++}
++
++static int dss_debug_show(struct seq_file *s, void *unused)
++{
++ void (*func)(struct seq_file *) = s->private;
++ func(s);
++ return 0;
++}
++
++static int dss_debug_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, dss_debug_show, inode->i_private);
++}
++
++static const struct file_operations dss_debug_fops = {
++ .open = dss_debug_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static struct dentry *dss_debugfs_dir;
++
++static int dss_initialize_debugfs(void)
++{
++ dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
++ if (IS_ERR(dss_debugfs_dir)) {
++ int err = PTR_ERR(dss_debugfs_dir);
++ dss_debugfs_dir = NULL;
++ return err;
++ }
++
++ debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
++ &dss_debug_dump_clocks, &dss_debug_fops);
++
++ debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
++ &dss_dump_regs, &dss_debug_fops);
++ debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
++ &dispc_dump_regs, &dss_debug_fops);
++#ifdef CONFIG_OMAP2_DSS_RFBI
++ debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
++ &rfbi_dump_regs, &dss_debug_fops);
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++ debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
++ &dsi_dump_regs, &dss_debug_fops);
++#endif
++ return 0;
++}
++
++static void dss_uninitialize_debugfs(void)
++{
++ if (dss_debugfs_dir)
++ debugfs_remove_recursive(dss_debugfs_dir);
++}
++#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
++
++
++/* DSI powers */
++int dss_dsi_power_up(void)
++{
++ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++
++ if (!pdata->dsi_power_up)
++ return 0; /* presume power is always on then */
++
++ return pdata->dsi_power_up();
++}
++
++void dss_dsi_power_down(void)
++{
++ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++
++ if (!pdata->dsi_power_down)
++ return;
++
++ pdata->dsi_power_down();
++}
++
++
++
++/* PLATFORM DEVICE */
++static int omap_dss_probe(struct platform_device *pdev)
++{
++ int skip_init = 0;
++ int r;
++
++ core.pdev = pdev;
++
++ r = dss_get_clocks();
++ if (r)
++ goto fail0;
++
++ dss_clk_enable_all_no_ctx();
++
++ core.ctx_id = dss_get_ctx_id();
++ DSSDBG("initial ctx id %u\n", core.ctx_id);
++
++#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
++ /* DISPC_CONTROL */
++ if (omap_readl(0x48050440) & 1) /* LCD enabled? */
++ skip_init = 1;
++#endif
++
++ r = dss_init(skip_init);
++ if (r) {
++ DSSERR("Failed to initialize DSS\n");
++ goto fail0;
++ }
++
++#ifdef CONFIG_OMAP2_DSS_RFBI
++ r = rfbi_init();
++ if (r) {
++ DSSERR("Failed to initialize rfbi\n");
++ goto fail0;
++ }
++#endif
++
++ r = dpi_init();
++ if (r) {
++ DSSERR("Failed to initialize dpi\n");
++ goto fail0;
++ }
++
++ r = dispc_init();
++ if (r) {
++ DSSERR("Failed to initialize dispc\n");
++ goto fail0;
++ }
++#ifdef CONFIG_OMAP2_DSS_VENC
++ r = venc_init();
++ if (r) {
++ DSSERR("Failed to initialize venc\n");
++ goto fail0;
++ }
++#endif
++ if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_SDI
++ r = sdi_init(skip_init);
++ if (r) {
++ DSSERR("Failed to initialize SDI\n");
++ goto fail0;
++ }
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++ r = dsi_init();
++ if (r) {
++ DSSERR("Failed to initialize DSI\n");
++ goto fail0;
++ }
++#endif
++ }
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++ r = dss_initialize_debugfs();
++ if (r)
++ goto fail0;
++#endif
++
++ dss_init_displays(pdev);
++ dss_init_overlay_managers(pdev);
++ dss_init_overlays(pdev, def_disp_name);
++
++ dss_clk_disable_all();
++
++ return 0;
++
++ /* XXX fail correctly */
++fail0:
++ return r;
++}
++
++static int omap_dss_remove(struct platform_device *pdev)
++{
++ int c;
++
++ dss_uninit_overlays(pdev);
++ dss_uninit_overlay_managers(pdev);
++ dss_uninit_displays(pdev);
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++ dss_uninitialize_debugfs();
++#endif
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++ venc_exit();
++#endif
++ dispc_exit();
++ dpi_exit();
++#ifdef CONFIG_OMAP2_DSS_RFBI
++ rfbi_exit();
++#endif
++ if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_DSI
++ dsi_exit();
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++ sdi_exit();
++#endif
++ }
++
++ dss_exit();
++
++ /* these should be removed at some point */
++ c = core.dss_ick->usecount;
++ if (c > 0) {
++ DSSERR("warning: dss_ick usecount %d, disabling\n", c);
++ while (c-- > 0)
++ clk_disable(core.dss_ick);
++ }
++
++ c = core.dss1_fck->usecount;
++ if (c > 0) {
++ DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
++ while (c-- > 0)
++ clk_disable(core.dss1_fck);
++ }
++
++ c = core.dss2_fck->usecount;
++ if (c > 0) {
++ DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
++ while (c-- > 0)
++ clk_disable(core.dss2_fck);
++ }
++
++ c = core.dss_54m_fck->usecount;
++ if (c > 0) {
++ DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
++ while (c-- > 0)
++ clk_disable(core.dss_54m_fck);
++ }
++
++ if (core.dss_96m_fck) {
++ c = core.dss_96m_fck->usecount;
++ if (c > 0) {
++ DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
++ c);
++ while (c-- > 0)
++ clk_disable(core.dss_96m_fck);
++ }
++ }
++
++ dss_put_clocks();
++
++ return 0;
++}
++
++static void omap_dss_shutdown(struct platform_device *pdev)
++{
++ DSSDBG("shutdown\n");
++}
++
++static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ DSSDBG("suspend %d\n", state.event);
++
++ return dss_suspend_all_displays();
++}
++
++static int omap_dss_resume(struct platform_device *pdev)
++{
++ DSSDBG("resume\n");
++
++ return dss_resume_all_displays();
++}
++
++static struct platform_driver omap_dss_driver = {
++ .probe = omap_dss_probe,
++ .remove = omap_dss_remove,
++ .shutdown = omap_dss_shutdown,
++ .suspend = omap_dss_suspend,
++ .resume = omap_dss_resume,
++ .driver = {
++ .name = "omapdss",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init omap_dss_init(void)
++{
++ return platform_driver_register(&omap_dss_driver);
++}
++
++static void __exit omap_dss_exit(void)
++{
++ platform_driver_unregister(&omap_dss_driver);
++}
++
++subsys_initcall(omap_dss_init);
++module_exit(omap_dss_exit);
++
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+new file mode 100644
+index 0000000..ae3e9d0
+--- /dev/null
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -0,0 +1,2781 @@
++/*
++ * linux/drivers/video/omap2/dss/dispc.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPC"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/jiffies.h>
++#include <linux/seq_file.h>
++
++#include <mach/sram.h>
++#include <mach/board.h>
++#include <mach/clock.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++/* DISPC */
++#define DISPC_BASE 0x48050400
++
++#define DISPC_SZ_REGS SZ_1K
++
++struct dispc_reg { u16 idx; };
++
++#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
++
++/* DISPC common */
++#define DISPC_REVISION DISPC_REG(0x0000)
++#define DISPC_SYSCONFIG DISPC_REG(0x0010)
++#define DISPC_SYSSTATUS DISPC_REG(0x0014)
++#define DISPC_IRQSTATUS DISPC_REG(0x0018)
++#define DISPC_IRQENABLE DISPC_REG(0x001C)
++#define DISPC_CONTROL DISPC_REG(0x0040)
++#define DISPC_CONFIG DISPC_REG(0x0044)
++#define DISPC_CAPABLE DISPC_REG(0x0048)
++#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
++#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
++#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
++#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
++#define DISPC_LINE_STATUS DISPC_REG(0x005C)
++#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
++#define DISPC_TIMING_H DISPC_REG(0x0064)
++#define DISPC_TIMING_V DISPC_REG(0x0068)
++#define DISPC_POL_FREQ DISPC_REG(0x006C)
++#define DISPC_DIVISOR DISPC_REG(0x0070)
++#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
++#define DISPC_SIZE_DIG DISPC_REG(0x0078)
++#define DISPC_SIZE_LCD DISPC_REG(0x007C)
++
++/* DISPC GFX plane */
++#define DISPC_GFX_BA0 DISPC_REG(0x0080)
++#define DISPC_GFX_BA1 DISPC_REG(0x0084)
++#define DISPC_GFX_POSITION DISPC_REG(0x0088)
++#define DISPC_GFX_SIZE DISPC_REG(0x008C)
++#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
++#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
++#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
++#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
++#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
++#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
++#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
++
++#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
++#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
++#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
++
++#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
++#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
++#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
++
++#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
++
++/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
++#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
++
++#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
++#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
++#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
++#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
++#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
++#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
++#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
++#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
++#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
++#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
++#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
++#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
++#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
++
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4} */
++#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
++
++#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
++
++
++#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
++ DISPC_IRQ_OCP_ERR | \
++ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
++ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
++ DISPC_IRQ_SYNC_LOST | \
++ DISPC_IRQ_SYNC_LOST_DIGIT)
++
++#define DISPC_MAX_NR_ISRS 8
++
++struct omap_dispc_isr_data {
++ omap_dispc_isr_t isr;
++ void *arg;
++ u32 mask;
++};
++
++#define REG_GET(idx, start, end) \
++ FLD_GET(dispc_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
++
++static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
++ DISPC_VID_ATTRIBUTES(0),
++ DISPC_VID_ATTRIBUTES(1) };
++
++static struct {
++ void __iomem *base;
++
++ struct clk *dpll4_m4_ck;
++
++ spinlock_t irq_lock;
++
++ unsigned long cache_req_pck;
++ unsigned long cache_prate;
++ struct dispc_clock_info cache_cinfo;
++
++ u32 irq_error_mask;
++ struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
++
++ u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
++} dispc;
++
++static void omap_dispc_set_irqs(void);
++
++static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
++{
++ __raw_writel(val, dispc.base + idx.idx);
++}
++
++static inline u32 dispc_read_reg(const struct dispc_reg idx)
++{
++ return __raw_readl(dispc.base + idx.idx);
++}
++
++#define SR(reg) \
++ dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
++#define RR(reg) \
++ dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
++
++void dispc_save_context(void)
++{
++ if (cpu_is_omap24xx())
++ return;
++
++ SR(SYSCONFIG);
++ SR(IRQENABLE);
++ SR(CONTROL);
++ SR(CONFIG);
++ SR(DEFAULT_COLOR0);
++ SR(DEFAULT_COLOR1);
++ SR(TRANS_COLOR0);
++ SR(TRANS_COLOR1);
++ SR(LINE_NUMBER);
++ SR(TIMING_H);
++ SR(TIMING_V);
++ SR(POL_FREQ);
++ SR(DIVISOR);
++ SR(GLOBAL_ALPHA);
++ SR(SIZE_DIG);
++ SR(SIZE_LCD);
++
++ SR(GFX_BA0);
++ SR(GFX_BA1);
++ SR(GFX_POSITION);
++ SR(GFX_SIZE);
++ SR(GFX_ATTRIBUTES);
++ SR(GFX_FIFO_THRESHOLD);
++ SR(GFX_ROW_INC);
++ SR(GFX_PIXEL_INC);
++ SR(GFX_WINDOW_SKIP);
++ SR(GFX_TABLE_BA);
++
++ SR(DATA_CYCLE1);
++ SR(DATA_CYCLE2);
++ SR(DATA_CYCLE3);
++
++ SR(CPR_COEF_R);
++ SR(CPR_COEF_G);
++ SR(CPR_COEF_B);
++
++ SR(GFX_PRELOAD);
++
++ /* VID1 */
++ SR(VID_BA0(0));
++ SR(VID_BA1(0));
++ SR(VID_POSITION(0));
++ SR(VID_SIZE(0));
++ SR(VID_ATTRIBUTES(0));
++ SR(VID_FIFO_THRESHOLD(0));
++ SR(VID_ROW_INC(0));
++ SR(VID_PIXEL_INC(0));
++ SR(VID_FIR(0));
++ SR(VID_PICTURE_SIZE(0));
++ SR(VID_ACCU0(0));
++ SR(VID_ACCU1(0));
++
++ SR(VID_FIR_COEF_H(0, 0));
++ SR(VID_FIR_COEF_H(0, 1));
++ SR(VID_FIR_COEF_H(0, 2));
++ SR(VID_FIR_COEF_H(0, 3));
++ SR(VID_FIR_COEF_H(0, 4));
++ SR(VID_FIR_COEF_H(0, 5));
++ SR(VID_FIR_COEF_H(0, 6));
++ SR(VID_FIR_COEF_H(0, 7));
++
++ SR(VID_FIR_COEF_HV(0, 0));
++ SR(VID_FIR_COEF_HV(0, 1));
++ SR(VID_FIR_COEF_HV(0, 2));
++ SR(VID_FIR_COEF_HV(0, 3));
++ SR(VID_FIR_COEF_HV(0, 4));
++ SR(VID_FIR_COEF_HV(0, 5));
++ SR(VID_FIR_COEF_HV(0, 6));
++ SR(VID_FIR_COEF_HV(0, 7));
++
++ SR(VID_CONV_COEF(0, 0));
++ SR(VID_CONV_COEF(0, 1));
++ SR(VID_CONV_COEF(0, 2));
++ SR(VID_CONV_COEF(0, 3));
++ SR(VID_CONV_COEF(0, 4));
++
++ SR(VID_FIR_COEF_V(0, 0));
++ SR(VID_FIR_COEF_V(0, 1));
++ SR(VID_FIR_COEF_V(0, 2));
++ SR(VID_FIR_COEF_V(0, 3));
++ SR(VID_FIR_COEF_V(0, 4));
++ SR(VID_FIR_COEF_V(0, 5));
++ SR(VID_FIR_COEF_V(0, 6));
++ SR(VID_FIR_COEF_V(0, 7));
++
++ SR(VID_PRELOAD(0));
++
++ /* VID2 */
++ SR(VID_BA0(1));
++ SR(VID_BA1(1));
++ SR(VID_POSITION(1));
++ SR(VID_SIZE(1));
++ SR(VID_ATTRIBUTES(1));
++ SR(VID_FIFO_THRESHOLD(1));
++ SR(VID_ROW_INC(1));
++ SR(VID_PIXEL_INC(1));
++ SR(VID_FIR(1));
++ SR(VID_PICTURE_SIZE(1));
++ SR(VID_ACCU0(1));
++ SR(VID_ACCU1(1));
++
++ SR(VID_FIR_COEF_H(1, 0));
++ SR(VID_FIR_COEF_H(1, 1));
++ SR(VID_FIR_COEF_H(1, 2));
++ SR(VID_FIR_COEF_H(1, 3));
++ SR(VID_FIR_COEF_H(1, 4));
++ SR(VID_FIR_COEF_H(1, 5));
++ SR(VID_FIR_COEF_H(1, 6));
++ SR(VID_FIR_COEF_H(1, 7));
++
++ SR(VID_FIR_COEF_HV(1, 0));
++ SR(VID_FIR_COEF_HV(1, 1));
++ SR(VID_FIR_COEF_HV(1, 2));
++ SR(VID_FIR_COEF_HV(1, 3));
++ SR(VID_FIR_COEF_HV(1, 4));
++ SR(VID_FIR_COEF_HV(1, 5));
++ SR(VID_FIR_COEF_HV(1, 6));
++ SR(VID_FIR_COEF_HV(1, 7));
++
++ SR(VID_CONV_COEF(1, 0));
++ SR(VID_CONV_COEF(1, 1));
++ SR(VID_CONV_COEF(1, 2));
++ SR(VID_CONV_COEF(1, 3));
++ SR(VID_CONV_COEF(1, 4));
++
++ SR(VID_FIR_COEF_V(1, 0));
++ SR(VID_FIR_COEF_V(1, 1));
++ SR(VID_FIR_COEF_V(1, 2));
++ SR(VID_FIR_COEF_V(1, 3));
++ SR(VID_FIR_COEF_V(1, 4));
++ SR(VID_FIR_COEF_V(1, 5));
++ SR(VID_FIR_COEF_V(1, 6));
++ SR(VID_FIR_COEF_V(1, 7));
++
++ SR(VID_PRELOAD(1));
++}
++
++void dispc_restore_context(void)
++{
++ RR(SYSCONFIG);
++ RR(IRQENABLE);
++ /*RR(CONTROL);*/
++ RR(CONFIG);
++ RR(DEFAULT_COLOR0);
++ RR(DEFAULT_COLOR1);
++ RR(TRANS_COLOR0);
++ RR(TRANS_COLOR1);
++ RR(LINE_NUMBER);
++ RR(TIMING_H);
++ RR(TIMING_V);
++ RR(POL_FREQ);
++ RR(DIVISOR);
++ RR(GLOBAL_ALPHA);
++ RR(SIZE_DIG);
++ RR(SIZE_LCD);
++
++ RR(GFX_BA0);
++ RR(GFX_BA1);
++ RR(GFX_POSITION);
++ RR(GFX_SIZE);
++ RR(GFX_ATTRIBUTES);
++ RR(GFX_FIFO_THRESHOLD);
++ RR(GFX_ROW_INC);
++ RR(GFX_PIXEL_INC);
++ RR(GFX_WINDOW_SKIP);
++ RR(GFX_TABLE_BA);
++
++ RR(DATA_CYCLE1);
++ RR(DATA_CYCLE2);
++ RR(DATA_CYCLE3);
++
++ RR(CPR_COEF_R);
++ RR(CPR_COEF_G);
++ RR(CPR_COEF_B);
++
++ RR(GFX_PRELOAD);
++
++ /* VID1 */
++ RR(VID_BA0(0));
++ RR(VID_BA1(0));
++ RR(VID_POSITION(0));
++ RR(VID_SIZE(0));
++ RR(VID_ATTRIBUTES(0));
++ RR(VID_FIFO_THRESHOLD(0));
++ RR(VID_ROW_INC(0));
++ RR(VID_PIXEL_INC(0));
++ RR(VID_FIR(0));
++ RR(VID_PICTURE_SIZE(0));
++ RR(VID_ACCU0(0));
++ RR(VID_ACCU1(0));
++
++ RR(VID_FIR_COEF_H(0, 0));
++ RR(VID_FIR_COEF_H(0, 1));
++ RR(VID_FIR_COEF_H(0, 2));
++ RR(VID_FIR_COEF_H(0, 3));
++ RR(VID_FIR_COEF_H(0, 4));
++ RR(VID_FIR_COEF_H(0, 5));
++ RR(VID_FIR_COEF_H(0, 6));
++ RR(VID_FIR_COEF_H(0, 7));
++
++ RR(VID_FIR_COEF_HV(0, 0));
++ RR(VID_FIR_COEF_HV(0, 1));
++ RR(VID_FIR_COEF_HV(0, 2));
++ RR(VID_FIR_COEF_HV(0, 3));
++ RR(VID_FIR_COEF_HV(0, 4));
++ RR(VID_FIR_COEF_HV(0, 5));
++ RR(VID_FIR_COEF_HV(0, 6));
++ RR(VID_FIR_COEF_HV(0, 7));
++
++ RR(VID_CONV_COEF(0, 0));
++ RR(VID_CONV_COEF(0, 1));
++ RR(VID_CONV_COEF(0, 2));
++ RR(VID_CONV_COEF(0, 3));
++ RR(VID_CONV_COEF(0, 4));
++
++ RR(VID_FIR_COEF_V(0, 0));
++ RR(VID_FIR_COEF_V(0, 1));
++ RR(VID_FIR_COEF_V(0, 2));
++ RR(VID_FIR_COEF_V(0, 3));
++ RR(VID_FIR_COEF_V(0, 4));
++ RR(VID_FIR_COEF_V(0, 5));
++ RR(VID_FIR_COEF_V(0, 6));
++ RR(VID_FIR_COEF_V(0, 7));
++
++ RR(VID_PRELOAD(0));
++
++ /* VID2 */
++ RR(VID_BA0(1));
++ RR(VID_BA1(1));
++ RR(VID_POSITION(1));
++ RR(VID_SIZE(1));
++ RR(VID_ATTRIBUTES(1));
++ RR(VID_FIFO_THRESHOLD(1));
++ RR(VID_ROW_INC(1));
++ RR(VID_PIXEL_INC(1));
++ RR(VID_FIR(1));
++ RR(VID_PICTURE_SIZE(1));
++ RR(VID_ACCU0(1));
++ RR(VID_ACCU1(1));
++
++ RR(VID_FIR_COEF_H(1, 0));
++ RR(VID_FIR_COEF_H(1, 1));
++ RR(VID_FIR_COEF_H(1, 2));
++ RR(VID_FIR_COEF_H(1, 3));
++ RR(VID_FIR_COEF_H(1, 4));
++ RR(VID_FIR_COEF_H(1, 5));
++ RR(VID_FIR_COEF_H(1, 6));
++ RR(VID_FIR_COEF_H(1, 7));
++
++ RR(VID_FIR_COEF_HV(1, 0));
++ RR(VID_FIR_COEF_HV(1, 1));
++ RR(VID_FIR_COEF_HV(1, 2));
++ RR(VID_FIR_COEF_HV(1, 3));
++ RR(VID_FIR_COEF_HV(1, 4));
++ RR(VID_FIR_COEF_HV(1, 5));
++ RR(VID_FIR_COEF_HV(1, 6));
++ RR(VID_FIR_COEF_HV(1, 7));
++
++ RR(VID_CONV_COEF(1, 0));
++ RR(VID_CONV_COEF(1, 1));
++ RR(VID_CONV_COEF(1, 2));
++ RR(VID_CONV_COEF(1, 3));
++ RR(VID_CONV_COEF(1, 4));
++
++ RR(VID_FIR_COEF_V(1, 0));
++ RR(VID_FIR_COEF_V(1, 1));
++ RR(VID_FIR_COEF_V(1, 2));
++ RR(VID_FIR_COEF_V(1, 3));
++ RR(VID_FIR_COEF_V(1, 4));
++ RR(VID_FIR_COEF_V(1, 5));
++ RR(VID_FIR_COEF_V(1, 6));
++ RR(VID_FIR_COEF_V(1, 7));
++
++ RR(VID_PRELOAD(1));
++
++ /* enable last, because LCD & DIGIT enable are here */
++ RR(CONTROL);
++}
++
++#undef SR
++#undef RR
++
++static inline void enable_clocks(bool enable)
++{
++ if (enable)
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++ else
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++void dispc_go(enum omap_channel channel)
++{
++ int bit;
++ unsigned long tmo;
++
++ enable_clocks(1);
++
++ if (channel == OMAP_DSS_CHANNEL_LCD)
++ bit = 0; /* LCDENABLE */
++ else
++ bit = 1; /* DIGITALENABLE */
++
++ /* if the channel is not enabled, we don't need GO */
++ if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
++ goto end;
++
++ if (channel == OMAP_DSS_CHANNEL_LCD)
++ bit = 5; /* GOLCD */
++ else
++ bit = 6; /* GODIGIT */
++
++ tmo = jiffies + msecs_to_jiffies(200);
++ while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
++ if (time_after(jiffies, tmo)) {
++ DSSERR("timeout waiting GO flag\n");
++ goto end;
++ }
++ cpu_relax();
++ }
++
++ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
++
++ REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
++end:
++ enable_clocks(0);
++}
++
++static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
++{
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
++}
++
++static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
++{
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
++}
++
++static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
++{
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
++}
++
++static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
++ int vscaleup, int five_taps)
++{
++ /* Coefficients for horizontal up-sampling */
++ static const u32 coef_hup[8] = {
++ 0x00800000,
++ 0x0D7CF800,
++ 0x1E70F5FF,
++ 0x335FF5FE,
++ 0xF74949F7,
++ 0xF55F33FB,
++ 0xF5701EFE,
++ 0xF87C0DFF,
++ };
++
++ /* Coefficients for horizontal down-sampling */
++ static const u32 coef_hdown[8] = {
++ 0x24382400,
++ 0x28371FFE,
++ 0x2C361BFB,
++ 0x303516F9,
++ 0x11343311,
++ 0x1635300C,
++ 0x1B362C08,
++ 0x1F372804,
++ };
++
++ /* Coefficients for horizontal and vertical up-sampling */
++ static const u32 coef_hvup[2][8] = {
++ {
++ 0x00800000,
++ 0x037B02FF,
++ 0x0C6F05FE,
++ 0x205907FB,
++ 0x00404000,
++ 0x075920FE,
++ 0x056F0CFF,
++ 0x027B0300,
++ },
++ {
++ 0x00800000,
++ 0x0D7CF8FF,
++ 0x1E70F5FE,
++ 0x335FF5FB,
++ 0xF7404000,
++ 0xF55F33FE,
++ 0xF5701EFF,
++ 0xF87C0D00,
++ },
++ };
++
++ /* Coefficients for horizontal and vertical down-sampling */
++ static const u32 coef_hvdown[2][8] = {
++ {
++ 0x24382400,
++ 0x28391F04,
++ 0x2D381B08,
++ 0x3237170C,
++ 0x123737F7,
++ 0x173732F9,
++ 0x1B382DFB,
++ 0x1F3928FE,
++ },
++ {
++ 0x24382400,
++ 0x28371F04,
++ 0x2C361B08,
++ 0x3035160C,
++ 0x113433F7,
++ 0x163530F9,
++ 0x1B362CFB,
++ 0x1F3728FE,
++ },
++ };
++
++ /* Coefficients for vertical up-sampling */
++ static const u32 coef_vup[8] = {
++ 0x00000000,
++ 0x0000FF00,
++ 0x0000FEFF,
++ 0x0000FBFE,
++ 0x000000F7,
++ 0x0000FEFB,
++ 0x0000FFFE,
++ 0x000000FF,
++ };
++
++
++ /* Coefficients for vertical down-sampling */
++ static const u32 coef_vdown[8] = {
++ 0x00000000,
++ 0x000004FE,
++ 0x000008FB,
++ 0x00000CF9,
++ 0x0000F711,
++ 0x0000F90C,
++ 0x0000FB08,
++ 0x0000FE04,
++ };
++
++ const u32 *h_coef;
++ const u32 *hv_coef;
++ const u32 *hv_coef_mod;
++ const u32 *v_coef;
++ int i;
++
++ if (hscaleup)
++ h_coef = coef_hup;
++ else
++ h_coef = coef_hdown;
++
++ if (vscaleup) {
++ hv_coef = coef_hvup[five_taps];
++ v_coef = coef_vup;
++
++ if (hscaleup)
++ hv_coef_mod = NULL;
++ else
++ hv_coef_mod = coef_hvdown[five_taps];
++ } else {
++ hv_coef = coef_hvdown[five_taps];
++ v_coef = coef_vdown;
++
++ if (hscaleup)
++ hv_coef_mod = coef_hvup[five_taps];
++ else
++ hv_coef_mod = NULL;
++ }
++
++ for (i = 0; i < 8; i++) {
++ u32 h, hv;
++
++ h = h_coef[i];
++
++ hv = hv_coef[i];
++
++ if (hv_coef_mod) {
++ hv &= 0xffffff00;
++ hv |= (hv_coef_mod[i] & 0xff);
++ }
++
++ _dispc_write_firh_reg(plane, i, h);
++ _dispc_write_firhv_reg(plane, i, hv);
++ }
++
++ if (!five_taps)
++ return;
++
++ for (i = 0; i < 8; i++) {
++ u32 v;
++ v = v_coef[i];
++ _dispc_write_firv_reg(plane, i, v);
++ }
++}
++
++static void _dispc_setup_color_conv_coef(void)
++{
++ const struct color_conv_coef {
++ int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
++ int full_range;
++ } ctbl_bt601_5 = {
++ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
++ };
++
++ const struct color_conv_coef *ct;
++
++#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
++
++ ct = &ctbl_bt601_5;
++
++ dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
++ dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
++ dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
++ dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
++ dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
++
++ dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
++ dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
++ dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
++ dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
++ dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
++
++#undef CVAL
++
++ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
++ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
++}
++
++
++static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
++{
++ const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
++ DISPC_VID_BA0(0),
++ DISPC_VID_BA0(1) };
++
++ dispc_write_reg(ba0_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
++{
++ const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
++ DISPC_VID_BA1(0),
++ DISPC_VID_BA1(1) };
++
++ dispc_write_reg(ba1_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
++{
++ const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
++ DISPC_VID_POSITION(0),
++ DISPC_VID_POSITION(1) };
++
++ u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
++ dispc_write_reg(pos_reg[plane], val);
++}
++
++static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
++{
++ const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
++ DISPC_VID_PICTURE_SIZE(0),
++ DISPC_VID_PICTURE_SIZE(1) };
++ u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++ dispc_write_reg(siz_reg[plane], val);
++}
++
++static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
++{
++ u32 val;
++ const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
++ DISPC_VID_SIZE(1) };
++
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++ dispc_write_reg(vsi_reg[plane-1], val);
++}
++
++static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
++{
++ const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
++ DISPC_VID_PIXEL_INC(0),
++ DISPC_VID_PIXEL_INC(1) };
++
++ dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
++{
++ const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
++ DISPC_VID_ROW_INC(0),
++ DISPC_VID_ROW_INC(1) };
++
++ dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_color_mode(enum omap_plane plane,
++ enum omap_color_mode color_mode)
++{
++ u32 m = 0;
++
++ switch (color_mode) {
++ case OMAP_DSS_COLOR_CLUT1:
++ m = 0x0; break;
++ case OMAP_DSS_COLOR_CLUT2:
++ m = 0x1; break;
++ case OMAP_DSS_COLOR_CLUT4:
++ m = 0x2; break;
++ case OMAP_DSS_COLOR_CLUT8:
++ m = 0x3; break;
++ case OMAP_DSS_COLOR_RGB12U:
++ m = 0x4; break;
++ case OMAP_DSS_COLOR_ARGB16:
++ m = 0x5; break;
++ case OMAP_DSS_COLOR_RGB16:
++ m = 0x6; break;
++ case OMAP_DSS_COLOR_RGB24U:
++ m = 0x8; break;
++ case OMAP_DSS_COLOR_RGB24P:
++ m = 0x9; break;
++ case OMAP_DSS_COLOR_YUV2:
++ m = 0xa; break;
++ case OMAP_DSS_COLOR_UYVY:
++ m = 0xb; break;
++ case OMAP_DSS_COLOR_ARGB32:
++ m = 0xc; break;
++ case OMAP_DSS_COLOR_RGBA32:
++ m = 0xd; break;
++ case OMAP_DSS_COLOR_RGBX32:
++ m = 0xe; break;
++ default:
++ BUG(); break;
++ }
++
++ REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
++}
++
++static void _dispc_set_channel_out(enum omap_plane plane,
++ enum omap_channel channel)
++{
++ int shift;
++ u32 val;
++
++ switch (plane) {
++ case OMAP_DSS_GFX:
++ shift = 8;
++ break;
++ case OMAP_DSS_VIDEO1:
++ case OMAP_DSS_VIDEO2:
++ shift = 16;
++ break;
++ default:
++ BUG();
++ return;
++ }
++
++ val = dispc_read_reg(dispc_reg_att[plane]);
++ val = FLD_MOD(val, channel, shift, shift);
++ dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_burst_size(enum omap_plane plane,
++ enum omap_burst_size burst_size)
++{
++ int shift;
++ u32 val;
++
++ enable_clocks(1);
++
++ switch (plane) {
++ case OMAP_DSS_GFX:
++ shift = 6;
++ break;
++ case OMAP_DSS_VIDEO1:
++ case OMAP_DSS_VIDEO2:
++ shift = 14;
++ break;
++ default:
++ BUG();
++ return;
++ }
++
++ val = dispc_read_reg(dispc_reg_att[plane]);
++ val = FLD_MOD(val, burst_size, shift+1, shift);
++ dispc_write_reg(dispc_reg_att[plane], val);
++
++ enable_clocks(0);
++}
++
++static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
++{
++ u32 val;
++
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ val = dispc_read_reg(dispc_reg_att[plane]);
++ val = FLD_MOD(val, enable, 9, 9);
++ dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_lcd_size(u16 width, u16 height)
++{
++ u32 val;
++ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++ enable_clocks(1);
++ dispc_write_reg(DISPC_SIZE_LCD, val);
++ enable_clocks(0);
++}
++
++void dispc_set_digit_size(u16 width, u16 height)
++{
++ u32 val;
++ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++ enable_clocks(1);
++ dispc_write_reg(DISPC_SIZE_DIG, val);
++ enable_clocks(0);
++}
++
++u32 dispc_get_plane_fifo_size(enum omap_plane plane)
++{
++ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
++ DISPC_VID_FIFO_SIZE_STATUS(0),
++ DISPC_VID_FIFO_SIZE_STATUS(1) };
++ u32 size;
++
++ enable_clocks(1);
++
++ if (cpu_is_omap24xx())
++ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
++ else if (cpu_is_omap34xx())
++ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
++ else
++ BUG();
++
++ if (cpu_is_omap34xx()) {
++ /* FIFOMERGE */
++ if (REG_GET(DISPC_CONFIG, 14, 14))
++ size *= 3;
++ }
++
++ enable_clocks(0);
++
++ return size;
++}
++
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
++{
++ const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
++ DISPC_VID_FIFO_THRESHOLD(0),
++ DISPC_VID_FIFO_THRESHOLD(1) };
++ u32 size;
++
++ enable_clocks(1);
++
++ size = dispc_get_plane_fifo_size(plane);
++
++ BUG_ON(low > size || high > size);
++
++ DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
++ plane, size,
++ REG_GET(ftrs_reg[plane], 11, 0),
++ REG_GET(ftrs_reg[plane], 27, 16),
++ low, high);
++
++ if (cpu_is_omap24xx())
++ dispc_write_reg(ftrs_reg[plane],
++ FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
++ else
++ dispc_write_reg(ftrs_reg[plane],
++ FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
++
++ enable_clocks(0);
++}
++
++void dispc_enable_fifomerge(bool enable)
++{
++ enable_clocks(1);
++
++ DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
++ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
++
++ enable_clocks(0);
++}
++
++static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
++{
++ u32 val;
++ const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
++ DISPC_VID_FIR(1) };
++
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
++ dispc_write_reg(fir_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
++{
++ u32 val;
++ const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
++ DISPC_VID_ACCU0(1) };
++
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++ dispc_write_reg(ac0_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
++{
++ u32 val;
++ const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
++ DISPC_VID_ACCU1(1) };
++
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++ dispc_write_reg(ac1_reg[plane-1], val);
++}
++
++
++static void _dispc_set_scaling(enum omap_plane plane,
++ u16 orig_width, u16 orig_height,
++ u16 out_width, u16 out_height,
++ bool ilace)
++{
++ int fir_hinc;
++ int fir_vinc;
++ int hscaleup, vscaleup, five_taps;
++ int fieldmode = 0;
++ int accu0 = 0;
++ int accu1 = 0;
++ u32 l;
++
++ BUG_ON(plane == OMAP_DSS_GFX);
++
++ hscaleup = orig_width <= out_width;
++ vscaleup = orig_height <= out_height;
++ five_taps = orig_height > out_height * 2;
++
++ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
++
++ if (!orig_width || orig_width == out_width)
++ fir_hinc = 0;
++ else
++ fir_hinc = 1024 * orig_width / out_width;
++
++ if (!orig_height || orig_height == out_height)
++ fir_vinc = 0;
++ else
++ fir_vinc = 1024 * orig_height / out_height;
++
++ _dispc_set_fir(plane, fir_hinc, fir_vinc);
++
++ l = dispc_read_reg(dispc_reg_att[plane]);
++ l &= ~((0x0f << 5) | (0x3 << 21));
++
++ l |= fir_hinc ? (1 << 5) : 0;
++ l |= fir_vinc ? (1 << 6) : 0;
++
++ l |= hscaleup ? 0 : (1 << 7);
++ l |= vscaleup ? 0 : (1 << 8);
++
++ l |= five_taps ? (1 << 21) : 0;
++ l |= five_taps ? (1 << 22) : 0;
++
++ dispc_write_reg(dispc_reg_att[plane], l);
++
++ if (ilace) {
++ if (fieldmode) {
++ accu0 = fir_vinc / 2;
++ accu1 = 0;
++ } else {
++ accu0 = 0;
++ accu1 = fir_vinc / 2;
++ if (accu1 >= 1024/2) {
++ accu0 = 1024/2;
++ accu1 -= accu0;
++ }
++ }
++ }
++
++ _dispc_set_vid_accu0(plane, 0, accu0);
++ _dispc_set_vid_accu1(plane, 0, accu1);
++}
++
++static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
++ bool mirroring, enum omap_color_mode color_mode)
++{
++ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++ color_mode == OMAP_DSS_COLOR_UYVY) {
++ int vidrot = 0;
++
++ if (mirroring) {
++ switch (rotation) {
++ case 0: vidrot = 2; break;
++ case 1: vidrot = 3; break;
++ case 2: vidrot = 0; break;
++ case 3: vidrot = 1; break;
++ }
++ } else {
++ switch (rotation) {
++ case 0: vidrot = 0; break;
++ case 1: vidrot = 1; break;
++ case 2: vidrot = 2; break;
++ case 3: vidrot = 1; break;
++ }
++ }
++
++ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
++
++ if (rotation == 1 || rotation == 3)
++ REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
++ else
++ REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
++ } else {
++ REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
++ REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
++ }
++}
++
++static int pixinc(int pixels, u8 ps)
++{
++ if (pixels == 1)
++ return 1;
++ else if (pixels > 1)
++ return 1 + (pixels - 1) * ps;
++ else if (pixels < 0)
++ return 1 - (-pixels + 1) * ps;
++ else
++ BUG();
++}
++
++static void calc_rotation_offset(u8 rotation, bool mirror,
++ u16 screen_width,
++ u16 width, u16 height,
++ enum omap_color_mode color_mode, bool fieldmode,
++ unsigned *offset0, unsigned *offset1,
++ u16 *row_inc, u16 *pix_inc)
++{
++ u8 ps;
++ u16 fbw, fbh;
++
++ switch (color_mode) {
++ case OMAP_DSS_COLOR_RGB16:
++ case OMAP_DSS_COLOR_ARGB16:
++ ps = 2;
++ break;
++
++ case OMAP_DSS_COLOR_RGB24P:
++ ps = 3;
++ break;
++
++ case OMAP_DSS_COLOR_RGB24U:
++ case OMAP_DSS_COLOR_ARGB32:
++ case OMAP_DSS_COLOR_RGBA32:
++ case OMAP_DSS_COLOR_RGBX32:
++ ps = 4;
++ break;
++
++ case OMAP_DSS_COLOR_YUV2:
++ case OMAP_DSS_COLOR_UYVY:
++ ps = 2;
++ break;
++ default:
++ BUG();
++ return;
++ }
++
++ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
++ width, height);
++
++ /* width & height are overlay sizes, convert to fb sizes */
++
++ if (rotation == 0 || rotation == 2) {
++ fbw = width;
++ fbh = height;
++ } else {
++ fbw = height;
++ fbh = width;
++ }
++
++ switch (rotation + mirror * 4) {
++ case 0:
++ *offset0 = 0;
++ if (fieldmode)
++ *offset1 = screen_width * ps;
++ else
++ *offset1 = 0;
++ *row_inc = pixinc(1 + (screen_width - fbw) +
++ (fieldmode ? screen_width : 0),
++ ps);
++ *pix_inc = pixinc(1, ps);
++ break;
++ case 1:
++ *offset0 = screen_width * (fbh - 1) * ps;
++ if (fieldmode)
++ *offset1 = *offset0 + ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
++ (fieldmode ? 1 : 0), ps);
++ *pix_inc = pixinc(-screen_width, ps);
++ break;
++ case 2:
++ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++ if (fieldmode)
++ *offset1 = *offset0 - screen_width * ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(-1 -
++ (screen_width - fbw) -
++ (fieldmode ? screen_width : 0),
++ ps);
++ *pix_inc = pixinc(-1, ps);
++ break;
++ case 3:
++ *offset0 = (fbw - 1) * ps;
++ if (fieldmode)
++ *offset1 = *offset0 - ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
++ (fieldmode ? 1 : 0), ps);
++ *pix_inc = pixinc(screen_width, ps);
++ break;
++
++ /* mirroring */
++ case 0 + 4:
++ *offset0 = (fbw - 1) * ps;
++ if (fieldmode)
++ *offset1 = *offset0 + screen_width * ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(screen_width * 2 - 1 +
++ (fieldmode ? screen_width : 0),
++ ps);
++ *pix_inc = pixinc(-1, ps);
++ break;
++
++ case 1 + 4:
++ *offset0 = 0;
++ if (fieldmode)
++ *offset1 = *offset0 + screen_width * ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
++ (fieldmode ? 1 : 0),
++ ps);
++ *pix_inc = pixinc(screen_width, ps);
++ break;
++
++ case 2 + 4:
++ *offset0 = screen_width * (fbh - 1) * ps;
++ if (fieldmode)
++ *offset1 = *offset0 + screen_width * ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(1 - screen_width * 2 -
++ (fieldmode ? screen_width : 0),
++ ps);
++ *pix_inc = pixinc(1, ps);
++ break;
++
++ case 3 + 4:
++ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++ if (fieldmode)
++ *offset1 = *offset0 + screen_width * ps;
++ else
++ *offset1 = *offset0;
++ *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
++ (fieldmode ? 1 : 0),
++ ps);
++ *pix_inc = pixinc(-screen_width, ps);
++ break;
++
++ default:
++ BUG();
++ }
++}
++
++static int _dispc_setup_plane(enum omap_plane plane,
++ enum omap_channel channel_out,
++ u32 paddr, u16 screen_width,
++ u16 pos_x, u16 pos_y,
++ u16 width, u16 height,
++ u16 out_width, u16 out_height,
++ enum omap_color_mode color_mode,
++ bool ilace,
++ u8 rotation, int mirror)
++{
++ const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
++ bool five_taps = height > out_height * 2;
++ bool fieldmode = 0;
++ int cconv;
++ unsigned offset0, offset1;
++ u16 row_inc;
++ u16 pix_inc;
++
++ if (plane == OMAP_DSS_GFX) {
++ if (width != out_width || height != out_height)
++ return -EINVAL;
++ } else {
++ /* video plane */
++ if (width > (2048 >> five_taps))
++ return -EINVAL;
++
++ if (out_width < width / maxdownscale ||
++ out_width > width * 8)
++ return -EINVAL;
++
++ if (out_height < height / maxdownscale ||
++ out_height > height * 8)
++ return -EINVAL;
++
++ switch (color_mode) {
++ case OMAP_DSS_COLOR_RGB16:
++ case OMAP_DSS_COLOR_RGB24U:
++ case OMAP_DSS_COLOR_YUV2:
++ case OMAP_DSS_COLOR_UYVY:
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ }
++
++
++ switch (color_mode) {
++ case OMAP_DSS_COLOR_RGB16:
++ case OMAP_DSS_COLOR_ARGB16:
++ case OMAP_DSS_COLOR_RGB24P:
++ case OMAP_DSS_COLOR_RGB24U:
++ case OMAP_DSS_COLOR_ARGB32:
++ case OMAP_DSS_COLOR_RGBA32:
++ case OMAP_DSS_COLOR_RGBX32:
++ cconv = 0;
++ break;
++
++ case OMAP_DSS_COLOR_YUV2:
++ case OMAP_DSS_COLOR_UYVY:
++ BUG_ON(plane == OMAP_DSS_GFX);
++ cconv = 1;
++ break;
++
++ default:
++ BUG();
++ return 1;
++ }
++
++ if (ilace && height >= out_height)
++ fieldmode = 1;
++
++ calc_rotation_offset(rotation, mirror,
++ screen_width, width, height, color_mode,
++ fieldmode,
++ &offset0, &offset1, &row_inc, &pix_inc);
++
++ DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
++ offset0, offset1, row_inc, pix_inc);
++
++ if (ilace) {
++ if (fieldmode)
++ height /= 2;
++ pos_y /= 2;
++ out_height /= 2;
++
++ DSSDBG("adjusting for ilace: height %d, pos_y %d, "
++ "out_height %d\n",
++ height, pos_y, out_height);
++ }
++
++ _dispc_set_channel_out(plane, channel_out);
++ _dispc_set_color_mode(plane, color_mode);
++
++ _dispc_set_plane_ba0(plane, paddr + offset0);
++ _dispc_set_plane_ba1(plane, paddr + offset1);
++
++ _dispc_set_row_inc(plane, row_inc);
++ _dispc_set_pix_inc(plane, pix_inc);
++
++ DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
++ out_width, out_height);
++
++ _dispc_set_plane_pos(plane, pos_x, pos_y);
++
++ _dispc_set_pic_size(plane, width, height);
++
++ if (plane != OMAP_DSS_GFX) {
++ _dispc_set_scaling(plane, width, height,
++ out_width, out_height,
++ ilace);
++ _dispc_set_vid_size(plane, out_width, out_height);
++ _dispc_set_vid_color_conv(plane, cconv);
++ }
++
++ _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
++
++ return 0;
++}
++
++static void _dispc_enable_plane(enum omap_plane plane, bool enable)
++{
++ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
++}
++
++static void dispc_disable_isr(void *data, u32 mask)
++{
++ struct completion *compl = data;
++ complete(compl);
++}
++
++static void _enable_lcd_out(bool enable)
++{
++ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
++}
++
++void dispc_enable_lcd_out(bool enable)
++{
++ struct completion frame_done_completion;
++ bool is_on;
++ int r;
++
++ enable_clocks(1);
++
++ /* When we disable LCD output, we need to wait until frame is done.
++ * Otherwise the DSS is still working, and turning off the clocks
++ * prevents DSS from going to OFF mode */
++ is_on = REG_GET(DISPC_CONTROL, 0, 0);
++
++ if (!enable && is_on) {
++ init_completion(&frame_done_completion);
++
++ r = omap_dispc_register_isr(dispc_disable_isr,
++ &frame_done_completion,
++ DISPC_IRQ_FRAMEDONE);
++
++ if (r)
++ DSSERR("failed to register FRAMEDONE isr\n");
++ }
++
++ _enable_lcd_out(enable);
++
++ if (!enable && is_on) {
++ if (!wait_for_completion_timeout(&frame_done_completion,
++ msecs_to_jiffies(100)))
++ DSSERR("timeout waiting for FRAME DONE\n");
++
++ r = omap_dispc_unregister_isr(dispc_disable_isr,
++ &frame_done_completion,
++ DISPC_IRQ_FRAMEDONE);
++
++ if (r)
++ DSSERR("failed to unregister FRAMEDONE isr\n");
++ }
++
++ enable_clocks(0);
++}
++
++static void _enable_digit_out(bool enable)
++{
++ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
++}
++
++void dispc_enable_digit_out(bool enable)
++{
++ struct completion frame_done_completion;
++ int r;
++
++ enable_clocks(1);
++
++ if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
++ enable_clocks(0);
++ return;
++ }
++
++ if (enable) {
++ /* When we enable digit output, we'll get an extra digit
++ * sync lost interrupt, that we need to ignore */
++ dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
++ omap_dispc_set_irqs();
++ }
++
++ /* When we disable digit output, we need to wait until fields are done.
++ * Otherwise the DSS is still working, and turning off the clocks
++ * prevents DSS from going to OFF mode. And when enabling, we need to
++ * wait for the extra sync losts */
++ init_completion(&frame_done_completion);
++
++ r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
++ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
++ if (r)
++ DSSERR("failed to register EVSYNC isr\n");
++
++ _enable_digit_out(enable);
++
++ /* XXX I understand from TRM that we should only wait for the
++ * current field to complete. But it seems we have to wait
++ * for both fields */
++ if (!wait_for_completion_timeout(&frame_done_completion,
++ msecs_to_jiffies(100)))
++ DSSERR("timeout waiting for EVSYNC\n");
++
++ if (!wait_for_completion_timeout(&frame_done_completion,
++ msecs_to_jiffies(100)))
++ DSSERR("timeout waiting for EVSYNC\n");
++
++ r = omap_dispc_unregister_isr(dispc_disable_isr,
++ &frame_done_completion,
++ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
++ if (r)
++ DSSERR("failed to unregister EVSYNC isr\n");
++
++ if (enable) {
++ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
++ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
++ omap_dispc_set_irqs();
++ }
++
++ enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal_polarity(bool act_high)
++{
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
++ enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal(bool enable)
++{
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
++ enable_clocks(0);
++}
++
++void dispc_pck_free_enable(bool enable)
++{
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
++ enable_clocks(0);
++}
++
++void dispc_enable_fifohandcheck(bool enable)
++{
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
++ enable_clocks(0);
++}
++
++
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
++{
++ int mode;
++
++ switch (type) {
++ case OMAP_DSS_LCD_DISPLAY_STN:
++ mode = 0;
++ break;
++
++ case OMAP_DSS_LCD_DISPLAY_TFT:
++ mode = 1;
++ break;
++
++ default:
++ BUG();
++ return;
++ }
++
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
++ enable_clocks(0);
++}
++
++void dispc_set_loadmode(enum omap_dss_load_mode mode)
++{
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
++ enable_clocks(0);
++}
++
++
++void dispc_set_default_color(enum omap_channel channel, u32 color)
++{
++ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
++ DISPC_DEFAULT_COLOR1 };
++
++ enable_clocks(1);
++ dispc_write_reg(def_reg[channel], color);
++ enable_clocks(0);
++}
++
++void dispc_set_trans_key(enum omap_channel ch,
++ enum omap_dss_color_key_type type,
++ u32 trans_key)
++{
++ const struct dispc_reg tr_reg[] = {
++ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
++
++ enable_clocks(1);
++ if (ch == OMAP_DSS_CHANNEL_LCD)
++ REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
++ else /* OMAP_DSS_CHANNEL_DIGIT */
++ REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
++
++ dispc_write_reg(tr_reg[ch], trans_key);
++ enable_clocks(0);
++}
++
++void dispc_enable_trans_key(enum omap_channel ch, bool enable)
++{
++ enable_clocks(1);
++ if (ch == OMAP_DSS_CHANNEL_LCD)
++ REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
++ else /* OMAP_DSS_CHANNEL_DIGIT */
++ REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
++ enable_clocks(0);
++}
++
++void dispc_set_tft_data_lines(u8 data_lines)
++{
++ int code;
++
++ switch (data_lines) {
++ case 12:
++ code = 0;
++ break;
++ case 16:
++ code = 1;
++ break;
++ case 18:
++ code = 2;
++ break;
++ case 24:
++ code = 3;
++ break;
++ default:
++ BUG();
++ return;
++ }
++
++ enable_clocks(1);
++ REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
++ enable_clocks(0);
++}
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
++{
++ u32 l;
++ int stallmode;
++ int gpout0 = 1;
++ int gpout1;
++
++ switch (mode) {
++ case OMAP_DSS_PARALLELMODE_BYPASS:
++ stallmode = 0;
++ gpout1 = 1;
++ break;
++
++ case OMAP_DSS_PARALLELMODE_RFBI:
++ stallmode = 1;
++ gpout1 = 0;
++ break;
++
++ case OMAP_DSS_PARALLELMODE_DSI:
++ stallmode = 1;
++ gpout1 = 1;
++ break;
++
++ default:
++ BUG();
++ return;
++ }
++
++ enable_clocks(1);
++
++ l = dispc_read_reg(DISPC_CONTROL);
++
++ l = FLD_MOD(l, stallmode, 11, 11);
++ l = FLD_MOD(l, gpout0, 15, 15);
++ l = FLD_MOD(l, gpout1, 16, 16);
++
++ dispc_write_reg(DISPC_CONTROL, l);
++
++ enable_clocks(0);
++}
++
++static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
++ int vsw, int vfp, int vbp)
++{
++ u32 timing_h, timing_v;
++
++ BUG_ON(hsw < 1 || hsw > 64);
++ BUG_ON(hfp < 1 || hfp > 256);
++ BUG_ON(hbp < 1 || hbp > 256);
++
++ BUG_ON(vsw < 1 || vsw > 64);
++ BUG_ON(vfp < 0 || vfp > 255);
++ BUG_ON(vbp < 0 || vbp > 255);
++
++ timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
++ FLD_VAL(hbp-1, 27, 20);
++
++ timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
++ FLD_VAL(vbp, 27, 20);
++
++ enable_clocks(1);
++ dispc_write_reg(DISPC_TIMING_H, timing_h);
++ dispc_write_reg(DISPC_TIMING_V, timing_v);
++ enable_clocks(0);
++}
++
++/* change name to mode? */
++void dispc_set_lcd_timings(struct omap_video_timings *timings)
++{
++ unsigned xtot, ytot;
++ unsigned long ht, vt;
++
++ _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
++ timings->vsw, timings->vfp, timings->vbp);
++
++ dispc_set_lcd_size(timings->x_res, timings->y_res);
++
++ xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
++ ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
++
++ ht = (timings->pixel_clock * 1000) / xtot;
++ vt = (timings->pixel_clock * 1000) / xtot / ytot;
++
++ DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
++ DSSDBG("pck %u\n", timings->pixel_clock);
++ DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
++ timings->hsw, timings->hfp, timings->hbp,
++ timings->vsw, timings->vfp, timings->vbp);
++
++ DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
++}
++
++void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
++{
++ BUG_ON(lck_div < 1);
++ BUG_ON(pck_div < 2);
++
++ enable_clocks(1);
++ dispc_write_reg(DISPC_DIVISOR,
++ FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
++ enable_clocks(0);
++}
++
++static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
++{
++ u32 l;
++ l = dispc_read_reg(DISPC_DIVISOR);
++ *lck_div = FLD_GET(l, 23, 16);
++ *pck_div = FLD_GET(l, 7, 0);
++}
++
++unsigned long dispc_fclk_rate(void)
++{
++ unsigned long r = 0;
++
++ if (dss_get_dispc_clk_source() == 0)
++ r = dss_clk_get_rate(DSS_CLK_FCK1);
++ else
++#ifdef CONFIG_OMAP2_DSS_DSI
++ r = dsi_get_dsi1_pll_rate();
++#else
++ BUG();
++#endif
++ return r;
++}
++
++unsigned long dispc_pclk_rate(void)
++{
++ int lcd, pcd;
++ unsigned long r;
++ u32 l;
++
++ l = dispc_read_reg(DISPC_DIVISOR);
++
++ lcd = FLD_GET(l, 23, 16);
++ pcd = FLD_GET(l, 7, 0);
++
++ r = dispc_fclk_rate();
++
++ return r / lcd / pcd;
++}
++
++void dispc_dump_clocks(struct seq_file *s)
++{
++ int lcd, pcd;
++
++ enable_clocks(1);
++
++ dispc_get_lcd_divisor(&lcd, &pcd);
++
++ seq_printf(s, "- dispc -\n");
++
++ seq_printf(s, "dispc fclk source = %s\n",
++ dss_get_dispc_clk_source() == 0 ?
++ "dss1_alwon_fclk" : "dsi1_pll_fclk");
++
++ seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
++ dispc_fclk_rate(),
++ lcd, pcd,
++ dispc_pclk_rate());
++
++ enable_clocks(0);
++}
++
++void dispc_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
++
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ DUMPREG(DISPC_REVISION);
++ DUMPREG(DISPC_SYSCONFIG);
++ DUMPREG(DISPC_SYSSTATUS);
++ DUMPREG(DISPC_IRQSTATUS);
++ DUMPREG(DISPC_IRQENABLE);
++ DUMPREG(DISPC_CONTROL);
++ DUMPREG(DISPC_CONFIG);
++ DUMPREG(DISPC_CAPABLE);
++ DUMPREG(DISPC_DEFAULT_COLOR0);
++ DUMPREG(DISPC_DEFAULT_COLOR1);
++ DUMPREG(DISPC_TRANS_COLOR0);
++ DUMPREG(DISPC_TRANS_COLOR1);
++ DUMPREG(DISPC_LINE_STATUS);
++ DUMPREG(DISPC_LINE_NUMBER);
++ DUMPREG(DISPC_TIMING_H);
++ DUMPREG(DISPC_TIMING_V);
++ DUMPREG(DISPC_POL_FREQ);
++ DUMPREG(DISPC_DIVISOR);
++ DUMPREG(DISPC_GLOBAL_ALPHA);
++ DUMPREG(DISPC_SIZE_DIG);
++ DUMPREG(DISPC_SIZE_LCD);
++
++ DUMPREG(DISPC_GFX_BA0);
++ DUMPREG(DISPC_GFX_BA1);
++ DUMPREG(DISPC_GFX_POSITION);
++ DUMPREG(DISPC_GFX_SIZE);
++ DUMPREG(DISPC_GFX_ATTRIBUTES);
++ DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
++ DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
++ DUMPREG(DISPC_GFX_ROW_INC);
++ DUMPREG(DISPC_GFX_PIXEL_INC);
++ DUMPREG(DISPC_GFX_WINDOW_SKIP);
++ DUMPREG(DISPC_GFX_TABLE_BA);
++
++ DUMPREG(DISPC_DATA_CYCLE1);
++ DUMPREG(DISPC_DATA_CYCLE2);
++ DUMPREG(DISPC_DATA_CYCLE3);
++
++ DUMPREG(DISPC_CPR_COEF_R);
++ DUMPREG(DISPC_CPR_COEF_G);
++ DUMPREG(DISPC_CPR_COEF_B);
++
++ DUMPREG(DISPC_GFX_PRELOAD);
++
++ DUMPREG(DISPC_VID_BA0(0));
++ DUMPREG(DISPC_VID_BA1(0));
++ DUMPREG(DISPC_VID_POSITION(0));
++ DUMPREG(DISPC_VID_SIZE(0));
++ DUMPREG(DISPC_VID_ATTRIBUTES(0));
++ DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
++ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
++ DUMPREG(DISPC_VID_ROW_INC(0));
++ DUMPREG(DISPC_VID_PIXEL_INC(0));
++ DUMPREG(DISPC_VID_FIR(0));
++ DUMPREG(DISPC_VID_PICTURE_SIZE(0));
++ DUMPREG(DISPC_VID_ACCU0(0));
++ DUMPREG(DISPC_VID_ACCU1(0));
++
++ DUMPREG(DISPC_VID_BA0(1));
++ DUMPREG(DISPC_VID_BA1(1));
++ DUMPREG(DISPC_VID_POSITION(1));
++ DUMPREG(DISPC_VID_SIZE(1));
++ DUMPREG(DISPC_VID_ATTRIBUTES(1));
++ DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
++ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
++ DUMPREG(DISPC_VID_ROW_INC(1));
++ DUMPREG(DISPC_VID_PIXEL_INC(1));
++ DUMPREG(DISPC_VID_FIR(1));
++ DUMPREG(DISPC_VID_PICTURE_SIZE(1));
++ DUMPREG(DISPC_VID_ACCU0(1));
++ DUMPREG(DISPC_VID_ACCU1(1));
++
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
++ DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
++ DUMPREG(DISPC_VID_CONV_COEF(0, 0));
++ DUMPREG(DISPC_VID_CONV_COEF(0, 1));
++ DUMPREG(DISPC_VID_CONV_COEF(0, 2));
++ DUMPREG(DISPC_VID_CONV_COEF(0, 3));
++ DUMPREG(DISPC_VID_CONV_COEF(0, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
++ DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
++
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
++ DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
++ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
++ DUMPREG(DISPC_VID_CONV_COEF(1, 0));
++ DUMPREG(DISPC_VID_CONV_COEF(1, 1));
++ DUMPREG(DISPC_VID_CONV_COEF(1, 2));
++ DUMPREG(DISPC_VID_CONV_COEF(1, 3));
++ DUMPREG(DISPC_VID_CONV_COEF(1, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
++ DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
++
++ DUMPREG(DISPC_VID_PRELOAD(0));
++ DUMPREG(DISPC_VID_PRELOAD(1));
++
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
++ bool ihs, bool ivs, u8 acbi, u8 acb)
++{
++ u32 l = 0;
++
++ DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
++ onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
++
++ l |= FLD_VAL(onoff, 17, 17);
++ l |= FLD_VAL(rf, 16, 16);
++ l |= FLD_VAL(ieo, 15, 15);
++ l |= FLD_VAL(ipc, 14, 14);
++ l |= FLD_VAL(ihs, 13, 13);
++ l |= FLD_VAL(ivs, 12, 12);
++ l |= FLD_VAL(acbi, 11, 8);
++ l |= FLD_VAL(acb, 7, 0);
++
++ enable_clocks(1);
++ dispc_write_reg(DISPC_POL_FREQ, l);
++ enable_clocks(0);
++}
++
++void dispc_set_pol_freq(struct omap_panel *panel)
++{
++ _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
++ (panel->config & OMAP_DSS_LCD_RF) != 0,
++ (panel->config & OMAP_DSS_LCD_IEO) != 0,
++ (panel->config & OMAP_DSS_LCD_IPC) != 0,
++ (panel->config & OMAP_DSS_LCD_IHS) != 0,
++ (panel->config & OMAP_DSS_LCD_IVS) != 0,
++ panel->acbi, panel->acb);
++}
++
++void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
++ u16 *lck_div, u16 *pck_div)
++{
++ u16 pcd_min = is_tft ? 2 : 3;
++ unsigned long best_pck;
++ u16 best_ld, cur_ld;
++ u16 best_pd, cur_pd;
++
++ best_pck = 0;
++ best_ld = 0;
++ best_pd = 0;
++
++ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
++ unsigned long lck = fck / cur_ld;
++
++ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
++ unsigned long pck = lck / cur_pd;
++ long old_delta = abs(best_pck - req_pck);
++ long new_delta = abs(pck - req_pck);
++
++ if (best_pck == 0 || new_delta < old_delta) {
++ best_pck = pck;
++ best_ld = cur_ld;
++ best_pd = cur_pd;
++
++ if (pck == req_pck)
++ goto found;
++ }
++
++ if (pck < req_pck)
++ break;
++ }
++
++ if (lck / pcd_min < req_pck)
++ break;
++ }
++
++found:
++ *lck_div = best_ld;
++ *pck_div = best_pd;
++}
++
++int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
++ struct dispc_clock_info *cinfo)
++{
++ unsigned long prate;
++ struct dispc_clock_info cur, best;
++ int match = 0;
++ int min_fck_per_pck;
++ unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
++
++ if (cpu_is_omap34xx())
++ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++ else
++ prate = 0;
++
++ if (req_pck == dispc.cache_req_pck &&
++ ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
++ dispc.cache_cinfo.fck == fck_rate)) {
++ DSSDBG("dispc clock info found from cache.\n");
++ *cinfo = dispc.cache_cinfo;
++ return 0;
++ }
++
++ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++ if (min_fck_per_pck &&
++ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++ DSSERR("Requested pixel clock not possible with the current "
++ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++ "the constraint off.\n");
++ min_fck_per_pck = 0;
++ }
++
++retry:
++ memset(&cur, 0, sizeof(cur));
++ memset(&best, 0, sizeof(best));
++
++ if (cpu_is_omap24xx()) {
++ /* XXX can we change the clock on omap2? */
++ cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
++ cur.fck_div = 1;
++
++ match = 1;
++
++ find_lck_pck_divs(is_tft, req_pck, cur.fck,
++ &cur.lck_div, &cur.pck_div);
++
++ cur.lck = cur.fck / cur.lck_div;
++ cur.pck = cur.lck / cur.pck_div;
++
++ best = cur;
++
++ goto found;
++ } else if (cpu_is_omap34xx()) {
++ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
++ cur.fck = prate / cur.fck_div * 2;
++
++ if (cur.fck > DISPC_MAX_FCK)
++ continue;
++
++ if (min_fck_per_pck &&
++ cur.fck < req_pck * min_fck_per_pck)
++ continue;
++
++ match = 1;
++
++ find_lck_pck_divs(is_tft, req_pck, cur.fck,
++ &cur.lck_div, &cur.pck_div);
++
++ cur.lck = cur.fck / cur.lck_div;
++ cur.pck = cur.lck / cur.pck_div;
++
++ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
++ best = cur;
++
++ if (cur.pck == req_pck)
++ goto found;
++ }
++ }
++ } else {
++ BUG();
++ }
++
++found:
++ if (!match) {
++ if (min_fck_per_pck) {
++ DSSERR("Could not find suitable clock settings.\n"
++ "Turning FCK/PCK constraint off and"
++ "trying again.\n");
++ min_fck_per_pck = 0;
++ goto retry;
++ }
++
++ DSSERR("Could not find suitable clock settings.\n");
++
++ return -EINVAL;
++ }
++
++ if (cinfo)
++ *cinfo = best;
++
++ dispc.cache_req_pck = req_pck;
++ dispc.cache_prate = prate;
++ dispc.cache_cinfo = best;
++
++ return 0;
++}
++
++int dispc_set_clock_div(struct dispc_clock_info *cinfo)
++{
++ unsigned long prate;
++ int r;
++
++ if (cpu_is_omap34xx()) {
++ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++ DSSDBG("dpll4_m4 = %ld\n", prate);
++ }
++
++ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
++ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
++ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
++
++ if (cpu_is_omap34xx()) {
++ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
++ if (r)
++ return r;
++ }
++
++ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
++
++ return 0;
++}
++
++int dispc_get_clock_div(struct dispc_clock_info *cinfo)
++{
++ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
++
++ if (cpu_is_omap34xx()) {
++ unsigned long prate;
++ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++ cinfo->fck_div = prate / (cinfo->fck / 2);
++ } else {
++ cinfo->fck_div = 0;
++ }
++
++ cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
++ cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
++
++ cinfo->lck = cinfo->fck / cinfo->lck_div;
++ cinfo->pck = cinfo->lck / cinfo->pck_div;
++
++ return 0;
++}
++
++static void omap_dispc_set_irqs(void)
++{
++ unsigned long flags;
++ u32 mask = dispc.irq_error_mask | DISPC_IRQ_WAKEUP;
++ int i;
++ struct omap_dispc_isr_data *isr_data;
++
++ spin_lock_irqsave(&dispc.irq_lock, flags);
++
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ isr_data = &dispc.registered_isr[i];
++
++ if (isr_data->isr == NULL)
++ continue;
++
++ mask |= isr_data->mask;
++ }
++
++ enable_clocks(1);
++ dispc_write_reg(DISPC_IRQENABLE, mask);
++ enable_clocks(0);
++
++ spin_unlock_irqrestore(&dispc.irq_lock, flags);
++}
++
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++ int i;
++ int ret;
++ unsigned long flags;
++ struct omap_dispc_isr_data *isr_data;
++
++ if (isr == NULL)
++ return -EINVAL;
++
++ spin_lock_irqsave(&dispc.irq_lock, flags);
++
++ /* check for duplicate entry */
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ isr_data = &dispc.registered_isr[i];
++ if (isr_data->isr == isr && isr_data->arg == arg &&
++ isr_data->mask == mask) {
++ ret = -EINVAL;
++ goto err;
++ }
++ }
++
++ isr_data = NULL;
++ ret = -EBUSY;
++
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ isr_data = &dispc.registered_isr[i];
++
++ if (isr_data->isr != NULL)
++ continue;
++
++ isr_data->isr = isr;
++ isr_data->arg = arg;
++ isr_data->mask = mask;
++ ret = 0;
++
++ break;
++ }
++err:
++ spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++ if (ret == 0)
++ omap_dispc_set_irqs();
++
++ return ret;
++}
++EXPORT_SYMBOL(omap_dispc_register_isr);
++
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++ int i;
++ unsigned long flags;
++ int ret = -EINVAL;
++ struct omap_dispc_isr_data *isr_data;
++
++ spin_lock_irqsave(&dispc.irq_lock, flags);
++
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ isr_data = &dispc.registered_isr[i];
++ if (isr_data->isr != isr || isr_data->arg != arg ||
++ isr_data->mask != mask)
++ continue;
++
++ /* found the correct isr */
++
++ isr_data->isr = NULL;
++ isr_data->arg = NULL;
++ isr_data->mask = 0;
++
++ ret = 0;
++ break;
++ }
++
++ spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++ if (ret == 0)
++ omap_dispc_set_irqs();
++
++ return ret;
++}
++EXPORT_SYMBOL(omap_dispc_unregister_isr);
++
++#ifdef DEBUG
++static void print_irq_status(u32 status)
++{
++ if ((status & dispc.irq_error_mask) == 0)
++ return;
++
++ printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++ if (status & DISPC_IRQ_##x) \
++ printk(#x " ");
++ PIS(GFX_FIFO_UNDERFLOW);
++ PIS(OCP_ERR);
++ PIS(VID1_FIFO_UNDERFLOW);
++ PIS(VID2_FIFO_UNDERFLOW);
++ PIS(SYNC_LOST);
++ PIS(SYNC_LOST_DIGIT);
++#undef PIS
++
++ printk("\n");
++}
++#endif
++
++/* Called from dss.c. Note that we don't touch clocks here,
++ * but we presume they are on because we got an IRQ. However,
++ * an irq handler may turn the clocks off, so we may not have
++ * clock later in the function. */
++void dispc_irq_handler(void)
++{
++ int i;
++ u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
++ static int errors;
++ u32 handledirqs = 0;
++ struct omap_dispc_isr_data *isr_data;
++
++#ifdef DEBUG
++ if (dss_debug)
++ print_irq_status(irqstatus);
++#endif
++ /* Ack the interrupt. Do it here before clocks are possibly turned
++ * off */
++ dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
++
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ isr_data = &dispc.registered_isr[i];
++
++ if (!isr_data->isr)
++ continue;
++
++ if (isr_data->mask & irqstatus) {
++ isr_data->isr(isr_data->arg, irqstatus);
++ handledirqs |= isr_data->mask;
++ }
++ }
++
++ if (irqstatus & ~handledirqs & dispc.irq_error_mask) {
++ if (printk_ratelimit()) {
++ DSSERR("dispc irq error status %04x\n",
++ irqstatus);
++ }
++ if (errors++ > 100) {
++ DSSERR("Excessive DISPC errors\n"
++ "Turning off lcd and digit\n");
++ _enable_lcd_out(0);
++ _enable_digit_out(0);
++ }
++ }
++
++}
++
++int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
++{
++ void dispc_irq_wait_handler(void *data, u32 mask)
++ {
++ complete((struct completion *)data);
++ }
++
++ int r;
++ DECLARE_COMPLETION_ONSTACK(completion);
++
++ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
++ irqmask);
++
++ if (r)
++ return r;
++
++ timeout = wait_for_completion_timeout(&completion, timeout);
++
++ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
++
++ if (timeout == 0)
++ return -ETIMEDOUT;
++
++ if (timeout == -ERESTARTSYS)
++ return -ERESTARTSYS;
++
++ return 0;
++}
++
++int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
++ unsigned long timeout)
++{
++ void dispc_irq_wait_handler(void *data, u32 mask)
++ {
++ complete((struct completion *)data);
++ }
++
++ int r;
++ DECLARE_COMPLETION_ONSTACK(completion);
++
++ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
++ irqmask);
++
++ if (r)
++ return r;
++
++ timeout = wait_for_completion_interruptible_timeout(&completion,
++ timeout);
++
++ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
++
++ if (timeout == 0)
++ return -ETIMEDOUT;
++
++ if (timeout == -ERESTARTSYS)
++ return -ERESTARTSYS;
++
++ return 0;
++}
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++void dispc_fake_vsync_irq(void)
++{
++ u32 irqstatus = DISPC_IRQ_VSYNC;
++ int i;
++
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ struct omap_dispc_isr_data *isr_data;
++ isr_data = &dispc.registered_isr[i];
++
++ if (!isr_data->isr)
++ continue;
++
++ if (isr_data->mask & irqstatus)
++ isr_data->isr(isr_data->arg, irqstatus);
++ }
++}
++#endif
++
++static void _omap_dispc_initialize_irq(void)
++{
++ memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
++
++ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
++
++ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
++ * so clear it */
++ dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
++
++ omap_dispc_set_irqs();
++}
++
++static void _omap_dispc_initial_config(void)
++{
++ u32 l;
++
++ l = dispc_read_reg(DISPC_SYSCONFIG);
++ l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
++ l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
++ l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
++ l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
++ dispc_write_reg(DISPC_SYSCONFIG, l);
++
++ /* FUNCGATED */
++ REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
++
++ /* L3 firewall setting: enable access to OCM RAM */
++ if (cpu_is_omap24xx())
++ __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
++
++ _dispc_setup_color_conv_coef();
++
++ dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
++}
++
++int dispc_init(void)
++{
++ u32 rev;
++
++ spin_lock_init(&dispc.irq_lock);
++
++ dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
++ if (!dispc.base) {
++ DSSERR("can't ioremap DISPC\n");
++ return -ENOMEM;
++ }
++
++ if (cpu_is_omap34xx()) {
++ dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
++ if (IS_ERR(dispc.dpll4_m4_ck)) {
++ DSSERR("Failed to get dpll4_m4_ck\n");
++ return -ENODEV;
++ }
++ }
++
++ enable_clocks(1);
++
++ _omap_dispc_initial_config();
++
++ _omap_dispc_initialize_irq();
++
++ dispc_save_context();
++
++ rev = dispc_read_reg(DISPC_REVISION);
++ printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
++ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++ enable_clocks(0);
++
++ return 0;
++}
++
++void dispc_exit(void)
++{
++ if (cpu_is_omap34xx())
++ clk_put(dispc.dpll4_m4_ck);
++ iounmap(dispc.base);
++}
++
++int dispc_enable_plane(enum omap_plane plane, bool enable)
++{
++ DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
++
++ enable_clocks(1);
++ _dispc_enable_plane(plane, enable);
++ enable_clocks(0);
++
++ return 0;
++}
++
++int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
++ u32 paddr, u16 screen_width,
++ u16 pos_x, u16 pos_y,
++ u16 width, u16 height,
++ u16 out_width, u16 out_height,
++ enum omap_color_mode color_mode,
++ bool ilace,
++ u8 rotation, bool mirror)
++{
++ int r = 0;
++
++ DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
++ "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
++ plane, channel_out, paddr, screen_width, pos_x, pos_y,
++ width, height,
++ out_width, out_height,
++ ilace, color_mode,
++ rotation, mirror);
++
++ enable_clocks(1);
++
++ r = _dispc_setup_plane(plane, channel_out,
++ paddr, screen_width,
++ pos_x, pos_y,
++ width, height,
++ out_width, out_height,
++ color_mode, ilace,
++ rotation, mirror);
++
++ enable_clocks(0);
++
++ return r;
++}
++
++static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
++ int x2, int y2, int w2, int h2)
++{
++ if (x1 >= (x2+w2))
++ return 0;
++
++ if ((x1+w1) <= x2)
++ return 0;
++
++ if (y1 >= (y2+h2))
++ return 0;
++
++ if ((y1+h1) <= y2)
++ return 0;
++
++ return 1;
++}
++
++static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
++{
++ if (pi->width != pi->out_width)
++ return 1;
++
++ if (pi->height != pi->out_height)
++ return 1;
++
++ return 0;
++}
++
++/* returns the area that needs updating */
++void dispc_setup_partial_planes(struct omap_display *display,
++ u16 *xi, u16 *yi, u16 *wi, u16 *hi)
++{
++ struct omap_overlay_manager *mgr;
++ int i;
++
++ int x, y, w, h;
++
++ x = *xi;
++ y = *yi;
++ w = *wi;
++ h = *hi;
++
++ DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
++ *xi, *yi, *wi, *hi);
++
++
++ mgr = display->manager;
++
++ if (!mgr) {
++ DSSDBG("no manager\n");
++ return;
++ }
++
++ for (i = 0; i < mgr->num_overlays; i++) {
++ struct omap_overlay *ovl;
++ struct omap_overlay_info *pi;
++ ovl = mgr->overlays[i];
++
++ if (ovl->manager != mgr)
++ continue;
++
++ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
++ continue;
++
++ pi = &ovl->info;
++
++ if (!pi->enabled)
++ continue;
++ /*
++ * If the plane is intersecting and scaled, we
++ * enlarge the update region to accomodate the
++ * whole area
++ */
++
++ if (dispc_is_intersecting(x, y, w, h,
++ pi->pos_x, pi->pos_y,
++ pi->out_width, pi->out_height)) {
++ if (dispc_is_overlay_scaled(pi)) {
++
++ int x1, y1, x2, y2;
++
++ if (x > pi->pos_x)
++ x1 = pi->pos_x;
++ else
++ x1 = x;
++
++ if (y > pi->pos_y)
++ y1 = pi->pos_y;
++ else
++ y1 = y;
++
++ if ((x + w) < (pi->pos_x + pi->out_width))
++ x2 = pi->pos_x + pi->out_width;
++ else
++ x2 = x + w;
++
++ if ((y + h) < (pi->pos_y + pi->out_height))
++ y2 = pi->pos_y + pi->out_height;
++ else
++ y2 = y + h;
++
++ x = x1;
++ y = y1;
++ w = x2 - x1;
++ h = y2 - y1;
++
++ DSSDBG("Update area after enlarge due to "
++ "scaling %d, %d %dx%d\n",
++ x, y, w, h);
++ }
++ }
++ }
++
++ for (i = 0; i < mgr->num_overlays; i++) {
++ struct omap_overlay *ovl = mgr->overlays[i];
++ struct omap_overlay_info *pi = &ovl->info;
++
++ int px = pi->pos_x;
++ int py = pi->pos_y;
++ int pw = pi->width;
++ int ph = pi->height;
++ int pow = pi->out_width;
++ int poh = pi->out_height;
++ u32 pa = pi->paddr;
++ int psw = pi->screen_width;
++ int bpp;
++
++ if (ovl->manager != mgr)
++ continue;
++
++ /*
++ * If plane is not enabled or the update region
++ * does not intersect with the plane in question,
++ * we really disable the plane from hardware
++ */
++
++ if (!pi->enabled ||
++ !dispc_is_intersecting(x, y, w, h,
++ px, py, pow, poh)) {
++ dispc_enable_plane(ovl->id, 0);
++ continue;
++ }
++
++ switch (pi->color_mode) {
++ case OMAP_DSS_COLOR_RGB16:
++ case OMAP_DSS_COLOR_ARGB16:
++ case OMAP_DSS_COLOR_YUV2:
++ case OMAP_DSS_COLOR_UYVY:
++ bpp = 16;
++ break;
++
++ case OMAP_DSS_COLOR_RGB24P:
++ bpp = 24;
++ break;
++
++ case OMAP_DSS_COLOR_RGB24U:
++ case OMAP_DSS_COLOR_ARGB32:
++ case OMAP_DSS_COLOR_RGBA32:
++ case OMAP_DSS_COLOR_RGBX32:
++ bpp = 32;
++ break;
++
++ default:
++ BUG();
++ return;
++ }
++
++ if (x > pi->pos_x) {
++ px = 0;
++ pw -= (x - pi->pos_x);
++ pa += (x - pi->pos_x) * bpp / 8;
++ } else {
++ px = pi->pos_x - x;
++ }
++
++ if (y > pi->pos_y) {
++ py = 0;
++ ph -= (y - pi->pos_y);
++ pa += (y - pi->pos_y) * psw * bpp / 8;
++ } else {
++ py = pi->pos_y - y;
++ }
++
++ if (w < (px+pw))
++ pw -= (px+pw) - (w);
++
++ if (h < (py+ph))
++ ph -= (py+ph) - (h);
++
++ /* Can't scale the GFX plane */
++ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
++ dispc_is_overlay_scaled(pi) == 0) {
++ pow = pw;
++ poh = ph;
++ }
++
++ DSSDBG("calc plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
++ ovl->id, pa, psw, px, py, pw, ph, pow, poh);
++
++ dispc_setup_plane(ovl->id, mgr->id,
++ pa, psw,
++ px, py,
++ pw, ph,
++ pow, poh,
++ pi->color_mode, 0,
++ pi->rotation, // XXX rotation probably wrong
++ pi->mirror);
++
++ dispc_enable_plane(ovl->id, 1);
++ }
++
++ *xi = x;
++ *yi = y;
++ *wi = w;
++ *hi = h;
++
++}
++
+diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
+new file mode 100644
+index 0000000..1a55010
+--- /dev/null
++++ b/drivers/video/omap2/dss/display.c
+@@ -0,0 +1,687 @@
++/*
++ * linux/drivers/video/omap2/dss/display.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPLAY"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/jiffies.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++#include "dss.h"
++
++static int num_displays;
++static LIST_HEAD(display_list);
++
++static ssize_t display_name_show(struct omap_display *display, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%s\n", display->name);
++}
++
++static ssize_t display_enabled_show(struct omap_display *display, char *buf)
++{
++ bool enabled = display->state != OMAP_DSS_DISPLAY_DISABLED;
++
++ return snprintf(buf, PAGE_SIZE, "%d\n", enabled);
++}
++
++static ssize_t display_enabled_store(struct omap_display *display,
++ const char *buf, size_t size)
++{
++ bool enabled, r;
++
++ enabled = simple_strtoul(buf, NULL, 10);
++
++ if (enabled != (display->state != OMAP_DSS_DISPLAY_DISABLED)) {
++ if (enabled) {
++ r = display->enable(display);
++ if (r)
++ return r;
++ } else {
++ display->disable(display);
++ }
++ }
++
++ return size;
++}
++
++static ssize_t display_upd_mode_show(struct omap_display *display, char *buf)
++{
++ enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO;
++ if (display->get_update_mode)
++ mode = display->get_update_mode(display);
++ return snprintf(buf, PAGE_SIZE, "%d\n", mode);
++}
++
++static ssize_t display_upd_mode_store(struct omap_display *display,
++ const char *buf, size_t size)
++{
++ int val, r;
++ enum omap_dss_update_mode mode;
++
++ val = simple_strtoul(buf, NULL, 10);
++
++ switch (val) {
++ case OMAP_DSS_UPDATE_DISABLED:
++ case OMAP_DSS_UPDATE_AUTO:
++ case OMAP_DSS_UPDATE_MANUAL:
++ mode = (enum omap_dss_update_mode)val;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if ((r = display->set_update_mode(display, mode)))
++ return r;
++
++ return size;
++}
++
++static ssize_t display_tear_show(struct omap_display *display, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n",
++ display->get_te ? display->get_te(display) : 0);
++}
++
++static ssize_t display_tear_store(struct omap_display *display,
++ const char *buf, size_t size)
++{
++ unsigned long te;
++ int r;
++
++ if (!display->enable_te || !display->get_te)
++ return -ENOENT;
++
++ te = simple_strtoul(buf, NULL, 0);
++
++ if ((r = display->enable_te(display, te)))
++ return r;
++
++ return size;
++}
++
++static ssize_t display_timings_show(struct omap_display *display, char *buf)
++{
++ struct omap_video_timings t;
++
++ if (!display->get_timings)
++ return -ENOENT;
++
++ display->get_timings(display, &t);
++
++ return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
++ t.pixel_clock,
++ t.x_res, t.hsw, t.hfp, t.hbp,
++ t.y_res, t.vsw, t.vfp, t.vbp);
++}
++
++static ssize_t display_timings_store(struct omap_display *display,
++ const char *buf, size_t size)
++{
++ struct omap_video_timings t;
++ int r;
++
++ if (!display->set_timings || !display->check_timings)
++ return -ENOENT;
++
++ if (strncmp("pal", buf, 3) == 0) {
++ t = omap_dss_pal_timings;
++ } else if (strncmp("ntsc", buf, 4) == 0) {
++ t = omap_dss_ntsc_timings;
++ } else if (sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
++ &t.pixel_clock,
++ &t.x_res, &t.hsw, &t.hfp, &t.hbp,
++ &t.y_res, &t.vsw, &t.vfp, &t.vbp) != 9)
++ return -EINVAL;
++
++ if ((r = display->check_timings(display, &t)))
++ return r;
++
++ display->set_timings(display, &t);
++
++ return size;
++}
++
++static ssize_t display_rotate_show(struct omap_display *display, char *buf)
++{
++ int rotate;
++ if (!display->get_rotate)
++ return -ENOENT;
++ rotate = display->get_rotate(display);
++ return snprintf(buf, PAGE_SIZE, "%u\n", rotate);
++}
++
++static ssize_t display_rotate_store(struct omap_display *display,
++ const char *buf, size_t size)
++{
++ unsigned long rot;
++ int r;
++
++ if (!display->set_rotate || !display->get_rotate)
++ return -ENOENT;
++
++ rot = simple_strtoul(buf, NULL, 0);
++
++ if ((r = display->set_rotate(display, rot)))
++ return r;
++
++ return size;
++}
++
++static ssize_t display_mirror_show(struct omap_display *display, char *buf)
++{
++ int mirror;
++ if (!display->get_mirror)
++ return -ENOENT;
++ mirror = display->get_mirror(display);
++ return snprintf(buf, PAGE_SIZE, "%u\n", mirror);
++}
++
++static ssize_t display_mirror_store(struct omap_display *display,
++ const char *buf, size_t size)
++{
++ unsigned long mirror;
++ int r;
++
++ if (!display->set_mirror || !display->get_mirror)
++ return -ENOENT;
++
++ mirror = simple_strtoul(buf, NULL, 0);
++
++ if ((r = display->set_mirror(display, mirror)))
++ return r;
++
++ return size;
++}
++
++static ssize_t display_panel_name_show(struct omap_display *display, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%s\n",
++ display->panel ? display->panel->name : "");
++}
++
++static ssize_t display_ctrl_name_show(struct omap_display *display, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%s\n",
++ display->ctrl ? display->ctrl->name : "");
++}
++
++struct display_attribute {
++ struct attribute attr;
++ ssize_t (*show)(struct omap_display *, char *);
++ ssize_t (*store)(struct omap_display *, const char *, size_t);
++};
++
++#define DISPLAY_ATTR(_name, _mode, _show, _store) \
++ struct display_attribute display_attr_##_name = \
++ __ATTR(_name, _mode, _show, _store)
++
++static DISPLAY_ATTR(name, S_IRUGO, display_name_show, NULL);
++static DISPLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
++ display_enabled_show, display_enabled_store);
++static DISPLAY_ATTR(update_mode, S_IRUGO|S_IWUSR,
++ display_upd_mode_show, display_upd_mode_store);
++static DISPLAY_ATTR(tear_elim, S_IRUGO|S_IWUSR,
++ display_tear_show, display_tear_store);
++static DISPLAY_ATTR(timings, S_IRUGO|S_IWUSR,
++ display_timings_show, display_timings_store);
++static DISPLAY_ATTR(rotate, S_IRUGO|S_IWUSR,
++ display_rotate_show, display_rotate_store);
++static DISPLAY_ATTR(mirror, S_IRUGO|S_IWUSR,
++ display_mirror_show, display_mirror_store);
++static DISPLAY_ATTR(panel_name, S_IRUGO, display_panel_name_show, NULL);
++static DISPLAY_ATTR(ctrl_name, S_IRUGO, display_ctrl_name_show, NULL);
++
++static struct attribute *display_sysfs_attrs[] = {
++ &display_attr_name.attr,
++ &display_attr_enabled.attr,
++ &display_attr_update_mode.attr,
++ &display_attr_tear_elim.attr,
++ &display_attr_timings.attr,
++ &display_attr_rotate.attr,
++ &display_attr_mirror.attr,
++ &display_attr_panel_name.attr,
++ &display_attr_ctrl_name.attr,
++ NULL
++};
++
++static ssize_t display_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
++{
++ struct omap_display *display;
++ struct display_attribute *display_attr;
++
++ display = container_of(kobj, struct omap_display, kobj);
++ display_attr = container_of(attr, struct display_attribute, attr);
++
++ if (!display_attr->show)
++ return -ENOENT;
++
++ return display_attr->show(display, buf);
++}
++
++static ssize_t display_attr_store(struct kobject *kobj, struct attribute *attr,
++ const char *buf, size_t size)
++{
++ struct omap_display *display;
++ struct display_attribute *display_attr;
++
++ display = container_of(kobj, struct omap_display, kobj);
++ display_attr = container_of(attr, struct display_attribute, attr);
++
++ if (!display_attr->store)
++ return -ENOENT;
++
++ return display_attr->store(display, buf, size);
++}
++
++static struct sysfs_ops display_sysfs_ops = {
++ .show = display_attr_show,
++ .store = display_attr_store,
++};
++
++static struct kobj_type display_ktype = {
++ .sysfs_ops = &display_sysfs_ops,
++ .default_attrs = display_sysfs_attrs,
++};
++
++static void default_get_resolution(struct omap_display *display,
++ u16 *xres, u16 *yres)
++{
++ *xres = display->panel->timings.x_res;
++ *yres = display->panel->timings.y_res;
++}
++
++static void default_configure_overlay(struct omap_overlay *ovl)
++{
++ unsigned low, high, size;
++ enum omap_burst_size burst;
++ enum omap_plane plane = ovl->id;
++
++ burst = OMAP_DSS_BURST_16x32;
++ size = 16 * 32 / 8;
++
++ dispc_set_burst_size(plane, burst);
++
++ high = dispc_get_plane_fifo_size(plane) - 1;
++ low = dispc_get_plane_fifo_size(plane) - size;
++
++ dispc_setup_plane_fifo(plane, low, high);
++}
++
++static int default_wait_vsync(struct omap_display *display)
++{
++ unsigned long timeout = msecs_to_jiffies(500);
++ u32 irq;
++
++ if (display->type == OMAP_DISPLAY_TYPE_VENC)
++ irq = DISPC_IRQ_EVSYNC_ODD;
++ else
++ irq = DISPC_IRQ_VSYNC;
++
++ return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
++}
++
++static int default_get_recommended_bpp(struct omap_display *display)
++{
++ if (display->panel->recommended_bpp)
++ return display->panel->recommended_bpp;
++
++ switch (display->type) {
++ case OMAP_DISPLAY_TYPE_DPI:
++ if (display->hw_config.u.dpi.data_lines == 24)
++ return 24;
++ else
++ return 16;
++
++ case OMAP_DISPLAY_TYPE_DBI:
++ case OMAP_DISPLAY_TYPE_DSI:
++ if (display->ctrl->pixel_size == 24)
++ return 24;
++ else
++ return 16;
++ case OMAP_DISPLAY_TYPE_VENC:
++ case OMAP_DISPLAY_TYPE_SDI:
++ return 24;
++ return 24;
++ default:
++ BUG();
++ }
++}
++
++void dss_init_displays(struct platform_device *pdev)
++{
++ struct omap_dss_board_info *pdata = pdev->dev.platform_data;
++ int i, r;
++
++ INIT_LIST_HEAD(&display_list);
++
++ num_displays = 0;
++
++ for (i = 0; i < pdata->num_displays; ++i) {
++ struct omap_display *display;
++
++ switch (pdata->displays[i]->type) {
++ case OMAP_DISPLAY_TYPE_DPI:
++#ifdef CONFIG_OMAP2_DSS_RFBI
++ case OMAP_DISPLAY_TYPE_DBI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++ case OMAP_DISPLAY_TYPE_SDI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++ case OMAP_DISPLAY_TYPE_DSI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++ case OMAP_DISPLAY_TYPE_VENC:
++#endif
++ break;
++ default:
++ DSSERR("Support for display '%s' not compiled in.\n",
++ pdata->displays[i]->name);
++ continue;
++ }
++
++ display = kzalloc(sizeof(*display), GFP_KERNEL);
++
++ /*atomic_set(&display->ref_count, 0);*/
++ display->ref_count = 0;
++
++ display->hw_config = *pdata->displays[i];
++ display->type = pdata->displays[i]->type;
++ display->name = pdata->displays[i]->name;
++
++ display->get_resolution = default_get_resolution;
++ display->get_recommended_bpp = default_get_recommended_bpp;
++ display->configure_overlay = default_configure_overlay;
++ display->wait_vsync = default_wait_vsync;
++
++ switch (display->type) {
++ case OMAP_DISPLAY_TYPE_DPI:
++ dpi_init_display(display);
++ break;
++#ifdef CONFIG_OMAP2_DSS_RFBI
++ case OMAP_DISPLAY_TYPE_DBI:
++ rfbi_init_display(display);
++ break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++ case OMAP_DISPLAY_TYPE_VENC:
++ venc_init_display(display);
++ break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++ case OMAP_DISPLAY_TYPE_SDI:
++ sdi_init_display(display);
++ break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++ case OMAP_DISPLAY_TYPE_DSI:
++ dsi_init_display(display);
++ break;
++#endif
++ default:
++ BUG();
++ }
++
++ r = kobject_init_and_add(&display->kobj, &display_ktype,
++ &pdev->dev.kobj, "display%d", num_displays);
++
++ if (r) {
++ DSSERR("failed to create sysfs file\n");
++ continue;
++ }
++
++ num_displays++;
++
++ list_add_tail(&display->list, &display_list);
++ }
++}
++
++void dss_uninit_displays(struct platform_device *pdev)
++{
++ struct omap_display *display;
++
++ while (!list_empty(&display_list)) {
++ display = list_first_entry(&display_list,
++ struct omap_display, list);
++ list_del(&display->list);
++ kobject_del(&display->kobj);
++ kobject_put(&display->kobj);
++ kfree(display);
++ }
++
++ num_displays = 0;
++}
++
++int dss_suspend_all_displays(void)
++{
++ int r;
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
++ display->activate_after_resume = 0;
++ continue;
++ }
++
++ if (!display->suspend) {
++ DSSERR("display '%s' doesn't implement suspend\n",
++ display->name);
++ r = -ENOSYS;
++ goto err;
++ }
++
++ r = display->suspend(display);
++
++ if (r)
++ goto err;
++
++ display->activate_after_resume = 1;
++ }
++
++ return 0;
++err:
++ /* resume all displays that were suspended */
++ dss_resume_all_displays();
++ return r;
++}
++
++int dss_resume_all_displays(void)
++{
++ int r;
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (display->activate_after_resume && display->resume) {
++ r = display->resume(display);
++ if (r)
++ return r;
++ }
++
++ display->activate_after_resume = 0;
++ }
++
++ return 0;
++}
++
++int omap_dss_get_num_displays(void)
++{
++ return num_displays;
++}
++EXPORT_SYMBOL(omap_dss_get_num_displays);
++
++struct omap_display *dss_get_display(int no)
++{
++ int i = 0;
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (i++ == no)
++ return display;
++ }
++
++ return NULL;
++}
++
++struct omap_display *omap_dss_get_display(int no)
++{
++ struct omap_display *display;
++
++ display = dss_get_display(no);
++
++ if (!display)
++ return NULL;
++
++ switch (display->type) {
++ case OMAP_DISPLAY_TYPE_VENC:
++ break;
++
++ case OMAP_DISPLAY_TYPE_DPI:
++ case OMAP_DISPLAY_TYPE_SDI:
++ if (display->panel == NULL)
++ return NULL;
++ break;
++
++ case OMAP_DISPLAY_TYPE_DBI:
++ case OMAP_DISPLAY_TYPE_DSI:
++ if (display->panel == NULL || display->ctrl == NULL)
++ return NULL;
++ break;
++
++ default:
++ return NULL;
++ }
++
++ if (display->ctrl) {
++ if (!try_module_get(display->ctrl->owner))
++ goto err0;
++
++ if (display->ctrl->init)
++ if (display->ctrl->init(display) != 0)
++ goto err1;
++ }
++
++ if (display->panel) {
++ if (!try_module_get(display->panel->owner))
++ goto err2;
++
++ if (display->panel->init)
++ if (display->panel->init(display) != 0)
++ goto err3;
++ }
++
++ display->ref_count++;
++ /*
++ if (atomic_cmpxchg(&display->ref_count, 0, 1) != 0)
++ return 0;
++*/
++
++ return display;
++err3:
++ if (display->panel)
++ module_put(display->panel->owner);
++err2:
++ if (display->ctrl && display->ctrl->cleanup)
++ display->ctrl->cleanup(display);
++err1:
++ if (display->ctrl)
++ module_put(display->ctrl->owner);
++err0:
++ return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_display);
++
++void omap_dss_put_display(struct omap_display *display)
++{
++ if (--display->ref_count > 0)
++ return;
++/*
++ if (atomic_cmpxchg(&display->ref_count, 1, 0) != 1)
++ return;
++*/
++ if (display->ctrl) {
++ if (display->ctrl->cleanup)
++ display->ctrl->cleanup(display);
++ module_put(display->ctrl->owner);
++ }
++
++ if (display->panel) {
++ if (display->panel->cleanup)
++ display->panel->cleanup(display);
++ module_put(display->panel->owner);
++ }
++}
++EXPORT_SYMBOL(omap_dss_put_display);
++
++void omap_dss_register_ctrl(struct omap_ctrl *ctrl)
++{
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (display->hw_config.ctrl_name &&
++ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0) {
++ display->ctrl = ctrl;
++ DSSDBG("ctrl '%s' registered\n", ctrl->name);
++ }
++ }
++}
++EXPORT_SYMBOL(omap_dss_register_ctrl);
++
++void omap_dss_register_panel(struct omap_panel *panel)
++{
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (display->hw_config.panel_name &&
++ strcmp(display->hw_config.panel_name, panel->name) == 0) {
++ display->panel = panel;
++ DSSDBG("panel '%s' registered\n", panel->name);
++ }
++ }
++}
++EXPORT_SYMBOL(omap_dss_register_panel);
++
++void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl)
++{
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (display->hw_config.ctrl_name &&
++ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0)
++ display->ctrl = NULL;
++ }
++}
++EXPORT_SYMBOL(omap_dss_unregister_ctrl);
++
++void omap_dss_unregister_panel(struct omap_panel *panel)
++{
++ struct omap_display *display;
++
++ list_for_each_entry(display, &display_list, list) {
++ if (display->hw_config.panel_name &&
++ strcmp(display->hw_config.panel_name, panel->name) == 0)
++ display->panel = NULL;
++ }
++}
++EXPORT_SYMBOL(omap_dss_unregister_panel);
+diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
+new file mode 100644
+index 0000000..b41b07e
+--- /dev/null
++++ b/drivers/video/omap2/dss/dpi.c
+@@ -0,0 +1,379 @@
++/*
++ * linux/drivers/video/omap2/dss/dpi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++
++static struct {
++ int update_enabled;
++} dpi;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
++ unsigned long *fck, int *lck_div, int *pck_div)
++{
++ struct dsi_clock_info cinfo;
++ int r;
++
++ r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo);
++ if (r)
++ return r;
++
++ r = dsi_pll_program(&cinfo);
++ if (r)
++ return r;
++
++ dss_select_clk_source(0, 1);
++
++ dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
++
++ *fck = cinfo.dsi1_pll_fclk;
++ *lck_div = cinfo.lck_div;
++ *pck_div = cinfo.pck_div;
++
++ return 0;
++}
++#else
++static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
++ unsigned long *fck, int *lck_div, int *pck_div)
++{
++ struct dispc_clock_info cinfo;
++ int r;
++
++ r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
++ if (r)
++ return r;
++
++ r = dispc_set_clock_div(&cinfo);
++ if (r)
++ return r;
++
++ *fck = cinfo.fck;
++ *lck_div = cinfo.lck_div;
++ *pck_div = cinfo.pck_div;
++
++ return 0;
++}
++#endif
++
++static int dpi_set_mode(struct omap_display *display)
++{
++ struct omap_panel *panel = display->panel;
++ int lck_div, pck_div;
++ unsigned long fck;
++ unsigned long pck;
++ bool is_tft;
++ int r = 0;
++
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ dispc_set_pol_freq(panel);
++
++ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++ r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000,
++ &fck, &lck_div, &pck_div);
++#else
++ r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000,
++ &fck, &lck_div, &pck_div);
++#endif
++ if (r)
++ goto err0;
++
++ pck = fck / lck_div / pck_div / 1000;
++
++ if (pck != panel->timings.pixel_clock) {
++ DSSWARN("Could not find exact pixel clock. "
++ "Requested %d kHz, got %lu kHz\n",
++ panel->timings.pixel_clock, pck);
++
++ panel->timings.pixel_clock = pck;
++ }
++
++ dispc_set_lcd_timings(&panel->timings);
++
++err0:
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++ return r;
++}
++
++static int dpi_basic_init(struct omap_display *display)
++{
++ bool is_tft;
++
++ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++ dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
++ OMAP_DSS_LCD_DISPLAY_STN);
++ dispc_set_tft_data_lines(display->hw_config.u.dpi.data_lines);
++
++ return 0;
++}
++
++static int dpi_display_enable(struct omap_display *display)
++{
++ struct omap_panel *panel = display->panel;
++ int r;
++
++ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++ DSSERR("display already enabled\n");
++ return -EINVAL;
++ }
++
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ r = dpi_basic_init(display);
++ if (r)
++ goto err0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++ dss_clk_enable(DSS_CLK_FCK2);
++ r = dsi_pll_init(0, 1);
++ if (r)
++ goto err1;
++#endif
++ r = dpi_set_mode(display);
++ if (r)
++ goto err2;
++
++ mdelay(2);
++
++ dispc_enable_lcd_out(1);
++
++ r = panel->enable(display);
++ if (r)
++ goto err3;
++
++ display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++ return 0;
++
++err3:
++ dispc_enable_lcd_out(0);
++err2:
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++ dsi_pll_uninit();
++err1:
++ dss_clk_disable(DSS_CLK_FCK2);
++#endif
++err0:
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++ return r;
++}
++
++static int dpi_display_resume(struct omap_display *display);
++
++static void dpi_display_disable(struct omap_display *display)
++{
++ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++ return;
++
++ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
++ dpi_display_resume(display);
++
++ display->panel->disable(display);
++
++ dispc_enable_lcd_out(0);
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++ dss_select_clk_source(0, 0);
++ dsi_pll_uninit();
++ dss_clk_disable(DSS_CLK_FCK2);
++#endif
++
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ display->state = OMAP_DSS_DISPLAY_DISABLED;
++}
++
++static int dpi_display_suspend(struct omap_display *display)
++{
++ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++ return -EINVAL;
++
++ DSSDBG("dpi_display_suspend\n");
++
++ if (display->panel->suspend)
++ display->panel->suspend(display);
++
++ dispc_enable_lcd_out(0);
++
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++ return 0;
++}
++
++static int dpi_display_resume(struct omap_display *display)
++{
++ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++ return -EINVAL;
++
++ DSSDBG("dpi_display_resume\n");
++
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ dispc_enable_lcd_out(1);
++
++ if (display->panel->resume)
++ display->panel->resume(display);
++
++ display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++ return 0;
++}
++
++static void dpi_set_timings(struct omap_display *display,
++ struct omap_video_timings *timings)
++{
++ DSSDBG("dpi_set_timings\n");
++ display->panel->timings = *timings;
++ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
++ dpi_set_mode(display);
++ dispc_go(OMAP_DSS_CHANNEL_LCD);
++ }
++}
++
++static int dpi_check_timings(struct omap_display *display,
++ struct omap_video_timings *timings)
++{
++ bool is_tft;
++ int r;
++ int lck_div, pck_div;
++ unsigned long fck;
++ unsigned long pck;
++
++ if (timings->hsw < 1 || timings->hsw > 64 ||
++ timings->hfp < 1 || timings->hfp > 256 ||
++ timings->hbp < 1 || timings->hbp > 256) {
++ return -EINVAL;
++ }
++
++ if (timings->vsw < 1 || timings->vsw > 64 ||
++ timings->vfp > 256 || timings->vbp > 256) {
++ return -EINVAL;
++ }
++
++ if (timings->pixel_clock == 0)
++ return -EINVAL;
++
++ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++ {
++ struct dsi_clock_info cinfo;
++ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
++ &cinfo);
++
++ if (r)
++ return r;
++
++ fck = cinfo.dsi1_pll_fclk;
++ lck_div = cinfo.lck_div;
++ pck_div = cinfo.pck_div;
++ }
++#else
++ {
++ struct dispc_clock_info cinfo;
++ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
++ &cinfo);
++
++ if (r)
++ return r;
++
++ fck = cinfo.fck;
++ lck_div = cinfo.lck_div;
++ pck_div = cinfo.pck_div;
++ }
++#endif
++
++ pck = fck / lck_div / pck_div / 1000;
++
++ timings->pixel_clock = pck;
++
++ return 0;
++}
++
++static void dpi_get_timings(struct omap_display *display,
++ struct omap_video_timings *timings)
++{
++ *timings = display->panel->timings;
++}
++
++static int dpi_display_set_update_mode(struct omap_display *display,
++ enum omap_dss_update_mode mode)
++{
++ if (mode == OMAP_DSS_UPDATE_MANUAL)
++ return -EINVAL;
++
++ if (mode == OMAP_DSS_UPDATE_DISABLED) {
++ dispc_enable_lcd_out(0);
++ dpi.update_enabled = 0;
++ } else {
++ dispc_enable_lcd_out(1);
++ dpi.update_enabled = 1;
++ }
++
++ return 0;
++}
++
++static enum omap_dss_update_mode dpi_display_get_update_mode(
++ struct omap_display *display)
++{
++ return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++ OMAP_DSS_UPDATE_DISABLED;
++}
++
++void dpi_init_display(struct omap_display *display)
++{
++ DSSDBG("DPI init_display\n");
++
++ display->enable = dpi_display_enable;
++ display->disable = dpi_display_disable;
++ display->suspend = dpi_display_suspend;
++ display->resume = dpi_display_resume;
++ display->set_timings = dpi_set_timings;
++ display->check_timings = dpi_check_timings;
++ display->get_timings = dpi_get_timings;
++ display->set_update_mode = dpi_display_set_update_mode;
++ display->get_update_mode = dpi_display_get_update_mode;
++}
++
++int dpi_init(void)
++{
++ return 0;
++}
++
++void dpi_exit(void)
++{
++}
++
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+new file mode 100644
+index 0000000..ea5a58e
+--- /dev/null
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -0,0 +1,3693 @@
++/*
++ * linux/drivers/video/omap2/dss/dsi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSI"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++#include <linux/mutex.h>
++#include <linux/seq_file.h>
++#include <linux/kfifo.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++/*#define VERBOSE_IRQ*/
++
++#define DSI_BASE 0x4804FC00
++
++struct dsi_reg { u16 idx; };
++
++#define DSI_REG(idx) ((const struct dsi_reg) { idx })
++
++#define DSI_SZ_REGS SZ_1K
++/* DSI Protocol Engine */
++
++#define DSI_REVISION DSI_REG(0x0000)
++#define DSI_SYSCONFIG DSI_REG(0x0010)
++#define DSI_SYSSTATUS DSI_REG(0x0014)
++#define DSI_IRQSTATUS DSI_REG(0x0018)
++#define DSI_IRQENABLE DSI_REG(0x001C)
++#define DSI_CTRL DSI_REG(0x0040)
++#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
++#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
++#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
++#define DSI_CLK_CTRL DSI_REG(0x0054)
++#define DSI_TIMING1 DSI_REG(0x0058)
++#define DSI_TIMING2 DSI_REG(0x005C)
++#define DSI_VM_TIMING1 DSI_REG(0x0060)
++#define DSI_VM_TIMING2 DSI_REG(0x0064)
++#define DSI_VM_TIMING3 DSI_REG(0x0068)
++#define DSI_CLK_TIMING DSI_REG(0x006C)
++#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
++#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
++#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
++#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
++#define DSI_VM_TIMING4 DSI_REG(0x0080)
++#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
++#define DSI_VM_TIMING5 DSI_REG(0x0088)
++#define DSI_VM_TIMING6 DSI_REG(0x008C)
++#define DSI_VM_TIMING7 DSI_REG(0x0090)
++#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
++#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
++#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
++#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
++#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
++#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
++
++/* DSIPHY_SCP */
++
++#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
++#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
++#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
++#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
++
++/* DSI_PLL_CTRL_SCP */
++
++#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
++#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
++#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
++#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
++#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
++
++#define REG_GET(idx, start, end) \
++ FLD_GET(dsi_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
++
++/* Global interrupts */
++#define DSI_IRQ_VC0 (1 << 0)
++#define DSI_IRQ_VC1 (1 << 1)
++#define DSI_IRQ_VC2 (1 << 2)
++#define DSI_IRQ_VC3 (1 << 3)
++#define DSI_IRQ_WAKEUP (1 << 4)
++#define DSI_IRQ_RESYNC (1 << 5)
++#define DSI_IRQ_PLL_LOCK (1 << 7)
++#define DSI_IRQ_PLL_UNLOCK (1 << 8)
++#define DSI_IRQ_PLL_RECALL (1 << 9)
++#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
++#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
++#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
++#define DSI_IRQ_TE_TRIGGER (1 << 16)
++#define DSI_IRQ_ACK_TRIGGER (1 << 17)
++#define DSI_IRQ_SYNC_LOST (1 << 18)
++#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
++#define DSI_IRQ_TA_TIMEOUT (1 << 20)
++#define DSI_IRQ_ERROR_MASK \
++ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
++ DSI_IRQ_TA_TIMEOUT)
++#define DSI_IRQ_CHANNEL_MASK 0xf
++
++/* Virtual channel interrupts */
++#define DSI_VC_IRQ_CS (1 << 0)
++#define DSI_VC_IRQ_ECC_CORR (1 << 1)
++#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
++#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
++#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
++#define DSI_VC_IRQ_BTA (1 << 5)
++#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
++#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
++#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
++#define DSI_VC_IRQ_ERROR_MASK \
++ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
++ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
++ DSI_VC_IRQ_FIFO_TX_UDF)
++
++/* ComplexIO interrupts */
++#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
++#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
++#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
++#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
++#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
++#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
++#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
++#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
++#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
++#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
++#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
++#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
++
++#define DSI_DT_DCS_SHORT_WRITE_0 0x05
++#define DSI_DT_DCS_SHORT_WRITE_1 0x15
++#define DSI_DT_DCS_READ 0x06
++#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
++#define DSI_DT_NULL_PACKET 0x09
++#define DSI_DT_DCS_LONG_WRITE 0x39
++
++#define DSI_DT_RX_ACK_WITH_ERR 0x02
++#define DSI_DT_RX_DCS_LONG_READ 0x1c
++#define DSI_DT_RX_SHORT_READ_1 0x21
++#define DSI_DT_RX_SHORT_READ_2 0x22
++
++#define FINT_MAX 2100000
++#define FINT_MIN 750000
++#define REGN_MAX (1 << 7)
++#define REGM_MAX ((1 << 11) - 1)
++#define REGM3_MAX (1 << 4)
++#define REGM4_MAX (1 << 4)
++
++enum fifo_size {
++ DSI_FIFO_SIZE_0 = 0,
++ DSI_FIFO_SIZE_32 = 1,
++ DSI_FIFO_SIZE_64 = 2,
++ DSI_FIFO_SIZE_96 = 3,
++ DSI_FIFO_SIZE_128 = 4,
++};
++
++#define DSI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct dsi_cmd_item))
++
++struct dsi_cmd_update {
++ int bytespp;
++ u16 x;
++ u16 y;
++ u16 w;
++ u16 h;
++};
++
++struct dsi_cmd_mem_read {
++ void *buf;
++ size_t size;
++ u16 x;
++ u16 y;
++ u16 w;
++ u16 h;
++ size_t *ret_size;
++ struct completion *completion;
++};
++
++struct dsi_cmd_test {
++ int test_num;
++ int *result;
++ struct completion *completion;
++};
++
++enum dsi_cmd {
++ DSI_CMD_UPDATE,
++ DSI_CMD_SYNC,
++ DSI_CMD_MEM_READ,
++ DSI_CMD_TEST,
++ DSI_CMD_SET_TE,
++ DSI_CMD_SET_UPDATE_MODE,
++ DSI_CMD_SET_ROTATE,
++ DSI_CMD_SET_MIRROR,
++};
++
++struct dsi_cmd_item {
++ struct omap_display *display;
++
++ enum dsi_cmd cmd;
++
++ union {
++ struct dsi_cmd_update r;
++ struct completion *sync;
++ struct dsi_cmd_mem_read mem_read;
++ struct dsi_cmd_test test;
++ int te;
++ enum omap_dss_update_mode update_mode;
++ int rotate;
++ int mirror;
++ } u;
++};
++
++static struct
++{
++ void __iomem *base;
++
++ unsigned long dsi1_pll_fclk; /* Hz */
++ unsigned long dsi2_pll_fclk; /* Hz */
++ unsigned long dsiphy; /* Hz */
++ unsigned long ddr_clk; /* Hz */
++
++ struct {
++ enum fifo_size fifo_size;
++ int dest_per; /* destination peripheral 0-3 */
++ } vc[4];
++
++ struct mutex lock;
++
++ unsigned pll_locked;
++
++ struct completion bta_completion;
++
++ struct work_struct framedone_work;
++ struct workqueue_struct *framedone_workqueue;
++
++ enum omap_dss_update_mode user_update_mode;
++ enum omap_dss_update_mode target_update_mode;
++ enum omap_dss_update_mode update_mode;
++ int use_te;
++ int framedone_scheduled; /* helps to catch strange framedone bugs */
++
++
++ struct {
++ struct omap_display *display;
++ int x, y, w, h;
++ int bytespp;
++ } update_region;
++
++ unsigned long cache_req_pck;
++ unsigned long cache_clk_freq;
++ struct dsi_clock_info cache_cinfo;
++
++ struct kfifo *cmd_fifo;
++ spinlock_t cmd_lock;
++ struct completion cmd_done;
++ atomic_t cmd_fifo_full;
++ atomic_t cmd_pending;
++
++#ifdef DEBUG
++ ktime_t perf_setup_time;
++ ktime_t perf_start_time;
++ int perf_measure_frames;
++#endif
++ int debug_process;
++ int debug_read;
++ int debug_write;
++} dsi;
++
++#ifdef DEBUG
++static unsigned int dsi_perf;
++module_param_named(dsi_perf, dsi_perf, bool, 0644);
++#endif
++
++static void dsi_process_cmd_fifo(void);
++static void dsi_push_update(struct omap_display *display,
++ int x, int y, int w, int h);
++
++static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
++{
++ __raw_writel(val, dsi.base + idx.idx);
++}
++
++static inline u32 dsi_read_reg(const struct dsi_reg idx)
++{
++ return __raw_readl(dsi.base + idx.idx);
++}
++
++
++void dsi_save_context(void)
++{
++}
++
++void dsi_restore_context(void)
++{
++}
++
++static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
++ int value)
++{
++ int t = 100000;
++
++ while (REG_GET(idx, bitnum, bitnum) != value) {
++ if (--t == 0)
++ return !value;
++ }
++
++ return value;
++}
++
++#ifdef DEBUG
++static void perf_mark_setup(void)
++{
++ dsi.perf_setup_time = ktime_get();
++}
++
++static void perf_mark_start(void)
++{
++ dsi.perf_start_time = ktime_get();
++}
++
++static void perf_show(const char *name)
++{
++ ktime_t t, setup_time, trans_time;
++ u32 total_bytes;
++ u32 setup_us, trans_us, total_us;
++ const int numframes = 100;
++ static u32 s_trans_us, s_min_us = 0xffffffff, s_max_us;
++
++ if (!dsi_perf)
++ return;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++ return;
++
++ t = ktime_get();
++
++ setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
++ setup_us = (u32)ktime_to_us(setup_time);
++ if (setup_us == 0)
++ setup_us = 1;
++
++ trans_time = ktime_sub(t, dsi.perf_start_time);
++ trans_us = (u32)ktime_to_us(trans_time);
++ if (trans_us == 0)
++ trans_us = 1;
++
++ total_us = setup_us + trans_us;
++
++ total_bytes = dsi.update_region.w *
++ dsi.update_region.h *
++ dsi.update_region.bytespp;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++ dsi.perf_measure_frames++;
++
++ if (trans_us < s_min_us)
++ s_min_us = trans_us;
++
++ if (trans_us > s_max_us)
++ s_max_us = trans_us;
++
++ s_trans_us += trans_us;
++
++ if (dsi.perf_measure_frames < numframes)
++ return;
++
++ DSSINFO("%s update: %d frames in %u us "
++ "(min/max/avg %u/%u/%u), %u fps\n",
++ name, numframes,
++ s_trans_us,
++ s_min_us,
++ s_max_us,
++ s_trans_us / numframes,
++ 1000*1000 / (s_trans_us / numframes));
++
++ dsi.perf_measure_frames = 0;
++ s_trans_us = 0;
++ s_min_us = 0xffffffff;
++ s_max_us = 0;
++ } else {
++ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
++ "%u kbytes/sec\n",
++ name,
++ setup_us,
++ trans_us,
++ total_us,
++ 1000*1000 / total_us,
++ total_bytes,
++ total_bytes * 1000 / total_us);
++ }
++}
++#else
++#define perf_mark_setup()
++#define perf_mark_start()
++#define perf_show(x)
++#endif
++
++static void print_irq_status(u32 status)
++{
++#ifndef VERBOSE_IRQ
++ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
++ return;
++#endif
++ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++ if (status & DSI_IRQ_##x) \
++ printk(#x " ");
++#ifdef VERBOSE_IRQ
++ PIS(VC0);
++ PIS(VC1);
++ PIS(VC2);
++ PIS(VC3);
++#endif
++ PIS(WAKEUP);
++ PIS(RESYNC);
++ PIS(PLL_LOCK);
++ PIS(PLL_UNLOCK);
++ PIS(PLL_RECALL);
++ PIS(COMPLEXIO_ERR);
++ PIS(HS_TX_TIMEOUT);
++ PIS(LP_RX_TIMEOUT);
++ PIS(TE_TRIGGER);
++ PIS(ACK_TRIGGER);
++ PIS(SYNC_LOST);
++ PIS(LDO_POWER_GOOD);
++ PIS(TA_TIMEOUT);
++#undef PIS
++
++ printk("\n");
++}
++
++static void print_irq_status_vc(int channel, u32 status)
++{
++#ifndef VERBOSE_IRQ
++ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
++ return;
++#endif
++ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
++
++#define PIS(x) \
++ if (status & DSI_VC_IRQ_##x) \
++ printk(#x " ");
++ PIS(CS);
++ PIS(ECC_CORR);
++#ifdef VERBOSE_IRQ
++ PIS(PACKET_SENT);
++#endif
++ PIS(FIFO_TX_OVF);
++ PIS(FIFO_RX_OVF);
++ PIS(BTA);
++ PIS(ECC_NO_CORR);
++ PIS(FIFO_TX_UDF);
++ PIS(PP_BUSY_CHANGE);
++#undef PIS
++ printk("\n");
++}
++
++static void print_irq_status_cio(u32 status)
++{
++ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
++
++#define PIS(x) \
++ if (status & DSI_CIO_IRQ_##x) \
++ printk(#x " ");
++ PIS(ERRSYNCESC1);
++ PIS(ERRSYNCESC2);
++ PIS(ERRSYNCESC3);
++ PIS(ERRESC1);
++ PIS(ERRESC2);
++ PIS(ERRESC3);
++ PIS(ERRCONTROL1);
++ PIS(ERRCONTROL2);
++ PIS(ERRCONTROL3);
++ PIS(STATEULPS1);
++ PIS(STATEULPS2);
++ PIS(STATEULPS3);
++ PIS(ERRCONTENTIONLP0_1);
++ PIS(ERRCONTENTIONLP1_1);
++ PIS(ERRCONTENTIONLP0_2);
++ PIS(ERRCONTENTIONLP1_2);
++ PIS(ERRCONTENTIONLP0_3);
++ PIS(ERRCONTENTIONLP1_3);
++ PIS(ULPSACTIVENOT_ALL0);
++ PIS(ULPSACTIVENOT_ALL1);
++#undef PIS
++
++ printk("\n");
++}
++
++static int debug_irq;
++
++/* called from dss */
++void dsi_irq_handler(void)
++{
++ u32 irqstatus, vcstatus, ciostatus;
++ int i;
++
++ irqstatus = dsi_read_reg(DSI_IRQSTATUS);
++
++ if (irqstatus & DSI_IRQ_ERROR_MASK) {
++ DSSERR("DSI error, irqstatus %x\n", irqstatus);
++ print_irq_status(irqstatus);
++ } else if (debug_irq) {
++ print_irq_status(irqstatus);
++ }
++
++ for (i = 0; i < 4; ++i) {
++ if ((irqstatus & (1<<i)) == 0)
++ continue;
++
++ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++
++ if (vcstatus & DSI_VC_IRQ_BTA)
++ complete(&dsi.bta_completion);
++
++ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
++ DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
++ i, vcstatus);
++ print_irq_status_vc(i, vcstatus);
++ } else if (debug_irq) {
++ print_irq_status_vc(i, vcstatus);
++ }
++
++ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
++ }
++
++ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
++ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
++
++ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
++ print_irq_status_cio(ciostatus);
++ }
++
++ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
++}
++
++
++static void _dsi_initialize_irq(void)
++{
++ u32 l;
++ int i;
++
++ /* disable all interrupts */
++ dsi_write_reg(DSI_IRQENABLE, 0);
++ for (i = 0; i < 4; ++i)
++ dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
++
++ /* clear interrupt status */
++ l = dsi_read_reg(DSI_IRQSTATUS);
++ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
++
++ for (i = 0; i < 4; ++i) {
++ l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++ dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
++ }
++
++ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
++
++ /* enable error irqs */
++ l = DSI_IRQ_ERROR_MASK;
++ dsi_write_reg(DSI_IRQENABLE, l);
++
++ l = DSI_VC_IRQ_ERROR_MASK;
++ for (i = 0; i < 4; ++i)
++ dsi_write_reg(DSI_VC_IRQENABLE(i), l);
++
++ /* XXX zonda responds incorrectly, causing control error:
++ Exit from LP-ESC mode to LP11 uses wrong transition states on the
++ data lines LP0 and LN0. */
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
++ -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
++}
++
++static void dsi_vc_enable_bta_irq(int channel)
++{
++ u32 l;
++
++ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++ l |= DSI_VC_IRQ_BTA;
++ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++static void dsi_vc_disable_bta_irq(int channel)
++{
++ u32 l;
++
++ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++ l &= ~DSI_VC_IRQ_BTA;
++ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++/* DSI func clock. this could also be DSI2_PLL_FCLK */
++static inline void enable_clocks(bool enable)
++{
++ if (enable)
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++ else
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++/* source clock for DSI PLL. this could also be PCLKFREE */
++static inline void dsi_enable_pll_clock(bool enable)
++{
++ if (enable)
++ dss_clk_enable(DSS_CLK_FCK2);
++ else
++ dss_clk_disable(DSS_CLK_FCK2);
++
++ if (enable && dsi.pll_locked) {
++ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
++ DSSERR("cannot lock PLL when enabling clocks\n");
++ }
++}
++
++#ifdef DEBUG
++static void _dsi_print_reset_status(void)
++{
++ u32 l;
++
++ if (!dss_debug)
++ return;
++
++ /* A dummy read using the SCP interface to any DSIPHY register is
++ * required after DSIPHY reset to complete the reset of the DSI complex
++ * I/O. */
++ l = dsi_read_reg(DSI_DSIPHY_CFG5);
++
++ printk(KERN_DEBUG "DSI resets: ");
++
++ l = dsi_read_reg(DSI_PLL_STATUS);
++ printk("PLL (%d) ", FLD_GET(l, 0, 0));
++
++ l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++ printk("CIO (%d) ", FLD_GET(l, 29, 29));
++
++ l = dsi_read_reg(DSI_DSIPHY_CFG5);
++ printk("PHY (%x, %d, %d, %d)\n",
++ FLD_GET(l, 28, 26),
++ FLD_GET(l, 29, 29),
++ FLD_GET(l, 30, 30),
++ FLD_GET(l, 31, 31));
++}
++#else
++#define _dsi_print_reset_status()
++#endif
++
++static inline int dsi_if_enable(bool enable)
++{
++ DSSDBG("dsi_if_enable(%d)\n", enable);
++
++ enable = enable ? 1 : 0;
++ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
++
++ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
++ DSSERR("Failed to set dsi_if_enable to %d\n", enable);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static unsigned long dsi_fclk_rate(void)
++{
++ unsigned long r;
++
++ if (dss_get_dsi_clk_source() == 0) {
++ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
++ r = dss_clk_get_rate(DSS_CLK_FCK1);
++ } else {
++ /* DSI FCLK source is DSI2_PLL_FCLK */
++ r = dsi.dsi2_pll_fclk;
++ }
++
++ return r;
++}
++
++static int dsi_set_lp_clk_divisor(void)
++{
++ int n;
++ unsigned long dsi_fclk;
++ unsigned long mhz;
++
++ /* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
++
++ dsi_fclk = dsi_fclk_rate();
++
++ for (n = 1; n < (1 << 13) - 1; ++n) {
++ mhz = dsi_fclk / n;
++ if (mhz <= 20*1000*1000)
++ break;
++ }
++
++ if (n == (1 << 13) - 1) {
++ DSSERR("Failed to find LP_CLK_DIVISOR\n");
++ return -EINVAL;
++ }
++
++ DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
++
++ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */
++ if (dsi_fclk > 30*1000*1000)
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
++
++ return 0;
++}
++
++
++enum dsi_pll_power_state {
++ DSI_PLL_POWER_OFF = 0x0,
++ DSI_PLL_POWER_ON_HSCLK = 0x1,
++ DSI_PLL_POWER_ON_ALL = 0x2,
++ DSI_PLL_POWER_ON_DIV = 0x3,
++};
++
++static int dsi_pll_power(enum dsi_pll_power_state state)
++{
++ int t = 0;
++
++ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
++
++ /* PLL_PWR_STATUS */
++ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
++ udelay(1);
++ if (t++ > 1000) {
++ DSSERR("Failed to set DSI PLL power mode to %d\n",
++ state);
++ return -ENODEV;
++ }
++ }
++
++ return 0;
++}
++
++int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
++ struct dsi_clock_info *cinfo)
++{
++ struct dsi_clock_info cur, best;
++ int min_fck_per_pck;
++ int match = 0;
++
++ if (req_pck == dsi.cache_req_pck &&
++ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
++ DSSDBG("DSI clock info found from cache\n");
++ *cinfo = dsi.cache_cinfo;
++ return 0;
++ }
++
++ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++ if (min_fck_per_pck &&
++ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++ DSSERR("Requested pixel clock not possible with the current "
++ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++ "the constraint off.\n");
++ min_fck_per_pck = 0;
++ }
++
++ DSSDBG("dsi_pll_calc\n");
++
++retry:
++ memset(&best, 0, sizeof(best));
++
++ memset(&cur, 0, sizeof(cur));
++ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
++ cur.use_dss2_fck = 1;
++ cur.highfreq = 0;
++
++ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++ if (cur.highfreq == 0)
++ cur.fint = cur.clkin / cur.regn;
++ else
++ cur.fint = cur.clkin / (2 * cur.regn);
++
++ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++ continue;
++
++ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++ unsigned long a, b;
++
++ a = 2 * cur.regm * (cur.clkin/1000);
++ b = cur.regn * (cur.highfreq + 1);
++ cur.dsiphy = a / b * 1000;
++
++ if (cur.dsiphy > 1800 * 1000 * 1000)
++ break;
++
++ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
++ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
++ ++cur.regm3) {
++ cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
++
++ /* this will narrow down the search a bit,
++ * but still give pixclocks below what was
++ * requested */
++ if (cur.dsi1_pll_fclk < req_pck)
++ break;
++
++ if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
++ continue;
++
++ if (min_fck_per_pck &&
++ cur.dsi1_pll_fclk <
++ req_pck * min_fck_per_pck)
++ continue;
++
++ match = 1;
++
++ find_lck_pck_divs(is_tft, req_pck,
++ cur.dsi1_pll_fclk,
++ &cur.lck_div,
++ &cur.pck_div);
++
++ cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
++ cur.pck = cur.lck / cur.pck_div;
++
++ if (abs(cur.pck - req_pck) <
++ abs(best.pck - req_pck)) {
++ best = cur;
++
++ if (cur.pck == req_pck)
++ goto found;
++ }
++ }
++ }
++ }
++found:
++ if (!match) {
++ if (min_fck_per_pck) {
++ DSSERR("Could not find suitable clock settings.\n"
++ "Turning FCK/PCK constraint off and"
++ "trying again.\n");
++ min_fck_per_pck = 0;
++ goto retry;
++ }
++
++ DSSERR("Could not find suitable clock settings.\n");
++
++ return -EINVAL;
++ }
++
++ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
++ best.regm4 = best.dsiphy / 48000000;
++ if (best.regm4 > REGM4_MAX)
++ best.regm4 = REGM4_MAX;
++ else if (best.regm4 == 0)
++ best.regm4 = 1;
++ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
++
++ if (cinfo)
++ *cinfo = best;
++
++ dsi.cache_req_pck = req_pck;
++ dsi.cache_clk_freq = 0;
++ dsi.cache_cinfo = best;
++
++ return 0;
++}
++
++static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
++ struct dsi_clock_info *cinfo)
++{
++ struct dsi_clock_info cur, best;
++ const bool use_dss2_fck = 1;
++ unsigned long datafreq;
++
++ DSSDBG("dsi_pll_calc_ddrfreq\n");
++
++ if (clk_freq == dsi.cache_clk_freq &&
++ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
++ DSSDBG("DSI clock info found from cache\n");
++ *cinfo = dsi.cache_cinfo;
++ return 0;
++ }
++
++ datafreq = clk_freq * 4;
++
++ memset(&best, 0, sizeof(best));
++
++ memset(&cur, 0, sizeof(cur));
++ cur.use_dss2_fck = use_dss2_fck;
++ if (use_dss2_fck) {
++ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
++ cur.highfreq = 0;
++ } else {
++ cur.clkin = dispc_pclk_rate();
++ if (cur.clkin < 32000000)
++ cur.highfreq = 0;
++ else
++ cur.highfreq = 1;
++ }
++
++ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++ if (cur.highfreq == 0)
++ cur.fint = cur.clkin / cur.regn;
++ else
++ cur.fint = cur.clkin / (2 * cur.regn);
++
++ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++ continue;
++
++ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++ unsigned long a, b;
++
++ a = 2 * cur.regm * (cur.clkin/1000);
++ b = cur.regn * (cur.highfreq + 1);
++ cur.dsiphy = a / b * 1000;
++
++ if (cur.dsiphy > 1800 * 1000 * 1000)
++ break;
++
++ if (abs(cur.dsiphy - datafreq) <
++ abs(best.dsiphy - datafreq)) {
++ best = cur;
++ /* DSSDBG("best %ld\n", best.dsiphy); */
++ }
++
++ if (cur.dsiphy == datafreq)
++ goto found;
++ }
++ }
++found:
++ /* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
++ best.regm3 = best.dsiphy / 48000000;
++ if (best.regm3 > REGM3_MAX)
++ best.regm3 = REGM3_MAX;
++ else if (best.regm3 == 0)
++ best.regm3 = 1;
++ best.dsi1_pll_fclk = best.dsiphy / best.regm3;
++
++ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
++ best.regm4 = best.dsiphy / 48000000;
++ if (best.regm4 > REGM4_MAX)
++ best.regm4 = REGM4_MAX;
++ else if (best.regm4 == 0)
++ best.regm4 = 1;
++ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
++
++ if (cinfo)
++ *cinfo = best;
++
++ dsi.cache_clk_freq = clk_freq;
++ dsi.cache_req_pck = 0;
++ dsi.cache_cinfo = best;
++
++ return 0;
++}
++
++int dsi_pll_program(struct dsi_clock_info *cinfo)
++{
++ int r = 0;
++ u32 l;
++
++ DSSDBG("dsi_pll_program\n");
++
++ dsi.dsiphy = cinfo->dsiphy;
++ dsi.ddr_clk = dsi.dsiphy / 4;
++ dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
++ dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
++
++ DSSDBG("DSI Fint %ld\n", cinfo->fint);
++
++ DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
++ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
++ cinfo->clkin,
++ cinfo->highfreq);
++
++ /* DSIPHY == CLKIN4DDR */
++ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
++ cinfo->regm,
++ cinfo->regn,
++ cinfo->clkin,
++ cinfo->highfreq + 1,
++ cinfo->dsiphy);
++
++ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
++ dsi.dsiphy / 1000 / 1000 / 2);
++
++ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
++
++ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
++ cinfo->regm3, cinfo->dsi1_pll_fclk);
++ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
++ cinfo->regm4, cinfo->dsi2_pll_fclk);
++
++ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
++
++ l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
++ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
++ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
++ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
++ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */
++ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */
++ dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
++
++ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */
++ /* DSI_PLL_CLKSEL */
++ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
++ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */
++ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
++ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
++ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
++ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
++
++ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
++ DSSERR("dsi pll go bit not going down.\n");
++ r = -EIO;
++ goto err;
++ }
++
++ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
++ DSSERR("cannot lock PLL\n");
++ r = -EIO;
++ goto err;
++ }
++
++ dsi.pll_locked = 1;
++
++ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
++ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
++ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
++ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
++ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
++ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
++ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
++ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
++ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
++ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
++ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
++ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
++ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
++ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
++ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++ DSSDBG("PLL config done\n");
++err:
++ return r;
++}
++
++int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
++{
++ int r = 0;
++ enum dsi_pll_power_state pwstate;
++ struct dispc_clock_info cinfo;
++
++ DSSDBG("PLL init\n");
++
++ enable_clocks(1);
++ dsi_enable_pll_clock(1);
++
++ /* configure dispc fck and pixel clock to something sane */
++ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
++ if (r)
++ goto err0;
++
++ r = dispc_set_clock_div(&cinfo);
++ if (r) {
++ DSSERR("Failed to set basic clocks\n");
++ goto err0;
++ }
++
++ r = dss_dsi_power_up();
++ if (r)
++ goto err0;
++
++ /* PLL does not come out of reset without this... */
++ dispc_pck_free_enable(1);
++
++ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
++ DSSERR("PLL not coming out of reset.\n");
++ r = -ENODEV;
++ goto err1;
++ }
++
++ /* ... but if left on, we get problems when planes do not
++ * fill the whole display. No idea about this XXX */
++ dispc_pck_free_enable(0);
++
++ if (enable_hsclk && enable_hsdiv)
++ pwstate = DSI_PLL_POWER_ON_ALL;
++ else if (enable_hsclk)
++ pwstate = DSI_PLL_POWER_ON_HSCLK;
++ else if (enable_hsdiv)
++ pwstate = DSI_PLL_POWER_ON_DIV;
++ else
++ pwstate = DSI_PLL_POWER_OFF;
++
++ r = dsi_pll_power(pwstate);
++
++ if (r)
++ goto err1;
++
++ DSSDBG("PLL init done\n");
++
++ return 0;
++err1:
++ dss_dsi_power_down();
++err0:
++ enable_clocks(0);
++ dsi_enable_pll_clock(0);
++ return r;
++}
++
++void dsi_pll_uninit(void)
++{
++ enable_clocks(0);
++ dsi_enable_pll_clock(0);
++
++ dsi.pll_locked = 0;
++ dsi_pll_power(DSI_PLL_POWER_OFF);
++ dss_dsi_power_down();
++ DSSDBG("PLL uninit done\n");
++}
++
++unsigned long dsi_get_dsi1_pll_rate(void)
++{
++ return dsi.dsi1_pll_fclk;
++}
++
++unsigned long dsi_get_dsi2_pll_rate(void)
++{
++ return dsi.dsi2_pll_fclk;
++}
++
++void dsi_dump_clocks(struct seq_file *s)
++{
++ int clksel;
++
++ enable_clocks(1);
++
++ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
++
++ seq_printf(s, "- dsi -\n");
++
++ seq_printf(s, "dsi fclk source = %s\n",
++ dss_get_dsi_clk_source() == 0 ?
++ "dss1_alwon_fclk" : "dsi2_pll_fclk");
++
++ seq_printf(s, "dsi pll source = %s\n",
++ clksel == 0 ?
++ "dss2_alwon_fclk" : "pclkfree");
++
++ seq_printf(s, "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
++ dsi.dsiphy, dsi.ddr_clk);
++
++ seq_printf(s, "dsi1_pll_fck\t%lu (%s)\n"
++ "dsi2_pll_fck\t%lu (%s)\n",
++ dsi.dsi1_pll_fclk,
++ dss_get_dispc_clk_source() == 0 ? "off" : "on",
++ dsi.dsi2_pll_fclk,
++ dss_get_dsi_clk_source() == 0 ? "off" : "on");
++
++ enable_clocks(0);
++}
++
++void dsi_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
++
++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++ DUMPREG(DSI_REVISION);
++ DUMPREG(DSI_SYSCONFIG);
++ DUMPREG(DSI_SYSSTATUS);
++ DUMPREG(DSI_IRQSTATUS);
++ DUMPREG(DSI_IRQENABLE);
++ DUMPREG(DSI_CTRL);
++ DUMPREG(DSI_COMPLEXIO_CFG1);
++ DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
++ DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
++ DUMPREG(DSI_CLK_CTRL);
++ DUMPREG(DSI_TIMING1);
++ DUMPREG(DSI_TIMING2);
++ DUMPREG(DSI_VM_TIMING1);
++ DUMPREG(DSI_VM_TIMING2);
++ DUMPREG(DSI_VM_TIMING3);
++ DUMPREG(DSI_CLK_TIMING);
++ DUMPREG(DSI_TX_FIFO_VC_SIZE);
++ DUMPREG(DSI_RX_FIFO_VC_SIZE);
++ DUMPREG(DSI_COMPLEXIO_CFG2);
++ DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
++ DUMPREG(DSI_VM_TIMING4);
++ DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
++ DUMPREG(DSI_VM_TIMING5);
++ DUMPREG(DSI_VM_TIMING6);
++ DUMPREG(DSI_VM_TIMING7);
++ DUMPREG(DSI_STOPCLK_TIMING);
++
++ DUMPREG(DSI_VC_CTRL(0));
++ DUMPREG(DSI_VC_TE(0));
++ DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
++ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
++ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
++ DUMPREG(DSI_VC_IRQSTATUS(0));
++ DUMPREG(DSI_VC_IRQENABLE(0));
++
++ DUMPREG(DSI_VC_CTRL(1));
++ DUMPREG(DSI_VC_TE(1));
++ DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
++ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
++ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
++ DUMPREG(DSI_VC_IRQSTATUS(1));
++ DUMPREG(DSI_VC_IRQENABLE(1));
++
++ DUMPREG(DSI_VC_CTRL(2));
++ DUMPREG(DSI_VC_TE(2));
++ DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
++ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
++ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
++ DUMPREG(DSI_VC_IRQSTATUS(2));
++ DUMPREG(DSI_VC_IRQENABLE(2));
++
++ DUMPREG(DSI_VC_CTRL(3));
++ DUMPREG(DSI_VC_TE(3));
++ DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
++ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
++ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
++ DUMPREG(DSI_VC_IRQSTATUS(3));
++ DUMPREG(DSI_VC_IRQENABLE(3));
++
++ DUMPREG(DSI_DSIPHY_CFG0);
++ DUMPREG(DSI_DSIPHY_CFG1);
++ DUMPREG(DSI_DSIPHY_CFG2);
++ DUMPREG(DSI_DSIPHY_CFG5);
++
++ DUMPREG(DSI_PLL_CONTROL);
++ DUMPREG(DSI_PLL_STATUS);
++ DUMPREG(DSI_PLL_GO);
++ DUMPREG(DSI_PLL_CONFIGURATION1);
++ DUMPREG(DSI_PLL_CONFIGURATION2);
++
++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++enum dsi_complexio_power_state {
++ DSI_COMPLEXIO_POWER_OFF = 0x0,
++ DSI_COMPLEXIO_POWER_ON = 0x1,
++ DSI_COMPLEXIO_POWER_ULPS = 0x2,
++};
++
++static int dsi_complexio_power(enum dsi_complexio_power_state state)
++{
++ int t = 0;
++
++ /* PWR_CMD */
++ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
++
++ /* PWR_STATUS */
++ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
++ udelay(1);
++ if (t++ > 1000) {
++ DSSERR("failed to set complexio power state to "
++ "%d\n", state);
++ return -ENODEV;
++ }
++ }
++
++ return 0;
++}
++
++static void dsi_complexio_config(struct omap_display *display)
++{
++ u32 r;
++
++ int clk_lane = display->hw_config.u.dsi.clk_lane;
++ int data1_lane = display->hw_config.u.dsi.data1_lane;
++ int data2_lane = display->hw_config.u.dsi.data2_lane;
++ int clk_pol = display->hw_config.u.dsi.clk_pol;
++ int data1_pol = display->hw_config.u.dsi.data1_pol;
++ int data2_pol = display->hw_config.u.dsi.data2_pol;
++
++ r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++ r = FLD_MOD(r, clk_lane, 2, 0);
++ r = FLD_MOD(r, clk_pol, 3, 3);
++ r = FLD_MOD(r, data1_lane, 6, 4);
++ r = FLD_MOD(r, data1_pol, 7, 7);
++ r = FLD_MOD(r, data2_lane, 10, 8);
++ r = FLD_MOD(r, data2_pol, 11, 11);
++ dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
++
++ /* The configuration of the DSI complex I/O (number of data lanes,
++ position, differential order) should not be changed while
++ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
++ the hardware to take into account a new configuration of the complex
++ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
++ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
++ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
++ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
++ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
++ DSI complex I/O configuration is unknown. */
++
++ /*
++ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++ REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
++ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++ */
++}
++
++static inline unsigned ns2ddr(unsigned ns)
++{
++ /* convert time in ns to ddr ticks, rounding up */
++ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
++}
++
++static inline unsigned ddr2ns(unsigned ddr)
++{
++ return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
++}
++
++static void dsi_complexio_timings(void)
++{
++ u32 r;
++ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
++ u32 tlpx_half, tclk_trail, tclk_zero;
++ u32 tclk_prepare;
++
++ /* calculate timings */
++
++ /* 1 * DDR_CLK = 2 * UI */
++
++ /* min 40ns + 4*UI max 85ns + 6*UI */
++ ths_prepare = ns2ddr(59) + 2;
++
++ /* min 145ns + 10*UI */
++ ths_prepare_ths_zero = ns2ddr(145) + 5;
++
++ /* min max(8*UI, 60ns+4*UI) */
++ ths_trail = max((unsigned)4, ns2ddr(60) + 2);
++
++ /* min 100ns */
++ ths_exit = ns2ddr(100);
++
++ /* tlpx min 50n */
++ tlpx_half = ns2ddr(25);
++
++ /* min 60ns */
++ tclk_trail = ns2ddr(60);
++
++ /* min 38ns, max 95ns */
++ tclk_prepare = ns2ddr(38);
++
++ /* min tclk-prepare + tclk-zero = 300ns */
++ tclk_zero = ns2ddr(300 - 38);
++
++ DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
++ ths_prepare, ddr2ns(ths_prepare),
++ ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
++ DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
++ ths_trail, ddr2ns(ths_trail),
++ ths_exit, ddr2ns(ths_exit));
++
++ DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
++ "tclk_zero %u (%uns)\n",
++ tlpx_half, ddr2ns(tlpx_half),
++ tclk_trail, ddr2ns(tclk_trail),
++ tclk_zero, ddr2ns(tclk_zero));
++ DSSDBG("tclk_prepare %u (%uns)\n",
++ tclk_prepare, ddr2ns(tclk_prepare));
++
++ /* program timings */
++
++ r = dsi_read_reg(DSI_DSIPHY_CFG0);
++ r = FLD_MOD(r, ths_prepare, 31, 24);
++ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
++ r = FLD_MOD(r, ths_trail, 15, 8);
++ r = FLD_MOD(r, ths_exit, 7, 0);
++ dsi_write_reg(DSI_DSIPHY_CFG0, r);
++
++ r = dsi_read_reg(DSI_DSIPHY_CFG1);
++ r = FLD_MOD(r, tlpx_half, 22, 16);
++ r = FLD_MOD(r, tclk_trail, 15, 8);
++ r = FLD_MOD(r, tclk_zero, 7, 0);
++ dsi_write_reg(DSI_DSIPHY_CFG1, r);
++
++ r = dsi_read_reg(DSI_DSIPHY_CFG2);
++ r = FLD_MOD(r, tclk_prepare, 7, 0);
++ dsi_write_reg(DSI_DSIPHY_CFG2, r);
++}
++
++
++static int dsi_complexio_init(struct omap_display *display)
++{
++ int r = 0;
++
++ DSSDBG("dsi_complexio_init\n");
++
++ /* CIO_CLK_ICG, enable L3 clk to CIO */
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
++
++ /* A dummy read using the SCP interface to any DSIPHY register is
++ * required after DSIPHY reset to complete the reset of the DSI complex
++ * I/O. */
++ dsi_read_reg(DSI_DSIPHY_CFG5);
++
++ if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
++ DSSERR("ComplexIO PHY not coming out of reset.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ dsi_complexio_config(display);
++
++ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
++
++ if (r)
++ goto err;
++
++ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
++ DSSERR("ComplexIO not coming out of reset.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
++ DSSERR("ComplexIO LDO power down.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ dsi_complexio_timings();
++
++ /*
++ The configuration of the DSI complex I/O (number of data lanes,
++ position, differential order) should not be changed while
++ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
++ hardware to recognize a new configuration of the complex I/O (done
++ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
++ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
++ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
++ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
++ bit to 1. If the sequence is not followed, the DSi complex I/O
++ configuration is undetermined.
++ */
++ dsi_if_enable(1);
++ dsi_if_enable(0);
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
++ dsi_if_enable(1);
++ dsi_if_enable(0);
++
++ DSSDBG("CIO init done\n");
++err:
++ return r;
++}
++
++static void dsi_complexio_uninit(void)
++{
++ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
++}
++
++static int _dsi_wait_reset(void)
++{
++ int i = 0;
++
++ while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
++ if (i++ > 5) {
++ DSSERR("soft reset failed\n");
++ return -ENODEV;
++ }
++ udelay(1);
++ }
++
++ return 0;
++}
++
++static int _dsi_reset(void)
++{
++ /* Soft reset */
++ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
++ return _dsi_wait_reset();
++}
++
++
++static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
++ enum fifo_size size3, enum fifo_size size4)
++{
++ u32 r = 0;
++ int add = 0;
++ int i;
++
++ dsi.vc[0].fifo_size = size1;
++ dsi.vc[1].fifo_size = size2;
++ dsi.vc[2].fifo_size = size3;
++ dsi.vc[3].fifo_size = size4;
++
++ for (i = 0; i < 4; i++) {
++ u8 v;
++ int size = dsi.vc[i].fifo_size;
++
++ if (add + size > 4) {
++ DSSERR("Illegal FIFO configuration\n");
++ BUG();
++ }
++
++ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++ r |= v << (8 * i);
++ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
++ add += size;
++ }
++
++ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
++}
++
++static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
++ enum fifo_size size3, enum fifo_size size4)
++{
++ u32 r = 0;
++ int add = 0;
++ int i;
++
++ dsi.vc[0].fifo_size = size1;
++ dsi.vc[1].fifo_size = size2;
++ dsi.vc[2].fifo_size = size3;
++ dsi.vc[3].fifo_size = size4;
++
++ for (i = 0; i < 4; i++) {
++ u8 v;
++ int size = dsi.vc[i].fifo_size;
++
++ if (add + size > 4) {
++ DSSERR("Illegal FIFO configuration\n");
++ BUG();
++ }
++
++ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++ r |= v << (8 * i);
++ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
++ add += size;
++ }
++
++ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
++}
++
++static int dsi_force_tx_stop_mode_io(void)
++{
++ u32 r;
++
++ r = dsi_read_reg(DSI_TIMING1);
++ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
++ dsi_write_reg(DSI_TIMING1, r);
++
++ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
++ DSSERR("TX_STOP bit not going down\n");
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static void dsi_vc_print_status(int channel)
++{
++ u32 r;
++
++ r = dsi_read_reg(DSI_VC_CTRL(channel));
++ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
++ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
++ channel,
++ FLD_GET(r, 5, 5),
++ FLD_GET(r, 6, 6),
++ FLD_GET(r, 15, 15),
++ FLD_GET(r, 16, 16),
++ FLD_GET(r, 20, 20));
++
++ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
++ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
++}
++
++static void dsi_vc_config(int channel)
++{
++ u32 r;
++
++ DSSDBG("dsi_vc_config %d\n", channel);
++
++ r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
++ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
++ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
++
++ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++ dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++static void dsi_vc_config_vp(int channel)
++{
++ u32 r;
++
++ DSSDBG("dsi_vc_config_vp\n");
++
++ r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
++ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
++ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
++
++ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++ dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++
++static int dsi_vc_enable(int channel, bool enable)
++{
++ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
++
++ enable = enable ? 1 : 0;
++
++ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
++
++ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
++ DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static void dsi_vc_enable_hs(int channel, bool enable)
++{
++ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
++
++ dsi_vc_enable(channel, 0);
++ dsi_if_enable(0);
++
++ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
++
++ dsi_vc_enable(channel, 1);
++ dsi_if_enable(1);
++
++ dsi_force_tx_stop_mode_io();
++}
++
++static void dsi_vc_flush_long_data(int channel)
++{
++ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++ u32 val;
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
++ (val >> 0) & 0xff,
++ (val >> 8) & 0xff,
++ (val >> 16) & 0xff,
++ (val >> 24) & 0xff);
++ }
++}
++
++static void dsi_show_rx_ack_with_err(u16 err)
++{
++ DSSERR("\tACK with ERROR (%#x):\n", err);
++ if (err & (1 << 0))
++ DSSERR("\t\tSoT Error\n");
++ if (err & (1 << 1))
++ DSSERR("\t\tSoT Sync Error\n");
++ if (err & (1 << 2))
++ DSSERR("\t\tEoT Sync Error\n");
++ if (err & (1 << 3))
++ DSSERR("\t\tEscape Mode Entry Command Error\n");
++ if (err & (1 << 4))
++ DSSERR("\t\tLP Transmit Sync Error\n");
++ if (err & (1 << 5))
++ DSSERR("\t\tHS Receive Timeout Error\n");
++ if (err & (1 << 6))
++ DSSERR("\t\tFalse Control Error\n");
++ if (err & (1 << 7))
++ DSSERR("\t\t(reserved7)\n");
++ if (err & (1 << 8))
++ DSSERR("\t\tECC Error, single-bit (corrected)\n");
++ if (err & (1 << 9))
++ DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
++ if (err & (1 << 10))
++ DSSERR("\t\tChecksum Error\n");
++ if (err & (1 << 11))
++ DSSERR("\t\tData type not recognized\n");
++ if (err & (1 << 12))
++ DSSERR("\t\tInvalid VC ID\n");
++ if (err & (1 << 13))
++ DSSERR("\t\tInvalid Transmission Length\n");
++ if (err & (1 << 14))
++ DSSERR("\t\t(reserved14)\n");
++ if (err & (1 << 15))
++ DSSERR("\t\tDSI Protocol Violation\n");
++}
++
++static u16 dsi_vc_flush_receive_data(int channel)
++{
++ /* RX_FIFO_NOT_EMPTY */
++ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++ u32 val;
++ u8 dt;
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ DSSDBG("\trawval %#08x\n", val);
++ dt = FLD_GET(val, 5, 0);
++ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++ u16 err = FLD_GET(val, 23, 8);
++ dsi_show_rx_ack_with_err(err);
++ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
++ DSSDBG("\tDCS short response, 1 byte: %#x\n",
++ FLD_GET(val, 23, 8));
++ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
++ DSSDBG("\tDCS short response, 2 byte: %#x\n",
++ FLD_GET(val, 23, 8));
++ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++ DSSDBG("\tDCS long response, len %d\n",
++ FLD_GET(val, 23, 8));
++ dsi_vc_flush_long_data(channel);
++ } else {
++ DSSERR("\tunknown datatype 0x%02x\n", dt);
++ }
++ }
++ return 0;
++}
++
++static int dsi_vc_send_bta(int channel)
++{
++ unsigned long tmo;
++
++ /*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
++
++ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
++ DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
++ dsi_vc_flush_receive_data(channel);
++ }
++
++ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
++
++ tmo = jiffies + msecs_to_jiffies(10);
++ while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
++ if (time_after(jiffies, tmo)) {
++ DSSERR("Failed to send BTA\n");
++ return -EIO;
++ }
++ }
++
++ return 0;
++}
++
++static int dsi_vc_send_bta_sync(int channel)
++{
++ int r = 0;
++
++ init_completion(&dsi.bta_completion);
++
++ dsi_vc_enable_bta_irq(channel);
++
++ r = dsi_vc_send_bta(channel);
++ if (r)
++ goto err;
++
++ if (wait_for_completion_timeout(&dsi.bta_completion,
++ msecs_to_jiffies(500)) == 0) {
++ DSSERR("Failed to receive BTA\n");
++ r = -EIO;
++ goto err;
++ }
++err:
++ dsi_vc_disable_bta_irq(channel);
++
++ return r;
++}
++
++static inline void dsi_vc_write_long_header(int channel, u8 data_type,
++ u16 len, u8 ecc)
++{
++ u32 val;
++ u8 data_id;
++
++ /*data_id = data_type | channel << 6; */
++ data_id = data_type | dsi.vc[channel].dest_per << 6;
++
++ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
++ FLD_VAL(ecc, 31, 24);
++
++ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
++}
++
++static inline void dsi_vc_write_long_payload(int channel,
++ u8 b1, u8 b2, u8 b3, u8 b4)
++{
++ u32 val;
++
++ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
++
++/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
++ b1, b2, b3, b4, val); */
++
++ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
++}
++
++static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
++ u8 ecc)
++{
++ /*u32 val; */
++ int i;
++ u8 *p;
++ int r = 0;
++ u8 b1, b2, b3, b4;
++
++ if (dsi.debug_write)
++ DSSDBG("dsi_vc_send_long, %d bytes\n", len);
++
++ /* len + header */
++ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
++ DSSERR("unable to send long packet: packet too long.\n");
++ return -EINVAL;
++ }
++
++ dsi_vc_write_long_header(channel, data_type, len, ecc);
++
++ /*dsi_vc_print_status(0); */
++
++ p = data;
++ for (i = 0; i < len >> 2; i++) {
++ if (dsi.debug_write)
++ DSSDBG("\tsending full packet %d\n", i);
++ /*dsi_vc_print_status(0); */
++
++ b1 = *p++;
++ b2 = *p++;
++ b3 = *p++;
++ b4 = *p++;
++
++ dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
++ }
++
++ i = len % 4;
++ if (i) {
++ b1 = 0; b2 = 0; b3 = 0;
++
++ if (dsi.debug_write)
++ DSSDBG("\tsending remainder bytes %d\n", i);
++
++ switch (i) {
++ case 3:
++ b1 = *p++;
++ b2 = *p++;
++ b3 = *p++;
++ break;
++ case 2:
++ b1 = *p++;
++ b2 = *p++;
++ break;
++ case 1:
++ b1 = *p++;
++ break;
++ }
++
++ dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
++ }
++
++ return r;
++}
++
++static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
++{
++ u32 r;
++ u8 data_id;
++
++ if (dsi.debug_write)
++ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
++ channel,
++ data_type, data & 0xff, (data >> 8) & 0xff);
++
++ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
++ DSSERR("ERROR FIFO FULL, aborting transfer\n");
++ return -EINVAL;
++ }
++
++ data_id = data_type | channel << 6;
++
++ r = (data_id << 0) | (data << 8) | (ecc << 24);
++
++ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
++
++ return 0;
++}
++
++int dsi_vc_send_null(int channel)
++{
++ u8 nullpkg[] = {0, 0, 0, 0};
++ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
++}
++EXPORT_SYMBOL(dsi_vc_send_null);
++
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
++{
++ int r;
++
++ BUG_ON(len == 0);
++
++ if (len == 1) {
++ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
++ data[0], 0);
++ } else if (len == 2) {
++ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
++ data[0] | (data[1] << 8), 0);
++ } else {
++ /* 0x39 = DCS Long Write */
++ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
++ data, len, 0);
++ }
++
++ return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
++
++int dsi_vc_dcs_write(int channel, u8 *data, int len)
++{
++ int r;
++
++ r = dsi_vc_dcs_write_nosync(channel, data, len);
++ if (r)
++ return r;
++
++ /* Some devices need time to process the msg in low power mode.
++ This also makes the write synchronous, and checks that
++ the peripheral is still alive */
++ r = dsi_vc_send_bta_sync(channel);
++
++ return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write);
++
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
++{
++ u32 val;
++ u8 dt;
++ int r;
++
++ if (dsi.debug_read)
++ DSSDBG("dsi_vc_dcs_read\n");
++
++ r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
++ if (r)
++ return r;
++
++ r = dsi_vc_send_bta_sync(channel);
++ if (r)
++ return r;
++
++ if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { /* RX_FIFO_NOT_EMPTY */
++ DSSERR("RX fifo empty when trying to read.\n");
++ return -EIO;
++ }
++
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ if (dsi.debug_read)
++ DSSDBG("\theader: %08x\n", val);
++ dt = FLD_GET(val, 5, 0);
++ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++ u16 err = FLD_GET(val, 23, 8);
++ dsi_show_rx_ack_with_err(err);
++ return -1;
++
++ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
++ u8 data = FLD_GET(val, 15, 8);
++ if (dsi.debug_read)
++ DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
++
++ if (buflen < 1)
++ return -1;
++
++ buf[0] = data;
++
++ return 1;
++ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
++ u16 data = FLD_GET(val, 23, 8);
++ if (dsi.debug_read)
++ DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
++
++ if (buflen < 2)
++ return -1;
++
++ buf[0] = data & 0xff;
++ buf[1] = (data >> 8) & 0xff;
++
++ return 2;
++ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++ int w;
++ int len = FLD_GET(val, 23, 8);
++ if (dsi.debug_read)
++ DSSDBG("\tDCS long response, len %d\n", len);
++
++ if (len > buflen)
++ return -1;
++
++ /* two byte checksum ends the packet, not included in len */
++ for (w = 0; w < len + 2;) {
++ int b;
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ if (dsi.debug_read)
++ DSSDBG("\t\t%02x %02x %02x %02x\n",
++ (val >> 0) & 0xff,
++ (val >> 8) & 0xff,
++ (val >> 16) & 0xff,
++ (val >> 24) & 0xff);
++
++ for (b = 0; b < 4; ++b) {
++ if (w < len)
++ buf[w] = (val >> (b * 8)) & 0xff;
++ /* we discard the 2 byte checksum */
++ ++w;
++ }
++ }
++
++ return len;
++
++ } else {
++ DSSERR("\tunknown datatype 0x%02x\n", dt);
++ return -1;
++ }
++}
++EXPORT_SYMBOL(dsi_vc_dcs_read);
++
++
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
++{
++ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
++ len, 0);
++}
++EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
++
++
++static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in DSI_FCK */
++
++ fck = dsi_fclk_rate();
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("LP_TX_TO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING2);
++ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
++ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
++ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
++ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
++ dsi_write_reg(DSI_TIMING2, r);
++
++ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++
++static int dsi_set_ta_timeout(int ns, int x8, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in DSI_FCK */
++
++ fck = dsi_fclk_rate();
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("TA_TO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING1);
++ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
++ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
++ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
++ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
++ dsi_write_reg(DSI_TIMING1, r);
++
++ DSSDBG("TA_TO %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++
++static int dsi_set_stop_state_counter(int ns, int x4, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in DSI_FCK */
++
++ fck = dsi_fclk_rate();
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("STOP_STATE_COUNTER_IO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING1);
++ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
++ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
++ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
++ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
++ dsi_write_reg(DSI_TIMING1, r);
++
++ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++
++static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in TxByteClkHS */
++
++ fck = dsi.ddr_clk / 4;
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("HS_TX_TO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING2);
++ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
++ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
++ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
++ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
++ dsi_write_reg(DSI_TIMING2, r);
++
++ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++static int dsi_proto_config(struct omap_display *display)
++{
++ u32 r;
++ int buswidth = 0;
++
++ dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0);
++
++ dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0);
++
++ /* XXX what values for the timeouts? */
++ dsi_set_stop_state_counter(1000, 0, 0);
++
++ dsi_set_ta_timeout(50000, 1, 1);
++
++ /* 3000ns * 16 */
++ dsi_set_lp_rx_timeout(3000, 0, 1);
++
++ /* 10000ns * 4 */
++ dsi_set_hs_tx_timeout(10000, 1, 0);
++
++ switch (display->ctrl->pixel_size) {
++ case 16:
++ buswidth = 0;
++ break;
++ case 18:
++ buswidth = 1;
++ break;
++ case 24:
++ buswidth = 2;
++ break;
++ default:
++ BUG();
++ }
++
++ r = dsi_read_reg(DSI_CTRL);
++ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
++ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
++ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
++ /* XXX what should the ratio be */
++ r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
++ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
++ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
++ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
++ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
++ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
++ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
++ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
++
++ dsi_write_reg(DSI_CTRL, r);
++
++ /* we configure vc0 for L4 communication, and
++ * vc1 for dispc */
++ dsi_vc_config(0);
++ dsi_vc_config_vp(1);
++
++ /* set all vc targets to peripheral 0 */
++ dsi.vc[0].dest_per = 0;
++ dsi.vc[1].dest_per = 0;
++ dsi.vc[2].dest_per = 0;
++ dsi.vc[3].dest_per = 0;
++
++ return 0;
++}
++
++static void dsi_proto_timings(void)
++{
++ int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
++ int tclk_pre, tclk_post;
++ int ddr_clk_pre, ddr_clk_post;
++ u32 r;
++
++ r = dsi_read_reg(DSI_DSIPHY_CFG1);
++ tlpx_half = FLD_GET(r, 22, 16);
++ tclk_trail = FLD_GET(r, 15, 8);
++ tclk_zero = FLD_GET(r, 7, 0);
++
++ r = dsi_read_reg(DSI_DSIPHY_CFG2);
++ tclk_prepare = FLD_GET(r, 7, 0);
++
++ /* min 8*UI */
++ tclk_pre = 20;
++ /* min 60ns + 52*UI */
++ tclk_post = ns2ddr(60) + 26;
++
++ ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
++ ddr_clk_post = (tclk_post + tclk_trail) / 4;
++
++ r = dsi_read_reg(DSI_CLK_TIMING);
++ r = FLD_MOD(r, ddr_clk_pre, 15, 8);
++ r = FLD_MOD(r, ddr_clk_post, 7, 0);
++ dsi_write_reg(DSI_CLK_TIMING, r);
++
++ DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
++ ddr_clk_pre,
++ ddr_clk_post);
++}
++
++
++#define DSI_DECL_VARS \
++ int __dsi_cb = 0; u32 __dsi_cv = 0;
++
++#define DSI_FLUSH(ch) \
++ if (__dsi_cb > 0) { \
++ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
++ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
++ __dsi_cb = __dsi_cv = 0; \
++ }
++
++#define DSI_PUSH(ch, data) \
++ do { \
++ __dsi_cv |= (data) << (__dsi_cb * 8); \
++ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
++ if (++__dsi_cb > 3) \
++ DSI_FLUSH(ch); \
++ } while (0)
++
++static int dsi_update_screen_l4(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ /* Note: supports only 24bit colors in 32bit container */
++ int first = 1;
++ int fifo_stalls = 0;
++ int max_dsi_packet_size;
++ int max_data_per_packet;
++ int max_pixels_per_packet;
++ int pixels_left;
++ int bytespp = 3;
++ int scr_width;
++ u32 __iomem *data;
++ int start_offset;
++ int horiz_inc;
++ int current_x;
++ struct omap_overlay *ovl;
++
++ debug_irq = 0;
++
++ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
++ x, y, w, h);
++
++ ovl = display->manager->overlays[0];
++
++ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
++ return -EINVAL;
++
++ if (display->ctrl->pixel_size != 24)
++ return -EINVAL;
++
++ scr_width = ovl->info.screen_width;
++ data = ovl->info.vaddr;
++
++ start_offset = scr_width * y + x;
++ horiz_inc = scr_width - w;
++ current_x = x;
++
++ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
++ * in fifo */
++
++ /* When using CPU, max long packet size is TX buffer size */
++ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++ /* we seem to get better perf if we divide the tx fifo to half,
++ and while the other half is being sent, we fill the other half
++ max_dsi_packet_size /= 2; */
++
++ max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++ max_pixels_per_packet = max_data_per_packet / bytespp;
++
++ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
++
++ display->ctrl->setup_update(display, x, y, w, h);
++
++ pixels_left = w * h;
++
++ DSSDBG("total pixels %d\n", pixels_left);
++
++ data += start_offset;
++
++ dsi.update_region.x = x;
++ dsi.update_region.y = y;
++ dsi.update_region.w = w;
++ dsi.update_region.h = h;
++ dsi.update_region.bytespp = bytespp;
++
++ perf_mark_start();
++
++ while (pixels_left > 0) {
++ /* 0x2c = write_memory_start */
++ /* 0x3c = write_memory_continue */
++ u8 dcs_cmd = first ? 0x2c : 0x3c;
++ int pixels;
++ DSI_DECL_VARS;
++ first = 0;
++
++#if 1
++ /* using fifo not empty */
++ /* TX_FIFO_NOT_EMPTY */
++ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++ udelay(1);
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow, pixels left %d\n",
++ pixels_left);
++ dsi_if_enable(0);
++ return -EIO;
++ }
++ }
++#elif 1
++ /* using fifo emptiness */
++ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
++ max_dsi_packet_size) {
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow, pixels left %d\n",
++ pixels_left);
++ dsi_if_enable(0);
++ return -EIO;
++ }
++ }
++#else
++ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow, pixels left %d\n",
++ pixels_left);
++ dsi_if_enable(0);
++ return -EIO;
++ }
++ }
++#endif
++ pixels = min(max_pixels_per_packet, pixels_left);
++
++ pixels_left -= pixels;
++
++ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++ 1 + pixels * bytespp, 0);
++
++ DSI_PUSH(0, dcs_cmd);
++
++ while (pixels-- > 0) {
++ u32 pix = __raw_readl(data++);
++
++ DSI_PUSH(0, (pix >> 16) & 0xff);
++ DSI_PUSH(0, (pix >> 8) & 0xff);
++ DSI_PUSH(0, (pix >> 0) & 0xff);
++
++ current_x++;
++ if (current_x == x+w) {
++ current_x = x;
++ data += horiz_inc;
++ }
++ }
++
++ DSI_FLUSH(0);
++ }
++
++ perf_show("L4");
++
++ return 0;
++}
++
++#if 0
++static void dsi_clear_screen_l4(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ int first = 1;
++ int fifo_stalls = 0;
++ int max_dsi_packet_size;
++ int max_data_per_packet;
++ int max_pixels_per_packet;
++ int pixels_left;
++ int bytespp = 3;
++ int pixnum;
++
++ debug_irq = 0;
++
++ DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
++ x, y, w, h);
++
++ if (display->ctrl->bpp != 24)
++ return -EINVAL;
++
++