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authormlafauci <mlafauci@metodo2.it>2011-11-06 19:38:04 +0100
committerMarco Cavallini <m.cavallini@koansoftware.com>2011-11-08 10:41:16 +0100
commit7df45fe1e077a64f589c56d27a2389c45beab508 (patch)
tree2131f0d37e0f92776def7661d57e247364f1e872
parent1960f4e4efc7ef830cb12c9cd366e77d0793005c (diff)
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at91bootstrap: Add VulcanoG20 board support
Signed-off-by: Marco Cavallini <m.cavallini@koansoftware.com>
-rw-r--r--recipes/at91bootstrap/at91bootstrap-3.0/vG20/0001-at91bootstrap-Add-VulcanoG20-support-on-common-files.patch1213
-rw-r--r--recipes/at91bootstrap/at91bootstrap-3.0/vG20/0002-at91bootstrap-Add-VulcanoG20-board.patch1310
-rw-r--r--recipes/at91bootstrap/at91bootstrap_3.0.bb5
3 files changed, 2528 insertions, 0 deletions
diff --git a/recipes/at91bootstrap/at91bootstrap-3.0/vG20/0001-at91bootstrap-Add-VulcanoG20-support-on-common-files.patch b/recipes/at91bootstrap/at91bootstrap-3.0/vG20/0001-at91bootstrap-Add-VulcanoG20-support-on-common-files.patch
new file mode 100644
index 0000000000..a70fdcb1df
--- /dev/null
+++ b/recipes/at91bootstrap/at91bootstrap-3.0/vG20/0001-at91bootstrap-Add-VulcanoG20-support-on-common-files.patch
@@ -0,0 +1,1213 @@
+From 70addf1fe62452b529175329b574002ac142f5bb Mon Sep 17 00:00:00 2001
+From: mlafauci <mlafauci@metodo2.it>
+Date: Sun, 6 Nov 2011 19:33:28 +0100
+Subject: [PATCH 1/2] at91bootstrap: Add VulcanoG20 support on common files
+
+---
+ Config.in | 28 ++-
+ board/Config.in | 34 ++-
+ board/boards | 1 +
+ driver/dataflash.c | 720 ++++++++++++++++++++++++++--------------------------
+ include/nand_ids.h | 23 +-
+ include/part.h | 14 +-
+ 6 files changed, 430 insertions(+), 390 deletions(-)
+
+diff --git a/Config.in b/Config.in
+index 0ef8da1..139fb1d 100644
+--- a/Config.in
++++ b/Config.in
+@@ -120,11 +120,12 @@ config CONFIG_OS_MEM_BANK
+ default "0x70000000" if CONFIG_AT91SAM9G45EKES
+ default "0x70000000" if CONFIG_AT91SAM9M10EK
+ default "0x70000000" if CONFIG_AT91SAM9M10EKES
+-
++ default "0x20000000" if CONFIG_VULCANOG20
++
+ config CONFIG_OS_MEM_SIZE
+ string "OS Memory Bank Size"
+ default "0x4000000"
+-
++
+ config CONFIG_LINUX_KERNEL_ARG_STRING
+ string "Linux kernel parameters"
+ default "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap),60M(rootfs),-(spare) root=/dev/mtdblock1 rw rootfstype=jffs2" if CONFIG_AT91SAM9260EK && !CONFIG_SDCARD
+@@ -138,6 +139,7 @@ config CONFIG_LINUX_KERNEL_ARG_STRING
+ default "mem=128M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap),60M(rootfs),-(spare) root=/dev/mtdblock1 rw rootfstype=jffs2" if CONFIG_AT91SAM9G45EKES && !CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap),60M(rootfs),-(spare) root=/dev/mtdblock1 rw rootfstype=jffs2" if CONFIG_AT91SAM9M10EK && !CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap),60M(rootfs),-(spare) root=/dev/mtdblock1 rw rootfstype=jffs2" if CONFIG_AT91SAM9M10EKES && !CONFIG_SDCARD
++ default "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap),60M(rootfs),-(spare) root=/dev/mtdblock1 rw rootfstype=jffs2" if CONFIG_VULCANOG20 && !CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9RLEK && CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9G10EK && CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9G20EK && CONFIG_SDCARD
+@@ -146,6 +148,7 @@ config CONFIG_LINUX_KERNEL_ARG_STRING
+ default "mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9G45EKES && CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9M10EK && CONFIG_SDCARD
+ default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_AT91SAM9M10EKES && CONFIG_SDCARD
++ default "mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2" if CONFIG_VULCANOG20 && CONFIG_SDCARD
+
+ config CONFIG_OS_IMAGE_NAME
+ depends on CONFIG_SDCARD && CONFIG_AT91SAM9G10EK
+@@ -183,7 +186,8 @@ config CONFIG_OS_MEM_BANK
+ default "0x70000000" if CONFIG_AT91SAM9G45EKES
+ default "0x70000000" if CONFIG_AT91SAM9M10EK
+ default "0x70000000" if CONFIG_AT91SAM9M10EKES
+-
++ default "0x20000000" if CONFIG_VULCANOG20
++
+ config CONFIG_OS_MEM_SIZE
+ string "OS Memory Bank Size"
+ default "0x4000000"
+@@ -200,6 +204,7 @@ config CONFIG_CE_LOAD_ADDR
+ default "1879490560" if CONFIG_AT91SAM9G45EKES
+ default "1879490560" if CONFIG_AT91SAM9M10EK
+ default "1879490560" if CONFIG_AT91SAM9M10EKES
++ default "537292800" if CONFIG_VULCANOG20
+
+ config CONFIG_OS_IMAGE_NAME
+ depends on CONFIG_SDCARD
+@@ -263,9 +268,9 @@ config CONFIG_SETTING_ADDRESS
+
+ config CONFIG_SETTING_SIZE
+ string
+- default "0x00001000"
+- help
+-
++ default "0x00001000"
++ help
++
+ config CONFIG_IMG_SIZE
+ string
+ default "0x00040000" if CONFIG_LOAD_UBOOT || CONFIG_LOAD_EBOOT
+@@ -305,10 +310,11 @@ config CONFIG_JUMP_ADDR
+ default "0x20067000" if CONFIG_AT91SAM9260EK
+ default "0x2006c000" if CONFIG_AT91SAM9RLEK
+ default "0x20069000" if CONFIG_AT91SAM9G10EK
++ default "0x20067000" if CONFIG_VULCANOG20
+ default "0x23F00000"
+ help
+ The entry point to which the bootstrap will pass control.
+-
++
+ config CONFIG_JUMP_ADDR
+ string
+ depends on CONFIG_LOAD_LINUX
+@@ -324,6 +330,7 @@ config CONFIG_JUMP_ADDR
+ default "0x22000000" if CONFIG_AT91SAM9260EK
+ default "0x22000000" if CONFIG_AT91SAM9RLEK
+ default "0x22000000" if CONFIG_AT91SAM9G10EK
++ default "0x22000000" if CONFIG_VULCANOG20
+ default "0x22000000"
+ help
+ The entry point to which the bootstrap will pass control.
+@@ -365,6 +372,7 @@ config CONFIG_GLBDRV_ADDR
+ default "0x20058000" if CONFIG_AT91SAM9260EK
+ default "0x2006b000" if CONFIG_AT91SAM9RLEK
+ default "0x20068000" if CONFIG_AT91SAM9G10EK
++ default "0x20058000" if CONFIG_VULCANOG20
+ default "0x23F00000"
+ help
+
+@@ -372,7 +380,7 @@ config CONFIG_LONG_TEST
+ bool "Perform a memory test at startup"
+ default n
+ help
+-
++
+ config CONFIG_DEBUG
+ bool "Debug Support"
+ default n
+@@ -408,10 +416,10 @@ config CONFIG_THUMB
+ help
+ Build code in thumb mode
+
+-config CONFIG_SCLK
++config CONFIG_SCLK
+ depends on CONFIG_AT91SAM9RLEK || CONFIG_AT91SAM9G45EK || CONFIG_AT91SAM9G45EKES || CONFIG_AT91SAM9M10EK || CONFIG_AT91SAM9M10EKES
+ bool "Use external 32KHZ oscillator as source of slow clock"
+ help
+ Use external 32KHZ oscillator as source of slow clock
+-
++
+ source "host-utilities/Config.in"
+diff --git a/board/Config.in b/board/Config.in
+index 78ac102..71633ba 100644
+--- a/board/Config.in
++++ b/board/Config.in
+@@ -46,7 +46,7 @@ config CONFIG_AT91SAM9263EK
+ select CONFIG_SDRAM
+ select ALLOW_DATAFLASH
+ select ALLOW_NANDFLASH
+- select ALLOW_SDCARD
++ select ALLOW_SDCARD
+ select ALLOW_PSRAM
+ select ALLOW_SDRAM_16BIT
+ select DATAFLASHCARD_ON_CS0
+@@ -222,6 +222,21 @@ config CONFIG_AFEB9260
+ help
+ Use the AFEB9260 Development board
+
++config CONFIG_VULCANOG20
++ bool "vulcano-g20"
++ select CONFIG_SDRAM
++ select ALLOW_DATAFLASH
++ select ALLOW_NANDFLASH
++ select ALLOW_SDCARD
++ select DATAFLASHCARD_ON_CS0
++ select ALLOW_CPU_CLK_400MHZ
++ select ALLOW_CRYSTAL_18_432MHZ
++ select ALLOW_BOOT_FROM_DATAFLASH_CS0
++ select ALLOW_BOOT_FROM_DATAFLASH_CS1
++ select ALLOW_DATAFLASH_RECOVERY
++ help
++ Use the VULCANO-G20 board
++
+ endchoice
+
+ config CONFIG_CHIP
+@@ -240,6 +255,7 @@ config CONFIG_CHIP
+ default "AT91CAP9" if CONFIG_AT91CAP9ADK
+ default "AT91CAP9" if CONFIG_AT91CAP9STK
+ default "AT91SAM9260" if CONFIG_AFEB9260
++ default "AT91SAM9G20" if CONFIG_VULCANOG20
+ help
+ Name of the board, A Board Support package
+ (BSP) must be available.
+@@ -260,6 +276,7 @@ config CONFIG_BOARD
+ default "at91cap9adk" if CONFIG_AT91CAP9ADK
+ default "at91cap9stk" if CONFIG_AT91CAP9STK
+ default "afeb9260" if CONFIG_AFEB9260
++ default "vulcano-g20" if CONFIG_VULCANOG20
+ help
+ Name of the board, A Board Support package
+ (BSP) must be available.
+@@ -268,12 +285,12 @@ config CONFIG_MACH_TYPE
+ string
+ default "0x44B" if CONFIG_AT91SAM9260EK
+ default "0x350" if CONFIG_AT91SAM9261EK
+- default "0x4B2" if CONFIG_AT91SAM9263EK
++ default "0x4B2" if CONFIG_AT91SAM9263EK
+ default "1326" if CONFIG_AT91SAM9RLEK
+ default "0x44B" if CONFIG_AT91SAM9XEEK
+- default "0x86F" if CONFIG_AT91SAM9G10EK
++ default "0x86F" if CONFIG_AT91SAM9G10EK
+ default "0x658" if CONFIG_AT91SAM9G20EK
+- default "1830" if CONFIG_AT91SAM9G45EK # 1830
++ default "1830" if CONFIG_AT91SAM9G45EK # 1830
+ default "2212" if CONFIG_AT91SAM9G45EKES # 2212
+ default "1830" if CONFIG_AT91SAM9M10EK # 1830
+ default "2509" if CONFIG_AT91SAM9M10EKES # 2509
+@@ -281,6 +298,8 @@ config CONFIG_MACH_TYPE
+ default "0x85E" if CONFIG_AT91CAP9STK # 2142
+ default "0x676" if CONFIG_AT572D940DOM # 1654
+ default "1859" if CONFIG_AFEB9260
++ default "0x658" if CONFIG_VULCANOG20
++
+ help
+
+ config CONFIG_LINK_ADDR
+@@ -295,7 +314,7 @@ config CONFIG_DATA_SECTION_ADDR
+
+ # default "0x200000" if CONFIG_AT91SAM9260EK
+ # default "0x300000" if CONFIG_AT91SAM9261EK
+-# default "0x300000" if CONFIG_AT91SAM9263EK
++# default "0x300000" if CONFIG_AT91SAM9263EK
+ # default "0x300000" if CONFIG_AT91SAM9RLEK
+ # default "0x200000" if CONFIG_AT91SAM9XEEK
+ # default "0x200000" if CONFIG_AT91SAM9G20EK
+@@ -305,10 +324,10 @@ config CONFIG_DATA_SECTION_ADDR
+ # default "0x200000" if CONFIG_AFEB9260
+
+ config CONFIG_TOP_OF_MEMORY
+- string
++ string
+ default "0x301000" if CONFIG_AT91SAM9260EK
+ default "0x328000" if CONFIG_AT91SAM9261EK
+- default "0x314000" if CONFIG_AT91SAM9263EK
++ default "0x314000" if CONFIG_AT91SAM9263EK
+ default "0x310000" if CONFIG_AT91SAM9RLEK
+ default "0x306000" if CONFIG_AT91SAM9XEEK
+ default "0x304000" if CONFIG_AT91SAM9G10EK
+@@ -320,6 +339,7 @@ config CONFIG_TOP_OF_MEMORY
+ default "0x108000" if CONFIG_AT91CAP9ADK
+ default "0x108000" if CONFIG_AT91CAP9STK
+ default "0x301000" if CONFIG_AFEB9260
++ default "0x304000" if CONFIG_VULCANOG20
+ help
+
+ choice
+diff --git a/board/boards b/board/boards
+index 9da6dd4..b58fc04 100644
+--- a/board/boards
++++ b/board/boards
+@@ -39,3 +39,4 @@ at91sam9xeek/at91sam9xedfc_defconfig
+ at91sam9xeek/at91sam9xedf_defconfig
+ at91sam9xeek/at91sam9xeek_defconfig
+ at91sam9xeek/at91sam9xenf_defconfig
++vulcano-g20/vulcano-g20_defconfig
+diff --git a/driver/dataflash.c b/driver/dataflash.c
+index 3c5e1fd..daa5372 100644
+--- a/driver/dataflash.c
++++ b/driver/dataflash.c
+@@ -1,5 +1,5 @@
+ /* ----------------------------------------------------------------------------
+- * ATMEL Microcontroller Software Support - ROUSSET -
++ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+
+@@ -25,9 +25,9 @@
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+- * File Name : dataflash.c
+- * Object : ATMEL DataFlash High level functions
+- * Creation : NLe Jul 12th 2006
++ * File Name : dataflash.c
++ * Object : ATMEL DataFlash High level functions
++ * Creation : NLe Jul 12th 2006
+ *---------------------------------------------------------------------------
+ */
+
+@@ -45,426 +45,432 @@ extern div_t udiv(unsigned int dividend, unsigned int divisor);
+ /* Write SPI register */
+ static inline void write_spi(unsigned int offset, const unsigned int value)
+ {
+- writel(value, offset + AT91C_BASE_SPI);
++ writel(value, offset + AT91C_BASE_SPI);
+ }
+
+ /* Read SPI registers */
+ static inline unsigned int read_spi(unsigned int offset)
+ {
+- return readl(offset + AT91C_BASE_SPI);
++ return readl(offset + AT91C_BASE_SPI);
+ }
+
+ static void msg_df_detect(int i)
+ {
+ #if defined(CONFIG_VERBOSE)
+- char *pn;
+- switch (i) {
+- case AT45DB011D:
+- pn = "011D";
+- break;
+- case AT45DB021D:
+- pn = "021D";
+- break;
+- case AT45DB041D:
+- pn = "041D";
+- break;
+- case AT45DB081D:
+- pn = "081D";
+- break;
+- case AT45DB161D:
+- pn = "161D";
+- break;
+- case AT45DB321D:
+- pn = "321D";
+- break;
+- case AT45DB642D:
+- pn = "642D";
+- break;
+- default:
+- pn = "????";
+- break;
+- }
+- dbgu_print(pn);
+- dbgu_print("detected\r\n");
++ char *pn;
++ switch (i) {
++ case AT45DB011D:
++ pn = "011D";
++ break;
++ case AT45DB021D:
++ pn = "021D";
++ break;
++ case AT45DB041D:
++ pn = "041D";
++ break;
++ case AT45DB081D:
++ pn = "081D";
++ break;
++ case AT45DB161D:
++ pn = "161D";
++ break;
++ case AT45DB321D:
++ pn = "321D";
++ break;
++ case AT45DB642D:
++ pn = "642D";
++ break;
++ default:
++ pn = "????";
++ break;
++ }
++ dbgu_print(pn);
++ dbgu_print("detected\r\n");
+ #endif
+ }
+
+ /*------------------------------------------------------------------------------*/
+-/* \fn df_spi_init */
++/* \fn df_spi_init */
+ /* \brief Configure SPI */
+ /*------------------------------------------------------------------------------*/
+ static int df_spi_init(unsigned int pcs, unsigned int spi_csr)
+ {
+- unsigned int ncs = 0;
+-
+- /*
+- * Open PIO for SPI0
+- */
+- df_hw_init();
+-
+- /*
+- * Enables the SPI0 Clock
+- */
+- writel((1 << AT91C_ID_SPI), PMC_PCER + AT91C_BASE_PMC);
+-
+- /*
+- * Reset SPI0
+- */
+- write_spi(SPI_CR, AT91C_SPI_SWRST);
+- /*
+- * SPI may need two software reset
+- */
+- write_spi(SPI_CR, AT91C_SPI_SWRST);
+-
+- /*
+- * Configure SPI0 in Master Mode with No CS selected
+- */
+- write_spi(SPI_MR, AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS);
+-
+- switch (pcs) {
+- case AT91C_SPI_PCS0_DATAFLASH:
+- ncs = 0;
+- break;
+- case AT91C_SPI_PCS1_DATAFLASH:
+- ncs = 1;
+- break;
+- case AT91C_SPI_PCS2_DATAFLASH:
+- ncs = 2;
+- break;
+- case AT91C_SPI_PCS3_DATAFLASH:
+- ncs = 3;
+- break;
+- }
+- /*
+- * Configure CSx
+- */
+- write_spi(SPI_CSR + 4 * ncs, spi_csr);
+-
+- /*
+- * Choose CSx
+- */
+- write_spi(SPI_MR, read_spi(SPI_MR) & 0xFFF0FFFF);
+- write_spi(SPI_MR, read_spi(SPI_MR) | ((pcs << 16) & AT91C_SPI_PCS));
+-
+- /*
+- * SPI_Enable
+- */
+- write_spi(SPI_CR, AT91C_SPI_SPIEN);
+-
+- return SUCCESS;
++ unsigned int ncs = 0;
++
++ /*
++ * Open PIO for SPI0
++ */
++ df_hw_init();
++
++ /*
++ * Enables the SPI0 Clock
++ */
++ writel((1 << AT91C_ID_SPI), PMC_PCER + AT91C_BASE_PMC);
++
++ /*
++ * Reset SPI0
++ */
++ write_spi(SPI_CR, AT91C_SPI_SWRST);
++ /*
++ * SPI may need two software reset
++ */
++ write_spi(SPI_CR, AT91C_SPI_SWRST);
++
++ /*
++ * Configure SPI0 in Master Mode with No CS selected
++ */
++ write_spi(SPI_MR, AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS);
++
++ switch (pcs) {
++ case AT91C_SPI_PCS0_DATAFLASH:
++ ncs = 0;
++ break;
++ case AT91C_SPI_PCS1_DATAFLASH:
++ ncs = 1;
++ break;
++ case AT91C_SPI_PCS2_DATAFLASH:
++ ncs = 2;
++ break;
++ case AT91C_SPI_PCS3_DATAFLASH:
++ ncs = 3;
++ break;
++ }
++ /*
++ * Configure CSx
++ */
++ write_spi(SPI_CSR + 4 * ncs, spi_csr);
++
++ /*
++ * Choose CSx
++ */
++ write_spi(SPI_MR, read_spi(SPI_MR) & 0xFFF0FFFF);
++ write_spi(SPI_MR, read_spi(SPI_MR) | ((pcs << 16) & AT91C_SPI_PCS));
++
++ /*
++ * SPI_Enable
++ */
++ write_spi(SPI_CR, AT91C_SPI_SPIEN);
++
++ return SUCCESS;
+ }
+
+ /*------------------------------------------------------------------------------*/
+-/* \fn df_is_busy */
++/* \fn df_is_busy */
+ /* \brief Test if SPI has received a buffer or not */
+ /*------------------------------------------------------------------------------*/
+ static AT91S_DF_SEM df_is_busy(AT91PS_DF pDataFlash)
+ {
+- unsigned int dStatus = read_spi(SPI_SR);
+-
+- /*
+- * If End of Receive Transfer interrupt occurred
+- */
+- if ((dStatus & AT91C_SPI_RXBUFF)) {
+- write_spi(SPI_PTCR, AT91C_PDC_TXTDIS); /* PDC Disable Tx */
+- write_spi(SPI_PTCR, AT91C_PDC_RXTDIS); /* PDC Disable Rx */
+-
+- /*
+- * Release the semaphore
+- */
+- pDataFlash->bSemaphore = UNLOCKED;
+- return UNLOCKED;
+- }
+- return pDataFlash->bSemaphore;
++ unsigned int dStatus = read_spi(SPI_SR);
++
++ /*
++ * If End of Receive Transfer interrupt occurred
++ */
++ if ((dStatus & AT91C_SPI_RXBUFF)) {
++ write_spi(SPI_PTCR, AT91C_PDC_TXTDIS); /* PDC Disable Tx */
++ write_spi(SPI_PTCR, AT91C_PDC_RXTDIS); /* PDC Disable Rx */
++
++ /*
++ * Release the semaphore
++ */
++ pDataFlash->bSemaphore = UNLOCKED;
++ return UNLOCKED;
++ }
++ return pDataFlash->bSemaphore;
+ }
+
+ /*------------------------------------------------------------------------------*/
+-/* \fn df_send_command */
++/* \fn df_send_command */
+ /* \brief Generic function to send a command to the dataflash */
+ /*------------------------------------------------------------------------------*/
+ char df_send_command(AT91PS_DF pDataFlash, unsigned char bCmd, /* Command value */
+- unsigned char bCmdSize, /* Command Size */
+- char *pData, /* Data to be sent */
+- unsigned int dDataSize, /* Data Size */
+- unsigned int dAddress)
+-{ /* Dataflash Address */
+- unsigned int dInternalAdr;
+-
+- div_t result = udiv(dAddress, AT91C_PAGE_SIZE(pDataFlash));
+-
+- /*
+- * Try to get the dataflash semaphore
+- */
+- if ((pDataFlash->bSemaphore) != UNLOCKED)
+- return (char)FAILURE;
+- pDataFlash->bSemaphore = LOCKED;
+-
+- /*
+- * Compute command pattern
+- */
+- if (pDataFlash->dfDescription.binaryPageMode == 0) {
+- dInternalAdr =
+- (result.quot << AT91C_PAGE_OFFSET(pDataFlash)) + result.rem;
+- } else {
+- dInternalAdr = dAddress;
+- }
+-
+- if (AT91C_DF_NB_PAGE(pDataFlash) >= 16384) {
+- pDataFlash->command[0] = (bCmd & 0x000000FF) |
+- ((dInternalAdr & 0x0F000000) >> 16) |
+- ((dInternalAdr & 0x00FF0000) >> 0) |
+- ((dInternalAdr & 0x0000FF00) << 16);
+- pDataFlash->command[1] = (dInternalAdr & 0x000000FF);
+-
+- if ((bCmd != DB_CONTINUOUS_ARRAY_READ) && (bCmd != DB_PAGE_READ))
+- bCmdSize++;
+- } else {
+- pDataFlash->command[0] = (bCmd & 0x000000FF) |
+- ((dInternalAdr & 0x00FF0000) >> 8) |
+- ((dInternalAdr & 0x0000FF00) << 8) |
+- ((dInternalAdr & 0x000000FF) << 24);
+- pDataFlash->command[1] = 0;
+- }
+-
+- /*
+- * Send Command and data through the SPI
+- */
+- write_spi(SPI_PTCR, AT91C_PDC_RXTDIS); /* PDC Disable Rx */
+- write_spi(SPI_RPR, (unsigned int)&(pDataFlash->command)); /* PDC Set Rx */
+- write_spi(SPI_RCR, bCmdSize);
+- write_spi(SPI_RNPR, (unsigned int)pData); /* PDC Set Next Rx */
+- write_spi(SPI_RNCR, dDataSize);
+-
+- write_spi(SPI_PTCR, AT91C_PDC_TXTDIS); /* PDC Disable Tx */
+- write_spi(SPI_TPR, (unsigned int)&(pDataFlash->command)); /* PDC Set Tx */
+- write_spi(SPI_TCR, bCmdSize);
+- write_spi(SPI_TNPR, (unsigned int)pData); /* PDC Set Next Tx */
+- write_spi(SPI_TNCR, dDataSize);
+-
+- write_spi(SPI_PTCR, AT91C_PDC_RXTEN); /* PDC Enable Rx */
+- write_spi(SPI_PTCR, AT91C_PDC_TXTEN); /* PDC Enable Tx */
+-
+- while (df_is_busy(pDataFlash) == LOCKED) ;
+-
+- return SUCCESS;
++ unsigned char bCmdSize, /* Command Size */
++ char *pData, /* Data to be sent */
++ unsigned int dDataSize, /* Data Size */
++ unsigned int dAddress)
++{ /* Dataflash Address */
++ unsigned int dInternalAdr;
++
++ div_t result = udiv(dAddress, AT91C_PAGE_SIZE(pDataFlash));
++
++ /*
++ * Try to get the dataflash semaphore
++ */
++ if ((pDataFlash->bSemaphore) != UNLOCKED)
++ return (char)FAILURE;
++ pDataFlash->bSemaphore = LOCKED;
++
++ /*
++ * Compute command pattern
++ */
++ if (pDataFlash->dfDescription.binaryPageMode == 0) {
++ dInternalAdr =
++ (result.quot << AT91C_PAGE_OFFSET(pDataFlash)) + result.rem;
++ } else {
++ dInternalAdr = dAddress;
++ }
++
++ if (AT91C_DF_NB_PAGE(pDataFlash) >= 16384) {
++ pDataFlash->command[0] = (bCmd & 0x000000FF) |
++ ((dInternalAdr & 0x0F000000) >> 16) |
++ ((dInternalAdr & 0x00FF0000) >> 0) |
++ ((dInternalAdr & 0x0000FF00) << 16);
++ pDataFlash->command[1] = (dInternalAdr & 0x000000FF);
++
++ if ((bCmd != DB_CONTINUOUS_ARRAY_READ) && (bCmd != DB_PAGE_READ))
++ bCmdSize++;
++ } else {
++ pDataFlash->command[0] = (bCmd & 0x000000FF) |
++ ((dInternalAdr & 0x00FF0000) >> 8) |
++ ((dInternalAdr & 0x0000FF00) << 8) |
++ ((dInternalAdr & 0x000000FF) << 24);
++ pDataFlash->command[1] = 0;
++ }
++
++ /*
++ * Send Command and data through the SPI
++ */
++ write_spi(SPI_PTCR, AT91C_PDC_RXTDIS); /* PDC Disable Rx */
++ write_spi(SPI_RPR, (unsigned int)&(pDataFlash->command)); /* PDC Set Rx */
++ write_spi(SPI_RCR, bCmdSize);
++ write_spi(SPI_RNPR, (unsigned int)pData); /* PDC Set Next Rx */
++ write_spi(SPI_RNCR, dDataSize);
++
++ write_spi(SPI_PTCR, AT91C_PDC_TXTDIS); /* PDC Disable Tx */
++ write_spi(SPI_TPR, (unsigned int)&(pDataFlash->command)); /* PDC Set Tx */
++ write_spi(SPI_TCR, bCmdSize);
++ write_spi(SPI_TNPR, (unsigned int)pData); /* PDC Set Next Tx */
++ write_spi(SPI_TNCR, dDataSize);
++
++ write_spi(SPI_PTCR, AT91C_PDC_RXTEN); /* PDC Enable Rx */
++ write_spi(SPI_PTCR, AT91C_PDC_TXTEN); /* PDC Enable Tx */
++
++ while (df_is_busy(pDataFlash) == LOCKED) ;
++
++ return SUCCESS;
+ }
+
+ /*------------------------------------------------------------------------------*/
+-/* \fn df_wait_ready */
++/* \fn df_wait_ready */
+ /* \brief wait for DataFlash to be ready */
+ /*------------------------------------------------------------------------------*/
+ static char df_wait_ready(AT91PS_DF pDataFlash)
+ {
+- unsigned int timeout = 0;
++ unsigned int timeout = 0;
+
+- while (timeout++ < AT91C_DF_TIMEOUT) {
+- if (df_get_status(pDataFlash)) {
+- if (df_is_ready(pDataFlash))
+- return SUCCESS;
+- }
+- }
++ while (timeout++ < AT91C_DF_TIMEOUT) {
++ if (df_get_status(pDataFlash)) {
++ if (df_is_ready(pDataFlash))
++ return SUCCESS;
++ }
++ }
+
+- return FAILURE;
++ return FAILURE;
+ }
+
+ void df_write(AT91PS_DF pDf, unsigned int addr, int size, unsigned long offset)
+ {
+- char rxBuffer[268];
+-
+- int i, j;
+-
+- i = offset;
+- if (offset == 0)
+- *((unsigned long *)(addr + 0x14)) = size;
+- while (size > 0) {
+- for (j = 0; j < ((size > 268) ? 268 : size); j++)
+- rxBuffer[j] = *((unsigned char *)(addr + i + j));
+- df_page_write(pDf, rxBuffer,
+- ((size <=
+- AT91C_PAGE_SIZE(pDf)) ? size : AT91C_PAGE_SIZE(pDf)),
+- i);
+- df_wait_ready(pDf);
+- i += AT91C_PAGE_SIZE(pDf);
+- size -= AT91C_PAGE_SIZE(pDf);
+- }
++ char rxBuffer[268];
++
++ int i, j;
++
++ i = offset;
++ if (offset == 0)
++ *((unsigned long *)(addr + 0x14)) = size;
++ while (size > 0) {
++ for (j = 0; j < ((size > 268) ? 268 : size); j++)
++ rxBuffer[j] = *((unsigned char *)(addr + i + j));
++ df_page_write(pDf, rxBuffer,
++ ((size <=
++ AT91C_PAGE_SIZE(pDf)) ? size : AT91C_PAGE_SIZE(pDf)),
++ i);
++ df_wait_ready(pDf);
++ i += AT91C_PAGE_SIZE(pDf);
++ size -= AT91C_PAGE_SIZE(pDf);
++ }
+
+ #define LONG_VAL(addr) *((unsigned long *)(addr))
+
+- for (j = 0; j < 0x1000; j += 32) {
+- df_continuous_read(pDf, (char *)rxBuffer, 32, j);
+- for (i = 0; i < 32; i += 4) {
++ for (j = 0; j < 0x1000; j += 32) {
++ df_continuous_read(pDf, (char *)rxBuffer, 32, j);
++ for (i = 0; i < 32; i += 4) {
+ #if 0
+- if (!(i & 4))
+- dbgu_print_hex(i + j);
++ if (!(i & 4))
++ dbgu_print_hex(i + j);
+ #endif
+ #if 0
+- if (LONG_VAL(0x200000 + i + j) == LONG_VAL(&rxBuffer[i]))
+- msg_print(MSG_SPACE);
+- else
+- msg_print(MSG_EXCLAMATION);
+- dbgu_print_hex(LONG_VAL(&rxBuffer[i]));
+- if (i & 4)
+- msg_print(MSG_NEWLINE);
++ if (LONG_VAL(0x200000 + i + j) == LONG_VAL(&rxBuffer[i]))
++ msg_print(MSG_SPACE);
++ else
++ msg_print(MSG_EXCLAMATION);
++ dbgu_print_hex(LONG_VAL(&rxBuffer[i]));
++ if (i & 4)
++ msg_print(MSG_NEWLINE);
+ #endif
+- }
+- }
++ }
++ }
+ }
+
+ /*------------------------------------------------------------------------------*/
+-/* \fn df_read */
++/* \fn df_read */
+ /* \brief Read a block in dataflash */
+ /*------------------------------------------------------------------------------*/
+ static int df_read(AT91PS_DF pDf,
+- unsigned int addr, unsigned char *buffer, unsigned int size)
++ unsigned int addr, unsigned char *buffer, unsigned int size)
+ {
+- unsigned int SizeToRead;
++ unsigned int SizeToRead;
+
+- int page_counter;
++ int page_counter;
+
+- page_counter = 32;
+- while (size) {
++ page_counter = 32;
++ while (size) {
+ dbg_log(1, "+");
+ /* SizeToRead = (size < AT91C_MAX_PDC_SIZE)? size : AT91C_MAX_PDC_SIZE; */
+- SizeToRead = (size < 0x8400) ? size : 0x8400;
+- /*
+- * wait the dataflash ready status
+- */
+- if (df_wait_ready(pDf) != 0) {
+-
+- df_continuous_read(pDf, (char *)buffer, SizeToRead, addr);
+- if (--page_counter <= 0) {
+- page_counter = 32;
+- }
+- size -= SizeToRead;
+- addr += SizeToRead;
+- buffer += SizeToRead;
+- } else {
+- /*
+- * We got a timeout
+- */
++ SizeToRead = (size < 0x8400) ? size : 0x8400;
++ /*
++ * wait the dataflash ready status
++ */
++ if (df_wait_ready(pDf) != 0) {
++
++ df_continuous_read(pDf, (char *)buffer, SizeToRead, addr);
++ if (--page_counter <= 0) {
++ page_counter = 32;
++ }
++ size -= SizeToRead;
++ addr += SizeToRead;
++ buffer += SizeToRead;
++ } else {
++ /*
++ * We got a timeout
++ */
+ #if 0
+ #if defined(CONFIG_VERBOSE)
+- msg_print(MSG_DATAFLASH);
+- msg_print(MSG_SPACE);
++ msg_print(MSG_DATAFLASH);
++ msg_print(MSG_SPACE);
+ #endif
+- msg_print(MSG_TIMEOUT);
+- msg_print(MSG_NEWLINE);
++ msg_print(MSG_TIMEOUT);
++ msg_print(MSG_NEWLINE);
+ #endif
+- return FAILURE;
+- }
+- }
++ return FAILURE;
++ }
++ }
+
+ dbg_log(1, "\r\n");
+- return SUCCESS;
++ return SUCCESS;
+ }
+
+ /*----------------------------------------------------------------------*/
+-/* \fn df_download */
++/* \fn df_download */
+ /* \brief load the content of the dataflash */
+ /*----------------------------------------------------------------------*/
+ static int df_download(AT91PS_DF pDf, unsigned int img_addr,
+- unsigned int img_size, unsigned int img_dest)
++ unsigned int img_size, unsigned int img_dest)
+ {
+- /*
+- * read bytes in the dataflash
+- */
+- if (df_read(pDf, img_addr, (unsigned char *)img_dest, img_size) == FAILURE) {
+- dbg_log(1, "df_read, failed!\r\n");
+- return FAILURE;
+- }
+-
+- /*
+- * wait the dataflash ready status
+- */
+- return df_wait_ready(pDf);
++ /*
++ * read bytes in the dataflash
++ */
++ if (df_read(pDf, img_addr, (unsigned char *)img_dest, img_size) == FAILURE) {
++ dbg_log(1, "df_read, failed!\r\n");
++ return FAILURE;
++ }
++
++ /*
++ * wait the dataflash ready status
++ */
++ return df_wait_ready(pDf);
+ }
+
+ /*----------------------------------------------------------------------*/
+-/* \fn df_probe */
++/* \fn df_probe */
+ /* \brief Returns DataFlash ID */
+ /*----------------------------------------------------------------------*/
+ static int df_probe(AT91PS_DF pDf)
+ {
+- char *pResult = (char *)(pDf->command);
++ char *pResult = (char *)(pDf->command);
+
+- df_get_status(pDf);
++ df_get_status(pDf);
+
+- // Check if DataFlash has been configured in binary page mode
+- if ((pResult[1] & 0x1) == 0x1) {
+- pDf->dfDescription.binaryPageMode = 1;
++ // Check if DataFlash has been configured in binary page mode
++ if ((pResult[1] & 0x1) == 0x1) {
++ pDf->dfDescription.binaryPageMode = 1;
+ #ifdef CONFIG_VERBOSE
+- dbgu_print("> DataFlash in binary mode\n\r");
+-#endif /* CONFIG_DEBUG */
+- } else {
+- pDf->dfDescription.binaryPageMode = 0;
+- }
++ dbgu_print("> DataFlash in binary mode\n\r");
++#endif /* CONFIG_DEBUG */
++ } else {
++ pDf->dfDescription.binaryPageMode = 0;
++ }
+
+- return (pResult[1] & 0x3C);
++ return (pResult[1] & 0x3C);
+ }
+
+ /*----------------------------------------------------------------------*/
+-/* \fn df_init */
++/* \fn df_init */
+ /* \brief This function tries to identify the DataFlash connected */
+ /*----------------------------------------------------------------------*/
+ static int df_init(AT91PS_DF pDf)
+ {
+- int dfcode = 0;
++ int dfcode = 0;
+
+- int status = SUCCESS;
++ int status = SUCCESS;
+
+- /*
+- * Default: AT45DB321B
+- */
+- pDf->dfDescription.pages_number = 8192;
+- pDf->dfDescription.pages_size = 528;
+- pDf->dfDescription.page_offset = 10;
++ /*
++ * Default: AT45DB321B
++ */
++ pDf->dfDescription.pages_number = 8192;
++ pDf->dfDescription.pages_size = 528;
++ pDf->dfDescription.page_offset = 10;
+
+- dfcode = df_probe(pDf);
++ dfcode = df_probe(pDf);
+
+- msg_df_detect(dfcode);
++ msg_df_detect(dfcode);
+
+- switch (dfcode) {
++ switch (dfcode) {
+ #if defined(CONFIG_SMALL_DATAFLASH)
+- case AT45DB011D:
+- pDf->dfDescription.pages_number = 512;
+- pDf->dfDescription.pages_size = 264;
+- pDf->dfDescription.page_offset = 9;
+- break;
+-
+- case AT45DB021D:
+- pDf->dfDescription.pages_number = 1024;
+- pDf->dfDescription.pages_size = 264;
+- pDf->dfDescription.page_offset = 9;
+- break;
+-
+- case AT45DB041D:
+- pDf->dfDescription.pages_number = 2048;
+- pDf->dfDescription.pages_size = 264;
+- pDf->dfDescription.page_offset = 9;
+- break;
+-
+- case AT45DB081D:
+- pDf->dfDescription.pages_number = 4096;
+- pDf->dfDescription.pages_size = 264;
+- pDf->dfDescription.page_offset = 9;
+- break;
+- case AT45DB161D:
+- pDf->dfDescription.pages_number = 4096;
+- pDf->dfDescription.pages_size = 528;
+- pDf->dfDescription.page_offset = 10;
+- break;
++ case AT45DB011D:
++ pDf->dfDescription.pages_number = 512;
++ pDf->dfDescription.pages_size = 264;
++ pDf->dfDescription.page_offset = 9;
++ break;
++
++ case AT45DB021D:
++ pDf->dfDescription.pages_number = 1024;
++ pDf->dfDescription.pages_size = 264;
++ pDf->dfDescription.page_offset = 9;
++ break;
++
++ case AT45DB041D:
++ pDf->dfDescription.pages_number = 2048;
++ pDf->dfDescription.pages_size = 264;
++ pDf->dfDescription.page_offset = 9;
++ break;
++
++ case AT45DB081D:
++ pDf->dfDescription.pages_number = 4096;
++ pDf->dfDescription.pages_size = 264;
++ pDf->dfDescription.page_offset = 9;
++ break;
++ case AT45DB161D:
++ pDf->dfDescription.pages_number = 4096;
++ pDf->dfDescription.pages_size = 528;
++ pDf->dfDescription.page_offset = 10;
++ break;
+ #endif
+- case AT45DB321D:
+- pDf->dfDescription.pages_number = 8192;
+- pDf->dfDescription.pages_size = 528;
+- pDf->dfDescription.page_offset = 10;
+- break;
+-
+- case AT45DB642D:
+- pDf->dfDescription.pages_number = 8192;
+- pDf->dfDescription.pages_size = 1056;
+- pDf->dfDescription.page_offset = 11;
+- break;
++ case AT45DB321D:
++ pDf->dfDescription.pages_number = 8192;
++ pDf->dfDescription.pages_size = 528;
++ pDf->dfDescription.page_offset = 10;
++ break;
++
++ case AT45DB642D:
++ pDf->dfDescription.pages_number = 8192;
++ if (pDf->dfDescription.binaryPageMode)
++ {
++ pDf->dfDescription.pages_size = 1024;
++ pDf->dfDescription.page_offset = 10;
++ }else{
++ pDf->dfDescription.pages_size = 1056;
++ pDf->dfDescription.page_offset = 11;
++ }
++ break;
+ /*
+ case AT45DB1282D:
+ pDf->dfDescription.pages_number = 16384;
+@@ -484,64 +490,64 @@ static int df_init(AT91PS_DF pDf)
+ pDf->dfDescription.page_offset = 12;
+ break;
+ */
+- default:
+- status = FAILURE;
+- break;
+- }
++ default:
++ status = FAILURE;
++ break;
++ }
+
+- return status;
++ return status;
+ }
+
+ int burn_df(unsigned int pcs, unsigned int addr, unsigned int size,
+- unsigned int offset)
++ unsigned int offset)
+ {
+- AT91S_DF sDF;
++ AT91S_DF sDF;
+
+- AT91PS_DF pDf = (AT91PS_DF) & sDF;
++ AT91PS_DF pDf = (AT91PS_DF) & sDF;
+
+- pDf->bSemaphore = UNLOCKED;
++ pDf->bSemaphore = UNLOCKED;
+
+- df_spi_init(pcs, DF_CS_SETTINGS);
++ df_spi_init(pcs, DF_CS_SETTINGS);
+
+- if (df_init(pDf) == FAILURE)
+- return FAILURE;
+- df_write(pDf, addr, size, offset);
++ if (df_init(pDf) == FAILURE)
++ return FAILURE;
++ df_write(pDf, addr, size, offset);
+
+- return SUCCESS;
++ return SUCCESS;
+ }
+
+ /*------------------------------------------------------------------------------*/
+-/* \fn load_df */
++/* \fn load_df */
+ /* \brief This function loads dataflash content to specified address */
+ /*------------------------------------------------------------------------------*/
+ int load_df(unsigned int pcs, unsigned int img_addr, unsigned int img_size,
+- unsigned int img_dest)
++ unsigned int img_dest)
+ {
+- AT91S_DF sDF;
++ AT91S_DF sDF;
+
+- AT91PS_DF pDf = (AT91PS_DF) & sDF;
++ AT91PS_DF pDf = (AT91PS_DF) & sDF;
+
+- unsigned int status;
++ unsigned int status;
+
+- pDf->bSemaphore = UNLOCKED;
++ pDf->bSemaphore = UNLOCKED;
+
+- df_spi_init(pcs, DF_CS_SETTINGS);
++ df_spi_init(pcs, DF_CS_SETTINGS);
+
+- if (df_init(pDf) == FAILURE)
+- return FAILURE;
++ if (df_init(pDf) == FAILURE)
++ return FAILURE;
+
+ #if defined(CONFIG_DATAFLASH_RECOVERY)
+- /*
+- * Test if a button has been pressed or not
+- */
+- /*
+- * Erase Page 0 to avoid infinite loop
+- */
+- df_recovery(pDf);
++ /*
++ * Test if a button has been pressed or not
++ */
++ /*
++ * Erase Page 0 to avoid infinite loop
++ */
++ df_recovery(pDf);
+ #endif
+
+- status = df_download(pDf, img_addr, img_size, img_dest);
+- return status;
++ status = df_download(pDf, img_addr, img_size, img_dest);
++ return status;
+ }
+
+-#endif /* CONFIG_DATAFLASH */
++#endif /* CONFIG_DATAFLASH */
+diff --git a/include/nand_ids.h b/include/nand_ids.h
+index 7bfcb08..6202faf 100644
+--- a/include/nand_ids.h
++++ b/include/nand_ids.h
+@@ -1,5 +1,5 @@
+ /* ----------------------------------------------------------------------------
+- * ATMEL Microcontroller Software Support - ROUSSET -
++ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+@@ -25,9 +25,9 @@
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+- * File Name : nand_ids.h
+- * Object :
+- * Creation : NLe Sep 28th 2006
++ * File Name : nand_ids.h
++ * Object :
++ * Creation : NLe Sep 28th 2006
+ *-----------------------------------------------------------------------------
+ */
+ #ifndef _NAND_IDS_H
+@@ -37,13 +37,14 @@
+
+ /* Supported NandFlash devices */
+ const static struct SNandInitInfo NandFlash_InitInfo[] = {
+- {0x2cca, 0x800, 0x20000, 0x800, 0x40, 0x1, "Micron MT29F2G16AAB 256MB\0"},
+- {0x2cda, 0x800, 0x20000, 0x800, 0x40, 0x0, "Micron MT29F2G08AAC 256MB\0"},
+- {0x2caa, 0x800, 0x20000, 0x800, 0x40, 0x0, "Micron MT29F2G08ABD 256MB\0"},
+- {0xecda, 0x800, 0x20000, 0x800, 0x40, 0x0, "Samsung K9F2G08U0M 256MB\0"},
+- {0xecaa, 0x800, 0x20000, 0x800, 0x40, 0x0, "Samsung K9F2G08U0A 256MB\0"},
+- {0x20aa, 0x800, 0x20000, 0x800, 0x40, 0x0, "ST Micro NAND02GR3B 256MB\0"},
+- {0,}
++ {0x2cca, 0x800, 0x20000, 0x800, 0x40, 0x1, "Micron MT29F2G16AAB 256MB\0"},
++ {0x2cda, 0x800, 0x20000, 0x800, 0x40, 0x0, "Micron MT29F2G08AAC 256MB\0"},
++ {0x2caa, 0x800, 0x20000, 0x800, 0x40, 0x0, "Micron MT29F2G08ABD 256MB\0"},
++ {0xecda, 0x800, 0x20000, 0x800, 0x40, 0x0, "Samsung K9F2G08U0M 256MB\0"},
++ {0xecaa, 0x800, 0x20000, 0x800, 0x40, 0x0, "Samsung K9F2G08U0A 256MB\0"},
++ {0x20aa, 0x800, 0x20000, 0x800, 0x40, 0x0, "ST Micro NAND02GR3B 256MB\0"},
++ {0x2076, 0x1000, 0x04000, 0x200, 0x10, 0x0, "Numonyx NAND512W3A2D 64MB\0"},
++ {0,}
+ };
+
+ #endif
+diff --git a/include/part.h b/include/part.h
+index cff8fa1..22b8b21 100644
+--- a/include/part.h
++++ b/include/part.h
+@@ -1,5 +1,5 @@
+ /* ----------------------------------------------------------------------------
+- * ATMEL Microcontroller Software Support - ROUSSET -
++ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+@@ -26,9 +26,9 @@
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+- * File Name : part.h
+- * Object :
+- * Creation : NLe Sep 28th 2006
++ * File Name : part.h
++ * Object :
++ * Creation : NLe Sep 28th 2006
+ *-----------------------------------------------------------------------------
+ */
+ #ifndef _PART_H
+@@ -60,8 +60,12 @@
+
+ #ifdef AT91SAM9G20
+ #include "AT91SAM9260_inc.h"
++#ifdef CONFIG_VULCANOG20
++#include "vulcano-g20.h"
++#else
+ #include "at91sam9g20ek.h"
+ #endif
++#endif
+
+ #ifdef AT91SAM9G45
+ #include "AT91SAM9G45_inc.h"
+@@ -107,4 +111,4 @@
+ #include "at91sam9rlek.h"
+ #endif
+
+-#endif /* _PART_H */
++#endif /* _PART_H */
+--
+1.7.0.4
+
diff --git a/recipes/at91bootstrap/at91bootstrap-3.0/vG20/0002-at91bootstrap-Add-VulcanoG20-board.patch b/recipes/at91bootstrap/at91bootstrap-3.0/vG20/0002-at91bootstrap-Add-VulcanoG20-board.patch
new file mode 100644
index 0000000000..8d37ba6981
--- /dev/null
+++ b/recipes/at91bootstrap/at91bootstrap-3.0/vG20/0002-at91bootstrap-Add-VulcanoG20-board.patch
@@ -0,0 +1,1310 @@
+From 93b9efb5790fe2d5a4c80032bf37e5e12e8c3124 Mon Sep 17 00:00:00 2001
+From: mlafauci <mlafauci@metodo2.it>
+Date: Sun, 6 Nov 2011 19:34:05 +0100
+Subject: [PATCH 2/2] at91bootstrap: Add VulcanoG20 board
+
+---
+ board/vulcano-g20/board.mk | 5 +
+ board/vulcano-g20/makefile | 6 +
+ board/vulcano-g20/sources | 119 +++++++++
+ board/vulcano-g20/vulcano-g20.c | 366 ++++++++++++++++++++++++++++
+ board/vulcano-g20/vulcano-g20.h | 116 +++++++++
+ board/vulcano-g20/vulcano-g20_defconfig | 129 ++++++++++
+ board/vulcano-g20/vulcano-g20df_defconfig | 129 ++++++++++
+ board/vulcano-g20/vulcano-g20dfc_defconfig | 128 ++++++++++
+ board/vulcano-g20/vulcano-g20nf_defconfig | 111 +++++++++
+ board/vulcano-g20/vulcano-g20sd_defconfig | 110 +++++++++
+ 10 files changed, 1219 insertions(+), 0 deletions(-)
+ create mode 100644 board/vulcano-g20/board.mk
+ create mode 100644 board/vulcano-g20/makefile
+ create mode 100644 board/vulcano-g20/sources
+ create mode 100644 board/vulcano-g20/vulcano-g20.c
+ create mode 100644 board/vulcano-g20/vulcano-g20.h
+ create mode 100644 board/vulcano-g20/vulcano-g20_defconfig
+ create mode 100644 board/vulcano-g20/vulcano-g20df_defconfig
+ create mode 100644 board/vulcano-g20/vulcano-g20dfc_defconfig
+ create mode 100644 board/vulcano-g20/vulcano-g20nf_defconfig
+ create mode 100644 board/vulcano-g20/vulcano-g20sd_defconfig
+
+diff --git a/board/vulcano-g20/board.mk b/board/vulcano-g20/board.mk
+new file mode 100644
+index 0000000..f151472
+--- /dev/null
++++ b/board/vulcano-g20/board.mk
+@@ -0,0 +1,5 @@
++CPPFLAGS += \
++ -DCONFIG_VULCANOG20
++
++ASFLAGS += \
++ -DCONFIG_VULCANOG20
+diff --git a/board/vulcano-g20/makefile b/board/vulcano-g20/makefile
+new file mode 100644
+index 0000000..39943ea
+--- /dev/null
++++ b/board/vulcano-g20/makefile
+@@ -0,0 +1,6 @@
++#
++# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source
++# file to this component. This file merely indirects to the real make file
++# that is shared by all the components of Pegasus
++#
++!INCLUDE $(_MAKEENVROOT)\makefile.def
+diff --git a/board/vulcano-g20/sources b/board/vulcano-g20/sources
+new file mode 100644
+index 0000000..3f6a89e
+--- /dev/null
++++ b/board/vulcano-g20/sources
+@@ -0,0 +1,119 @@
++TARGETNAME=at91sam9g20ek
++TARGETTYPE=LIBRARY
++RELEASETYPE=PLATFORM
++
++CDEFINES=$(CDEFINES) -DWINCE
++
++WINCE_OVERRIDE_CFLAGS=/GL /O1 /Ob1 /Os /QRthumb
++!IF $(_WINCEOSVER) >= 600
++CDEFINES=$(CDEFINES) /GS-
++CDEFINES=$(CDEFINES) /DWINCE600
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9260EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9260EK
++CDEFINES=$(CDEFINES) -DCONFIG_SDRAM
++!ENDIF
++!IF ("$(AT91SAM9260)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9260
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9261EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9261EK
++CDEFINES=$(CDEFINES) -DCONFIG_SDRAM
++!ENDIF
++!IF ("$(AT91SAM9261)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9261
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9263EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9263EK
++CDEFINES=$(CDEFINES) -DCONFIG_SDRAM
++!ENDIF
++!IF ("$(AT91SAM9263)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9263
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9RLEK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9RLEK
++CDEFINES=$(CDEFINES) -DCONFIG_SDRAM
++!ENDIF
++!IF ("$(AT91SAM9RL)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9RL
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9G10EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9G10EK
++CDEFINES=$(CDEFINES) -DCONFIG_SDRAM
++!ENDIF
++!IF ("$(AT91SAM9G10)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9G10
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9G20EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9G20EK
++CDEFINES=$(CDEFINES) -DCONFIG_SDRAM
++!ENDIF
++!IF ("$(AT91SAM9G20)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9G20
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9G45EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9G45EK
++CDEFINES=$(CDEFINES) -DCONFIG_DDR2
++!ENDIF
++!IF ("$(AT91SAM9G45)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9G45
++!ENDIF
++
++!IF ("$(CONFIG_AT91SAM9M10EK)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_AT91SAM9M10EK
++CDEFINES=$(CDEFINES) -DCONFIG_DDR2
++!ENDIF
++!IF ("$(AT91SAM9M10)" == "Y")
++CDEFINES=$(CDEFINES) -DAT91SAM9M10
++!ENDIF
++
++!IF ("$(CONFIG_DATAFLASH)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_DATAFLASH
++CDEFINES=$(CDEFINES) -DAT91C_SPI_PCS_DATAFLASH=0xD
++!ENDIF
++!IF ("$(CONFIG_NANDFLASH)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_NANDFLASH
++!ENDIF
++!IF ("$(CONFIG_SDCARD)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_SDCARD
++!ENDIF
++!IF ("$(CONFIG_SERIALFLASH)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_SERIALFLASH
++!ENDIF
++!IF ("$(CONFIG_EEPROM)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_EEPROM
++!ENDIF
++
++CDEFINES=$(CDEFINES) -DJUMP_ADDR=$(JUMP_ADDR)
++CDEFINES=$(CDEFINES) -DIMG_ADDRESS=$(IMG_ADDRESS)
++CDEFINES=$(CDEFINES) -DIMG_SIZE=$(IMG_SIZE)
++
++CDEFINES=$(CDEFINES) -DCONFIG_HW_INIT
++
++!IF ("$(CONFIG_DEBUG)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_DEBUG
++!ENDIF
++CDEFINES=$(CDEFINES) -DBOOTSTRAP_DEBUG_LEVEL
++
++!IF ("$(CONFIG_CPU_CLK_200MHZ)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_CPU_CLK_200MHZ
++!ENDIF
++!IF ("$(CONFIG_CPU_CLK_250MHZ)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_CPU_CLK_250MHZ
++!ENDIF
++!IF ("$(CONFIG_CPU_CLK_266MHZ)" == "Y")
++CDEFINES=$(CDEFINES) -DCONFIG_CPU_CLK_266MHZ
++!ENDIF
++
++INCLUDES=..\..\include; \
++ $(_WINCEROOT)\PUBLIC\COMMON\SDK\INC; \
++
++SOURCES= \
++ at91sam9g20ek.c \
+diff --git a/board/vulcano-g20/vulcano-g20.c b/board/vulcano-g20/vulcano-g20.c
+new file mode 100644
+index 0000000..ab4c282
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20.c
+@@ -0,0 +1,366 @@
++/* ----------------------------------------------------------------------------
++ * ATMEL Microcontroller Software Support - ROUSSET -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2008, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaimer below.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name : vulcano-g20.c
++ * Object :
++ * Creation : MLF Aug 2011
++ *-----------------------------------------------------------------------------
++ */
++#if defined(WINCE) && !defined(CONFIG_VULCANOG20)
++
++#else
++
++#include "part.h"
++#include "main.h"
++#include "gpio.h"
++#include "pmc.h"
++#include "rstc.h"
++#include "dbgu.h"
++#include "debug.h"
++#include "memory.h"
++
++int get_cp15(void);
++
++void set_cp15(unsigned int value);
++
++int get_cpsr(void);
++
++void set_cpsr(unsigned int value);
++
++#ifdef CONFIG_HW_INIT
++/*----------------------------------------------------------------------------*/
++/* \fn hw_init */
++/* \brief This function performs very low level HW initialization */
++/* This function is invoked as soon as possible during the c_startup */
++/* The bss segment must be initialized */
++/*----------------------------------------------------------------------------*/
++void hw_init(void)
++{
++ unsigned int cp15;
++
++ /*
++ * Configure PIOs
++ */
++ const struct pio_desc hw_pio[] = {
++#ifdef CONFIG_DEBUG
++ {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
++#endif
++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++
++ /*
++ * Disable watchdog
++ */
++ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
++
++ /*
++ * At this stage the main oscillator is supposed to be enabled
++ * * PCK = MCK = MOSC
++ */
++ writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
++
++ /*
++ * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
++ */
++ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
++
++ /*
++ * PCK = PLLA/2 = 3 * MCK
++ */
++ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
++ /*
++ * Switch MCK on PLLA output
++ */
++ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
++
++ /*
++ * Configure PLLB
++ */
++ pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
++
++ /*
++ * Enable External Reset
++ */
++ writel(AT91C_RSTC_KEY_UNLOCK
++ || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
++
++ /*
++ * Configure CP15
++ */
++ cp15 = get_cp15();
++#ifndef WINCE
++ cp15 |= I_CACHE;
++#endif
++ set_cp15(cp15);
++
++ /*
++ * Enable External Reset
++ */
++ writel(AT91C_RSTC_KEY_UNLOCK
++ || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
++ /*
++ * Configure the PIO controller
++ */
++ pio_setup(hw_pio);
++
++ /*
++ * Configure the EBI Slave Slot Cycle to 64
++ */
++ writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
++ (AT91C_BASE_MATRIX + MATRIX_SCFG3));
++
++#ifdef CONFIG_DEBUG
++ /*
++ * Enable Debug messages on the DBGU
++ */
++ dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
++ dbgu_print("Start AT91Bootstrap...\n\r");
++#endif /* CONFIG_DEBUG */
++
++#ifdef CONFIG_SDRAM
++ /*
++ * Initialize the matrix (memory voltage = 3.3)
++ */
++ writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC |
++ (1 << 16), AT91C_BASE_CCFG + CCFG_EBICSA);
++
++ /*
++ * Configure SDRAM Controller
++ */
++ sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
++ (MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
++ AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
++
++#endif /* CONFIG_SDRAM */
++}
++#endif /* CONFIG_HW_INIT */
++
++#ifdef CONFIG_SDRAM
++/*------------------------------------------------------------------------------*/
++/* \fn sdramc_hw_init */
++/* \brief This function performs SDRAMC HW initialization */
++/*------------------------------------------------------------------------------*/
++void sdramc_hw_init(void)
++{
++ /*
++ * Configure PIOs
++ */
++/* const struct pio_desc sdramc_pio[] = {
++ {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++*/
++ /*
++ * Configure the SDRAMC PIO controller to output PCK0
++ */
++/* pio_setup(sdramc_pio); */
++
++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
++
++}
++#endif /* CONFIG_SDRAM */
++
++#ifdef CONFIG_DATAFLASH
++#if defined(CONFIG_DATAFLASH_RECOVERY)
++/*------------------------------------------------------------------------------*/
++/* \fn df_recovery */
++/* \brief This function erases DataFlash Page 0 if BP4 is pressed */
++/* during boot sequence */
++/*------------------------------------------------------------------------------*/
++void df_recovery(AT91PS_DF pDf)
++{
++#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
++ /*
++ * Configure PIOs
++ */
++ const struct pio_desc bp4_pio[] = {
++ {"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++
++ /*
++ * Configure the PIO controller
++ */
++ writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
++ pio_setup(bp4_pio);
++
++ /*
++ * If BP4 is pressed during Boot sequence
++ */
++ /*
++ * Erase NandFlash block 0
++ */
++ if (!pio_get_value(AT91C_PIN_PA(31)))
++ df_page_erase(pDf, 0);
++#endif
++}
++#endif
++
++/*------------------------------------------------------------------------------*/
++/* \fn df_hw_init */
++/* \brief This function performs DataFlash HW initialization */
++/*------------------------------------------------------------------------------*/
++void df_hw_init(void)
++{
++ /*
++ * Configure PIOs
++ */
++ const struct pio_desc df_pio[] = {
++ {"MISO", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"MOSI", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
++ {"SPCK", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
++#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
++ {"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
++#endif
++#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
++ {"NPCS1", AT91C_PIN_PC(11), 0, PIO_DEFAULT, PIO_PERIPH_B},
++#endif
++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++
++ /*
++ * Configure the PIO controller
++ */
++ pio_setup(df_pio);
++}
++#endif /* CONFIG_DATAFLASH */
++
++#ifdef CONFIG_NANDFLASH
++/*------------------------------------------------------------------------------*/
++/* \fn nand_recovery */
++/* \brief This function erases NandFlash Block 0 if BP4 is pressed */
++/* during boot sequence */
++/*------------------------------------------------------------------------------*/
++static void nand_recovery(void)
++{
++ /*
++ * Configure PIOs
++ */
++ const struct pio_desc bp4_pio[] = {
++ {"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++
++ /*
++ * Configure the PIO controller
++ */
++ writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
++ pio_setup(bp4_pio);
++
++ /*
++ * If BP4 is pressed during Boot sequence
++ */
++ /*
++ * Erase NandFlash block 0
++ */
++ if (!pio_get_value(AT91C_PIN_PA(31)))
++ AT91F_NandEraseBlock0();
++}
++
++/*------------------------------------------------------------------------------*/
++/* \fn nandflash_hw_init */
++/* \brief NandFlash HW init */
++/*------------------------------------------------------------------------------*/
++void nandflash_hw_init(void)
++{
++ /*
++ * Configure PIOs
++ */
++ const struct pio_desc nand_pio[] = {
++ {"RDY_BSY", AT91C_PIN_PA(28), 0, PIO_PULLUP, PIO_INPUT},
++ {"NANDCS", AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++
++ /*
++ * Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface
++ */
++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM,
++ AT91C_BASE_CCFG + CCFG_EBICSA);
++
++ /*
++ * Configure SMC CS3
++ */
++ writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP |
++ AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
++ writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE |
++ AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
++ writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE),
++ AT91C_BASE_SMC + SMC_CYCLE3);
++ writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE |
++ AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
++ AT91C_SM_TDF), AT91C_BASE_SMC + SMC_CTRL3);
++
++ /*
++ * Configure the PIO controller
++ */
++ writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
++ pio_setup(nand_pio);
++
++ nand_recovery();
++}
++
++/*------------------------------------------------------------------------------*/
++/* \fn nandflash_cfg_16bits_dbw_init */
++/* \brief Configure SMC in 16 bits mode */
++/*------------------------------------------------------------------------------*/
++void nandflash_cfg_16bits_dbw_init(void)
++{
++ writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS,
++ AT91C_BASE_SMC + SMC_CTRL3);
++}
++
++/*------------------------------------------------------------------------------*/
++/* \fn nandflash_cfg_8bits_dbw_init */
++/* \brief Configure SMC in 8 bits mode */
++/*------------------------------------------------------------------------------*/
++void nandflash_cfg_8bits_dbw_init(void)
++{
++ writel((readl(AT91C_BASE_SMC + SMC_CTRL3) & ~(AT91C_SMC_DBW)) |
++ AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC + SMC_CTRL3);
++}
++
++#endif /* #ifdef CONFIG_NANDFLASH */
++
++#endif /* CONFIG_AT91SAM9G20EK */
+diff --git a/board/vulcano-g20/vulcano-g20.h b/board/vulcano-g20/vulcano-g20.h
+new file mode 100644
+index 0000000..25771dd
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20.h
+@@ -0,0 +1,116 @@
++/* ----------------------------------------------------------------------------
++ * ATMEL Microcontroller Software Support - ROUSSET -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2008, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaimer below.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name : vulcano-g20.h
++ * Object :
++ * Creation : MLF Aug 2011
++ *-----------------------------------------------------------------------------
++ */
++#ifndef _VULCANOG20_H
++#define _VULCANOG20_H
++
++/* ******************************************************************* */
++/* PMC Settings */
++/* */
++/* The main oscillator is enabled as soon as possible in the c_startup */
++/* and MCK is switched on the main oscillator. */
++/* PLL initialization is done later in the hw_init() function */
++/* ******************************************************************* */
++#define MASTER_CLOCK (132096000)
++#define TOP_OF_MEMORY 0x304000
++#define PLL_LOCK_TIMEOUT 1000000
++
++#define PLLA_SETTINGS 0x202A3F01
++#define PLLB_SETTINGS 0x10193F05
++
++/* Switch MCK on PLLA output PCK = PLLA/2 = 3 * MCK */
++#define MCKR_SETTINGS 0x1300
++#define MCKR_CSS_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS)
++
++/* ******************************************************************* */
++/* DataFlash Settings */
++/* */
++/* ******************************************************************* */
++#define AT91C_BASE_SPI AT91C_BASE_SPI0
++#define AT91C_ID_SPI AT91C_ID_SPI0
++
++/* AC characteristics */
++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS (0x22 << 16)
++#define DATAFLASH_TCHS (0x1 << 24)
++
++#define DF_CS_SETTINGS (AT91C_SPI_NCPHA | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
++
++/* ******************************************************************* */
++/* NandFlash Settings */
++/* */
++/* ******************************************************************* */
++#define AT91C_SMARTMEDIA_BASE 0x40000000
++
++#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */
++#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */
++
++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
++
++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOA_PDSR & AT91C_PIO_PA28))
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 133000000.*/
++/* Please refer to SMC section in AT91SAM9 datasheet to learn how */
++/* to generate these values. */
++/* ******************************************************************** */
++#define AT91C_SM_NWE_SETUP (2 << 0)
++#define AT91C_SM_NCS_WR_SETUP (0 << 8)
++#define AT91C_SM_NRD_SETUP (2 << 16)
++#define AT91C_SM_NCS_RD_SETUP (0 << 24)
++
++#define AT91C_SM_NWE_PULSE (4 << 0)
++#define AT91C_SM_NCS_WR_PULSE (4 << 8)
++#define AT91C_SM_NRD_PULSE (4 << 16)
++#define AT91C_SM_NCS_RD_PULSE (4 << 24)
++
++#define AT91C_SM_NWE_CYCLE (7 << 0)
++#define AT91C_SM_NRD_CYCLE (7 << 16)
++
++#define AT91C_SM_TDF (3 << 16)
++
++#define OP_BOOTSTRAP_MCI_on
++#define BOARD_SD_PIN_CD \
++ {1 << 9, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}
++
++#define BOARD_SD_PINS \
++ {0x0000003B, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_PULLUP}, \
++ {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
++
++/// List of second MCI slot pins definitions.
++#define BOARD_SD_MCI1_PINS \
++ {0xec0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \
++ {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
++
++#define at91sam9g20
++#endif /* _VULCANOG20_H */
+diff --git a/board/vulcano-g20/vulcano-g20_defconfig b/board/vulcano-g20/vulcano-g20_defconfig
+new file mode 100644
+index 0000000..c2c2d7f
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20_defconfig
+@@ -0,0 +1,129 @@
++#
++# Automatically generated make config: don't edit
++# Mon Jan 24 19:40:39 2011
++#
++HAVE_DOT_CONFIG=y
++CONFIG_BOARDNAME="vulcano-g20"
++# CONFIG_AT91SAM9260EK is not set
++# CONFIG_AT91SAM9261EK is not set
++# CONFIG_AT91SAM9263EK is not set
++# CONFIG_AT91SAM9RLEK is not set
++# CONFIG_AT91SAM9XEEK is not set
++# CONFIG_AT91SAM9G10EK is not set
++# CONFIG_AT91SAM9G20EK is not set
++CONFIG_VULCANOG20=y
++# CONFIG_AT91SAM9G45EK is not set
++# CONFIG_AT91SAM9G45EKES is not set
++# CONFIG_AT91SAM9M10EK is not set
++# CONFIG_AT91SAM9M10EKES is not set
++# CONFIG_AT91CAP9ADK is not set
++# CONFIG_AT91CAP9STK is not set
++# CONFIG_AFEB9260 is not set
++CONFIG_CHIP="AT91SAM9G20"
++CONFIG_BOARD="vulcano-g20"
++CONFIG_MACH_TYPE="0x658"
++CONFIG_LINK_ADDR="0x000000"
++CONFIG_TOP_OF_MEMORY="0x304000"
++# CONFIG_CRYSTAL_12_000MHZ is not set
++# CONFIG_CRYSTAL_16_000MHZ is not set
++# CONFIG_CRYSTAL_16_36766MHZ is not set
++CONFIG_CRYSTAL_18_432MHZ=y
++ALLOW_CRYSTAL_18_432MHZ=y
++CONFIG_CRYSTAL="CRYSTAL_18_432MHZ"
++# CONFIG_CPU_CLK_166MHZ is not set
++# CONFIG_CPU_CLK_180MHZ is not set
++# CONFIG_CPU_CLK_200MHZ is not set
++# CONFIG_CPU_CLK_240MHZ is not set
++# CONFIG_CPU_CLK_266MHZ is not set
++CONFIG_CPU_CLK_400MHZ=y
++ALLOW_CPU_CLK_400MHZ=y
++# DISABLE_CPU_CLK_240MHZ is not set
++# CONFIG_BUS_SPEED_83MHZ is not set
++# CONFIG_BUS_SPEED_90MHZ is not set
++# CONFIG_BUS_SPEED_100MHZ is not set
++CONFIG_BUS_SPEED_133MHZ=y
++
++#
++# Memory selection
++#
++CONFIG_SDRAM=y
++# CONFIG_SDDRC is not set
++# CONFIG_DDR2 is not set
++ALLOW_DATAFLASH=y
++# ALLOW_FLASH is not set
++ALLOW_NANDFLASH=y
++ALLOW_SDCARD=y
++# ALLOW_HSMCI is not set
++# ALLOW_PSRAM is not set
++# ALLOW_SDRAM_16BIT is not set
++# CONFIG_RAM_32MB is not set
++CONFIG_RAM_64MB=y
++# CONFIG_RAM_128MB is not set
++# CONFIG_RAM_256MB is not set
++CONFIG_DATAFLASH=y
++# CONFIG_FLASH is not set
++# CONFIG_NANDFLASH is not set
++# CONFIG_SDCARD is not set
++CONFIG_MEMORY="dataflash"
++# CONFIG_SDCARD_HS is not set
++
++#
++# SPI configuration
++#
++CONFIG_SPI_CLK=33000000
++CONFIG_SMALL_DATAFLASH=y
++CONFIG_DATAFLASH_RECOVERY=y
++ALLOW_DATAFLASH_RECOVERY=y
++# CONFIG_SPI_BOOT_CS0 is not set
++CONFIG_SPI_BOOT_CS1=y
++# CONFIG_SPI_BOOT_CS2 is not set
++# CONFIG_SPI_BOOT_CS3 is not set
++ALLOW_BOOT_FROM_DATAFLASH_CS0=y
++ALLOW_BOOT_FROM_DATAFLASH_CS1=y
++# ALLOW_BOOT_FROM_DATAFLASH_CS2 is not set
++# ALLOW_BOOT_FROM_DATAFLASH_CS3 is not set
++# DATAFLASHCARD_ON_CS0 is not set
++DATAFLASHCARD_ON_CS1=y
++# DATAFLASHCARD_ON_CS2 is not set
++# DATAFLASHCARD_ON_CS3 is not set
++# CONFIG_DATAFLASHCARD is not set
++CONFIG_CARD_SUFFIX=""
++CONFIG_SPI_BOOT="AT91C_SPI_PCS1_DATAFLASH"
++CONFIG_SPI_MODE_0=y
++# CONFIG_SPI_MODE_1 is not set
++# CONFIG_SPI_MODE_2 is not set
++# CONFIG_SPI_MODE_3 is not set
++CONFIG_SPI_MODE=0
++CONFIG_BOOTSTRAP_MAXSIZE="23000"
++CONFIG_PROJECT="dataflash"
++CONFIG_LOAD_UBOOT=y
++# CONFIG_LOAD_EBOOT is not set
++# CONFIG_LOAD_LINUX is not set
++# CONFIG_LOAD_NK is not set
++# CONFIG_LOAD_64KB is not set
++# CONFIG_LOAD_1MB is not set
++# CONFIG_LOAD_4MB is not set
++CONFIG_ALT_IMG_ADDRESS="0x00063000"
++CONFIG_ALT_IMG_SIZE="0x00010000"
++CONFIG_OS_IMG_SIZE="0x40000"
++
++#
++# U-Boot Image Storage Setup
++#
++CONFIG_IMG_ADDRESS="0x00008400"
++CONFIG_SETTING_ADDRESS="0x00408400"
++CONFIG_SETTING_SIZE="0x00001000"
++CONFIG_IMG_SIZE="0x00040000"
++CONFIG_JUMP_ADDR="0x23F00000"
++CONFIG_ALT_JUMP_ADDR="0x20000000"
++CONFIG_GLBDRV_ADDR="0x20058000"
++# CONFIG_LONG_TEST is not set
++CONFIG_DEBUG=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_LOUD is not set
++# CONFIG_DEBUG_VERY_LOUD is not set
++CONFIG_HW_INIT=y
++# CONFIG_USER_HW_INIT is not set
++CONFIG_THUMB=y
++# CONFIG_SX_AT91 is not set
++# CONFIG_RAW_AT91 is not set
+diff --git a/board/vulcano-g20/vulcano-g20df_defconfig b/board/vulcano-g20/vulcano-g20df_defconfig
+new file mode 100644
+index 0000000..0ffba13
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20df_defconfig
+@@ -0,0 +1,129 @@
++#
++# Automatically generated make config: don't edit
++# Mon Jan 24 19:40:38 2011
++#
++HAVE_DOT_CONFIG=y
++CONFIG_BOARDNAME="vulcano-g20df"
++# CONFIG_AT91SAM9260EK is not set
++# CONFIG_AT91SAM9261EK is not set
++# CONFIG_AT91SAM9263EK is not set
++# CONFIG_AT91SAM9RLEK is not set
++# CONFIG_AT91SAM9XEEK is not set
++# CONFIG_AT91SAM9G10EK is not set
++# CONFIG_AT91SAM9G20EK is not set
++CONFIG_VULCANOG20=y
++# CONFIG_AT91SAM9G45EK is not set
++# CONFIG_AT91SAM9G45EKES is not set
++# CONFIG_AT91SAM9M10EK is not set
++# CONFIG_AT91SAM9M10EKES is not set
++# CONFIG_AT91CAP9ADK is not set
++# CONFIG_AT91CAP9STK is not set
++# CONFIG_AFEB9260 is not set
++CONFIG_CHIP="AT91SAM9G20"
++CONFIG_BOARD="vulcano-g20"
++CONFIG_MACH_TYPE="0x658"
++CONFIG_LINK_ADDR="0x000000"
++CONFIG_TOP_OF_MEMORY="0x304000"
++# CONFIG_CRYSTAL_12_000MHZ is not set
++# CONFIG_CRYSTAL_16_000MHZ is not set
++# CONFIG_CRYSTAL_16_36766MHZ is not set
++CONFIG_CRYSTAL_18_432MHZ=y
++ALLOW_CRYSTAL_18_432MHZ=y
++CONFIG_CRYSTAL="CRYSTAL_18_432MHZ"
++# CONFIG_CPU_CLK_166MHZ is not set
++# CONFIG_CPU_CLK_180MHZ is not set
++# CONFIG_CPU_CLK_200MHZ is not set
++# CONFIG_CPU_CLK_240MHZ is not set
++# CONFIG_CPU_CLK_266MHZ is not set
++CONFIG_CPU_CLK_400MHZ=y
++ALLOW_CPU_CLK_400MHZ=y
++# DISABLE_CPU_CLK_240MHZ is not set
++# CONFIG_BUS_SPEED_83MHZ is not set
++# CONFIG_BUS_SPEED_90MHZ is not set
++# CONFIG_BUS_SPEED_100MHZ is not set
++CONFIG_BUS_SPEED_133MHZ=y
++
++#
++# Memory selection
++#
++CONFIG_SDRAM=y
++# CONFIG_SDDRC is not set
++# CONFIG_DDR2 is not set
++ALLOW_DATAFLASH=y
++# ALLOW_FLASH is not set
++ALLOW_NANDFLASH=y
++ALLOW_SDCARD=y
++# ALLOW_HSMCI is not set
++# ALLOW_PSRAM is not set
++# ALLOW_SDRAM_16BIT is not set
++# CONFIG_RAM_32MB is not set
++CONFIG_RAM_64MB=y
++# CONFIG_RAM_128MB is not set
++# CONFIG_RAM_256MB is not set
++CONFIG_DATAFLASH=y
++# CONFIG_FLASH is not set
++# CONFIG_NANDFLASH is not set
++# CONFIG_SDCARD is not set
++CONFIG_MEMORY="dataflash"
++# CONFIG_SDCARD_HS is not set
++
++#
++# SPI configuration
++#
++CONFIG_SPI_CLK=33000000
++CONFIG_SMALL_DATAFLASH=y
++CONFIG_DATAFLASH_RECOVERY=y
++ALLOW_DATAFLASH_RECOVERY=y
++# CONFIG_SPI_BOOT_CS0 is not set
++CONFIG_SPI_BOOT_CS1=y
++# CONFIG_SPI_BOOT_CS2 is not set
++# CONFIG_SPI_BOOT_CS3 is not set
++ALLOW_BOOT_FROM_DATAFLASH_CS0=y
++ALLOW_BOOT_FROM_DATAFLASH_CS1=y
++# ALLOW_BOOT_FROM_DATAFLASH_CS2 is not set
++# ALLOW_BOOT_FROM_DATAFLASH_CS3 is not set
++# DATAFLASHCARD_ON_CS0 is not set
++DATAFLASHCARD_ON_CS1=y
++# DATAFLASHCARD_ON_CS2 is not set
++# DATAFLASHCARD_ON_CS3 is not set
++# CONFIG_DATAFLASHCARD is not set
++CONFIG_CARD_SUFFIX=""
++CONFIG_SPI_BOOT="AT91C_SPI_PCS1_DATAFLASH"
++CONFIG_SPI_MODE_0=y
++# CONFIG_SPI_MODE_1 is not set
++# CONFIG_SPI_MODE_2 is not set
++# CONFIG_SPI_MODE_3 is not set
++CONFIG_SPI_MODE=0
++CONFIG_BOOTSTRAP_MAXSIZE="23000"
++CONFIG_PROJECT="dataflash"
++CONFIG_LOAD_UBOOT=y
++# CONFIG_LOAD_EBOOT is not set
++# CONFIG_LOAD_LINUX is not set
++# CONFIG_LOAD_NK is not set
++# CONFIG_LOAD_64KB is not set
++# CONFIG_LOAD_1MB is not set
++# CONFIG_LOAD_4MB is not set
++CONFIG_ALT_IMG_ADDRESS="0x00063000"
++CONFIG_ALT_IMG_SIZE="0x00010000"
++CONFIG_OS_IMG_SIZE="0x40000"
++
++#
++# U-Boot Image Storage Setup
++#
++CONFIG_IMG_ADDRESS="0x00008400"
++CONFIG_SETTING_ADDRESS="0x00408400"
++CONFIG_SETTING_SIZE="0x00001000"
++CONFIG_IMG_SIZE="0x00040000"
++CONFIG_JUMP_ADDR="0x23F00000"
++CONFIG_ALT_JUMP_ADDR="0x20000000"
++CONFIG_GLBDRV_ADDR="0x20058000"
++# CONFIG_LONG_TEST is not set
++CONFIG_DEBUG=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_LOUD is not set
++# CONFIG_DEBUG_VERY_LOUD is not set
++CONFIG_HW_INIT=y
++# CONFIG_USER_HW_INIT is not set
++CONFIG_THUMB=y
++# CONFIG_SX_AT91 is not set
++# CONFIG_RAW_AT91 is not set
+diff --git a/board/vulcano-g20/vulcano-g20dfc_defconfig b/board/vulcano-g20/vulcano-g20dfc_defconfig
+new file mode 100644
+index 0000000..46a2445
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20dfc_defconfig
+@@ -0,0 +1,128 @@
++#
++# Automatically generated make config: don't edit
++# Mon Jan 24 19:40:36 2011
++#
++HAVE_DOT_CONFIG=y
++CONFIG_BOARDNAME="vulcano-g20dfc"
++# CONFIG_AT91SAM9260EK is not set
++# CONFIG_AT91SAM9261EK is not set
++# CONFIG_AT91SAM9263EK is not set
++# CONFIG_AT91SAM9RLEK is not set
++# CONFIG_AT91SAM9XEEK is not set
++# CONFIG_AT91SAM9G10EK is not set
++CONFIG_AT91SAM9G20EK=y
++# CONFIG_AT91SAM9G45EK is not set
++# CONFIG_AT91SAM9G45EKES is not set
++# CONFIG_AT91SAM9M10EK is not set
++# CONFIG_AT91SAM9M10EKES is not set
++# CONFIG_AT91CAP9ADK is not set
++# CONFIG_AT91CAP9STK is not set
++# CONFIG_AFEB9260 is not set
++CONFIG_CHIP="AT91SAM9G20"
++CONFIG_BOARD="vulcano-g20"
++CONFIG_MACH_TYPE="0x658"
++CONFIG_LINK_ADDR="0x000000"
++CONFIG_TOP_OF_MEMORY="0x304000"
++# CONFIG_CRYSTAL_12_000MHZ is not set
++# CONFIG_CRYSTAL_16_000MHZ is not set
++# CONFIG_CRYSTAL_16_36766MHZ is not set
++CONFIG_CRYSTAL_18_432MHZ=y
++ALLOW_CRYSTAL_18_432MHZ=y
++CONFIG_CRYSTAL="CRYSTAL_18_432MHZ"
++# CONFIG_CPU_CLK_166MHZ is not set
++# CONFIG_CPU_CLK_180MHZ is not set
++# CONFIG_CPU_CLK_200MHZ is not set
++# CONFIG_CPU_CLK_240MHZ is not set
++# CONFIG_CPU_CLK_266MHZ is not set
++CONFIG_CPU_CLK_400MHZ=y
++ALLOW_CPU_CLK_400MHZ=y
++# DISABLE_CPU_CLK_240MHZ is not set
++# CONFIG_BUS_SPEED_83MHZ is not set
++# CONFIG_BUS_SPEED_90MHZ is not set
++# CONFIG_BUS_SPEED_100MHZ is not set
++CONFIG_BUS_SPEED_133MHZ=y
++
++#
++# Memory selection
++#
++CONFIG_SDRAM=y
++# CONFIG_SDDRC is not set
++# CONFIG_DDR2 is not set
++ALLOW_DATAFLASH=y
++# ALLOW_FLASH is not set
++ALLOW_NANDFLASH=y
++ALLOW_SDCARD=y
++# ALLOW_HSMCI is not set
++# ALLOW_PSRAM is not set
++# ALLOW_SDRAM_16BIT is not set
++# CONFIG_RAM_32MB is not set
++CONFIG_RAM_64MB=y
++# CONFIG_RAM_128MB is not set
++# CONFIG_RAM_256MB is not set
++CONFIG_DATAFLASH=y
++# CONFIG_FLASH is not set
++# CONFIG_NANDFLASH is not set
++# CONFIG_SDCARD is not set
++CONFIG_MEMORY="dataflash"
++# CONFIG_SDCARD_HS is not set
++
++#
++# SPI configuration
++#
++CONFIG_SPI_CLK=33000000
++CONFIG_SMALL_DATAFLASH=y
++CONFIG_DATAFLASH_RECOVERY=y
++ALLOW_DATAFLASH_RECOVERY=y
++CONFIG_SPI_BOOT_CS0=y
++# CONFIG_SPI_BOOT_CS1 is not set
++# CONFIG_SPI_BOOT_CS2 is not set
++# CONFIG_SPI_BOOT_CS3 is not set
++ALLOW_BOOT_FROM_DATAFLASH_CS0=y
++ALLOW_BOOT_FROM_DATAFLASH_CS1=y
++# ALLOW_BOOT_FROM_DATAFLASH_CS2 is not set
++# ALLOW_BOOT_FROM_DATAFLASH_CS3 is not set
++# DATAFLASHCARD_ON_CS0 is not set
++DATAFLASHCARD_ON_CS1=y
++# DATAFLASHCARD_ON_CS2 is not set
++# DATAFLASHCARD_ON_CS3 is not set
++CONFIG_DATAFLASHCARD=y
++CONFIG_CARD_SUFFIX="card"
++CONFIG_SPI_BOOT="AT91C_SPI_PCS0_DATAFLASH"
++CONFIG_SPI_MODE_0=y
++# CONFIG_SPI_MODE_1 is not set
++# CONFIG_SPI_MODE_2 is not set
++# CONFIG_SPI_MODE_3 is not set
++CONFIG_SPI_MODE=0
++CONFIG_BOOTSTRAP_MAXSIZE="23000"
++CONFIG_PROJECT="dataflash"
++CONFIG_LOAD_UBOOT=y
++# CONFIG_LOAD_EBOOT is not set
++# CONFIG_LOAD_LINUX is not set
++# CONFIG_LOAD_NK is not set
++# CONFIG_LOAD_64KB is not set
++# CONFIG_LOAD_1MB is not set
++# CONFIG_LOAD_4MB is not set
++CONFIG_ALT_IMG_ADDRESS="0x00063000"
++CONFIG_ALT_IMG_SIZE="0x00010000"
++CONFIG_OS_IMG_SIZE="0x40000"
++
++#
++# U-Boot Image Storage Setup
++#
++CONFIG_IMG_ADDRESS="0x00008400"
++CONFIG_SETTING_ADDRESS="0x00408400"
++CONFIG_SETTING_SIZE="0x00001000"
++CONFIG_IMG_SIZE="0x00040000"
++CONFIG_JUMP_ADDR="0x23F00000"
++CONFIG_ALT_JUMP_ADDR="0x20000000"
++CONFIG_GLBDRV_ADDR="0x20058000"
++# CONFIG_LONG_TEST is not set
++CONFIG_DEBUG=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_LOUD is not set
++# CONFIG_DEBUG_VERY_LOUD is not set
++CONFIG_HW_INIT=y
++# CONFIG_USER_HW_INIT is not set
++# CONFIG_THUMB is not set
++CONFIG_SX_AT91=y
++CONFIG_RAW_AT91=y
+diff --git a/board/vulcano-g20/vulcano-g20nf_defconfig b/board/vulcano-g20/vulcano-g20nf_defconfig
+new file mode 100644
+index 0000000..97dfa15
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20nf_defconfig
+@@ -0,0 +1,111 @@
++#
++# Automatically generated make config: don't edit
++# Mon Jan 24 19:40:35 2011
++#
++HAVE_DOT_CONFIG=y
++CONFIG_BOARDNAME="vulcano-g20nf"
++# CONFIG_AT91SAM9260EK is not set
++# CONFIG_AT91SAM9261EK is not set
++# CONFIG_AT91SAM9263EK is not set
++# CONFIG_AT91SAM9RLEK is not set
++# CONFIG_AT91SAM9XEEK is not set
++# CONFIG_AT91SAM9G10EK is not set
++# CONFIG_AT91SAM9G20EK is not set
++CONFIG_VULCANOG20=y
++# CONFIG_AT91SAM9G45EK is not set
++# CONFIG_AT91SAM9G45EKES is not set
++# CONFIG_AT91SAM9M10EK is not set
++# CONFIG_AT91SAM9M10EKES is not set
++# CONFIG_AT91CAP9ADK is not set
++# CONFIG_AT91CAP9STK is not set
++# CONFIG_AFEB9260 is not set
++CONFIG_CHIP="AT91SAM9G20"
++CONFIG_BOARD="vulcano-g20"
++CONFIG_MACH_TYPE="0x658"
++CONFIG_LINK_ADDR="0x000000"
++CONFIG_TOP_OF_MEMORY="0x304000"
++# CONFIG_CRYSTAL_12_000MHZ is not set
++# CONFIG_CRYSTAL_16_000MHZ is not set
++# CONFIG_CRYSTAL_16_36766MHZ is not set
++CONFIG_CRYSTAL_18_432MHZ=y
++ALLOW_CRYSTAL_18_432MHZ=y
++CONFIG_CRYSTAL="CRYSTAL_18_432MHZ"
++# CONFIG_CPU_CLK_166MHZ is not set
++# CONFIG_CPU_CLK_180MHZ is not set
++# CONFIG_CPU_CLK_200MHZ is not set
++# CONFIG_CPU_CLK_240MHZ is not set
++# CONFIG_CPU_CLK_266MHZ is not set
++CONFIG_CPU_CLK_400MHZ=y
++ALLOW_CPU_CLK_400MHZ=y
++# DISABLE_CPU_CLK_240MHZ is not set
++# CONFIG_BUS_SPEED_83MHZ is not set
++# CONFIG_BUS_SPEED_90MHZ is not set
++# CONFIG_BUS_SPEED_100MHZ is not set
++CONFIG_BUS_SPEED_133MHZ=y
++
++#
++# Memory selection
++#
++CONFIG_SDRAM=y
++# CONFIG_SDDRC is not set
++# CONFIG_DDR2 is not set
++ALLOW_DATAFLASH=y
++# ALLOW_FLASH is not set
++ALLOW_NANDFLASH=y
++ALLOW_SDCARD=y
++# ALLOW_HSMCI is not set
++# ALLOW_PSRAM is not set
++# ALLOW_SDRAM_16BIT is not set
++# CONFIG_RAM_32MB is not set
++CONFIG_RAM_64MB=y
++# CONFIG_RAM_128MB is not set
++# CONFIG_RAM_256MB is not set
++# CONFIG_DATAFLASH is not set
++# CONFIG_FLASH is not set
++CONFIG_NANDFLASH=y
++# CONFIG_SDCARD is not set
++CONFIG_ENABLE_SW_ECC=y
++CONFIG_MEMORY="nandflash"
++# CONFIG_SDCARD_HS is not set
++ALLOW_DATAFLASH_RECOVERY=y
++ALLOW_BOOT_FROM_DATAFLASH_CS0=y
++ALLOW_BOOT_FROM_DATAFLASH_CS1=y
++DATAFLASHCARD_ON_CS1=y
++
++#
++# NAND Flash configuration
++#
++CONFIG_NANDFLASH_SMALL_BLOCKS=y
++CONFIG_BOOTSTRAP_MAXSIZE="23000"
++CONFIG_PROJECT="nandflash"
++CONFIG_LOAD_UBOOT=y
++# CONFIG_LOAD_EBOOT is not set
++# CONFIG_LOAD_LINUX is not set
++# CONFIG_LOAD_NK is not set
++# CONFIG_LOAD_64KB is not set
++# CONFIG_LOAD_1MB is not set
++# CONFIG_LOAD_4MB is not set
++CONFIG_ALT_IMG_ADDRESS="0x00040000"
++CONFIG_ALT_IMG_SIZE="0x00010000"
++CONFIG_OS_IMG_SIZE="0x40000"
++
++#
++# U-Boot Image Storage Setup
++#
++CONFIG_IMG_ADDRESS="0x00020000"
++CONFIG_SETTING_ADDRESS="0x01FE0000"
++CONFIG_SETTING_SIZE="0x00001000"
++CONFIG_IMG_SIZE="0x00040000"
++CONFIG_JUMP_ADDR="0x23F00000"
++CONFIG_ALT_JUMP_ADDR="0x20000000"
++CONFIG_GLBDRV_ADDR="0x20058000"
++# CONFIG_LONG_TEST is not set
++CONFIG_DEBUG=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_LOUD is not set
++# CONFIG_DEBUG_VERY_LOUD is not set
++CONFIG_HW_INIT=y
++# CONFIG_USER_HW_INIT is not set
++CONFIG_THUMB=y
++# CONFIG_SX_AT91 is not set
++# CONFIG_RAW_AT91 is not set
+diff --git a/board/vulcano-g20/vulcano-g20sd_defconfig b/board/vulcano-g20/vulcano-g20sd_defconfig
+new file mode 100644
+index 0000000..7381968
+--- /dev/null
++++ b/board/vulcano-g20/vulcano-g20sd_defconfig
+@@ -0,0 +1,110 @@
++#
++# Automatically generated make config: don't edit
++# Mon Jan 24 19:40:37 2011
++#
++HAVE_DOT_CONFIG=y
++CONFIG_BOARDNAME="vulcano-g20sd"
++# CONFIG_AT91SAM9260EK is not set
++# CONFIG_AT91SAM9261EK is not set
++# CONFIG_AT91SAM9263EK is not set
++# CONFIG_AT91SAM9RLEK is not set
++# CONFIG_AT91SAM9XEEK is not set
++# CONFIG_AT91SAM9G10EK is not set
++# CONFIG_AT91SAM9G20EK is not set
++CONFIG_VULCANOG20=y
++# CONFIG_AT91SAM9G45EK is not set
++# CONFIG_AT91SAM9G45EKES is not set
++# CONFIG_AT91SAM9M10EK is not set
++# CONFIG_AT91SAM9M10EKES is not set
++# CONFIG_AT91CAP9ADK is not set
++# CONFIG_AT91CAP9STK is not set
++# CONFIG_AFEB9260 is not set
++CONFIG_CHIP="AT91SAM9G20"
++CONFIG_BOARD="vulcano-g20"
++CONFIG_MACH_TYPE="0x658"
++CONFIG_LINK_ADDR="0x000000"
++CONFIG_TOP_OF_MEMORY="0x304000"
++# CONFIG_CRYSTAL_12_000MHZ is not set
++# CONFIG_CRYSTAL_16_000MHZ is not set
++# CONFIG_CRYSTAL_16_36766MHZ is not set
++CONFIG_CRYSTAL_18_432MHZ=y
++ALLOW_CRYSTAL_18_432MHZ=y
++CONFIG_CRYSTAL="CRYSTAL_18_432MHZ"
++# CONFIG_CPU_CLK_166MHZ is not set
++# CONFIG_CPU_CLK_180MHZ is not set
++# CONFIG_CPU_CLK_200MHZ is not set
++# CONFIG_CPU_CLK_240MHZ is not set
++# CONFIG_CPU_CLK_266MHZ is not set
++CONFIG_CPU_CLK_400MHZ=y
++ALLOW_CPU_CLK_400MHZ=y
++# DISABLE_CPU_CLK_240MHZ is not set
++# CONFIG_BUS_SPEED_83MHZ is not set
++# CONFIG_BUS_SPEED_90MHZ is not set
++# CONFIG_BUS_SPEED_100MHZ is not set
++CONFIG_BUS_SPEED_133MHZ=y
++
++#
++# Memory selection
++#
++CONFIG_SDRAM=y
++# CONFIG_SDDRC is not set
++# CONFIG_DDR2 is not set
++ALLOW_DATAFLASH=y
++# ALLOW_FLASH is not set
++ALLOW_NANDFLASH=y
++ALLOW_SDCARD=y
++# ALLOW_HSMCI is not set
++# ALLOW_PSRAM is not set
++# ALLOW_SDRAM_16BIT is not set
++# CONFIG_RAM_32MB is not set
++CONFIG_RAM_64MB=y
++# CONFIG_RAM_128MB is not set
++# CONFIG_RAM_256MB is not set
++# CONFIG_DATAFLASH is not set
++# CONFIG_FLASH is not set
++# CONFIG_NANDFLASH is not set
++CONFIG_SDCARD=y
++CONFIG_MEMORY="sdcard"
++# CONFIG_SDCARD_HS is not set
++ALLOW_DATAFLASH_RECOVERY=y
++ALLOW_BOOT_FROM_DATAFLASH_CS0=y
++ALLOW_BOOT_FROM_DATAFLASH_CS1=y
++# DATAFLASHCARD_ON_CS0 is not set
++DATAFLASHCARD_ON_CS1=y
++CONFIG_BOOTSTRAP_MAXSIZE="23000"
++CONFIG_PROJECT="sdcard"
++# CONFIG_LOAD_UBOOT is not set
++# CONFIG_LOAD_EBOOT is not set
++CONFIG_LOAD_LINUX=y
++# CONFIG_LOAD_NK is not set
++# CONFIG_LOAD_64KB is not set
++# CONFIG_LOAD_1MB is not set
++# CONFIG_LOAD_4MB is not set
++CONFIG_ALT_IMG_ADDRESS="0x00000000"
++CONFIG_ALT_IMG_SIZE="0x00010000"
++
++#
++# Linux Image Storage Setup
++#
++CONFIG_OS_MEM_BANK="0x20000000"
++CONFIG_OS_MEM_SIZE="0x4000000"
++CONFIG_LINUX_KERNEL_ARG_STRING="mem=64M console=ttyS0,115200 root=/dev/mmcblk0p2 rootdelay=2"
++CONFIG_OS_IMAGE_NAME="image.bin"
++CONFIG_OS_IMG_SIZE="0x280000"
++CONFIG_IMG_ADDRESS="0x00000000"
++CONFIG_SETTING_ADDRESS="0x00000000"
++CONFIG_SETTING_SIZE="0x00001000"
++CONFIG_IMG_SIZE="0x00280000"
++CONFIG_JUMP_ADDR="0x22000000"
++CONFIG_ALT_JUMP_ADDR="0x20000000"
++CONFIG_GLBDRV_ADDR="0x20058000"
++# CONFIG_LONG_TEST is not set
++CONFIG_DEBUG=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_LOUD is not set
++# CONFIG_DEBUG_VERY_LOUD is not set
++CONFIG_HW_INIT=y
++# CONFIG_USER_HW_INIT is not set
++CONFIG_THUMB=y
++# CONFIG_SX_AT91 is not set
++# CONFIG_RAW_AT91 is not set
+--
+1.7.0.4
+
diff --git a/recipes/at91bootstrap/at91bootstrap_3.0.bb b/recipes/at91bootstrap/at91bootstrap_3.0.bb
index 6b8629761c..4a37c238a9 100644
--- a/recipes/at91bootstrap/at91bootstrap_3.0.bb
+++ b/recipes/at91bootstrap/at91bootstrap_3.0.bb
@@ -28,6 +28,11 @@ SRC_URI_append = " \
file://0017-at91bootstrap-fix-build-error-in-openembedded-due-to.patch;apply=yes \
file://0018-Change-switch-statements-to-if-statements-to-avoid-b.patch;apply=yes \
"
+
+SRC_URI_append_vulcano-g20 = " \
+ file://vG20/0001-at91bootstrap-Add-VulcanoG20-support-on-common-files.patch;apply=yes;striplevel=1 \
+ file://vG20/0002-at91bootstrap-Add-VulcanoG20-board.patch;apply=yes;striplevel=1 \
+ "
# S = "${WORKDIR}/${PN}-${PV}"
S = "${WORKDIR}/bootstrap30"