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authorKhem Raj <raj.khem@gmail.com>2009-03-13 07:44:36 -0700
committerKhem Raj <raj.khem@gmail.com>2009-03-13 07:44:36 -0700
commit151270f47ba3382b708a6bb86b90baef43bf3c7a (patch)
treeda1a7974d528e3c44641f8133ece51e45e19d812
parent3992e7dd4369223e190c2ab61fcc601dd1e5ecc7 (diff)
parente49b45906527062083b716c33c840b49e3c8741c (diff)
downloadopenembedded-151270f47ba3382b708a6bb86b90baef43bf3c7a.tar.gz
openembedded-151270f47ba3382b708a6bb86b90baef43bf3c7a.tar.bz2
openembedded-151270f47ba3382b708a6bb86b90baef43bf3c7a.zip
Merge branch 'org.openembedded.dev' of git@git.openembedded.net:openembedded into org.openembedded.dev
-rw-r--r--classes/kernel.bbclass4
-rw-r--r--conf/checksums.ini364
-rw-r--r--conf/distro/include/preferred-om-2008-versions.inc27
-rw-r--r--conf/distro/include/sane-srcrevs.inc6
-rw-r--r--conf/machine/dm355-leopard.conf19
-rwxr-xr-xcontrib/angstrom/build-feeds.sh2
-rw-r--r--packages/cmake/cmake-native_2.6.3.bb11
-rw-r--r--packages/dsplink/gstreamer-ti_svn.bb2
-rw-r--r--packages/llvm/llvm-native_2.5.bb15
-rw-r--r--packages/proftpd/files/make.patch51
-rw-r--r--packages/proftpd/proftpd_1.3.2.bb36
-rw-r--r--packages/python/python-coherence_0.6.0.bb15
-rw-r--r--packages/python/python-coherence_0.6.2.bb7
-rw-r--r--packages/thttpd/thttpd_2.25b.bb4
-rw-r--r--packages/u-boot/u-boot-1.2.0/dm355-leopard.diff48455
-rw-r--r--packages/u-boot/u-boot_1.2.0.bb2
-rw-r--r--packages/wt/wt3-2.99.0/ext.patch7
-rw-r--r--packages/wt/wt3-2.99.0/src.patch18
-rw-r--r--packages/wt/wt3-2.99.0/wgooglemap.patch15
-rw-r--r--packages/wt/wt3_2.99.0.bb41
-rw-r--r--packages/zope/zope_3.3.1.bb6
21 files changed, 49050 insertions, 57 deletions
diff --git a/classes/kernel.bbclass b/classes/kernel.bbclass
index 86f00da5cf..4c1dbda35c 100644
--- a/classes/kernel.bbclass
+++ b/classes/kernel.bbclass
@@ -295,12 +295,14 @@ python populate_packages_prepend () {
def extract_modinfo(file):
import tempfile, os, re
tempfile.tempdir = bb.data.getVar("WORKDIR", d, 1)
- tmpfile = tempfile.mkstemp()[1]
+ tf = tempfile.mkstemp()
+ tmpfile = tf[1]
cmd = "PATH=\"%s\" %sobjcopy -j .modinfo -O binary %s %s" % (bb.data.getVar("PATH", d, 1), bb.data.getVar("HOST_PREFIX", d, 1) or "", file, tmpfile)
os.system(cmd)
f = open(tmpfile)
l = f.read().split("\000")
f.close()
+ os.close(tf[0])
os.unlink(tmpfile)
exp = re.compile("([^=]+)=(.*)")
vals = {}
diff --git a/conf/checksums.ini b/conf/checksums.ini
index 2beb03ee7e..815726872f 100644
--- a/conf/checksums.ini
+++ b/conf/checksums.ini
@@ -426,6 +426,10 @@ sha256=0ef94a1857e03e826825c559b5b8f07a4b412112fb9326f5eb694d5216747071
md5=4769d70bcd9d8390afb64c5eddfcd60e
sha256=0ef94a1857e03e826825c559b5b8f07a4b412112fb9326f5eb694d5216747071
+[http://kernel.org//pub/linux/libs/pam/pre/library/Linux-PAM-0.79.tar.bz2]
+md5=0b89b73970c7d490ad9a13718b74d27b
+sha256=5ed480cb76c91c2739ddba87f15437510e58c60dfdd7ead6f469149b2da94bb7
+
[http://kernel.org/pub/linux/libs/pam/pre/library/Linux-PAM-0.79.tar.bz2]
md5=0b89b73970c7d490ad9a13718b74d27b
sha256=5ed480cb76c91c2739ddba87f15437510e58c60dfdd7ead6f469149b2da94bb7
@@ -630,14 +634,6 @@ sha256=fbd907dde45054227568f3117df0418a7819cfee02875d3723779432e8a66dc9
md5=f766680bb237ca2f837c005efba54efa
sha256=fbd907dde45054227568f3117df0418a7819cfee02875d3723779432e8a66dc9
-[http://download.java.net/openjdk/jdk6/promoted/b12/openjdk-6-src-b12-28_aug_2008.tar.gz]
-md5=b53e1ef643909ce82721ee4c970d958b
-sha256=f099b3b1f3c22b8cea950403b992267ec69f43ad8a80bbcb84448b26340807ab
-
-[http://download.java.net/openjdk/jdk6/promoted/b14/openjdk-6-src-b14-25_nov_2008.tar.gz]
-md5=9f9773a822156dd3d576d83d794364ce
-sha256=1272f975052e51d3faf2d7ac13d0b8b4ac68019a688bffe03d9b684a9e3b4480
-
[http://downloads.sourceforge.net/openjade/OpenSP-1.5.tar.gz]
md5=87f56e79ae0c20397f4207d61d154303
sha256=987eeb9460185950e066e5db3b5fa531e53e213742b545288405552a5a7bb704
@@ -1942,26 +1938,50 @@ sha256=f0cde70a8f135098a6a3e85869f2e1cc3f141beea766fa3d6636e086cd8b90a7
md5=36d3fe706ad0950f1be10c46a429efe0
sha256=93a2ceab963618b021db153f0c881a2de82455c1dc7422be436fcd5c554085a1
+[http://kernel.org//pub/linux/daemons/autofs/v3/autofs-3.1.7.tar.bz2]
+md5=4f602f82442b48ce9c2e0005d59c3408
+sha256=838c6e92c39827b54a37559a02c9b409a4f7ec3124cc6d20845aabfaabe2dd18
+
[http://kernel.org/pub/linux/daemons/autofs/v3/autofs-3.1.7.tar.bz2]
md5=4f602f82442b48ce9c2e0005d59c3408
sha256=838c6e92c39827b54a37559a02c9b409a4f7ec3124cc6d20845aabfaabe2dd18
+[http://kernel.org//pub/linux/daemons/autofs/v4/old/autofs-4.0.0-1.tar.bz2]
+md5=eca614ef301b49aa8105876e8abd91b5
+sha256=f5555e41fc351644fd5ff935c2d2340719a18fa32d1f6ccdc6bbd4c18a694f88
+
[http://kernel.org/pub/linux/daemons/autofs/v4/old/autofs-4.0.0-1.tar.bz2]
md5=eca614ef301b49aa8105876e8abd91b5
sha256=f5555e41fc351644fd5ff935c2d2340719a18fa32d1f6ccdc6bbd4c18a694f88
+[http://kernel.org//pub/linux/daemons/autofs/v4/autofs-4.1.4-misc-fixes.patch]
+md5=6342d6908c35af72b29231ecc6a10b5a
+sha256=4fc5725c683405e0da29021aacb3674c71ce1b61f62b810430aa112644773cf8
+
[http://kernel.org/pub/linux/daemons/autofs/v4/autofs-4.1.4-misc-fixes.patch]
md5=6342d6908c35af72b29231ecc6a10b5a
sha256=4fc5725c683405e0da29021aacb3674c71ce1b61f62b810430aa112644773cf8
+[http://kernel.org//pub/linux/daemons/autofs/v4/autofs-4.1.4-multi-parse-fix.patch]
+md5=2783f4498c7e90a2cbf93b44d4fc4b94
+sha256=91d852ae612b19862d3925a807c319c74a0a06cc7a8f7390715591b6e1110108
+
[http://kernel.org/pub/linux/daemons/autofs/v4/autofs-4.1.4-multi-parse-fix.patch]
md5=2783f4498c7e90a2cbf93b44d4fc4b94
sha256=91d852ae612b19862d3925a807c319c74a0a06cc7a8f7390715591b6e1110108
+[http://kernel.org//pub/linux/daemons/autofs/v4/autofs-4.1.4-non-replicated-ping.patch]
+md5=b7d81c9aa92884d55ce5a1075d49fe78
+sha256=398c921161a57f1d87a5829ea264deed9e2f3adc64ac011f7f0490257d31b633
+
[http://kernel.org/pub/linux/daemons/autofs/v4/autofs-4.1.4-non-replicated-ping.patch]
md5=b7d81c9aa92884d55ce5a1075d49fe78
sha256=398c921161a57f1d87a5829ea264deed9e2f3adc64ac011f7f0490257d31b633
+[http://kernel.org//pub/linux/daemons/autofs/v4/autofs-4.1.4.tar.bz2]
+md5=7e3949114c00665b4636f0c318179657
+sha256=e25caa0e9639ea54dd7c4f21e8146ac9859a61fa126f397edf874b5fdc147430
+
[http://kernel.org/pub/linux/daemons/autofs/v4/autofs-4.1.4.tar.bz2]
md5=7e3949114c00665b4636f0c318179657
sha256=e25caa0e9639ea54dd7c4f21e8146ac9859a61fa126f397edf874b5fdc147430
@@ -2382,10 +2402,18 @@ sha256=275f4d19b8af8bbc93eda9d8532c21d32cd30195db82f15f10916c02416f9f03
md5=0ccd96cc01351c0562f1e4b94aaa2790
sha256=3151893aa5597491b7cb7083b4e786017b522cac55dffacbe475c9abdd7fe61a
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.14.90.0.6.tar.bz2]
+md5=71b99dba3045a359dc314dbebedcf502
+sha256=6f75f36f35d16fd1fdc6600926af3ceaaa3bdca4e91ae3bf22891594afa0116e
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.14.90.0.6.tar.bz2]
md5=71b99dba3045a359dc314dbebedcf502
sha256=6f75f36f35d16fd1fdc6600926af3ceaaa3bdca4e91ae3bf22891594afa0116e
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.14.90.0.7.tar.bz2]
+md5=b5b1608f7308c487c0f3af8e4592a71a
+sha256=204c2624b5712a3482d0e774bb84850c1ee6b1ccdfd885abfe1f7c23abf4f5c0
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.14.90.0.7.tar.bz2]
md5=b5b1608f7308c487c0f3af8e4592a71a
sha256=204c2624b5712a3482d0e774bb84850c1ee6b1ccdfd885abfe1f7c23abf4f5c0
@@ -2398,6 +2426,10 @@ sha256=e8df35e97d6789fd34268e8c2e4daba8aa17e7bf6f0432f6ea8123a2e344363c
md5=4a4cde8e5d0c97249bf6933f095813fe
sha256=c4ad801a7ed5a4e3d5d943d73c82f0af75998c95b69184dc884460bf40e48ee9
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.15.94.0.1.tar.bz2]
+md5=4a4cde8e5d0c97249bf6933f095813fe
+sha256=c4ad801a7ed5a4e3d5d943d73c82f0af75998c95b69184dc884460bf40e48ee9
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.15.94.0.1.tar.bz2]
md5=4a4cde8e5d0c97249bf6933f095813fe
sha256=c4ad801a7ed5a4e3d5d943d73c82f0af75998c95b69184dc884460bf40e48ee9
@@ -2406,6 +2438,10 @@ sha256=c4ad801a7ed5a4e3d5d943d73c82f0af75998c95b69184dc884460bf40e48ee9
md5=6a9d529efb285071dad10e1f3d2b2967
sha256=351a6846ee179a37ed87a487971547159a7f4f92a1dec598c727f184a0de61ae
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.16.91.0.6.tar.bz2]
+md5=00ef9f1429d5f18702d08552f5c09441
+sha256=7cffa91af850d3fd5f086e3690eae05c1d9d5ad82f915b36f0de920a3c9920be
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.16.91.0.6.tar.bz2]
md5=00ef9f1429d5f18702d08552f5c09441
sha256=7cffa91af850d3fd5f086e3690eae05c1d9d5ad82f915b36f0de920a3c9920be
@@ -2414,6 +2450,10 @@ sha256=7cffa91af850d3fd5f086e3690eae05c1d9d5ad82f915b36f0de920a3c9920be
md5=26c3fddb07bfe3128d2e09e628eb33a0
sha256=af9cfdde06693ecaaf3b558e6a66e7245d04cb981812ce06d023de868aa92b41
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.16.91.0.7.tar.bz2]
+md5=26c3fddb07bfe3128d2e09e628eb33a0
+sha256=af9cfdde06693ecaaf3b558e6a66e7245d04cb981812ce06d023de868aa92b41
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.16.91.0.7.tar.bz2]
md5=26c3fddb07bfe3128d2e09e628eb33a0
sha256=af9cfdde06693ecaaf3b558e6a66e7245d04cb981812ce06d023de868aa92b41
@@ -2430,18 +2470,34 @@ sha256=5645c3371aac47cbbcc1354eab10ec32777837d7cb4ba47b94c9043612b12f36
md5=64905b00a89f4e7ba3b3991c89ba59a4
sha256=1e041ad002aa2f7a06624afcb4a9832085c63abe0a9551cdbc40522aac18871a
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.17.50.0.1.tar.bz2]
+md5=cfecfb29e260225fa192654f3763c2f8
+sha256=9a56b06e4f533745e9b7cde5b170f905f74d130b899f48498cbd6d376c664b7a
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.17.50.0.1.tar.bz2]
md5=cfecfb29e260225fa192654f3763c2f8
sha256=9a56b06e4f533745e9b7cde5b170f905f74d130b899f48498cbd6d376c664b7a
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.17.50.0.12.tar.bz2]
+md5=6f3e83399b965d70008860f697c50ec2
+sha256=7360808266f72aed6fda41735242fb9f1b6dd3307cd6e283a646932438eaa929
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.17.50.0.12.tar.bz2]
md5=6f3e83399b965d70008860f697c50ec2
sha256=7360808266f72aed6fda41735242fb9f1b6dd3307cd6e283a646932438eaa929
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.17.50.0.5.tar.bz2]
+md5=00eccd47e19a9f24410a137a849aa3fc
+sha256=bbfa06ee0173c5e9ae65ff14ba29502ddf4e355ac3419f88e3346299cfaf4e19
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.17.50.0.5.tar.bz2]
md5=00eccd47e19a9f24410a137a849aa3fc
sha256=bbfa06ee0173c5e9ae65ff14ba29502ddf4e355ac3419f88e3346299cfaf4e19
+[http://kernel.org//pub/linux/devel/binutils/binutils-2.17.50.0.8.tar.bz2]
+md5=1441fe6fa44b344d0575cb66d3f89252
+sha256=016b0faa1bbe20c13a4b5f495a5a4071349f6385012b767c89bb908452faecf2
+
[http://kernel.org/pub/linux/devel/binutils/binutils-2.17.50.0.8.tar.bz2]
md5=1441fe6fa44b344d0575cb66d3f89252
sha256=016b0faa1bbe20c13a4b5f495a5a4071349f6385012b767c89bb908452faecf2
@@ -3538,6 +3594,10 @@ sha256=f20607d4f33376ea648307681630574662d0c3f59d88a7a02ad547b6320631f1
md5=e95ae003672dfc6c8151a1ee49a0d4a6
sha256=4999d3054a04e6cf4847a72316e32e9e98e6152b1fd72adc87d15e305f990f27
+[http://www.cmake.org/files/v2.6/cmake-2.6.3.tar.gz]
+md5=5ba47a94ce276f326abca1fd72a7e7c6
+sha256=3c3af80526a32bc2afed616e8f486b847144f2fa3a8e441908bd39c38b146450
+
[http://install.tarball.in.source.dir/codec_engine_2_10_01.tar.gz]
md5=32b0df93b285ee094e053552d9301cb6
sha256=eb9f4b4b5973f444d16920201dfea217fb30542fea23107cf80a1f189408b321
@@ -4438,6 +4498,10 @@ sha256=ca494bf9c1ccf2e74bee90cf903743eee78a0dfa5d9bf0840bc59c4ad498f9de
md5=94d5fb06d091804b31658481f23b120f
sha256=31e8e536f5efd7d7d1d5f4e4458b42aa9cd7910acf3da933cb7fa3507cf7f752
+[http://kernel.org//pub/linux/utils/kernel/hotplug/diethotplug-0.4.tar.gz]
+md5=1fd89c902006271f00a774cc3183c15d
+sha256=dcc1809e8477b95317a7ff503cdd8b6d3f85b8d83a3245252ff47cf631523620
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/diethotplug-0.4.tar.gz]
md5=1fd89c902006271f00a774cc3183c15d
sha256=dcc1809e8477b95317a7ff503cdd8b6d3f85b8d83a3245252ff47cf631523620
@@ -5438,6 +5502,10 @@ sha256=7754930742d3c3cc2a05af38263ba58ba416b7359f8a0c598ae0f7377277d3b3
md5=6505c9d18ef6b5ce13fe2a668eb5724b
sha256=f7ff9bf972139b303616018a6937aa4c6df4e93c935ffd004b30845e2ad41ea6
+[http://hg.openjdk.java.net/jdk7/hotspot/hotspot/archive/f9d938ede196.tar.gz]
+md5=c8f78d48ac83987bc2adebeebcd354e9
+sha256=89952cf8bbe1bcce91c2c1fcf9a071991a890b3f8a783dee741cdb23c8ac763a
+
[http://downloads.sourceforge.net/faac/faac-1.24.tar.gz]
md5=e72dc74db17b42b06155613489077ad7
sha256=a5844ff3bce0d7c885af71f41da01395d3253dcfc33863306a027a78a7cfad9e
@@ -9914,10 +9982,18 @@ sha256=f4754629eb70a63e9774ac97ebd28f3dea22fb5b422dd43d02ab5053d37ca61c
md5=ed669d96346dfc7d9f9fad079731853f
sha256=a99908d5765757ad6025b57d5ecf43b412aaaaf2ca379c02aafa33ca5c9d35c1
+[http://kernel.org//pub/linux/utils/kernel/hotplug/hotplug-2004_03_29.tar.gz]
+md5=167bd479a1ca30243c51ca088e0942b3
+sha256=397e06eefc4639342e9f650cc47336ebc8c86a37fdcd9b857e55f99d37d8da9f
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/hotplug-2004_03_29.tar.gz]
md5=167bd479a1ca30243c51ca088e0942b3
sha256=397e06eefc4639342e9f650cc47336ebc8c86a37fdcd9b857e55f99d37d8da9f
+[http://kernel.org//pub/linux/utils/kernel/hotplug/hotplug-2004_09_20.tar.gz]
+md5=9e6b06dfa3b91f051b55e1483adb5a68
+sha256=3f2d989f7cbef92612b1ecd913398fc42165e29f214fdf68fa997a8e5b2a138f
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/hotplug-2004_09_20.tar.gz]
md5=9e6b06dfa3b91f051b55e1483adb5a68
sha256=3f2d989f7cbef92612b1ecd913398fc42165e29f214fdf68fa997a8e5b2a138f
@@ -9926,17 +10002,21 @@ sha256=3f2d989f7cbef92612b1ecd913398fc42165e29f214fdf68fa997a8e5b2a138f
md5=75245aa9adc5acb9d6ac8eae45533c96
sha256=96144ffbb24f23acd3615594344902a3fad241bc05127d38e5dde8df300c27c0
+[http://kernel.org//pub/linux/utils/kernel/hotplug/hotplug-ng-001.tar.gz]
+md5=e81d4159a01620b37721b2a05d6a4740
+sha256=af40399fe434678454ae8ea100db6cba0482aa65b8972a05098c779cac57bc48
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/hotplug-ng-001.tar.gz]
md5=e81d4159a01620b37721b2a05d6a4740
sha256=af40399fe434678454ae8ea100db6cba0482aa65b8972a05098c779cac57bc48
-[http://kernel.org/pub/linux/utils/kernel/hotplug/hotplug-ng-002.tar.gz]
+[http://kernel.org//pub/linux/utils/kernel/hotplug/hotplug-ng-002.tar.gz]
md5=faa08f321fefd2c61ce4c9355a62fe31
sha256=ca7ef124cde06883fbf28c7e78ce1e4c5526434bbe5672ef0a3e85a61a9d0b5f
-[http://hg.openjdk.java.net/jdk7/hotspot/hotspot/archive/f9d938ede196.tar.gz]
-md5=c8f78d48ac83987bc2adebeebcd354e9
-sha256=89952cf8bbe1bcce91c2c1fcf9a071991a890b3f8a783dee741cdb23c8ac763a
+[http://kernel.org/pub/linux/utils/kernel/hotplug/hotplug-ng-002.tar.gz]
+md5=faa08f321fefd2c61ce4c9355a62fe31
+sha256=ca7ef124cde06883fbf28c7e78ce1e4c5526434bbe5672ef0a3e85a61a9d0b5f
[http://www.porchdogsoft.com/download/howl-0.9.7.tar.gz]
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@@ -10122,10 +10202,6 @@ sha256=ef6b1c8def236f16ea914eccbb050c84ee314c0028b03c560ed20ff96776f74c
md5=641ec45fe377529c7fd914f77b11b44f
sha256=9ff8360375432a7a5c476cc6d55b3fdea9d6f3edc080d295a60421d8f47b1834
-[http://jalimo.evolvis.org/repository/sources/icepick-0.0+hg20080118.tar.bz2]
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-
[http://icedtea.classpath.org/download/source/icedtea6-1.3.1.tar.gz]
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sha256=c15fb24475ad93e064ba252f2739c020f9981a808bde6cbd6c41eae38dd0143d
@@ -10134,6 +10210,10 @@ sha256=c15fb24475ad93e064ba252f2739c020f9981a808bde6cbd6c41eae38dd0143d
md5=6428ca1b0c38111cca230f5b69460b03
sha256=4f23aadcee80a9a03c858e36a8eaaa92149987ce0a3eac276e3003c9b2462739
+[http://jalimo.evolvis.org/repository/sources/icepick-0.0+hg20080118.tar.bz2]
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[http://ftp.de.debian.org/debian/pool/main/i/iceweasel/iceweasel_3.0.1-1.diff.gz]
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sha256=1d70e21e1c20e8d88bf3d2590de75c3e65b12da335097716adc58712cea41dad
@@ -10422,6 +10502,10 @@ sha256=2dd29e066dece7062cb30daeedad7e5baa0b5cb993c67ba700ebacd6e0212487
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sha256=49521feb1a6e2bc9b355e93b3251e3c74ebe2327eb89c6e681347464e81e3664
+[http://kernel.org//pub/linux/kernel/people/ck/apps/interbench/interbench-0.30.tar.bz2]
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[http://kernel.org/pub/linux/kernel/people/ck/apps/interbench/interbench-0.30.tar.bz2]
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sha256=a77d4a82573b07a9f6c6d256b399accea1f6cd433f3f1e6d038272cf0d320365
@@ -10730,6 +10814,14 @@ sha256=18b269b1bfad7230384681e89189c6af18584e19cddbf92208c0acef814046ab
md5=a965452442cdbfc94caba57d0dd25a8f
sha256=18b269b1bfad7230384681e89189c6af18584e19cddbf92208c0acef814046ab
+[http://downloads.sourceforge.net/jamvm/jamvm-1.5.1.tar.gz]
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+[http://heanet.dl.sourceforge.net/jamvm/jamvm-1.5.1.tar.gz]
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+
[http://downloads.sourceforge.net/jamvm/jamvm-1.5.2.tar.gz]
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sha256=76c976616d344a3b1abd8896be6610c4d97a58af6960e1bc2f442b774bdda839
@@ -10942,6 +11034,10 @@ sha256=d6b21f0dad8277925abbb15d3c9cbc0a58af5b5119bbd1fde8637b600bae0489
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sha256=ad5d912a4c726015e351981b5c71014f6cbd6b9d79d6b58d89ea8b4ffa31bb76
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[http://kernel.org/pub/linux/kernel/people/ck/apps/kernbench/kernbench-0.41.tar.bz2]
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sha256=6d5de792b0a3b119da3b584eb64076ed192d050516f7d44a36f95ecd8cf32362
@@ -11014,10 +11110,18 @@ sha256=1b998b34e2e9377f5ac7704295d64507234fe7656e49d384f8bf95604e97e05b
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sha256=023e7f47039c1ad8615052e464f76a3cd496a423449b931036d127c56d58b2b9
+[http://kernel.org//pub/linux/libs/klibc/Stable/klibc-0.190.tar.bz2]
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[http://kernel.org/pub/linux/libs/klibc/Stable/klibc-0.190.tar.bz2]
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sha256=5767cbb094300c5e26eb0bab588ecdbf9e5db2a637e9ae73c2efb8a62e05217e
+[http://kernel.org//pub/linux/libs/klibc/Stable/klibc-1.1.1.tar.bz2]
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+
[http://kernel.org/pub/linux/libs/klibc/Stable/klibc-1.1.1.tar.bz2]
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sha256=6a2efdfc757c518a8185f457799506086084b59498f53db37cfb6728008127e0
@@ -11058,6 +11162,10 @@ sha256=7a1bd7d4bd326828c8ee382ed2b69ccd6c58762601df897d6a32169d84583d2a
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sha256=650f0b3ae4d30282b191e456ebf2679a4ec549da83f69667bd4396bad9abf9f5
+[http://kernel.org//pub/linux/utils/kernel/ksymoops/v2.4/ksymoops-2.4.9.tar.bz2]
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+
[http://kernel.org/pub/linux/utils/kernel/ksymoops/v2.4/ksymoops-2.4.9.tar.bz2]
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sha256=125fcecc9f650dc2ec82db3194d17c0af40b48900204fedb0c695b5fcc5a99e3
@@ -11206,6 +11314,10 @@ sha256=e5ef90ff30897448a7c090c2e31ceb302ed064a60411436e8995580848ed1a63
md5=ab895165c149d7f95843c7584b1c7ad4
sha256=e5ef90ff30897448a7c090c2e31ceb302ed064a60411436e8995580848ed1a63
+[ftp://ftp.wiretapped.net/pub/mirrors/lftp/old/lftp-3.5.1.tar.bz2]
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+
[http://ftp.yars.free.net/pub/source/lftp/old/lftp-3.5.1.tar.bz2]
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sha256=463f0b46ce3a0fc09ef9ad7a5429959034d50a1eadbed5dfeae36c25dca31130
@@ -11938,6 +12050,10 @@ sha256=97f63ed9c2d685a25306bd5ffa4bdf0a5e296c9ad28fd7210e6e53f75cf6dcc4
md5=2623370bfcecaeecaeb85e5ec445f340
sha256=b0e3cb59e605412a52352cf9cf36344b165463d4e65916c95deb73fc51838272
+[http://kernel.org//pub/linux/libs/security/linux-privs/kernel-2.4/libcap-1.10.tar.bz2]
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[http://kernel.org/pub/linux/libs/security/linux-privs/kernel-2.4/libcap-1.10.tar.bz2]
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sha256=66c3f033fdc8f9ba0bd9d0ae2d1f2c11f9fa51bf0d1418e5cb75e29e6577a5bc
@@ -14258,38 +14374,74 @@ sha256=ba1c32207fd62d374c9397a81fb1247da93edb859e30d0d855dc65e5457f690b
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sha256=3dcafe41355fcc688f4a376a5dc71901ea2fbb95698397c87c6a6b12aa058c69
+[http://kernel.org//pub/linux/kernel/v2.4/linux-2.4.18.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.4/linux-2.4.18.tar.bz2]
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sha256=90d9a45ba395f742050f791b6944f6263d0ab03c84aad8a32967ca866906490e
+[http://kernel.org//pub/linux/kernel/v2.4/linux-2.4.24.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.4/linux-2.4.24.tar.bz2]
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sha256=9a6c37e048376cd2a9845f6f75cb44fb27c244d719e9d9dd81063a525f081e1f
+[http://kernel.org//pub/linux/kernel/v2.4/linux-2.4.25.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.4/linux-2.4.25.tar.bz2]
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sha256=877af8ed89e56af004bb0662c1a9cfc785b40c602f71a8bf81521991026cf2f0
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.11.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/testing/linux-2.6.12-rc2.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/testing/linux-2.6.12-rc5.tar.bz2]
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sha256=4cc5ca6e2ea8583f026620169e5d6eceb6c620181ba0633efbeb74cdb8c2fc59
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.12.6.tar.bz2]
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sha256=d8bbdd8064c3564e6ec74fec3332776733e7982e67af66c5311fd1955bf309dd
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.12.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.12.tar.bz2]
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sha256=727b55291a2c52f9f6b9f7ef03b2cd9fc54f7d4d1b0b2baed4c3dd6d9a890c71
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.14.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.14.tar.bz2]
md5=66d02cbd723876c6d69846a067875a22
sha256=cc56285834bed461fd405c00a34d3c3095673333b94621580eeeb0c65237af15
@@ -14298,14 +14450,26 @@ sha256=cc56285834bed461fd405c00a34d3c3095673333b94621580eeeb0c65237af15
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sha256=69468ffe7dade5448c498230bd67fd5a9b843ef1b11ea3fe7161b2c7fc26ea77
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.16.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.16.tar.bz2]
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sha256=1200dcc7e60fcdaf68618dba991917a47e41e67099e8b22143976ec972e2cad7
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.17.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.17.tar.bz2]
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sha256=ab0f647d52f124958439517df9e1ae0efda90cdb851f59f522fa1749f1d87d58
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.18.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.18.tar.bz2]
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sha256=c95280ff6c5d2a17788f7cc582d23ae8a9a7ba3f202ec6e4238eaadfce7c163d
@@ -14314,6 +14478,10 @@ sha256=c95280ff6c5d2a17788f7cc582d23ae8a9a7ba3f202ec6e4238eaadfce7c163d
md5=ca0ce8f288e8ae93ac243b568f906bf8
sha256=c55c52caa613d1f25718b35811e4614d9712b9e1de56a91aa73c867f351a540b
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.19.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.19.tar.bz2]
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sha256=c2fd6bcd2b7c1b3d37d64e4d1825703792a75474830a3db7d2dc603a8d392d58
@@ -14322,6 +14490,10 @@ sha256=c2fd6bcd2b7c1b3d37d64e4d1825703792a75474830a3db7d2dc603a8d392d58
md5=691a9fd94de318aebb4b241fcff22cc6
sha256=4f8529718a45a570cfbf452760009960264028467f398769236b501c9338fc1e
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.20.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.20.tar.bz2]
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sha256=2c14ada1ac7d272e03b430d3a530d60fc9ec69cc8252382aa049afba7d2b8558
@@ -14342,6 +14514,10 @@ sha256=9ebfddb396465533944f2c3c3a2c6725ca33f5bfd260e491a8d98cff1abe7953
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sha256=9879bb214a12b15a6a589fe15c2acad3177b3a49fd03a26e79ae558755e98a4b
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.22.5.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.22.5.tar.bz2]
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sha256=7904cd53bf681611dff65d04afcdab6205f6e06cb0c40a568174d83a3a5d8a01
@@ -14350,6 +14526,10 @@ sha256=7904cd53bf681611dff65d04afcdab6205f6e06cb0c40a568174d83a3a5d8a01
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sha256=914424a9ae14cf6fa2debbfed327e071b43b06daf5085282cdb133a02fab1ca3
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.22.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.22.tar.bz2]
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sha256=73c10604c53f1a6ee65ef805293d23903696f8cef864f42d7de9506f0d2ba4c7
@@ -14426,6 +14606,10 @@ sha256=ae0d97c55efe7fce01273c97f8152af0deff5541e3bbf5b9ad98689112b54380
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sha256=ae0d97c55efe7fce01273c97f8152af0deff5541e3bbf5b9ad98689112b54380
+[http://kernel.org//pub/linux/kernel/v2.6/linux-2.6.9.tar.bz2]
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[http://kernel.org/pub/linux/kernel/v2.6/linux-2.6.9.tar.bz2]
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sha256=f5dba6366e87e91234d1b0069cfea655b0a4cb37ea97f899226f16998e6ab9f1
@@ -14434,6 +14618,10 @@ sha256=f5dba6366e87e91234d1b0069cfea655b0a4cb37ea97f899226f16998e6ab9f1
md5=84fef49cc39ff2605204246666f65864
sha256=a812816ee1742bf3bf8977a391b369a7351f54a1917dc90b27e666679dd1742a
+[http://kernel.org//pub/linux/kernel/people/dwmw2/kernel-headers/snapshot/linux-kernel-headers-2.6.19-rc1.tar.bz2]
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[http://kernel.org/pub/linux/kernel/people/dwmw2/kernel-headers/snapshot/linux-kernel-headers-2.6.19-rc1.tar.bz2]
md5=f1fc22939d71224923f168ba179b3e51
sha256=35b9045edc5992c2d168fc72ca04a57f4e1c81a0ea987fa88342e54f7c79fbd4
@@ -14546,6 +14734,10 @@ sha256=8cabd422f249ada736d864fc8a1f4d14aabefacb6f860c9beefbc53f93e0f96c
md5=bf43eee98c364fd79c7d2b72e645a15e
sha256=5fc295b3cf3de019962aee3be1c5efb49d6bf5041dae59451f6c0f544eb36bdc
+[http://llvm.org/releases/2.5/llvm-2.5.tar.gz]
+md5=55df2ea8665c8094ad2ef85187b9fc74
+sha256=8f3d69e63bc5d1ee2c2ee49ff07ccb7e070070a0e937813d2a6179b9e2e173ed
+
[http://dl.lm-sensors.org/lm-sensors/releases/lm_sensors-2.10.1.tar.gz]
md5=cdc857b78e813b88cbf8be92441aa299
sha256=a332cacfa9d0eed6e9158c394db714e536f38c27451d7df08b9634952118fa1b
@@ -15134,10 +15326,18 @@ sha256=8599712f2b2b3778eea344f59e1512cea284e802560317fac436585885a41dfa
md5=cb5e4656fc3b13aa02d94096966ef2a9
sha256=6d5f1f771de97e08378940070b28dd75ac394ea611965ed1751600adbd099a59
+[http://kernel.org//pub/linux/utils/man/man-1.5p.tar.bz2]
+md5=3800006ccd2f1f16124a2ac3abf04b30
+sha256=5431073fb315f9b8dd43f430d7a9082e0a6232e20af559604da573270df8236b
+
[http://kernel.org/pub/linux/utils/man/man-1.5p.tar.bz2]
md5=3800006ccd2f1f16124a2ac3abf04b30
sha256=5431073fb315f9b8dd43f430d7a9082e0a6232e20af559604da573270df8236b
+[http://kernel.org//pub/linux/docs/manpages/man-pages-2.41.tar.bz2]
+md5=7b193c2fcf1d8f625e998df54582fee9
+sha256=bc9e3fe06a550d6eb48fd84eaf58415c78fbc29ba042e4a074adb62736f50760
+
[http://kernel.org/pub/linux/docs/man-pages/Archive/man-pages-2.41.tar.bz2]
md5=7b193c2fcf1d8f625e998df54582fee9
sha256=bc9e3fe06a550d6eb48fd84eaf58415c78fbc29ba042e4a074adb62736f50760
@@ -15370,10 +15570,18 @@ sha256=f6ea98fb44e978966d41bf5ad7f662df33dd0ef236403753bfbbea93a1c34701
md5=04468563b3b6942e72844904f1c34e9b
sha256=1112d3ea07f519ca7a45b6c82b43a9d368ba2d8a4a4244172b5e66f63eee6fb8
+[http://kernel.org//pub/linux/utils/raid/mdadm/mdadm-1.12.0.tar.bz2]
+md5=736705240e918294740929518477fc6f
+sha256=22831449225cc39948b187c9e3bd89ba12d5c8abee18b2d0242da883cb7d9490
+
[http://kernel.org/pub/linux/utils/raid/mdadm/mdadm-1.12.0.tar.bz2]
md5=736705240e918294740929518477fc6f
sha256=22831449225cc39948b187c9e3bd89ba12d5c8abee18b2d0242da883cb7d9490
+[http://kernel.org//pub/linux/utils/raid/mdadm/mdadm-2.5.5.tar.bz2]
+md5=099bb5f340c5d334445dd003a6d86460
+sha256=d54ae28bdafdbd3c71bfafa8f8814583356714b6a1436783161413a1e34a38c9
+
[http://kernel.org/pub/linux/utils/raid/mdadm/mdadm-2.5.5.tar.bz2]
md5=099bb5f340c5d334445dd003a6d86460
sha256=d54ae28bdafdbd3c71bfafa8f8814583356714b6a1436783161413a1e34a38c9
@@ -15762,6 +15970,10 @@ sha256=d78a39b4158901695c59d0757e8fe622e9b4cebcfb77eedfc20b937e5a0d521d
md5=ac8e98865d90dca25c85748b3916bf07
sha256=d78a39b4158901695c59d0757e8fe622e9b4cebcfb77eedfc20b937e5a0d521d
+[http://kernel.org//pub/linux/utils/kernel/module-init-tools/module-init-tools-3.2.1.tar.bz2]
+md5=29aa770c6ce92cbbc6da00161d2784d8
+sha256=f7c66e151d3d89df02c41f82cae5c384cad76ad3956519a872d98d5676bddd47
+
[http://kernel.org/pub/linux/utils/kernel/module-init-tools/module-init-tools-3.2.1.tar.bz2]
md5=29aa770c6ce92cbbc6da00161d2784d8
sha256=f7c66e151d3d89df02c41f82cae5c384cad76ad3956519a872d98d5676bddd47
@@ -15770,6 +15982,10 @@ sha256=f7c66e151d3d89df02c41f82cae5c384cad76ad3956519a872d98d5676bddd47
md5=a1ad0a09d3231673f70d631f3f5040e9
sha256=c080f7e42e60456eab33051026da388b5d21a360e9d2bee26ce9991427a758aa
+[http://kernel.org//pub/linux/utils/kernel/module-init-tools/module-init-tools-3.2.2.tar.bz2]
+md5=a1ad0a09d3231673f70d631f3f5040e9
+sha256=c080f7e42e60456eab33051026da388b5d21a360e9d2bee26ce9991427a758aa
+
[http://kernel.org/pub/linux/utils/kernel/module-init-tools/module-init-tools-3.2.2.tar.bz2]
md5=a1ad0a09d3231673f70d631f3f5040e9
sha256=c080f7e42e60456eab33051026da388b5d21a360e9d2bee26ce9991427a758aa
@@ -15778,6 +15994,10 @@ sha256=c080f7e42e60456eab33051026da388b5d21a360e9d2bee26ce9991427a758aa
md5=db6ac059e80e8dd4389dbe81ee61f3c6
sha256=96c7a1b313722a5203d7a6c4cb89f09ac186f8565bb1666a6053979072633d87
+[http://kernel.org//pub/linux/utils/kernel/modutils/v2.4/modutils-2.4.27.tar.bz2]
+md5=bac989c74ed10f3bf86177fc5b4b89b6
+sha256=ab4c9191645f9ffb455ae7c014d8c45339c13a1d0f6914817cfbf30a0bc56bf0
+
[http://kernel.org/pub/linux/utils/kernel/modutils/v2.4/modutils-2.4.27.tar.bz2]
md5=bac989c74ed10f3bf86177fc5b4b89b6
sha256=ab4c9191645f9ffb455ae7c014d8c45339c13a1d0f6914817cfbf30a0bc56bf0
@@ -16698,6 +16918,10 @@ sha256=460d0851b743b1f144ef2a8259004d6774504c95d08e9357a96a296111496feb
md5=4c03759b76a0649a6d5108c8e172e1e4
sha256=460d0851b743b1f144ef2a8259004d6774504c95d08e9357a96a296111496feb
+[ftp://ftp.debian.org/debian/pool/main/o//offlineimap/offlineimap_4.0.14.tar.gz]
+md5=b374415d7f5d485993fa697ab9a678b4
+sha256=3b46936339fe5c2dcb8fb2f9213fa36dcddefaa1e00d1d93b5640d8cc9898ca1
+
[ftp://ftp.debian.org/debian/pool/main/o/offlineimap/offlineimap_4.0.14.tar.gz]
md5=b374415d7f5d485993fa697ab9a678b4
sha256=3b46936339fe5c2dcb8fb2f9213fa36dcddefaa1e00d1d93b5640d8cc9898ca1
@@ -16790,6 +17014,10 @@ sha256=1bb805b13ca5fe4b889f21b74feff0cdbf2a4603c9570a2b0050ae51db7c6306
md5=1b48bbb5df6b4c12ebb42b92ae1bf1f9
sha256=908a69340b020f7d865acf70724e37837016a81a0cb499fb83441759cbef7616
+[http://software-dl.ti.com/sdo/sdo_apps_public_sw/omap3530_dvsdk_combos_tspa/omap3530_dvsdk_combos_tspa-3_16-Linux-x86.bin]
+md5=8347c8980ccf6cc46039ca75e8b0f543
+sha256=f9bd3921377ab64138c7dd550d5753e3668e99de37d743cf112b88ad933d4420
+
[http://www.devzero.net/openmoko/dist/omext-0.2.tar.gz]
md5=3c1fcd85f0a0cd3ccc4d7b4f26996b47
sha256=3d3cc3e4f92f7e0b6a352c3f68a337a599a90f4e4b6e6743adc0c70b570639f5
@@ -16846,6 +17074,14 @@ sha256=1d2d7996cc94f9b87d0c51cf0e028070ac177c4123ecbfd7ac1cb8d0b7d322d1
md5=7df692e3186109cc00db6825b777201e
sha256=1d2d7996cc94f9b87d0c51cf0e028070ac177c4123ecbfd7ac1cb8d0b7d322d1
+[http://download.java.net/openjdk/jdk6/promoted/b12/openjdk-6-src-b12-28_aug_2008.tar.gz]
+md5=b53e1ef643909ce82721ee4c970d958b
+sha256=f099b3b1f3c22b8cea950403b992267ec69f43ad8a80bbcb84448b26340807ab
+
+[http://download.java.net/openjdk/jdk6/promoted/b14/openjdk-6-src-b14-25_nov_2008.tar.gz]
+md5=9f9773a822156dd3d576d83d794364ce
+sha256=1272f975052e51d3faf2d7ac13d0b8b4ac68019a688bffe03d9b684a9e3b4480
+
[http://jalimo.evolvis.org/repository/sources/openjdk-langtools-jdk7-b31.tar.bz2]
md5=670931f67b2e4ac46c6e0cd15418f2fa
sha256=f8b8820e410c137d279d14dec7e7a93217cc371acdfe1b3343b2278d1728932e
@@ -16962,6 +17198,10 @@ sha256=b839b024fd717a404711f5ec14ee9b9e412a080f23e90841cde14f20970dc5dd
md5=70f22e8adc39e07a165f75eccb7cd079
sha256=b839b024fd717a404711f5ec14ee9b9e412a080f23e90841cde14f20970dc5dd
+[http://downloads.sourceforge.net/openttd/openttd-0.4.0.1-source.tar.gz]
+md5=ddd9790c86b7ccc68f60761704cbcf81
+sha256=56e844da580761ddbb580683fc455a8d9eb3179df631568c26b7188d1ff16363
+
[http://binaries.openttd.org/releases/0.6.3/openttd-0.6.3-source.tar.bz2]
md5=d05b9ebf67c83f07e8286d0d2b1fc293
sha256=2d60e8a08768a9c81f37e699df6890c12d53f4d56b5562724c3a9ffa302c7197
@@ -17450,6 +17690,10 @@ sha256=f7f3c7bb493df1f19da32fd2001a8d52cc6ab3c7286781ebdc4d7d2367debc1d
md5=ee5ae84d115f051d87fcaaef3b4ae782
sha256=dd2fc5a745bfca5450d13d7032fdc47ab102514aae3efb3fe334a6eff87df799
+[http://kernel.org//pub/linux/kernel/v2.6/snapshots/old/patch-2.6.11-bk1.gz]
+md5=92d8225c6b75b142054ad2321a992a42
+sha256=2886eb4ceedac69f3924dbc9d979869b8a188dfb5b94a3e1068932859b4c9b3f
+
[http://kernel.org/pub/linux/kernel/v2.6/snapshots/old/patch-2.6.11-bk1.gz]
md5=92d8225c6b75b142054ad2321a992a42
sha256=2886eb4ceedac69f3924dbc9d979869b8a188dfb5b94a3e1068932859b4c9b3f
@@ -17498,6 +17742,10 @@ sha256=808ca62a66d7cfe40123301c2f51fc0dcd817ee3bb0df96d1e9e97cc3bad6a9c
md5=b9c8734471a454806c77f040fcf9869b
sha256=5ee24e1c5636bcffed155b1c01d7d09fedb135fa2458c190a0da03a82c8c2f60
+[http://kernel.org//pub/linux/kernel/v2.6/patch-2.6.22.5.bz2]
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+sha256=0f96188e8d1c6e0934f8e8dc2455e1f94a47c10cb17268364bcd77df68c83c2a
+
[http://kernel.org/pub/linux/kernel/v2.6/patch-2.6.22.5.bz2]
md5=27544a58763bbd4ce497a77658af744a
sha256=0f96188e8d1c6e0934f8e8dc2455e1f94a47c10cb17268364bcd77df68c83c2a
@@ -17674,6 +17922,10 @@ sha256=c64986ede63deda10a4b0aa5fd3fda1ae7fcd28d91ecc149fceec4ccffd9c620
md5=e192ee993b04749f82dd3e8b529d40c0
sha256=2e55067741a5f48ca6962c135fcbe6d1c1b70b95c825156c7db046277929cf28
+[http://kernel.org//pub/software/utils/pciutils/pciutils-2.1.11.tar.bz2]
+md5=2b3b2147b7bc91f362be55cb49fa1c4e
+sha256=8817295a7db11f31837c7c23f49e768131700b2b729d9fc724520d94a8b00f4b
+
[http://kernel.org/pub/software/utils/pciutils/pciutils-2.1.11.tar.bz2]
md5=2b3b2147b7bc91f362be55cb49fa1c4e
sha256=8817295a7db11f31837c7c23f49e768131700b2b729d9fc724520d94a8b00f4b
@@ -17726,14 +17978,26 @@ sha256=ef93921e8555862df4c24b1c357430ff3d5ba1d3b6b7e324862ea37b511270c0
md5=52423f0766882809c5ace9ed4ccb2131
sha256=c701207f506e3975510a9abc07eaab59f3e7e1fb13b8045ff1fff33964f4be89
+[http://kernel.org//pub/linux/utils/kernel/pcmcia/pcmciautils-010.tar.bz2]
+md5=ff3cb012fd1a8801e912054b45420ac2
+sha256=9ed7fe56197b4e1328a94842b602aef0a3a2e3380dacc95b4366661582e05661
+
[http://kernel.org/pub/linux/utils/kernel/pcmcia/pcmciautils-010.tar.bz2]
md5=ff3cb012fd1a8801e912054b45420ac2
sha256=9ed7fe56197b4e1328a94842b602aef0a3a2e3380dacc95b4366661582e05661
+[http://kernel.org//pub/linux/utils/kernel/pcmcia/pcmciautils-013.tar.bz2]
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+sha256=7c1adf1a5ebeba124cef4102cbbf9ca65b8493ad6b8fcfb48091e27e983ffc41
+
[http://kernel.org/pub/linux/utils/kernel/pcmcia/pcmciautils-013.tar.bz2]
md5=5882b7c84f095a7492b1ebe7577dce5a
sha256=7c1adf1a5ebeba124cef4102cbbf9ca65b8493ad6b8fcfb48091e27e983ffc41
+[http://kernel.org//pub/linux/utils/kernel/pcmcia/pcmciautils-014.tar.bz2]
+md5=3f07c926875f6c5dcb83240f39725177
+sha256=6bef7c05ba9fad231fe7a188043c61c116c24bab5fa79d9d72c1d8e11ff38925
+
[http://kernel.org/pub/linux/utils/kernel/pcmcia/pcmciautils-014.tar.bz2]
md5=3f07c926875f6c5dcb83240f39725177
sha256=6bef7c05ba9fad231fe7a188043c61c116c24bab5fa79d9d72c1d8e11ff38925
@@ -18378,6 +18642,10 @@ sha256=6d52c706401af197bd9d7e0187c35b4a3463ea720392ffa0c020d94899b361e5
md5=f490bca772b16472962c7b9f23b1e97d
sha256=b439e04adab9b1e66e11f59c4331680da48f1722f2123123f7c16dfbed2c38dc
+[ftp://ftp.nl.uu.net/pub/unix/ftp/proftpd/ftp/distrib/source/proftpd-1.3.2.tar.gz]
+md5=756f762883cc8eed03d99dc3b1c56a8e
+sha256=5e00c20d74bbf98fb8bcc63bd4aecfd08480a87ec731dae8955bd9fca6a01bb3
+
[http://downloads.sourceforge.net/progear/progear-ac-0.1.tar.gz]
md5=60a89c2c907fb5ff2293ce3dfbcdace6
sha256=4124e24726369b42ed0a7aff33e5c572de5e4a0f46edd4e1e81125412c4bdf24
@@ -18462,6 +18730,10 @@ sha256=1ae8b587759b33ad954e717728fab6df58bd28088d0ac8faf22e90253b774975
md5=fa121f8e5dd4b98d65096de1b6c84021
sha256=6cc4aff778275f087cfbd65d2040b1587cafc588749499a452eb496329505ab0
+[http://0pointer.de/lennart/projects/pulseaudio/pulseaudio-0.9.14.tar.gz]
+md5=0ed1115222d1d8c64cc14961cccb2eb0
+sha256=e6129f9239235981d329de40eeffa55041e6815a93aaa994d1eae242ea7446b5
+
[http://0pointer.de/lennart/projects/pulseaudio/pulseaudio-0.9.5.tar.gz]
md5=99b5d9efd4fce35cabb4ae5d0ebb230d
sha256=cd82eabcf9fa310a64b58b621730cebe5d3edae7596a9c121155db455b1e58f6
@@ -18566,6 +18838,10 @@ sha256=012882309a06987397beb3484e91467bb1be47e23850750ecaaa415be015cb79
md5=8763f3d6fd0f9738ef9854de205a126d
sha256=dad803c34e902e286a3d6fb052f48b826c62a8ad19a54ced2936da7641b62907
+[http://kernel.org//pub/linux/utils/net/NIS/OLD/pwdutils/pwdutils-2.6.tar.bz2]
+md5=8567328b1ad7609f8851eec57658f1a0
+sha256=19c6eeb42f2688464cf4fc7dadecf58faeebfa6a13f05974f6dad910f5fd6b98
+
[http://kernel.org/pub/linux/utils/net/NIS/OLD/pwdutils/pwdutils-2.6.tar.bz2]
md5=8567328b1ad7609f8851eec57658f1a0
sha256=19c6eeb42f2688464cf4fc7dadecf58faeebfa6a13f05974f6dad910f5fd6b98
@@ -19747,8 +20023,8 @@ md5=b8f0661ac765ce1a2de66ca53e37af83
sha256=a8168b8884ab40aadebba0ba696b889e25020d32a88e646d4f4bc56f2236b184
[ftp://ftp.freebsd.org/pub/FreeBSD//ports/packages/archivers/rpm2cpio-1.2_2.tbz]
-md5=63f39118ea5ef7cda84a0638002ed6d2
-sha256=27ffe0392ae193eb04786a2159c099a00fe38ccdaebcebd72afc842c528bb6d3
+md5=d4950dc6918ca79a4abab306b6188512
+sha256=5ec970d34b4e22feea0333dae3b5f5ee0e38295d89e306b4929b910f4a2aae25
[http://www.freebsd.org/cgi/cvsweb.cgi/%7Echeckout%7E/ports/archivers/rpm2cpio/files/rpm2cpio?rev=1.2]
md5=07f64fa3dae6eb8b1b578d01473a5c07
@@ -21310,14 +21586,26 @@ sha256=44357e0fae8c8f0e315bf130b4e86a4f96b91d66eeb4e473def4ce8336fff102
md5=e053094e8103165f98ddafe828f6ae4b
sha256=6169b8e91d29288e90404f01462b69e7f2afb1161aa419826fe4736c7f9eb773
+[http://kernel.org//pub/linux/utils/boot/syslinux/Old/syslinux-2.11.tar.bz2]
+md5=38a30cc790265f19f80330330ffaa527
+sha256=cdc785cb2356a7147e988e6b572d378c3762cf701c85e4c91a634545e6b9aff4
+
[http://kernel.org/pub/linux/utils/boot/syslinux/Old/syslinux-2.11.tar.bz2]
md5=38a30cc790265f19f80330330ffaa527
sha256=cdc785cb2356a7147e988e6b572d378c3762cf701c85e4c91a634545e6b9aff4
+[http://kernel.org//pub/linux/utils/boot/syslinux/Old/syslinux-3.11.tar.bz2]
+md5=513ff71287a4397d507879a1a836c2e8
+sha256=3baef57243c2475b46a913afe38bc7228ddc0297dfaa33e2213903eb9f130bd0
+
[http://kernel.org/pub/linux/utils/boot/syslinux/Old/syslinux-3.11.tar.bz2]
md5=513ff71287a4397d507879a1a836c2e8
sha256=3baef57243c2475b46a913afe38bc7228ddc0297dfaa33e2213903eb9f130bd0
+[http://kernel.org//pub/linux/utils/boot/syslinux/syslinux-3.31.tar.bz2]
+md5=5faae89d18baf92e28bc820c62270db9
+sha256=57c4ca6e7836460297edcc45148373ec131157b29c184ee011b29ec491e010f0
+
[http://kernel.org/pub/linux/utils/boot/syslinux/syslinux-3.31.tar.bz2]
md5=5faae89d18baf92e28bc820c62270db9
sha256=57c4ca6e7836460297edcc45148373ec131157b29c184ee011b29ec491e010f0
@@ -22182,14 +22470,26 @@ sha256=3ffcdc0e4597046f476ae5d4250783eb563723614bad9f1f58cc0cd9932d0b1d
md5=ee48a4ec191cb6ae61dad1bf6378cc85
sha256=31cfb81c4a4b16a6a0fe8fec04241d37c9ca98fe3bb0a434141c287fcb98e2bb
+[http://kernel.org//pub/linux/utils/kernel/hotplug/udev-092.tar.gz]
+md5=a3954a4fc25cee4e1f6df498de8f72c7
+sha256=e402e316ffddbdd5312d3a5957fccf47de7a8b62c7bb3710829a2e696e3818d1
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/udev-092.tar.gz]
md5=a3954a4fc25cee4e1f6df498de8f72c7
sha256=e402e316ffddbdd5312d3a5957fccf47de7a8b62c7bb3710829a2e696e3818d1
+[http://kernel.org//pub/linux/utils/kernel/hotplug/udev-097.tar.gz]
+md5=dfee443eed87892cc7eb50969191ff17
+sha256=1af8fedef2e76c99ab4dbf75e5ff573739dd952adc7856c5dbcebf0512e4adbe
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/udev-097.tar.gz]
md5=dfee443eed87892cc7eb50969191ff17
sha256=1af8fedef2e76c99ab4dbf75e5ff573739dd952adc7856c5dbcebf0512e4adbe
+[http://kernel.org//pub/linux/utils/kernel/hotplug/udev-100.tar.gz]
+md5=1ceb626a86630287cc28585eb16d7131
+sha256=faa9b6e000509039bbd4e1f24694adacf2cd86228d22240ec1a13acc13517aa6
+
[http://kernel.org/pub/linux/utils/kernel/hotplug/udev-100.tar.gz]
md5=1ceb626a86630287cc28585eb16d7131
sha256=faa9b6e000509039bbd4e1f24694adacf2cd86228d22240ec1a13acc13517aa6
@@ -22438,14 +22738,26 @@ sha256=c9be448984840ae960874c3c536942ba63c79a7f6a0dff3970540190b1500804
md5=997adf78b98d9d1c5db4f37ea982acff
sha256=9c239b947b9a7352d88625073ab512d601da92a00703f73dc1e1b83b78b4ca1d
+[http://kernel.org//pub/linux/utils/util-linux/util-linux-2.12o.tar.bz2]
+md5=a7c0c2729ed27beac39cf656d2097dd3
+sha256=913a83f69a370b6ee858577f8f1d218cfe899fd39d7b8a380df4971b6059e8e0
+
[http://kernel.org/pub/linux/utils/util-linux/util-linux-2.12o.tar.bz2]
md5=a7c0c2729ed27beac39cf656d2097dd3
sha256=913a83f69a370b6ee858577f8f1d218cfe899fd39d7b8a380df4971b6059e8e0
+[http://kernel.org//pub/linux/utils/util-linux/util-linux-2.12q.tar.bz2]
+md5=54320aa1abbce00c0dc030e2c3afe5d7
+sha256=2e68a53d1393e97926340d9b21e1bde488aaef05ab3e8bcab4849d1859115c6d
+
[http://kernel.org/pub/linux/utils/util-linux/util-linux-2.12q.tar.bz2]
md5=54320aa1abbce00c0dc030e2c3afe5d7
sha256=2e68a53d1393e97926340d9b21e1bde488aaef05ab3e8bcab4849d1859115c6d
+[http://kernel.org//pub/linux/utils/util-linux/util-linux-2.12r.tar.bz2]
+md5=af9d9e03038481fbf79ea3ac33f116f9
+sha256=b8e499b338ce9fbd1fb315194b26540ec823c0afc46c9e145ac7a3e38ad57e6b
+
[http://kernel.org/pub/linux/utils/util-linux/util-linux-2.12r.tar.bz2]
md5=af9d9e03038481fbf79ea3ac33f116f9
sha256=b8e499b338ce9fbd1fb315194b26540ec823c0afc46c9e145ac7a3e38ad57e6b
@@ -23038,6 +23350,10 @@ sha256=f91445e5e1a02ee16f0bc1eb31a1cdfa53c4bb1e1cb4f76fae33436d472e9345
md5=2f4c34f1e092451d3c4d2e7f8c250015
sha256=c6f692956d93765f12402a0b22617566decc52a9bb1a707b4e8d12affd1528d3
+[http://downloads.sourceforge.net/witty/wt-2.99.0.tar.gz]
+md5=3d35c181dfab7dfd3fe898738dffb421
+sha256=64e6bd25d18e838e1c60693eccbd11926c65b228d6ac69c4dafc7ebe7341dbbf
+
[http://downloads.sourceforge.net/wvware/wv-1.2.0.tar.gz]
md5=b6319d5e75611fe2210453b5feb82c0c
sha256=a76f44468e78591e6d510d326702e7c3999d2b9dd3ab8ab8c1c9811fd5b111e4
@@ -26086,14 +26402,26 @@ sha256=41f17cfab8e88824a8dc1476602a0944b9030a8f8da2538a7a6549e3534e3bdf
md5=476552b3b88b651ba161d22c1db5314d
sha256=2f596ef4c57e29708d6246949289341d9f9756d162bf49e89f0828180329aa51
+[http://kernel.org//pub/linux/utils/net/NIS/yp-tools-2.9.tar.bz2]
+md5=19de06a04129ec26773f9198e086fcd4
+sha256=65c27f5c9ef3af56b17108ecb2e89276e0fe8722152d4353bb86672c1060a718
+
[http://kernel.org/pub/linux/utils/net/NIS/yp-tools-2.9.tar.bz2]
md5=19de06a04129ec26773f9198e086fcd4
sha256=65c27f5c9ef3af56b17108ecb2e89276e0fe8722152d4353bb86672c1060a718
+[http://kernel.org//pub/linux/utils/net/NIS/ypbind-mt-1.19.tar.bz2]
+md5=4878b742d61590501230aa8baa6a4f53
+sha256=a39753a22b1f77b1fdb8163e800ee2d4f98a9e3018693d127459b509069a23f3
+
[http://kernel.org/pub/linux/utils/net/NIS/ypbind-mt-1.19.tar.bz2]
md5=4878b742d61590501230aa8baa6a4f53
sha256=a39753a22b1f77b1fdb8163e800ee2d4f98a9e3018693d127459b509069a23f3
+[http://kernel.org//pub/linux/utils/net/NIS/OLD/ypserv/ypserv-2.17.tar.bz2]
+md5=d0366ade2f46a2292de47bc1fe60e8fd
+sha256=afed29dd6f0401be0fa2a8761993dd6dd93d1ad93aa1812a87ce8aa00736e89b
+
[http://kernel.org/pub/linux/utils/net/NIS/OLD/ypserv/ypserv-2.17.tar.bz2]
md5=d0366ade2f46a2292de47bc1fe60e8fd
sha256=afed29dd6f0401be0fa2a8761993dd6dd93d1ad93aa1812a87ce8aa00736e89b
diff --git a/conf/distro/include/preferred-om-2008-versions.inc b/conf/distro/include/preferred-om-2008-versions.inc
index 538e0527d2..2c3b338cce 100644
--- a/conf/distro/include/preferred-om-2008-versions.inc
+++ b/conf/distro/include/preferred-om-2008-versions.inc
@@ -56,8 +56,8 @@ PREFERRED_VERSION_aumix ?= "2.8"
PREFERRED_VERSION_autoconf ?= "2.61"
PREFERRED_VERSION_autoconf-native ?= "2.61"
PREFERRED_VERSION_autofs ?= "4.1.4"
-PREFERRED_VERSION_automake ?= "1.10"
-PREFERRED_VERSION_automake-native ?= "1.10"
+PREFERRED_VERSION_automake ?= "1.10.2"
+PREFERRED_VERSION_automake-native ?= "1.10.2"
PREFERRED_VERSION_avahi ?= "0.6.22"
PREFERRED_VERSION_avahi-python ?= "0.6.21"
PREFERRED_VERSION_avahi-ui ?= "0.6.21"
@@ -179,8 +179,8 @@ PREFERRED_VERSION_connman ?= "0.10"
PREFERRED_VERSION_conserver ?= "8.1.14"
PREFERRED_VERSION_console-tools ?= "0.3.2"
PREFERRED_VERSION_contacts ?= "0.7"
-PREFERRED_VERSION_coreutils ?= "5.3.0"
-PREFERRED_VERSION_coreutils-native ?= "5.3.0"
+PREFERRED_VERSION_coreutils ?= "7.1"
+PREFERRED_VERSION_coreutils-native ?= "7.1"
PREFERRED_VERSION_corkscrew ?= "2.0"
PREFERRED_VERSION_corsair ?= "0.2.6"
PREFERRED_VERSION_cpio ?= "2.5"
@@ -536,7 +536,6 @@ PREFERRED_VERSION_gpe-edit ?= "0.40"
PREFERRED_VERSION_gpe-expenses ?= "0.0.6"
PREFERRED_VERSION_gpe-filemanager ?= "0.30"
PREFERRED_VERSION_gpe-fsi ?= "0.1"
-PREFERRED_VERSION_gpe-gallery ?= "0.97"
PREFERRED_VERSION_gpe-go ?= "0.05"
PREFERRED_VERSION_gpe-helpviewer ?= "1.0"
PREFERRED_VERSION_gpe-icons ?= "0.25"
@@ -589,7 +588,7 @@ PREFERRED_VERSION_gpicview ?= "0.1.5"
PREFERRED_VERSION_gpm ?= "1.20.1"
PREFERRED_VERSION_gpp ?= "2.21"
PREFERRED_VERSION_gpsbabel ?= "1.3.3"
-PREFERRED_VERSION_gpsd ?= "2.37"
+PREFERRED_VERSION_gpsd ?= "2.38"
PREFERRED_VERSION_gpsdrive ?= "2.10pre4"
PREFERRED_VERSION_gpstk ?= "1.2"
PREFERRED_VERSION_gqview ?= "2.1.1"
@@ -606,16 +605,16 @@ PREFERRED_VERSION_gsoap ?= "2.7.7"
PREFERRED_VERSION_gsoap-native ?= "2.7.7"
PREFERRED_VERSION_gsoko ?= "0.4.2-gpe6"
PREFERRED_VERSION_gspcav1 ?= "20070110"
-PREFERRED_VERSION_gst-ffmpeg ?= "0.10.2"
+PREFERRED_VERSION_gst-ffmpeg ?= "0.10.6"
PREFERRED_VERSION_gst-meta-base ?= "0.10"
PREFERRED_VERSION_gst-plugin-pulse ?= "0.9.7"
PREFERRED_VERSION_gst-plugins-bad ?= "0.10.6"
-PREFERRED_VERSION_gst-plugins-base ?= "0.10.17"
+PREFERRED_VERSION_gst-plugins-base ?= "0.10.22"
PREFERRED_VERSION_gst-plugins-farsight ?= "0.10.1"
-PREFERRED_VERSION_gst-plugins-good ?= "0.10.7"
-PREFERRED_VERSION_gst-plugins-ugly ?= "0.10.7"
+PREFERRED_VERSION_gst-plugins-good ?= "0.10.13"
+PREFERRED_VERSION_gst-plugins-ugly ?= "0.10.10"
PREFERRED_VERSION_gst-pulse = "0.9.7"
-PREFERRED_VERSION_gstreamer ?= "0.10.17"
+PREFERRED_VERSION_gstreamer ?= "0.10.22"
PREFERRED_VERSION_gthumb ?= "2.6.9"
PREFERRED_VERSION_gtk+ ?= "2.12.11"
PREFERRED_VERSION_gtk2-ssh-askpass ?= "0.3"
@@ -1928,8 +1927,8 @@ PREFERRED_VERSION_util-macros ?= "1.1.5"
PREFERRED_VERSION_util-macros-native ?= "1.1.5"
PREFERRED_VERSION_uucp ?= "1.07"
PREFERRED_VERSION_v4l2apps ?= "20020317"
-PREFERRED_VERSION_vala ?= "0.5.6"
-PREFERRED_VERSION_vala-native ?= "0.5.6"
+PREFERRED_VERSION_vala ?= "0.5.7"
+PREFERRED_VERSION_vala-native ?= "0.5.7"
PREFERRED_VERSION_vde ?= "2.0.2"
PREFERRED_VERSION_vectoroids ?= "1.1.0"
PREFERRED_VERSION_videoplayer ?= "0.1"
@@ -1949,7 +1948,7 @@ PREFERRED_VERSION_void11 ?= "0.2.0"
PREFERRED_VERSION_vorbis-tools ?= "1.0.1"
PREFERRED_VERSION_vpnc ?= "0.3.3"
PREFERRED_VERSION_vsftpd ?= "2.0.5"
-PREFERRED_VERSION_vte ?= "0.16.13"
+PREFERRED_VERSION_vte ?= "0.16.14"
PREFERRED_VERSION_vtun ?= "2.6"
PREFERRED_VERSION_w3cam ?= "0.7.2"
PREFERRED_VERSION_wakelan ?= "1.1"
diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc
index 3581a170a7..e0b8dba733 100644
--- a/conf/distro/include/sane-srcrevs.inc
+++ b/conf/distro/include/sane-srcrevs.inc
@@ -56,7 +56,7 @@ SRCREV_pn-flashrom ?= "3682"
SRCREV_pn-frameworkd ?= "b652f9cc4efbccc1df941c0d93e156631879f174"
SRCREV_pn-frameworkd-devel ?= "858c8d58d1f7e807f2c09532787c4e7b1a5daa52"
SRCREV_pn-fsod ?= "3fa5eb6f2edcf7c9f0fc2027fda47b91d9f0f136"
-SRCREV_pn-fso-abyss ?= "fc4324a328834eb55c35d1670efc53f6e8c892a1"
+SRCREV_pn-fso-abyss ?= "6ed342f833930474ac506cbaad705c0d8beaa71f"
SRCREV_pn-fso-apm ?= "eb39ce7fb81bfa64e1a9eb5f142ca3d1065be3fa"
SRCREV_pn-fso-gpsd ?= "78fe48dffb923175bde9f0aabc3500a9264a57e0"
SRCREV_pn-fso-gsm0710muxd ?= "abcbcd7cc532a8834906de3fc24c8f8fe7643cd4"
@@ -84,8 +84,8 @@ SRCREV_pn-libexalt-dbus ?= "76"
SRCREV_pn-libfakekey ?= "1455"
SRCREV_pn-libframeworkd-glib ?= "e90f7c208356b53c34e025585248ea0a7a2ea13c"
SRCREV_pn-libgdbus ?= "aeab6e3c0185b271ca343b439470491b99cc587f"
-SRCREV_pn-libgsm0710 ?= "243ef1b0db523a1ff163803e8277dc02e7c7b0b8"
-SRCREV_pn-libgsm0710mux ?= "092fcf31f56a3755d402d470d082df8f5373b2e0"
+SRCREV_pn-libgsm0710 ?= "6fdfbc2bb50c6ce49d644b92cd371a1df5942e1d"
+SRCREV_pn-libgsm0710mux ?= "a97b263f939f9a09d0a38c3346807215c72a6197"
SRCREV_pn-libgsmd ?= "4505"
SRCREV_pn-libiac ?= "1590"
SRCREV_pn-libjana ?= "713"
diff --git a/conf/machine/dm355-leopard.conf b/conf/machine/dm355-leopard.conf
new file mode 100644
index 0000000000..a9699499b7
--- /dev/null
+++ b/conf/machine/dm355-leopard.conf
@@ -0,0 +1,19 @@
+#@TYPE: Machine
+#@NAME: Leopard "beagle buddy" DM355 based IP cam board
+#@DESCRIPTION: Machine configuration for the DM355 leopard board
+
+TARGET_ARCH = "arm"
+
+PREFERRED_PROVIDER_virtual/kernel = "linux-davinci"
+PREFERRED_PROVIDERS += "virtual/${TARGET_PREFIX}depmod:module-init-tools-cross"
+
+PREFERRED_VERSION_u-boot = "1.2.0"
+UBOOT_MACHINE = "dm355_leopard_config"
+UBOOT_ENTRYPOINT = "0x80008000"
+
+SERIAL_CONSOLE ?= "115200 ttyS0"
+
+MACHINE_FEATURES = "kernel26 alsa"
+
+require conf/machine/include/tune-arm926ejs.inc
+
diff --git a/contrib/angstrom/build-feeds.sh b/contrib/angstrom/build-feeds.sh
index af66e229da..7e5f1b6f83 100755
--- a/contrib/angstrom/build-feeds.sh
+++ b/contrib/angstrom/build-feeds.sh
@@ -241,6 +241,7 @@ do
povray \
prboom \
prelink \
+ proftpd \
pushover \
python \
python-pybluez \
@@ -308,6 +309,7 @@ do
wireshark \
wpa-gui \
wt \
+ wt3 \
x11vnc \
xf86-input-evdev \
xf86-input-keyboard \
diff --git a/packages/cmake/cmake-native_2.6.3.bb b/packages/cmake/cmake-native_2.6.3.bb
new file mode 100644
index 0000000000..faf397614b
--- /dev/null
+++ b/packages/cmake/cmake-native_2.6.3.bb
@@ -0,0 +1,11 @@
+inherit native
+require cmake.inc
+
+do_stage() {
+ oe_runmake install
+ autotools_stage_all
+}
+
+do_install() {
+ :
+}
diff --git a/packages/dsplink/gstreamer-ti_svn.bb b/packages/dsplink/gstreamer-ti_svn.bb
index 824bbd21fe..bcfaa3458b 100644
--- a/packages/dsplink/gstreamer-ti_svn.bb
+++ b/packages/dsplink/gstreamer-ti_svn.bb
@@ -4,7 +4,7 @@ SRC_URI = "svn://gforge.ti.com/svn/gstreamer_ti/trunk;module=gstreamer_ti;proto=
file://gst-buffsize.diff;patch=1"
SRCREV = "127"
-PR = "r4"
+PR = "r5"
# Again, no '.' in PWD allowed :(
PV = "0+svnr${SRCREV}"
diff --git a/packages/llvm/llvm-native_2.5.bb b/packages/llvm/llvm-native_2.5.bb
new file mode 100644
index 0000000000..010f49ab32
--- /dev/null
+++ b/packages/llvm/llvm-native_2.5.bb
@@ -0,0 +1,15 @@
+require llvm.inc
+
+SRC_URI = "http://llvm.org/releases/2.5/llvm-${PV}.tar.gz"
+
+inherit native
+
+S = "${WORKDIR}/llvm-${PV}"
+
+do_stage() {
+ install -m 755 ${S}/Release/bin/* ${STAGING_BINDIR_NATIVE}/
+}
+
+do_rm_work() {
+ :
+}
diff --git a/packages/proftpd/files/make.patch b/packages/proftpd/files/make.patch
new file mode 100644
index 0000000000..66ebf2ce89
--- /dev/null
+++ b/packages/proftpd/files/make.patch
@@ -0,0 +1,51 @@
+Index: proftpd-1.3.2/Makefile.in
+===================================================================
+--- proftpd-1.3.2.orig/Makefile.in
++++ proftpd-1.3.2/Makefile.in
+@@ -76,7 +76,6 @@ check: proftpd$(EXEEXT)
+ $(DESTDIR)$(localedir) $(DESTDIR)$(includedir) $(DESTDIR)$(includedir)/proftpd $(DESTDIR)$(libdir) $(DESTDIR)$(pkgconfigdir) $(DESTDIR)$(libdir)/proftpd $(DESTDIR)$(libexecdir) $(DESTDIR)$(localstatedir) $(DESTDIR)$(sysconfdir) $(DESTDIR)$(rundir) $(DESTDIR)$(bindir) $(DESTDIR)$(sbindir) $(DESTDIR)$(mandir) $(DESTDIR)$(mandir)/man1 $(DESTDIR)$(mandir)/man5 $(DESTDIR)$(mandir)/man8:
+ @if [ ! -d $@ ]; then \
+ mkdir -p $@; \
+- chown $(INSTALL_USER):$(INSTALL_GROUP) $@; \
+ chmod 0755 $@; \
+ fi
+
+@@ -86,7 +85,6 @@ install-proftpd: proftpd $(DESTDIR)$(inc
+ rm -f $(DESTDIR)$(sbindir)/in.proftpd ; \
+ fi
+ ln -s proftpd $(DESTDIR)$(sbindir)/in.proftpd
+- -chown -h $(INSTALL_USER):$(INSTALL_GROUP) $(DESTDIR)$(sbindir)/in.proftpd
+
+ install-libs: $(DESTDIR)$(libdir)/proftpd
+ cd lib/ && $(MAKE) install
+@@ -121,11 +119,11 @@ install-utils: $(DESTDIR)$(sbindir) $(DE
+ $(INSTALL_SBIN) ftpshut $(DESTDIR)$(sbindir)/ftpshut
+ $(INSTALL_BIN) ftptop $(DESTDIR)$(bindir)/ftptop
+ $(INSTALL_BIN) ftpwho $(DESTDIR)$(bindir)/ftpwho
+- $(INSTALL) -o $(INSTALL_USER) -g $(INSTALL_GROUP) -m 0755 src/prxs $(DESTDIR)$(bindir)/prxs
++ $(INSTALL) -m 0755 src/prxs $(DESTDIR)$(bindir)/prxs
+
+ install-conf: $(DESTDIR)$(sysconfdir)
+ if [ ! -f $(DESTDIR)$(sysconfdir)/proftpd.conf ] ; then \
+- $(INSTALL) -o $(INSTALL_USER) -g $(INSTALL_GROUP) -m 0644 \
++ $(INSTALL) -m 0644 \
+ $(top_srcdir)/sample-configurations/basic.conf \
+ $(DESTDIR)$(sysconfdir)/proftpd.conf ; \
+ fi
+Index: proftpd-1.3.2/Make.rules.in
+===================================================================
+--- proftpd-1.3.2.orig/Make.rules.in
++++ proftpd-1.3.2/Make.rules.in
+@@ -29,9 +29,9 @@ UTILS_LIBS=@UTILS_LIBS@ @LIBS@
+ INSTALL=@INSTALL@
+ INSTALL_USER=@install_user@
+ INSTALL_GROUP=@install_group@
+-INSTALL_BIN=$(INSTALL) @INSTALL_STRIP@ -o $(INSTALL_USER) -g $(INSTALL_GROUP) -m 0755
+-INSTALL_SBIN=$(INSTALL) @INSTALL_STRIP@ -o $(INSTALL_USER) -g $(INSTALL_GROUP) -m 0755
+-INSTALL_MAN=$(INSTALL) -o $(INSTALL_USER) -g $(INSTALL_GROUP) -m 0644
++INSTALL_BIN=$(INSTALL) @INSTALL_STRIP@ -m 0755
++INSTALL_SBIN=$(INSTALL) @INSTALL_STRIP@ -m 0755
++INSTALL_MAN=$(INSTALL) -m 0644
+
+ RM=rm -f
+ SHELL=/bin/sh
diff --git a/packages/proftpd/proftpd_1.3.2.bb b/packages/proftpd/proftpd_1.3.2.bb
new file mode 100644
index 0000000000..1a9736dbf3
--- /dev/null
+++ b/packages/proftpd/proftpd_1.3.2.bb
@@ -0,0 +1,36 @@
+DESCRIPTION = "Secure ftp daemon"
+SECTION = "console/network"
+LICENSE = "GPL"
+PR = "r2"
+
+SRC_URI = "ftp://ftp.nl.uu.net/pub/unix/ftp/proftpd/ftp/distrib/source/${PN}-${PV}.tar.gz \
+ file://make.patch;patch=1 \
+ "
+
+
+EXTRA_OECONF = "ac_cv_func_setpgrp_void=yes ac_cv_func_setgrent_void=yes"
+LDFLAGS += "-Llib"
+PARALLEL_MAKE = ""
+
+do_configure () {
+ ./configure \
+ --disable-auth-pam \
+ --build=${BUILD_SYS} \
+ --host=${HOST_SYS} \
+ --target=${TARGET_SYS} \
+ --prefix=/usr \
+ --sysconfdir=/etc \
+ --sharedstatedir=/com \
+ --localstatedir=/var \
+ ${EXTRA_OECONF} \
+ $@;
+}
+
+do_install () {
+ oe_runmake DESTDIR=${D} install
+}
+
+pkg_postinst () {
+ # more chown's might be needed
+ chown root:root /usr/sbin/proftpd
+}
diff --git a/packages/python/python-coherence_0.6.0.bb b/packages/python/python-coherence_0.6.0.bb
deleted file mode 100644
index bf9d964f99..0000000000
--- a/packages/python/python-coherence_0.6.0.bb
+++ /dev/null
@@ -1,15 +0,0 @@
-DESCRIPTION = "Coherence is a DLNA/UPnP mediaserver + backends"
-SECTION = "devel/python"
-LICENSE = "MIT"
-HOMEPAGE = "http://coherence.beebits.net/wiki"
-PR = "r5"
-
-inherit setuptools
-
-SRC_URI = "http://coherence.beebits.net/download/Coherence-${PV}.tar.gz"
-S = "${WORKDIR}/Coherence-${PV}"
-
-FILES_${PN} += "${datadir}"
-RDEPENDS_${PN} += "python-gst python-dbus python-configobj python-twisted python-twisted-core python-misc python-zopeinterface zope python-modules"
-
-
diff --git a/packages/python/python-coherence_0.6.2.bb b/packages/python/python-coherence_0.6.2.bb
index 7d25f0868e..54eed59574 100644
--- a/packages/python/python-coherence_0.6.2.bb
+++ b/packages/python/python-coherence_0.6.2.bb
@@ -2,7 +2,7 @@ DESCRIPTION = "Coherence is a DLNA/UPnP mediaserver + backends"
SECTION = "devel/python"
LICENSE = "MIT"
HOMEPAGE = "http://coherence.beebits.net/wiki"
-PR = "r0"
+PR = "r1"
inherit setuptools
@@ -12,6 +12,9 @@ S = "${WORKDIR}/Coherence-${PV}"
FILES_${PN} += "${datadir}"
DEPENDS = "libxml2 libxml2-native"
-RDEPENDS_${PN} += "python-gst python-dbus python-configobj python-twisted python-twisted-core python-misc python-zopeinterface zope python-modules"
+RDEPENDS_${PN} += "python-twisted-pair python-divmodepsilon python-nevow python-gst python-dbus \
+ python-configobj python-twisted python-twisted-core python-twisted-protocols python-misc \
+ python-zopeinterface python-modules python-pygobject python-gdata \
+ python-divmodaxiom"
diff --git a/packages/thttpd/thttpd_2.25b.bb b/packages/thttpd/thttpd_2.25b.bb
index 6beb01f3d6..c1ec7e73b9 100644
--- a/packages/thttpd/thttpd_2.25b.bb
+++ b/packages/thttpd/thttpd_2.25b.bb
@@ -1,7 +1,7 @@
DESCRIPTION = "A simple, small, portable, fast, and secure HTTP server."
LICENSE = "BSD"
HOMEPAGE = "http://www.acme.com/software/thttpd/"
-PR ="r6"
+PR ="r7"
SRC_URI = "http://www.acme.com/software/thttpd/thttpd-2.25b.tar.gz \
file://install.patch;patch=1 \
@@ -10,6 +10,8 @@ SRC_URI = "http://www.acme.com/software/thttpd/thttpd-2.25b.tar.gz \
file://htpasswd_shared.diff;patch=1"
S = "${WORKDIR}/thttpd-${PV}"
+PARALLEL_MAKE = ""
+
INITSCRIPT_NAME = "thttpd"
INITSCRIPT_PARAMS = "defaults"
diff --git a/packages/u-boot/u-boot-1.2.0/dm355-leopard.diff b/packages/u-boot/u-boot-1.2.0/dm355-leopard.diff
new file mode 100644
index 0000000000..b614522f42
--- /dev/null
+++ b/packages/u-boot/u-boot-1.2.0/dm355-leopard.diff
@@ -0,0 +1,48455 @@
+ Makefile | 36
+ board/davinci/Makefile | 47
+ board/davinci/config.mk | 27
+ board/davinci/davinci.c | 417 +
+ board/davinci/dm644x_emac.c | 491 +
+ board/davinci/dm644x_emac.h | 290
+ board/davinci/flash.c | 686 +
+ board/davinci/flash_params.h | 319
+ board/davinci/lowlevel_init.S | 764 ++
+ board/davinci/nand.c | 111
+ board/davinci/soc.h | 339
+ board/davinci/timer.c | 73
+ board/davinci/timer.h | 51
+ board/davinci/types.h | 46
+ board/davinci/u-boot.lds | 52
+ board/dm355_evm/Makefile | 47
+ board/dm355_evm/config.mk | 25
+ board/dm355_evm/dm355_evm.c | 598 +
+ board/dm355_evm/flash.c | 758 ++
+ board/dm355_evm/flash_params.h | 319
+ board/dm355_evm/lowlevel_init.S | 766 ++
+ board/dm355_evm/nand.c | 805 ++
+ board/dm355_evm/timer.c | 72
+ board/dm355_evm/timer.h | 51
+ board/dm355_evm/types.h | 46
+ board/dm355_evm/u-boot.lds | 52
+ board/dm355_ipnc/Makefile | 47
+ board/dm355_ipnc/config.mk | 25
+ board/dm355_ipnc/dm355_ipnc.c | 671 +
+ board/dm355_ipnc/flash.c | 758 ++
+ board/dm355_ipnc/flash_params.h | 319
+ board/dm355_ipnc/lowlevel_init.S | 766 ++
+ board/dm355_ipnc/nand.c | 830 ++
+ board/dm355_ipnc/timer.c | 72
+ board/dm355_ipnc/timer.h | 51
+ board/dm355_ipnc/types.h | 46
+ board/dm355_ipnc/u-boot.lds | 52
+ board/dm355_leopard/Makefile | 47
+ board/dm355_leopard/config.mk | 25
+ board/dm355_leopard/dm355_leopard.c | 671 +
+ board/dm355_leopard/flash.c | 758 ++
+ board/dm355_leopard/flash_params.h | 319
+ board/dm355_leopard/lowlevel_init.S | 766 ++
+ board/dm355_leopard/nand.c | 830 ++
+ board/dm355_leopard/timer.c | 72
+ board/dm355_leopard/timer.h | 51
+ board/dm355_leopard/types.h | 46
+ board/dm355_leopard/u-boot.lds | 52
+ board/dm700/Makefile | 47
+ board/dm700/config.mk | 26
+ board/dm700/davinci_hd.c | 203
+ board/dm700/dm646x_emac.c | 506 +
+ board/dm700/dm646x_emac.h | 321
+ board/dm700/flash.c | 686 +
+ board/dm700/flash_params.h | 319
+ board/dm700/lowlevel_init.S | 725 ++
+ board/dm700/nand.c | 111
+ board/dm700/soc.h | 349 +
+ board/dm700/timer.c | 73
+ board/dm700/timer.h | 51
+ board/dm700/types.h | 46
+ board/dm700/u-boot.lds | 52
+ common/cmd_nand.c | 11
+ common/env_nand.c | 14
+ cpu/arm926ejs/config.mk | 4
+ cpu/arm926ejs/interrupts.c | 148
+ cpu/arm926ejs/interrupts.c.orig | 191
+ doc/README.SBC8560 | 57
+ doc/README.sbc8560 | 53
+ drivers/Makefile | 4
+ drivers/davinci_i2c.c | 296
+ drivers/davinci_i2c.h | 87
+ drivers/dm9000.c | 370 +
+ drivers/dm9000.h | 181
+ drivers/dm9000x.c | 124
+ drivers/nand/nand_base.c | 1404 ++--
+ drivers/nand/nand_bbt.c | 17
+ drivers/nand/nand_ids.c | 44
+ drivers/nand/nand_util.c | 3
+ examples/hello_world.bin |binary
+ examples/hello_world.srec | 36
+ include/asm-arm/arch-arm926ejs/emif_defs.h | 59
+ include/asm-arm/arch-arm926ejs/nand_defs.h | 92
+ include/asm-arm/arch-arm926ejs/types.h | 31
+ include/asm-arm/arch/emif_defs.h | 59
+ include/asm-arm/arch/nand_defs.h | 92
+ include/asm-arm/arch/sizes.h | 51
+ include/asm-arm/arch/types.h | 31
+ include/asm-arm/proc/domain.h | 50
+ include/asm-arm/proc/processor.h | 74
+ include/asm-arm/proc/ptrace.h | 109
+ include/asm-arm/proc/system.h | 199
+ include/asm/arch-arm1136/bits.h | 48
+ include/asm/arch-arm1136/clocks.h | 112
+ include/asm/arch-arm1136/i2c.h | 107
+ include/asm/arch-arm1136/mem.h | 156
+ include/asm/arch-arm1136/mux.h | 158
+ include/asm/arch-arm1136/omap2420.h | 221
+ include/asm/arch-arm1136/sizes.h | 49
+ include/asm/arch-arm1136/sys_info.h | 82
+ include/asm/arch-arm1136/sys_proto.h | 54
+ include/asm/arch-arm720t/hardware.h | 43
+ include/asm/arch-arm720t/netarm_dma_module.h | 182
+ include/asm/arch-arm720t/netarm_eni_module.h | 121
+ include/asm/arch-arm720t/netarm_eth_module.h | 160
+ include/asm/arch-arm720t/netarm_gen_module.h | 186
+ include/asm/arch-arm720t/netarm_mem_module.h | 184
+ include/asm/arch-arm720t/netarm_registers.h | 96
+ include/asm/arch-arm720t/netarm_ser_module.h | 347
+ include/asm/arch-arm720t/s3c4510b.h | 272
+ include/asm/arch-arm925t/sizes.h | 50
+ include/asm/arch-arm926ejs/emif_defs.h | 59
+ include/asm/arch-arm926ejs/nand_defs.h | 92
+ include/asm/arch-arm926ejs/sizes.h | 51
+ include/asm/arch-arm926ejs/types.h | 31
+ include/asm/arch-at91rm9200/AT91RM9200.h | 762 ++
+ include/asm/arch-at91rm9200/hardware.h | 77
+ include/asm/arch-imx/imx-regs.h | 577 +
+ include/asm/arch-ixp/ixp425.h | 543 +
+ include/asm/arch-ixp/ixp425pci.h | 312
+ include/asm/arch-ks8695/platform.h | 306
+ include/asm/arch-omap/sizes.h | 52
+ include/asm/arch-pxa/bitfield.h | 112
+ include/asm/arch-pxa/hardware.h | 158
+ include/asm/arch-pxa/mmc.h | 200
+ include/asm/arch-pxa/pxa-regs.h | 2399 ++++++
+ include/asm/arch-s3c24x0/memory.h | 162
+ include/asm/arch-s3c44b0/hardware.h | 281
+ include/asm/arch-sa1100/bitfield.h | 112
+ include/asm/arch/emif_defs.h | 59
+ include/asm/arch/nand_defs.h | 92
+ include/asm/arch/sizes.h | 51
+ include/asm/arch/types.h | 31
+ include/asm/atomic.h | 113
+ include/asm/bitops.h | 144
+ include/asm/byteorder.h | 32
+ include/asm/errno.h | 138
+ include/asm/global_data.h | 66
+ include/asm/hardware.h | 18
+ include/asm/io.h | 307
+ include/asm/mach-types.h | 9415 +++++++++++++++++++++++++++
+ include/asm/memory.h | 137
+ include/asm/posix_types.h | 79
+ include/asm/proc-armv/domain.h | 50
+ include/asm/proc-armv/processor.h | 74
+ include/asm/proc-armv/ptrace.h | 109
+ include/asm/proc-armv/system.h | 199
+ include/asm/proc/domain.h | 50
+ include/asm/proc/processor.h | 74
+ include/asm/proc/ptrace.h | 109
+ include/asm/proc/system.h | 199
+ include/asm/processor.h | 134
+ include/asm/ptrace.h | 33
+ include/asm/setup.h | 269
+ include/asm/sizes.h | 52
+ include/asm/string.h | 47
+ include/asm/types.h | 50
+ include/asm/u-boot-arm.h | 62
+ include/asm/u-boot.h | 60
+ include/config.h | 2
+ include/config.mk | 3
+ include/configs/SBC8560.h | 410 -
+ include/configs/davinci.h | 222
+ include/configs/dm355_evm.h | 227
+ include/configs/dm355_ipnc.h | 234
+ include/configs/dm355_leopard.h | 234
+ include/configs/dm700.h | 204
+ include/configs/omap2420h4.h | 2
+ include/configs/sbc8560.h | 408 +
+ include/flash.h | 2
+ include/linux/mtd/nand.h | 190
+ include/linux/mtd/nand_ids.h | 1
+ include/version_autogenerated.h | 1
+ lib_arm/board.c | 8
+ tools/crc32.c | 198
+ tools/environment.c | 214
+ 176 files changed, 44713 insertions(+), 982 deletions(-)
+diff -Nurd u-boot-1.2.0/Makefile u-boot-1.2.0-leopard/Makefile
+--- u-boot-1.2.0/Makefile 2007-01-06 20:13:11.000000000 -0300
++++ u-boot-1.2.0-leopard/Makefile 2009-03-10 02:16:35.000000000 -0300
+@@ -125,7 +125,7 @@
+ CROSS_COMPILE = powerpc-linux-
+ endif
+ ifeq ($(ARCH),arm)
+-CROSS_COMPILE = arm-linux-
++CROSS_COMPILE = arm_v5t_le-
+ endif
+ ifeq ($(ARCH),i386)
+ ifeq ($(HOSTARCH),i386)
+@@ -233,10 +233,12 @@
+ __OBJS := $(subst $(obj),,$(OBJS))
+ __LIBS := $(subst $(obj),,$(LIBS))
+
++U-BOOT = u-boot-1.2.0-$(BOARD).bin
++
+ #########################################################################
+ #########################################################################
+
+-ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
++ALL = $(obj)u-boot.srec $(obj)$(U-BOOT) $(obj)System.map $(U_BOOT_NAND)
+
+ all: $(ALL)
+
+@@ -249,7 +251,10 @@
+ $(obj)u-boot.bin: $(obj)u-boot
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+-$(obj)u-boot.img: $(obj)u-boot.bin
++$(obj)$(U-BOOT): $(obj)u-boot
++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
++
++$(obj)u-boot.img: $(obj)$(U-BOOT)
+ ./tools/mkimage -A $(ARCH) -T firmware -C none \
+ -a $(TEXT_BASE) -e 0 \
+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
+@@ -277,8 +282,8 @@
+ $(NAND_SPL): version
+ $(MAKE) -C nand_spl/board/$(BOARDDIR) all
+
+-$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin
+- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
++$(U_BOOT_NAND): $(NAND_SPL) $(obj)$(U-BOOT)
++ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)$(U-BOOT) > $(obj)u-boot-nand.bin
+
+ version:
+ @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
+@@ -320,7 +325,7 @@
+
+ #########################################################################
+ else
+-all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
++all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)$(U-BOOT) \
+ $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
+ $(SUBDIRS) version gdbtools updater env depend \
+ dep tags ctags etags $(obj)System.map:
+@@ -336,7 +341,7 @@
+ #########################################################################
+
+ unconfig:
+- @rm -f $(obj)include/config.h $(obj)include/config.mk \
++ @rm -rf $(obj)include/config.h $(obj)include/config.mk \
+ $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp
+
+ #========================================================================
+@@ -1858,6 +1863,21 @@
+ mx1fs2_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
+
++davinci_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm926ejs davinci
++
++dm700_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm700
++
++dm355_evm_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355_evm
++
++dm355_ipnc_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355_ipnc
++
++dm355_leopard_config: unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355_leopard
++
+ netstar_32_config \
+ netstar_config: unconfig
+ @mkdir -p $(obj)include
+@@ -2333,7 +2353,7 @@
+ rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
+ rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
+ rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
+- rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
++ rm -rf $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+ [ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
+
+ ifeq ($(OBJTREE),$(SRCTREE))
+diff -Nurd u-boot-1.2.0/board/davinci/Makefile u-boot-1.2.0-leopard/board/davinci/Makefile
+--- u-boot-1.2.0/board/davinci/Makefile 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/Makefile 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := davinci.o flash.o timer.o dm644x_emac.o nand.o
++SOBJS := lowlevel_init.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -Nurd u-boot-1.2.0/board/davinci/config.mk u-boot-1.2.0-leopard/board/davinci/config.mk
+--- u-boot-1.2.0/board/davinci/config.mk 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/config.mk 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,27 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++#
++# (C) Copyright 2003
++# Texas Instruments, <www.ti.com>
++# Swaminathan <swami.iyer@ti.com>
++#
++# Davinci EVM board (ARM925EJS) cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# Davinci EVM has 1 bank of 256 MB DDR RAM
++# Physical Address:
++# 8000'0000 to 9000'0000
++#
++#
++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
++# (mem base + reserved)
++#
++# we load ourself to 8100 '0000
++#
++#
++
++#Provide a atleast 16MB spacing between us and the Linux Kernel image
++TEXT_BASE = 0x81080000
++BOARDLIBS = drivers/nand/libnand.a
+diff -Nurd u-boot-1.2.0/board/davinci/davinci.c u-boot-1.2.0-leopard/board/davinci/davinci.c
+--- u-boot-1.2.0/board/davinci/davinci.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/davinci.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,417 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++
++#include <common.h>
++#include <i2c.h>
++
++#if 0
++void flash__init (void);
++void ether__init (void);
++#endif
++#define PLL1_PLLM *(volatile unsigned int *)0x01c40910
++#define PLL2_PLLM *(volatile unsigned int *)0x01c40D10
++#define PLL2_DIV2 *(volatile unsigned char *)0x01c40D1C
++
++void davinci_psc_all_enable(void);
++
++/*******************************************
++ Routine: delay
++ Description: Delay function
++*******************************************/
++static inline void delay (unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*******************************************
++ Routine: board_init
++ Description: Board Initialization routine
++*******************************************/
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* arch number of DaVinci DVDP-Board */
++ gd->bd->bi_arch_number = 901;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
++ /* Configure MUX settings */
++
++ /* Power on required peripherals */
++ davinci_psc_all_enable();
++#if 0
++ /* this speeds up your boot a quite a bit. However to make it
++ * work, you need make sure your kernel startup flush bug is fixed.
++ * ... rkw ...
++ */
++ icache_enable ();
++#endif
++ inittimer ();
++
++ return 0;
++}
++
++/* PSC Domains */
++#define LPSC_VPSSMSTR 0 // VPSS Master LPSC
++#define LPSC_VPSSSLV 1 // VPSS Slave LPSC
++#define LPSC_TPCC 2 // TPCC LPSC
++#define LPSC_TPTC0 3 // TPTC0 LPSC
++#define LPSC_TPTC1 4 // TPTC1 LPSC
++#define LPSC_EMAC 5 // EMAC LPSC
++#define LPSC_EMAC_WRAPPER 6 // EMAC WRAPPER LPSC
++#define LPSC_MDIO 7 // MDIO LPSC
++#define LPSC_IEEE1394 8 // IEEE1394 LPSC
++#define LPSC_USB 9 // USB LPSC
++#define LPSC_ATA 10 // ATA LPSC
++#define LPSC_VLYNQ 11 // VLYNQ LPSC
++#define LPSC_UHPI 12 // UHPI LPSC
++#define LPSC_DDR_EMIF 13 // DDR_EMIF LPSC
++#define LPSC_AEMIF 14 // AEMIF LPSC
++#define LPSC_MMC_SD 15 // MMC_SD LPSC
++#define LPSC_MEMSTICK 16 // MEMSTICK LPSC
++#define LPSC_McBSP 17 // McBSP LPSC
++#define LPSC_I2C 18 // I2C LPSC
++#define LPSC_UART0 19 // UART0 LPSC
++#define LPSC_UART1 20 // UART1 LPSC
++#define LPSC_UART2 21 // UART2 LPSC
++#define LPSC_SPI 22 // SPI LPSC
++#define LPSC_PWM0 23 // PWM0 LPSC
++#define LPSC_PWM1 24 // PWM1 LPSC
++#define LPSC_PWM2 25 // PWM2 LPSC
++#define LPSC_GPIO 26 // GPIO LPSC
++#define LPSC_TIMER0 27 // TIMER0 LPSC
++#define LPSC_TIMER1 28 // TIMER1 LPSC
++#define LPSC_TIMER2 29 // TIMER2 LPSC
++#define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM LPSC
++#define LPSC_ARM 31 // ARM LPSC
++#define LPSC_SCR2 32 // SCR2 LPSC
++#define LPSC_SCR3 33 // SCR3 LPSC
++#define LPSC_SCR4 34 // SCR4 LPSC
++#define LPSC_CROSSBAR 35 // CROSSBAR LPSC
++#define LPSC_CFG27 36 // CFG27 LPSC
++#define LPSC_CFG3 37 // CFG3 LPSC
++#define LPSC_CFG5 38 // CFG5 LPSC
++#define LPSC_GEM 39 // GEM LPSC
++#define LPSC_IMCOP 40 // IMCOP LPSC
++
++#define CHP_SHRTSW *( volatile unsigned int* )( 0x01C40038 )
++#define GBLCTL *( volatile unsigned int* )( 0x01C41010 )
++#define EPCPR *( volatile unsigned int* )( 0x01C41070 )
++#define EPCCR *( volatile unsigned int* )( 0x01C41078 )
++#define PTCMD *( volatile unsigned int* )( 0x01C41120 )
++#define PTSTAT *( volatile unsigned int* )( 0x01C41128 )
++#define PDSTAT *( volatile unsigned int* )( 0x01C41200 )
++#define PDSTAT1 *( volatile unsigned int* )( 0x01C41204 )
++#define PDCTL *( volatile unsigned int* )( 0x01C41300 )
++#define PDCTL1 *( volatile unsigned int* )( 0x01C41304 )
++#define VBPR *( volatile unsigned int* )( 0x20000020 )
++
++/**************************************
++ Routine: board_setup_psc_on
++ Description: Enable a PSC domain
++**************************************/
++void board_setup_psc_on( unsigned int domain, unsigned int id )
++{
++ volatile unsigned int* mdstat = ( unsigned int* )( 0x01C41800 + 4 * id );
++ volatile unsigned int* mdctl = ( unsigned int* )( 0x01C41A00 + 4 * id );
++
++ *mdctl |= 0x00000003; // Set PowerDomain to turn on
++
++ if ( ( PDSTAT & 0x00000001 ) == 0 )
++ {
++ PDCTL1 |= 0x1;
++ PTCMD = ( 1 << domain );
++ while ( ( ( ( EPCPR >> domain ) & 1 ) == 0 ) );
++
++ PDCTL1 |= 0x100 ;
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++ else
++ {
++ PTCMD = ( 1<<domain );
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++
++ while( ! ( ( *mdstat & 0x0000001F ) == 0x3 ) );
++}
++
++/**************************************
++ Routine: davinci_psc_all_enable
++ Description: Enable all PSC domains
++**************************************/
++void davinci_psc_all_enable(void)
++{
++#define PSC_ADDR 0x01C41000
++#define PTCMD (PSC_ADDR+0x120)
++#define PTSTAT (PSC_ADDR+0x128)
++
++ unsigned int alwaysOnPdNum = 0, dspPdNum = 1, i;
++ int waiting;
++ unsigned int state;
++
++ /* This function turns on all clocks in the ALWAYSON and DSP Power
++ * Domains. Note this function assumes that the Power Domains are
++ * already on.
++ */
++#if 0
++ /* Write ENABLE (0x3) to all 41 MDCTL[i].NEXT bit fields. */
++ for( i = 0; i < 41; i++){
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) =
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) | 0x3;
++ }
++
++ /* For special workaround: Set MDCTL[i].EMURSTIE to 0x1 for all of the
++ * following Modules. VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) | 0x203;*/
++#endif
++
++ /* For special workaround: Clear MDCTL[i].EMURSTIE to 0x0 for all of the following Modules.
++ * VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) & 0x003;*/
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x003;
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x003;
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) & 0x003;*/
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x003;
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) & 0x003;*/
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x003;
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*18) = *(unsigned int*) (PSC_ADDR+0xA00+4*18) | 0x003;
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*28) = *(unsigned int*) (PSC_ADDR+0xA00+4*28) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) & 0x003;*/
++
++ /* Set PTCMD.GO0 to 0x1 to initiate the state transtion for Modules in
++ * the ALWAYSON Power Domain
++ */
++ *(volatile unsigned int*) PTCMD = (1<<alwaysOnPdNum);
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! (((*(volatile unsigned int*) PTSTAT >> alwaysOnPdNum) & 0x00000001) == 0));
++
++ /* DO GEM AND IMCOP INITIALIZATION, ONLY IF DSP POWER DOMAIN IS OFF... */
++ /* NOTE: this is a precise and refined sequence - use extreme care if modifying! */
++ if ((PDSTAT1 & 0x1F) == 0) {
++
++ /* set PSC FORCE mode; may not be necessary, added per reference code */
++ GBLCTL = GBLCTL | 0x01;
++
++ /* set DSP power domain next state to ON */
++ PDCTL1 = PDCTL1 | 0x01;
++
++ /* ensure external power indicator is cleared */
++ PDCTL1 = PDCTL1 & 0xFFFFFEFF;
++
++ /* enable DSP module */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) =
++ (*(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) & 0xFFFFFFE0) | 0x3;
++
++ /* hold DSP in reset on next power ON */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) =
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) & 0xFFFFFEFF;
++
++ /* set IMCOP to enable state */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) =
++ (*(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) & 0xFFFFFFE0) | 0x3;
++
++ /* hold IMCOP in reset on next power ON */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) =
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) & 0xFFFFFEFF;
++
++ /* start power state transitions for DSP power domain */
++ *(volatile unsigned int*) PTCMD = (1<<dspPdNum);
++
++ /* wait for external power control pending to assert */
++ for (i = 0, waiting = 1; (i < 100) && waiting; i++) {
++ if (((EPCPR >> dspPdNum) & 0x00000001) == 1) {
++ waiting = 0;
++ }
++ }
++
++ /* close rail shorting switch */
++ CHP_SHRTSW = 0x1;
++
++ /* set external power good indicator */
++ PDCTL1 = PDCTL1 | 0x0100;
++
++ /* clear external power control pending register bit */
++ EPCCR = (1 << dspPdNum);
++
++ /* wait for DSP domain transitions to complete */
++ for (i = 0, waiting = 1; (i < 100) && waiting; i++) {
++ state = *(volatile unsigned int*) PTSTAT;
++ if (((state >> dspPdNum) & 0x00000001) == 0) {
++ waiting = 0;
++ }
++ }
++
++ /* turn off PSC FORCE mode */
++ GBLCTL = GBLCTL & 0xFFFFFFFE;
++
++ } /* END GEM AND IMCOP INITIALIZATION */
++
++ /* Bringup UART out of reset here since NS16650 code that we are using from uBoot
++ * will not do it
++ */
++#define UARTPWREMU_MGMT 0x01c20030
++ *(volatile unsigned int*) UARTPWREMU_MGMT = 0x0000E003;
++
++ /* Enable GIO3.3V cells used for EMAC */
++#define VDD3P3V_PWDN 0x01c40048
++ *(volatile unsigned int*) VDD3P3V_PWDN = 0;
++
++#define PINMUX0 0x01C40000
++#define PINMUX4 0x01C40004
++
++ /* Enable UART0 MUX lines */
++ *(volatile unsigned int *)PINMUX4 |= 1;
++ /* Enable EMAC and AEMIF pins */
++#if (CONFIG_COMMANDS & CFG_CMD_NAND)
++ *(volatile unsigned int*) PINMUX0 = 0x80000000;
++#else
++ *(volatile unsigned int*) PINMUX0 = 0x80000C1F;
++#endif
++
++ /* Enable I2C pin Mux */
++ *(volatile unsigned int *)PINMUX4 |= (1 << 7);
++
++ /* Set the Bus Priority Register to appropriate value */
++ VBPR = 0x20;
++}
++
++/******************************
++ Routine: misc_init_r
++ Description: Misc. init
++******************************/
++int misc_init_r (void)
++{
++ char temp[20];
++ char rtcdata[10] = { 2, 1, 0, 0, 0, 0, 0, 0, 0, 0};
++ char emac_read_addr [10] = { 0x7f, 0 }, i= 0;
++ int clk = 0;
++
++ clk = ((PLL2_PLLM + 1) * 27) / (PLL2_DIV2 + 1);
++
++ printf ("ARM Clock :- %dMHz\n", ((((PLL1_PLLM + 1) * 27 ) / 2)) );
++ printf ("DDR Clock :- %dMHz\n", (clk/2));
++
++ i2c_write (0x50, 0x00, 1, emac_read_addr, 2);
++ i2c_read (0x50, 0x00, 1, emac_read_addr, 6);
++ temp[0] = (emac_read_addr[0] & 0xF0) >> 4;
++ temp[1] = (emac_read_addr[0] & 0x0F);
++ temp[2] = ':';
++ temp[3] = (emac_read_addr[1] & 0xF0) >> 4;
++ temp[4] = (emac_read_addr[1] & 0x0F);
++ temp[5] = ':';
++ temp[6] = (emac_read_addr[2] & 0xF0) >> 4;
++ temp[7] = (emac_read_addr[2] & 0x0F);
++ temp[8] = ':';
++ temp[9] = (emac_read_addr[3] & 0xF0) >> 4;
++ temp[10]= (emac_read_addr[3] & 0x0F);
++ temp[11]= ':';
++ temp[12]= (emac_read_addr[4] & 0xF0) >> 4;
++ temp[13]= (emac_read_addr[4] & 0x0F);
++ temp[14]= ':';
++ temp[15]= (emac_read_addr[5] & 0xF0) >> 4;
++ temp[16]= (emac_read_addr[5] & 0x0F);
++
++ for (i = 0; i < 17; i++)
++ {
++ if (temp[i] == ':')
++ continue;
++ else if (temp[i] >= 0 && temp[i] <= 9)
++ temp[i] = temp[i] + 48;
++ else
++ temp[i] = temp[i] + 87;
++ }
++
++ temp [17] = 0;
++ if ((emac_read_addr [0] != 0xFF) ||
++ (emac_read_addr [1] != 0xFF) ||
++ (emac_read_addr [2] != 0xFF) ||
++ (emac_read_addr [3] != 0xFF) ||
++ (emac_read_addr [4] != 0xFF) ||
++ (emac_read_addr [5] != 0xFF))
++ {
++ setenv ("ethaddr", temp);
++ }
++
++ i2c_read (0x39, 0x00, 1, &i, 1);
++
++ if ( !getenv("videostd") )
++ setenv ("videostd", ((i & 0x80)?"pal":"ntsc"));
++
++ i2c_write (0x23, 0x00, 1, rtcdata, 2);
++ i2c_read (0x23, 0x00, 1, rtcdata, 1);
++
++ if (rtcdata[0] == 10)
++ printf ("MSP430 Firmware supports AM/PM Feature\n");
++ else
++ printf ("MSP430 Firmware does not support AM/PM Feature\n");
++
++ return (0);
++}
++
++/******************************
++ Routine: dram_init
++ Description: Memory Info
++******************************/
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
+diff -Nurd u-boot-1.2.0/board/davinci/dm644x_emac.c u-boot-1.2.0-leopard/board/davinci/dm644x_emac.c
+--- u-boot-1.2.0/board/davinci/dm644x_emac.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/dm644x_emac.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,491 @@
++/*
++ * dm644x_emac.c
++ *
++ * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
++ *
++ * Copyright (C) 2005 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++
++ * Modifications:
++ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
++ * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
++ *
++ */
++
++#include <common.h>
++#include <command.h>
++#include <net.h>
++#include "dm644x_emac.h"
++
++#ifdef CONFIG_DRIVER_TI_EMAC
++
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
++
++unsigned int emac_dbg = 0;
++#define debug_emac(fmt,args...) if (emac_dbg) printf (fmt ,##args)
++
++/* EMAC internal functions - called when eth_xxx functions are invoked by the kernel */
++static int emac_hw_init (void);
++static int emac_open (void);
++static int emac_close (void);
++static int emac_send_packet (volatile void *packet, int length);
++static int emac_rcv_packet (void);
++
++/* The driver can be entered at any of the following entry points */
++extern int eth_init (bd_t * bd);
++extern void eth_halt (void);
++extern int eth_rx (void);
++extern int eth_send (volatile void *packet, int length);
++
++int eth_hw_init (void)
++{
++ return emac_hw_init();
++}
++
++int eth_init (bd_t * bd)
++{
++ return emac_open ();
++}
++
++void eth_halt ()
++{
++ emac_close ();
++}
++
++int eth_send (volatile void *packet, int length)
++{
++ return emac_send_packet (packet, length);
++}
++
++int eth_rx ()
++{
++ return emac_rcv_packet ();
++}
++
++
++static char emac_mac_addr[] = { 0x00, 0x00, 0x5b, 0xee, 0xde, 0xad };
++
++/*
++ * This function must be called before emac_open() if you want to override
++ * the default mac address.
++ */
++
++void emac_set_mac_addr (const char *addr)
++{
++ int i;
++
++ for (i = 0; i < sizeof (emac_mac_addr); i++) {
++ emac_mac_addr[i] = addr[i];
++ }
++}
++
++/***************************
++ * EMAC Global variables
++ ***************************/
++
++/* EMAC Addresses */
++static volatile emac_regs* adap_emac = (emac_regs *) EMAC_BASE_ADDR;
++static volatile ewrap_regs* adap_ewrap = (ewrap_regs *) EMAC_WRAPPER_BASE_ADDR;
++static volatile mdio_regs* adap_mdio = (mdio_regs *) EMAC_MDIO_BASE_ADDR;
++
++/* EMAC descriptors */
++static volatile emac_desc *emac_rx_desc = (emac_desc *) (EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
++static volatile emac_desc *emac_tx_desc = (emac_desc *) (EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
++static volatile emac_desc *emac_rx_active_head = 0;
++static volatile emac_desc *emac_rx_active_tail = 0;
++static int emac_rx_queue_active = 0;
++
++/* EMAC link status */
++static int emac_link_status = 0; /* 0 = link down, 1 = link up */
++
++/* Receive packet buffers */
++static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
++
++/* This function initializes the emac hardware */
++static int emac_hw_init (void)
++{
++ /* Enabling power and reset from outside the module is required */
++ return (0);
++}
++
++/* Read a PHY register via MDIO inteface */
++static int mdio_read(int phy_addr, int reg_num)
++{
++ adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
++ ((reg_num & 0x1F) << 21) |
++ ((phy_addr & 0x1F) << 16);
++
++ /* Wait for command to complete */
++ while ((adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) != 0);
++
++ return (adap_mdio->USERACCESS0 & 0xFFFF);
++}
++
++/* Write to a PHY register via MDIO inteface */
++void mdio_write(int phy_addr, int reg_num, unsigned int data)
++{
++ /* Wait for User access register to be ready */
++ while ((adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) != 0);
++
++ adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
++ ((reg_num & 0x1F) << 21) |
++ ((phy_addr & 0x1F) << 16) |
++ (data & 0xFFFF);
++}
++
++
++/* Get PHY link state - this function accepts a PHY mask for the caller to
++ * find out if any of the passed PHY addresses is connected
++ */
++int mdio_get_link_state(unsigned int phy_mask)
++{
++ unsigned int act_phy, phy_addr = 0, link_state = 0;
++ unsigned int config;
++
++ act_phy = (adap_mdio->ALIVE & phy_mask);
++
++ if (act_phy)
++ {
++ /* find the phy number */
++ while(act_phy)
++ {
++ while(!(act_phy & 0x1))
++ {
++ phy_addr++;
++ act_phy >>= 1;
++ }
++ /* Read the status register from PHY */
++ link_state = ((mdio_read(phy_addr, MII_STATUS_REG) & 0x4) >> 2);
++ if(link_state == 1)
++ {
++ /* The link can break off anytime, hence adding the fix for boosting the PHY signal
++ * strength here so that everytime the link is found, this can be done and ensured
++ * that we dont miss it
++ */
++ config = mdio_read(phy_addr, MII_DIGITAL_CONFIG_REG);
++ config |= 0x800;
++ mdio_write(phy_addr, MII_DIGITAL_CONFIG_REG, config);
++ /* Read back to verify */
++ config = mdio_read(phy_addr, MII_DIGITAL_CONFIG_REG);
++
++ break;
++ }
++ else
++ {
++ /* If no link, go to next phy. */
++ act_phy >>= 1;
++ phy_addr++;
++ }
++ }
++ }
++ return link_state;
++}
++
++/*
++ * The kernel calls this function when someone wants to use the device,
++ * typically 'ifconfig ethX up'.
++ */
++static int emac_open (void)
++{
++ volatile unsigned int *addr;
++ unsigned int clkdiv, cnt;
++ volatile emac_desc *rx_desc;
++
++ debug_emac("+ emac_open\n");
++
++ /* Reset EMAC module and disable interrupts in wrapper */
++ adap_emac->SOFTRESET = 1;
++ while (adap_emac->SOFTRESET != 0);
++ adap_ewrap->EWCTL = 0;
++ for (cnt=0; cnt < 5; cnt++) {
++ clkdiv = adap_ewrap->EWCTL;
++ }
++
++ rx_desc = emac_rx_desc;
++
++ adap_emac->TXCONTROL = 0x1;
++ adap_emac->RXCONTROL = 0x1;
++
++ /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
++ /* Using channel 0 only - other channels are disabled */
++ adap_emac->MACINDEX = 0;
++ adap_emac->MACADDRHI = (emac_mac_addr[3] << 24) | (emac_mac_addr[2] << 16) |
++ (emac_mac_addr[1] << 8) | (emac_mac_addr[0]);
++ adap_emac->MACADDRLO = ((emac_mac_addr[5] << 8) | emac_mac_addr[4]);
++
++ adap_emac->MACHASH1 = 0;
++ adap_emac->MACHASH2 = 0;
++
++ /* Set source MAC address - REQUIRED */
++ adap_emac->MACSRCADDRHI = (emac_mac_addr[3] << 24) | (emac_mac_addr[2] << 16) |
++ (emac_mac_addr[1] << 8) | (emac_mac_addr[0]);
++ adap_emac->MACSRCADDRLO = ((emac_mac_addr[4] << 8) | emac_mac_addr[5]);
++
++ /* Set DMA 8 TX / 8 RX Head pointers to 0 */
++ addr = &adap_emac->TX0HDP;
++ for( cnt=0; cnt<16; cnt++ )
++ *addr++ = 0;
++ addr = &adap_emac->RX0HDP;
++ for( cnt=0; cnt<16; cnt++ )
++ *addr++ = 0;
++
++ /* Clear Statistics (do this before setting MacControl register) */
++ addr = &adap_emac->RXGOODFRAMES;
++ for( cnt=0; cnt < EMAC_NUM_STATS; cnt++ )
++ *addr++ = 0;
++
++ /* No multicast addressing */
++ adap_emac->MACHASH1 = 0 ;
++ adap_emac->MACHASH2 = 0 ;
++
++ /* Create RX queue and set receive process in place */
++ emac_rx_active_head = emac_rx_desc;
++ for (cnt=0; cnt < EMAC_MAX_RX_BUFFERS; cnt++)
++ {
++ rx_desc->next = (unsigned int) (rx_desc + 1);
++ rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
++ rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
++ rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
++ ++rx_desc;
++ }
++
++ /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */
++ --rx_desc;
++ rx_desc->next = 0;
++ emac_rx_active_tail = rx_desc;
++ emac_rx_queue_active = 1;
++
++ /* Enable TX/RX */
++ adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE;
++ adap_emac->RXBUFFEROFFSET = 0;
++
++ /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */
++ adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN ;
++
++ /* Enable ch 0 only */
++ adap_emac->RXUNICASTSET = 0x1;
++
++ /* Enable MII interface and Full duplex mode */
++ adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE);
++
++ /* Init MDIO & get link state */
++ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
++ adap_mdio->CONTROL = ((clkdiv & 0xFF) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT);
++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK);
++
++ /* Start receive process */
++ adap_emac->RX0HDP = (unsigned int) emac_rx_desc;
++
++ debug_emac("- emac_open\n");
++
++ return (1);
++}
++
++/* EMAC Channel Teardown */
++void emac_ch_teardown(int ch)
++{
++ volatile unsigned int dly = 0xFF;
++ volatile unsigned int cnt;
++
++ debug_emac("+ emac_ch_teardown\n");
++
++ if (ch == EMAC_CH_TX)
++ {
++ /* Init TX channel teardown */
++ adap_emac->TXTEARDOWN = 1;
++ for( cnt = 0; cnt != 0xFFFFFFFC; cnt = adap_emac->TX0CP){
++ /* Wait here for Tx teardown completion interrupt to occur
++ * Note: A task delay can be called here to pend rather than
++ * occupying CPU cycles - anyway it has been found that teardown
++ * takes very few cpu cycles and does not affect functionality */
++ --dly;
++ udelay(1);
++ if (dly == 0) break;
++ }
++ adap_emac->TX0CP = cnt;
++ adap_emac->TX0HDP = 0;
++ }
++ else
++ {
++ /* Init RX channel teardown */
++ adap_emac->RXTEARDOWN = 1;
++ for( cnt = 0; cnt != 0xFFFFFFFC; cnt = adap_emac->RX0CP){
++ /* Wait here for Tx teardown completion interrupt to occur
++ * Note: A task delay can be called here to pend rather than
++ * occupying CPU cycles - anyway it has been found that teardown
++ * takes very few cpu cycles and does not affect functionality */
++ --dly;
++ udelay(1);
++ if (dly == 0) break;
++ }
++ adap_emac->RX0CP = cnt;
++ adap_emac->RX0HDP = 0;
++ }
++
++ debug_emac("- emac_ch_teardown\n");
++}
++
++/*
++ * This is called by the kernel in response to 'ifconfig ethX down'. It
++ * is responsible for cleaning up everything that the open routine
++ * does, and maybe putting the card into a powerdown state.
++ */
++static int emac_close (void)
++{
++ debug_emac("+ emac_close\n");
++
++ emac_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
++ emac_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
++
++ /* Reset EMAC module and disable interrupts in wrapper */
++ adap_emac->SOFTRESET = 1;
++ adap_ewrap->EWCTL = 0;
++
++ debug_emac("- emac_close\n");
++ return (1);
++}
++
++static int tx_send_loop = 0;
++
++/*
++ * This function sends a single packet on the network and returns
++ * positive number (number of bytes transmitted) or negative for error
++ */
++static int emac_send_packet (volatile void *packet, int length)
++{
++ int ret_status = -1;
++ tx_send_loop = 0;
++
++ /* Return error if no link */
++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK);
++ if (emac_link_status == 0)
++ {
++ printf("WARN: emac_send_packet: No link\n");
++ return (ret_status);
++ }
++
++ /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
++ if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
++ {
++ length = EMAC_MIN_ETHERNET_PKT_SIZE;
++ }
++
++ /* Populate the TX descriptor */
++ emac_tx_desc->next = 0;
++ emac_tx_desc->buffer = (unsigned char *)packet;
++ emac_tx_desc->buff_off_len = (length & 0xFFFF);
++ emac_tx_desc->pkt_flag_len = ((length & 0xFFFF) |
++ EMAC_CPPI_SOP_BIT |
++ EMAC_CPPI_OWNERSHIP_BIT |
++ EMAC_CPPI_EOP_BIT);
++ /* Send the packet */
++ adap_emac->TX0HDP = (unsigned int) emac_tx_desc;
++
++ /* Wait for packet to complete or link down */
++ while (1)
++ {
++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK);
++ if (emac_link_status == 0)
++ {
++ emac_ch_teardown(EMAC_CH_TX);
++ return (ret_status);
++ }
++ if (adap_emac->TXINTSTATRAW & 0x1)
++ {
++ ret_status = length;
++ break;
++ }
++ ++tx_send_loop;
++ }
++
++ return (ret_status);
++
++}
++
++/*
++ * This function handles receipt of a packet from the network
++ */
++static int emac_rcv_packet (void)
++{
++ volatile emac_desc *rx_curr_desc;
++ volatile emac_desc *curr_desc;
++ volatile emac_desc *tail_desc;
++ unsigned int status, ret= -1;
++
++ rx_curr_desc = emac_rx_active_head;
++ status = rx_curr_desc->pkt_flag_len;
++ if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0))
++ {
++ if (status & EMAC_CPPI_RX_ERROR_FRAME) {
++ /* Error in packet - discard it and requeue desc */
++ printf("WARN: emac_rcv_pkt: Error in packet\n");
++ }
++ else {
++ NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xFFFF));
++ ret = rx_curr_desc->buff_off_len & 0xFFFF;
++ }
++
++ /* Ack received packet descriptor */
++ adap_emac->RX0CP = (unsigned int) rx_curr_desc;
++ curr_desc = rx_curr_desc;
++ emac_rx_active_head = rx_curr_desc->next;
++
++ if (status & EMAC_CPPI_EOQ_BIT) {
++ if (emac_rx_active_head) {
++ adap_emac->RX0HDP = (unsigned int) emac_rx_active_head;
++ } else {
++ emac_rx_queue_active = 0;
++ printf("INFO:emac_rcv_packet: RX Queue not active\n");
++ }
++ }
++
++ /* Recycle RX descriptor */
++ rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
++ rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
++ rx_curr_desc->next = 0;
++
++ if (emac_rx_active_head == 0) {
++ printf("INFO: emac_rcv_pkt: active queue head = 0\n");
++ emac_rx_active_head = curr_desc;
++ emac_rx_active_tail = curr_desc;
++ if (emac_rx_queue_active != 0) {
++ adap_emac->RX0HDP = (unsigned int) emac_rx_active_head;
++ printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
++ emac_rx_queue_active = 1;
++ }
++ } else {
++
++ tail_desc = emac_rx_active_tail;
++ emac_rx_active_tail = curr_desc;
++ tail_desc->next = curr_desc;
++ status = tail_desc->pkt_flag_len;
++ if (status & EMAC_CPPI_EOQ_BIT) {
++ adap_emac->RX0HDP = (unsigned int) curr_desc;
++ status &= ~EMAC_CPPI_EOQ_BIT;
++ tail_desc->pkt_flag_len = status;
++ }
++ }
++ return ret;
++ }
++ return (0);
++}
++
++#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
++
++#endif /* CONFIG_DRIVER_TI_EMAC */
+diff -Nurd u-boot-1.2.0/board/davinci/dm644x_emac.h u-boot-1.2.0-leopard/board/davinci/dm644x_emac.h
+--- u-boot-1.2.0/board/davinci/dm644x_emac.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/dm644x_emac.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,290 @@
++/*
++ * dm644x_emac.h
++ *
++ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
++ *
++ * Copyright (C) 2005 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++
++ * Modifications:
++ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
++ *
++ */
++
++#ifndef _DM644X_EMAC_H_
++#define _DM644X_EMAC_H_
++
++/***********************************************
++ ********** Configurable items *****************
++ ***********************************************/
++
++/* Addresses of EMAC module in DaVinci */
++#define EMAC_BASE_ADDR (0x01C80000)
++#define EMAC_WRAPPER_BASE_ADDR (0x01C81000)
++#define EMAC_WRAPPER_RAM_ADDR (0x01C82000)
++#define EMAC_MDIO_BASE_ADDR (0x01C84000)
++
++/* MDIO module input frequency */
++#define EMAC_MDIO_BUS_FREQ 76500000 /* PLL/6 - 76.5 MHz */
++/* MDIO clock output frequency */
++#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
++
++/* PHY mask - set only those phy number bits where phy is/can be connected */
++#define EMAC_MDIO_PHY_MASK 0xFFFFFFFF
++
++/* Ethernet Min/Max packet size */
++#define EMAC_MIN_ETHERNET_PKT_SIZE 60
++#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
++#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
++
++/* Number of RX packet buffers
++ * NOTE: Only 1 buffer supported as of now
++ */
++#define EMAC_MAX_RX_BUFFERS 10
++
++/***********************************************
++ ******** Internally used macros ***************
++ ***********************************************/
++
++#define EMAC_CH_TX 1
++#define EMAC_CH_RX 0
++
++/* Each descriptor occupies 4, lets start RX desc's at 0 and
++ * reserve space for 64 descriptors max
++ */
++#define EMAC_RX_DESC_BASE 0x0
++#define EMAC_TX_DESC_BASE 0x1000
++
++/* EMAC Teardown value */
++#define EMAC_TEARDOWN_VALUE 0xFFFFFFFC
++
++/* MII Status Register */
++#define MII_STATUS_REG 1
++
++/* Intel LXT971 Digtal Config Register */
++#define MII_DIGITAL_CONFIG_REG 26
++
++/* Number of statistics registers */
++#define EMAC_NUM_STATS 36
++
++/* EMAC Descriptor */
++typedef volatile struct _emac_desc
++{
++ unsigned int next; /* Pointer to next descriptor in chain */
++ unsigned char *buffer; /* Pointer to data buffer */
++ unsigned int buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
++ unsigned int pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
++} emac_desc;
++
++/* CPPI bit positions */
++#define EMAC_CPPI_SOP_BIT (0x80000000) /*(1 << 31)*/
++#define EMAC_CPPI_EOP_BIT (0x40000000) /*(1 << 30*/
++#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) /*(1 << 29)*/
++#define EMAC_CPPI_EOQ_BIT (0x10000000) /*(1 << 28)*/
++#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) /*(1 << 27)*/
++#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) /*(1 << 26)*/
++
++#define EMAC_CPPI_RX_ERROR_FRAME (0x03FC0000)
++
++#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
++#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
++
++#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
++#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
++
++
++#define MDIO_CONTROL_ENABLE (0x40000000)
++#define MDIO_CONTROL_FAULT (0x80000)
++#define MDIO_USERACCESS0_GO (0x80000000)
++#define MDIO_USERACCESS0_WRITE_READ (0x0)
++#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
++
++
++
++/* EMAC Register overlay */
++
++/* Ethernet MAC Register Overlay Structure */
++typedef volatile struct {
++ unsigned int TXIDVER;
++ unsigned int TXCONTROL;
++ unsigned int TXTEARDOWN;
++ unsigned char RSVD0[4];
++ unsigned int RXIDVER;
++ unsigned int RXCONTROL;
++ unsigned int RXTEARDOWN;
++ unsigned char RSVD1[100];
++ unsigned int TXINTSTATRAW;
++ unsigned int TXINTSTATMASKED;
++ unsigned int TXINTMASKSET;
++ unsigned int TXINTMASKCLEAR;
++ unsigned int MACINVECTOR;
++ unsigned char RSVD2[12];
++ unsigned int RXINTSTATRAW;
++ unsigned int RXINTSTATMASKED;
++ unsigned int RXINTMASKSET;
++ unsigned int RXINTMASKCLEAR;
++ unsigned int MACINTSTATRAW;
++ unsigned int MACINTSTATMASKED;
++ unsigned int MACINTMASKSET;
++ unsigned int MACINTMASKCLEAR;
++ unsigned char RSVD3[64];
++ unsigned int RXMBPENABLE;
++ unsigned int RXUNICASTSET;
++ unsigned int RXUNICASTCLEAR;
++ unsigned int RXMAXLEN;
++ unsigned int RXBUFFEROFFSET;
++ unsigned int RXFILTERLOWTHRESH;
++ unsigned char RSVD4[8];
++ unsigned int RX0FLOWTHRESH;
++ unsigned int RX1FLOWTHRESH;
++ unsigned int RX2FLOWTHRESH;
++ unsigned int RX3FLOWTHRESH;
++ unsigned int RX4FLOWTHRESH;
++ unsigned int RX5FLOWTHRESH;
++ unsigned int RX6FLOWTHRESH;
++ unsigned int RX7FLOWTHRESH;
++ unsigned int RX0FREEBUFFER;
++ unsigned int RX1FREEBUFFER;
++ unsigned int RX2FREEBUFFER;
++ unsigned int RX3FREEBUFFER;
++ unsigned int RX4FREEBUFFER;
++ unsigned int RX5FREEBUFFER;
++ unsigned int RX6FREEBUFFER;
++ unsigned int RX7FREEBUFFER;
++ unsigned int MACCONTROL;
++ unsigned int MACSTATUS;
++ unsigned int EMCONTROL;
++ unsigned int FIFOCONTROL;
++ unsigned int MACCONFIG;
++ unsigned int SOFTRESET;
++ unsigned char RSVD5[88];
++ unsigned int MACSRCADDRLO;
++ unsigned int MACSRCADDRHI;
++ unsigned int MACHASH1;
++ unsigned int MACHASH2;
++ unsigned int BOFFTEST;
++ unsigned int TPACETEST;
++ unsigned int RXPAUSE;
++ unsigned int TXPAUSE;
++ unsigned char RSVD6[16];
++ unsigned int RXGOODFRAMES;
++ unsigned int RXBCASTFRAMES;
++ unsigned int RXMCASTFRAMES;
++ unsigned int RXPAUSEFRAMES;
++ unsigned int RXCRCERRORS;
++ unsigned int RXALIGNCODEERRORS;
++ unsigned int RXOVERSIZED;
++ unsigned int RXJABBER;
++ unsigned int RXUNDERSIZED;
++ unsigned int RXFRAGMENTS;
++ unsigned int RXFILTERED;
++ unsigned int RXQOSFILTERED;
++ unsigned int RXOCTETS;
++ unsigned int TXGOODFRAMES;
++ unsigned int TXBCASTFRAMES;
++ unsigned int TXMCASTFRAMES;
++ unsigned int TXPAUSEFRAMES;
++ unsigned int TXDEFERRED;
++ unsigned int TXCOLLISION;
++ unsigned int TXSINGLECOLL;
++ unsigned int TXMULTICOLL;
++ unsigned int TXEXCESSIVECOLL;
++ unsigned int TXLATECOLL;
++ unsigned int TXUNDERRUN;
++ unsigned int TXCARRIERSENSE;
++ unsigned int TXOCTETS;
++ unsigned int FRAME64;
++ unsigned int FRAME65T127;
++ unsigned int FRAME128T255;
++ unsigned int FRAME256T511;
++ unsigned int FRAME512T1023;
++ unsigned int FRAME1024TUP;
++ unsigned int NETOCTETS;
++ unsigned int RXSOFOVERRUNS;
++ unsigned int RXMOFOVERRUNS;
++ unsigned int RXDMAOVERRUNS;
++ unsigned char RSVD7[624];
++ unsigned int MACADDRLO;
++ unsigned int MACADDRHI;
++ unsigned int MACINDEX;
++ unsigned char RSVD8[244];
++ unsigned int TX0HDP;
++ unsigned int TX1HDP;
++ unsigned int TX2HDP;
++ unsigned int TX3HDP;
++ unsigned int TX4HDP;
++ unsigned int TX5HDP;
++ unsigned int TX6HDP;
++ unsigned int TX7HDP;
++ unsigned int RX0HDP;
++ unsigned int RX1HDP;
++ unsigned int RX2HDP;
++ unsigned int RX3HDP;
++ unsigned int RX4HDP;
++ unsigned int RX5HDP;
++ unsigned int RX6HDP;
++ unsigned int RX7HDP;
++ unsigned int TX0CP;
++ unsigned int TX1CP;
++ unsigned int TX2CP;
++ unsigned int TX3CP;
++ unsigned int TX4CP;
++ unsigned int TX5CP;
++ unsigned int TX6CP;
++ unsigned int TX7CP;
++ unsigned int RX0CP;
++ unsigned int RX1CP;
++ unsigned int RX2CP;
++ unsigned int RX3CP;
++ unsigned int RX4CP;
++ unsigned int RX5CP;
++ unsigned int RX6CP;
++ unsigned int RX7CP;
++} emac_regs;
++
++/* EMAC Wrapper Register Overlay */
++typedef volatile struct {
++ volatile unsigned char RSVD0[4100];
++ volatile unsigned int EWCTL;
++ volatile unsigned int EWINTTCNT;
++} ewrap_regs;
++
++
++/* EMAC MDIO Register Overlay */
++typedef volatile struct {
++ volatile unsigned int VERSION;
++ volatile unsigned int CONTROL;
++ volatile unsigned int ALIVE;
++ volatile unsigned int LINK;
++ volatile unsigned int LINKINTRAW;
++ volatile unsigned int LINKINTMASKED;
++ volatile unsigned char RSVD0[8];
++ volatile unsigned int USERINTRAW;
++ volatile unsigned int USERINTMASKED;
++ volatile unsigned int USERINTMASKSET;
++ volatile unsigned int USERINTMASKCLEAR;
++ volatile unsigned char RSVD1[80];
++ volatile unsigned int USERACCESS0;
++ volatile unsigned int USERPHYSEL0;
++ volatile unsigned int USERACCESS1;
++ volatile unsigned int USERPHYSEL1;
++} mdio_regs;
++
++
++#endif /* _DM644X_EMAC_H_ */
+diff -Nurd u-boot-1.2.0/board/davinci/flash.c u-boot-1.2.0-leopard/board/davinci/flash.c
+--- u-boot-1.2.0/board/davinci/flash.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/flash.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,686 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * (C) Copyright 2003
++ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include "types.h"
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++#if defined (CFG_DAVINCI)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++ #define SWAP(x) __swab16(x)
++#endif
++
++#if defined (CONFIG_TOP860)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++#endif
++
++#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0aaa
++ #define FLASH_CYCLE2 0x0555
++ #define FLASH_ID1 0
++ #define FLASH_ID2 2
++ #define FLASH_ID3 0x1c
++ #define FLASH_ID4 0x1E
++#endif
++
++#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0E
++ #define FLASH_ID4 0x0F
++#endif
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size(FPWV *addr, flash_info_t *info);
++static void flash_reset(flash_info_t *info);
++static int write_word(flash_info_t *info, FPWV *dest, FPW data);
++static flash_info_t *flash_get_info(ulong base);
++void inline spin_wheel (void);
++
++/*-----------------------------------------------------------------------
++ * flash_init()
++ *
++ * sets up flash_info and returns size of FLASH (bytes)
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i = 0;
++ extern void flash_preinit(void);
++ extern void flash_afterinit(uint, ulong, ulong);
++ ulong flashbase = CFG_FLASH_BASE;
++
++ /*flash_preinit();*/
++
++ /* There is only ONE FLASH device */
++ memset(&flash_info[i], 0, sizeof(flash_info_t));
++ flash_info[i].size =
++ flash_get_size((FPW *)flashbase, &flash_info[i]);
++ size += flash_info[i].size;
++
++#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
++ /* monitor protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_MONITOR_BASE,
++ CFG_MONITOR_BASE+monitor_flash_len-1,
++ flash_get_info(CFG_MONITOR_BASE));
++#endif
++
++#ifdef CFG_ENV_IS_IN_FLASH
++ /* ENV protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
++ flash_get_info(CFG_ENV_ADDR));
++#endif
++
++
++ /*flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);*/
++ return size ? size : 1;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_reset(flash_info_t *info)
++{
++ FPWV *base = (FPWV *)(info->start[0]);
++
++ /* Put FLASH back in read mode */
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *base = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++
++void flash_reset_sector(flash_info_t *info, ULONG addr)
++{
++ // Reset Flash to be in Read Array Mode
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *(FPWV *)addr = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *(FPWV *)addr = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size &&
++ info->start[0] <= base && base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++ uchar *boottype;
++ uchar *bootletter;
++ uchar *fmt;
++ uchar botbootletter[] = "B";
++ uchar topbootletter[] = "T";
++ uchar botboottype[] = "bottom boot sector";
++ uchar topboottype[] = "top boot sector";
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_AMD: printf ("MY AMD "); break;
++#if 0
++ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
++ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
++ case FLASH_MAN_SST: printf ("SST "); break;
++ case FLASH_MAN_STM: printf ("STM "); break;
++#endif
++ case FLASH_MAN_INTEL: printf ("INTEL "); break;
++ default: printf ("Unknown Vendor "); break;
++ }
++
++ /* check for top or bottom boot, if it applies */
++ if (info->flash_id & FLASH_BTYPE) {
++ boottype = botboottype;
++ bootletter = botbootletter;
++ }
++ else {
++ boottype = topboottype;
++ bootletter = topbootletter;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160T:
++ case FLASH_AM160B:
++ fmt = "29LV160%s (16 Mbit, %s)\n";
++ break;
++ case FLASH_AMLV640U:
++ fmt = "29LV640M (64 Mbit)\n";
++ break;
++ case FLASH_AMDLV065D:
++ fmt = "29LV065D (64 Mbit)\n";
++ break;
++ case FLASH_AMLV256U:
++ fmt = "29LV256M (256 Mbit)\n";
++ break;
++ case FLASH_28F128P30T:
++ fmt = "28F128P30T\n";
++ break;
++ default:
++ fmt = "Unknown Chip Type\n";
++ break;
++ }
++
++ printf (fmt, bootletter, boottype);
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20,
++ info->sector_count);
++
++ printf (" Sector Start Addresses:");
++
++ for (i=0; i<info->sector_count; ++i) {
++ ulong size;
++ int erased;
++ ulong *flash = (unsigned long *) info->start[i];
++
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++
++ /*
++ * Check if whole sector is erased
++ */
++ size =
++ (i != (info->sector_count - 1)) ?
++ (info->start[i + 1] - info->start[i]) >> 2 :
++ (info->start[0] + info->size - info->start[i]) >> 2;
++
++ for (
++ flash = (unsigned long *) info->start[i], erased = 1;
++ (flash != (unsigned long *) info->start[i] + size) && erased;
++ flash++
++ )
++ erased = *flash == ~0x0UL;
++
++ printf (" %08lX %s %s",
++ info->start[i],
++ erased ? "E": " ",
++ info->protect[i] ? "(RO)" : " ");
++ }
++
++ printf ("\n");
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++
++ulong flash_get_size (FPWV *addr, flash_info_t *info)
++{
++ int i;
++
++ /* Write auto select command: read Manufacturer ID */
++ /* Write auto select command sequence and test FLASH answer */
++ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
++
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++ switch (addr[FLASH_ID1] & 0xff) {
++
++ case (uchar)AMD_MANUFACT:
++ printf ("MY AMD ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_AMD;
++ break;
++
++ case (uchar)INTEL_MANUFACT:
++ printf ("INTEL ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++ printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++ break;
++ }
++
++ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
++ if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
++
++ case (FPW)AMD_ID_LV160B:
++ info->flash_id += FLASH_AM160B;
++ info->sector_count = 35;
++ info->size = 0x00200000;
++ info->start[0] = (ulong)addr;
++ info->start[1] = (ulong)addr + 0x4000;
++ info->start[2] = (ulong)addr + 0x6000;
++ info->start[3] = (ulong)addr + 0x8000;
++ for (i = 4; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * (i-3);
++ }
++ break;
++
++ case (FPW)AMD_ID_LV065D:
++ info->flash_id += FLASH_AMDLV065D;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++
++ case (FPW)AMD_ID_MIRROR:
++ /* MIRROR BIT FLASH, read more ID bytes */
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
++ {
++ info->flash_id += FLASH_AMLV640U;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
++ {
++ /* attention: only the first 16 MB will be used in u-boot */
++ info->flash_id += FLASH_AMLV256U;
++ info->sector_count = 256;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ case (FPW)INTEL_ID_28F128P30T:
++ /* Intel StrataFlash 28F128P30T */
++ info->flash_id += FLASH_28F128P30T;
++ info->sector_count = 131;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ if (i < 127)
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ else
++ info->start[i] = (ulong)addr + 0xfe0000 + 0x8000 * (i-127);
++ }
++ break;
++
++ /* fall thru to here ! */
++ default:
++ printf ("unknown AMD device=%x %x %x",
++ (FPW)addr[FLASH_ID2],
++ (FPW)addr[FLASH_ID3],
++ (FPW)addr[FLASH_ID4]);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0x800000;
++ break;
++ }
++
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ return (info->size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ FPWV *addr;
++ int flag, prot, sect;
++ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
++ ulong start, now, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160B:
++ case FLASH_AMLV640U:
++ break;
++ case FLASH_AMLV256U:
++ break;
++ case FLASH_28F128P30T:
++ break;
++ case FLASH_UNKNOWN:
++ default:
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect=s_first; sect<=s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
++
++ if (info->protect[sect] != 0) /*bmw esteem192e ispan mx1fs2 RPXlite tqm8540
++ protected, skip it */
++ continue;
++
++ printf ("Erasing sector %2d ... ", sect);
++ addr = (FPWV *)(info->start[sect]);
++
++ if (intel) {
++ *addr = (FPW)0x00600060; /* unlock block setup */
++ *addr = (FPW)0x00d000d0; /* unlock block confirm */
++ *addr = (FPW)0x00500050; /* clear status register */
++ *addr = (FPW)0x00200020; /* erase setup */
++ *addr = (FPW)0x00D000D0; /* erase confirm */
++ while((*addr & 0x80) == 0);
++ printf("done.\n");
++ }
++ else {
++ /* must be AMD style if not Intel */
++ FPWV *base; /* first address in bank */
++
++ base = (FPWV *)(info->start[0]);
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ *addr = (FPW)0x00300030; /* erase sector */
++ while (*((vHwdptr)addr) != 0xffff);
++ printf("done.\n");
++ }
++
++ }
++
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ printf (" Erase Operation Completed.\n");
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
++ int bytes; /* number of bytes to program in current word */
++ int left; /* number of bytes left to program */
++ int res;
++ ulong cp, wp;
++ int count, i, l, rc, port_width;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++
++ /* get lower word aligned address */
++ wp = (addr & ~1);
++ port_width = 2;
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ cnt -= port_width;
++
++ if (count++ > 0x800) {
++ spin_wheel ();
++ count = 0;
++ }
++ }
++
++ if (cnt == 0) {
++ return (0);
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ return (write_word (info, wp, SWAP (data)));
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word to Flash
++ * A word is 16 or 32 bits, whichever the bus width of the flash bank
++ * (not an individual chip) is.
++ *
++ * returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_word (flash_info_t *info, FPWV *plAddress, FPW ulData)
++{
++ ulong start;
++ int flag;
++ int res = 0; /* result, assume success */
++ FPWV *base; /* first address in flash bank */
++ volatile USHORT *psAddress;
++ volatile USHORT *address_cs;
++ USHORT tmp;
++ ULONG tmp_ptr;
++
++ // Lower WORD.
++ psAddress = (USHORT *)plAddress;
++ tmp_ptr = (ULONG) plAddress;
++ address_cs = (USHORT *) (tmp_ptr & 0xFE000000);
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ {
++ *plAddress = (FPW)0x00400040;
++ *plAddress = ulData;
++ while ((*plAddress & 0x80) == 0);
++ }
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ {
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xAA);
++ *((vHwdptr)address_cs + 0x2AA) = ((Hwd)0x55);
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xA0);
++ *psAddress = ulData;
++ // Wait for ready.
++ while (1)
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ if(tmp & 0x20) // Exceeded Time Limit
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ flash_reset_sector(info, (ULONG) psAddress);
++ return 1;
++ }
++ }
++ }
++ }
++ }
++
++ // Return to read mode
++ flash_reset_sector(info, (ULONG) psAddress);
++
++ // Verify the data.
++ if (*psAddress != ulData)
++ {
++ return 1;
++ printf("Write of one 16-bit word failed\n");
++ }
++ return 0;
++}
++
++void inline spin_wheel (void)
++{
++ static int p = 0;
++ static char w[] = "\\/-";
++
++ printf ("\010%c", w[p]);
++ (++p == 3) ? (p = 0) : 0;
++}
+diff -Nurd u-boot-1.2.0/board/davinci/flash_params.h u-boot-1.2.0-leopard/board/davinci/flash_params.h
+--- u-boot-1.2.0/board/davinci/flash_params.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/flash_params.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,319 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _FLASH_PARAMSH_
++#define _FLASH_PARAMSH_
++//
++//Structs
++//
++typedef struct _PageInfo
++{
++ ULONG reserved;
++ BYTE BlockReserved;
++ BYTE BadBlockFlag;
++ USHORT reserved2;
++}PageInfo, *PPageInfo;
++
++typedef struct
++{
++ ULONG ReturnValue;
++ ULONG ReadAddress;
++ ULONG WriteAddress;
++ ULONG Size;
++} Download_Parms, *PDownload_Parms;
++
++#define NO_ERROR 0
++#define CORRECTED_ERROR 1
++#define ECC_ERROR 2
++#define UNCORRECTED_ERROR 3
++
++
++#define BIT0 0x00000001
++#define BIT1 0x00000002
++#define BIT2 0x00000004
++#define BIT3 0x00000008
++#define BIT4 0x00000010
++#define BIT5 0x00000020
++#define BIT6 0x00000040
++#define BIT7 0x00000080
++#define BIT8 0x00000100
++#define BIT9 0x00000200
++#define BIT10 0x00000400
++#define BIT11 0x00000800
++#define BIT12 0x00001000
++#define BIT13 0x00002000
++#define BIT14 0x00004000
++#define BIT15 0x00008000
++#define BIT16 0x00010000
++#define BIT17 0x00020000
++#define BIT18 0x00040000
++#define BIT19 0x00080000
++#define BIT20 0x00100000
++#define BIT21 0x00200000
++#define BIT22 0x00400000
++#define BIT23 0x00800000
++#define BIT24 0x01000000
++#define BIT25 0x02000000
++#define BIT26 0x04000000
++#define BIT27 0x08000000
++#define BIT28 0x10000000
++#define BIT29 0x20000000
++#define BIT30 0x40000000
++#define BIT31 0x80000000
++
++
++
++// Status bit pattern
++#define STATUS_READY 0x40
++#define STATUS_ERROR 0x01
++//
++//NOR SUPPORT
++//
++// Flash ID Commands INTEL
++#define INTEL_ID_CMD ((Hwd)0x0090) // INTEL ID CMD
++#define INTEL_MANF_ID ((Hwd)0x0089) // INTEL Manf ID expected
++#define INTEL_DEVICE_8T ((Hwd)0x88F1) // INTEL 8Mb top device code
++#define INTEL_DEVICE_8B ((Hwd)0x88F2) // INTEL 8Mb bottom device code
++#define INTEL_DEVICE_16T ((Hwd)0x88F3) // INTEL 16Mb top device code
++#define INTEL_DEVICE_16B ((Hwd)0x88F4) // INTEL 16Mb bottom device code
++#define INTELS_J3_DEVICE_32 ((Hwd)0x0016) // INTEL Strata J3 32Mb device code
++#define INTELS_J3_DEVICE_64 ((Hwd)0x0017) // INTEL Strata J3 64Mb device code
++#define INTELS_J3_DEVICE_128 ((Hwd)0x0018) // INTEL Strata J3 128Mb device code
++#define INTELS_K3_DEVICE_64 ((Hwd)0x8801) // INTEL Strata K3 64Mb device code
++#define INTELS_K3_DEVICE_128 ((Hwd)0x8802) // INTEL Strata K3 128Mb device code
++#define INTELS_K3_DEVICE_256 ((Hwd)0x8803) // INTEL Strata K3 256Mb device code
++#define INTELS_W18_DEVICE_128T ((Hwd)0x8876) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_W18_DEVICE_128B ((Hwd)0x8867) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_128T ((Hwd)0x880C) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_L18_DEVICE_128B ((Hwd)0x880F) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_256T ((Hwd)0x880D) // INTEL Wirless Flash Top 256 Mb device code
++#define INTELS_L18_DEVICE_256B ((Hwd)0x8810) // INTEL Wirless Flash Bottom 256 Mb device code
++#define INTELS_K18_DEVICE_256B ((Hwd)0x8807) // INTEL Wirless Flash Bottom 256 Mb device code
++#define AMD1_DEVICE_ID ((Hwd)0x2253) // AMD29DL323CB
++#define AMD2_DEVICE_ID ((Hwd)0x2249) // AMD29LV160D
++#define AMD3_DEVICE_ID1 ((Hwd)0x2212) // AMD29LV256M
++#define AMD3_DEVICE_ID2 ((Hwd)0x2201) // AMD29LV256M
++// Flash ID Commands FUJITSU (Programs like AMD)
++#define FUJITSU_MANF_ID ((Hwd)0x04) // Fujitsu Manf ID expected
++#define FUJITSU1_DEVICE_ID ((Hwd)0x2253) // MBM29DL323BD
++//Micron Programs Like Intel or Micron
++#define MICRON_MANF_ID ((Hwd)0x002C) // MICRON Manf ID expected
++#define MICRON_MT28F_DEVICE_128T ((Hwd)0x4492) // MICRON Flash device Bottom 128 Mb
++//Samsung Programs like AMD
++#define SAMSUNG_MANF_ID ((Hwd)0x00EC) //SAMSUNG Manf ID expected
++#define SAMSUNG_K8S2815E_128T ((Hwd) 0x22F8) //SAMSUNG NOR Flash device TOP 128 Mb
++// Flash Erase Commands AMD and FUJITSU
++// Flash ID Commands AMD
++#define AMD_ID_CMD0 ((Hwd)0xAA) // AMD ID CMD 0
++#define AMD_CMD0_ADDR 0x555 // AMD CMD0 Offset
++#define AMD_ID_CMD1 ((Hwd)0x55) // AMD ID CMD 1
++#define AMD_CMD1_ADDR 0x2AA // AMD CMD1 Offset
++#define AMD_ID_CMD2 ((Hwd)0x90) // AMD ID CMD 2
++#define AMD_CMD2_ADDR 0x555 // AMD CMD2 Offset
++#define AMD_MANF_ID ((Hwd)0x01) // AMD Manf ID expected
++#define AMD_DEVICE_ID_MULTI ((Hwd)0x227E)// Indicates Multi-Address Device ID
++#define AMD_DEVICE_ID_OFFSET 0x1
++#define AMD_DEVICE_ID_OFFSET1 0x0E // First Addr for Multi-Address ID
++#define AMD_DEVICE_ID_OFFSET2 0x0F // Second Addr for Multi-Address ID
++#define AMD_DEVICE_RESET ((Hwd)0x00F0) // AMD Device Reset Command
++#define AMD_ERASE_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_CMD3 ((Hwd)0xAA) // AMD29LV017B Erase CMD 3
++#define AMD_ERASE_CMD4 ((Hwd)0x55) // AMD29LV017B Erase CMD 4
++#define AMD_ERASE_CMD5 ((Hwd)0x10) // AMD29LV017B Erase CMD 5
++#define AMD_ERASE_DONE ((Hwd)0xFFFF) // AMD29LV017B Erase Done
++#define AMD_ERASE_BLK_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_BLK_CMD3 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD4 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD5 ((Hwd)0x30)
++#define AMD_PROG_CMD0 ((Hwd)0xAA)
++#define AMD_PROG_CMD1 ((Hwd)0x55)
++#define AMD_PROG_CMD2 ((Hwd)0xA0)
++#define AMD2_ERASE_CMD0 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 0
++#define AMD2_ERASE_CMD1 ((Hwd)0x0055) // AMD29DL800B Erase CMD 1
++#define AMD2_ERASE_CMD2 ((Hwd)0x0080) // AMD29DL800B Erase CMD 2
++#define AMD2_ERASE_CMD3 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 3
++#define AMD2_ERASE_CMD4 ((Hwd)0x0055) // AMD29DL800B Erase CMD 4
++#define AMD2_ERASE_CMD5 ((Hwd)0x0030) // AMD29DL800B Erase CMD 5
++#define AMD2_ERASE_DONE ((Hwd)0x00FF) // AMD29DL800B Erase Done
++#define AMD_WRT_BUF_LOAD_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_LOAD_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_LOAD_CMD2 ((Hwd)0x25)
++#define AMD_WRT_BUF_CONF_CMD0 ((Hwd)0x29)
++#define AMD_WRT_BUF_ABORT_RESET_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_ABORT_RESET_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_ABORT_RESET_CMD2 ((Hwd)0xF0)
++// Flash Erase Commands INTEL
++#define INTEL_ERASE_CMD0 ((Hwd)0x0020) // INTEL Erase CMD 0
++#define INTEL_ERASE_CMD1 ((Hwd)0x00D0) // INTEL Erase CMD 1
++#define INTEL_ERASE_DONE ((Hwd)0x0080) // INTEL Erase Done
++#define INTEL_READ_MODE ((Hwd)0x00FF) // INTEL Read Array Mode
++#define STRATA_READ 0x4
++#define STRATA_WRITE 0x8
++// Flash Block Information
++// Intel Burst devices:
++// 2MB each (8 8KB [param] and 31 64KB [main] blocks each) for 8MB total
++#define NUM_INTEL_BURST_BLOCKS 8
++#define PARAM_SET0 0
++#define MAIN_SET0 1
++#define PARAM_SET1 2
++#define MAIN_SET1 3
++#define PARAM_SET2 4
++#define MAIN_SET2 5
++#define PARAM_SET3 6
++#define MAIN_SET3 7
++// Intel Strata devices:
++// 4MB each (32 128KB blocks each) for 8MB total
++// 8MB each (64 128KB blocks each) for 16MB total
++// 16MB each (128 128KB blocks each) for 32MB total
++#define NUM_INTEL_STRATA_BLOCKS 8
++#define BLOCK_SET0 0
++#define BLOCK_SET1 1
++#define BLOCK_SET2 2
++#define BLOCK_SET3 3
++#define BLOCK_SET4 4
++#define BLOCK_SET5 5
++#define BLOCK_SET6 6
++#define BLOCK_SET7 7
++// For AMD Flash
++#define NUM_AMD_SECTORS 8 // Only using the first 8 8-KB sections (64 KB Total)
++#define AMD_ADDRESS_CS_MASK 0xFE000000 //--AMD-- Set-up as 0xFE000000 per Jon Hunter (Ti)
++// Flash Types
++enum NORFlashType {
++ FLASH_NOT_FOUND,
++ FLASH_UNSUPPORTED,
++ FLASH_AMD_LV017_2MB, // (AMD AM29LV017B-80RFC/RE)
++ FLASH_AMD_DL800_1MB_BOTTOM, // (AMD AM29DL800BB-70EC)
++ FLASH_AMD_DL800_1MB_TOP, // (AMD AM29DL800BT-70EC)
++ FLASH_AMD_DL323_4MB_BOTTOM, // (AMD AM29DL323CB-70EC)
++ FLASH_AMD_DL323_4MB_TOP, // (AMD AM29DL323BT-70EC)
++ FLASH_AMD_LV160_2MB_BOTTOM,
++ FLASH_AMD_LV160_2MB_TOP,
++ FLASH_AMD_LV256M_32MB, // (AMD AM29LV256MH/L)
++ FLASH_INTEL_BURST_8MB_BOTTOM, // (Intel DT28F80F3B-95)
++ FLASH_INTEL_BURST_8MB_TOP, // (Intel DT28F80F3T-95)
++ FLASH_INTEL_BURST_16MB_BOTTOM, // (Intel DT28F160F3B-95)
++ FLASH_INTEL_BURST_16MB_TOP, // (Intel DT28F160F3T-95)
++ FLASH_INTEL_STRATA_J3_4MB, // (Intel DT28F320J3A)
++ FLASH_INTEL_STRATA_J3_8MB, // (Intel DT28F640J3A)
++ FLASH_INTEL_STRATA_J3_16MB, // (Intel DT28F128J3A)
++ FLASH_FUJITSU_DL323_4MB_BOTTOM, // (Fujitsu DL323 Bottom
++ FLASH_INTEL_STRATA_K3_8MB, // (Intel 28F64K3C115)
++ FLASH_INTEL_STRATA_K3_16MB, // (Intel 28F128K3C115)
++ FLASH_INTEL_STRATA_K3_32MB, // (Intel 28F256K3C115)
++ FLASH_INTEL_W18_16MB_TOP, // (Intel 28F128W18T) }
++ FLASH_INTEL_W18_16MB_BOTTOM, // (Intel 28F128W18B) }
++ FLASH_INTEL_L18_16MB_TOP, // (Intel 28F128L18T) }
++ FLASH_INTEL_L18_16MB_BOTTOM, // (Intel 28F128L18B) }
++ FLASH_INTEL_L18_32MB_TOP, // (Intel 28F256L18T) }
++ FLASH_INTEL_L18_32MB_BOTTOM, // (Intel 28F256L18B) }
++ FLASH_INTEL_K18_32MB_BOTTOM, // (Intel 28F256K18B) }
++ FLASH_MICRON_16MB_TOP, // (Micron MT28F160C34 )
++ FLASH_SAMSUNG_16MB_TOP // (Samsung K8S281ETA)
++};
++////NAND SUPPORT
++//
++enum NANDFlashType {
++ NANDFLASH_NOT_FOUND,
++ NANDFLASH_SAMSUNG_32x8_Q, // (Samsung K9F5608Q0B)
++ NANDFLASH_SAMSUNG_32x8_U, // (Samsung K9F5608U0B)
++ NANDFLASH_SAMSUNG_16x16_Q, // (Samsung K9F5616Q0B)
++ NANDFLASH_SAMSUNG_16x16_U, // (Samsung K9F5616U0B)
++ NANDFLASH_SAMSUNG_16x8_U // (Samsung K9F1G08QOM)
++};
++// Samsung Manufacture Code
++#define SAMSUNG_MANUFACT_ID 0xEC
++// Samsung Nand Flash Device ID
++#define SAMSUNG_K9F5608Q0B 0x35
++#define SAMSUNG_K9F5608U0B 0x75
++#define SAMSUNG_K9F5616Q0B 0x45
++#define SAMSUNG_K9F5616U0B 0x55
++// MACROS for NAND Flash support
++// Flash Chip Capability
++#define NUM_BLOCKS 0x800 // 32 MB On-board NAND flash.
++#define PAGE_SIZE 512
++#define SPARE_SIZE 16
++#define PAGES_PER_BLOCK 32
++#define PAGE_TO_BLOCK(page) ((page) >> 5 )
++#define BLOCK_TO_PAGE(block) ((block) << 5 )
++#define FILE_TO_PAGE_SIZE(fs) ((fs / PAGE_SIZE) + ((fs % PAGE_SIZE) ? 1 : 0))
++// For flash chip that is bigger than 32 MB, we need to have 4 step address
++#ifdef NAND_SIZE_GT_32MB
++#define NEED_EXT_ADDR 1
++#else
++#define NEED_EXT_ADDR 0
++#endif
++// Nand flash block status definitions.
++#define BLOCK_STATUS_UNKNOWN 0x01
++#define BLOCK_STATUS_BAD 0x02
++#define BLOCK_STATUS_READONLY 0x04
++#define BLOCK_STATUS_RESERVED 0x08
++#define BLOCK_RESERVED 0x01
++#define BLOCK_READONLY 0x02
++#define BADBLOCKMARK 0x00
++// NAND Flash Command. This appears to be generic across all NAND flash chips
++#define CMD_READ 0x00 // Read
++#define CMD_READ1 0x01 // Read1
++#define CMD_READ2 0x50 // Read2
++#define CMD_READID 0x90 // ReadID
++#define CMD_WRITE 0x80 // Write phase 1
++#define CMD_WRITE2 0x10 // Write phase 2
++#define CMD_ERASE 0x60 // Erase phase 1
++#define CMD_ERASE2 0xd0 // Erase phase 2
++#define CMD_STATUS 0x70 // Status read
++#define CMD_RESET 0xff // Reset
++//
++//Prototpyes
++//
++// NOR Flash Dependent Function Pointers
++void (*User_Hard_Reset_Flash)(void);
++void (*User_Soft_Reset_Flash)(unsigned long addr);
++void (*User_Flash_Erase_Block)(unsigned long addr);
++void (*User_Flash_Erase_All)(unsigned long addr);
++void (*User_Flash_Write_Entry)(void);
++int (*User_Flash_Write)(unsigned long *addr, unsigned short data);
++int (*User_Flash_Optimized_Write)(unsigned long *addr, unsigned short data[], unsigned long);
++void (*User_Flash_Write_Exit)(void);
++// Flash AMD Device Dependent Routines
++void AMD_Hard_Reset_Flash(void);
++void AMD_Soft_Reset_Flash(unsigned long);
++void AMD_Flash_Erase_Block(unsigned long);
++void AMD_Flash_Erase_All(unsigned long);
++int AMD_Flash_Write(unsigned long *, unsigned short);
++int AMD_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++void AMD_Write_Buf_Abort_Reset_Flash( unsigned long plAddress );
++// Flash Intel Device Dependent Routines
++void INTEL_Hard_Reset_Flash(void);
++void INTEL_Soft_Reset_Flash(unsigned long addr);
++void INTEL_Flash_Erase_Block(unsigned long);
++int INTEL_Flash_Write(unsigned long *addr, unsigned short data);
++int INTEL_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++
++//General Functions
++void Flash_Do_Nothing(void);
++
++#endif
++
++
+diff -Nurd u-boot-1.2.0/board/davinci/lowlevel_init.S u-boot-1.2.0-leopard/board/davinci/lowlevel_init.S
+--- u-boot-1.2.0/board/davinci/lowlevel_init.S 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/lowlevel_init.S 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,764 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2003
++ * Texas Instruments, <www.ti.com>
++ * Kshitij Gupta <Kshitij@ti.com>
++ *
++ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
++ *
++ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Swaminathan S, Nov 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#if defined(CONFIG_OMAP1610)
++#include <./configs/omap1510.h>
++#endif
++
++_TEXT_BASE:
++ .word TEXT_BASE /* sdram load addr from config.mk */
++
++.global reset_cpu
++reset_cpu:
++ bl reset_processor
++
++
++.globl lowlevel_init
++lowlevel_init:
++ /*mov pc, lr*/
++
++ /*------------------------------------------------------*
++ * mask all IRQs by setting all bits in the EINT default *
++ *------------------------------------------------------*/
++ mov r1, #0x00000000
++ ldr r0, =EINT_ENABLE0
++ str r1, [r0]
++ ldr r0, =EINT_ENABLE1
++ str r1, [r0]
++
++ /*------------------------------------------------------*
++ * Put the GEM in reset *
++ *------------------------------------------------------*/
++
++ /* Put the GEM in reset */
++ LDR R8, PSC_GEM_FLAG_CLEAR
++ LDR R6, MDCTL_GEM
++ LDR R7, [R6]
++ AND R7, R7, R8
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x2
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStopGem:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x2
++ CMP R7, #0x0
++ BNE checkStatClkStopGem
++
++ /* Check for GEM Reset Completion */
++checkGemStatClkStop:
++ LDR R6, MDSTAT_GEM
++ LDR R7, [R6]
++ AND R7, R7, #0x100
++ CMP R7, #0x0
++ BNE checkGemStatClkStop
++
++ /* Do this for enabling a WDT initiated reset this is a workaround
++ for a chip bug. Not required under normal situations */
++ LDR R6, P1394
++ MOV R10, #0x0
++ STR R10, [R6]
++
++ /*------------------------------------------------------*
++ * Enable L1 & L2 Memories in Fast mode *
++ *------------------------------------------------------*/
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, MMARG_BRF0
++ LDR R10, MMARG_BRF0_VAL
++ STR R10, [R6]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++ /*------------------------------------------------------*
++ * DDR2 PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R10, #0x0
++ LDR R6, PLL2_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R10, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++WaitPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitPPL2Loop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL2_PLLM
++ /*MOV R2, #0x13 Orig value */
++ /*MOV R2, #0xB 165MHz */
++ /*MOV R2, #0xD 189 MHz */
++ MOV R2, #0x17 /* 162 MHz */
++ STR R2, [R6] /* R2 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV2
++ MOV R3, #0x1 /* Orig */
++ /*MOV R3, #0x0*/
++ STR R3, [R6] /* R3 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV1
++ /*MOV R4, #0x9 Orig */
++ /*MOV R4, #0x5 165MHz */
++ /*MOV R4, #0x6 189 MHz */
++ MOV R4, #0xB /* 54 MHz */
++ STR R4, [R6] /* R4 */
++
++ /* PLL2 DIV1 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV2
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop_0:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop_0
++
++ /* PLL2 DIV2 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV1
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0x218
++ResetPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetPPL2Loop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++PLL2Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL2Lock
++
++ /* Enable the PLL */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkStop
++
++ /*------------------------------------------------------*
++ * Program DDR2 MMRs for 162MHz Setting *
++ *------------------------------------------------------*/
++
++ /* Program PHY Control Register */
++ LDR R6, DDRCTL
++ LDR R7, DDRCTL_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM Bank Config Register */
++ LDR R6, SDCFG
++ LDR R7, SDCFG_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-0 Config Register */
++ LDR R6, SDTIM0
++ LDR R7, SDTIM0_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDTIM1
++ LDR R7, SDTIM1_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program the SDRAM Bang Config Control Register */
++ LDR R10, MASK_VAL
++ LDR R8, SDCFG
++ LDR R9, SDCFG_VAL
++ AND R9, R9, R10
++ STR R9, [R8]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDREF
++ LDR R7, SDREF_VAL
++ STR R7, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Issue a Dummy DDR2 read/write */
++ LDR R8, DDR2_VAL
++ LDR R7, DUMMY_VAL
++ STR R7, [R8]
++ LDR R7, [R8]
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x1
++ BNE checkDDRStatClkStop2
++
++ /*------------------------------------------------------*
++ * Turn DDR2 Controller Clocks On *
++ *------------------------------------------------------*/
++
++ /* Enable the DDR2 LPSC Module */
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkEn2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkEn2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkEn2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkEn2
++
++ /* DDR Writes and Reads */
++ LDR R6, CFGTEST
++ MOV R3, #0x1
++ STR R3, [R6] /* R3 */
++
++ /*------------------------------------------------------*
++ * System PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R2, #0x0
++ LDR R6, PLL1_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R2, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++
++WaitLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitLoop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Disable the PLL */
++ ORR R8, R8, #0x10
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL1_PLLM
++ /*MOV R3, #0x10 As per Amit, PLL should be in normal mode i.e X by 16 */
++ /*MOV R3, #0x11 As per Ebby 486 MHz */
++ /*MOV R3, #0x14 For 567MHz */
++ MOV R3, #0x15 /* For 594MHz */
++ STR R3, [R6]
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0xFF
++
++ResetLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetLoop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL1_CTL
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++
++PLL1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL1Lock
++
++ /* Enable the PLL */
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ nop
++ nop
++ nop
++ nop
++
++ /*------------------------------------------------------*
++ * AEMIF configuration for NOR Flash (double check) *
++ *------------------------------------------------------*/
++ LDR R0, _PINMUX0
++ LDR R1, _DEV_SETTING
++ STR R1, [R0]
++
++ LDR R0, WAITCFG
++ LDR R1, WAITCFG_VAL
++ LDR R2, [R0]
++ ORR R2, R2, R1
++ STR R2, [R0]
++
++ LDR R0, ACFG3
++ LDR R1, ACFG3_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG4
++ LDR R1, ACFG4_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG5
++ LDR R1, ACFG5_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ /*--------------------------------------*
++ * VTP manual Calibration *
++ *--------------------------------------*/
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR0
++ STR R1, [R0]
++
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR1
++ STR R1, [R0]
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTPLock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTPLock
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, DDRVTPR
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ AND R8, R7, #0x3E0
++ ORR R8, R7, R8
++ LDR R7, VTP_RECAL
++ ORR R8, R7, R8
++ LDR R7, VTP_EN
++ ORR R8, R7, R8
++ STR R8, [R0]
++
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTP1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTP1Lock
++
++ LDR R1, [R0]
++ LDR R2, VTP_MASK
++ AND R2, R1, R2
++ STR R2, [R0]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++
++
++ /* Start MPU Timer 1 */
++/* MOV R10, #0x1AFFFFFF
++
++WaitRam:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitRam
++*/
++
++ /* back to arch calling code */
++ mov pc, lr
++
++ /* the literal pools origin */
++ .ltorg
++
++REG_TC_EMIFS_CONFIG: /* 32 bits */
++ .word 0xfffecc0c
++REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
++ .word 0xfffecc10
++REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
++ .word 0xfffecc14
++REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
++ .word 0xfffecc18
++REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
++ .word 0xfffecc1c
++
++_PINMUX0: .word 0x01C40000 /* Device Configuration Registers */
++_PINMUX1: .word 0x01C40004 /* Device Configuration Registers */
++
++_DEV_SETTING: .word 0x00000C1F
++
++AEMIF_BASE_ADDR: .word 0x01E00000
++WAITCFG: .word 0x01E00004
++ACFG2: .word 0x01E00010
++ACFG3: .word 0x01E00014
++ACFG4: .word 0x01E00018
++ACFG5: .word 0x01E0001C
++
++WAITCFG_VAL: .word 0x0
++ACFG2_VAL: .word 0x3FFFFFFD
++ACFG3_VAL: .word 0x3FFFFFFD
++ACFG4_VAL: .word 0x3FFFFFFD
++ACFG5_VAL: .word 0x3FFFFFFD
++
++MDCTL_DDR2: .word 0x01C41A34
++PTCMD: .word 0x01C41120
++PTSTAT: .word 0x01C41128
++MDSTAT_DDR2: .word 0x01C41834
++
++MDCTL_TPCC: .word 0x01C41A08
++MDSTAT_TPCC: .word 0x01C41808
++
++MDCTL_TPTC0: .word 0x01C41A0C
++MDSTAT_TPTC0: .word 0x01C4180C
++
++MDCTL_TPTC1: .word 0x01C41A10
++MDSTAT_TPTC1: .word 0x01C41810
++
++DDR2DEBUG: .word 0x8FFFF000
++
++/* EINT0 register */
++EINT_ENABLE0:
++ .word 0x01c48018
++
++/* EINT1 register */
++EINT_ENABLE1:
++ .word 0x01c4801C
++
++CLEAR_FLAG: .word 0xFFFFFFFF
++EDMA_PARAM0_D_S_BIDX_VAL: .word 0x00010001
++PSC_FLAG_CLEAR: .word 0xFFFFFFE0
++PSC_GEM_FLAG_CLEAR: .word 0xFFFFFEFF
++MDCTL_TPCC_SYNC: .word 0x01C41A08
++MDSTAT_TPCC_SYNC: .word 0x01C41808
++
++MDCTL_TPTC0_SYNC: .word 0x01C41A0C
++MDSTAT_TPTC0_SYNC: .word 0x01C4180C
++
++MDCTL_TPTC1_SYNC: .word 0x01C41A10
++MDSTAT_TPTC1_SYNC: .word 0x01C41810
++
++PTCMD_SYNC: .word 0x01C41120
++PTSTAT_SYNC: .word 0x01C41128
++DATA_MAX: .word 0x0000FFFF
++SPIN_ADDR: .word 0x00003FFC /* ARM PC value(B $) for the DSP Test cases */
++SPIN_OPCODE: .word 0xEAFFFFFE
++
++/* Interrupt Clear Register */
++FIQ0_CLEAR: .word 0x01C48000
++FIQ1_CLEAR: .word 0x01C48004
++IRQ0_CLEAR: .word 0x01C48008
++IRQ1_CLEAR: .word 0x01C4800C
++
++/* DDR2 MMR & CONFIGURATION VALUES for 75 MHZ */
++DDRCTL: .word 0x200000E4
++SDREF: .word 0x2000000C
++SDCFG: .word 0x20000008
++SDTIM0: .word 0x20000010
++SDTIM1: .word 0x20000014
++SDSTAT: .word 0x20000004
++VTPIOCR: .word 0x200000F0 /* VTP IO Control register */
++DDRVTPR: .word 0x01C42030 /* DDR VPTR MMR */
++DFT_ENABLE: .word 0x01C4004C
++VTP_MMR0: .word 0x201F
++VTP_MMR1: .word 0xA01F
++PCH_MASK: .word 0x3E0
++VTP_LOCK_COUNT: .word 0x5b0
++VTP_MASK: .word 0xFFFFDFFF
++VTP_RECAL: .word 0x40000
++VTP_EN: .word 0x02000
++
++
++CFGTEST: .word 0x80010000
++
++/* original values
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00008832
++MASK_VAL: .word 0x00000FFF
++SDTIM0_VAL_135MHz: .word 0x30923A91
++SDTIM1_VAL_135MHz: .word 0x0019c722
++SDREF_VAL: .word 0x000005c3
++*/
++
++/* 162MHz as per GEL file for DVEVM with Micron DDR2 SDRAM */
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00178632 /* CL=3 for MT47H64M16BT-5E */
++MASK_VAL: .word 0xFFFF7FFF
++SDTIM0_VAL_162MHz: .word 0x28923211
++SDTIM1_VAL_162MHz: .word 0x0016c722
++SDREF_VAL: .word 0x000004F0
++
++/* GEM Power Up & LPSC Control Register */
++CHP_SHRTSW: .word 0x01C40038
++
++PD1_CTL: .word 0x01C41304
++EPCPR: .word 0x01C41070
++EPCCR: .word 0x01C41078
++MDCTL_GEM: .word 0x01C41A9C
++MDSTAT_GEM: .word 0x01C4189C
++MDCTL_IMCOP: .word 0x01C41AA0
++MDSTAT_IMCOP: .word 0x01C418A0
++
++PTCMD_0: .word 0x01C41120
++PTSTAT_0: .word 0x01C41128
++P1394: .word 0x01C41a20
++
++PLL_CLKSRC_MASK: .word 0xFFFFFEFF /* Mask the Clock Mode bit and it is programmble through the run script */
++PLL_ENSRC_MASK: .word 0xFFFFFFDF /* Select the PLLEN source */
++PLL_BYPASS_MASK: .word 0xFFFFFFFE /* Put the PLL in BYPASS, eventhough the device */
++PLL_RESET_MASK: .word 0xFFFFFFF7 /* Put the PLL in Reset Mode */
++PLL_PWRUP_MASK: .word 0xFFFFFFFD /* PLL Power up Mask Bit */
++PLL_DISABLE_ENABLE_MASK: .word 0xFFFFFFEF /* Enable the PLL from Disable */
++PLL_LOCK_COUNT: .word 0x2000
++
++/* PLL1-SYSTEM PLL MMRs */
++PLL1_CTL: .word 0x01C40900
++PLL1_PLLM: .word 0x01C40910
++
++/* PLL2-SYSTEM PLL MMRs */
++PLL2_CTL: .word 0x01C40D00
++PLL2_PLLM: .word 0x01C40D10
++PLL2_DIV2: .word 0x01C40D1C
++PLL2_DIV1: .word 0x01C40D18
++PLL2_PLLCMD: .word 0x01C40D38
++PLL2_PLLSTAT: .word 0x01C40D3C
++PLL2_BPDIV: .word 0x01C40D2C
++PLL2_DIV_MASK: .word 0xFFFF7FFF
++
++
++MDCTL_DDR2_0: .word 0x01C41A34
++MDSTAT_DDR2_0: .word 0x01C41834
++DLLPWRUPMASK: .word 0xFFFFFFEF
++DDR2_ADDR: .word 0x80000000
++
++DFT_BASEADDR: .word 0x01C42000
++MMARG_BRF0: .word 0x01C42010 /* BRF margin mode 0 (Read / write)*/
++MMARG_G10: .word 0x01C42018 /*GL margin mode 0 (Read / write)*/
++MMARG_BRF0_VAL: .word 0x00444400
++DDR2_VAL: .word 0x80000000
++DUMMY_VAL: .word 0xA55AA55A
++
++/* command values */
++.equ CMD_SDRAM_NOP, 0x00000000
++.equ CMD_SDRAM_PRECHARGE, 0x00000001
++.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
++.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
+diff -Nurd u-boot-1.2.0/board/davinci/nand.c u-boot-1.2.0-leopard/board/davinci/nand.c
+--- u-boot-1.2.0/board/davinci/nand.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/nand.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,111 @@
++/*
++ * NAND driver for TI DaVinci based boards.
++ *
++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
++ *
++ * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
++ */
++
++/*
++ *
++ * linux/drivers/mtd/nand/nand_davinci.c
++ *
++ * NAND Flash Driver
++ *
++ * Copyright (C) 2006 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ * Overview:
++ * This is a device driver for the NAND flash device found on the
++ * DaVinci board which utilizes the Samsung k9k2g08 part.
++ *
++ Modifications:
++ ver. 1.0: Feb 2005, Vinod/Sudhakar
++ -
++ *
++ */
++
++#include <common.h>
++
++#if (CONFIG_COMMANDS & CFG_CMD_NAND)
++#if !defined(CFG_NAND_LEGACY)
++
++#include "soc.h"
++#include <nand.h>
++#include <asm/arch/nand_defs.h>
++#include <asm/arch/emif_defs.h>
++
++extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
++
++static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++ struct nand_chip *this = mtd->priv;
++ u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
++
++ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++
++ switch (cmd) {
++ case NAND_CTL_SETCLE:
++ IO_ADDR_W |= MASK_CLE;
++ break;
++ case NAND_CTL_SETALE:
++ IO_ADDR_W |= MASK_ALE;
++ break;
++ }
++
++ this->IO_ADDR_W = (void *)IO_ADDR_W;
++}
++
++static int nand_davinci_dev_ready(struct mtd_info *mtd)
++{
++ emifregs emif_addr;
++
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ return(emif_addr->NANDFSR & 0x1);
++}
++
++static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
++{
++ while(!nand_davinci_dev_ready(mtd)) {;}
++ *NAND_CE0CLE = NAND_STATUS;
++ return(*NAND_CE0DATA);
++}
++
++int board_nand_init(struct nand_chip *nand)
++{
++ nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
++ nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
++ nand->chip_delay = 0;
++ nand->options = 0;
++ nand->eccmode = NAND_ECC_SOFT;
++
++ /* Set address of hardware control function */
++ nand->hwcontrol = nand_davinci_hwcontrol;
++
++ nand->dev_ready = nand_davinci_dev_ready;
++ nand->waitfunc = nand_davinci_waitfunc;
++
++ return 0;
++}
++
++#else
++#error "U-Boot legacy NAND support not available for DaVinci chips"
++#endif
++#endif /* CFG_USE_NAND */
+diff -Nurd u-boot-1.2.0/board/davinci/soc.h u-boot-1.2.0-leopard/board/davinci/soc.h
+--- u-boot-1.2.0/board/davinci/soc.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/soc.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,339 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Modifications:
++ * ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++
++#ifndef _SOC_H
++#define _SOC_H
++
++#include <asm/arch/types.h>
++
++#define CSL_IDEF_INLINE static inline
++/*****************************************************************************\
++* Peripheral Instance counts
++\*****************************************************************************/
++
++#define CSL_UART_CNT 3
++#define CSL_I2C_CNT 1
++#define CSL_TMR_CNT 4
++#define CSL_WDT_CNT 1
++#define CSL_PWM_CNT 3
++#define CSL_PLLC_CNT 2
++#define CSL_PWR_SLEEP_CTRL_CNT 1
++#define CSL_SYS_DFT_CNT 1
++#define CSL_INTC_CNT 1
++#define CSL_IEEE1394_CNT 1
++#define CSL_USBOTG_CNT 1
++#define CSL_ATA_CNT 1
++#define CSL_SPI_CNT 1
++#define CSL_GPIO_CNT 1
++#define CSL_UHPI_CNT 1
++#define CSL_VPSS_REGS_CNT 1
++#define CSL_EMAC_CTRL_CNT 1
++#define CSL_EMAC_WRAP_CNT 1
++#define CSL_EMAC_RAM_CNT 1
++#define CSL_MDIO_CNT 1
++#define CSL_EMIF_CNT 1
++#define CSL_NAND_CNT 1
++#define CSL_MCBSP_CNT 1
++#define CSL_MMCSD_CNT 1
++#define CSL_MS_CNT 1
++#define CSL_DDR_CNT 1
++#define CSL_VLYNQ_CNT 1
++#define CSL_PMX_CNT 1
++
++/*****************************************************************************\
++* Peripheral Instance enumeration
++\*****************************************************************************/
++
++/** @brief Peripheral Instance for UART */
++#define CSL_UART_1 (0) /** Instance 1 of UART */
++
++/** @brief Peripheral Instance for UART */
++#define CSL_UART_2 (1) /** Instance 2 of UART */
++
++/** @brief Peripheral Instance for UART */
++#define CSL_UART_3 (2) /** Instance 3 of UART */
++
++/** @brief Peripheral Instance for I2C */
++#define CSL_I2C (0) /** Instance 1 of I2C */
++
++/** @brief Peripheral Instance for Tmr0 */
++#define CSL_TMR_1 (0) /** Instance 1 of Tmr */
++
++/** @brief Peripheral Instance for Tmr1 */
++#define CSL_TMR_2 (1) /** Instance 2 of Tmr */
++
++/** @brief Peripheral Instance for Tmr2 */
++#define CSL_TMR_3 (2) /** Instance 3 of Tmr */
++
++/** @brief Peripheral Instance for Tmr3 */
++#define CSL_TMR_4 (3) /** Instance 4 of Tmr */
++
++/** @brief Peripheral Instance for WDT */
++#define CSL_WDT (0) /** Instance of WDT */
++
++/** @brief Peripheral Instance for PWM */
++#define CSL_PWM_1 (0) /** Instance 1 of PWM */
++
++/** @brief Peripheral Instance for PWM */
++#define CSL_PWM_2 (1) /** Instance 2 of PWM */
++
++/** @brief Peripheral Instance for PWM */
++#define CSL_PWM_3 (2) /** Instance 3 of PWM */
++
++/** @brief Peripheral Instance for PLLC */
++#define CSL_PLLC_1 (0) /** Instance 1 of PLLC */
++
++/** @brief Peripheral Instance for PLLC */
++#define CSL_PLLC_2 (1) /** Instance 2 of PLLC */
++
++/** @brief Peripheral Instance for CSL_PWR_SLEEP_CTRL */
++#define CSL_PWR_SLEEP_CTRL (0) /** Instance 1 of PWR_SLEEP_CTRL */
++
++/** @brief Peripheral Instance for SYS_DFT */
++#define CSL_SYS_DFT (0) /** Instance 1 of SYS_DFT*/
++
++/** @brief Peripheral Instance for INTC */
++#define CSL_INTC (0) /** Instance 1 of INTC */
++
++/** @brief Peripheral Instance for IEEE 1394 */
++#define CSL_IEEE1394 (0) /** Instance 1 of IEEE 1394 */
++
++/** @brief Peripheral Instance for USBOTG */
++#define CSL_USBOTG (0) /** Instance 1 of USBOTG */
++
++/** @brief Peripheral Instance for ATA */
++#define CSL_ATA_PRIMARY (0) /** Instance 1 of ATA */
++
++/** @brief Peripheral Instance for ATA */
++#define CSL_ATA_SECONDARY (1) /** Instance 2 of ATA */
++
++/** @brief Peripheral Instance for SPI */
++#define CSL_SPI (0) /** Instance 1 of SPI */
++
++/** @brief Peripheral Instance for GPIO */
++#define CSL_GPIO (0) /** Instance 1 of GPIO */
++
++/** @brief Peripheral Instance for UHPI */
++#define CSL_UHPI (0) /** Instance 1 of UHPI */
++
++/** @brief Peripheral Instance for VPSS_REGS */
++#define CSL_VPSS_REGS (0) /** Instance 1 of VPSS_REGS */
++
++/** @brief Peripheral Instance for EMAC_CTRL */
++#define CSL_EMAC_CTRL (0) /** Instance 1 of EMAC_CTRL */
++
++/** @brief Peripheral Instance for EMAC_WRAP */
++#define CSL_EMAC_WRAP (0) /** Instance 1 of EMAC_WRAP */
++
++/** @brief Peripheral Instance for EMAC_RAM */
++#define CSL_EMAC_RAM (0) /** Instance 1 of EMAC_RAM */
++
++/** @brief Peripheral Instance for MDIO */
++#define CSL_MDIO (0) /** Instance 1 of MDIO */
++
++/** @brief Peripheral Instance for EMIF */
++#define CSL_EMIF (0) /** Instance 1 of EMIF */
++
++/** @brief Peripheral Instance for NAND */
++#define CSL_NAND (0) /** Instance 1 of NAND */
++
++/** @brief Peripheral Instance for MCBSP */
++#define CSL_MCBSP (0) /** Instance 1 of MCBSP */
++
++/** @brief Peripheral Instance for MMCSD */
++#define CSL_MMCSD (0) /** Instance 1 of MMCSD */
++
++/** @brief Peripheral Instance for MS */
++#define CSL_MS (0) /** Instance 1 of MS */
++
++/** @brief Peripheral Instance for DDR */
++#define CSL_DDR (0) /** Instance 1 of DDR */
++
++/** @brief Peripheral Instance for VLYNQ */
++#define CSL_VLYNQ (0) /** Instance 1 of VLYNQ */
++
++/** @brief Peripheral Instance for PMX */
++#define CSL_PMX (0) /** Instance 1 of PMX */
++
++/*****************************************************************************\
++* Peripheral Base Address
++\*****************************************************************************/
++
++#define CSL_UART_1_REGS (0x01C20000)
++#define CSL_UART_2_REGS (0x01C20400)
++#define CSL_UART_3_REGS (0x01C20800)
++#define CSL_I2C_1_REGS (0x01C21000)
++#define CSL_TMR_1_REGS (0x01C21400)
++#define CSL_TMR_2_REGS (0x01C21400)
++#define CSL_TMR_3_REGS (0x01C21800)
++#define CSL_TMR_4_REGS (0x01C21800)
++#define CSL_WDT_1_REGS (0x01C21C00)
++#define CSL_PWM_1_REGS (0x01C22000)
++#define CSL_PWM_2_REGS (0x01C22400)
++#define CSL_PWM_3_REGS (0x01C22800)
++#define CSL_PLLC_1_REGS (0x01C40800)
++#define CSL_PLLC_2_REGS (0x01C40C00)
++#define CSL_PWR_SLEEP_CTRL_1_REGS (0x01C41000)
++#define CSL_SYS_DFT_1_REGS (0x01C42000)
++#define CSL_INTC1_REGS (0x01C48000)
++#define CSL_IEEE1394_1_REGS (0x01C60000)
++#define CSL_USBOTG_1_REGS (0x01C48000)
++#define CSL_ATA_1_REGS (0x01C66000)
++#define CSL_SPI_1_REGS (0x01C66800)
++#define CSL_GPIO_1_REGS (0x01C67000)
++#define CSL_UHPI_1_REGS (0x01C67800)
++#define CSL_VPSS_REGS_1_REGS (0x01C70000)
++#define CSL_EMAC_CTRL_1_REGS (0x01C80000)
++#define CSL_EMAC_WRAP_1_REGS (0x01C81000)
++#define CSL_EMAC_RAM_1_REGS (0x01C82000)
++#define CSL_MDIO_1_REGS (0x01C84000)
++#define CSL_EMIF_1_REGS (0x01E00000)
++#define CSL_NAND_1_REGS (0x01E00000)
++#define CSL_MCBSP_1_REGS (0x01E02000)
++#define CSL_MMCSD_1_REGS (0x01E10000)
++#define CSL_MS_1_REGS (0x01E20000)
++#define CSL_DDR_1_REGS (0x20000000)
++#define CSL_VLYNQ_1_REGS (0x01E01000)
++#define CSL_PMX_1_REGS (0x01DEAD00) // TODO: Get correct base address.
++#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
++#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
++#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
++#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
++#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000)
++
++/* Added for EDMA */
++/** @brief Base address of Channel controller memory mapped registers */
++#define CSL_EDMACC_1_REGS (0x01C00000u)
++#define CSL_EDMA_1 0
++
++
++/*****************************************************************************\
++* Interrupt/Exception Counts
++\*****************************************************************************/
++
++#define _CSL_INTC_EVENTID__INTC0CNT (8) /* ARM exception count */
++#define _CSL_INTC_EVENTID__INTC1CNT (64) /* Level-1 Interrupt count */
++
++/**
++ * @brief Count of the number of interrupt-events
++ */
++#define CSL_INTC_EVENTID_CNT \
++ (_CSL_INTC_EVENTID__INTC0CNT + _CSL_INTC_EVENTID__INTC1CNT)
++
++/*****************************************************************************\
++* Interrupt Event IDs
++\*****************************************************************************/
++
++#define _CSL_INTC_EVENTID__SPURIOUS (0)
++#define _CSL_INTC_EVENTID__INTC1START (0)
++
++#define CSL_INTC_EVENTID_VD0 (_CSL_INTC_EVENTID__INTC1START + 0) /**< VPSS - CCDC */
++#define CSL_INTC_EVENTID_VD1 (_CSL_INTC_EVENTID__INTC1START + 1) /**< VPSS - CCDC */
++#define CSL_INTC_EVENTID_VD2 (_CSL_INTC_EVENTID__INTC1START + 2) /**< VPSS - CCDC */
++#define CSL_INTC_EVENTID_HIST (_CSL_INTC_EVENTID__INTC1START + 3) /**< VPSS - Histogram */
++#define CSL_INTC_EVENTID_H3A (_CSL_INTC_EVENTID__INTC1START + 4) /**< VPSS - AE/AWB/AF */
++#define CSL_INTC_EVENTID_PRVU (_CSL_INTC_EVENTID__INTC1START + 5) /**< VPSS - Previewer */
++#define CSL_INTC_EVENTID_RSZ (_CSL_INTC_EVENTID__INTC1START + 6) /**< VPSS - Resizer */
++#define CSL_INTC_EVENTID_VFOC (_CSL_INTC_EVENTID__INTC1START + 7) /**< VPSS - Focus */
++#define CSL_INTC_EVENTID_VENC (_CSL_INTC_EVENTID__INTC1START + 8) /**< VPSS - VPBE */
++#define CSL_INTC_EVENTID_ASQ (_CSL_INTC_EVENTID__INTC1START + 9) /**< IMCOP - Sqr */
++#define CSL_INTC_EVENTID_IMX (_CSL_INTC_EVENTID__INTC1START + 10) /**< IMCOP - iMX */
++#define CSL_INTC_EVENTID_VLCD (_CSL_INTC_EVENTID__INTC1START + 11) /**< IMCOP - VLCD */
++#define CSL_INTC_EVENTID_USBC (_CSL_INTC_EVENTID__INTC1START + 12) /**< USB OTG Collector*/
++#define CSL_INTC_EVENTID_EMAC (_CSL_INTC_EVENTID__INTC1START + 13) /**< CPGMAC Wrapper */
++#define CSL_INTC_EVENTID_1394 (_CSL_INTC_EVENTID__INTC1START + 14) /**< IEEE1394 */
++#define CSL_INTC_EVENTID_1394WK (_CSL_INTC_EVENTID__INTC1START + 15) /**< IEEE1394 */
++#define CSL_INTC_EVENTID_CC0 (_CSL_INTC_EVENTID__INTC1START + 16) /**< 3PCC Region 0 */
++#define CSL_INTC_EVENTID_CCERR (_CSL_INTC_EVENTID__INTC1START + 17) /**< 3PCC Error */
++#define CSL_INTC_EVENTID_TCERR0 (_CSL_INTC_EVENTID__INTC1START + 18) /**< 3PTC0 Error */
++#define CSL_INTC_EVENTID_TCERR1 (_CSL_INTC_EVENTID__INTC1START + 19) /**< 3PTC1 Error */
++#define CSL_INTC_EVENTID_PSCINT (_CSL_INTC_EVENTID__INTC1START + 20) /**< PSC - ALLINT */
++#define CSL_INTC_EVENTID_RSVD21 (_CSL_INTC_EVENTID__INTC1START + 21) /**< Reserved */
++#define CSL_INTC_EVENTID_ATA (_CSL_INTC_EVENTID__INTC1START + 22) /**< ATA/IDE */
++#define CSL_INTC_EVENTID_HPIINT (_CSL_INTC_EVENTID__INTC1START + 23) /**< UHPI */
++#define CSL_INTC_EVENTID_MBX (_CSL_INTC_EVENTID__INTC1START + 24) /**< McBSP */
++#define CSL_INTC_EVENTID_MBR (_CSL_INTC_EVENTID__INTC1START + 25) /**< McBSP */
++#define CSL_INTC_EVENTID_MMCSD (_CSL_INTC_EVENTID__INTC1START + 26) /**< MMC/SD */
++#define CSL_INTC_EVENTID_SDIO (_CSL_INTC_EVENTID__INTC1START + 27) /**< MMC/SD */
++#define CSL_INTC_EVENTID_MS (_CSL_INTC_EVENTID__INTC1START + 28) /**< Memory Stick */
++#define CSL_INTC_EVENTID_DDR (_CSL_INTC_EVENTID__INTC1START + 29) /**< DDR EMIF */
++#define CSL_INTC_EVENTID_EMIF (_CSL_INTC_EVENTID__INTC1START + 30) /**< Async EMIF */
++#define CSL_INTC_EVENTID_VLQ (_CSL_INTC_EVENTID__INTC1START + 31) /**< VLYNQ */
++#define CSL_INTC_EVENTID_TIMER0INT12 (_CSL_INTC_EVENTID__INTC1START + 32) /**< Timer 0 - TINT12 */
++#define CSL_INTC_EVENTID_TIMER0INT34 (_CSL_INTC_EVENTID__INTC1START + 33) /**< Timer 0 - TINT34 */
++#define CSL_INTC_EVENTID_TIMER1INT12 (_CSL_INTC_EVENTID__INTC1START + 34) /**< Timer 1 - TINT12 */
++#define CSL_INTC_EVENTID_TIMER1INT34 (_CSL_INTC_EVENTID__INTC1START + 35) /**< Timer 2 - TINT34 */
++#define CSL_INTC_EVENTID_PWM0 (_CSL_INTC_EVENTID__INTC1START + 36) /**< PWM0 */
++#define CSL_INTC_EVENTID_PWM1 (_CSL_INTC_EVENTID__INTC1START + 37) /**< PWM1 */
++#define CSL_INTC_EVENTID_PWM2 (_CSL_INTC_EVENTID__INTC1START + 38) /**< PWM2 */
++#define CSL_INTC_EVENTID_I2C (_CSL_INTC_EVENTID__INTC1START + 39) /**< I2C */
++#define CSL_INTC_EVENTID_UART0 (_CSL_INTC_EVENTID__INTC1START + 40) /**< UART0 */
++#define CSL_INTC_EVENTID_UART1 (_CSL_INTC_EVENTID__INTC1START + 41) /**< UART1 */
++#define CSL_INTC_EVENTID_UART2 (_CSL_INTC_EVENTID__INTC1START + 42) /**< UART2 */
++#define CSL_INTC_EVENTID_SPI0 (_CSL_INTC_EVENTID__INTC1START + 43) /**< SPI */
++#define CSL_INTC_EVENTID_SPI1 (_CSL_INTC_EVENTID__INTC1START + 44) /**< SPI */
++#define CSL_INTC_EVENTID_WDT (_CSL_INTC_EVENTID__INTC1START + 45) /**< Timer 3 - TINT12 */
++#define CSL_INTC_EVENTID_DSP0 (_CSL_INTC_EVENTID__INTC1START + 46) /**< DSP Controller */
++#define CSL_INTC_EVENTID_DSP1 (_CSL_INTC_EVENTID__INTC1START + 47) /**< DSP Controller */
++#define CSL_INTC_EVENTID_GPIO0 (_CSL_INTC_EVENTID__INTC1START + 48) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO1 (_CSL_INTC_EVENTID__INTC1START + 49) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO2 (_CSL_INTC_EVENTID__INTC1START + 50) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO3 (_CSL_INTC_EVENTID__INTC1START + 51) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO4 (_CSL_INTC_EVENTID__INTC1START + 52) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO5 (_CSL_INTC_EVENTID__INTC1START + 53) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO6 (_CSL_INTC_EVENTID__INTC1START + 54) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIO7 (_CSL_INTC_EVENTID__INTC1START + 55) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIOBNK0 (_CSL_INTC_EVENTID__INTC1START + 56) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIOBNK1 (_CSL_INTC_EVENTID__INTC1START + 57) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIOBNK2 (_CSL_INTC_EVENTID__INTC1START + 58) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIOBNK3 (_CSL_INTC_EVENTID__INTC1START + 59) /**< GPIO */
++#define CSL_INTC_EVENTID_GPIOBNK4 (_CSL_INTC_EVENTID__INTC1START + 60) /**< GPIO */
++#define CSL_INTC_EVENTID_COMMTX (_CSL_INTC_EVENTID__INTC1START + 61) /**< ARMSS */
++#define CSL_INTC_EVENTID_COMMRX (_CSL_INTC_EVENTID__INTC1START + 62) /**< ARMSS */
++#define CSL_INTC_EVENTID_EMU (_CSL_INTC_EVENTID__INTC1START + 63) /**< E2ICE */
++
++#define _CSL_INTC_EVENTID__INTC1END (_CSL_INTC_EVENTID__INTC1START + _CSL_INTC_EVENTID__INTC1CNT - 1)
++
++
++#define _CSL_INTC_EVENTID__INTC0START (_CSL_INTC_EVENTID__INTC1END + 1)
++
++#define CSL_INTC_EVENTID_RESET (_CSL_INTC_EVENTID__INTC0START + 0) /**< the RESET exception vector */
++#define CSL_INTC_EVENTID_UNDEF (_CSL_INTC_EVENTID__INTC0START + 1) /**< the UNDEF exception vector */
++#define CSL_INTC_EVENTID_SWI (_CSL_INTC_EVENTID__INTC0START + 2) /**< the SWI exception vector */
++#define CSL_INTC_EVENTID_PREABT (_CSL_INTC_EVENTID__INTC0START + 3) /**< the PREABT exception vector */
++#define CSL_INTC_EVENTID_DATABT (_CSL_INTC_EVENTID__INTC0START + 4) /**< the DATABT exception vector */
++#define CSL_INTC_EVENTID_IRQ (_CSL_INTC_EVENTID__INTC0START + 6) /**< the IRQ exception vector */
++#define CSL_INTC_EVENTID_FIQ (_CSL_INTC_EVENTID__INTC0START + 7) /**< the FIQ exception vector */
++
++#define _CSL_INTC_EVENTID__INTC0END (_CSL_INTC_EVENTID__INTC0START + _CSL_INTC_EVENTID__INTC0CNT - 1)
++
++#define CSL_INTC_EVENTID_INVALID (-1) /**< Invalid Event-ID */
++
++#endif
+diff -Nurd u-boot-1.2.0/board/davinci/timer.c u-boot-1.2.0-leopard/board/davinci/timer.c
+--- u-boot-1.2.0/board/davinci/timer.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/timer.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,73 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++
++#include "soc.h"
++#include "timer.h"
++
++/* Use Timer 3&4 (Timer 2) */
++#define TIMER_BASE_ADDR CSL_TMR_1_REGS
++
++davinci_timer_reg *davinci_timer = (davinci_timer_reg *) TIMER_BASE_ADDR;
++
++/* Timer Initialize */
++void inittimer(void)
++{
++ /* disable Timer 1 & 2 timers */
++ davinci_timer->tcr = 0;
++
++ /* Set timers to unchained dual 32 bit timers, Unreset timer34 */
++ davinci_timer->tgcr = 0x0;
++ davinci_timer->tgcr = 0x6;
++
++ /* Program the timer12 counter register - set the prd12 for right count */
++ davinci_timer->tim34 = 0;
++
++ /* The timer is programmed to expire after 0xFFFFFFFF ticks */
++ davinci_timer->prd34 = 0xFFFFFFFF;
++
++ /* Enable timer34 */
++ davinci_timer->tcr = (0x80 << 16); /* Timer34 continously enabled, Timer12 disabled */
++}
++
++/************************************************************
++********************** Reset Processor **********************
++************************************************************/
++#define WDT_BASE_ADDR CSL_WDT_1_REGS
++
++
++void reset_processor(void)
++{
++ davinci_timer_reg *davinci_wdt = (davinci_timer_reg *) WDT_BASE_ADDR;
++ davinci_wdt->tgcr = 0x00000008;
++ davinci_wdt->tgcr |= 0x00000003;
++ davinci_wdt->tim12 = 0x00000000;
++ davinci_wdt->tim34 = 0x00000000;
++ davinci_wdt->prd12 = 0x00000000;
++ davinci_wdt->prd34 = 0x00000000;
++ davinci_wdt->tcr |= 0x00000040;
++ davinci_wdt->wdtcr |= 0x00004000;
++ davinci_wdt->wdtcr = 0xA5C64000;
++ davinci_wdt->wdtcr = 0xDA7E4000;
++}
+diff -Nurd u-boot-1.2.0/board/davinci/timer.h u-boot-1.2.0-leopard/board/davinci/timer.h
+--- u-boot-1.2.0/board/davinci/timer.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/timer.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,51 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Modifications:
++ * ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#ifndef __TIMER_H__
++#define __TIMER_H__
++
++typedef volatile struct davinci_timer_reg_t
++{
++ unsigned int pid12; /* 0x0 */
++ unsigned int emumgt_clksped;/* 0x4 */
++ unsigned int gpint_en; /* 0x8 */
++ unsigned int gpdir_dat; /* 0xC */
++ unsigned int tim12; /* 0x10 */
++ unsigned int tim34; /* 0x14 */
++ unsigned int prd12; /* 0x18 */
++ unsigned int prd34; /* 0x1C */
++ unsigned int tcr; /* 0x20 */
++ unsigned int tgcr; /* 0x24 */
++ unsigned int wdtcr; /* 0x28 */
++ unsigned int tlgc; /* 0x2C */
++ unsigned int tlmr; /* 0x30 */
++} davinci_timer_reg;
++
++#endif /* __TIMER_H__ */
++
+diff -Nurd u-boot-1.2.0/board/davinci/types.h u-boot-1.2.0-leopard/board/davinci/types.h
+--- u-boot-1.2.0/board/davinci/types.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/types.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,46 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _TYPESH_
++#define _TYPESH_
++
++typedef unsigned long ULONG;
++typedef unsigned short USHORT;
++typedef unsigned long BOOL;
++typedef unsigned int WORD;
++typedef char CHAR;
++typedef unsigned char BYTE, *LPBYTE, UCHAR, *PUCHAR, PBYTE;
++
++#define FALSE 0
++#define TRUE 1
++
++#define NULL 0
++
++typedef unsigned short int Hwd;
++typedef volatile unsigned short int vHwd;
++typedef unsigned short int * Hwdptr;
++typedef volatile unsigned short int * vHwdptr;
++//typedef volatile unsigned int * vHwdptr;
++
++
++#endif
++
+diff -Nurd u-boot-1.2.0/board/davinci/u-boot.lds u-boot-1.2.0-leopard/board/davinci/u-boot.lds
+--- u-boot-1.2.0/board/davinci/u-boot.lds 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/davinci/u-boot.lds 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,52 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm926ejs/start.o (.text)
++ *(.text)
++ }
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++ . = ALIGN(4);
++ .data : { *(.data) }
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -Nurd u-boot-1.2.0/board/dm355_evm/Makefile u-boot-1.2.0-leopard/board/dm355_evm/Makefile
+--- u-boot-1.2.0/board/dm355_evm/Makefile 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/Makefile 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := dm355_evm.o flash.o nand.o timer.o
++SOBJS := lowlevel_init.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -Nurd u-boot-1.2.0/board/dm355_evm/config.mk u-boot-1.2.0-leopard/board/dm355_evm/config.mk
+--- u-boot-1.2.0/board/dm355_evm/config.mk 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/config.mk 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,25 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++#
++# (C) Copyright 2003
++# Texas Instruments, <www.ti.com>
++# Swaminathan <swami.iyer@ti.com>
++#
++# Davinci EVM board (ARM925EJS) cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# Davinci EVM has 1 bank of 256 MB DDR RAM
++# Physical Address:
++# 8000'0000 to 9000'0000
++#
++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
++# (mem base + reserved)
++#
++# we load ourself to 8100 '0000
++#
++#
++
++#Provide a atleast 16MB spacing between us and the Linux Kernel image
++TEXT_BASE = 0x81080000
+diff -Nurd u-boot-1.2.0/board/dm355_evm/dm355_evm.c u-boot-1.2.0-leopard/board/dm355_evm/dm355_evm.c
+--- u-boot-1.2.0/board/dm355_evm/dm355_evm.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/dm355_evm.c 2008-01-05 03:44:03.000000000 -0300
+@@ -0,0 +1,598 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++
++#define inw(a) __raw_readw(a)
++#define outw(a,v) __raw_writew(a,v)
++
++
++#define PLL1_PLLM *(volatile unsigned int *)0x01c40910
++#define PLL2_PLLM *(volatile unsigned int *)0x01c40D10
++#define PLL2_DIV2 *(volatile unsigned char *)0x01c40D1C
++#define PLL2_PREDIV *(volatile unsigned int *)0x01C40D14
++#define PLL1_PLLDIV3 *(volatile unsigned int *)0x01C40920
++#define PLL1_POSTDIV *(volatile unsigned int *)0x01C40928
++#define PLL1_PLLDIV4 *(volatile unsigned int *)0x01C40960
++#define SYSTEM_MISC *(volatile unsigned int *)0x01C40038
++#define MACH_DM350_EVM 1381
++
++void davinci_psc_all_enable(void);
++short MSP430_getReg( short reg, unsigned short *regval );
++unsigned int UARTSendInt(unsigned int value);
++
++/*******************************************
++ Routine: delay
++ Description: Delay function
++*******************************************/
++static inline void delay (unsigned long loops)
++{
++__asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*******************************************
++ Routine: board_init
++ Description: Board Initialization routine
++*******************************************/
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* arch number of DaVinci DVDP-Board */
++ gd->bd->bi_arch_number = MACH_DM350_EVM;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
++ /* Configure MUX settings */
++
++ /* Power on required peripherals
++ davinci_psc_all_enable(); */
++#if 0
++ /* this speeds up your boot a quite a bit. However to make it
++ * work, you need make sure your kernel startup flush bug is fixed.
++ * ... rkw ...
++ */
++ icache_enable ();
++
++#endif
++ inittimer ();
++
++ return 0;
++}
++
++/* PSC Domains */
++
++#define LPSC_VPSSMSTR 0 // VPSS Master LPSC
++#define LPSC_VPSSSLV 1 // VPSS Slave LPSC
++#define LPSC_TPCC 2 // TPCC LPSC
++#define LPSC_TPTC0 3 // TPTC0 LPSC
++#define LPSC_TPTC1 4 // TPTC1 LPSC
++#define PAL_SYS_CLK_MODULE_SPI1 6 /**<SPI1 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_MMCSD1 7 /**<MMCSD1 LPSC Module No*/
++#define LPSC_USB 9 // USB LPSC
++#define PAL_SYS_CLK_MODULE_PWM3 10 /**<PWM3 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_SPI2 11 /**<SPI2 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_RTO 12 /**<TIMER2 LPSC Module No*/
++#define LPSC_DDR_EMIF 13 // DDR_EMIF LPSC
++#define LPSC_AEMIF 14 // AEMIF LPSC
++#define LPSC_MMC_SD 15 // MMC_SD LPSC
++#define LPSC_MEMSTICK 16 // MEMSTICK LPSC
++#define PAL_SYS_CLK_MODULE_ASP 17 /**<AEMIF LPSC Module No*/
++#define LPSC_I2C 18 // I2C LPSC
++#define LPSC_UART0 19 // UART0 LPSC
++#define LPSC_UART1 20 // UART1 LPSC
++#define LPSC_UART2 21 // UART2 LPSC
++#define LPSC_SPI 22 // SPI LPSC
++#define LPSC_PWM0 23 // PWM0 LPSC
++#define LPSC_PWM1 24 // PWM1 LPSC
++#define LPSC_PWM2 25 // PWM2 LPSC
++#define LPSC_GPIO 26 // GPIO LPSC
++#define LPSC_TIMER0 27 // TIMER0 LPSC
++#define LPSC_TIMER1 28 // TIMER1 LPSC
++#define LPSC_TIMER2 29 // TIMER2 LPSC
++#define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM LPSC
++#define LPSC_ARM 31 // ARM LPSC
++#define PAL_SYS_CLK_MODULE_VPSS_DAC 40 /**<VPSS DAC LPSC Module No*/
++
++#define EPCPR *( unsigned int* )( 0x01C41070 )
++#define PTCMD *( unsigned int* )( 0x01C41120 )
++#define PTSTAT *( unsigned int* )( 0x01C41128 )
++#define PDSTAT *( unsigned int* )( 0x01C41200 )
++#define PDSTAT1 *( unsigned int* )( 0x01C41204 )
++#define PDCTL *( unsigned int* )( 0x01C41300 )
++#define PDCTL1 *( unsigned int* )( 0x01C41304 )
++#define VBPR *( unsigned int* )( 0x20000020 )
++
++/**************************************
++ Routine: board_setup_psc_on
++ Description: Enable a PSC domain
++**************************************/
++void board_setup_psc_on( unsigned int domain, unsigned int id )
++{
++ volatile unsigned int* mdstat = ( unsigned int* )( 0x01C41800 + 4 * id );
++ volatile unsigned int* mdctl = ( unsigned int* )( 0x01C41A00 + 4 * id );
++
++ *mdctl |= 0x00000003; // Set PowerDomain to turn on
++
++ if ( ( PDSTAT & 0x00000001 ) == 0 )
++ {
++ PDCTL1 |= 0x1;
++ PTCMD = ( 1 << domain );
++ while ( ( ( ( EPCPR >> domain ) & 1 ) == 0 ) );
++
++ PDCTL1 |= 0x100 ;
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++ else
++ {
++ PTCMD = ( 1<<domain );
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++
++ while( ! ( ( *mdstat & 0x0000001F ) == 0x3 ) );
++}
++
++/**************************************
++ Routine: davinci_psc_all_enable
++ Description: Enable all PSC domains
++**************************************/
++void davinci_psc_all_enable(void)
++{
++#define PSC_ADDR 0x01C41000
++#define PTCMD (PSC_ADDR+0x120)
++#define PTSTAT (PSC_ADDR+0x128)
++
++ unsigned int alwaysOnPdNum = 0, dspPdNum = 1, i;
++
++ /* This function turns on all clocks in the ALWAYSON and DSP Power
++ * Domains. Note this function assumes that the Power Domains are
++ * already on.
++ */
++#if 0
++ /* Write ENABLE (0x3) to all 41 MDCTL[i].NEXT bit fields. */
++ for( i = 0; i < 41; i++){
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) =
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) | 0x3;
++ }
++
++ /* For special workaround: Set MDCTL[i].EMURSTIE to 0x1 for all of the
++ * following Modules. VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) | 0x203;*/
++#endif
++
++ /* For special workaround: Clear MDCTL[i].EMURSTIE to 0x0 for all of the following Modules.
++ * VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*19))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*20) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*20))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*21) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*21))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*18) = *(unsigned int*) (PSC_ADDR+0xA00+4*18) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*28) = *(unsigned int*) (PSC_ADDR+0xA00+4*28) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) & 0x003;*/
++
++ /* Set PTCMD.GO0 to 0x1 to initiate the state transtion for Modules in
++ * the ALWAYSON Power Domain
++ */
++ *(volatile unsigned int*) PTCMD = (1<<alwaysOnPdNum);
++
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! (((*(volatile unsigned int*) PTSTAT >> alwaysOnPdNum) & 0x00000001) == 0));
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*19)& 0x0000001F ) == 0x3));
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*20)& 0x0000001F ) == 0x3));
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*21)& 0x0000001F ) == 0x3));
++ /* Bringup UART out of reset here since NS16650 code that we are using from uBoot
++ * will not do it
++ */
++
++#define UART0PWREMU_MGMT 0x01c20030
++ *(volatile unsigned int*) UART0PWREMU_MGMT |= 0x00008001;
++
++
++#define UART1PWREMU_MGMT 0x01c20430
++ *(volatile unsigned int*) UART1PWREMU_MGMT |= 0x00008001;
++
++#define UART2PWREMU_MGMT 0x01e06030
++ *(volatile unsigned int*) UART2PWREMU_MGMT |= 0x00008001;
++
++#define PINMUX3 0x01C4000C
++ /* Enable UART1 MUX Lines */
++ *(volatile unsigned int *)PINMUX3 |= 0x00600000;
++
++ /* Enable UART2 MUX Lines */
++ *(volatile unsigned int *)PINMUX3 |= 0x0000AA00;
++
++ /* Set the Bus Priority Register to appropriate value */
++ VBPR = 0x20;
++}
++
++/******************************
++ Routine: misc_init_r
++ Description: Misc. init
++******************************/
++int misc_init_r (void)
++{
++ char temp[20], *env=0;
++ char rtcdata[10] = { 4, 1, 0, 0, 0, 0, 0, 0, 0, 0};
++ int clk = 0;
++ unsigned short regval=0 ;
++
++ clk = ((PLL2_PLLM + 1) * 24) / ((PLL2_PREDIV & 0x1F) + 1);
++
++ printf ("ARM Clock :- %dMHz\n", ( ( ((PLL1_PLLM+1)*24 )/(2*(7+1)*((SYSTEM_MISC & 0x2)?2:1 )))) );
++ printf ("DDR Clock :- %dMHz\n", (clk/2));
++
++ if ( !(env=getenv("videostd")) || !strcmp(env,"ntsc") || !strcmp(env, "pal") )
++ {
++ MSP430_getReg( 0x04, &regval);
++ //printf("regval is %x\n",regval);
++ setenv ("videostd", ((regval & 0x10)?"ntsc":"pal"));
++ }
++
++ return (0);
++}
++
++/******************************
++ Routine: dram_init
++ Description: Memory Info
++******************************/
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++
++typedef int Bool;
++#define TRUE ((Bool) 1)
++#define FALSE ((Bool) 0)
++
++
++typedef int Int;
++typedef unsigned int Uns; /* deprecated type */
++typedef char Char;
++typedef char * String;
++typedef void * Ptr;
++
++/* unsigned quantities */
++typedef unsigned int Uint32;
++typedef unsigned short Uint16;
++typedef unsigned char Uint8;
++
++/* signed quantities */
++typedef int Int32;
++typedef short Int16;
++typedef char Int8;
++
++/* volatile unsigned quantities */
++typedef volatile unsigned int VUint32;
++typedef volatile unsigned short VUint16;
++typedef volatile unsigned char VUint8;
++
++/* volatile signed quantities */
++typedef volatile int VInt32;
++typedef volatile short VInt16;
++typedef volatile char VInt8;
++
++typedef struct _uart_regs
++{
++ VUint32 RBR;
++ VUint32 IER;
++ VUint32 IIR;
++ VUint32 LCR;
++ VUint32 MCR;
++ VUint32 LSR;
++ VUint32 MSR;
++ VUint32 SCR;
++ VUint8 DLL;
++ VUint8 RSVDO[3];
++ VUint8 DLH;
++ VUint8 RSVD1[3];
++ VUint32 PID1;
++ VUint32 PID2;
++ VUint32 PWREMU_MGNT;
++} uartRegs;
++
++#define THR RBR
++#define FCR IIR
++
++#define UART0 ((uartRegs*) 0x01C20000)
++
++#define MAXSTRLEN 256
++#define E_PASS 0x00000000u
++#define E_FAIL 0x00000001u
++#define E_TIMEOUT 0x00000002u
++
++
++
++// Send specified number of bytes
++
++Int32 GetStringLen(Uint8* seq)
++{
++ Int32 i = 0;
++ while ((seq[i] != 0) && (i<MAXSTRLEN)){ i++;}
++ if (i == MAXSTRLEN)
++ return -1;
++ else
++ return i;
++}
++
++Uint32 UARTSendData(Uint8* seq, Bool includeNull)
++{
++ Uint32 status = 0;
++ Int32 i,numBytes;
++ Uint32 timerStatus = 0x1000000;
++
++ numBytes = includeNull?(GetStringLen(seq)+1):(GetStringLen(seq));
++
++ for(i=0;i<numBytes;i++) {
++ /* Enable Timer one time */
++ //TIMER0Start();
++ do{
++ status = (UART0->LSR)&(0x60);
++ //timerStatus = TIMER0Status();
++ timerStatus--;
++ } while (!status && timerStatus);
++
++ if(timerStatus == 0)
++ return E_TIMEOUT;
++
++ // Send byte
++ (UART0->THR) = seq[i];
++ }
++ return E_PASS;
++}
++
++Uint32 UARTSendInt(Uint32 value)
++{
++ char seq[9];
++ Uint32 i,shift,temp;
++
++ for( i = 0; i < 8; i++)
++ {
++ shift = ((7-i)*4);
++ temp = ((value>>shift) & (0x0000000F));
++ if (temp > 9)
++ {
++ temp = temp + 7;
++ }
++ seq[i] = temp + 48;
++ seq[i] = temp + 48;
++ }
++ seq[8] = 0;
++ return UARTSendData(seq, FALSE);
++}
++
++#define I2C_BASE 0x01C21000
++#define I2C_OA (I2C_BASE + 0x00)
++#define I2C_IE (I2C_BASE + 0x04)
++#define I2C_STAT (I2C_BASE + 0x08)
++#define I2C_SCLL (I2C_BASE + 0x0c)
++#define I2C_SCLH (I2C_BASE + 0x10)
++#define I2C_CNT (I2C_BASE + 0x14)
++#define I2C_DRR (I2C_BASE + 0x18)
++#define I2C_SA (I2C_BASE + 0x1c)
++#define I2C_DXR (I2C_BASE + 0x20)
++#define I2C_CON (I2C_BASE + 0x24)
++#define I2C_IV (I2C_BASE + 0x28)
++#define I2C_PSC (I2C_BASE + 0x30)
++
++#define I2C_CON_EN (1 << 5) /* I2C module enable */
++#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
++#define I2C_CON_MST (1 << 10) /* Master/slave mode */
++#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
++#define I2C_CON_XA (1 << 8) /* Expand address */
++#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
++#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
++
++#define I2C_STAT_BB (1 << 12) /* Bus busy */
++#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
++#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
++#define I2C_STAT_AAS (1 << 9) /* Address as slave */
++#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
++#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
++#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
++#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
++#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
++#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
++
++static Int16 I2C_init(void );
++static Int16 I2C_close(void );
++static Int16 I2C_reset( void);
++static Int16 I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len );
++static Int16 I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len );
++Int32 i2c_timeout = 0x10000;
++
++Int16 MSP430_getReg( Int16 reg, Uint16 *regval )
++{
++ volatile Int16 retcode;
++ Uint8 msg[2];
++
++ I2C_reset();
++ udelay(10000);
++ /* Send Msg */
++ msg[0] = (Uint8)(reg & 0xff);
++ if ( retcode = I2C_write( 0x25, msg, 1) )
++ {
++ return retcode;
++ }
++
++ if ( retcode = I2C_read( 0x25, msg, 1 ) )
++ {
++ return retcode;
++ }
++
++ *regval = msg[0];
++
++ /* Wait 1 msec */
++ udelay( 1000 );
++
++ return 0;
++}
++
++static Int16 I2C_init( )
++{
++ outw(0, I2C_CON); // Reset I2C
++ outw(26,I2C_PSC); // Config prescaler for 27MHz
++ outw(20,I2C_SCLL); // Config clk LOW for 20kHz
++ outw(20,I2C_SCLH); // Config clk HIGH for 20kHz
++ outw(inw(I2C_CON) | I2C_CON_EN,I2C_CON); // Release I2C from reset
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ *
++ * *
++ * _I2C_close( ) *
++ * *
++ * ------------------------------------------------------------------------ */
++static Int16 I2C_close( )
++{
++ outw(0,I2C_CON); // Reset I2C
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ *
++ * *
++ * _I2C_reset( ) *
++ * *
++ * ------------------------------------------------------------------------ */
++static Int16 I2C_reset( )
++{
++ I2C_close( );
++ I2C_init( );
++ return 0;
++}
++
++static Int16 I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len )
++{
++ Int32 timeout, i, status;
++
++ outw(len, I2C_CNT); // Set length
++ outw(i2c_addr, I2C_SA); // Set I2C slave address
++ outw(0x2000 // Set for Master Write
++ | 0x0200
++ | 0x0400
++ | I2C_CON_EN
++ | 0x4000, I2C_CON );
++
++ udelay( 10 ); // Short delay
++
++ for ( i = 0 ; i < len ; i++ )
++ {
++ outw( data[i],I2C_DXR);; // Write
++
++ timeout = i2c_timeout;
++ do
++ {
++ if ( timeout-- < 0 )
++ {
++ I2C_reset( );
++ return -1;
++ }
++ } while ( ( inw(I2C_STAT) & I2C_STAT_XRDY ) == 0 );// Wait for Tx Ready
++ }
++
++ outw( inw(I2C_CON) | 0x0800, I2C_CON); // Generate STOP
++
++ return 0;
++
++}
++static Int16 I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len )
++{
++ Int32 timeout, i, status;
++
++ outw( len, I2C_CNT); // Set length
++ outw( i2c_addr, I2C_SA); // Set I2C slave address
++ outw( 0x2000 // Set for Master Read
++ | 0x0400
++ | I2C_CON_EN
++ | 0x4000,I2C_CON);
++
++ udelay( 10 ); // Short delay
++
++ for ( i = 0 ; i < len ; i++ )
++ {
++ timeout = i2c_timeout;
++
++ /* Wait for Rx Ready */
++ do
++ {
++ if ( timeout-- < 0 )
++ {
++ I2C_reset( );
++ return -1;
++ }
++ } while ( ( inw(I2C_STAT) & I2C_STAT_RRDY ) == 0 );// Wait for Rx Ready
++
++ data[i] = inw(I2C_DRR); // Read
++ }
++
++ //I2C_ICMDR |= ICMDR_STP; // Generate STOP
++ return 0;
++}
++
+diff -Nurd u-boot-1.2.0/board/dm355_evm/flash.c u-boot-1.2.0-leopard/board/dm355_evm/flash.c
+--- u-boot-1.2.0/board/dm355_evm/flash.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/flash.c 2008-01-05 03:44:03.000000000 -0300
+@@ -0,0 +1,758 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * (C) Copyright 2003
++ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include "types.h"
++
++#if !defined(CFG_NO_FLASH)
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++#if defined (CFG_DM355_EVM)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define EVMDM355_FLASH_CTL555 *(u16*)( CFG_FLASH_BASE + (0x555 << 1))
++ #define EVMDM355_FLASH_CTL2AA *(u16*)( CFG_FLASH_BASE + (0x2aa << 1))
++ #define EVMDM355_CPLD *(u16*)( CFG_FLASH_BASE + (0x1c000 << 0) )
++ #define EVMDM355_CPLD_MASK 0x3FC000
++
++ #define FLASH_CYCLE1 (0x0555)
++ #define FLASH_CYCLE2 (0x02aa)
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++ #define SWAP(x) __swab16(x)
++#endif
++
++#if defined (CONFIG_TOP860)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++#endif
++
++#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 (0x0aaa << 1)
++ #define FLASH_CYCLE2 (0x0555 << 1)
++ #define FLASH_ID1 0
++ #define FLASH_ID2 2
++ #define FLASH_ID3 0x1c
++ #define FLASH_ID4 0x1E
++#endif
++
++#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0E
++ #define FLASH_ID4 0x0F
++#endif
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size(FPWV *addr, flash_info_t *info);
++static void flash_reset(flash_info_t *info);
++static int write_word(flash_info_t *info, FPWV *dest, FPW data);
++static flash_info_t *flash_get_info(ulong base);
++void inline spin_wheel (void);
++
++/*-----------------------------------------------------------------------
++ * flash_init()
++ *
++ * sets up flash_info and returns size of FLASH (bytes)
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i = 0;
++ u16 mfgid, devid;
++ extern void flash_preinit(void);
++ extern void flash_afterinit(uint, ulong, ulong);
++ ulong flashbase = CFG_FLASH_BASE;
++
++#if 0
++ EVMDM355_CPLD = 0;
++ EVMDM355_FLASH_CTL555 = 0xf0;
++
++ EVMDM355_FLASH_CTL555 = 0xaa;
++ EVMDM355_FLASH_CTL2AA = 0x55;
++ EVMDM355_FLASH_CTL555 = 0x90;
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++ mgfid = *((u16*)CFG_FLASH_BASE);
++ devid = *((u16*)CFG_FLASH_BASE +1);
++
++ *((u8 *)CFG_FLASH_BASE) = 0xf0;
++
++ printf("MFGID %x \n", mfgid);
++ printf("DEVIU %x \n", devid);
++ if ((mfgid != 0x0001) || (devid != 0x227e))
++ return 1;
++#endif
++
++ /*flash_preinit();*/
++
++ /* There is only ONE FLASH device */
++ memset(&flash_info[i], 0, sizeof(flash_info_t));
++ flash_info[i].size =
++ flash_get_size((FPW *)flashbase, &flash_info[i]);
++ size += flash_info[i].size;
++
++#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
++ /* monitor protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_MONITOR_BASE,
++ CFG_MONITOR_BASE+monitor_flash_len-1,
++ flash_get_info(CFG_MONITOR_BASE));
++#endif
++
++#ifdef CFG_ENV_IS_IN_FLASH
++ /* ENV protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
++ flash_get_info(CFG_ENV_ADDR));
++#endif
++
++
++ /*flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);*/
++ return size ? size : 1;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_reset(flash_info_t *info)
++{
++ FPWV *base = (FPWV *)(info->start[0]);
++
++ /* Put FLASH back in read mode */
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *base = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++
++void flash_reset_sector(flash_info_t *info, ULONG addr)
++{
++ // Reset Flash to be in Read Array Mode
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *(FPWV *)addr = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *(FPWV *)addr = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size &&
++ info->start[0] <= base && base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++ uchar *boottype;
++ uchar *bootletter;
++ uchar *fmt;
++ uchar botbootletter[] = "B";
++ uchar topbootletter[] = "T";
++ uchar botboottype[] = "bottom boot sector";
++ uchar topboottype[] = "top boot sector";
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_AMD: printf ("MY AMD "); break;
++#if 0
++ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
++ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
++ case FLASH_MAN_SST: printf ("SST "); break;
++ case FLASH_MAN_STM: printf ("STM "); break;
++#endif
++ case FLASH_MAN_INTEL: printf ("INTEL "); break;
++ default: printf ("Unknown Vendor "); break;
++ }
++
++ /* check for top or bottom boot, if it applies */
++ if (info->flash_id & FLASH_BTYPE) {
++ boottype = botboottype;
++ bootletter = botbootletter;
++ }
++ else {
++ boottype = topboottype;
++ bootletter = topbootletter;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160T:
++ case FLASH_AM160B:
++ fmt = "29LV160%s (16 Mbit, %s)\n";
++ break;
++ case FLASH_AMLV640U:
++ fmt = "29LV640M (64 Mbit)\n";
++ break;
++ case FLASH_AMDLV065D:
++ fmt = "29LV065D (64 Mbit)\n";
++ break;
++ case FLASH_AMLV256U:
++ fmt = "29LV256M (256 Mbit)\n";
++ break;
++ case FLASH_28F128P30T:
++ fmt = "28F128P30T\n";
++ break;
++ case FLASH_S29GL256N:
++ fmt = "S29GL256N\n";
++ break;
++ default:
++ fmt = "Unknown Chip Type\n";
++ break;
++ }
++
++ printf (fmt, bootletter, boottype);
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20,
++ info->sector_count);
++
++ printf (" Sector Start Addresses:");
++
++ for (i=0; i<info->sector_count; ++i) {
++ ulong size;
++ int erased;
++ ulong *flash = (unsigned long *) info->start[i];
++
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++
++ /*
++ * Check if whole sector is erased
++ */
++ size =
++ (i != (info->sector_count - 1)) ?
++ (info->start[i + 1] - info->start[i]) >> 2 :
++ (info->start[0] + info->size - info->start[i]) >> 2;
++
++ for (
++ flash = (unsigned long *) info->start[i], erased = 1;
++ (flash != (unsigned long *) info->start[i] + size) && erased;
++ flash++
++ )
++ erased = *flash == ~0x0UL;
++
++ printf (" %08lX %s %s",
++ info->start[i],
++ erased ? "E": " ",
++ info->protect[i] ? "(RO)" : " ");
++ }
++
++ printf ("\n");
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++
++ulong flash_get_size (FPWV *addr, flash_info_t *info)
++{
++ int i;
++ u16 mfgid, devid, id3,id4;
++
++
++ /* Write auto select command: read Manufacturer ID */
++ /* Write auto select command sequence and test FLASH answer */
++ //EVMDM355_CPLD = 0;
++ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
++#if 0
++ EVMDM355_FLASH_CTL555 = 0xf0;
++
++ EVMDM355_FLASH_CTL555 = 0xaa;
++ EVMDM355_FLASH_CTL2AA = 0x55;
++ EVMDM355_FLASH_CTL555 = 0x90;
++#endif
++
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++
++ switch ( (mfgid = addr[FLASH_ID1]) & 0xff) {
++
++ case (uchar)AMD_MANUFACT:
++ printf ("MY AMD ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_AMD;
++ break;
++
++ case (uchar)INTEL_MANUFACT:
++ printf ("INTEL %x", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++ printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++ break;
++ }
++
++ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
++ if (info->flash_id != FLASH_UNKNOWN) switch (devid = (FPW)addr[FLASH_ID2]) {
++
++ case (FPW)AMD_ID_LV160B:
++ info->flash_id += FLASH_AM160B;
++ info->sector_count = 35;
++ info->size = 0x00200000;
++ info->start[0] = (ulong)addr;
++ info->start[1] = (ulong)addr + 0x4000;
++ info->start[2] = (ulong)addr + 0x6000;
++ info->start[3] = (ulong)addr + 0x8000;
++ for (i = 4; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * (i-3);
++ }
++ break;
++
++ case (FPW)AMD_ID_LV065D:
++ info->flash_id += FLASH_AMDLV065D;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++
++ case (FPW)AMD_ID_MIRROR:
++ /* MIRROR BIT FLASH, read more ID bytes */
++ id3 = (FPW)addr[FLASH_ID3];
++ id4 = (FPW)addr[FLASH_ID4];
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
++ {
++ info->flash_id += FLASH_AMLV640U;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ else if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
++ {
++ /* attention: only the first 16 MB will be used in u-boot */
++ info->flash_id += FLASH_AMLV256U;
++ info->sector_count = 256;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ else
++ {
++ /* This is the default NOR flash for DM355 */
++ info->flash_id += FLASH_S29GL256N;
++ info->sector_count = 256;
++ info->size = 0x02000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ }
++ break;
++ }
++ case (FPW)INTEL_ID_28F128P30T:
++ /* Intel StrataFlash 28F128P30T */
++ info->flash_id += FLASH_28F128P30T;
++ info->sector_count = 131;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ if (i < 127)
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ else
++ info->start[i] = (ulong)addr + 0xfe0000 + 0x8000 * (i-127);
++ }
++ break;
++
++ /* fall thru to here ! */
++ default:
++ printf ("unknown AMD device=%x %x %x",
++ (FPW)addr[FLASH_ID2],
++ (FPW)addr[FLASH_ID3],
++ (FPW)addr[FLASH_ID4]);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0x800000;
++ break;
++ }
++
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ return (info->size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ FPWV *addr;
++ int flag, prot, sect;
++ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
++ ulong start, now, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160B:
++ case FLASH_AMLV640U:
++ break;
++ case FLASH_AMLV256U:
++ break;
++ case FLASH_28F128P30T:
++ break;
++ case FLASH_S29GL256N:
++ break;
++ case FLASH_UNKNOWN:
++ default:
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect=s_first; sect<=s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
++
++ if (info->protect[sect] != 0) /*bmw esteem192e ispan mx1fs2 RPXlite tqm8540
++ protected, skip it */
++ continue;
++
++ printf ("Erasing sector %2d ... ", sect);
++
++ if ( sect == s_first )
++ {
++ addr = (FPWV *)(((info->start[sect]) & EVMDM355_CPLD_MASK) >> 14 );
++ }
++ else
++ {
++ addr += 2;
++ }
++
++ EVMDM355_CPLD = addr;
++
++ if (intel) {
++ *addr = (FPW)0x00600060; /* unlock block setup */
++ *addr = (FPW)0x00d000d0; /* unlock block confirm */
++ *addr = (FPW)0x00500050; /* clear status register */
++ *addr = (FPW)0x00200020; /* erase setup */
++ *addr = (FPW)0x00D000D0; /* erase confirm */
++ while((*addr & 0x80) == 0);
++ printf("done.\n");
++ }
++ else {
++ /* must be AMD style if not Intel */
++ FPWV *base; /* first address in bank */
++
++ base = (FPWV *)(info->start[0]);
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[0] = (FPW)0x00300030; /* erase sector */
++ while (!(*((vHwdptr)base) & 0x80));
++ printf("done.\n");
++ }
++
++
++ }
++
++ EVMDM355_CPLD = 0;
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ printf (" Erase Operation Completed.\n");
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
++ int bytes; /* number of bytes to program in current word */
++ int left; /* number of bytes left to program */
++ int res;
++ ulong cp, wp;
++ int count, i, l, rc, port_width;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++
++ /* get lower word aligned address */
++ wp = (addr & ~1);
++ port_width = 2;
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ cnt -= port_width;
++
++ if (count++ > 0x800) {
++ spin_wheel ();
++ count = 0;
++ }
++ }
++
++ if (cnt == 0) {
++ return (0);
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ return (write_word (info, wp, SWAP (data)));
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word to Flash
++ * A word is 16 or 32 bits, whichever the bus width of the flash bank
++ * (not an individual chip) is.
++ *
++ * returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_word (flash_info_t *info, FPWV *plAddress, FPW ulData)
++{
++ ulong start;
++ int flag;
++ int res = 0; /* result, assume success */
++ FPWV *base; /* first address in flash bank */
++ volatile USHORT *psAddress;
++ volatile USHORT *address_cs;
++ USHORT tmp;
++ ULONG tmp_ptr;
++
++ // Lower WORD.
++ psAddress = (USHORT *)plAddress;
++ tmp_ptr = (ULONG) plAddress;
++ address_cs = (USHORT *) (tmp_ptr & 0xFE000000);
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ {
++ *plAddress = (FPW)0x00400040;
++ *plAddress = ulData;
++ while ((*plAddress & 0x80) == 0);
++ }
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ {
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xAA);
++ *((vHwdptr)address_cs + 0x2AA) = ((Hwd)0x55);
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xA0);
++ *psAddress = ulData;
++ // Wait for ready.
++ while (1)
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ if(tmp & 0x20) // Exceeded Time Limit
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ flash_reset_sector(info, (ULONG) psAddress);
++ return 1;
++ }
++ }
++ }
++ }
++ }
++
++ // Return to read mode
++ flash_reset_sector(info, (ULONG) psAddress);
++
++ // Verify the data.
++ if (*psAddress != ulData)
++ {
++ return 1;
++ printf("Write of one 16-bit word failed\n");
++ }
++ return 0;
++}
++
++void inline spin_wheel (void)
++{
++ static int p = 0;
++ static char w[] = "\\/-";
++
++ printf ("\010%c", w[p]);
++ (++p == 3) ? (p = 0) : 0;
++}
++#endif
+diff -Nurd u-boot-1.2.0/board/dm355_evm/flash_params.h u-boot-1.2.0-leopard/board/dm355_evm/flash_params.h
+--- u-boot-1.2.0/board/dm355_evm/flash_params.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/flash_params.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,319 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _FLASH_PARAMSH_
++#define _FLASH_PARAMSH_
++//
++//Structs
++//
++typedef struct _PageInfo
++{
++ ULONG reserved;
++ BYTE BlockReserved;
++ BYTE BadBlockFlag;
++ USHORT reserved2;
++}PageInfo, *PPageInfo;
++
++typedef struct
++{
++ ULONG ReturnValue;
++ ULONG ReadAddress;
++ ULONG WriteAddress;
++ ULONG Size;
++} Download_Parms, *PDownload_Parms;
++
++#define NO_ERROR 0
++#define CORRECTED_ERROR 1
++#define ECC_ERROR 2
++#define UNCORRECTED_ERROR 3
++
++
++#define BIT0 0x00000001
++#define BIT1 0x00000002
++#define BIT2 0x00000004
++#define BIT3 0x00000008
++#define BIT4 0x00000010
++#define BIT5 0x00000020
++#define BIT6 0x00000040
++#define BIT7 0x00000080
++#define BIT8 0x00000100
++#define BIT9 0x00000200
++#define BIT10 0x00000400
++#define BIT11 0x00000800
++#define BIT12 0x00001000
++#define BIT13 0x00002000
++#define BIT14 0x00004000
++#define BIT15 0x00008000
++#define BIT16 0x00010000
++#define BIT17 0x00020000
++#define BIT18 0x00040000
++#define BIT19 0x00080000
++#define BIT20 0x00100000
++#define BIT21 0x00200000
++#define BIT22 0x00400000
++#define BIT23 0x00800000
++#define BIT24 0x01000000
++#define BIT25 0x02000000
++#define BIT26 0x04000000
++#define BIT27 0x08000000
++#define BIT28 0x10000000
++#define BIT29 0x20000000
++#define BIT30 0x40000000
++#define BIT31 0x80000000
++
++
++
++// Status bit pattern
++#define STATUS_READY 0x40
++#define STATUS_ERROR 0x01
++//
++//NOR SUPPORT
++//
++// Flash ID Commands INTEL
++#define INTEL_ID_CMD ((Hwd)0x0090) // INTEL ID CMD
++#define INTEL_MANF_ID ((Hwd)0x0089) // INTEL Manf ID expected
++#define INTEL_DEVICE_8T ((Hwd)0x88F1) // INTEL 8Mb top device code
++#define INTEL_DEVICE_8B ((Hwd)0x88F2) // INTEL 8Mb bottom device code
++#define INTEL_DEVICE_16T ((Hwd)0x88F3) // INTEL 16Mb top device code
++#define INTEL_DEVICE_16B ((Hwd)0x88F4) // INTEL 16Mb bottom device code
++#define INTELS_J3_DEVICE_32 ((Hwd)0x0016) // INTEL Strata J3 32Mb device code
++#define INTELS_J3_DEVICE_64 ((Hwd)0x0017) // INTEL Strata J3 64Mb device code
++#define INTELS_J3_DEVICE_128 ((Hwd)0x0018) // INTEL Strata J3 128Mb device code
++#define INTELS_K3_DEVICE_64 ((Hwd)0x8801) // INTEL Strata K3 64Mb device code
++#define INTELS_K3_DEVICE_128 ((Hwd)0x8802) // INTEL Strata K3 128Mb device code
++#define INTELS_K3_DEVICE_256 ((Hwd)0x8803) // INTEL Strata K3 256Mb device code
++#define INTELS_W18_DEVICE_128T ((Hwd)0x8876) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_W18_DEVICE_128B ((Hwd)0x8867) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_128T ((Hwd)0x880C) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_L18_DEVICE_128B ((Hwd)0x880F) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_256T ((Hwd)0x880D) // INTEL Wirless Flash Top 256 Mb device code
++#define INTELS_L18_DEVICE_256B ((Hwd)0x8810) // INTEL Wirless Flash Bottom 256 Mb device code
++#define INTELS_K18_DEVICE_256B ((Hwd)0x8807) // INTEL Wirless Flash Bottom 256 Mb device code
++#define AMD1_DEVICE_ID ((Hwd)0x2253) // AMD29DL323CB
++#define AMD2_DEVICE_ID ((Hwd)0x2249) // AMD29LV160D
++#define AMD3_DEVICE_ID1 ((Hwd)0x2212) // AMD29LV256M
++#define AMD3_DEVICE_ID2 ((Hwd)0x2201) // AMD29LV256M
++// Flash ID Commands FUJITSU (Programs like AMD)
++#define FUJITSU_MANF_ID ((Hwd)0x04) // Fujitsu Manf ID expected
++#define FUJITSU1_DEVICE_ID ((Hwd)0x2253) // MBM29DL323BD
++//Micron Programs Like Intel or Micron
++#define MICRON_MANF_ID ((Hwd)0x002C) // MICRON Manf ID expected
++#define MICRON_MT28F_DEVICE_128T ((Hwd)0x4492) // MICRON Flash device Bottom 128 Mb
++//Samsung Programs like AMD
++#define SAMSUNG_MANF_ID ((Hwd)0x00EC) //SAMSUNG Manf ID expected
++#define SAMSUNG_K8S2815E_128T ((Hwd) 0x22F8) //SAMSUNG NOR Flash device TOP 128 Mb
++// Flash Erase Commands AMD and FUJITSU
++// Flash ID Commands AMD
++#define AMD_ID_CMD0 ((Hwd)0xAA) // AMD ID CMD 0
++#define AMD_CMD0_ADDR 0x555 // AMD CMD0 Offset
++#define AMD_ID_CMD1 ((Hwd)0x55) // AMD ID CMD 1
++#define AMD_CMD1_ADDR 0x2AA // AMD CMD1 Offset
++#define AMD_ID_CMD2 ((Hwd)0x90) // AMD ID CMD 2
++#define AMD_CMD2_ADDR 0x555 // AMD CMD2 Offset
++#define AMD_MANF_ID ((Hwd)0x01) // AMD Manf ID expected
++#define AMD_DEVICE_ID_MULTI ((Hwd)0x227E)// Indicates Multi-Address Device ID
++#define AMD_DEVICE_ID_OFFSET 0x1
++#define AMD_DEVICE_ID_OFFSET1 0x0E // First Addr for Multi-Address ID
++#define AMD_DEVICE_ID_OFFSET2 0x0F // Second Addr for Multi-Address ID
++#define AMD_DEVICE_RESET ((Hwd)0x00F0) // AMD Device Reset Command
++#define AMD_ERASE_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_CMD3 ((Hwd)0xAA) // AMD29LV017B Erase CMD 3
++#define AMD_ERASE_CMD4 ((Hwd)0x55) // AMD29LV017B Erase CMD 4
++#define AMD_ERASE_CMD5 ((Hwd)0x10) // AMD29LV017B Erase CMD 5
++#define AMD_ERASE_DONE ((Hwd)0xFFFF) // AMD29LV017B Erase Done
++#define AMD_ERASE_BLK_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_BLK_CMD3 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD4 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD5 ((Hwd)0x30)
++#define AMD_PROG_CMD0 ((Hwd)0xAA)
++#define AMD_PROG_CMD1 ((Hwd)0x55)
++#define AMD_PROG_CMD2 ((Hwd)0xA0)
++#define AMD2_ERASE_CMD0 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 0
++#define AMD2_ERASE_CMD1 ((Hwd)0x0055) // AMD29DL800B Erase CMD 1
++#define AMD2_ERASE_CMD2 ((Hwd)0x0080) // AMD29DL800B Erase CMD 2
++#define AMD2_ERASE_CMD3 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 3
++#define AMD2_ERASE_CMD4 ((Hwd)0x0055) // AMD29DL800B Erase CMD 4
++#define AMD2_ERASE_CMD5 ((Hwd)0x0030) // AMD29DL800B Erase CMD 5
++#define AMD2_ERASE_DONE ((Hwd)0x00FF) // AMD29DL800B Erase Done
++#define AMD_WRT_BUF_LOAD_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_LOAD_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_LOAD_CMD2 ((Hwd)0x25)
++#define AMD_WRT_BUF_CONF_CMD0 ((Hwd)0x29)
++#define AMD_WRT_BUF_ABORT_RESET_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_ABORT_RESET_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_ABORT_RESET_CMD2 ((Hwd)0xF0)
++// Flash Erase Commands INTEL
++#define INTEL_ERASE_CMD0 ((Hwd)0x0020) // INTEL Erase CMD 0
++#define INTEL_ERASE_CMD1 ((Hwd)0x00D0) // INTEL Erase CMD 1
++#define INTEL_ERASE_DONE ((Hwd)0x0080) // INTEL Erase Done
++#define INTEL_READ_MODE ((Hwd)0x00FF) // INTEL Read Array Mode
++#define STRATA_READ 0x4
++#define STRATA_WRITE 0x8
++// Flash Block Information
++// Intel Burst devices:
++// 2MB each (8 8KB [param] and 31 64KB [main] blocks each) for 8MB total
++#define NUM_INTEL_BURST_BLOCKS 8
++#define PARAM_SET0 0
++#define MAIN_SET0 1
++#define PARAM_SET1 2
++#define MAIN_SET1 3
++#define PARAM_SET2 4
++#define MAIN_SET2 5
++#define PARAM_SET3 6
++#define MAIN_SET3 7
++// Intel Strata devices:
++// 4MB each (32 128KB blocks each) for 8MB total
++// 8MB each (64 128KB blocks each) for 16MB total
++// 16MB each (128 128KB blocks each) for 32MB total
++#define NUM_INTEL_STRATA_BLOCKS 8
++#define BLOCK_SET0 0
++#define BLOCK_SET1 1
++#define BLOCK_SET2 2
++#define BLOCK_SET3 3
++#define BLOCK_SET4 4
++#define BLOCK_SET5 5
++#define BLOCK_SET6 6
++#define BLOCK_SET7 7
++// For AMD Flash
++#define NUM_AMD_SECTORS 8 // Only using the first 8 8-KB sections (64 KB Total)
++#define AMD_ADDRESS_CS_MASK 0xFE000000 //--AMD-- Set-up as 0xFE000000 per Jon Hunter (Ti)
++// Flash Types
++enum NORFlashType {
++ FLASH_NOT_FOUND,
++ FLASH_UNSUPPORTED,
++ FLASH_AMD_LV017_2MB, // (AMD AM29LV017B-80RFC/RE)
++ FLASH_AMD_DL800_1MB_BOTTOM, // (AMD AM29DL800BB-70EC)
++ FLASH_AMD_DL800_1MB_TOP, // (AMD AM29DL800BT-70EC)
++ FLASH_AMD_DL323_4MB_BOTTOM, // (AMD AM29DL323CB-70EC)
++ FLASH_AMD_DL323_4MB_TOP, // (AMD AM29DL323BT-70EC)
++ FLASH_AMD_LV160_2MB_BOTTOM,
++ FLASH_AMD_LV160_2MB_TOP,
++ FLASH_AMD_LV256M_32MB, // (AMD AM29LV256MH/L)
++ FLASH_INTEL_BURST_8MB_BOTTOM, // (Intel DT28F80F3B-95)
++ FLASH_INTEL_BURST_8MB_TOP, // (Intel DT28F80F3T-95)
++ FLASH_INTEL_BURST_16MB_BOTTOM, // (Intel DT28F160F3B-95)
++ FLASH_INTEL_BURST_16MB_TOP, // (Intel DT28F160F3T-95)
++ FLASH_INTEL_STRATA_J3_4MB, // (Intel DT28F320J3A)
++ FLASH_INTEL_STRATA_J3_8MB, // (Intel DT28F640J3A)
++ FLASH_INTEL_STRATA_J3_16MB, // (Intel DT28F128J3A)
++ FLASH_FUJITSU_DL323_4MB_BOTTOM, // (Fujitsu DL323 Bottom
++ FLASH_INTEL_STRATA_K3_8MB, // (Intel 28F64K3C115)
++ FLASH_INTEL_STRATA_K3_16MB, // (Intel 28F128K3C115)
++ FLASH_INTEL_STRATA_K3_32MB, // (Intel 28F256K3C115)
++ FLASH_INTEL_W18_16MB_TOP, // (Intel 28F128W18T) }
++ FLASH_INTEL_W18_16MB_BOTTOM, // (Intel 28F128W18B) }
++ FLASH_INTEL_L18_16MB_TOP, // (Intel 28F128L18T) }
++ FLASH_INTEL_L18_16MB_BOTTOM, // (Intel 28F128L18B) }
++ FLASH_INTEL_L18_32MB_TOP, // (Intel 28F256L18T) }
++ FLASH_INTEL_L18_32MB_BOTTOM, // (Intel 28F256L18B) }
++ FLASH_INTEL_K18_32MB_BOTTOM, // (Intel 28F256K18B) }
++ FLASH_MICRON_16MB_TOP, // (Micron MT28F160C34 )
++ FLASH_SAMSUNG_16MB_TOP // (Samsung K8S281ETA)
++};
++////NAND SUPPORT
++//
++enum NANDFlashType {
++ NANDFLASH_NOT_FOUND,
++ NANDFLASH_SAMSUNG_32x8_Q, // (Samsung K9F5608Q0B)
++ NANDFLASH_SAMSUNG_32x8_U, // (Samsung K9F5608U0B)
++ NANDFLASH_SAMSUNG_16x16_Q, // (Samsung K9F5616Q0B)
++ NANDFLASH_SAMSUNG_16x16_U, // (Samsung K9F5616U0B)
++ NANDFLASH_SAMSUNG_16x8_U // (Samsung K9F1G08QOM)
++};
++// Samsung Manufacture Code
++#define SAMSUNG_MANUFACT_ID 0xEC
++// Samsung Nand Flash Device ID
++#define SAMSUNG_K9F5608Q0B 0x35
++#define SAMSUNG_K9F5608U0B 0x75
++#define SAMSUNG_K9F5616Q0B 0x45
++#define SAMSUNG_K9F5616U0B 0x55
++// MACROS for NAND Flash support
++// Flash Chip Capability
++#define NUM_BLOCKS 0x800 // 32 MB On-board NAND flash.
++#define PAGE_SIZE 512
++#define SPARE_SIZE 16
++#define PAGES_PER_BLOCK 32
++#define PAGE_TO_BLOCK(page) ((page) >> 5 )
++#define BLOCK_TO_PAGE(block) ((block) << 5 )
++#define FILE_TO_PAGE_SIZE(fs) ((fs / PAGE_SIZE) + ((fs % PAGE_SIZE) ? 1 : 0))
++// For flash chip that is bigger than 32 MB, we need to have 4 step address
++#ifdef NAND_SIZE_GT_32MB
++#define NEED_EXT_ADDR 1
++#else
++#define NEED_EXT_ADDR 0
++#endif
++// Nand flash block status definitions.
++#define BLOCK_STATUS_UNKNOWN 0x01
++#define BLOCK_STATUS_BAD 0x02
++#define BLOCK_STATUS_READONLY 0x04
++#define BLOCK_STATUS_RESERVED 0x08
++#define BLOCK_RESERVED 0x01
++#define BLOCK_READONLY 0x02
++#define BADBLOCKMARK 0x00
++// NAND Flash Command. This appears to be generic across all NAND flash chips
++#define CMD_READ 0x00 // Read
++#define CMD_READ1 0x01 // Read1
++#define CMD_READ2 0x50 // Read2
++#define CMD_READID 0x90 // ReadID
++#define CMD_WRITE 0x80 // Write phase 1
++#define CMD_WRITE2 0x10 // Write phase 2
++#define CMD_ERASE 0x60 // Erase phase 1
++#define CMD_ERASE2 0xd0 // Erase phase 2
++#define CMD_STATUS 0x70 // Status read
++#define CMD_RESET 0xff // Reset
++//
++//Prototpyes
++//
++// NOR Flash Dependent Function Pointers
++void (*User_Hard_Reset_Flash)(void);
++void (*User_Soft_Reset_Flash)(unsigned long addr);
++void (*User_Flash_Erase_Block)(unsigned long addr);
++void (*User_Flash_Erase_All)(unsigned long addr);
++void (*User_Flash_Write_Entry)(void);
++int (*User_Flash_Write)(unsigned long *addr, unsigned short data);
++int (*User_Flash_Optimized_Write)(unsigned long *addr, unsigned short data[], unsigned long);
++void (*User_Flash_Write_Exit)(void);
++// Flash AMD Device Dependent Routines
++void AMD_Hard_Reset_Flash(void);
++void AMD_Soft_Reset_Flash(unsigned long);
++void AMD_Flash_Erase_Block(unsigned long);
++void AMD_Flash_Erase_All(unsigned long);
++int AMD_Flash_Write(unsigned long *, unsigned short);
++int AMD_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++void AMD_Write_Buf_Abort_Reset_Flash( unsigned long plAddress );
++// Flash Intel Device Dependent Routines
++void INTEL_Hard_Reset_Flash(void);
++void INTEL_Soft_Reset_Flash(unsigned long addr);
++void INTEL_Flash_Erase_Block(unsigned long);
++int INTEL_Flash_Write(unsigned long *addr, unsigned short data);
++int INTEL_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++
++//General Functions
++void Flash_Do_Nothing(void);
++
++#endif
++
++
+diff -Nurd u-boot-1.2.0/board/dm355_evm/lowlevel_init.S u-boot-1.2.0-leopard/board/dm355_evm/lowlevel_init.S
+--- u-boot-1.2.0/board/dm355_evm/lowlevel_init.S 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/lowlevel_init.S 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,766 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2003
++ * Texas Instruments, <www.ti.com>
++ * Kshitij Gupta <Kshitij@ti.com>
++ *
++ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
++ *
++ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Swaminathan S, Nov 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#if defined(CONFIG_OMAP1610)
++#include <./configs/omap1510.h>
++#endif
++
++_TEXT_BASE:
++ .word TEXT_BASE /* sdram load addr from config.mk */
++
++.global reset_cpu
++reset_cpu:
++ bl reset_processor
++
++
++.globl lowlevel_init
++lowlevel_init:
++ /*mov pc, lr*/
++
++ /*------------------------------------------------------*
++ * mask all IRQs by setting all bits in the EINT default *
++ *------------------------------------------------------*/
++ mov r1, #0x00000000
++ ldr r0, =EINT_ENABLE0
++ str r1, [r0]
++ ldr r0, =EINT_ENABLE1
++ str r1, [r0]
++
++ /*------------------------------------------------------*
++ * Put the GEM in reset *
++ *------------------------------------------------------*/
++
++ /* Put the GEM in reset */
++ /* bhavinp: commented: No GEM in DM350*/
++#if 0
++ LDR R8, PSC_GEM_FLAG_CLEAR
++ LDR R6, MDCTL_GEM
++ LDR R7, [R6]
++ AND R7, R7, R8
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x2
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStopGem:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x2
++ CMP R7, #0x0
++ BNE checkStatClkStopGem
++
++ /* Check for GEM Reset Completion */
++checkGemStatClkStop:
++ LDR R6, MDSTAT_GEM
++ LDR R7, [R6]
++ AND R7, R7, #0x100
++ CMP R7, #0x0
++ BNE checkGemStatClkStop
++
++ /* Do this for enabling a WDT initiated reset this is a workaround
++ for a chip bug. Not required under normal situations */
++ LDR R6, P1394
++ MOV R10, #0x0
++ STR R10, [R6]
++#endif //bhavinp: commented: End
++ /*------------------------------------------------------*
++ * Enable L1 & L2 Memories in Fast mode *
++ *------------------------------------------------------*/
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, MMARG_BRF0
++ LDR R10, MMARG_BRF0_VAL
++ STR R10, [R6]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++ /*------------------------------------------------------*
++ * DDR2 PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R10, #0x0
++ LDR R6, PLL2_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R10, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++WaitPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitPPL2Loop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL2_PLLM
++ /*MOV R2, #0x13 Orig value */
++ /*MOV R2, #0xB 165MHz */
++ /*MOV R2, #0xD 189 MHz */
++ MOV R2, #0x17 /* 162 MHz */
++ STR R2, [R6] /* R2 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV2
++ MOV R3, #0x1 /* Orig */
++ /*MOV R3, #0x0*/
++ STR R3, [R6] /* R3 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV1
++ /*MOV R4, #0x9 Orig */
++ /*MOV R4, #0x5 165MHz */
++ /*MOV R4, #0x6 189 MHz */
++ MOV R4, #0xB /* 54 MHz */
++ STR R4, [R6] /* R4 */
++
++ /* PLL2 DIV1 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV2
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop_0:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop_0
++
++ /* PLL2 DIV2 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV1
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0x218
++ResetPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetPPL2Loop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++PLL2Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL2Lock
++
++ /* Enable the PLL */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkStop
++
++ /*------------------------------------------------------*
++ * Program DDR2 MMRs for 162MHz Setting *
++ *------------------------------------------------------*/
++
++ /* Program PHY Control Register */
++ LDR R6, DDRCTL
++ LDR R7, DDRCTL_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM Bank Config Register */
++ LDR R6, SDCFG
++ LDR R7, SDCFG_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-0 Config Register */
++ LDR R6, SDTIM0
++ LDR R7, SDTIM0_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDTIM1
++ LDR R7, SDTIM1_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program the SDRAM Bang Config Control Register */
++ LDR R10, MASK_VAL
++ LDR R8, SDCFG
++ LDR R9, SDCFG_VAL
++ AND R9, R9, R10
++ STR R9, [R8]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDREF
++ LDR R7, SDREF_VAL
++ STR R7, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Issue a Dummy DDR2 read/write */
++ LDR R8, DDR2_VAL
++ LDR R7, DUMMY_VAL
++ STR R7, [R8]
++ LDR R7, [R8]
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x1
++ BNE checkDDRStatClkStop2
++
++ /*------------------------------------------------------*
++ * Turn DDR2 Controller Clocks On *
++ *------------------------------------------------------*/
++
++ /* Enable the DDR2 LPSC Module */
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkEn2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkEn2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkEn2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkEn2
++
++ /* DDR Writes and Reads */
++ LDR R6, CFGTEST
++ MOV R3, #0x1
++ STR R3, [R6] /* R3 */
++
++ /*------------------------------------------------------*
++ * System PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R2, #0x0
++ LDR R6, PLL1_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R2, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++
++WaitLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitLoop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Disable the PLL */
++ ORR R8, R8, #0x10
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL1_PLLM
++ /*MOV R3, #0x10 As per Amit, PLL should be in normal mode i.e X by 16 */
++ /*MOV R3, #0x11 As per Ebby 486 MHz */
++ /*MOV R3, #0x14 For 567MHz */
++ MOV R3, #0x15 /* For 594MHz */
++ STR R3, [R6]
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0xFF
++
++ResetLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetLoop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL1_CTL
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++
++PLL1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL1Lock
++
++ /* Enable the PLL */
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ nop
++ nop
++ nop
++ nop
++
++ /*------------------------------------------------------*
++ * AEMIF configuration for NOR Flash (double check) *
++ *------------------------------------------------------*/
++ LDR R0, _PINMUX0
++ LDR R1, _DEV_SETTING
++ STR R1, [R0]
++
++ LDR R0, WAITCFG
++ LDR R1, WAITCFG_VAL
++ LDR R2, [R0]
++ ORR R2, R2, R1
++ STR R2, [R0]
++
++ LDR R0, ACFG3
++ LDR R1, ACFG3_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG4
++ LDR R1, ACFG4_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG5
++ LDR R1, ACFG5_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ /*--------------------------------------*
++ * VTP manual Calibration *
++ *--------------------------------------*/
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR0
++ STR R1, [R0]
++
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR1
++ STR R1, [R0]
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTPLock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTPLock
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, DDRVTPR
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ AND R8, R7, #0x3E0
++ ORR R8, R7, R8
++ LDR R7, VTP_RECAL
++ ORR R8, R7, R8
++ LDR R7, VTP_EN
++ ORR R8, R7, R8
++ STR R8, [R0]
++
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTP1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTP1Lock
++
++ LDR R1, [R0]
++ LDR R2, VTP_MASK
++ AND R2, R1, R2
++ STR R2, [R0]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++
++
++ /* Start MPU Timer 1 */
++/* MOV R10, #0x1AFFFFFF
++
++WaitRam:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitRam
++*/
++
++ /* back to arch calling code */
++ mov pc, lr
++
++ /* the literal pools origin */
++ .ltorg
++
++REG_TC_EMIFS_CONFIG: /* 32 bits */
++ .word 0xfffecc0c
++REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
++ .word 0xfffecc10
++REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
++ .word 0xfffecc14
++REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
++ .word 0xfffecc18
++REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
++ .word 0xfffecc1c
++
++_PINMUX0: .word 0x01C40000 /* Device Configuration Registers */
++_PINMUX1: .word 0x01C40004 /* Device Configuration Registers */
++
++_DEV_SETTING: .word 0x00000C1F
++
++AEMIF_BASE_ADDR: .word 0x01E10000
++WAITCFG: .word 0x01E10004
++ACFG2: .word 0x01E10010
++ACFG3: .word 0x01E10014
++ACFG4: .word 0x01E10018
++ACFG5: .word 0x01E1001C
++
++WAITCFG_VAL: .word 0x0
++ACFG2_VAL: .word 0x3FFFFFFD
++ACFG3_VAL: .word 0x3FFFFFFD
++ACFG4_VAL: .word 0x3FFFFFFD
++ACFG5_VAL: .word 0x3FFFFFFD
++
++MDCTL_DDR2: .word 0x01C41A34
++PTCMD: .word 0x01C41120
++PTSTAT: .word 0x01C41128
++MDSTAT_DDR2: .word 0x01C41834
++
++MDCTL_TPCC: .word 0x01C41A08
++MDSTAT_TPCC: .word 0x01C41808
++
++MDCTL_TPTC0: .word 0x01C41A0C
++MDSTAT_TPTC0: .word 0x01C4180C
++
++MDCTL_TPTC1: .word 0x01C41A10
++MDSTAT_TPTC1: .word 0x01C41810
++
++DDR2DEBUG: .word 0x8FFFF000
++
++/* EINT0 register */
++EINT_ENABLE0:
++ .word 0x01c48018
++
++/* EINT1 register */
++EINT_ENABLE1:
++ .word 0x01c4801C
++
++CLEAR_FLAG: .word 0xFFFFFFFF
++EDMA_PARAM0_D_S_BIDX_VAL: .word 0x00010001
++PSC_FLAG_CLEAR: .word 0xFFFFFFE0
++PSC_GEM_FLAG_CLEAR: .word 0xFFFFFEFF
++MDCTL_TPCC_SYNC: .word 0x01C41A08
++MDSTAT_TPCC_SYNC: .word 0x01C41808
++
++MDCTL_TPTC0_SYNC: .word 0x01C41A0C
++MDSTAT_TPTC0_SYNC: .word 0x01C4180C
++
++MDCTL_TPTC1_SYNC: .word 0x01C41A10
++MDSTAT_TPTC1_SYNC: .word 0x01C41810
++
++PTCMD_SYNC: .word 0x01C41120
++PTSTAT_SYNC: .word 0x01C41128
++DATA_MAX: .word 0x0000FFFF
++SPIN_ADDR: .word 0x00003FFC /* ARM PC value(B $) for the DSP Test cases */
++SPIN_OPCODE: .word 0xEAFFFFFE
++
++/* Interrupt Clear Register */
++FIQ0_CLEAR: .word 0x01C48000
++FIQ1_CLEAR: .word 0x01C48004
++IRQ0_CLEAR: .word 0x01C48008
++IRQ1_CLEAR: .word 0x01C4800C
++
++/* DDR2 MMR & CONFIGURATION VALUES for 75 MHZ */
++DDRCTL: .word 0x200000E4
++SDREF: .word 0x2000000C
++SDCFG: .word 0x20000008
++SDTIM0: .word 0x20000010
++SDTIM1: .word 0x20000014
++SDSTAT: .word 0x20000004
++VTPIOCR: .word 0x200000F0 /* VTP IO Control register */
++DDRVTPR: .word 0x01C42030 /* DDR VPTR MMR */
++DFT_ENABLE: .word 0x01C4004C
++VTP_MMR0: .word 0x201F
++VTP_MMR1: .word 0xA01F
++PCH_MASK: .word 0x3E0
++VTP_LOCK_COUNT: .word 0x5b0
++VTP_MASK: .word 0xFFFFDFFF
++VTP_RECAL: .word 0x40000
++VTP_EN: .word 0x02000
++
++
++CFGTEST: .word 0x80010000
++
++/* original values
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00008832
++MASK_VAL: .word 0x00000FFF
++SDTIM0_VAL_135MHz: .word 0x30923A91
++SDTIM1_VAL_135MHz: .word 0x0019c722
++SDREF_VAL: .word 0x000005c3
++*/
++
++/* 162MHz as per GEL file for DVEVM with Micron DDR2 SDRAM */
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00178632 /* CL=3 for MT47H64M16BT-5E */
++MASK_VAL: .word 0xFFFF7FFF
++SDTIM0_VAL_162MHz: .word 0x28923211
++SDTIM1_VAL_162MHz: .word 0x0016c722
++SDREF_VAL: .word 0x000004F0
++
++/* GEM Power Up & LPSC Control Register */
++CHP_SHRTSW: .word 0x01C40038
++
++PD1_CTL: .word 0x01C41304
++EPCPR: .word 0x01C41070
++EPCCR: .word 0x01C41078
++MDCTL_GEM: .word 0x01C41A9C
++MDSTAT_GEM: .word 0x01C4189C
++MDCTL_IMCOP: .word 0x01C41AA0
++MDSTAT_IMCOP: .word 0x01C418A0
++
++PTCMD_0: .word 0x01C41120
++PTSTAT_0: .word 0x01C41128
++P1394: .word 0x01C41a20
++
++PLL_CLKSRC_MASK: .word 0xFFFFFEFF /* Mask the Clock Mode bit and it is programmble through the run script */
++PLL_ENSRC_MASK: .word 0xFFFFFFDF /* Select the PLLEN source */
++PLL_BYPASS_MASK: .word 0xFFFFFFFE /* Put the PLL in BYPASS, eventhough the device */
++PLL_RESET_MASK: .word 0xFFFFFFF7 /* Put the PLL in Reset Mode */
++PLL_PWRUP_MASK: .word 0xFFFFFFFD /* PLL Power up Mask Bit */
++PLL_DISABLE_ENABLE_MASK: .word 0xFFFFFFEF /* Enable the PLL from Disable */
++PLL_LOCK_COUNT: .word 0x2000
++
++/* PLL1-SYSTEM PLL MMRs */
++PLL1_CTL: .word 0x01C40900
++PLL1_PLLM: .word 0x01C40910
++
++/* PLL2-SYSTEM PLL MMRs */
++PLL2_CTL: .word 0x01C40D00
++PLL2_PLLM: .word 0x01C40D10
++PLL2_DIV2: .word 0x01C40D1C
++PLL2_DIV1: .word 0x01C40D18
++PLL2_PLLCMD: .word 0x01C40D38
++PLL2_PLLSTAT: .word 0x01C40D3C
++PLL2_BPDIV: .word 0x01C40D2C
++PLL2_DIV_MASK: .word 0xFFFF7FFF
++
++
++MDCTL_DDR2_0: .word 0x01C41A34
++MDSTAT_DDR2_0: .word 0x01C41834
++DLLPWRUPMASK: .word 0xFFFFFFEF
++DDR2_ADDR: .word 0x80000000
++
++DFT_BASEADDR: .word 0x01C42000
++MMARG_BRF0: .word 0x01C42010 /* BRF margin mode 0 (Read / write)*/
++MMARG_G10: .word 0x01C42018 /*GL margin mode 0 (Read / write)*/
++MMARG_BRF0_VAL: .word 0x00444400
++DDR2_VAL: .word 0x80000000
++DUMMY_VAL: .word 0xA55AA55A
++
++/* command values */
++.equ CMD_SDRAM_NOP, 0x00000000
++.equ CMD_SDRAM_PRECHARGE, 0x00000001
++.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
++.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
+diff -Nurd u-boot-1.2.0/board/dm355_evm/nand.c u-boot-1.2.0-leopard/board/dm355_evm/nand.c
+--- u-boot-1.2.0/board/dm355_evm/nand.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/nand.c 2008-01-05 03:44:03.000000000 -0300
+@@ -0,0 +1,805 @@
++/*
++ * NAND driver for TI DaVinci based boards.
++ *
++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
++ *
++ * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
++ */
++
++/*
++ *
++ * linux/drivers/mtd/nand/nand_dm355.c
++ *
++ * NAND Flash Driver
++ *
++ * Copyright (C) 2006 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ * Overview:
++ * This is a device driver for the NAND flash device found on the
++ * DaVinci board which utilizes the Samsung k9k2g08 part.
++ *
++ Modifications:
++ ver. 1.0: Feb 2005, Vinod/Sudhakar
++ -
++ *
++ */
++
++#include <common.h>
++
++#if (CONFIG_COMMANDS & CFG_CMD_NAND)
++#if !defined(CFG_NAND_LEGACY)
++
++#include <asm/arch/types.h>
++//#include "soc.h"
++#include <nand.h>
++#include <asm/arch/nand_defs.h>
++#include <asm/arch/emif_defs.h>
++
++#define NAND_Ecc_P1e (1 << 0)
++#define NAND_Ecc_P2e (1 << 1)
++#define NAND_Ecc_P4e (1 << 2)
++#define NAND_Ecc_P8e (1 << 3)
++#define NAND_Ecc_P16e (1 << 4)
++#define NAND_Ecc_P32e (1 << 5)
++#define NAND_Ecc_P64e (1 << 6)
++#define NAND_Ecc_P128e (1 << 7)
++#define NAND_Ecc_P256e (1 << 8)
++#define NAND_Ecc_P512e (1 << 9)
++#define NAND_Ecc_P1024e (1 << 10)
++#define NAND_Ecc_P2048e (1 << 11)
++
++#define NAND_Ecc_P1o (1 << 16)
++#define NAND_Ecc_P2o (1 << 17)
++#define NAND_Ecc_P4o (1 << 18)
++#define NAND_Ecc_P8o (1 << 19)
++#define NAND_Ecc_P16o (1 << 20)
++#define NAND_Ecc_P32o (1 << 21)
++#define NAND_Ecc_P64o (1 << 22)
++#define NAND_Ecc_P128o (1 << 23)
++#define NAND_Ecc_P256o (1 << 24)
++#define NAND_Ecc_P512o (1 << 25)
++#define NAND_Ecc_P1024o (1 << 26)
++#define NAND_Ecc_P2048o (1 << 27)
++
++#define TF(value) (value ? 1 : 0)
++
++#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0 )
++#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1 )
++#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2 )
++#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3 )
++#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4 )
++#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5 )
++#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6 )
++#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7 )
++
++#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0 )
++#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1 )
++#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2 )
++#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3 )
++#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4 )
++#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5 )
++#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6 )
++#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7 )
++
++#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0 )
++#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1 )
++#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2 )
++#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3 )
++#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4 )
++#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5 )
++#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6 )
++#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7 )
++
++#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0 )
++#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1 )
++#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2 )
++#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3 )
++#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4 )
++#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5 )
++#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6 )
++#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7 )
++
++#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0 )
++#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1 )
++
++#define CSL_EMIF_1_REGS 0x01E10000
++
++#define NAND4BITECCLOAD (0x01E10000 +0xBC)
++#define NAND4BITECC1 (0x01E10000 +0xC0)
++#define NAND4BITECC2 (0x01E10000 +0xC4)
++#define NAND4BITECC3 (0x01E10000 +0xC8)
++#define NAND4BITECC4 (0x01E10000 +0xCC)
++
++#define NANDERRADD1 (0x01E10000 +0xD0)
++#define NANDERRADD2 (0x01E10000 +0xD4)
++#define NANDERRVAL1 (0x01E10000 +0xD8)
++#define NANDERRVAL2 (0x01E10000 +0xDC)
++
++/* Definitions for 4-bit hardware ECC */
++#define NAND_4BITECC_MASK 0x03FF03FF
++#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
++#define ECC_STATE_NO_ERR 0x0
++#define ECC_STATE_TOO_MANY_ERRS 0x1
++#define ECC_STATE_ERR_CORR_COMP_P 0x2
++#define ECC_STATE_ERR_CORR_COMP_N 0x3
++#define ECC_MAX_CORRECTABLE_ERRORS 0x4
++extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
++
++static void nand_dm350evm_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++ struct nand_chip *this = mtd->priv;
++ u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
++ u_int32_t IO_ADDR_R = (u_int32_t)this->IO_ADDR_R;
++
++ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++
++ switch (cmd) {
++ case NAND_CTL_SETCLE:
++ IO_ADDR_W |= MASK_CLE;
++ break;
++ case NAND_CTL_SETALE:
++ IO_ADDR_W |= MASK_ALE;
++ break;
++ }
++
++ this->IO_ADDR_W = (void *)IO_ADDR_W;
++}
++
++static int nand_dm350evm_dev_ready(struct mtd_info *mtd)
++{
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ return(emif_addr->NANDFSR) /*& 0x1)*/;
++}
++
++static int nand_dm350evm_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
++{
++ while(!nand_dm350evm_dev_ready(mtd)) {;}
++ *NAND_CE0CLE = NAND_STATUS;
++ return(*NAND_CE0DATA);
++}
++
++static void nand_dm355evm_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ emifregs emif_addr;
++
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ emif_addr->NANDFCR |= (1 << 8);
++}
++
++static u32 nand_dm355evm_readecc(struct mtd_info *mtd, u32 Reg)
++{
++ u32 l = 0;
++ emifregs emif_addr;
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ if (Reg == 1)
++ l = emif_addr->NANDF1ECC;
++ else if (Reg == 2)
++ l = emif_addr->NANDF2ECC;
++ else if (Reg == 3)
++ l = emif_addr->NANDF3ECC;
++ else if (Reg == 4)
++ l = emif_addr->NANDF4ECC;
++
++ return l;
++}
++
++static int nand_dm355evm_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
++ u_char *ecc_code)
++{
++ unsigned int l;
++ int reg;
++ int n;
++ struct nand_chip *this = mtd->priv;
++
++ if (this->eccmode == NAND_ECC_HW12_2048)
++ n = 4;
++ else
++ n = 1;
++
++ reg = 1;
++ while (n--) {
++ l = nand_dm355evm_readecc(mtd, reg);
++ *ecc_code++ = l; // P128e, ..., P1e
++ *ecc_code++ = l >> 16; // P128o, ..., P1o
++ // P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e
++ *ecc_code++ = ((l >> 8) & 0x0f) | ((l >> 20) & 0xf0);
++ reg++;
++ }
++ return 0;
++}
++
++static void nand_dm355evm_gen_true_ecc(u8 *ecc_buf)
++{
++ u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
++
++ ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp) );
++ ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
++ ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
++}
++
++static int nand_dm355evm_compare_ecc(u8 * ecc_data1, /* read from NAND memory */
++ u8 * ecc_data2, /* read from register */
++ u8 * page_data)
++{
++ u32 i;
++ u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
++ u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
++ u8 ecc_bit[24];
++ u8 ecc_sum = 0;
++ u8 find_bit = 0;
++ u32 find_byte = 0;
++ int isEccFF;
++
++ isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
++
++ nand_dm355evm_gen_true_ecc(ecc_data1);
++ nand_dm355evm_gen_true_ecc(ecc_data2);
++
++ for (i = 0; i <= 2; i++) {
++ *(ecc_data1 + i) = ~(*(ecc_data1 + i));
++ *(ecc_data2 + i) = ~(*(ecc_data2 + i));
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp0_bit[i] = *ecc_data1 % 2;
++ *ecc_data1 = *ecc_data1 / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp1_bit[i] = *(ecc_data1 + 1) % 2;
++ *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp2_bit[i] = *(ecc_data1 + 2) % 2;
++ *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp0_bit[i] = *ecc_data2 % 2;
++ *ecc_data2 = *ecc_data2 / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp1_bit[i] = *(ecc_data2 + 1) % 2;
++ *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp2_bit[i] = *(ecc_data2 + 2) % 2;
++ *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
++ }
++
++ for (i = 0; i< 6; i++ )
++ ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
++
++ for (i = 0; i < 8; i++)
++ ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
++
++ for (i = 0; i < 8; i++)
++ ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
++
++ ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
++ ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
++
++ for (i = 0; i < 24; i++)
++ ecc_sum += ecc_bit[i];
++
++ switch (ecc_sum) {
++ case 0:
++ /* Not reached because this function is not called if
++ ECC values are equal */
++ return 0;
++
++ case 1:
++ /* Uncorrectable error */
++ DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
++ return -1;
++
++ case 12:
++ /* Correctable error */
++ find_byte = (ecc_bit[23] << 8) +
++ (ecc_bit[21] << 7) +
++ (ecc_bit[19] << 6) +
++ (ecc_bit[17] << 5) +
++ (ecc_bit[15] << 4) +
++ (ecc_bit[13] << 3) +
++ (ecc_bit[11] << 2) +
++ (ecc_bit[9] << 1) +
++ ecc_bit[7];
++
++ find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
++
++ DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit);
++
++ page_data[find_byte] ^= (1 << find_bit);
++
++ return 0;
++
++ default:
++ if (isEccFF) {
++ if (ecc_data2[0] == 0 && ecc_data2[1] == 0 && ecc_data2[2] == 0)
++ return 0;
++ }
++ DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
++ return -1;
++ }
++}
++
++static int nand_dm355evm_correct_data(struct mtd_info *mtd, u_char *dat,
++ u_char *read_ecc, u_char *calc_ecc)
++{
++ int r = 0;
++#if 0
++ if (memcmp(read_ecc, calc_ecc, 3) != 0) {
++ u_char read_ecc_copy[3], calc_ecc_copy[3];
++ int i;
++
++ for (i = 0; i < 3; i++) {
++ read_ecc_copy[i] = read_ecc[i];
++ calc_ecc_copy[i] = calc_ecc[i];
++ }
++ r = nand_dm355_1bit_compare_ecc(read_ecc_copy, calc_ecc_copy,
++ dat);
++ }
++#endif
++ return r;
++}
++
++/*
++ * 4-bit ECC routines
++ */
++
++/*
++ * Instead of placing the spare data at the end of the page, the 4-bit ECC
++ * hardware generator requires that the page be subdivided into 4 subpages,
++ * each with its own spare data area. This structure defines the format of
++ * each of these subpages.
++ */
++static struct page_layout_item nand_dm355_hw10_512_layout[] = {
++ {.type = ITEM_TYPE_DATA,.length = 512},
++ {.type = ITEM_TYPE_OOB,.length = 6,},
++ {.type = ITEM_TYPE_ECC,.length = 10,},
++ {.type = 0,.length = 0,},
++};
++
++static struct nand_oobinfo nand_dm355_hw10_512_oobinfo = {
++ .useecc = MTD_NANDECC_AUTOPLACE,
++ /*
++ * We actually have 40 bytes of ECC per page, but the nand_oobinfo
++ * structure definition limits us to a maximum of 32 bytes. This
++ * doesn't matter, because out page_layout_item structure definition
++ * determines where our ECC actually goes in the flash page.
++ */
++ .eccbytes = 32,
++ .eccpos = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
++ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
++ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
++ 54, 55,
++ },
++ .oobfree = {{0, 6}, {16, 6}, {32, 6}, {48, 6}},
++};
++
++/*
++ * We should always have a flash-based bad block table. However, if one isn't
++ * found then all blocks will be scanned to look for factory-marked bad blocks.
++ * We supply a null pattern so that no blocks will be detected as bad.
++ */
++static struct nand_bbt_descr nand_dm355_hw10_512_badblock_pattern = {
++ .options = 0,
++ .offs = 0,
++ .len = 0,
++ .pattern = NULL,
++};
++
++/*
++ * When using 4-bit ECC with a 2048-byte data + 64-byte spare page size, the
++ * oob is scattered throughout the page in 4 16-byte chunks instead of being
++ * grouped together at the end of the page. This means that the factory
++ * bad-block markers at offsets 2048 and 2049 will be overwritten when data
++ * is written to the flash. Thus, we cannot use the factory method to mark
++ * or detect bad blocks and must rely on a flash-based bad block table instead.
++ *
++ */
++static int nand_dm355_hw10_512_block_bad(struct mtd_info *mtd, loff_t ofs,
++ int getchip)
++{
++ return 0;
++}
++
++static int nand_dm355_hw10_512_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct nand_chip *this = mtd->priv;
++ int block;
++
++ /* Get block number */
++ block = ((int)ofs) >> this->bbt_erase_shift;
++ if (this->bbt)
++ this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
++
++ /* Do we have a flash based bad block table ? */
++ if (this->options & NAND_USE_FLASH_BBT)
++ return nand_update_bbt(mtd, ofs);
++
++ return 0;
++}
++
++static void nand_dm355_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ struct nand_chip *this = mtd->priv;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++
++ switch (mode) {
++ case NAND_ECC_WRITE:
++ case NAND_ECC_READ:
++ /*
++ * Start a new ECC calculation for reading or writing 512 bytes
++ * of data.
++ */
++ val = (emif_addr->NANDFCR & ~(3 << 4))
++ | (1 << 12);
++ emif_addr->NANDFCR = val;
++ break;
++ case NAND_ECC_WRITEOOB:
++ case NAND_ECC_READOOB:
++ /*
++ * Terminate ECC calculation by performing a dummy read of an
++ * ECC register. Our hardware ECC generator supports including
++ * the OOB in the ECC calculation, but the NAND core code
++ * doesn't really support that. We will only calculate the ECC
++ * on the data; errors in the non-ECC bytes in the OOB will not
++ * be detected or corrected.
++ */
++ val = emif_addr->NANDF1ECC;
++ break;
++ case NAND_ECC_WRITESYN:
++ case NAND_ECC_READSYN:
++ /*
++ * Our ECC calculation has already been terminated, so no need
++ * to do anything here.
++ */
++ break;
++ default:
++ break;
++ }
++}
++
++static u32 nand_dm355_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
++{
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ ecc[0] = (*(dv_reg_p) NAND4BITECC1) & NAND_4BITECC_MASK;
++ ecc[1] = (*(dv_reg_p) NAND4BITECC2) & NAND_4BITECC_MASK;
++ ecc[2] = (*(dv_reg_p) NAND4BITECC3) & NAND_4BITECC_MASK;
++ ecc[3] = (*(dv_reg_p) NAND4BITECC4) & NAND_4BITECC_MASK;
++
++ return 0;
++}
++
++static int nand_dm355_4bit_calculate_ecc(struct mtd_info *mtd,
++ const u_char * dat,
++ u_char * ecc_code)
++{
++ unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
++ unsigned int const1 = 0, const2 = 0;
++ unsigned char count1 = 0;
++
++ /*
++ * Since the NAND_HWECC_SYNDROME option is enabled, this routine is
++ * only called just after the data and oob have been written. The
++ * ECC value calculated by the hardware ECC generator is available
++ * for us to read.
++ */
++ nand_dm355_4bit_readecc(mtd, hw_4ecc);
++
++ /*Convert 10 bit ecc value to 8 bit */
++ for (count1 = 0; count1 < 2; count1++) {
++ const2 = count1 * 5;
++ const1 = count1 * 2;
++
++ /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
++ ecc_code[const2] = hw_4ecc[const1] & 0xFF;
++
++ /*
++ * Take 2 bits as LSB bits from val1 (count1=0) or val5
++ * (count1=1) and 6 bits from val2 (count1=0) or val5 (count1=1)
++ */
++ ecc_code[const2 + 1] =
++ ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
++ 0xFC);
++
++ /*
++ * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
++ * 4 bits from val3 (count1=0) or val6 (count1=1)
++ */
++ ecc_code[const2 + 2] =
++ ((hw_4ecc[const1] >> 22) & 0xF) |
++ ((hw_4ecc[const1 + 1] << 4) & 0xF0);
++
++ /*
++ * Take 6 bits from val3(count1=0) or val6 (count1=1) and
++ * 2 bits from val4 (count1=0) or val7 (count1=1)
++ */
++ ecc_code[const2 + 3] =
++ ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
++ ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
++
++ /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
++ ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
++ }
++
++ return 0;
++}
++
++static int nand_dm355_4bit_compare_ecc(struct mtd_info *mtd, u8 * read_ecc, /* read from NAND */
++ u8 * page_data)
++{
++ struct nand_chip *this = mtd->priv;
++ struct nand_dm355_info *info = this->priv;
++ unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
++ int i;
++ unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
++ unsigned short *pspare = NULL, *pspare1 = NULL;
++ unsigned int numErrors, errorAddress, errorValue;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++
++ /*
++ * Check for an ECC where all bytes are 0xFF. If this is the case, we
++ * will assume we are looking at an erased page and we should ignore the
++ * ECC.
++ */
++ for (i = 0; i < 10; i++) {
++ if (read_ecc[i] != 0xFF)
++ break;
++ }
++ if (i == 10)
++ return 0;
++
++ /* Convert 8 bit in to 10 bit */
++ pspare = (unsigned short *)&read_ecc[2];
++ pspare1 = (unsigned short *)&read_ecc[0];
++ /* Take 10 bits from 0th and 1st bytes */
++ ecc_10bit[0] = (*pspare1) & 0x3FF; /* 10 */
++ /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
++ ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
++ | (((pspare[0]) << 6) & 0x3C0); /* 6 + 4 */
++ /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
++ ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF; /* 10 */
++ /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
++ ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
++ | ((((pspare[1])) << 2) & 0x3FC); /* 2 + 8 */
++ /* Take 8 bits from 5th byte and 2 bits from 6th byte */
++ ecc_10bit[4] = ((pspare[1]) >> 8)
++ | ((((pspare[2])) << 8) & 0x300); /* 8 + 2 */
++ /* Take 6 bits from 6th byte and 4 bits from 7th byte */
++ ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF; /* 10 */
++ /* Take 4 bits from 7th byte and 6 bits from 8th byte */
++ ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
++ | ((((pspare[3])) << 4) & 0x3F0); /* 4 + 6 */
++ /*Take 2 bits from 8th byte and 8 bits from 9th byte */
++ ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF; /* 10 */
++
++ /*
++ * Write the parity values in the NAND Flash 4-bit ECC Load register.
++ * Write each parity value one at a time starting from 4bit_ecc_val8
++ * to 4bit_ecc_val1.
++ */
++ for (i = 7; i >= 0; i--)
++ {
++ *(dv_reg_p)NAND4BITECCLOAD = ecc_10bit[i];
++ }
++
++ /*
++ * Perform a dummy read to the EMIF Revision Code and Status register.
++ * This is required to ensure time for syndrome calculation after
++ * writing the ECC values in previous step.
++ */
++ val = emif_addr->ERCSR;
++
++ /*
++ * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
++ * A syndrome value of 0 means no bit errors. If the syndrome is
++ * non-zero then go further otherwise return.
++ */
++ nand_dm355_4bit_readecc(mtd, hw_4ecc);
++
++ if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
++ hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
++ return 0;
++
++ /*
++ * Clear any previous address calculation by doing a dummy read of an
++ * error address register.
++ */
++ val = *(dv_reg_p)NANDERRADD1;
++
++ /*
++ * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
++ * register to 1.
++ */
++
++ emif_addr->NANDFCR |= (1 << 13);
++
++ /*
++ * Wait for the corr_state field (bits 8 to 11)in the
++ * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
++ */
++ do {
++ iserror = emif_addr->NANDFSR & 0xC00;
++ } while (iserror);
++
++ iserror = emif_addr->NANDFSR;
++ iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
++ iserror = iserror >> 8;
++
++#if 0
++ do {
++ iserror = emif_addr->NANDFSR;
++ iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
++ iserror = iserror >> 8;
++ } while ((ECC_STATE_NO_ERR != iserror) &&
++ (ECC_STATE_TOO_MANY_ERRS != iserror) &&
++ (ECC_STATE_ERR_CORR_COMP_P != iserror) &&
++ (ECC_STATE_ERR_CORR_COMP_N != iserror));
++#endif
++ /*
++ * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
++ * corrected (five or more errors). The number of errors
++ * calculated (err_num field) differs from the number of errors
++ * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
++ * correction complete (errors on bit 8 or 9).
++ * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
++ * complete (error exists).
++ */
++
++ if (iserror == ECC_STATE_NO_ERR)
++ return 0;
++ else if (iserror == ECC_STATE_TOO_MANY_ERRS)
++ {
++ printf("too many erros to be corrected!\n");
++ return -1;
++ }
++
++#if 1
++ numErrors = ((emif_addr->NANDFSR >> 16) & 0x3) + 1;
++
++ /* Read the error address, error value and correct */
++ for (i = 0; i < numErrors; i++) {
++ if (i > 1) {
++ errorAddress =
++ ((*(dv_reg_p)(NANDERRADD2) >>
++ (16 * (i & 1))) & 0x3FF);
++ errorAddress = ((512 + 7) - errorAddress);
++ errorValue =
++ ((*(dv_reg_p)(NANDERRVAL2) >>
++ (16 * (i & 1))) & 0xFF);
++ } else {
++ errorAddress =
++ ((*(dv_reg_p)(NANDERRADD1) >>
++ (16 * (i & 1))) & 0x3FF);
++ errorAddress = ((512 + 7) - errorAddress);
++ errorValue =
++ ((*(dv_reg_p)(NANDERRVAL1) >>
++ (16 * (i & 1))) & 0xFF);
++ }
++ /* xor the corrupt data with error value */
++ if (errorAddress < 512)
++ page_data[errorAddress] ^= errorValue;
++ }
++#else
++ numErrors = ((emif_addr->NANDFSR >> 16) & 0x3);
++ // bit 9:0
++ errorAddress = 519 - (*(dv_reg_p)NANDERRADD1 & (0x3FF));
++ errorValue = (*(dv_reg_p)NANDERRVAL1) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if(numErrors == 0)
++ return numErrors;
++ else {
++ // bit 25:16
++ errorAddress = 519 - ( (*(dv_reg_p)NANDERRADD1 & (0x3FF0000))>>16 );
++ errorValue = (*(dv_reg_p)NANDERRVAL1) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if(numErrors == 1)
++ return numErrors;
++ else {
++ // bit 9:0
++ errorAddress = 519 - (*(dv_reg_p)NANDERRADD2 & (0x3FF));
++ errorValue = (*(dv_reg_p)NANDERRVAL2) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if (numErrors == 2)
++ return numErrors;
++ else {
++ // bit 25:16
++ errorAddress = 519 - ( (*(dv_reg_p)NANDERRADD2 & (0x3FF0000))>>16 );
++ errorValue = (*(dv_reg_p)NANDERRVAL2) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++ }
++ }
++ }
++#endif
++
++ return numErrors;
++}
++
++static int nand_dm355_4bit_correct_data(struct mtd_info *mtd, u_char * dat,
++ u_char * read_ecc, u_char * calc_ecc)
++{
++ int r = 0;
++
++ /*
++ * dat points to 512 bytes of data. read_ecc points to the start of the
++ * oob area for this subpage, so the ecc values start at offset 6.
++ * The calc_ecc pointer is not needed since our caclulated ECC is
++ * already latched in the hardware ECC generator.
++ */
++#if 1
++ r = nand_dm355_4bit_compare_ecc(mtd, read_ecc + 6, dat);
++#endif
++
++ return r;
++}
++int board_nand_init(struct nand_chip *nand)
++{
++#if 0
++ nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
++ nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
++#endif
++ nand->chip_delay = 0;
++ nand->options = NAND_USE_FLASH_BBT /*| NAND_BBT_LASTBLOCK*/;
++// nand->eccmode = NAND_ECC_SOFT;
++#if 0
++ nand->eccmode = NAND_ECC_HW3_512;
++ nand->calculate_ecc = nand_dm355evm_calculate_ecc;
++ nand->correct_data = nand_dm355evm_correct_data;
++ nand->enable_hwecc = nand_dm355evm_enable_hwecc;
++#else
++ nand->eccmode = NAND_ECC_HW10_512;
++ nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME;
++ nand->autooob = &nand_dm355_hw10_512_oobinfo;
++ nand->layout = nand_dm355_hw10_512_layout;
++ nand->calculate_ecc = nand_dm355_4bit_calculate_ecc;
++ nand->correct_data = nand_dm355_4bit_correct_data;
++ nand->enable_hwecc = nand_dm355_4bit_enable_hwecc;
++ //nand->block_bad = nand_dm355_hw10_512_block_bad;
++ nand->block_markbad = nand_dm355_hw10_512_block_markbad;
++ //nand->badblock_pattern =
++ // &nand_dm355_hw10_512_badblock_pattern;
++
++#endif
++ /* Set address of hardware control function */
++ nand->hwcontrol = nand_dm350evm_hwcontrol;
++
++ //nand->dev_ready = nand_dm350evm_dev_ready;
++ //nand->waitfunc = nand_dm350evm_waitfunc;
++
++ return 0;
++}
++
++#else
++#error "U-Boot legacy NAND support not available for DaVinci chips"
++#endif
++#endif /* CFG_USE_NAND */
+diff -Nurd u-boot-1.2.0/board/dm355_evm/timer.c u-boot-1.2.0-leopard/board/dm355_evm/timer.c
+--- u-boot-1.2.0/board/dm355_evm/timer.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/timer.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,72 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++
++#include "timer.h"
++
++/* Use Timer 3&4 (Timer 2) */
++#define TIMER_BASE_ADDR 0x01C21400
++
++dm350_timer_reg *dm350_timer = (dm350_timer_reg *) TIMER_BASE_ADDR;
++
++/* Timer Initialize */
++void inittimer(void)
++{
++ /* disable Timer 1 & 2 timers */
++ dm350_timer->tcr = 0;
++
++ /* Set timers to unchained dual 32 bit timers, Unreset timer34 */
++ dm350_timer->tgcr = 0x0;
++ dm350_timer->tgcr = 0x6;
++
++ /* Program the timer12 counter register - set the prd12 for right count */
++ dm350_timer->tim34 = 0;
++
++ /* The timer is programmed to expire after 0xFFFFFFFF ticks */
++ dm350_timer->prd34 = 0xFFFFFFFF;
++
++ /* Enable timer34 */
++ dm350_timer->tcr = (0x80 << 16); /* Timer34 continously enabled, Timer12 disabled */
++}
++
++/************************************************************
++********************** Reset Processor **********************
++************************************************************/
++#define WDT_BASE_ADDR 0x01C21C00
++
++
++void reset_processor(void)
++{
++ dm350_timer_reg *dm350_wdt = (dm350_timer_reg *) WDT_BASE_ADDR;
++ dm350_wdt->tgcr = 0x00000008;
++ dm350_wdt->tgcr |= 0x00000003;
++ dm350_wdt->tim12 = 0x00000000;
++ dm350_wdt->tim34 = 0x00000000;
++ dm350_wdt->prd12 = 0x00000000;
++ dm350_wdt->prd34 = 0x00000000;
++ dm350_wdt->tcr |= 0x00000040;
++ dm350_wdt->wdtcr |= 0x00004000;
++ dm350_wdt->wdtcr = 0xA5C64000;
++ dm350_wdt->wdtcr = 0xDA7E4000;
++}
+diff -Nurd u-boot-1.2.0/board/dm355_evm/timer.h u-boot-1.2.0-leopard/board/dm355_evm/timer.h
+--- u-boot-1.2.0/board/dm355_evm/timer.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/timer.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,51 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Modifications:
++ * ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#ifndef __TIMER_H__
++#define __TIMER_H__
++
++typedef volatile struct dm350_timer_reg_t
++{
++ unsigned int pid12; /* 0x0 */
++ unsigned int emumgt_clksped;/* 0x4 */
++ unsigned int gpint_en; /* 0x8 */
++ unsigned int gpdir_dat; /* 0xC */
++ unsigned int tim12; /* 0x10 */
++ unsigned int tim34; /* 0x14 */
++ unsigned int prd12; /* 0x18 */
++ unsigned int prd34; /* 0x1C */
++ unsigned int tcr; /* 0x20 */
++ unsigned int tgcr; /* 0x24 */
++ unsigned int wdtcr; /* 0x28 */
++ unsigned int tlgc; /* 0x2C */
++ unsigned int tlmr; /* 0x30 */
++} dm350_timer_reg;
++
++#endif /* __TIMER_H__ */
++
+diff -Nurd u-boot-1.2.0/board/dm355_evm/types.h u-boot-1.2.0-leopard/board/dm355_evm/types.h
+--- u-boot-1.2.0/board/dm355_evm/types.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/types.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,46 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _TYPESH_
++#define _TYPESH_
++
++typedef unsigned long ULONG;
++typedef unsigned short USHORT;
++typedef unsigned long BOOL;
++typedef unsigned int WORD;
++typedef char CHAR;
++typedef unsigned char BYTE, *LPBYTE, UCHAR, *PUCHAR, PBYTE;
++
++#define FALSE 0
++#define TRUE 1
++
++#define NULL 0
++
++typedef unsigned short int Hwd;
++typedef volatile unsigned short int vHwd;
++typedef unsigned short int * Hwdptr;
++typedef volatile unsigned short int * vHwdptr;
++//typedef volatile unsigned int * vHwdptr;
++
++
++#endif
++
+diff -Nurd u-boot-1.2.0/board/dm355_evm/u-boot.lds u-boot-1.2.0-leopard/board/dm355_evm/u-boot.lds
+--- u-boot-1.2.0/board/dm355_evm/u-boot.lds 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_evm/u-boot.lds 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,52 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm926ejs/start.o (.text)
++ *(.text)
++ }
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++ . = ALIGN(4);
++ .data : { *(.data) }
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/Makefile u-boot-1.2.0-leopard/board/dm355_ipnc/Makefile
+--- u-boot-1.2.0/board/dm355_ipnc/Makefile 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/Makefile 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := dm355_ipnc.o flash.o nand.o timer.o
++SOBJS := lowlevel_init.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/config.mk u-boot-1.2.0-leopard/board/dm355_ipnc/config.mk
+--- u-boot-1.2.0/board/dm355_ipnc/config.mk 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/config.mk 2008-01-31 04:18:33.000000000 -0300
+@@ -0,0 +1,25 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++#
++# (C) Copyright 2003
++# Texas Instruments, <www.ti.com>
++# Swaminathan <swami.iyer@ti.com>
++#
++# Davinci EVM board (ARM925EJS) cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# Davinci EVM has 1 bank of 256 MB DDR RAM
++# Physical Address:
++# 8000'0000 to 9000'0000
++#
++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
++# (mem base + reserved)
++#
++# we load ourself to 8100 '0000
++#
++#
++
++#Provide a atleast 16MB spacing between us and the Linux Kernel image
++TEXT_BASE = 0x81080000
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/dm355_ipnc.c u-boot-1.2.0-leopard/board/dm355_ipnc/dm355_ipnc.c
+--- u-boot-1.2.0/board/dm355_ipnc/dm355_ipnc.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/dm355_ipnc.c 2009-02-13 04:25:31.000000000 -0300
+@@ -0,0 +1,671 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++
++#define inw(a) __raw_readw(a)
++#define outw(a,v) __raw_writew(a,v)
++
++
++#define PLL1_PLLM *(volatile unsigned int *)0x01c40910
++#define PLL2_PLLM *(volatile unsigned int *)0x01c40D10
++#define PLL2_DIV2 *(volatile unsigned char *)0x01c40D1C
++#define PLL2_PREDIV *(volatile unsigned int *)0x01C40D14
++#define PLL1_PLLDIV3 *(volatile unsigned int *)0x01C40920
++#define PLL1_POSTDIV *(volatile unsigned int *)0x01C40928
++#define PLL1_PLLDIV4 *(volatile unsigned int *)0x01C40960
++#define SYSTEM_MISC *(volatile unsigned int *)0x01C40038
++#define MACH_DM350_IPNC 1381
++
++#define W_SETUP 0x1 //0~f
++#define W_STROBE 0x3 //0~3f
++#define W_HOLD 0x1 //0~7
++#define R_SETUP 0x1 //0~f
++#define R_STROBE 0x3 //0~3f
++#define R_HOLD 0x1 //0~7
++
++#define TA 3 //0~3
++#define A_SIZE 1 //1:16 bit 0:8bit
++#define DM9000_TIMING W_SETUP<<26 | W_STROBE<<20 | W_HOLD <<17 | R_SETUP<<13 | R_STROBE<<7 | R_HOLD <<4 | TA<<2 | A_SIZE
++
++
++
++/* GIO register */
++#define GIO_BINTEN 0x01C67008 /* GPIO Interrupt Per-Bank Enable Register */
++#define GIO_DIR01 0x01C67010
++#define GIO_OUT_DATA01 0x01C67014
++#define GIO_SET_DATA01 0x01C67018
++#define GIO_CLR_DATA01 0x01C6701C
++#define GIO_SET_RIS_TRIG01 0x01C67024
++#define GIO_SET_FAL_TRIG01 0x01C6702c
++#define GIO_A2CR 0x01e10014
++
++#define GIO_DIR23 0x01C67038
++#define GIO_OUT_DATA23 0x01C6703c
++#define GIO_SET_DATA23 0x01C67040
++#define GIO_CLR_DATA23 0x01C67044
++
++#define GIO_DIR45 (0x01C67060)
++#define GIO_OUT_DATA45 (0x01C67064)
++#define GIO_SET_DATA45 (0x01C67068)
++#define GIO_CLR_DATA45 (0x01C6706C)
++
++#define GIO_DIR06 (0x01C67088)
++#define GIO_OUT_DATA06 (0x01C6708C)
++#define GIO_SET_DATA06 (0x01C67090)
++#define GIO_CLR_DATA06 (0x01C67094)
++
++void davinci_psc_all_enable(void);
++short MSP430_getReg( short reg, unsigned short *regval );
++unsigned int UARTSendInt(unsigned int value);
++
++/*******************************************
++ Routine: delay
++ Description: Delay function
++*******************************************/
++static inline void delay (unsigned long loops)
++{
++__asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*******************************************
++ Routine: board_init
++ Description: Board Initialization routine
++*******************************************/
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++ int i;
++ /* arch number of DaVinci DVDP-Board */
++ gd->bd->bi_arch_number = MACH_DM350_IPNC;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
++#if 1
++#define PINMUX3 0x01C4000C
++ *(volatile unsigned int *)PINMUX3 &= 0XF8FFFFFF; // GIO9 & 10 are IO
++
++ /* Interrupt set GIO9 */
++ *((volatile unsigned int *) GIO_BINTEN) |=0x01; //bank 0
++ /* set GIO9input */
++ *((volatile unsigned int *) GIO_DIR01) |=(1<<9);
++ /* Both edge tigger GIO9 */
++ *((volatile unsigned int *) GIO_SET_RIS_TRIG01) |=(1<<9);
++
++ /* set GIO5 output, imager reset */
++ printf("pull down gio5\n");
++ *((volatile unsigned int *) GIO_DIR01) &= ~(1<<5);
++ *((volatile unsigned int *) GIO_SET_DATA01) &= ~(1<<5); // output Low
++
++ /* set GIO10 output */
++ printf("pull up gio10\n");
++ *((volatile unsigned int *) GIO_DIR01) &= ~(1<<10);
++ *((volatile unsigned int *) GIO_SET_DATA01) |= (1<<10); // output Hi
++
++
++ /* set GIO32 output */
++ *((volatile unsigned int *) GIO_DIR23) &= ~(1<<0);
++ *((volatile unsigned int *) GIO_SET_DATA23) |= (1<<0); // output Hi
++ /* set GIO102 output */
++#define PINMUX0 0x01C40000
++ /* Enable UART1 MUX Lines */
++ *(volatile unsigned int *)PINMUX0 &= ~3;
++ *((volatile unsigned int *) GIO_DIR06) &= ~(1<<6);
++ *((volatile unsigned int *) GIO_SET_DATA06) |= (1<<6); // output Hi
++
++ /* CE01:External Memory setting */
++ /* PLL1 404MHZ EMIF 101MHZ unit 10 ns */
++
++ /* *((volatile unsigned int *) GIO_A2CR) = DM9000_TIMING ; */
++#endif
++ /* Configure MUX settings */
++
++ /* Power on required peripherals
++ davinci_psc_all_enable(); */
++#if 0
++ /* this speeds up your boot a quite a bit. However to make it
++ * work, you need make sure your kernel startup flush bug is fixed.
++ * ... rkw ...
++ */
++ icache_enable ();
++
++#endif
++ inittimer ();
++
++ return 0;
++}
++
++/* PSC Domains */
++
++#define LPSC_VPSSMSTR 0 // VPSS Master LPSC
++#define LPSC_VPSSSLV 1 // VPSS Slave LPSC
++#define LPSC_TPCC 2 // TPCC LPSC
++#define LPSC_TPTC0 3 // TPTC0 LPSC
++#define LPSC_TPTC1 4 // TPTC1 LPSC
++#define PAL_SYS_CLK_MODULE_SPI1 6 /**<SPI1 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_MMCSD1 7 /**<MMCSD1 LPSC Module No*/
++#define LPSC_USB 9 // USB LPSC
++#define PAL_SYS_CLK_MODULE_PWM3 10 /**<PWM3 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_SPI2 11 /**<SPI2 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_RTO 12 /**<TIMER2 LPSC Module No*/
++#define LPSC_DDR_EMIF 13 // DDR_EMIF LPSC
++#define LPSC_AEMIF 14 // AEMIF LPSC
++#define LPSC_MMC_SD 15 // MMC_SD LPSC
++#define LPSC_MEMSTICK 16 // MEMSTICK LPSC
++#define PAL_SYS_CLK_MODULE_ASP 17 /**<AEMIF LPSC Module No*/
++#define LPSC_I2C 18 // I2C LPSC
++#define LPSC_UART0 19 // UART0 LPSC
++#define LPSC_UART1 20 // UART1 LPSC
++#define LPSC_UART2 21 // UART2 LPSC
++#define LPSC_SPI 22 // SPI LPSC
++#define LPSC_PWM0 23 // PWM0 LPSC
++#define LPSC_PWM1 24 // PWM1 LPSC
++#define LPSC_PWM2 25 // PWM2 LPSC
++#define LPSC_GPIO 26 // GPIO LPSC
++#define LPSC_TIMER0 27 // TIMER0 LPSC
++#define LPSC_TIMER1 28 // TIMER1 LPSC
++#define LPSC_TIMER2 29 // TIMER2 LPSC
++#define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM LPSC
++#define LPSC_ARM 31 // ARM LPSC
++#define PAL_SYS_CLK_MODULE_VPSS_DAC 40 /**<VPSS DAC LPSC Module No*/
++
++#define EPCPR *( unsigned int* )( 0x01C41070 )
++#define PTCMD *( unsigned int* )( 0x01C41120 )
++#define PTSTAT *( unsigned int* )( 0x01C41128 )
++#define PDSTAT *( unsigned int* )( 0x01C41200 )
++#define PDSTAT1 *( unsigned int* )( 0x01C41204 )
++#define PDCTL *( unsigned int* )( 0x01C41300 )
++#define PDCTL1 *( unsigned int* )( 0x01C41304 )
++#define VBPR *( unsigned int* )( 0x20000020 )
++
++/**************************************
++ Routine: board_setup_psc_on
++ Description: Enable a PSC domain
++**************************************/
++void board_setup_psc_on( unsigned int domain, unsigned int id )
++{
++ volatile unsigned int* mdstat = ( unsigned int* )( 0x01C41800 + 4 * id );
++ volatile unsigned int* mdctl = ( unsigned int* )( 0x01C41A00 + 4 * id );
++
++ *mdctl |= 0x00000003; // Set PowerDomain to turn on
++
++ if ( ( PDSTAT & 0x00000001 ) == 0 )
++ {
++ PDCTL1 |= 0x1;
++ PTCMD = ( 1 << domain );
++ while ( ( ( ( EPCPR >> domain ) & 1 ) == 0 ) );
++
++ PDCTL1 |= 0x100 ;
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++ else
++ {
++ PTCMD = ( 1<<domain );
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++
++ while( ! ( ( *mdstat & 0x0000001F ) == 0x3 ) );
++}
++
++/**************************************
++ Routine: davinci_psc_all_enable
++ Description: Enable all PSC domains
++**************************************/
++void davinci_psc_all_enable(void)
++{
++#define PSC_ADDR 0x01C41000
++#define PTCMD (PSC_ADDR+0x120)
++#define PTSTAT (PSC_ADDR+0x128)
++
++ unsigned int alwaysOnPdNum = 0, dspPdNum = 1, i;
++
++ /* This function turns on all clocks in the ALWAYSON and DSP Power
++ * Domains. Note this function assumes that the Power Domains are
++ * already on.
++ */
++#if 0
++ /* Write ENABLE (0x3) to all 41 MDCTL[i].NEXT bit fields. */
++ for( i = 0; i < 41; i++){
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) =
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) | 0x3;
++ }
++
++ /* For special workaround: Set MDCTL[i].EMURSTIE to 0x1 for all of the
++ * following Modules. VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) | 0x203;*/
++#endif
++
++ /* For special workaround: Clear MDCTL[i].EMURSTIE to 0x0 for all of the following Modules.
++ * VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*19))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*20) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*20))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*21) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*21))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*18) = *(unsigned int*) (PSC_ADDR+0xA00+4*18) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*28) = *(unsigned int*) (PSC_ADDR+0xA00+4*28) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) & 0x003;*/
++
++ /* Set PTCMD.GO0 to 0x1 to initiate the state transtion for Modules in
++ * the ALWAYSON Power Domain
++ */
++ *(volatile unsigned int*) PTCMD = (1<<alwaysOnPdNum);
++
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! (((*(volatile unsigned int*) PTSTAT >> alwaysOnPdNum) & 0x00000001) == 0));
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*19)& 0x0000001F ) == 0x3));
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*20)& 0x0000001F ) == 0x3));
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*21)& 0x0000001F ) == 0x3));
++ /* Bringup UART out of reset here since NS16650 code that we are using from uBoot
++ * will not do it
++ */
++
++#define UART0PWREMU_MGMT 0x01c20030
++ *(volatile unsigned int*) UART0PWREMU_MGMT |= 0x00008001;
++
++
++#define UART1PWREMU_MGMT 0x01c20430
++ *(volatile unsigned int*) UART1PWREMU_MGMT |= 0x00008001;
++
++#define UART2PWREMU_MGMT 0x01e06030
++ *(volatile unsigned int*) UART2PWREMU_MGMT |= 0x00008001;
++
++#define PINMUX3 0x01C4000C
++ /* Enable UART1 MUX Lines */
++ *(volatile unsigned int *)PINMUX3 |= 0x00600000;
++
++ /* Enable UART2 MUX Lines */
++ *(volatile unsigned int *)PINMUX3 |= 0x0000AA00;
++
++ /* Set the Bus Priority Register to appropriate value */
++ VBPR = 0x20;
++}
++
++/******************************
++ Routine: misc_init_r
++ Description: Misc. init
++******************************/
++int misc_init_r (void)
++{
++ char temp[20], *env=0;
++ char rtcdata[10] = { 4, 1, 0, 0, 0, 0, 0, 0, 0, 0};
++ int clk = 0;
++ unsigned short regval=0 ;
++
++ clk = ((PLL2_PLLM + 1) * 24) / ((PLL2_PREDIV & 0x1F) + 1);
++
++ printf ("ARM Clock :- %dMHz\n", ( ( ((PLL1_PLLM+1)*24 )/(2*(7+1)*((SYSTEM_MISC & 0x2)?2:1 )))) );
++ printf ("DDR Clock :- %dMHz\n", (clk/2));
++
++ /* set GIO5 output, imager reset */
++ printf("pull up gio5\n");
++ *((volatile unsigned int *) GIO_SET_DATA01) |= (1<<5); // output High
++
++ return (0);
++}
++
++/******************************
++ Routine: dram_init
++ Description: Memory Info
++******************************/
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++
++typedef int Bool;
++#define TRUE ((Bool) 1)
++#define FALSE ((Bool) 0)
++
++
++typedef int Int;
++typedef unsigned int Uns; /* deprecated type */
++typedef char Char;
++typedef char * String;
++typedef void * Ptr;
++
++/* unsigned quantities */
++typedef unsigned int Uint32;
++typedef unsigned short Uint16;
++typedef unsigned char Uint8;
++
++/* signed quantities */
++typedef int Int32;
++typedef short Int16;
++typedef char Int8;
++
++/* volatile unsigned quantities */
++typedef volatile unsigned int VUint32;
++typedef volatile unsigned short VUint16;
++typedef volatile unsigned char VUint8;
++
++/* volatile signed quantities */
++typedef volatile int VInt32;
++typedef volatile short VInt16;
++typedef volatile char VInt8;
++
++typedef struct _uart_regs
++{
++ VUint32 RBR;
++ VUint32 IER;
++ VUint32 IIR;
++ VUint32 LCR;
++ VUint32 MCR;
++ VUint32 LSR;
++ VUint32 MSR;
++ VUint32 SCR;
++ VUint8 DLL;
++ VUint8 RSVDO[3];
++ VUint8 DLH;
++ VUint8 RSVD1[3];
++ VUint32 PID1;
++ VUint32 PID2;
++ VUint32 PWREMU_MGNT;
++} uartRegs;
++
++#define THR RBR
++#define FCR IIR
++
++#define UART0 ((uartRegs*) 0x01C20000)
++#define UART1 ((uartRegs*) 0x01C20400)
++
++#define MAXSTRLEN 256
++#define E_PASS 0x00000000u
++#define E_FAIL 0x00000001u
++#define E_TIMEOUT 0x00000002u
++
++
++
++// Send specified number of bytes
++
++Int32 GetStringLen(Uint8* seq)
++{
++ Int32 i = 0;
++ while ((seq[i] != 0) && (i<MAXSTRLEN)){ i++;}
++ if (i == MAXSTRLEN)
++ return -1;
++ else
++ return i;
++}
++
++Uint32 UARTSendData(Uint8* seq, Bool includeNull)
++{
++ Uint32 status = 0;
++ Int32 i,numBytes;
++ Uint32 timerStatus = 0x1000000;
++
++ numBytes = includeNull?(GetStringLen(seq)+1):(GetStringLen(seq));
++
++ for(i=0;i<numBytes;i++) {
++ /* Enable Timer one time */
++ //TIMER0Start();
++ do{
++ status = (UART0->LSR)&(0x60);
++ //timerStatus = TIMER0Status();
++ timerStatus--;
++ } while (!status && timerStatus);
++
++ if(timerStatus == 0)
++ return E_TIMEOUT;
++
++ // Send byte
++ (UART0->THR) = seq[i];
++ }
++ return E_PASS;
++}
++
++Uint32 UARTSendInt(Uint32 value)
++{
++ char seq[9];
++ Uint32 i,shift,temp;
++
++ for( i = 0; i < 8; i++)
++ {
++ shift = ((7-i)*4);
++ temp = ((value>>shift) & (0x0000000F));
++ if (temp > 9)
++ {
++ temp = temp + 7;
++ }
++ seq[i] = temp + 48;
++ seq[i] = temp + 48;
++ }
++ seq[8] = 0;
++ return UARTSendData(seq, FALSE);
++}
++
++#define I2C_BASE 0x01C21000
++#define I2C_OA (I2C_BASE + 0x00)
++#define I2C_IE (I2C_BASE + 0x04)
++#define I2C_STAT (I2C_BASE + 0x08)
++#define I2C_SCLL (I2C_BASE + 0x0c)
++#define I2C_SCLH (I2C_BASE + 0x10)
++#define I2C_CNT (I2C_BASE + 0x14)
++#define I2C_DRR (I2C_BASE + 0x18)
++#define I2C_SA (I2C_BASE + 0x1c)
++#define I2C_DXR (I2C_BASE + 0x20)
++#define I2C_CON (I2C_BASE + 0x24)
++#define I2C_IV (I2C_BASE + 0x28)
++#define I2C_PSC (I2C_BASE + 0x30)
++
++#define I2C_CON_EN (1 << 5) /* I2C module enable */
++#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
++#define I2C_CON_MST (1 << 10) /* Master/slave mode */
++#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
++#define I2C_CON_XA (1 << 8) /* Expand address */
++#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
++#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
++
++#define I2C_STAT_BB (1 << 12) /* Bus busy */
++#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
++#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
++#define I2C_STAT_AAS (1 << 9) /* Address as slave */
++#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
++#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
++#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
++#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
++#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
++#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
++
++static Int16 I2C_init(void );
++static Int16 I2C_close(void );
++static Int16 I2C_reset( void);
++static Int16 I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len );
++static Int16 I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len );
++Int32 i2c_timeout = 0x10000;
++
++Int16 MSP430_getReg( Int16 reg, Uint16 *regval )
++{
++ volatile Int16 retcode;
++ Uint8 msg[2];
++
++ I2C_reset();
++ udelay(10000);
++ /* Send Msg */
++ msg[0] = (Uint8)(reg & 0xff);
++ if ( retcode = I2C_write( 0x25, msg, 1) )
++ {
++ return retcode;
++ }
++
++ if ( retcode = I2C_read( 0x25, msg, 1 ) )
++ {
++ return retcode;
++ }
++
++ *regval = msg[0];
++
++ /* Wait 1 msec */
++ udelay( 1000 );
++
++ return 0;
++}
++
++static Int16 I2C_init( )
++{
++ outw(0, I2C_CON); // Reset I2C
++ outw(26,I2C_PSC); // Config prescaler for 27MHz
++ outw(20,I2C_SCLL); // Config clk LOW for 20kHz
++ outw(20,I2C_SCLH); // Config clk HIGH for 20kHz
++ outw(inw(I2C_CON) | I2C_CON_EN,I2C_CON); // Release I2C from reset
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ *
++ * *
++ * _I2C_close( ) *
++ * *
++ * ------------------------------------------------------------------------ */
++static Int16 I2C_close( )
++{
++ outw(0,I2C_CON); // Reset I2C
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ *
++ * *
++ * _I2C_reset( ) *
++ * *
++ * ------------------------------------------------------------------------ */
++static Int16 I2C_reset( )
++{
++ I2C_close( );
++ I2C_init( );
++ return 0;
++}
++
++static Int16 I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len )
++{
++ Int32 timeout, i, status;
++
++ outw(len, I2C_CNT); // Set length
++ outw(i2c_addr, I2C_SA); // Set I2C slave address
++ outw(0x2000 // Set for Master Write
++ | 0x0200
++ | 0x0400
++ | I2C_CON_EN
++ | 0x4000, I2C_CON );
++
++ udelay( 10 ); // Short delay
++
++ for ( i = 0 ; i < len ; i++ )
++ {
++ outw( data[i],I2C_DXR);; // Write
++
++ timeout = i2c_timeout;
++ do
++ {
++ if ( timeout-- < 0 )
++ {
++ I2C_reset( );
++ return -1;
++ }
++ } while ( ( inw(I2C_STAT) & I2C_STAT_XRDY ) == 0 );// Wait for Tx Ready
++ }
++
++ outw( inw(I2C_CON) | 0x0800, I2C_CON); // Generate STOP
++
++ return 0;
++
++}
++static Int16 I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len )
++{
++ Int32 timeout, i, status;
++
++ outw( len, I2C_CNT); // Set length
++ outw( i2c_addr, I2C_SA); // Set I2C slave address
++ outw( 0x2000 // Set for Master Read
++ | 0x0400
++ | I2C_CON_EN
++ | 0x4000,I2C_CON);
++
++ udelay( 10 ); // Short delay
++
++ for ( i = 0 ; i < len ; i++ )
++ {
++ timeout = i2c_timeout;
++
++ /* Wait for Rx Ready */
++ do
++ {
++ if ( timeout-- < 0 )
++ {
++ I2C_reset( );
++ return -1;
++ }
++ } while ( ( inw(I2C_STAT) & I2C_STAT_RRDY ) == 0 );// Wait for Rx Ready
++
++ data[i] = inw(I2C_DRR); // Read
++ }
++
++ //I2C_ICMDR |= ICMDR_STP; // Generate STOP
++ return 0;
++}
++
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/flash.c u-boot-1.2.0-leopard/board/dm355_ipnc/flash.c
+--- u-boot-1.2.0/board/dm355_ipnc/flash.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/flash.c 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,758 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * (C) Copyright 2003
++ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include "types.h"
++
++#if !defined(CFG_NO_FLASH)
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++#if define (CFG_DM355_IPNC)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define EVMDM355_FLASH_CTL555 *(u16*)( CFG_FLASH_BASE + (0x555 << 1))
++ #define EVMDM355_FLASH_CTL2AA *(u16*)( CFG_FLASH_BASE + (0x2aa << 1))
++ #define EVMDM355_CPLD *(u16*)( CFG_FLASH_BASE + (0x1c000 << 0) )
++ #define EVMDM355_CPLD_MASK 0x3FC000
++
++ #define FLASH_CYCLE1 (0x0555)
++ #define FLASH_CYCLE2 (0x02aa)
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++ #define SWAP(x) __swab16(x)
++#endif
++
++#if defined (CONFIG_TOP860)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++#endif
++
++#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 (0x0aaa << 1)
++ #define FLASH_CYCLE2 (0x0555 << 1)
++ #define FLASH_ID1 0
++ #define FLASH_ID2 2
++ #define FLASH_ID3 0x1c
++ #define FLASH_ID4 0x1E
++#endif
++
++#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0E
++ #define FLASH_ID4 0x0F
++#endif
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size(FPWV *addr, flash_info_t *info);
++static void flash_reset(flash_info_t *info);
++static int write_word(flash_info_t *info, FPWV *dest, FPW data);
++static flash_info_t *flash_get_info(ulong base);
++void inline spin_wheel (void);
++
++/*-----------------------------------------------------------------------
++ * flash_init()
++ *
++ * sets up flash_info and returns size of FLASH (bytes)
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i = 0;
++ u16 mfgid, devid;
++ extern void flash_preinit(void);
++ extern void flash_afterinit(uint, ulong, ulong);
++ ulong flashbase = CFG_FLASH_BASE;
++
++#if 0
++ EVMDM355_CPLD = 0;
++ EVMDM355_FLASH_CTL555 = 0xf0;
++
++ EVMDM355_FLASH_CTL555 = 0xaa;
++ EVMDM355_FLASH_CTL2AA = 0x55;
++ EVMDM355_FLASH_CTL555 = 0x90;
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++ mgfid = *((u16*)CFG_FLASH_BASE);
++ devid = *((u16*)CFG_FLASH_BASE +1);
++
++ *((u8 *)CFG_FLASH_BASE) = 0xf0;
++
++ printf("MFGID %x \n", mfgid);
++ printf("DEVIU %x \n", devid);
++ if ((mfgid != 0x0001) || (devid != 0x227e))
++ return 1;
++#endif
++
++ /*flash_preinit();*/
++
++ /* There is only ONE FLASH device */
++ memset(&flash_info[i], 0, sizeof(flash_info_t));
++ flash_info[i].size =
++ flash_get_size((FPW *)flashbase, &flash_info[i]);
++ size += flash_info[i].size;
++
++#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
++ /* monitor protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_MONITOR_BASE,
++ CFG_MONITOR_BASE+monitor_flash_len-1,
++ flash_get_info(CFG_MONITOR_BASE));
++#endif
++
++#ifdef CFG_ENV_IS_IN_FLASH
++ /* ENV protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
++ flash_get_info(CFG_ENV_ADDR));
++#endif
++
++
++ /*flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);*/
++ return size ? size : 1;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_reset(flash_info_t *info)
++{
++ FPWV *base = (FPWV *)(info->start[0]);
++
++ /* Put FLASH back in read mode */
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *base = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++
++void flash_reset_sector(flash_info_t *info, ULONG addr)
++{
++ // Reset Flash to be in Read Array Mode
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *(FPWV *)addr = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *(FPWV *)addr = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size &&
++ info->start[0] <= base && base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++ uchar *boottype;
++ uchar *bootletter;
++ uchar *fmt;
++ uchar botbootletter[] = "B";
++ uchar topbootletter[] = "T";
++ uchar botboottype[] = "bottom boot sector";
++ uchar topboottype[] = "top boot sector";
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_AMD: printf ("MY AMD "); break;
++#if 0
++ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
++ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
++ case FLASH_MAN_SST: printf ("SST "); break;
++ case FLASH_MAN_STM: printf ("STM "); break;
++#endif
++ case FLASH_MAN_INTEL: printf ("INTEL "); break;
++ default: printf ("Unknown Vendor "); break;
++ }
++
++ /* check for top or bottom boot, if it applies */
++ if (info->flash_id & FLASH_BTYPE) {
++ boottype = botboottype;
++ bootletter = botbootletter;
++ }
++ else {
++ boottype = topboottype;
++ bootletter = topbootletter;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160T:
++ case FLASH_AM160B:
++ fmt = "29LV160%s (16 Mbit, %s)\n";
++ break;
++ case FLASH_AMLV640U:
++ fmt = "29LV640M (64 Mbit)\n";
++ break;
++ case FLASH_AMDLV065D:
++ fmt = "29LV065D (64 Mbit)\n";
++ break;
++ case FLASH_AMLV256U:
++ fmt = "29LV256M (256 Mbit)\n";
++ break;
++ case FLASH_28F128P30T:
++ fmt = "28F128P30T\n";
++ break;
++ case FLASH_S29GL256N:
++ fmt = "S29GL256N\n";
++ break;
++ default:
++ fmt = "Unknown Chip Type\n";
++ break;
++ }
++
++ printf (fmt, bootletter, boottype);
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20,
++ info->sector_count);
++
++ printf (" Sector Start Addresses:");
++
++ for (i=0; i<info->sector_count; ++i) {
++ ulong size;
++ int erased;
++ ulong *flash = (unsigned long *) info->start[i];
++
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++
++ /*
++ * Check if whole sector is erased
++ */
++ size =
++ (i != (info->sector_count - 1)) ?
++ (info->start[i + 1] - info->start[i]) >> 2 :
++ (info->start[0] + info->size - info->start[i]) >> 2;
++
++ for (
++ flash = (unsigned long *) info->start[i], erased = 1;
++ (flash != (unsigned long *) info->start[i] + size) && erased;
++ flash++
++ )
++ erased = *flash == ~0x0UL;
++
++ printf (" %08lX %s %s",
++ info->start[i],
++ erased ? "E": " ",
++ info->protect[i] ? "(RO)" : " ");
++ }
++
++ printf ("\n");
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++
++ulong flash_get_size (FPWV *addr, flash_info_t *info)
++{
++ int i;
++ u16 mfgid, devid, id3,id4;
++
++
++ /* Write auto select command: read Manufacturer ID */
++ /* Write auto select command sequence and test FLASH answer */
++ //EVMDM355_CPLD = 0;
++ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
++#if 0
++ EVMDM355_FLASH_CTL555 = 0xf0;
++
++ EVMDM355_FLASH_CTL555 = 0xaa;
++ EVMDM355_FLASH_CTL2AA = 0x55;
++ EVMDM355_FLASH_CTL555 = 0x90;
++#endif
++
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++
++ switch ( (mfgid = addr[FLASH_ID1]) & 0xff) {
++
++ case (uchar)AMD_MANUFACT:
++ printf ("MY AMD ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_AMD;
++ break;
++
++ case (uchar)INTEL_MANUFACT:
++ printf ("INTEL %x", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++ printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++ break;
++ }
++
++ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
++ if (info->flash_id != FLASH_UNKNOWN) switch (devid = (FPW)addr[FLASH_ID2]) {
++
++ case (FPW)AMD_ID_LV160B:
++ info->flash_id += FLASH_AM160B;
++ info->sector_count = 35;
++ info->size = 0x00200000;
++ info->start[0] = (ulong)addr;
++ info->start[1] = (ulong)addr + 0x4000;
++ info->start[2] = (ulong)addr + 0x6000;
++ info->start[3] = (ulong)addr + 0x8000;
++ for (i = 4; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * (i-3);
++ }
++ break;
++
++ case (FPW)AMD_ID_LV065D:
++ info->flash_id += FLASH_AMDLV065D;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++
++ case (FPW)AMD_ID_MIRROR:
++ /* MIRROR BIT FLASH, read more ID bytes */
++ id3 = (FPW)addr[FLASH_ID3];
++ id4 = (FPW)addr[FLASH_ID4];
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
++ {
++ info->flash_id += FLASH_AMLV640U;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ else if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
++ {
++ /* attention: only the first 16 MB will be used in u-boot */
++ info->flash_id += FLASH_AMLV256U;
++ info->sector_count = 256;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ else
++ {
++ /* This is the default NOR flash for DM355 */
++ info->flash_id += FLASH_S29GL256N;
++ info->sector_count = 256;
++ info->size = 0x02000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ }
++ break;
++ }
++ case (FPW)INTEL_ID_28F128P30T:
++ /* Intel StrataFlash 28F128P30T */
++ info->flash_id += FLASH_28F128P30T;
++ info->sector_count = 131;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ if (i < 127)
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ else
++ info->start[i] = (ulong)addr + 0xfe0000 + 0x8000 * (i-127);
++ }
++ break;
++
++ /* fall thru to here ! */
++ default:
++ printf ("unknown AMD device=%x %x %x",
++ (FPW)addr[FLASH_ID2],
++ (FPW)addr[FLASH_ID3],
++ (FPW)addr[FLASH_ID4]);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0x800000;
++ break;
++ }
++
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ return (info->size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ FPWV *addr;
++ int flag, prot, sect;
++ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
++ ulong start, now, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160B:
++ case FLASH_AMLV640U:
++ break;
++ case FLASH_AMLV256U:
++ break;
++ case FLASH_28F128P30T:
++ break;
++ case FLASH_S29GL256N:
++ break;
++ case FLASH_UNKNOWN:
++ default:
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect=s_first; sect<=s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
++
++ if (info->protect[sect] != 0) /*bmw esteem192e ispan mx1fs2 RPXlite tqm8540
++ protected, skip it */
++ continue;
++
++ printf ("Erasing sector %2d ... ", sect);
++
++ if ( sect == s_first )
++ {
++ addr = (FPWV *)(((info->start[sect]) & EVMDM355_CPLD_MASK) >> 14 );
++ }
++ else
++ {
++ addr += 2;
++ }
++
++ EVMDM355_CPLD = addr;
++
++ if (intel) {
++ *addr = (FPW)0x00600060; /* unlock block setup */
++ *addr = (FPW)0x00d000d0; /* unlock block confirm */
++ *addr = (FPW)0x00500050; /* clear status register */
++ *addr = (FPW)0x00200020; /* erase setup */
++ *addr = (FPW)0x00D000D0; /* erase confirm */
++ while((*addr & 0x80) == 0);
++ printf("done.\n");
++ }
++ else {
++ /* must be AMD style if not Intel */
++ FPWV *base; /* first address in bank */
++
++ base = (FPWV *)(info->start[0]);
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[0] = (FPW)0x00300030; /* erase sector */
++ while (!(*((vHwdptr)base) & 0x80));
++ printf("done.\n");
++ }
++
++
++ }
++
++ EVMDM355_CPLD = 0;
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ printf (" Erase Operation Completed.\n");
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
++ int bytes; /* number of bytes to program in current word */
++ int left; /* number of bytes left to program */
++ int res;
++ ulong cp, wp;
++ int count, i, l, rc, port_width;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++
++ /* get lower word aligned address */
++ wp = (addr & ~1);
++ port_width = 2;
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ cnt -= port_width;
++
++ if (count++ > 0x800) {
++ spin_wheel ();
++ count = 0;
++ }
++ }
++
++ if (cnt == 0) {
++ return (0);
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ return (write_word (info, wp, SWAP (data)));
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word to Flash
++ * A word is 16 or 32 bits, whichever the bus width of the flash bank
++ * (not an individual chip) is.
++ *
++ * returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_word (flash_info_t *info, FPWV *plAddress, FPW ulData)
++{
++ ulong start;
++ int flag;
++ int res = 0; /* result, assume success */
++ FPWV *base; /* first address in flash bank */
++ volatile USHORT *psAddress;
++ volatile USHORT *address_cs;
++ USHORT tmp;
++ ULONG tmp_ptr;
++
++ // Lower WORD.
++ psAddress = (USHORT *)plAddress;
++ tmp_ptr = (ULONG) plAddress;
++ address_cs = (USHORT *) (tmp_ptr & 0xFE000000);
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ {
++ *plAddress = (FPW)0x00400040;
++ *plAddress = ulData;
++ while ((*plAddress & 0x80) == 0);
++ }
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ {
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xAA);
++ *((vHwdptr)address_cs + 0x2AA) = ((Hwd)0x55);
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xA0);
++ *psAddress = ulData;
++ // Wait for ready.
++ while (1)
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ if(tmp & 0x20) // Exceeded Time Limit
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ flash_reset_sector(info, (ULONG) psAddress);
++ return 1;
++ }
++ }
++ }
++ }
++ }
++
++ // Return to read mode
++ flash_reset_sector(info, (ULONG) psAddress);
++
++ // Verify the data.
++ if (*psAddress != ulData)
++ {
++ return 1;
++ printf("Write of one 16-bit word failed\n");
++ }
++ return 0;
++}
++
++void inline spin_wheel (void)
++{
++ static int p = 0;
++ static char w[] = "\\/-";
++
++ printf ("\010%c", w[p]);
++ (++p == 3) ? (p = 0) : 0;
++}
++#endif
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/flash_params.h u-boot-1.2.0-leopard/board/dm355_ipnc/flash_params.h
+--- u-boot-1.2.0/board/dm355_ipnc/flash_params.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/flash_params.h 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,319 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _FLASH_PARAMSH_
++#define _FLASH_PARAMSH_
++//
++//Structs
++//
++typedef struct _PageInfo
++{
++ ULONG reserved;
++ BYTE BlockReserved;
++ BYTE BadBlockFlag;
++ USHORT reserved2;
++}PageInfo, *PPageInfo;
++
++typedef struct
++{
++ ULONG ReturnValue;
++ ULONG ReadAddress;
++ ULONG WriteAddress;
++ ULONG Size;
++} Download_Parms, *PDownload_Parms;
++
++#define NO_ERROR 0
++#define CORRECTED_ERROR 1
++#define ECC_ERROR 2
++#define UNCORRECTED_ERROR 3
++
++
++#define BIT0 0x00000001
++#define BIT1 0x00000002
++#define BIT2 0x00000004
++#define BIT3 0x00000008
++#define BIT4 0x00000010
++#define BIT5 0x00000020
++#define BIT6 0x00000040
++#define BIT7 0x00000080
++#define BIT8 0x00000100
++#define BIT9 0x00000200
++#define BIT10 0x00000400
++#define BIT11 0x00000800
++#define BIT12 0x00001000
++#define BIT13 0x00002000
++#define BIT14 0x00004000
++#define BIT15 0x00008000
++#define BIT16 0x00010000
++#define BIT17 0x00020000
++#define BIT18 0x00040000
++#define BIT19 0x00080000
++#define BIT20 0x00100000
++#define BIT21 0x00200000
++#define BIT22 0x00400000
++#define BIT23 0x00800000
++#define BIT24 0x01000000
++#define BIT25 0x02000000
++#define BIT26 0x04000000
++#define BIT27 0x08000000
++#define BIT28 0x10000000
++#define BIT29 0x20000000
++#define BIT30 0x40000000
++#define BIT31 0x80000000
++
++
++
++// Status bit pattern
++#define STATUS_READY 0x40
++#define STATUS_ERROR 0x01
++//
++//NOR SUPPORT
++//
++// Flash ID Commands INTEL
++#define INTEL_ID_CMD ((Hwd)0x0090) // INTEL ID CMD
++#define INTEL_MANF_ID ((Hwd)0x0089) // INTEL Manf ID expected
++#define INTEL_DEVICE_8T ((Hwd)0x88F1) // INTEL 8Mb top device code
++#define INTEL_DEVICE_8B ((Hwd)0x88F2) // INTEL 8Mb bottom device code
++#define INTEL_DEVICE_16T ((Hwd)0x88F3) // INTEL 16Mb top device code
++#define INTEL_DEVICE_16B ((Hwd)0x88F4) // INTEL 16Mb bottom device code
++#define INTELS_J3_DEVICE_32 ((Hwd)0x0016) // INTEL Strata J3 32Mb device code
++#define INTELS_J3_DEVICE_64 ((Hwd)0x0017) // INTEL Strata J3 64Mb device code
++#define INTELS_J3_DEVICE_128 ((Hwd)0x0018) // INTEL Strata J3 128Mb device code
++#define INTELS_K3_DEVICE_64 ((Hwd)0x8801) // INTEL Strata K3 64Mb device code
++#define INTELS_K3_DEVICE_128 ((Hwd)0x8802) // INTEL Strata K3 128Mb device code
++#define INTELS_K3_DEVICE_256 ((Hwd)0x8803) // INTEL Strata K3 256Mb device code
++#define INTELS_W18_DEVICE_128T ((Hwd)0x8876) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_W18_DEVICE_128B ((Hwd)0x8867) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_128T ((Hwd)0x880C) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_L18_DEVICE_128B ((Hwd)0x880F) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_256T ((Hwd)0x880D) // INTEL Wirless Flash Top 256 Mb device code
++#define INTELS_L18_DEVICE_256B ((Hwd)0x8810) // INTEL Wirless Flash Bottom 256 Mb device code
++#define INTELS_K18_DEVICE_256B ((Hwd)0x8807) // INTEL Wirless Flash Bottom 256 Mb device code
++#define AMD1_DEVICE_ID ((Hwd)0x2253) // AMD29DL323CB
++#define AMD2_DEVICE_ID ((Hwd)0x2249) // AMD29LV160D
++#define AMD3_DEVICE_ID1 ((Hwd)0x2212) // AMD29LV256M
++#define AMD3_DEVICE_ID2 ((Hwd)0x2201) // AMD29LV256M
++// Flash ID Commands FUJITSU (Programs like AMD)
++#define FUJITSU_MANF_ID ((Hwd)0x04) // Fujitsu Manf ID expected
++#define FUJITSU1_DEVICE_ID ((Hwd)0x2253) // MBM29DL323BD
++//Micron Programs Like Intel or Micron
++#define MICRON_MANF_ID ((Hwd)0x002C) // MICRON Manf ID expected
++#define MICRON_MT28F_DEVICE_128T ((Hwd)0x4492) // MICRON Flash device Bottom 128 Mb
++//Samsung Programs like AMD
++#define SAMSUNG_MANF_ID ((Hwd)0x00EC) //SAMSUNG Manf ID expected
++#define SAMSUNG_K8S2815E_128T ((Hwd) 0x22F8) //SAMSUNG NOR Flash device TOP 128 Mb
++// Flash Erase Commands AMD and FUJITSU
++// Flash ID Commands AMD
++#define AMD_ID_CMD0 ((Hwd)0xAA) // AMD ID CMD 0
++#define AMD_CMD0_ADDR 0x555 // AMD CMD0 Offset
++#define AMD_ID_CMD1 ((Hwd)0x55) // AMD ID CMD 1
++#define AMD_CMD1_ADDR 0x2AA // AMD CMD1 Offset
++#define AMD_ID_CMD2 ((Hwd)0x90) // AMD ID CMD 2
++#define AMD_CMD2_ADDR 0x555 // AMD CMD2 Offset
++#define AMD_MANF_ID ((Hwd)0x01) // AMD Manf ID expected
++#define AMD_DEVICE_ID_MULTI ((Hwd)0x227E)// Indicates Multi-Address Device ID
++#define AMD_DEVICE_ID_OFFSET 0x1
++#define AMD_DEVICE_ID_OFFSET1 0x0E // First Addr for Multi-Address ID
++#define AMD_DEVICE_ID_OFFSET2 0x0F // Second Addr for Multi-Address ID
++#define AMD_DEVICE_RESET ((Hwd)0x00F0) // AMD Device Reset Command
++#define AMD_ERASE_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_CMD3 ((Hwd)0xAA) // AMD29LV017B Erase CMD 3
++#define AMD_ERASE_CMD4 ((Hwd)0x55) // AMD29LV017B Erase CMD 4
++#define AMD_ERASE_CMD5 ((Hwd)0x10) // AMD29LV017B Erase CMD 5
++#define AMD_ERASE_DONE ((Hwd)0xFFFF) // AMD29LV017B Erase Done
++#define AMD_ERASE_BLK_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_BLK_CMD3 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD4 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD5 ((Hwd)0x30)
++#define AMD_PROG_CMD0 ((Hwd)0xAA)
++#define AMD_PROG_CMD1 ((Hwd)0x55)
++#define AMD_PROG_CMD2 ((Hwd)0xA0)
++#define AMD2_ERASE_CMD0 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 0
++#define AMD2_ERASE_CMD1 ((Hwd)0x0055) // AMD29DL800B Erase CMD 1
++#define AMD2_ERASE_CMD2 ((Hwd)0x0080) // AMD29DL800B Erase CMD 2
++#define AMD2_ERASE_CMD3 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 3
++#define AMD2_ERASE_CMD4 ((Hwd)0x0055) // AMD29DL800B Erase CMD 4
++#define AMD2_ERASE_CMD5 ((Hwd)0x0030) // AMD29DL800B Erase CMD 5
++#define AMD2_ERASE_DONE ((Hwd)0x00FF) // AMD29DL800B Erase Done
++#define AMD_WRT_BUF_LOAD_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_LOAD_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_LOAD_CMD2 ((Hwd)0x25)
++#define AMD_WRT_BUF_CONF_CMD0 ((Hwd)0x29)
++#define AMD_WRT_BUF_ABORT_RESET_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_ABORT_RESET_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_ABORT_RESET_CMD2 ((Hwd)0xF0)
++// Flash Erase Commands INTEL
++#define INTEL_ERASE_CMD0 ((Hwd)0x0020) // INTEL Erase CMD 0
++#define INTEL_ERASE_CMD1 ((Hwd)0x00D0) // INTEL Erase CMD 1
++#define INTEL_ERASE_DONE ((Hwd)0x0080) // INTEL Erase Done
++#define INTEL_READ_MODE ((Hwd)0x00FF) // INTEL Read Array Mode
++#define STRATA_READ 0x4
++#define STRATA_WRITE 0x8
++// Flash Block Information
++// Intel Burst devices:
++// 2MB each (8 8KB [param] and 31 64KB [main] blocks each) for 8MB total
++#define NUM_INTEL_BURST_BLOCKS 8
++#define PARAM_SET0 0
++#define MAIN_SET0 1
++#define PARAM_SET1 2
++#define MAIN_SET1 3
++#define PARAM_SET2 4
++#define MAIN_SET2 5
++#define PARAM_SET3 6
++#define MAIN_SET3 7
++// Intel Strata devices:
++// 4MB each (32 128KB blocks each) for 8MB total
++// 8MB each (64 128KB blocks each) for 16MB total
++// 16MB each (128 128KB blocks each) for 32MB total
++#define NUM_INTEL_STRATA_BLOCKS 8
++#define BLOCK_SET0 0
++#define BLOCK_SET1 1
++#define BLOCK_SET2 2
++#define BLOCK_SET3 3
++#define BLOCK_SET4 4
++#define BLOCK_SET5 5
++#define BLOCK_SET6 6
++#define BLOCK_SET7 7
++// For AMD Flash
++#define NUM_AMD_SECTORS 8 // Only using the first 8 8-KB sections (64 KB Total)
++#define AMD_ADDRESS_CS_MASK 0xFE000000 //--AMD-- Set-up as 0xFE000000 per Jon Hunter (Ti)
++// Flash Types
++enum NORFlashType {
++ FLASH_NOT_FOUND,
++ FLASH_UNSUPPORTED,
++ FLASH_AMD_LV017_2MB, // (AMD AM29LV017B-80RFC/RE)
++ FLASH_AMD_DL800_1MB_BOTTOM, // (AMD AM29DL800BB-70EC)
++ FLASH_AMD_DL800_1MB_TOP, // (AMD AM29DL800BT-70EC)
++ FLASH_AMD_DL323_4MB_BOTTOM, // (AMD AM29DL323CB-70EC)
++ FLASH_AMD_DL323_4MB_TOP, // (AMD AM29DL323BT-70EC)
++ FLASH_AMD_LV160_2MB_BOTTOM,
++ FLASH_AMD_LV160_2MB_TOP,
++ FLASH_AMD_LV256M_32MB, // (AMD AM29LV256MH/L)
++ FLASH_INTEL_BURST_8MB_BOTTOM, // (Intel DT28F80F3B-95)
++ FLASH_INTEL_BURST_8MB_TOP, // (Intel DT28F80F3T-95)
++ FLASH_INTEL_BURST_16MB_BOTTOM, // (Intel DT28F160F3B-95)
++ FLASH_INTEL_BURST_16MB_TOP, // (Intel DT28F160F3T-95)
++ FLASH_INTEL_STRATA_J3_4MB, // (Intel DT28F320J3A)
++ FLASH_INTEL_STRATA_J3_8MB, // (Intel DT28F640J3A)
++ FLASH_INTEL_STRATA_J3_16MB, // (Intel DT28F128J3A)
++ FLASH_FUJITSU_DL323_4MB_BOTTOM, // (Fujitsu DL323 Bottom
++ FLASH_INTEL_STRATA_K3_8MB, // (Intel 28F64K3C115)
++ FLASH_INTEL_STRATA_K3_16MB, // (Intel 28F128K3C115)
++ FLASH_INTEL_STRATA_K3_32MB, // (Intel 28F256K3C115)
++ FLASH_INTEL_W18_16MB_TOP, // (Intel 28F128W18T) }
++ FLASH_INTEL_W18_16MB_BOTTOM, // (Intel 28F128W18B) }
++ FLASH_INTEL_L18_16MB_TOP, // (Intel 28F128L18T) }
++ FLASH_INTEL_L18_16MB_BOTTOM, // (Intel 28F128L18B) }
++ FLASH_INTEL_L18_32MB_TOP, // (Intel 28F256L18T) }
++ FLASH_INTEL_L18_32MB_BOTTOM, // (Intel 28F256L18B) }
++ FLASH_INTEL_K18_32MB_BOTTOM, // (Intel 28F256K18B) }
++ FLASH_MICRON_16MB_TOP, // (Micron MT28F160C34 )
++ FLASH_SAMSUNG_16MB_TOP // (Samsung K8S281ETA)
++};
++////NAND SUPPORT
++//
++enum NANDFlashType {
++ NANDFLASH_NOT_FOUND,
++ NANDFLASH_SAMSUNG_32x8_Q, // (Samsung K9F5608Q0B)
++ NANDFLASH_SAMSUNG_32x8_U, // (Samsung K9F5608U0B)
++ NANDFLASH_SAMSUNG_16x16_Q, // (Samsung K9F5616Q0B)
++ NANDFLASH_SAMSUNG_16x16_U, // (Samsung K9F5616U0B)
++ NANDFLASH_SAMSUNG_16x8_U // (Samsung K9F1G08QOM)
++};
++// Samsung Manufacture Code
++#define SAMSUNG_MANUFACT_ID 0xEC
++// Samsung Nand Flash Device ID
++#define SAMSUNG_K9F5608Q0B 0x35
++#define SAMSUNG_K9F5608U0B 0x75
++#define SAMSUNG_K9F5616Q0B 0x45
++#define SAMSUNG_K9F5616U0B 0x55
++// MACROS for NAND Flash support
++// Flash Chip Capability
++#define NUM_BLOCKS 0x800 // 32 MB On-board NAND flash.
++#define PAGE_SIZE 512
++#define SPARE_SIZE 16
++#define PAGES_PER_BLOCK 32
++#define PAGE_TO_BLOCK(page) ((page) >> 5 )
++#define BLOCK_TO_PAGE(block) ((block) << 5 )
++#define FILE_TO_PAGE_SIZE(fs) ((fs / PAGE_SIZE) + ((fs % PAGE_SIZE) ? 1 : 0))
++// For flash chip that is bigger than 32 MB, we need to have 4 step address
++#ifdef NAND_SIZE_GT_32MB
++#define NEED_EXT_ADDR 1
++#else
++#define NEED_EXT_ADDR 0
++#endif
++// Nand flash block status definitions.
++#define BLOCK_STATUS_UNKNOWN 0x01
++#define BLOCK_STATUS_BAD 0x02
++#define BLOCK_STATUS_READONLY 0x04
++#define BLOCK_STATUS_RESERVED 0x08
++#define BLOCK_RESERVED 0x01
++#define BLOCK_READONLY 0x02
++#define BADBLOCKMARK 0x00
++// NAND Flash Command. This appears to be generic across all NAND flash chips
++#define CMD_READ 0x00 // Read
++#define CMD_READ1 0x01 // Read1
++#define CMD_READ2 0x50 // Read2
++#define CMD_READID 0x90 // ReadID
++#define CMD_WRITE 0x80 // Write phase 1
++#define CMD_WRITE2 0x10 // Write phase 2
++#define CMD_ERASE 0x60 // Erase phase 1
++#define CMD_ERASE2 0xd0 // Erase phase 2
++#define CMD_STATUS 0x70 // Status read
++#define CMD_RESET 0xff // Reset
++//
++//Prototpyes
++//
++// NOR Flash Dependent Function Pointers
++void (*User_Hard_Reset_Flash)(void);
++void (*User_Soft_Reset_Flash)(unsigned long addr);
++void (*User_Flash_Erase_Block)(unsigned long addr);
++void (*User_Flash_Erase_All)(unsigned long addr);
++void (*User_Flash_Write_Entry)(void);
++int (*User_Flash_Write)(unsigned long *addr, unsigned short data);
++int (*User_Flash_Optimized_Write)(unsigned long *addr, unsigned short data[], unsigned long);
++void (*User_Flash_Write_Exit)(void);
++// Flash AMD Device Dependent Routines
++void AMD_Hard_Reset_Flash(void);
++void AMD_Soft_Reset_Flash(unsigned long);
++void AMD_Flash_Erase_Block(unsigned long);
++void AMD_Flash_Erase_All(unsigned long);
++int AMD_Flash_Write(unsigned long *, unsigned short);
++int AMD_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++void AMD_Write_Buf_Abort_Reset_Flash( unsigned long plAddress );
++// Flash Intel Device Dependent Routines
++void INTEL_Hard_Reset_Flash(void);
++void INTEL_Soft_Reset_Flash(unsigned long addr);
++void INTEL_Flash_Erase_Block(unsigned long);
++int INTEL_Flash_Write(unsigned long *addr, unsigned short data);
++int INTEL_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++
++//General Functions
++void Flash_Do_Nothing(void);
++
++#endif
++
++
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/lowlevel_init.S u-boot-1.2.0-leopard/board/dm355_ipnc/lowlevel_init.S
+--- u-boot-1.2.0/board/dm355_ipnc/lowlevel_init.S 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/lowlevel_init.S 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,766 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2003
++ * Texas Instruments, <www.ti.com>
++ * Kshitij Gupta <Kshitij@ti.com>
++ *
++ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
++ *
++ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Swaminathan S, Nov 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#if defined(CONFIG_OMAP1610)
++#include <./configs/omap1510.h>
++#endif
++
++_TEXT_BASE:
++ .word TEXT_BASE /* sdram load addr from config.mk */
++
++.global reset_cpu
++reset_cpu:
++ bl reset_processor
++
++
++.globl lowlevel_init
++lowlevel_init:
++ /*mov pc, lr*/
++
++ /*------------------------------------------------------*
++ * mask all IRQs by setting all bits in the EINT default *
++ *------------------------------------------------------*/
++ mov r1, #0x00000000
++ ldr r0, =EINT_ENABLE0
++ str r1, [r0]
++ ldr r0, =EINT_ENABLE1
++ str r1, [r0]
++
++ /*------------------------------------------------------*
++ * Put the GEM in reset *
++ *------------------------------------------------------*/
++
++ /* Put the GEM in reset */
++ /* bhavinp: commented: No GEM in DM350*/
++#if 0
++ LDR R8, PSC_GEM_FLAG_CLEAR
++ LDR R6, MDCTL_GEM
++ LDR R7, [R6]
++ AND R7, R7, R8
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x2
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStopGem:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x2
++ CMP R7, #0x0
++ BNE checkStatClkStopGem
++
++ /* Check for GEM Reset Completion */
++checkGemStatClkStop:
++ LDR R6, MDSTAT_GEM
++ LDR R7, [R6]
++ AND R7, R7, #0x100
++ CMP R7, #0x0
++ BNE checkGemStatClkStop
++
++ /* Do this for enabling a WDT initiated reset this is a workaround
++ for a chip bug. Not required under normal situations */
++ LDR R6, P1394
++ MOV R10, #0x0
++ STR R10, [R6]
++#endif //bhavinp: commented: End
++ /*------------------------------------------------------*
++ * Enable L1 & L2 Memories in Fast mode *
++ *------------------------------------------------------*/
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, MMARG_BRF0
++ LDR R10, MMARG_BRF0_VAL
++ STR R10, [R6]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++ /*------------------------------------------------------*
++ * DDR2 PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R10, #0x0
++ LDR R6, PLL2_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R10, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++WaitPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitPPL2Loop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL2_PLLM
++ /*MOV R2, #0x13 Orig value */
++ /*MOV R2, #0xB 165MHz */
++ /*MOV R2, #0xD 189 MHz */
++ MOV R2, #0x17 /* 162 MHz */
++ STR R2, [R6] /* R2 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV2
++ MOV R3, #0x1 /* Orig */
++ /*MOV R3, #0x0*/
++ STR R3, [R6] /* R3 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV1
++ /*MOV R4, #0x9 Orig */
++ /*MOV R4, #0x5 165MHz */
++ /*MOV R4, #0x6 189 MHz */
++ MOV R4, #0xB /* 54 MHz */
++ STR R4, [R6] /* R4 */
++
++ /* PLL2 DIV1 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV2
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop_0:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop_0
++
++ /* PLL2 DIV2 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV1
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0x218
++ResetPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetPPL2Loop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++PLL2Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL2Lock
++
++ /* Enable the PLL */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkStop
++
++ /*------------------------------------------------------*
++ * Program DDR2 MMRs for 162MHz Setting *
++ *------------------------------------------------------*/
++
++ /* Program PHY Control Register */
++ LDR R6, DDRCTL
++ LDR R7, DDRCTL_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM Bank Config Register */
++ LDR R6, SDCFG
++ LDR R7, SDCFG_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-0 Config Register */
++ LDR R6, SDTIM0
++ LDR R7, SDTIM0_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDTIM1
++ LDR R7, SDTIM1_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program the SDRAM Bang Config Control Register */
++ LDR R10, MASK_VAL
++ LDR R8, SDCFG
++ LDR R9, SDCFG_VAL
++ AND R9, R9, R10
++ STR R9, [R8]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDREF
++ LDR R7, SDREF_VAL
++ STR R7, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Issue a Dummy DDR2 read/write */
++ LDR R8, DDR2_VAL
++ LDR R7, DUMMY_VAL
++ STR R7, [R8]
++ LDR R7, [R8]
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x1
++ BNE checkDDRStatClkStop2
++
++ /*------------------------------------------------------*
++ * Turn DDR2 Controller Clocks On *
++ *------------------------------------------------------*/
++
++ /* Enable the DDR2 LPSC Module */
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkEn2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkEn2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkEn2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkEn2
++
++ /* DDR Writes and Reads */
++ LDR R6, CFGTEST
++ MOV R3, #0x1
++ STR R3, [R6] /* R3 */
++
++ /*------------------------------------------------------*
++ * System PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R2, #0x0
++ LDR R6, PLL1_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R2, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++
++WaitLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitLoop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Disable the PLL */
++ ORR R8, R8, #0x10
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL1_PLLM
++ /*MOV R3, #0x10 As per Amit, PLL should be in normal mode i.e X by 16 */
++ /*MOV R3, #0x11 As per Ebby 486 MHz */
++ /*MOV R3, #0x14 For 567MHz */
++ MOV R3, #0x15 /* For 594MHz */
++ STR R3, [R6]
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0xFF
++
++ResetLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetLoop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL1_CTL
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++
++PLL1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL1Lock
++
++ /* Enable the PLL */
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ nop
++ nop
++ nop
++ nop
++
++ /*------------------------------------------------------*
++ * AEMIF configuration for NOR Flash (double check) *
++ *------------------------------------------------------*/
++ LDR R0, _PINMUX0
++ LDR R1, _DEV_SETTING
++ STR R1, [R0]
++
++ LDR R0, WAITCFG
++ LDR R1, WAITCFG_VAL
++ LDR R2, [R0]
++ ORR R2, R2, R1
++ STR R2, [R0]
++
++ LDR R0, ACFG3
++ LDR R1, ACFG3_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG4
++ LDR R1, ACFG4_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG5
++ LDR R1, ACFG5_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ /*--------------------------------------*
++ * VTP manual Calibration *
++ *--------------------------------------*/
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR0
++ STR R1, [R0]
++
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR1
++ STR R1, [R0]
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTPLock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTPLock
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, DDRVTPR
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ AND R8, R7, #0x3E0
++ ORR R8, R7, R8
++ LDR R7, VTP_RECAL
++ ORR R8, R7, R8
++ LDR R7, VTP_EN
++ ORR R8, R7, R8
++ STR R8, [R0]
++
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTP1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTP1Lock
++
++ LDR R1, [R0]
++ LDR R2, VTP_MASK
++ AND R2, R1, R2
++ STR R2, [R0]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++
++
++ /* Start MPU Timer 1 */
++/* MOV R10, #0x1AFFFFFF
++
++WaitRam:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitRam
++*/
++
++ /* back to arch calling code */
++ mov pc, lr
++
++ /* the literal pools origin */
++ .ltorg
++
++REG_TC_EMIFS_CONFIG: /* 32 bits */
++ .word 0xfffecc0c
++REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
++ .word 0xfffecc10
++REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
++ .word 0xfffecc14
++REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
++ .word 0xfffecc18
++REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
++ .word 0xfffecc1c
++
++_PINMUX0: .word 0x01C40000 /* Device Configuration Registers */
++_PINMUX1: .word 0x01C40004 /* Device Configuration Registers */
++
++_DEV_SETTING: .word 0x00000C1F
++
++AEMIF_BASE_ADDR: .word 0x01E10000
++WAITCFG: .word 0x01E10004
++ACFG2: .word 0x01E10010
++ACFG3: .word 0x01E10014
++ACFG4: .word 0x01E10018
++ACFG5: .word 0x01E1001C
++
++WAITCFG_VAL: .word 0x0
++ACFG2_VAL: .word 0x3FFFFFFD
++ACFG3_VAL: .word 0x3FFFFFFD
++ACFG4_VAL: .word 0x3FFFFFFD
++ACFG5_VAL: .word 0x3FFFFFFD
++
++MDCTL_DDR2: .word 0x01C41A34
++PTCMD: .word 0x01C41120
++PTSTAT: .word 0x01C41128
++MDSTAT_DDR2: .word 0x01C41834
++
++MDCTL_TPCC: .word 0x01C41A08
++MDSTAT_TPCC: .word 0x01C41808
++
++MDCTL_TPTC0: .word 0x01C41A0C
++MDSTAT_TPTC0: .word 0x01C4180C
++
++MDCTL_TPTC1: .word 0x01C41A10
++MDSTAT_TPTC1: .word 0x01C41810
++
++DDR2DEBUG: .word 0x8FFFF000
++
++/* EINT0 register */
++EINT_ENABLE0:
++ .word 0x01c48018
++
++/* EINT1 register */
++EINT_ENABLE1:
++ .word 0x01c4801C
++
++CLEAR_FLAG: .word 0xFFFFFFFF
++EDMA_PARAM0_D_S_BIDX_VAL: .word 0x00010001
++PSC_FLAG_CLEAR: .word 0xFFFFFFE0
++PSC_GEM_FLAG_CLEAR: .word 0xFFFFFEFF
++MDCTL_TPCC_SYNC: .word 0x01C41A08
++MDSTAT_TPCC_SYNC: .word 0x01C41808
++
++MDCTL_TPTC0_SYNC: .word 0x01C41A0C
++MDSTAT_TPTC0_SYNC: .word 0x01C4180C
++
++MDCTL_TPTC1_SYNC: .word 0x01C41A10
++MDSTAT_TPTC1_SYNC: .word 0x01C41810
++
++PTCMD_SYNC: .word 0x01C41120
++PTSTAT_SYNC: .word 0x01C41128
++DATA_MAX: .word 0x0000FFFF
++SPIN_ADDR: .word 0x00003FFC /* ARM PC value(B $) for the DSP Test cases */
++SPIN_OPCODE: .word 0xEAFFFFFE
++
++/* Interrupt Clear Register */
++FIQ0_CLEAR: .word 0x01C48000
++FIQ1_CLEAR: .word 0x01C48004
++IRQ0_CLEAR: .word 0x01C48008
++IRQ1_CLEAR: .word 0x01C4800C
++
++/* DDR2 MMR & CONFIGURATION VALUES for 75 MHZ */
++DDRCTL: .word 0x200000E4
++SDREF: .word 0x2000000C
++SDCFG: .word 0x20000008
++SDTIM0: .word 0x20000010
++SDTIM1: .word 0x20000014
++SDSTAT: .word 0x20000004
++VTPIOCR: .word 0x200000F0 /* VTP IO Control register */
++DDRVTPR: .word 0x01C42030 /* DDR VPTR MMR */
++DFT_ENABLE: .word 0x01C4004C
++VTP_MMR0: .word 0x201F
++VTP_MMR1: .word 0xA01F
++PCH_MASK: .word 0x3E0
++VTP_LOCK_COUNT: .word 0x5b0
++VTP_MASK: .word 0xFFFFDFFF
++VTP_RECAL: .word 0x40000
++VTP_EN: .word 0x02000
++
++
++CFGTEST: .word 0x80010000
++
++/* original values
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00008832
++MASK_VAL: .word 0x00000FFF
++SDTIM0_VAL_135MHz: .word 0x30923A91
++SDTIM1_VAL_135MHz: .word 0x0019c722
++SDREF_VAL: .word 0x000005c3
++*/
++
++/* 162MHz as per GEL file for DVEVM with Micron DDR2 SDRAM */
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00178632 /* CL=3 for MT47H64M16BT-5E */
++MASK_VAL: .word 0xFFFF7FFF
++SDTIM0_VAL_162MHz: .word 0x28923211
++SDTIM1_VAL_162MHz: .word 0x0016c722
++SDREF_VAL: .word 0x000004F0
++
++/* GEM Power Up & LPSC Control Register */
++CHP_SHRTSW: .word 0x01C40038
++
++PD1_CTL: .word 0x01C41304
++EPCPR: .word 0x01C41070
++EPCCR: .word 0x01C41078
++MDCTL_GEM: .word 0x01C41A9C
++MDSTAT_GEM: .word 0x01C4189C
++MDCTL_IMCOP: .word 0x01C41AA0
++MDSTAT_IMCOP: .word 0x01C418A0
++
++PTCMD_0: .word 0x01C41120
++PTSTAT_0: .word 0x01C41128
++P1394: .word 0x01C41a20
++
++PLL_CLKSRC_MASK: .word 0xFFFFFEFF /* Mask the Clock Mode bit and it is programmble through the run script */
++PLL_ENSRC_MASK: .word 0xFFFFFFDF /* Select the PLLEN source */
++PLL_BYPASS_MASK: .word 0xFFFFFFFE /* Put the PLL in BYPASS, eventhough the device */
++PLL_RESET_MASK: .word 0xFFFFFFF7 /* Put the PLL in Reset Mode */
++PLL_PWRUP_MASK: .word 0xFFFFFFFD /* PLL Power up Mask Bit */
++PLL_DISABLE_ENABLE_MASK: .word 0xFFFFFFEF /* Enable the PLL from Disable */
++PLL_LOCK_COUNT: .word 0x2000
++
++/* PLL1-SYSTEM PLL MMRs */
++PLL1_CTL: .word 0x01C40900
++PLL1_PLLM: .word 0x01C40910
++
++/* PLL2-SYSTEM PLL MMRs */
++PLL2_CTL: .word 0x01C40D00
++PLL2_PLLM: .word 0x01C40D10
++PLL2_DIV2: .word 0x01C40D1C
++PLL2_DIV1: .word 0x01C40D18
++PLL2_PLLCMD: .word 0x01C40D38
++PLL2_PLLSTAT: .word 0x01C40D3C
++PLL2_BPDIV: .word 0x01C40D2C
++PLL2_DIV_MASK: .word 0xFFFF7FFF
++
++
++MDCTL_DDR2_0: .word 0x01C41A34
++MDSTAT_DDR2_0: .word 0x01C41834
++DLLPWRUPMASK: .word 0xFFFFFFEF
++DDR2_ADDR: .word 0x80000000
++
++DFT_BASEADDR: .word 0x01C42000
++MMARG_BRF0: .word 0x01C42010 /* BRF margin mode 0 (Read / write)*/
++MMARG_G10: .word 0x01C42018 /*GL margin mode 0 (Read / write)*/
++MMARG_BRF0_VAL: .word 0x00444400
++DDR2_VAL: .word 0x80000000
++DUMMY_VAL: .word 0xA55AA55A
++
++/* command values */
++.equ CMD_SDRAM_NOP, 0x00000000
++.equ CMD_SDRAM_PRECHARGE, 0x00000001
++.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
++.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/nand.c u-boot-1.2.0-leopard/board/dm355_ipnc/nand.c
+--- u-boot-1.2.0/board/dm355_ipnc/nand.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/nand.c 2008-05-20 03:57:42.000000000 -0300
+@@ -0,0 +1,830 @@
++/*
++ * NAND driver for TI DaVinci based boards.
++ *
++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
++ *
++ * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
++ */
++
++/*
++ *
++ * linux/drivers/mtd/nand/nand_dm355.c
++ *
++ * NAND Flash Driver
++ *
++ * Copyright (C) 2006 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ * Overview:
++ * This is a device driver for the NAND flash device found on the
++ * DaVinci board which utilizes the Samsung k9k2g08 part.
++ *
++ Modifications:
++ ver. 1.0: Feb 2005, Vinod/Sudhakar
++ -
++ *
++ */
++
++#include <common.h>
++
++#if (CONFIG_COMMANDS & CFG_CMD_NAND)
++#if !defined(CFG_NAND_LEGACY)
++
++#include <asm/arch/types.h>
++//#include "soc.h"
++#include <nand.h>
++#include <asm/arch/nand_defs.h>
++#include <asm/arch/emif_defs.h>
++
++#define NAND_Ecc_P1e (1 << 0)
++#define NAND_Ecc_P2e (1 << 1)
++#define NAND_Ecc_P4e (1 << 2)
++#define NAND_Ecc_P8e (1 << 3)
++#define NAND_Ecc_P16e (1 << 4)
++#define NAND_Ecc_P32e (1 << 5)
++#define NAND_Ecc_P64e (1 << 6)
++#define NAND_Ecc_P128e (1 << 7)
++#define NAND_Ecc_P256e (1 << 8)
++#define NAND_Ecc_P512e (1 << 9)
++#define NAND_Ecc_P1024e (1 << 10)
++#define NAND_Ecc_P2048e (1 << 11)
++
++#define NAND_Ecc_P1o (1 << 16)
++#define NAND_Ecc_P2o (1 << 17)
++#define NAND_Ecc_P4o (1 << 18)
++#define NAND_Ecc_P8o (1 << 19)
++#define NAND_Ecc_P16o (1 << 20)
++#define NAND_Ecc_P32o (1 << 21)
++#define NAND_Ecc_P64o (1 << 22)
++#define NAND_Ecc_P128o (1 << 23)
++#define NAND_Ecc_P256o (1 << 24)
++#define NAND_Ecc_P512o (1 << 25)
++#define NAND_Ecc_P1024o (1 << 26)
++#define NAND_Ecc_P2048o (1 << 27)
++
++#define TF(value) (value ? 1 : 0)
++
++#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0 )
++#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1 )
++#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2 )
++#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3 )
++#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4 )
++#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5 )
++#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6 )
++#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7 )
++
++#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0 )
++#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1 )
++#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2 )
++#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3 )
++#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4 )
++#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5 )
++#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6 )
++#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7 )
++
++#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0 )
++#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1 )
++#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2 )
++#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3 )
++#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4 )
++#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5 )
++#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6 )
++#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7 )
++
++#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0 )
++#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1 )
++#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2 )
++#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3 )
++#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4 )
++#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5 )
++#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6 )
++#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7 )
++
++#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0 )
++#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1 )
++
++#define CSL_EMIF_1_REGS 0x01E10000
++
++#define NAND4BITECCLOAD (0x01E10000 +0xBC)
++#define NAND4BITECC1 (0x01E10000 +0xC0)
++#define NAND4BITECC2 (0x01E10000 +0xC4)
++#define NAND4BITECC3 (0x01E10000 +0xC8)
++#define NAND4BITECC4 (0x01E10000 +0xCC)
++
++#define NANDERRADD1 (0x01E10000 +0xD0)
++#define NANDERRADD2 (0x01E10000 +0xD4)
++#define NANDERRVAL1 (0x01E10000 +0xD8)
++#define NANDERRVAL2 (0x01E10000 +0xDC)
++
++/* Definitions for 4-bit hardware ECC */
++#define NAND_4BITECC_MASK 0x03FF03FF
++#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
++#define ECC_STATE_NO_ERR 0x0
++#define ECC_STATE_TOO_MANY_ERRS 0x1
++#define ECC_STATE_ERR_CORR_COMP_P 0x2
++#define ECC_STATE_ERR_CORR_COMP_N 0x3
++#define ECC_MAX_CORRECTABLE_ERRORS 0x4
++extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
++
++static void nand_dm350evm_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++ struct nand_chip *this = mtd->priv;
++ u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
++ u_int32_t IO_ADDR_R = (u_int32_t)this->IO_ADDR_R;
++
++ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++
++ switch (cmd) {
++ case NAND_CTL_SETCLE:
++ IO_ADDR_W |= MASK_CLE;
++ break;
++ case NAND_CTL_SETALE:
++ IO_ADDR_W |= MASK_ALE;
++ break;
++ }
++
++ this->IO_ADDR_W = (void *)IO_ADDR_W;
++}
++
++static int nand_dm350evm_dev_ready(struct mtd_info *mtd)
++{
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ return(emif_addr->NANDFSR) /*& 0x1)*/;
++}
++
++static int nand_dm350evm_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
++{
++ while(!nand_dm350evm_dev_ready(mtd)) {;}
++ *NAND_CE0CLE = NAND_STATUS;
++ return(*NAND_CE0DATA);
++}
++
++static void nand_dm355evm_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ emifregs emif_addr;
++
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ emif_addr->NANDFCR |= (1 << 8);
++}
++
++static u32 nand_dm355evm_readecc(struct mtd_info *mtd, u32 Reg)
++{
++ u32 l = 0;
++ emifregs emif_addr;
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ if (Reg == 1)
++ l = emif_addr->NANDF1ECC;
++ else if (Reg == 2)
++ l = emif_addr->NANDF2ECC;
++ else if (Reg == 3)
++ l = emif_addr->NANDF3ECC;
++ else if (Reg == 4)
++ l = emif_addr->NANDF4ECC;
++
++ return l;
++}
++
++static int nand_dm355evm_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
++ u_char *ecc_code)
++{
++ unsigned int l;
++ int reg;
++ int n;
++ struct nand_chip *this = mtd->priv;
++
++ if (this->eccmode == NAND_ECC_HW12_2048)
++ n = 4;
++ else
++ n = 1;
++
++ reg = 1;
++ while (n--) {
++ l = nand_dm355evm_readecc(mtd, reg);
++ *ecc_code++ = l; // P128e, ..., P1e
++ *ecc_code++ = l >> 16; // P128o, ..., P1o
++ // P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e
++ *ecc_code++ = ((l >> 8) & 0x0f) | ((l >> 20) & 0xf0);
++ reg++;
++ }
++ return 0;
++}
++
++static void nand_dm355evm_gen_true_ecc(u8 *ecc_buf)
++{
++ u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
++
++ ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp) );
++ ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
++ ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
++}
++
++static int nand_dm355evm_compare_ecc(u8 * ecc_data1, /* read from NAND memory */
++ u8 * ecc_data2, /* read from register */
++ u8 * page_data)
++{
++ u32 i;
++ u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
++ u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
++ u8 ecc_bit[24];
++ u8 ecc_sum = 0;
++ u8 find_bit = 0;
++ u32 find_byte = 0;
++ int isEccFF;
++
++ isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
++
++ nand_dm355evm_gen_true_ecc(ecc_data1);
++ nand_dm355evm_gen_true_ecc(ecc_data2);
++
++ for (i = 0; i <= 2; i++) {
++ *(ecc_data1 + i) = ~(*(ecc_data1 + i));
++ *(ecc_data2 + i) = ~(*(ecc_data2 + i));
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp0_bit[i] = *ecc_data1 % 2;
++ *ecc_data1 = *ecc_data1 / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp1_bit[i] = *(ecc_data1 + 1) % 2;
++ *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp2_bit[i] = *(ecc_data1 + 2) % 2;
++ *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp0_bit[i] = *ecc_data2 % 2;
++ *ecc_data2 = *ecc_data2 / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp1_bit[i] = *(ecc_data2 + 1) % 2;
++ *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp2_bit[i] = *(ecc_data2 + 2) % 2;
++ *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
++ }
++
++ for (i = 0; i< 6; i++ )
++ ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
++
++ for (i = 0; i < 8; i++)
++ ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
++
++ for (i = 0; i < 8; i++)
++ ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
++
++ ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
++ ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
++
++ for (i = 0; i < 24; i++)
++ ecc_sum += ecc_bit[i];
++
++ switch (ecc_sum) {
++ case 0:
++ /* Not reached because this function is not called if
++ ECC values are equal */
++ return 0;
++
++ case 1:
++ /* Uncorrectable error */
++ DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
++ return -1;
++
++ case 12:
++ /* Correctable error */
++ find_byte = (ecc_bit[23] << 8) +
++ (ecc_bit[21] << 7) +
++ (ecc_bit[19] << 6) +
++ (ecc_bit[17] << 5) +
++ (ecc_bit[15] << 4) +
++ (ecc_bit[13] << 3) +
++ (ecc_bit[11] << 2) +
++ (ecc_bit[9] << 1) +
++ ecc_bit[7];
++
++ find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
++
++ DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit);
++
++ page_data[find_byte] ^= (1 << find_bit);
++
++ return 0;
++
++ default:
++ if (isEccFF) {
++ if (ecc_data2[0] == 0 && ecc_data2[1] == 0 && ecc_data2[2] == 0)
++ return 0;
++ }
++ DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
++ return -1;
++ }
++}
++
++static int nand_dm355evm_correct_data(struct mtd_info *mtd, u_char *dat,
++ u_char *read_ecc, u_char *calc_ecc)
++{
++ int r = 0;
++#if 0
++ if (memcmp(read_ecc, calc_ecc, 3) != 0) {
++ u_char read_ecc_copy[3], calc_ecc_copy[3];
++ int i;
++
++ for (i = 0; i < 3; i++) {
++ read_ecc_copy[i] = read_ecc[i];
++ calc_ecc_copy[i] = calc_ecc[i];
++ }
++ r = nand_dm355_1bit_compare_ecc(read_ecc_copy, calc_ecc_copy,
++ dat);
++ }
++#endif
++ return r;
++}
++
++/*
++ * 4-bit ECC routines
++ */
++
++/*
++ * Instead of placing the spare data at the end of the page, the 4-bit ECC
++ * hardware generator requires that the page be subdivided into 4 subpages,
++ * each with its own spare data area. This structure defines the format of
++ * each of these subpages.
++ */
++static struct page_layout_item nand_dm355_hw10_512_layout[] = {
++ {.type = ITEM_TYPE_DATA,.length = 512},
++ {.type = ITEM_TYPE_OOB,.length = 6,},
++ {.type = ITEM_TYPE_ECC,.length = 10,},
++ {.type = 0,.length = 0,},
++};
++
++static struct nand_oobinfo nand_dm355_hw10_512_oobinfo = {
++ .useecc = MTD_NANDECC_AUTOPLACE,
++ .eccbytes = 10,
++ .eccpos = {6,7,8,9,10,11,12,13,14,15,
++ },
++ .oobfree ={0, 6},
++};
++
++static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
++/*
++ * We should always have a flash-based bad block table. However, if one isn't
++ * found then all blocks will be scanned to look for factory-marked bad blocks.
++ * We supply a null pattern so that no blocks will be detected as bad.
++ */
++static struct nand_bbt_descr nand_dm355_hw10_512_badblock_pattern = {
++ .options = 0, //NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
++ .offs = 5,
++ .len = 1,
++ .pattern = scan_ff_pattern
++};
++
++
++/* Generic flash bbt decriptors
++*/
++static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
++static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
++
++static struct nand_bbt_descr bbt_main_descr = {
++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
++ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
++ .offs = 0,
++ .len = 4,
++ .veroffs = 5,
++ .maxblocks = 4,
++ .pattern = bbt_pattern
++};
++
++static struct nand_bbt_descr bbt_mirror_descr = {
++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
++ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
++ .offs = 0,
++ .len = 4,
++ .veroffs = 5,
++ .maxblocks = 4,
++ .pattern = mirror_pattern
++};
++
++/*
++ * When using 4-bit ECC with a 2048-byte data + 64-byte spare page size, the
++ * oob is scattered throughout the page in 4 16-byte chunks instead of being
++ * grouped together at the end of the page. This means that the factory
++ * bad-block markers at offsets 2048 and 2049 will be overwritten when data
++ * is written to the flash. Thus, we cannot use the factory method to mark
++ * or detect bad blocks and must rely on a flash-based bad block table instead.
++ *
++ */
++static int nand_dm355_hw10_512_block_bad(struct mtd_info *mtd, loff_t ofs,
++ int getchip)
++{
++ return 0;
++}
++
++static int nand_dm355_hw10_512_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct nand_chip *this = mtd->priv;
++ int block;
++
++ /* Get block number */
++ block = ((int)ofs) >> this->bbt_erase_shift;
++ if (this->bbt)
++ this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
++
++ /* Do we have a flash based bad block table ? */
++ if (this->options & NAND_USE_FLASH_BBT)
++ return nand_update_bbt(mtd, ofs);
++
++ return 0;
++}
++
++static void nand_dm355_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ struct nand_chip *this = mtd->priv;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++
++ switch (mode) {
++ case NAND_ECC_WRITE:
++ case NAND_ECC_READ:
++ /*
++ * Start a new ECC calculation for reading or writing 512 bytes
++ * of data.
++ */
++ val = (emif_addr->NANDFCR & ~(3 << 4))
++ | (1 << 12);
++ emif_addr->NANDFCR = val;
++ break;
++ case NAND_ECC_WRITEOOB:
++ case NAND_ECC_READOOB:
++ /*
++ * Terminate ECC calculation by performing a dummy read of an
++ * ECC register. Our hardware ECC generator supports including
++ * the OOB in the ECC calculation, but the NAND core code
++ * doesn't really support that. We will only calculate the ECC
++ * on the data; errors in the non-ECC bytes in the OOB will not
++ * be detected or corrected.
++ */
++ val =(*(dv_reg_p) NAND4BITECC1);
++ break;
++ case NAND_ECC_WRITESYN:
++ case NAND_ECC_READSYN:
++ /*
++ * Our ECC calculation has already been terminated, so no need
++ * to do anything here.
++ */
++ break;
++ default:
++ break;
++ }
++}
++
++static u32 nand_dm355_4bit_readecc(struct mtd_info *mtd, unsigned int *ecc)
++{
++ unsigned int ecc_temp[4];
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ ecc[0] = (*(dv_reg_p) NAND4BITECC1) & NAND_4BITECC_MASK;
++ ecc[1] = (*(dv_reg_p) NAND4BITECC2) & NAND_4BITECC_MASK;
++ ecc[2] = (*(dv_reg_p) NAND4BITECC3) & NAND_4BITECC_MASK;
++ ecc[3] = (*(dv_reg_p) NAND4BITECC4) & NAND_4BITECC_MASK;
++
++ return 0;
++}
++
++static int nand_dm355_4bit_calculate_ecc(struct mtd_info *mtd,
++ const u_char * dat,
++ u_char * ecc_code)
++{
++ unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
++ unsigned int const1 = 0, const2 = 0;
++ unsigned char count1 = 0;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++ /*
++ * Since the NAND_HWECC_SYNDROME option is enabled, this routine is
++ * only called just after the data and oob have been written. The
++ * ECC value calculated by the hardware ECC generator is available
++ * for us to read.
++ */
++ nand_dm355_4bit_readecc(mtd, hw_4ecc);
++
++ /*Convert 10 bit ecc value to 8 bit */
++ for (count1 = 0; count1 < 2; count1++) {
++ const2 = count1 * 5;
++ const1 = count1 * 2;
++
++ /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
++ ecc_code[const2] = hw_4ecc[const1] & 0xFF;
++
++ /*
++ * Take 2 bits as LSB bits from val1 (count1=0) or val5
++ * (count1=1) and 6 bits from val2 (count1=0) or val5 (count1=1)
++ */
++ ecc_code[const2 + 1] =
++ ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
++ 0xFC);
++
++ /*
++ * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
++ * 4 bits from val3 (count1=0) or val6 (count1=1)
++ */
++ ecc_code[const2 + 2] =
++ ((hw_4ecc[const1] >> 22) & 0xF) |
++ ((hw_4ecc[const1 + 1] << 4) & 0xF0);
++
++ /*
++ * Take 6 bits from val3(count1=0) or val6 (count1=1) and
++ * 2 bits from val4 (count1=0) or val7 (count1=1)
++ */
++ ecc_code[const2 + 3] =
++ ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
++ ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
++
++ /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
++ ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
++ }
++
++ return 0;
++}
++
++static int nand_dm355_4bit_compare_ecc(struct mtd_info *mtd, u8 * read_ecc, /* read from NAND */
++ u8 * page_data)
++{
++ struct nand_chip *this = mtd->priv;
++ struct nand_dm355_info *info = this->priv;
++ unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
++ int i;
++ unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
++ unsigned short *pspare = NULL, *pspare1 = NULL;
++ unsigned int numErrors, errorAddress, errorValue;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++
++ /*
++ * Check for an ECC where all bytes are 0xFF. If this is the case, we
++ * will assume we are looking at an erased page and we should ignore the
++ * ECC.
++ */
++ for (i = 0; i < 10; i++) {
++ if (read_ecc[i] != 0xFF)
++ break;
++ }
++ if (i == 10)
++ return 0;
++
++ /* Convert 8 bit in to 10 bit */
++ pspare = (unsigned short *)&read_ecc[2];
++ pspare1 = (unsigned short *)&read_ecc[0];
++ /* Take 10 bits from 0th and 1st bytes */
++ ecc_10bit[0] = (*pspare1) & 0x3FF; /* 10 */
++ /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
++ ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
++ | (((pspare[0]) << 6) & 0x3C0); /* 6 + 4 */
++ /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
++ ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF; /* 10 */
++ /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
++ ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
++ | ((((pspare[1])) << 2) & 0x3FC); /* 2 + 8 */
++ /* Take 8 bits from 5th byte and 2 bits from 6th byte */
++ ecc_10bit[4] = ((pspare[1]) >> 8)
++ | ((((pspare[2])) << 8) & 0x300); /* 8 + 2 */
++ /* Take 6 bits from 6th byte and 4 bits from 7th byte */
++ ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF; /* 10 */
++ /* Take 4 bits from 7th byte and 6 bits from 8th byte */
++ ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
++ | ((((pspare[3])) << 4) & 0x3F0); /* 4 + 6 */
++ /*Take 2 bits from 8th byte and 8 bits from 9th byte */
++ ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF; /* 10 */
++
++ /*
++ * Write the parity values in the NAND Flash 4-bit ECC Load register.
++ * Write each parity value one at a time starting from 4bit_ecc_val8
++ * to 4bit_ecc_val1.
++ */
++ for (i = 7; i >= 0; i--)
++ {
++ *(dv_reg_p)NAND4BITECCLOAD = ecc_10bit[i];
++ }
++
++ /*
++ * Perform a dummy read to the EMIF Revision Code and Status register.
++ * This is required to ensure time for syndrome calculation after
++ * writing the ECC values in previous step.
++ */
++ val = emif_addr->ERCSR;
++
++ /*
++ * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
++ * A syndrome value of 0 means no bit errors. If the syndrome is
++ * non-zero then go further otherwise return.
++ */
++ nand_dm355_4bit_readecc(mtd, hw_4ecc);
++
++ if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
++ hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR){
++ return 0;
++ }
++
++
++ /*
++ * Clear any previous address calculation by doing a dummy read of an
++ * error address register.
++ */
++ val = *(dv_reg_p)NANDERRADD1;
++
++ /*
++ * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
++ * register to 1.
++ */
++
++ emif_addr->NANDFCR |= (1 << 13);
++
++ /*
++ * Wait for the corr_state field (bits 8 to 11)in the
++ * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
++ */
++ do {
++ iserror = emif_addr->NANDFSR & 0xC00;
++ } while (iserror);
++
++ iserror = emif_addr->NANDFSR;
++ iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
++ iserror = iserror >> 8;
++
++#if 0
++ do {
++ iserror = emif_addr->NANDFSR;
++ iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
++ iserror = iserror >> 8;
++ } while ((ECC_STATE_NO_ERR != iserror) &&
++ (ECC_STATE_TOO_MANY_ERRS != iserror) &&
++ (ECC_STATE_ERR_CORR_COMP_P != iserror) &&
++ (ECC_STATE_ERR_CORR_COMP_N != iserror));
++#endif
++ /*
++ * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
++ * corrected (five or more errors). The number of errors
++ * calculated (err_num field) differs from the number of errors
++ * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
++ * correction complete (errors on bit 8 or 9).
++ * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
++ * complete (error exists).
++ */
++
++ if (iserror == ECC_STATE_NO_ERR)
++ return 0;
++ else if (iserror == ECC_STATE_TOO_MANY_ERRS)
++ {
++ printf("too many erros to be corrected!\n");
++ return -1;
++ }
++
++#if 1
++ numErrors = ((emif_addr->NANDFSR >> 16) & 0x3) + 1;
++// printf("numErrors =%d\n",numErrors);
++ if(numErrors==4)
++ return numErrors;
++ /* Read the error address, error value and correct */
++ for (i = 0; i < numErrors; i++) {
++ if (i > 1) {
++ errorAddress =
++ ((*(dv_reg_p)(NANDERRADD2) >>
++ (16 * (i & 1))) & 0x3FF);
++ errorAddress = ((512 + 7) - errorAddress);
++ errorValue =
++ ((*(dv_reg_p)(NANDERRVAL2) >>
++ (16 * (i & 1))) & 0xFF);
++ } else {
++ errorAddress =
++ ((*(dv_reg_p)(NANDERRADD1) >>
++ (16 * (i & 1))) & 0x3FF);
++ errorAddress = ((512 + 7) - errorAddress);
++ errorValue =
++ ((*(dv_reg_p)(NANDERRVAL1) >>
++ (16 * (i & 1))) & 0xFF);
++ }
++ /* xor the corrupt data with error value */
++ if (errorAddress < 512)
++ page_data[errorAddress] ^= errorValue;
++ }
++#else
++ numErrors = ((emif_addr->NANDFSR >> 16) & 0x3);
++ // bit 9:0
++ errorAddress = 519 - (*(dv_reg_p)NANDERRADD1 & (0x3FF));
++ errorValue = (*(dv_reg_p)NANDERRVAL1) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if(numErrors == 0)
++ return numErrors;
++ else {
++ // bit 25:16
++ errorAddress = 519 - ( (*(dv_reg_p)NANDERRADD1 & (0x3FF0000))>>16 );
++ errorValue = (*(dv_reg_p)NANDERRVAL1) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if(numErrors == 1)
++ return numErrors;
++ else {
++ // bit 9:0
++ errorAddress = 519 - (*(dv_reg_p)NANDERRADD2 & (0x3FF));
++ errorValue = (*(dv_reg_p)NANDERRVAL2) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if (numErrors == 2)
++ return numErrors;
++ else {
++ // bit 25:16
++ errorAddress = 519 - ( (*(dv_reg_p)NANDERRADD2 & (0x3FF0000))>>16 );
++ errorValue = (*(dv_reg_p)NANDERRVAL2) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++ }
++ }
++ }
++#endif
++
++ return numErrors;
++}
++
++static int nand_dm355_4bit_correct_data(struct mtd_info *mtd, u_char * dat,
++ u_char * read_ecc, u_char * calc_ecc)
++{
++ int r = 0;
++
++ /*
++ * dat points to 512 bytes of data. read_ecc points to the start of the
++ * oob area for this subpage, so the ecc values start at offset 6.
++ * The calc_ecc pointer is not needed since our caclulated ECC is
++ * already latched in the hardware ECC generator.
++ */
++#if 1
++ r = nand_dm355_4bit_compare_ecc(mtd, read_ecc + 6, dat);
++#endif
++
++ return r;
++}
++int board_nand_init(struct nand_chip *nand)
++{
++#if 0
++ nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
++ nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
++#endif
++ nand->chip_delay = 0;
++ nand->options = NAND_USE_FLASH_BBT /*| NAND_BBT_LASTBLOCK*/;
++// nand->eccmode = NAND_ECC_SOFT;
++#if 0
++ nand->eccmode = NAND_ECC_HW3_512;
++ nand->calculate_ecc = nand_dm355evm_calculate_ecc;
++ nand->correct_data = nand_dm355evm_correct_data;
++ nand->enable_hwecc = nand_dm355evm_enable_hwecc;
++#else
++ nand->eccmode = NAND_ECC_HW10_512;
++ nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME;
++ nand->autooob = &nand_dm355_hw10_512_oobinfo;
++ nand->layout = nand_dm355_hw10_512_layout;
++ nand->calculate_ecc = nand_dm355_4bit_calculate_ecc;
++ nand->correct_data = nand_dm355_4bit_correct_data;
++ nand->enable_hwecc = nand_dm355_4bit_enable_hwecc;
++ //nand->block_bad = nand_dm355_hw10_512_block_bad;
++ nand->block_markbad = nand_dm355_hw10_512_block_markbad;
++ nand->badblock_pattern = &nand_dm355_hw10_512_badblock_pattern;
++ nand->bbt_td =&bbt_main_descr;
++ nand->bbt_md = &bbt_mirror_descr;
++
++#endif
++ /* Set address of hardware control function */
++ nand->hwcontrol = nand_dm350evm_hwcontrol;
++
++ //nand->dev_ready = nand_dm350evm_dev_ready;
++ //nand->waitfunc = nand_dm350evm_waitfunc;
++
++ return 0;
++}
++
++#else
++#error "U-Boot legacy NAND support not available for DaVinci chips"
++#endif
++#endif /* CFG_USE_NAND */
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/timer.c u-boot-1.2.0-leopard/board/dm355_ipnc/timer.c
+--- u-boot-1.2.0/board/dm355_ipnc/timer.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/timer.c 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,72 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++
++#include "timer.h"
++
++/* Use Timer 3&4 (Timer 2) */
++#define TIMER_BASE_ADDR 0x01C21400
++
++dm350_timer_reg *dm350_timer = (dm350_timer_reg *) TIMER_BASE_ADDR;
++
++/* Timer Initialize */
++void inittimer(void)
++{
++ /* disable Timer 1 & 2 timers */
++ dm350_timer->tcr = 0;
++
++ /* Set timers to unchained dual 32 bit timers, Unreset timer34 */
++ dm350_timer->tgcr = 0x0;
++ dm350_timer->tgcr = 0x6;
++
++ /* Program the timer12 counter register - set the prd12 for right count */
++ dm350_timer->tim34 = 0;
++
++ /* The timer is programmed to expire after 0xFFFFFFFF ticks */
++ dm350_timer->prd34 = 0xFFFFFFFF;
++
++ /* Enable timer34 */
++ dm350_timer->tcr = (0x80 << 16); /* Timer34 continously enabled, Timer12 disabled */
++}
++
++/************************************************************
++********************** Reset Processor **********************
++************************************************************/
++#define WDT_BASE_ADDR 0x01C21C00
++
++
++void reset_processor(void)
++{
++ dm350_timer_reg *dm350_wdt = (dm350_timer_reg *) WDT_BASE_ADDR;
++ dm350_wdt->tgcr = 0x00000008;
++ dm350_wdt->tgcr |= 0x00000003;
++ dm350_wdt->tim12 = 0x00000000;
++ dm350_wdt->tim34 = 0x00000000;
++ dm350_wdt->prd12 = 0x00000000;
++ dm350_wdt->prd34 = 0x00000000;
++ dm350_wdt->tcr |= 0x00000040;
++ dm350_wdt->wdtcr |= 0x00004000;
++ dm350_wdt->wdtcr = 0xA5C64000;
++ dm350_wdt->wdtcr = 0xDA7E4000;
++}
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/timer.h u-boot-1.2.0-leopard/board/dm355_ipnc/timer.h
+--- u-boot-1.2.0/board/dm355_ipnc/timer.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/timer.h 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,51 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Modifications:
++ * ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#ifndef __TIMER_H__
++#define __TIMER_H__
++
++typedef volatile struct dm350_timer_reg_t
++{
++ unsigned int pid12; /* 0x0 */
++ unsigned int emumgt_clksped;/* 0x4 */
++ unsigned int gpint_en; /* 0x8 */
++ unsigned int gpdir_dat; /* 0xC */
++ unsigned int tim12; /* 0x10 */
++ unsigned int tim34; /* 0x14 */
++ unsigned int prd12; /* 0x18 */
++ unsigned int prd34; /* 0x1C */
++ unsigned int tcr; /* 0x20 */
++ unsigned int tgcr; /* 0x24 */
++ unsigned int wdtcr; /* 0x28 */
++ unsigned int tlgc; /* 0x2C */
++ unsigned int tlmr; /* 0x30 */
++} dm350_timer_reg;
++
++#endif /* __TIMER_H__ */
++
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/types.h u-boot-1.2.0-leopard/board/dm355_ipnc/types.h
+--- u-boot-1.2.0/board/dm355_ipnc/types.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/types.h 2008-01-05 03:45:25.000000000 -0300
+@@ -0,0 +1,46 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _TYPESH_
++#define _TYPESH_
++
++typedef unsigned long ULONG;
++typedef unsigned short USHORT;
++typedef unsigned long BOOL;
++typedef unsigned int WORD;
++typedef char CHAR;
++typedef unsigned char BYTE, *LPBYTE, UCHAR, *PUCHAR, PBYTE;
++
++#define FALSE 0
++#define TRUE 1
++
++#define NULL 0
++
++typedef unsigned short int Hwd;
++typedef volatile unsigned short int vHwd;
++typedef unsigned short int * Hwdptr;
++typedef volatile unsigned short int * vHwdptr;
++//typedef volatile unsigned int * vHwdptr;
++
++
++#endif
++
+diff -Nurd u-boot-1.2.0/board/dm355_ipnc/u-boot.lds u-boot-1.2.0-leopard/board/dm355_ipnc/u-boot.lds
+--- u-boot-1.2.0/board/dm355_ipnc/u-boot.lds 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_ipnc/u-boot.lds 2008-01-31 04:18:33.000000000 -0300
+@@ -0,0 +1,52 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm926ejs/start.o (.text)
++ *(.text)
++ }
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++ . = ALIGN(4);
++ .data : { *(.data) }
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/Makefile u-boot-1.2.0-leopard/board/dm355_leopard/Makefile
+--- u-boot-1.2.0/board/dm355_leopard/Makefile 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/Makefile 2009-03-10 02:17:43.000000000 -0300
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := dm355_leopard.o flash.o nand.o timer.o
++SOBJS := lowlevel_init.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/config.mk u-boot-1.2.0-leopard/board/dm355_leopard/config.mk
+--- u-boot-1.2.0/board/dm355_leopard/config.mk 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/config.mk 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,25 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++#
++# (C) Copyright 2003
++# Texas Instruments, <www.ti.com>
++# Swaminathan <swami.iyer@ti.com>
++#
++# Davinci EVM board (ARM925EJS) cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# Davinci EVM has 1 bank of 256 MB DDR RAM
++# Physical Address:
++# 8000'0000 to 9000'0000
++#
++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
++# (mem base + reserved)
++#
++# we load ourself to 8100 '0000
++#
++#
++
++#Provide a atleast 16MB spacing between us and the Linux Kernel image
++TEXT_BASE = 0x81080000
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/dm355_leopard.c u-boot-1.2.0-leopard/board/dm355_leopard/dm355_leopard.c
+--- u-boot-1.2.0/board/dm355_leopard/dm355_leopard.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/dm355_leopard.c 2009-03-10 02:19:53.000000000 -0300
+@@ -0,0 +1,671 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++
++#define inw(a) __raw_readw(a)
++#define outw(a,v) __raw_writew(a,v)
++
++
++#define PLL1_PLLM *(volatile unsigned int *)0x01c40910
++#define PLL2_PLLM *(volatile unsigned int *)0x01c40D10
++#define PLL2_DIV2 *(volatile unsigned char *)0x01c40D1C
++#define PLL2_PREDIV *(volatile unsigned int *)0x01C40D14
++#define PLL1_PLLDIV3 *(volatile unsigned int *)0x01C40920
++#define PLL1_POSTDIV *(volatile unsigned int *)0x01C40928
++#define PLL1_PLLDIV4 *(volatile unsigned int *)0x01C40960
++#define SYSTEM_MISC *(volatile unsigned int *)0x01C40038
++#define MACH_DM355_LEOPARD 1381
++
++#define W_SETUP 0x1 //0~f
++#define W_STROBE 0x3 //0~3f
++#define W_HOLD 0x1 //0~7
++#define R_SETUP 0x1 //0~f
++#define R_STROBE 0x3 //0~3f
++#define R_HOLD 0x1 //0~7
++
++#define TA 3 //0~3
++#define A_SIZE 1 //1:16 bit 0:8bit
++#define DM9000_TIMING W_SETUP<<26 | W_STROBE<<20 | W_HOLD <<17 | R_SETUP<<13 | R_STROBE<<7 | R_HOLD <<4 | TA<<2 | A_SIZE
++
++
++
++/* GIO register */
++#define GIO_BINTEN 0x01C67008 /* GPIO Interrupt Per-Bank Enable Register */
++#define GIO_DIR01 0x01C67010
++#define GIO_OUT_DATA01 0x01C67014
++#define GIO_SET_DATA01 0x01C67018
++#define GIO_CLR_DATA01 0x01C6701C
++#define GIO_SET_RIS_TRIG01 0x01C67024
++#define GIO_SET_FAL_TRIG01 0x01C6702c
++#define GIO_A2CR 0x01e10014
++
++#define GIO_DIR23 0x01C67038
++#define GIO_OUT_DATA23 0x01C6703c
++#define GIO_SET_DATA23 0x01C67040
++#define GIO_CLR_DATA23 0x01C67044
++
++#define GIO_DIR45 (0x01C67060)
++#define GIO_OUT_DATA45 (0x01C67064)
++#define GIO_SET_DATA45 (0x01C67068)
++#define GIO_CLR_DATA45 (0x01C6706C)
++
++#define GIO_DIR06 (0x01C67088)
++#define GIO_OUT_DATA06 (0x01C6708C)
++#define GIO_SET_DATA06 (0x01C67090)
++#define GIO_CLR_DATA06 (0x01C67094)
++
++void davinci_psc_all_enable(void);
++short MSP430_getReg( short reg, unsigned short *regval );
++unsigned int UARTSendInt(unsigned int value);
++
++/*******************************************
++ Routine: delay
++ Description: Delay function
++*******************************************/
++static inline void delay (unsigned long loops)
++{
++__asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*******************************************
++ Routine: board_init
++ Description: Board Initialization routine
++*******************************************/
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++ int i;
++ /* arch number of DaVinci DVDP-Board */
++ gd->bd->bi_arch_number = MACH_DM355_LEOPARD;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
++#if 1
++#define PINMUX3 0x01C4000C
++ *(volatile unsigned int *)PINMUX3 &= 0XF8FFFFFF; // GIO9 & 10 are IO
++
++ /* Interrupt set GIO9 */
++ *((volatile unsigned int *) GIO_BINTEN) |=0x01; //bank 0
++ /* set GIO9input */
++ *((volatile unsigned int *) GIO_DIR01) |=(1<<9);
++ /* Both edge tigger GIO9 */
++ *((volatile unsigned int *) GIO_SET_RIS_TRIG01) |=(1<<9);
++
++ /* set GIO5 output, imager reset */
++ //printf("pull down gio5\n");
++ *((volatile unsigned int *) GIO_DIR01) &= ~(1<<5);
++ *((volatile unsigned int *) GIO_SET_DATA01) &= ~(1<<5); // output Low
++
++ /* set GIO10 output */
++ // printf("pull up gio10\n");
++ *((volatile unsigned int *) GIO_DIR01) &= ~(1<<10);
++ *((volatile unsigned int *) GIO_SET_DATA01) |= (1<<10); // output Hi
++
++
++ /* set GIO32 output */
++ *((volatile unsigned int *) GIO_DIR23) &= ~(1<<0);
++ *((volatile unsigned int *) GIO_SET_DATA23) |= (1<<0); // output Hi
++ /* set GIO102 output */
++#define PINMUX0 0x01C40000
++ /* Enable UART1 MUX Lines */
++ *(volatile unsigned int *)PINMUX0 &= ~3;
++ *((volatile unsigned int *) GIO_DIR06) &= ~(1<<6);
++ *((volatile unsigned int *) GIO_SET_DATA06) |= (1<<6); // output Hi
++
++ /* CE01:External Memory setting */
++ /* PLL1 404MHZ EMIF 101MHZ unit 10 ns */
++
++ /* *((volatile unsigned int *) GIO_A2CR) = DM9000_TIMING ; */
++#endif
++ /* Configure MUX settings */
++
++ /* Power on required peripherals
++ davinci_psc_all_enable(); */
++#if 0
++ /* this speeds up your boot a quite a bit. However to make it
++ * work, you need make sure your kernel startup flush bug is fixed.
++ * ... rkw ...
++ */
++ icache_enable ();
++
++#endif
++ inittimer ();
++
++ return 0;
++}
++
++/* PSC Domains */
++
++#define LPSC_VPSSMSTR 0 // VPSS Master LPSC
++#define LPSC_VPSSSLV 1 // VPSS Slave LPSC
++#define LPSC_TPCC 2 // TPCC LPSC
++#define LPSC_TPTC0 3 // TPTC0 LPSC
++#define LPSC_TPTC1 4 // TPTC1 LPSC
++#define PAL_SYS_CLK_MODULE_SPI1 6 /**<SPI1 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_MMCSD1 7 /**<MMCSD1 LPSC Module No*/
++#define LPSC_USB 9 // USB LPSC
++#define PAL_SYS_CLK_MODULE_PWM3 10 /**<PWM3 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_SPI2 11 /**<SPI2 LPSC Module No*/
++#define PAL_SYS_CLK_MODULE_RTO 12 /**<TIMER2 LPSC Module No*/
++#define LPSC_DDR_EMIF 13 // DDR_EMIF LPSC
++#define LPSC_AEMIF 14 // AEMIF LPSC
++#define LPSC_MMC_SD 15 // MMC_SD LPSC
++#define LPSC_MEMSTICK 16 // MEMSTICK LPSC
++#define PAL_SYS_CLK_MODULE_ASP 17 /**<AEMIF LPSC Module No*/
++#define LPSC_I2C 18 // I2C LPSC
++#define LPSC_UART0 19 // UART0 LPSC
++#define LPSC_UART1 20 // UART1 LPSC
++#define LPSC_UART2 21 // UART2 LPSC
++#define LPSC_SPI 22 // SPI LPSC
++#define LPSC_PWM0 23 // PWM0 LPSC
++#define LPSC_PWM1 24 // PWM1 LPSC
++#define LPSC_PWM2 25 // PWM2 LPSC
++#define LPSC_GPIO 26 // GPIO LPSC
++#define LPSC_TIMER0 27 // TIMER0 LPSC
++#define LPSC_TIMER1 28 // TIMER1 LPSC
++#define LPSC_TIMER2 29 // TIMER2 LPSC
++#define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM LPSC
++#define LPSC_ARM 31 // ARM LPSC
++#define PAL_SYS_CLK_MODULE_VPSS_DAC 40 /**<VPSS DAC LPSC Module No*/
++
++#define EPCPR *( unsigned int* )( 0x01C41070 )
++#define PTCMD *( unsigned int* )( 0x01C41120 )
++#define PTSTAT *( unsigned int* )( 0x01C41128 )
++#define PDSTAT *( unsigned int* )( 0x01C41200 )
++#define PDSTAT1 *( unsigned int* )( 0x01C41204 )
++#define PDCTL *( unsigned int* )( 0x01C41300 )
++#define PDCTL1 *( unsigned int* )( 0x01C41304 )
++#define VBPR *( unsigned int* )( 0x20000020 )
++
++/**************************************
++ Routine: board_setup_psc_on
++ Description: Enable a PSC domain
++**************************************/
++void board_setup_psc_on( unsigned int domain, unsigned int id )
++{
++ volatile unsigned int* mdstat = ( unsigned int* )( 0x01C41800 + 4 * id );
++ volatile unsigned int* mdctl = ( unsigned int* )( 0x01C41A00 + 4 * id );
++
++ *mdctl |= 0x00000003; // Set PowerDomain to turn on
++
++ if ( ( PDSTAT & 0x00000001 ) == 0 )
++ {
++ PDCTL1 |= 0x1;
++ PTCMD = ( 1 << domain );
++ while ( ( ( ( EPCPR >> domain ) & 1 ) == 0 ) );
++
++ PDCTL1 |= 0x100 ;
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++ else
++ {
++ PTCMD = ( 1<<domain );
++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) );
++ }
++
++ while( ! ( ( *mdstat & 0x0000001F ) == 0x3 ) );
++}
++
++/**************************************
++ Routine: davinci_psc_all_enable
++ Description: Enable all PSC domains
++**************************************/
++void davinci_psc_all_enable(void)
++{
++#define PSC_ADDR 0x01C41000
++#define PTCMD (PSC_ADDR+0x120)
++#define PTSTAT (PSC_ADDR+0x128)
++
++ unsigned int alwaysOnPdNum = 0, dspPdNum = 1, i;
++
++ /* This function turns on all clocks in the ALWAYSON and DSP Power
++ * Domains. Note this function assumes that the Power Domains are
++ * already on.
++ */
++#if 0
++ /* Write ENABLE (0x3) to all 41 MDCTL[i].NEXT bit fields. */
++ for( i = 0; i < 41; i++){
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) =
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) | 0x3;
++ }
++
++ /* For special workaround: Set MDCTL[i].EMURSTIE to 0x1 for all of the
++ * following Modules. VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) | 0x203;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x203;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) | 0x203;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) | 0x203;*/
++#endif
++
++ /* For special workaround: Clear MDCTL[i].EMURSTIE to 0x0 for all of the following Modules.
++ * VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ,
++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP.
++ */
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) & 0x003;*/
++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*19))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*20) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*20))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*21) = ((*(unsigned int*) (PSC_ADDR+0xA00+4*21))&0xFFFFFFF8) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*18) = *(unsigned int*) (PSC_ADDR+0xA00+4*18) | 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*28) = *(unsigned int*) (PSC_ADDR+0xA00+4*28) | 0x003;
++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) & 0x003;
++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) & 0x003;*/
++
++ /* Set PTCMD.GO0 to 0x1 to initiate the state transtion for Modules in
++ * the ALWAYSON Power Domain
++ */
++ *(volatile unsigned int*) PTCMD = (1<<alwaysOnPdNum);
++
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! (((*(volatile unsigned int*) PTSTAT >> alwaysOnPdNum) & 0x00000001) == 0));
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*19)& 0x0000001F ) == 0x3));
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*20)& 0x0000001F ) == 0x3));
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! ((*(unsigned int*) (PSC_ADDR+0x800+4*21)& 0x0000001F ) == 0x3));
++ /* Bringup UART out of reset here since NS16650 code that we are using from uBoot
++ * will not do it
++ */
++
++#define UART0PWREMU_MGMT 0x01c20030
++ *(volatile unsigned int*) UART0PWREMU_MGMT |= 0x00008001;
++
++
++#define UART1PWREMU_MGMT 0x01c20430
++ *(volatile unsigned int*) UART1PWREMU_MGMT |= 0x00008001;
++
++#define UART2PWREMU_MGMT 0x01e06030
++ *(volatile unsigned int*) UART2PWREMU_MGMT |= 0x00008001;
++
++#define PINMUX3 0x01C4000C
++ /* Enable UART1 MUX Lines */
++ *(volatile unsigned int *)PINMUX3 |= 0x00600000;
++
++ /* Enable UART2 MUX Lines */
++ *(volatile unsigned int *)PINMUX3 |= 0x0000AA00;
++
++ /* Set the Bus Priority Register to appropriate value */
++ VBPR = 0x20;
++}
++
++/******************************
++ Routine: misc_init_r
++ Description: Misc. init
++******************************/
++int misc_init_r (void)
++{
++ char temp[20], *env=0;
++ char rtcdata[10] = { 4, 1, 0, 0, 0, 0, 0, 0, 0, 0};
++ int clk = 0;
++ unsigned short regval=0 ;
++
++ clk = ((PLL2_PLLM + 1) * 24) / ((PLL2_PREDIV & 0x1F) + 1);
++
++ printf ("ARM Clock :- %dMHz\n", ( ( ((PLL1_PLLM+1)*24 )/(2*(7+1)*((SYSTEM_MISC & 0x2)?2:1 )))) );
++ printf ("DDR Clock :- %dMHz\n", (clk/2));
++
++ /* set GIO5 output, imager reset */
++ //printf("pull up gio5\n");
++ *((volatile unsigned int *) GIO_SET_DATA01) |= (1<<5); // output High
++
++ return (0);
++}
++
++/******************************
++ Routine: dram_init
++ Description: Memory Info
++******************************/
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++
++typedef int Bool;
++#define TRUE ((Bool) 1)
++#define FALSE ((Bool) 0)
++
++
++typedef int Int;
++typedef unsigned int Uns; /* deprecated type */
++typedef char Char;
++typedef char * String;
++typedef void * Ptr;
++
++/* unsigned quantities */
++typedef unsigned int Uint32;
++typedef unsigned short Uint16;
++typedef unsigned char Uint8;
++
++/* signed quantities */
++typedef int Int32;
++typedef short Int16;
++typedef char Int8;
++
++/* volatile unsigned quantities */
++typedef volatile unsigned int VUint32;
++typedef volatile unsigned short VUint16;
++typedef volatile unsigned char VUint8;
++
++/* volatile signed quantities */
++typedef volatile int VInt32;
++typedef volatile short VInt16;
++typedef volatile char VInt8;
++
++typedef struct _uart_regs
++{
++ VUint32 RBR;
++ VUint32 IER;
++ VUint32 IIR;
++ VUint32 LCR;
++ VUint32 MCR;
++ VUint32 LSR;
++ VUint32 MSR;
++ VUint32 SCR;
++ VUint8 DLL;
++ VUint8 RSVDO[3];
++ VUint8 DLH;
++ VUint8 RSVD1[3];
++ VUint32 PID1;
++ VUint32 PID2;
++ VUint32 PWREMU_MGNT;
++} uartRegs;
++
++#define THR RBR
++#define FCR IIR
++
++#define UART0 ((uartRegs*) 0x01C20000)
++#define UART1 ((uartRegs*) 0x01C20400)
++
++#define MAXSTRLEN 256
++#define E_PASS 0x00000000u
++#define E_FAIL 0x00000001u
++#define E_TIMEOUT 0x00000002u
++
++
++
++// Send specified number of bytes
++
++Int32 GetStringLen(Uint8* seq)
++{
++ Int32 i = 0;
++ while ((seq[i] != 0) && (i<MAXSTRLEN)){ i++;}
++ if (i == MAXSTRLEN)
++ return -1;
++ else
++ return i;
++}
++
++Uint32 UARTSendData(Uint8* seq, Bool includeNull)
++{
++ Uint32 status = 0;
++ Int32 i,numBytes;
++ Uint32 timerStatus = 0x1000000;
++
++ numBytes = includeNull?(GetStringLen(seq)+1):(GetStringLen(seq));
++
++ for(i=0;i<numBytes;i++) {
++ /* Enable Timer one time */
++ //TIMER0Start();
++ do{
++ status = (UART0->LSR)&(0x60);
++ //timerStatus = TIMER0Status();
++ timerStatus--;
++ } while (!status && timerStatus);
++
++ if(timerStatus == 0)
++ return E_TIMEOUT;
++
++ // Send byte
++ (UART0->THR) = seq[i];
++ }
++ return E_PASS;
++}
++
++Uint32 UARTSendInt(Uint32 value)
++{
++ char seq[9];
++ Uint32 i,shift,temp;
++
++ for( i = 0; i < 8; i++)
++ {
++ shift = ((7-i)*4);
++ temp = ((value>>shift) & (0x0000000F));
++ if (temp > 9)
++ {
++ temp = temp + 7;
++ }
++ seq[i] = temp + 48;
++ seq[i] = temp + 48;
++ }
++ seq[8] = 0;
++ return UARTSendData(seq, FALSE);
++}
++
++#define I2C_BASE 0x01C21000
++#define I2C_OA (I2C_BASE + 0x00)
++#define I2C_IE (I2C_BASE + 0x04)
++#define I2C_STAT (I2C_BASE + 0x08)
++#define I2C_SCLL (I2C_BASE + 0x0c)
++#define I2C_SCLH (I2C_BASE + 0x10)
++#define I2C_CNT (I2C_BASE + 0x14)
++#define I2C_DRR (I2C_BASE + 0x18)
++#define I2C_SA (I2C_BASE + 0x1c)
++#define I2C_DXR (I2C_BASE + 0x20)
++#define I2C_CON (I2C_BASE + 0x24)
++#define I2C_IV (I2C_BASE + 0x28)
++#define I2C_PSC (I2C_BASE + 0x30)
++
++#define I2C_CON_EN (1 << 5) /* I2C module enable */
++#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
++#define I2C_CON_MST (1 << 10) /* Master/slave mode */
++#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
++#define I2C_CON_XA (1 << 8) /* Expand address */
++#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
++#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
++
++#define I2C_STAT_BB (1 << 12) /* Bus busy */
++#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
++#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
++#define I2C_STAT_AAS (1 << 9) /* Address as slave */
++#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
++#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
++#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
++#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
++#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
++#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
++
++static Int16 I2C_init(void );
++static Int16 I2C_close(void );
++static Int16 I2C_reset( void);
++static Int16 I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len );
++static Int16 I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len );
++Int32 i2c_timeout = 0x10000;
++
++Int16 MSP430_getReg( Int16 reg, Uint16 *regval )
++{
++ volatile Int16 retcode;
++ Uint8 msg[2];
++
++ I2C_reset();
++ udelay(10000);
++ /* Send Msg */
++ msg[0] = (Uint8)(reg & 0xff);
++ if ( retcode = I2C_write( 0x25, msg, 1) )
++ {
++ return retcode;
++ }
++
++ if ( retcode = I2C_read( 0x25, msg, 1 ) )
++ {
++ return retcode;
++ }
++
++ *regval = msg[0];
++
++ /* Wait 1 msec */
++ udelay( 1000 );
++
++ return 0;
++}
++
++static Int16 I2C_init( )
++{
++ outw(0, I2C_CON); // Reset I2C
++ outw(26,I2C_PSC); // Config prescaler for 27MHz
++ outw(20,I2C_SCLL); // Config clk LOW for 20kHz
++ outw(20,I2C_SCLH); // Config clk HIGH for 20kHz
++ outw(inw(I2C_CON) | I2C_CON_EN,I2C_CON); // Release I2C from reset
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ *
++ * *
++ * _I2C_close( ) *
++ * *
++ * ------------------------------------------------------------------------ */
++static Int16 I2C_close( )
++{
++ outw(0,I2C_CON); // Reset I2C
++ return 0;
++}
++
++/* ------------------------------------------------------------------------ *
++ * *
++ * _I2C_reset( ) *
++ * *
++ * ------------------------------------------------------------------------ */
++static Int16 I2C_reset( )
++{
++ I2C_close( );
++ I2C_init( );
++ return 0;
++}
++
++static Int16 I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len )
++{
++ Int32 timeout, i, status;
++
++ outw(len, I2C_CNT); // Set length
++ outw(i2c_addr, I2C_SA); // Set I2C slave address
++ outw(0x2000 // Set for Master Write
++ | 0x0200
++ | 0x0400
++ | I2C_CON_EN
++ | 0x4000, I2C_CON );
++
++ udelay( 10 ); // Short delay
++
++ for ( i = 0 ; i < len ; i++ )
++ {
++ outw( data[i],I2C_DXR);; // Write
++
++ timeout = i2c_timeout;
++ do
++ {
++ if ( timeout-- < 0 )
++ {
++ I2C_reset( );
++ return -1;
++ }
++ } while ( ( inw(I2C_STAT) & I2C_STAT_XRDY ) == 0 );// Wait for Tx Ready
++ }
++
++ outw( inw(I2C_CON) | 0x0800, I2C_CON); // Generate STOP
++
++ return 0;
++
++}
++static Int16 I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len )
++{
++ Int32 timeout, i, status;
++
++ outw( len, I2C_CNT); // Set length
++ outw( i2c_addr, I2C_SA); // Set I2C slave address
++ outw( 0x2000 // Set for Master Read
++ | 0x0400
++ | I2C_CON_EN
++ | 0x4000,I2C_CON);
++
++ udelay( 10 ); // Short delay
++
++ for ( i = 0 ; i < len ; i++ )
++ {
++ timeout = i2c_timeout;
++
++ /* Wait for Rx Ready */
++ do
++ {
++ if ( timeout-- < 0 )
++ {
++ I2C_reset( );
++ return -1;
++ }
++ } while ( ( inw(I2C_STAT) & I2C_STAT_RRDY ) == 0 );// Wait for Rx Ready
++
++ data[i] = inw(I2C_DRR); // Read
++ }
++
++ //I2C_ICMDR |= ICMDR_STP; // Generate STOP
++ return 0;
++}
++
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/flash.c u-boot-1.2.0-leopard/board/dm355_leopard/flash.c
+--- u-boot-1.2.0/board/dm355_leopard/flash.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/flash.c 2009-03-01 04:27:24.000000000 -0300
+@@ -0,0 +1,758 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * (C) Copyright 2003
++ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include "types.h"
++
++#if !defined(CFG_NO_FLASH)
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++#if define (CFG_DM355_BASSET)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define EVMDM355_FLASH_CTL555 *(u16*)( CFG_FLASH_BASE + (0x555 << 1))
++ #define EVMDM355_FLASH_CTL2AA *(u16*)( CFG_FLASH_BASE + (0x2aa << 1))
++ #define EVMDM355_CPLD *(u16*)( CFG_FLASH_BASE + (0x1c000 << 0) )
++ #define EVMDM355_CPLD_MASK 0x3FC000
++
++ #define FLASH_CYCLE1 (0x0555)
++ #define FLASH_CYCLE2 (0x02aa)
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++ #define SWAP(x) __swab16(x)
++#endif
++
++#if defined (CONFIG_TOP860)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++#endif
++
++#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 (0x0aaa << 1)
++ #define FLASH_CYCLE2 (0x0555 << 1)
++ #define FLASH_ID1 0
++ #define FLASH_ID2 2
++ #define FLASH_ID3 0x1c
++ #define FLASH_ID4 0x1E
++#endif
++
++#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0E
++ #define FLASH_ID4 0x0F
++#endif
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size(FPWV *addr, flash_info_t *info);
++static void flash_reset(flash_info_t *info);
++static int write_word(flash_info_t *info, FPWV *dest, FPW data);
++static flash_info_t *flash_get_info(ulong base);
++void inline spin_wheel (void);
++
++/*-----------------------------------------------------------------------
++ * flash_init()
++ *
++ * sets up flash_info and returns size of FLASH (bytes)
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i = 0;
++ u16 mfgid, devid;
++ extern void flash_preinit(void);
++ extern void flash_afterinit(uint, ulong, ulong);
++ ulong flashbase = CFG_FLASH_BASE;
++
++#if 0
++ EVMDM355_CPLD = 0;
++ EVMDM355_FLASH_CTL555 = 0xf0;
++
++ EVMDM355_FLASH_CTL555 = 0xaa;
++ EVMDM355_FLASH_CTL2AA = 0x55;
++ EVMDM355_FLASH_CTL555 = 0x90;
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++ mgfid = *((u16*)CFG_FLASH_BASE);
++ devid = *((u16*)CFG_FLASH_BASE +1);
++
++ *((u8 *)CFG_FLASH_BASE) = 0xf0;
++
++ printf("MFGID %x \n", mfgid);
++ printf("DEVIU %x \n", devid);
++ if ((mfgid != 0x0001) || (devid != 0x227e))
++ return 1;
++#endif
++
++ /*flash_preinit();*/
++
++ /* There is only ONE FLASH device */
++ memset(&flash_info[i], 0, sizeof(flash_info_t));
++ flash_info[i].size =
++ flash_get_size((FPW *)flashbase, &flash_info[i]);
++ size += flash_info[i].size;
++
++#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
++ /* monitor protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_MONITOR_BASE,
++ CFG_MONITOR_BASE+monitor_flash_len-1,
++ flash_get_info(CFG_MONITOR_BASE));
++#endif
++
++#ifdef CFG_ENV_IS_IN_FLASH
++ /* ENV protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
++ flash_get_info(CFG_ENV_ADDR));
++#endif
++
++
++ /*flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);*/
++ return size ? size : 1;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_reset(flash_info_t *info)
++{
++ FPWV *base = (FPWV *)(info->start[0]);
++
++ /* Put FLASH back in read mode */
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *base = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++
++void flash_reset_sector(flash_info_t *info, ULONG addr)
++{
++ // Reset Flash to be in Read Array Mode
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *(FPWV *)addr = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *(FPWV *)addr = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size &&
++ info->start[0] <= base && base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++ uchar *boottype;
++ uchar *bootletter;
++ uchar *fmt;
++ uchar botbootletter[] = "B";
++ uchar topbootletter[] = "T";
++ uchar botboottype[] = "bottom boot sector";
++ uchar topboottype[] = "top boot sector";
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_AMD: printf ("MY AMD "); break;
++#if 0
++ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
++ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
++ case FLASH_MAN_SST: printf ("SST "); break;
++ case FLASH_MAN_STM: printf ("STM "); break;
++#endif
++ case FLASH_MAN_INTEL: printf ("INTEL "); break;
++ default: printf ("Unknown Vendor "); break;
++ }
++
++ /* check for top or bottom boot, if it applies */
++ if (info->flash_id & FLASH_BTYPE) {
++ boottype = botboottype;
++ bootletter = botbootletter;
++ }
++ else {
++ boottype = topboottype;
++ bootletter = topbootletter;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160T:
++ case FLASH_AM160B:
++ fmt = "29LV160%s (16 Mbit, %s)\n";
++ break;
++ case FLASH_AMLV640U:
++ fmt = "29LV640M (64 Mbit)\n";
++ break;
++ case FLASH_AMDLV065D:
++ fmt = "29LV065D (64 Mbit)\n";
++ break;
++ case FLASH_AMLV256U:
++ fmt = "29LV256M (256 Mbit)\n";
++ break;
++ case FLASH_28F128P30T:
++ fmt = "28F128P30T\n";
++ break;
++ case FLASH_S29GL256N:
++ fmt = "S29GL256N\n";
++ break;
++ default:
++ fmt = "Unknown Chip Type\n";
++ break;
++ }
++
++ printf (fmt, bootletter, boottype);
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20,
++ info->sector_count);
++
++ printf (" Sector Start Addresses:");
++
++ for (i=0; i<info->sector_count; ++i) {
++ ulong size;
++ int erased;
++ ulong *flash = (unsigned long *) info->start[i];
++
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++
++ /*
++ * Check if whole sector is erased
++ */
++ size =
++ (i != (info->sector_count - 1)) ?
++ (info->start[i + 1] - info->start[i]) >> 2 :
++ (info->start[0] + info->size - info->start[i]) >> 2;
++
++ for (
++ flash = (unsigned long *) info->start[i], erased = 1;
++ (flash != (unsigned long *) info->start[i] + size) && erased;
++ flash++
++ )
++ erased = *flash == ~0x0UL;
++
++ printf (" %08lX %s %s",
++ info->start[i],
++ erased ? "E": " ",
++ info->protect[i] ? "(RO)" : " ");
++ }
++
++ printf ("\n");
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++
++ulong flash_get_size (FPWV *addr, flash_info_t *info)
++{
++ int i;
++ u16 mfgid, devid, id3,id4;
++
++
++ /* Write auto select command: read Manufacturer ID */
++ /* Write auto select command sequence and test FLASH answer */
++ //EVMDM355_CPLD = 0;
++ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
++#if 0
++ EVMDM355_FLASH_CTL555 = 0xf0;
++
++ EVMDM355_FLASH_CTL555 = 0xaa;
++ EVMDM355_FLASH_CTL2AA = 0x55;
++ EVMDM355_FLASH_CTL555 = 0x90;
++#endif
++
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++
++ switch ( (mfgid = addr[FLASH_ID1]) & 0xff) {
++
++ case (uchar)AMD_MANUFACT:
++ printf ("MY AMD ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_AMD;
++ break;
++
++ case (uchar)INTEL_MANUFACT:
++ printf ("INTEL %x", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++ printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++ break;
++ }
++
++ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
++ if (info->flash_id != FLASH_UNKNOWN) switch (devid = (FPW)addr[FLASH_ID2]) {
++
++ case (FPW)AMD_ID_LV160B:
++ info->flash_id += FLASH_AM160B;
++ info->sector_count = 35;
++ info->size = 0x00200000;
++ info->start[0] = (ulong)addr;
++ info->start[1] = (ulong)addr + 0x4000;
++ info->start[2] = (ulong)addr + 0x6000;
++ info->start[3] = (ulong)addr + 0x8000;
++ for (i = 4; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * (i-3);
++ }
++ break;
++
++ case (FPW)AMD_ID_LV065D:
++ info->flash_id += FLASH_AMDLV065D;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++
++ case (FPW)AMD_ID_MIRROR:
++ /* MIRROR BIT FLASH, read more ID bytes */
++ id3 = (FPW)addr[FLASH_ID3];
++ id4 = (FPW)addr[FLASH_ID4];
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
++ {
++ info->flash_id += FLASH_AMLV640U;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ else if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
++ {
++ /* attention: only the first 16 MB will be used in u-boot */
++ info->flash_id += FLASH_AMLV256U;
++ info->sector_count = 256;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ else
++ {
++ /* This is the default NOR flash for DM355 */
++ info->flash_id += FLASH_S29GL256N;
++ info->sector_count = 256;
++ info->size = 0x02000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ }
++ break;
++ }
++ case (FPW)INTEL_ID_28F128P30T:
++ /* Intel StrataFlash 28F128P30T */
++ info->flash_id += FLASH_28F128P30T;
++ info->sector_count = 131;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ if (i < 127)
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ else
++ info->start[i] = (ulong)addr + 0xfe0000 + 0x8000 * (i-127);
++ }
++ break;
++
++ /* fall thru to here ! */
++ default:
++ printf ("unknown AMD device=%x %x %x",
++ (FPW)addr[FLASH_ID2],
++ (FPW)addr[FLASH_ID3],
++ (FPW)addr[FLASH_ID4]);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0x800000;
++ break;
++ }
++
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ return (info->size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ FPWV *addr;
++ int flag, prot, sect;
++ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
++ ulong start, now, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160B:
++ case FLASH_AMLV640U:
++ break;
++ case FLASH_AMLV256U:
++ break;
++ case FLASH_28F128P30T:
++ break;
++ case FLASH_S29GL256N:
++ break;
++ case FLASH_UNKNOWN:
++ default:
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect=s_first; sect<=s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
++
++ if (info->protect[sect] != 0) /*bmw esteem192e ispan mx1fs2 RPXlite tqm8540
++ protected, skip it */
++ continue;
++
++ printf ("Erasing sector %2d ... ", sect);
++
++ if ( sect == s_first )
++ {
++ addr = (FPWV *)(((info->start[sect]) & EVMDM355_CPLD_MASK) >> 14 );
++ }
++ else
++ {
++ addr += 2;
++ }
++
++ EVMDM355_CPLD = addr;
++
++ if (intel) {
++ *addr = (FPW)0x00600060; /* unlock block setup */
++ *addr = (FPW)0x00d000d0; /* unlock block confirm */
++ *addr = (FPW)0x00500050; /* clear status register */
++ *addr = (FPW)0x00200020; /* erase setup */
++ *addr = (FPW)0x00D000D0; /* erase confirm */
++ while((*addr & 0x80) == 0);
++ printf("done.\n");
++ }
++ else {
++ /* must be AMD style if not Intel */
++ FPWV *base; /* first address in bank */
++
++ base = (FPWV *)(info->start[0]);
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
++ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
++ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
++ base[0] = (FPW)0x00300030; /* erase sector */
++ while (!(*((vHwdptr)base) & 0x80));
++ printf("done.\n");
++ }
++
++
++ }
++
++ EVMDM355_CPLD = 0;
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ printf (" Erase Operation Completed.\n");
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
++ int bytes; /* number of bytes to program in current word */
++ int left; /* number of bytes left to program */
++ int res;
++ ulong cp, wp;
++ int count, i, l, rc, port_width;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++
++ /* get lower word aligned address */
++ wp = (addr & ~1);
++ port_width = 2;
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_word (info, wp, SWAP (data))) != 0) {
++ return (rc);
++ }
++ wp += port_width;
++ cnt -= port_width;
++
++ if (count++ > 0x800) {
++ spin_wheel ();
++ count = 0;
++ }
++ }
++
++ if (cnt == 0) {
++ return (0);
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ return (write_word (info, wp, SWAP (data)));
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word to Flash
++ * A word is 16 or 32 bits, whichever the bus width of the flash bank
++ * (not an individual chip) is.
++ *
++ * returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_word (flash_info_t *info, FPWV *plAddress, FPW ulData)
++{
++ ulong start;
++ int flag;
++ int res = 0; /* result, assume success */
++ FPWV *base; /* first address in flash bank */
++ volatile USHORT *psAddress;
++ volatile USHORT *address_cs;
++ USHORT tmp;
++ ULONG tmp_ptr;
++
++ // Lower WORD.
++ psAddress = (USHORT *)plAddress;
++ tmp_ptr = (ULONG) plAddress;
++ address_cs = (USHORT *) (tmp_ptr & 0xFE000000);
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ {
++ *plAddress = (FPW)0x00400040;
++ *plAddress = ulData;
++ while ((*plAddress & 0x80) == 0);
++ }
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ {
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xAA);
++ *((vHwdptr)address_cs + 0x2AA) = ((Hwd)0x55);
++ *((vHwdptr)address_cs + 0x555) = ((Hwd)0xA0);
++ *psAddress = ulData;
++ // Wait for ready.
++ while (1)
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ if(tmp & 0x20) // Exceeded Time Limit
++ {
++ tmp = *psAddress;
++ if( (tmp & 0x80) == (ulData & 0x80))
++ {
++ break;
++ }
++ else
++ {
++ flash_reset_sector(info, (ULONG) psAddress);
++ return 1;
++ }
++ }
++ }
++ }
++ }
++
++ // Return to read mode
++ flash_reset_sector(info, (ULONG) psAddress);
++
++ // Verify the data.
++ if (*psAddress != ulData)
++ {
++ return 1;
++ printf("Write of one 16-bit word failed\n");
++ }
++ return 0;
++}
++
++void inline spin_wheel (void)
++{
++ static int p = 0;
++ static char w[] = "\\/-";
++
++ printf ("\010%c", w[p]);
++ (++p == 3) ? (p = 0) : 0;
++}
++#endif
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/flash_params.h u-boot-1.2.0-leopard/board/dm355_leopard/flash_params.h
+--- u-boot-1.2.0/board/dm355_leopard/flash_params.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/flash_params.h 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,319 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _FLASH_PARAMSH_
++#define _FLASH_PARAMSH_
++//
++//Structs
++//
++typedef struct _PageInfo
++{
++ ULONG reserved;
++ BYTE BlockReserved;
++ BYTE BadBlockFlag;
++ USHORT reserved2;
++}PageInfo, *PPageInfo;
++
++typedef struct
++{
++ ULONG ReturnValue;
++ ULONG ReadAddress;
++ ULONG WriteAddress;
++ ULONG Size;
++} Download_Parms, *PDownload_Parms;
++
++#define NO_ERROR 0
++#define CORRECTED_ERROR 1
++#define ECC_ERROR 2
++#define UNCORRECTED_ERROR 3
++
++
++#define BIT0 0x00000001
++#define BIT1 0x00000002
++#define BIT2 0x00000004
++#define BIT3 0x00000008
++#define BIT4 0x00000010
++#define BIT5 0x00000020
++#define BIT6 0x00000040
++#define BIT7 0x00000080
++#define BIT8 0x00000100
++#define BIT9 0x00000200
++#define BIT10 0x00000400
++#define BIT11 0x00000800
++#define BIT12 0x00001000
++#define BIT13 0x00002000
++#define BIT14 0x00004000
++#define BIT15 0x00008000
++#define BIT16 0x00010000
++#define BIT17 0x00020000
++#define BIT18 0x00040000
++#define BIT19 0x00080000
++#define BIT20 0x00100000
++#define BIT21 0x00200000
++#define BIT22 0x00400000
++#define BIT23 0x00800000
++#define BIT24 0x01000000
++#define BIT25 0x02000000
++#define BIT26 0x04000000
++#define BIT27 0x08000000
++#define BIT28 0x10000000
++#define BIT29 0x20000000
++#define BIT30 0x40000000
++#define BIT31 0x80000000
++
++
++
++// Status bit pattern
++#define STATUS_READY 0x40
++#define STATUS_ERROR 0x01
++//
++//NOR SUPPORT
++//
++// Flash ID Commands INTEL
++#define INTEL_ID_CMD ((Hwd)0x0090) // INTEL ID CMD
++#define INTEL_MANF_ID ((Hwd)0x0089) // INTEL Manf ID expected
++#define INTEL_DEVICE_8T ((Hwd)0x88F1) // INTEL 8Mb top device code
++#define INTEL_DEVICE_8B ((Hwd)0x88F2) // INTEL 8Mb bottom device code
++#define INTEL_DEVICE_16T ((Hwd)0x88F3) // INTEL 16Mb top device code
++#define INTEL_DEVICE_16B ((Hwd)0x88F4) // INTEL 16Mb bottom device code
++#define INTELS_J3_DEVICE_32 ((Hwd)0x0016) // INTEL Strata J3 32Mb device code
++#define INTELS_J3_DEVICE_64 ((Hwd)0x0017) // INTEL Strata J3 64Mb device code
++#define INTELS_J3_DEVICE_128 ((Hwd)0x0018) // INTEL Strata J3 128Mb device code
++#define INTELS_K3_DEVICE_64 ((Hwd)0x8801) // INTEL Strata K3 64Mb device code
++#define INTELS_K3_DEVICE_128 ((Hwd)0x8802) // INTEL Strata K3 128Mb device code
++#define INTELS_K3_DEVICE_256 ((Hwd)0x8803) // INTEL Strata K3 256Mb device code
++#define INTELS_W18_DEVICE_128T ((Hwd)0x8876) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_W18_DEVICE_128B ((Hwd)0x8867) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_128T ((Hwd)0x880C) // INTEL Wirless Flash Top 128 Mb device code
++#define INTELS_L18_DEVICE_128B ((Hwd)0x880F) // INTEL Wirless Flash Bottom 128 Mb device code
++#define INTELS_L18_DEVICE_256T ((Hwd)0x880D) // INTEL Wirless Flash Top 256 Mb device code
++#define INTELS_L18_DEVICE_256B ((Hwd)0x8810) // INTEL Wirless Flash Bottom 256 Mb device code
++#define INTELS_K18_DEVICE_256B ((Hwd)0x8807) // INTEL Wirless Flash Bottom 256 Mb device code
++#define AMD1_DEVICE_ID ((Hwd)0x2253) // AMD29DL323CB
++#define AMD2_DEVICE_ID ((Hwd)0x2249) // AMD29LV160D
++#define AMD3_DEVICE_ID1 ((Hwd)0x2212) // AMD29LV256M
++#define AMD3_DEVICE_ID2 ((Hwd)0x2201) // AMD29LV256M
++// Flash ID Commands FUJITSU (Programs like AMD)
++#define FUJITSU_MANF_ID ((Hwd)0x04) // Fujitsu Manf ID expected
++#define FUJITSU1_DEVICE_ID ((Hwd)0x2253) // MBM29DL323BD
++//Micron Programs Like Intel or Micron
++#define MICRON_MANF_ID ((Hwd)0x002C) // MICRON Manf ID expected
++#define MICRON_MT28F_DEVICE_128T ((Hwd)0x4492) // MICRON Flash device Bottom 128 Mb
++//Samsung Programs like AMD
++#define SAMSUNG_MANF_ID ((Hwd)0x00EC) //SAMSUNG Manf ID expected
++#define SAMSUNG_K8S2815E_128T ((Hwd) 0x22F8) //SAMSUNG NOR Flash device TOP 128 Mb
++// Flash Erase Commands AMD and FUJITSU
++// Flash ID Commands AMD
++#define AMD_ID_CMD0 ((Hwd)0xAA) // AMD ID CMD 0
++#define AMD_CMD0_ADDR 0x555 // AMD CMD0 Offset
++#define AMD_ID_CMD1 ((Hwd)0x55) // AMD ID CMD 1
++#define AMD_CMD1_ADDR 0x2AA // AMD CMD1 Offset
++#define AMD_ID_CMD2 ((Hwd)0x90) // AMD ID CMD 2
++#define AMD_CMD2_ADDR 0x555 // AMD CMD2 Offset
++#define AMD_MANF_ID ((Hwd)0x01) // AMD Manf ID expected
++#define AMD_DEVICE_ID_MULTI ((Hwd)0x227E)// Indicates Multi-Address Device ID
++#define AMD_DEVICE_ID_OFFSET 0x1
++#define AMD_DEVICE_ID_OFFSET1 0x0E // First Addr for Multi-Address ID
++#define AMD_DEVICE_ID_OFFSET2 0x0F // Second Addr for Multi-Address ID
++#define AMD_DEVICE_RESET ((Hwd)0x00F0) // AMD Device Reset Command
++#define AMD_ERASE_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_CMD3 ((Hwd)0xAA) // AMD29LV017B Erase CMD 3
++#define AMD_ERASE_CMD4 ((Hwd)0x55) // AMD29LV017B Erase CMD 4
++#define AMD_ERASE_CMD5 ((Hwd)0x10) // AMD29LV017B Erase CMD 5
++#define AMD_ERASE_DONE ((Hwd)0xFFFF) // AMD29LV017B Erase Done
++#define AMD_ERASE_BLK_CMD0 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD1 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD2 ((Hwd)0x80)
++#define AMD_ERASE_BLK_CMD3 ((Hwd)0xAA)
++#define AMD_ERASE_BLK_CMD4 ((Hwd)0x55)
++#define AMD_ERASE_BLK_CMD5 ((Hwd)0x30)
++#define AMD_PROG_CMD0 ((Hwd)0xAA)
++#define AMD_PROG_CMD1 ((Hwd)0x55)
++#define AMD_PROG_CMD2 ((Hwd)0xA0)
++#define AMD2_ERASE_CMD0 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 0
++#define AMD2_ERASE_CMD1 ((Hwd)0x0055) // AMD29DL800B Erase CMD 1
++#define AMD2_ERASE_CMD2 ((Hwd)0x0080) // AMD29DL800B Erase CMD 2
++#define AMD2_ERASE_CMD3 ((Hwd)0x00AA) // AMD29DL800B Erase CMD 3
++#define AMD2_ERASE_CMD4 ((Hwd)0x0055) // AMD29DL800B Erase CMD 4
++#define AMD2_ERASE_CMD5 ((Hwd)0x0030) // AMD29DL800B Erase CMD 5
++#define AMD2_ERASE_DONE ((Hwd)0x00FF) // AMD29DL800B Erase Done
++#define AMD_WRT_BUF_LOAD_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_LOAD_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_LOAD_CMD2 ((Hwd)0x25)
++#define AMD_WRT_BUF_CONF_CMD0 ((Hwd)0x29)
++#define AMD_WRT_BUF_ABORT_RESET_CMD0 ((Hwd)0xAA)
++#define AMD_WRT_BUF_ABORT_RESET_CMD1 ((Hwd)0x55)
++#define AMD_WRT_BUF_ABORT_RESET_CMD2 ((Hwd)0xF0)
++// Flash Erase Commands INTEL
++#define INTEL_ERASE_CMD0 ((Hwd)0x0020) // INTEL Erase CMD 0
++#define INTEL_ERASE_CMD1 ((Hwd)0x00D0) // INTEL Erase CMD 1
++#define INTEL_ERASE_DONE ((Hwd)0x0080) // INTEL Erase Done
++#define INTEL_READ_MODE ((Hwd)0x00FF) // INTEL Read Array Mode
++#define STRATA_READ 0x4
++#define STRATA_WRITE 0x8
++// Flash Block Information
++// Intel Burst devices:
++// 2MB each (8 8KB [param] and 31 64KB [main] blocks each) for 8MB total
++#define NUM_INTEL_BURST_BLOCKS 8
++#define PARAM_SET0 0
++#define MAIN_SET0 1
++#define PARAM_SET1 2
++#define MAIN_SET1 3
++#define PARAM_SET2 4
++#define MAIN_SET2 5
++#define PARAM_SET3 6
++#define MAIN_SET3 7
++// Intel Strata devices:
++// 4MB each (32 128KB blocks each) for 8MB total
++// 8MB each (64 128KB blocks each) for 16MB total
++// 16MB each (128 128KB blocks each) for 32MB total
++#define NUM_INTEL_STRATA_BLOCKS 8
++#define BLOCK_SET0 0
++#define BLOCK_SET1 1
++#define BLOCK_SET2 2
++#define BLOCK_SET3 3
++#define BLOCK_SET4 4
++#define BLOCK_SET5 5
++#define BLOCK_SET6 6
++#define BLOCK_SET7 7
++// For AMD Flash
++#define NUM_AMD_SECTORS 8 // Only using the first 8 8-KB sections (64 KB Total)
++#define AMD_ADDRESS_CS_MASK 0xFE000000 //--AMD-- Set-up as 0xFE000000 per Jon Hunter (Ti)
++// Flash Types
++enum NORFlashType {
++ FLASH_NOT_FOUND,
++ FLASH_UNSUPPORTED,
++ FLASH_AMD_LV017_2MB, // (AMD AM29LV017B-80RFC/RE)
++ FLASH_AMD_DL800_1MB_BOTTOM, // (AMD AM29DL800BB-70EC)
++ FLASH_AMD_DL800_1MB_TOP, // (AMD AM29DL800BT-70EC)
++ FLASH_AMD_DL323_4MB_BOTTOM, // (AMD AM29DL323CB-70EC)
++ FLASH_AMD_DL323_4MB_TOP, // (AMD AM29DL323BT-70EC)
++ FLASH_AMD_LV160_2MB_BOTTOM,
++ FLASH_AMD_LV160_2MB_TOP,
++ FLASH_AMD_LV256M_32MB, // (AMD AM29LV256MH/L)
++ FLASH_INTEL_BURST_8MB_BOTTOM, // (Intel DT28F80F3B-95)
++ FLASH_INTEL_BURST_8MB_TOP, // (Intel DT28F80F3T-95)
++ FLASH_INTEL_BURST_16MB_BOTTOM, // (Intel DT28F160F3B-95)
++ FLASH_INTEL_BURST_16MB_TOP, // (Intel DT28F160F3T-95)
++ FLASH_INTEL_STRATA_J3_4MB, // (Intel DT28F320J3A)
++ FLASH_INTEL_STRATA_J3_8MB, // (Intel DT28F640J3A)
++ FLASH_INTEL_STRATA_J3_16MB, // (Intel DT28F128J3A)
++ FLASH_FUJITSU_DL323_4MB_BOTTOM, // (Fujitsu DL323 Bottom
++ FLASH_INTEL_STRATA_K3_8MB, // (Intel 28F64K3C115)
++ FLASH_INTEL_STRATA_K3_16MB, // (Intel 28F128K3C115)
++ FLASH_INTEL_STRATA_K3_32MB, // (Intel 28F256K3C115)
++ FLASH_INTEL_W18_16MB_TOP, // (Intel 28F128W18T) }
++ FLASH_INTEL_W18_16MB_BOTTOM, // (Intel 28F128W18B) }
++ FLASH_INTEL_L18_16MB_TOP, // (Intel 28F128L18T) }
++ FLASH_INTEL_L18_16MB_BOTTOM, // (Intel 28F128L18B) }
++ FLASH_INTEL_L18_32MB_TOP, // (Intel 28F256L18T) }
++ FLASH_INTEL_L18_32MB_BOTTOM, // (Intel 28F256L18B) }
++ FLASH_INTEL_K18_32MB_BOTTOM, // (Intel 28F256K18B) }
++ FLASH_MICRON_16MB_TOP, // (Micron MT28F160C34 )
++ FLASH_SAMSUNG_16MB_TOP // (Samsung K8S281ETA)
++};
++////NAND SUPPORT
++//
++enum NANDFlashType {
++ NANDFLASH_NOT_FOUND,
++ NANDFLASH_SAMSUNG_32x8_Q, // (Samsung K9F5608Q0B)
++ NANDFLASH_SAMSUNG_32x8_U, // (Samsung K9F5608U0B)
++ NANDFLASH_SAMSUNG_16x16_Q, // (Samsung K9F5616Q0B)
++ NANDFLASH_SAMSUNG_16x16_U, // (Samsung K9F5616U0B)
++ NANDFLASH_SAMSUNG_16x8_U // (Samsung K9F1G08QOM)
++};
++// Samsung Manufacture Code
++#define SAMSUNG_MANUFACT_ID 0xEC
++// Samsung Nand Flash Device ID
++#define SAMSUNG_K9F5608Q0B 0x35
++#define SAMSUNG_K9F5608U0B 0x75
++#define SAMSUNG_K9F5616Q0B 0x45
++#define SAMSUNG_K9F5616U0B 0x55
++// MACROS for NAND Flash support
++// Flash Chip Capability
++#define NUM_BLOCKS 0x800 // 32 MB On-board NAND flash.
++#define PAGE_SIZE 512
++#define SPARE_SIZE 16
++#define PAGES_PER_BLOCK 32
++#define PAGE_TO_BLOCK(page) ((page) >> 5 )
++#define BLOCK_TO_PAGE(block) ((block) << 5 )
++#define FILE_TO_PAGE_SIZE(fs) ((fs / PAGE_SIZE) + ((fs % PAGE_SIZE) ? 1 : 0))
++// For flash chip that is bigger than 32 MB, we need to have 4 step address
++#ifdef NAND_SIZE_GT_32MB
++#define NEED_EXT_ADDR 1
++#else
++#define NEED_EXT_ADDR 0
++#endif
++// Nand flash block status definitions.
++#define BLOCK_STATUS_UNKNOWN 0x01
++#define BLOCK_STATUS_BAD 0x02
++#define BLOCK_STATUS_READONLY 0x04
++#define BLOCK_STATUS_RESERVED 0x08
++#define BLOCK_RESERVED 0x01
++#define BLOCK_READONLY 0x02
++#define BADBLOCKMARK 0x00
++// NAND Flash Command. This appears to be generic across all NAND flash chips
++#define CMD_READ 0x00 // Read
++#define CMD_READ1 0x01 // Read1
++#define CMD_READ2 0x50 // Read2
++#define CMD_READID 0x90 // ReadID
++#define CMD_WRITE 0x80 // Write phase 1
++#define CMD_WRITE2 0x10 // Write phase 2
++#define CMD_ERASE 0x60 // Erase phase 1
++#define CMD_ERASE2 0xd0 // Erase phase 2
++#define CMD_STATUS 0x70 // Status read
++#define CMD_RESET 0xff // Reset
++//
++//Prototpyes
++//
++// NOR Flash Dependent Function Pointers
++void (*User_Hard_Reset_Flash)(void);
++void (*User_Soft_Reset_Flash)(unsigned long addr);
++void (*User_Flash_Erase_Block)(unsigned long addr);
++void (*User_Flash_Erase_All)(unsigned long addr);
++void (*User_Flash_Write_Entry)(void);
++int (*User_Flash_Write)(unsigned long *addr, unsigned short data);
++int (*User_Flash_Optimized_Write)(unsigned long *addr, unsigned short data[], unsigned long);
++void (*User_Flash_Write_Exit)(void);
++// Flash AMD Device Dependent Routines
++void AMD_Hard_Reset_Flash(void);
++void AMD_Soft_Reset_Flash(unsigned long);
++void AMD_Flash_Erase_Block(unsigned long);
++void AMD_Flash_Erase_All(unsigned long);
++int AMD_Flash_Write(unsigned long *, unsigned short);
++int AMD_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++void AMD_Write_Buf_Abort_Reset_Flash( unsigned long plAddress );
++// Flash Intel Device Dependent Routines
++void INTEL_Hard_Reset_Flash(void);
++void INTEL_Soft_Reset_Flash(unsigned long addr);
++void INTEL_Flash_Erase_Block(unsigned long);
++int INTEL_Flash_Write(unsigned long *addr, unsigned short data);
++int INTEL_Flash_Optimized_Write(unsigned long *addr, unsigned short data[], unsigned long length);
++
++//General Functions
++void Flash_Do_Nothing(void);
++
++#endif
++
++
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/lowlevel_init.S u-boot-1.2.0-leopard/board/dm355_leopard/lowlevel_init.S
+--- u-boot-1.2.0/board/dm355_leopard/lowlevel_init.S 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/lowlevel_init.S 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,766 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2003
++ * Texas Instruments, <www.ti.com>
++ * Kshitij Gupta <Kshitij@ti.com>
++ *
++ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
++ *
++ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * Modified for DV-EVM board by Swaminathan S, Nov 2005
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#if defined(CONFIG_OMAP1610)
++#include <./configs/omap1510.h>
++#endif
++
++_TEXT_BASE:
++ .word TEXT_BASE /* sdram load addr from config.mk */
++
++.global reset_cpu
++reset_cpu:
++ bl reset_processor
++
++
++.globl lowlevel_init
++lowlevel_init:
++ /*mov pc, lr*/
++
++ /*------------------------------------------------------*
++ * mask all IRQs by setting all bits in the EINT default *
++ *------------------------------------------------------*/
++ mov r1, #0x00000000
++ ldr r0, =EINT_ENABLE0
++ str r1, [r0]
++ ldr r0, =EINT_ENABLE1
++ str r1, [r0]
++
++ /*------------------------------------------------------*
++ * Put the GEM in reset *
++ *------------------------------------------------------*/
++
++ /* Put the GEM in reset */
++ /* bhavinp: commented: No GEM in DM350*/
++#if 0
++ LDR R8, PSC_GEM_FLAG_CLEAR
++ LDR R6, MDCTL_GEM
++ LDR R7, [R6]
++ AND R7, R7, R8
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x2
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStopGem:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x2
++ CMP R7, #0x0
++ BNE checkStatClkStopGem
++
++ /* Check for GEM Reset Completion */
++checkGemStatClkStop:
++ LDR R6, MDSTAT_GEM
++ LDR R7, [R6]
++ AND R7, R7, #0x100
++ CMP R7, #0x0
++ BNE checkGemStatClkStop
++
++ /* Do this for enabling a WDT initiated reset this is a workaround
++ for a chip bug. Not required under normal situations */
++ LDR R6, P1394
++ MOV R10, #0x0
++ STR R10, [R6]
++#endif //bhavinp: commented: End
++ /*------------------------------------------------------*
++ * Enable L1 & L2 Memories in Fast mode *
++ *------------------------------------------------------*/
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, MMARG_BRF0
++ LDR R10, MMARG_BRF0_VAL
++ STR R10, [R6]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++ /*------------------------------------------------------*
++ * DDR2 PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R10, #0x0
++ LDR R6, PLL2_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R10, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++WaitPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitPPL2Loop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL2_PLLM
++ /*MOV R2, #0x13 Orig value */
++ /*MOV R2, #0xB 165MHz */
++ /*MOV R2, #0xD 189 MHz */
++ MOV R2, #0x17 /* 162 MHz */
++ STR R2, [R6] /* R2 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV2
++ MOV R3, #0x1 /* Orig */
++ /*MOV R3, #0x0*/
++ STR R3, [R6] /* R3 */
++
++ /* Program the PLL2 Divisior Value */
++ LDR R6, PLL2_DIV1
++ /*MOV R4, #0x9 Orig */
++ /*MOV R4, #0x5 165MHz */
++ /*MOV R4, #0x6 189 MHz */
++ MOV R4, #0xB /* 54 MHz */
++ STR R4, [R6] /* R4 */
++
++ /* PLL2 DIV1 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV2
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop_0:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop_0
++
++ /* PLL2 DIV2 MMR */
++ LDR R8, PLL2_DIV_MASK
++ LDR R6, PLL2_DIV1
++ LDR R9, [R6]
++ AND R8, R8, R9
++ MOV R9, #0X1
++ MOV R9, R9, LSL #15
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Program the GOSET bit to take new divier values */
++ LDR R6, PLL2_PLLCMD
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Wait for Done */
++ LDR R6, PLL2_PLLSTAT
++doneLoop:
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE doneLoop
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0x218
++ResetPPL2Loop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetPPL2Loop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++PLL2Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL2Lock
++
++ /* Enable the PLL */
++ LDR R6, PLL2_CTL
++ LDR R8, [R6]
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkStop
++
++ /*------------------------------------------------------*
++ * Program DDR2 MMRs for 162MHz Setting *
++ *------------------------------------------------------*/
++
++ /* Program PHY Control Register */
++ LDR R6, DDRCTL
++ LDR R7, DDRCTL_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM Bank Config Register */
++ LDR R6, SDCFG
++ LDR R7, SDCFG_VAL
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-0 Config Register */
++ LDR R6, SDTIM0
++ LDR R7, SDTIM0_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDTIM1
++ LDR R7, SDTIM1_VAL_162MHz
++ STR R7, [R6]
++
++ /* Program the SDRAM Bang Config Control Register */
++ LDR R10, MASK_VAL
++ LDR R8, SDCFG
++ LDR R9, SDCFG_VAL
++ AND R9, R9, R10
++ STR R9, [R8]
++
++ /* Program SDRAM TIM-1 Config Register */
++ LDR R6, SDREF
++ LDR R7, SDREF_VAL
++ STR R7, [R6]
++
++ /*------------------------------------------------------*
++ * Issue Soft Reset to DDR Module *
++ *------------------------------------------------------*/
++
++ /* Issue a Dummy DDR2 read/write */
++ LDR R8, DDR2_VAL
++ LDR R7, DUMMY_VAL
++ STR R7, [R8]
++ LDR R7, [R8]
++
++ /* Shut down the DDR2 LPSC Module */
++ LDR R8, PSC_FLAG_CLEAR
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, R8
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkStop2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkStop2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkStop2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x1
++ BNE checkDDRStatClkStop2
++
++ /*------------------------------------------------------*
++ * Turn DDR2 Controller Clocks On *
++ *------------------------------------------------------*/
++
++ /* Enable the DDR2 LPSC Module */
++ LDR R6, MDCTL_DDR2_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x3
++ STR R7, [R6]
++
++ /* Enable the Power Domain Transition Command */
++ LDR R6, PTCMD_0
++ LDR R7, [R6]
++ ORR R7, R7, #0x1
++ STR R7, [R6]
++
++ /* Check for Transition Complete(PTSTAT) */
++checkStatClkEn2:
++ LDR R6, PTSTAT_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1
++ CMP R7, #0x0
++ BNE checkStatClkEn2
++
++ /* Check for DDR2 Controller Enable Completion */
++checkDDRStatClkEn2:
++ LDR R6, MDSTAT_DDR2_0
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ CMP R7, #0x3
++ BNE checkDDRStatClkEn2
++
++ /* DDR Writes and Reads */
++ LDR R6, CFGTEST
++ MOV R3, #0x1
++ STR R3, [R6] /* R3 */
++
++ /*------------------------------------------------------*
++ * System PLL Intialization *
++ *------------------------------------------------------*/
++
++ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
++ MOV R2, #0x0
++ LDR R6, PLL1_CTL
++ LDR R7, PLL_CLKSRC_MASK
++ LDR R8, [R6]
++ AND R8, R8, R7
++ MOV R9, R2, LSL #0x8
++ ORR R8, R8, R9
++ STR R8, [R6]
++
++ /* Select the PLLEN source */
++ LDR R7, PLL_ENSRC_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Bypass the PLL */
++ LDR R7, PLL_BYPASS_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
++ MOV R10, #0x20
++
++WaitLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitLoop
++
++ /* Reset the PLL */
++ LDR R7, PLL_RESET_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Disable the PLL */
++ ORR R8, R8, #0x10
++ STR R8, [R6]
++
++ /* Power up the PLL */
++ LDR R7, PLL_PWRUP_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Enable the PLL from Disable Mode */
++ LDR R7, PLL_DISABLE_ENABLE_MASK
++ AND R8, R8, R7
++ STR R8, [R6]
++
++ /* Program the PLL Multiplier */
++ LDR R6, PLL1_PLLM
++ /*MOV R3, #0x10 As per Amit, PLL should be in normal mode i.e X by 16 */
++ /*MOV R3, #0x11 As per Ebby 486 MHz */
++ /*MOV R3, #0x14 For 567MHz */
++ MOV R3, #0x15 /* For 594MHz */
++ STR R3, [R6]
++
++ /* Wait for PLL to Reset Properly */
++ MOV R10, #0xFF
++
++ResetLoop:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE ResetLoop
++
++ /* Bring PLL out of Reset */
++ LDR R6, PLL1_CTL
++ ORR R8, R8, #0x08
++ STR R8, [R6]
++
++ /* Wait for PLL to Lock */
++ LDR R10, PLL_LOCK_COUNT
++
++PLL1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE PLL1Lock
++
++ /* Enable the PLL */
++ ORR R8, R8, #0x01
++ STR R8, [R6]
++
++ nop
++ nop
++ nop
++ nop
++
++ /*------------------------------------------------------*
++ * AEMIF configuration for NOR Flash (double check) *
++ *------------------------------------------------------*/
++ LDR R0, _PINMUX0
++ LDR R1, _DEV_SETTING
++ STR R1, [R0]
++
++ LDR R0, WAITCFG
++ LDR R1, WAITCFG_VAL
++ LDR R2, [R0]
++ ORR R2, R2, R1
++ STR R2, [R0]
++
++ LDR R0, ACFG3
++ LDR R1, ACFG3_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG4
++ LDR R1, ACFG4_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ LDR R0, ACFG5
++ LDR R1, ACFG5_VAL
++ LDR R2, [R0]
++ AND R1, R2, R1
++ STR R1, [R0]
++
++ /*--------------------------------------*
++ * VTP manual Calibration *
++ *--------------------------------------*/
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR0
++ STR R1, [R0]
++
++ LDR R0, VTPIOCR
++ LDR R1, VTP_MMR1
++ STR R1, [R0]
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTPLock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTPLock
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x1
++ STR R10, [R6]
++
++ LDR R6, DDRVTPR
++ LDR R7, [R6]
++ AND R7, R7, #0x1F
++ AND R8, R7, #0x3E0
++ ORR R8, R7, R8
++ LDR R7, VTP_RECAL
++ ORR R8, R7, R8
++ LDR R7, VTP_EN
++ ORR R8, R7, R8
++ STR R8, [R0]
++
++
++ /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
++ LDR R10, VTP_LOCK_COUNT
++VTP1Lock:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE VTP1Lock
++
++ LDR R1, [R0]
++ LDR R2, VTP_MASK
++ AND R2, R1, R2
++ STR R2, [R0]
++
++ LDR R6, DFT_ENABLE
++ MOV R10, #0x0
++ STR R10, [R6]
++
++
++ /* Start MPU Timer 1 */
++/* MOV R10, #0x1AFFFFFF
++
++WaitRam:
++ SUB R10, R10, #0x1
++ CMP R10, #0x0
++ BNE WaitRam
++*/
++
++ /* back to arch calling code */
++ mov pc, lr
++
++ /* the literal pools origin */
++ .ltorg
++
++REG_TC_EMIFS_CONFIG: /* 32 bits */
++ .word 0xfffecc0c
++REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
++ .word 0xfffecc10
++REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
++ .word 0xfffecc14
++REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
++ .word 0xfffecc18
++REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
++ .word 0xfffecc1c
++
++_PINMUX0: .word 0x01C40000 /* Device Configuration Registers */
++_PINMUX1: .word 0x01C40004 /* Device Configuration Registers */
++
++_DEV_SETTING: .word 0x00000C1F
++
++AEMIF_BASE_ADDR: .word 0x01E10000
++WAITCFG: .word 0x01E10004
++ACFG2: .word 0x01E10010
++ACFG3: .word 0x01E10014
++ACFG4: .word 0x01E10018
++ACFG5: .word 0x01E1001C
++
++WAITCFG_VAL: .word 0x0
++ACFG2_VAL: .word 0x3FFFFFFD
++ACFG3_VAL: .word 0x3FFFFFFD
++ACFG4_VAL: .word 0x3FFFFFFD
++ACFG5_VAL: .word 0x3FFFFFFD
++
++MDCTL_DDR2: .word 0x01C41A34
++PTCMD: .word 0x01C41120
++PTSTAT: .word 0x01C41128
++MDSTAT_DDR2: .word 0x01C41834
++
++MDCTL_TPCC: .word 0x01C41A08
++MDSTAT_TPCC: .word 0x01C41808
++
++MDCTL_TPTC0: .word 0x01C41A0C
++MDSTAT_TPTC0: .word 0x01C4180C
++
++MDCTL_TPTC1: .word 0x01C41A10
++MDSTAT_TPTC1: .word 0x01C41810
++
++DDR2DEBUG: .word 0x8FFFF000
++
++/* EINT0 register */
++EINT_ENABLE0:
++ .word 0x01c48018
++
++/* EINT1 register */
++EINT_ENABLE1:
++ .word 0x01c4801C
++
++CLEAR_FLAG: .word 0xFFFFFFFF
++EDMA_PARAM0_D_S_BIDX_VAL: .word 0x00010001
++PSC_FLAG_CLEAR: .word 0xFFFFFFE0
++PSC_GEM_FLAG_CLEAR: .word 0xFFFFFEFF
++MDCTL_TPCC_SYNC: .word 0x01C41A08
++MDSTAT_TPCC_SYNC: .word 0x01C41808
++
++MDCTL_TPTC0_SYNC: .word 0x01C41A0C
++MDSTAT_TPTC0_SYNC: .word 0x01C4180C
++
++MDCTL_TPTC1_SYNC: .word 0x01C41A10
++MDSTAT_TPTC1_SYNC: .word 0x01C41810
++
++PTCMD_SYNC: .word 0x01C41120
++PTSTAT_SYNC: .word 0x01C41128
++DATA_MAX: .word 0x0000FFFF
++SPIN_ADDR: .word 0x00003FFC /* ARM PC value(B $) for the DSP Test cases */
++SPIN_OPCODE: .word 0xEAFFFFFE
++
++/* Interrupt Clear Register */
++FIQ0_CLEAR: .word 0x01C48000
++FIQ1_CLEAR: .word 0x01C48004
++IRQ0_CLEAR: .word 0x01C48008
++IRQ1_CLEAR: .word 0x01C4800C
++
++/* DDR2 MMR & CONFIGURATION VALUES for 75 MHZ */
++DDRCTL: .word 0x200000E4
++SDREF: .word 0x2000000C
++SDCFG: .word 0x20000008
++SDTIM0: .word 0x20000010
++SDTIM1: .word 0x20000014
++SDSTAT: .word 0x20000004
++VTPIOCR: .word 0x200000F0 /* VTP IO Control register */
++DDRVTPR: .word 0x01C42030 /* DDR VPTR MMR */
++DFT_ENABLE: .word 0x01C4004C
++VTP_MMR0: .word 0x201F
++VTP_MMR1: .word 0xA01F
++PCH_MASK: .word 0x3E0
++VTP_LOCK_COUNT: .word 0x5b0
++VTP_MASK: .word 0xFFFFDFFF
++VTP_RECAL: .word 0x40000
++VTP_EN: .word 0x02000
++
++
++CFGTEST: .word 0x80010000
++
++/* original values
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00008832
++MASK_VAL: .word 0x00000FFF
++SDTIM0_VAL_135MHz: .word 0x30923A91
++SDTIM1_VAL_135MHz: .word 0x0019c722
++SDREF_VAL: .word 0x000005c3
++*/
++
++/* 162MHz as per GEL file for DVEVM with Micron DDR2 SDRAM */
++DDRCTL_VAL: .word 0x50006405
++SDCFG_VAL: .word 0x00178632 /* CL=3 for MT47H64M16BT-5E */
++MASK_VAL: .word 0xFFFF7FFF
++SDTIM0_VAL_162MHz: .word 0x28923211
++SDTIM1_VAL_162MHz: .word 0x0016c722
++SDREF_VAL: .word 0x000004F0
++
++/* GEM Power Up & LPSC Control Register */
++CHP_SHRTSW: .word 0x01C40038
++
++PD1_CTL: .word 0x01C41304
++EPCPR: .word 0x01C41070
++EPCCR: .word 0x01C41078
++MDCTL_GEM: .word 0x01C41A9C
++MDSTAT_GEM: .word 0x01C4189C
++MDCTL_IMCOP: .word 0x01C41AA0
++MDSTAT_IMCOP: .word 0x01C418A0
++
++PTCMD_0: .word 0x01C41120
++PTSTAT_0: .word 0x01C41128
++P1394: .word 0x01C41a20
++
++PLL_CLKSRC_MASK: .word 0xFFFFFEFF /* Mask the Clock Mode bit and it is programmble through the run script */
++PLL_ENSRC_MASK: .word 0xFFFFFFDF /* Select the PLLEN source */
++PLL_BYPASS_MASK: .word 0xFFFFFFFE /* Put the PLL in BYPASS, eventhough the device */
++PLL_RESET_MASK: .word 0xFFFFFFF7 /* Put the PLL in Reset Mode */
++PLL_PWRUP_MASK: .word 0xFFFFFFFD /* PLL Power up Mask Bit */
++PLL_DISABLE_ENABLE_MASK: .word 0xFFFFFFEF /* Enable the PLL from Disable */
++PLL_LOCK_COUNT: .word 0x2000
++
++/* PLL1-SYSTEM PLL MMRs */
++PLL1_CTL: .word 0x01C40900
++PLL1_PLLM: .word 0x01C40910
++
++/* PLL2-SYSTEM PLL MMRs */
++PLL2_CTL: .word 0x01C40D00
++PLL2_PLLM: .word 0x01C40D10
++PLL2_DIV2: .word 0x01C40D1C
++PLL2_DIV1: .word 0x01C40D18
++PLL2_PLLCMD: .word 0x01C40D38
++PLL2_PLLSTAT: .word 0x01C40D3C
++PLL2_BPDIV: .word 0x01C40D2C
++PLL2_DIV_MASK: .word 0xFFFF7FFF
++
++
++MDCTL_DDR2_0: .word 0x01C41A34
++MDSTAT_DDR2_0: .word 0x01C41834
++DLLPWRUPMASK: .word 0xFFFFFFEF
++DDR2_ADDR: .word 0x80000000
++
++DFT_BASEADDR: .word 0x01C42000
++MMARG_BRF0: .word 0x01C42010 /* BRF margin mode 0 (Read / write)*/
++MMARG_G10: .word 0x01C42018 /*GL margin mode 0 (Read / write)*/
++MMARG_BRF0_VAL: .word 0x00444400
++DDR2_VAL: .word 0x80000000
++DUMMY_VAL: .word 0xA55AA55A
++
++/* command values */
++.equ CMD_SDRAM_NOP, 0x00000000
++.equ CMD_SDRAM_PRECHARGE, 0x00000001
++.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
++.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/nand.c u-boot-1.2.0-leopard/board/dm355_leopard/nand.c
+--- u-boot-1.2.0/board/dm355_leopard/nand.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/nand.c 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,830 @@
++/*
++ * NAND driver for TI DaVinci based boards.
++ *
++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
++ *
++ * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
++ */
++
++/*
++ *
++ * linux/drivers/mtd/nand/nand_dm355.c
++ *
++ * NAND Flash Driver
++ *
++ * Copyright (C) 2006 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ * Overview:
++ * This is a device driver for the NAND flash device found on the
++ * DaVinci board which utilizes the Samsung k9k2g08 part.
++ *
++ Modifications:
++ ver. 1.0: Feb 2005, Vinod/Sudhakar
++ -
++ *
++ */
++
++#include <common.h>
++
++#if (CONFIG_COMMANDS & CFG_CMD_NAND)
++#if !defined(CFG_NAND_LEGACY)
++
++#include <asm/arch/types.h>
++//#include "soc.h"
++#include <nand.h>
++#include <asm/arch/nand_defs.h>
++#include <asm/arch/emif_defs.h>
++
++#define NAND_Ecc_P1e (1 << 0)
++#define NAND_Ecc_P2e (1 << 1)
++#define NAND_Ecc_P4e (1 << 2)
++#define NAND_Ecc_P8e (1 << 3)
++#define NAND_Ecc_P16e (1 << 4)
++#define NAND_Ecc_P32e (1 << 5)
++#define NAND_Ecc_P64e (1 << 6)
++#define NAND_Ecc_P128e (1 << 7)
++#define NAND_Ecc_P256e (1 << 8)
++#define NAND_Ecc_P512e (1 << 9)
++#define NAND_Ecc_P1024e (1 << 10)
++#define NAND_Ecc_P2048e (1 << 11)
++
++#define NAND_Ecc_P1o (1 << 16)
++#define NAND_Ecc_P2o (1 << 17)
++#define NAND_Ecc_P4o (1 << 18)
++#define NAND_Ecc_P8o (1 << 19)
++#define NAND_Ecc_P16o (1 << 20)
++#define NAND_Ecc_P32o (1 << 21)
++#define NAND_Ecc_P64o (1 << 22)
++#define NAND_Ecc_P128o (1 << 23)
++#define NAND_Ecc_P256o (1 << 24)
++#define NAND_Ecc_P512o (1 << 25)
++#define NAND_Ecc_P1024o (1 << 26)
++#define NAND_Ecc_P2048o (1 << 27)
++
++#define TF(value) (value ? 1 : 0)
++
++#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0 )
++#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1 )
++#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2 )
++#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3 )
++#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4 )
++#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5 )
++#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6 )
++#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7 )
++
++#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0 )
++#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1 )
++#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2 )
++#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3 )
++#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4 )
++#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5 )
++#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6 )
++#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7 )
++
++#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0 )
++#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1 )
++#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2 )
++#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3 )
++#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4 )
++#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5 )
++#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6 )
++#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7 )
++
++#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0 )
++#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1 )
++#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2 )
++#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3 )
++#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4 )
++#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5 )
++#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6 )
++#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7 )
++
++#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0 )
++#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1 )
++
++#define CSL_EMIF_1_REGS 0x01E10000
++
++#define NAND4BITECCLOAD (0x01E10000 +0xBC)
++#define NAND4BITECC1 (0x01E10000 +0xC0)
++#define NAND4BITECC2 (0x01E10000 +0xC4)
++#define NAND4BITECC3 (0x01E10000 +0xC8)
++#define NAND4BITECC4 (0x01E10000 +0xCC)
++
++#define NANDERRADD1 (0x01E10000 +0xD0)
++#define NANDERRADD2 (0x01E10000 +0xD4)
++#define NANDERRVAL1 (0x01E10000 +0xD8)
++#define NANDERRVAL2 (0x01E10000 +0xDC)
++
++/* Definitions for 4-bit hardware ECC */
++#define NAND_4BITECC_MASK 0x03FF03FF
++#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
++#define ECC_STATE_NO_ERR 0x0
++#define ECC_STATE_TOO_MANY_ERRS 0x1
++#define ECC_STATE_ERR_CORR_COMP_P 0x2
++#define ECC_STATE_ERR_CORR_COMP_N 0x3
++#define ECC_MAX_CORRECTABLE_ERRORS 0x4
++extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
++
++static void nand_dm350evm_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++ struct nand_chip *this = mtd->priv;
++ u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
++ u_int32_t IO_ADDR_R = (u_int32_t)this->IO_ADDR_R;
++
++ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++
++ switch (cmd) {
++ case NAND_CTL_SETCLE:
++ IO_ADDR_W |= MASK_CLE;
++ break;
++ case NAND_CTL_SETALE:
++ IO_ADDR_W |= MASK_ALE;
++ break;
++ }
++
++ this->IO_ADDR_W = (void *)IO_ADDR_W;
++}
++
++static int nand_dm350evm_dev_ready(struct mtd_info *mtd)
++{
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ return(emif_addr->NANDFSR) /*& 0x1)*/;
++}
++
++static int nand_dm350evm_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
++{
++ while(!nand_dm350evm_dev_ready(mtd)) {;}
++ *NAND_CE0CLE = NAND_STATUS;
++ return(*NAND_CE0DATA);
++}
++
++static void nand_dm355evm_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ emifregs emif_addr;
++
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ emif_addr->NANDFCR |= (1 << 8);
++}
++
++static u32 nand_dm355evm_readecc(struct mtd_info *mtd, u32 Reg)
++{
++ u32 l = 0;
++ emifregs emif_addr;
++ emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ if (Reg == 1)
++ l = emif_addr->NANDF1ECC;
++ else if (Reg == 2)
++ l = emif_addr->NANDF2ECC;
++ else if (Reg == 3)
++ l = emif_addr->NANDF3ECC;
++ else if (Reg == 4)
++ l = emif_addr->NANDF4ECC;
++
++ return l;
++}
++
++static int nand_dm355evm_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
++ u_char *ecc_code)
++{
++ unsigned int l;
++ int reg;
++ int n;
++ struct nand_chip *this = mtd->priv;
++
++ if (this->eccmode == NAND_ECC_HW12_2048)
++ n = 4;
++ else
++ n = 1;
++
++ reg = 1;
++ while (n--) {
++ l = nand_dm355evm_readecc(mtd, reg);
++ *ecc_code++ = l; // P128e, ..., P1e
++ *ecc_code++ = l >> 16; // P128o, ..., P1o
++ // P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e
++ *ecc_code++ = ((l >> 8) & 0x0f) | ((l >> 20) & 0xf0);
++ reg++;
++ }
++ return 0;
++}
++
++static void nand_dm355evm_gen_true_ecc(u8 *ecc_buf)
++{
++ u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
++
++ ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp) );
++ ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
++ ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
++}
++
++static int nand_dm355evm_compare_ecc(u8 * ecc_data1, /* read from NAND memory */
++ u8 * ecc_data2, /* read from register */
++ u8 * page_data)
++{
++ u32 i;
++ u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
++ u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
++ u8 ecc_bit[24];
++ u8 ecc_sum = 0;
++ u8 find_bit = 0;
++ u32 find_byte = 0;
++ int isEccFF;
++
++ isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
++
++ nand_dm355evm_gen_true_ecc(ecc_data1);
++ nand_dm355evm_gen_true_ecc(ecc_data2);
++
++ for (i = 0; i <= 2; i++) {
++ *(ecc_data1 + i) = ~(*(ecc_data1 + i));
++ *(ecc_data2 + i) = ~(*(ecc_data2 + i));
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp0_bit[i] = *ecc_data1 % 2;
++ *ecc_data1 = *ecc_data1 / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp1_bit[i] = *(ecc_data1 + 1) % 2;
++ *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ tmp2_bit[i] = *(ecc_data1 + 2) % 2;
++ *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp0_bit[i] = *ecc_data2 % 2;
++ *ecc_data2 = *ecc_data2 / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp1_bit[i] = *(ecc_data2 + 1) % 2;
++ *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
++ }
++
++ for (i = 0; i < 8; i++) {
++ comp2_bit[i] = *(ecc_data2 + 2) % 2;
++ *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
++ }
++
++ for (i = 0; i< 6; i++ )
++ ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
++
++ for (i = 0; i < 8; i++)
++ ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
++
++ for (i = 0; i < 8; i++)
++ ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
++
++ ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
++ ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
++
++ for (i = 0; i < 24; i++)
++ ecc_sum += ecc_bit[i];
++
++ switch (ecc_sum) {
++ case 0:
++ /* Not reached because this function is not called if
++ ECC values are equal */
++ return 0;
++
++ case 1:
++ /* Uncorrectable error */
++ DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
++ return -1;
++
++ case 12:
++ /* Correctable error */
++ find_byte = (ecc_bit[23] << 8) +
++ (ecc_bit[21] << 7) +
++ (ecc_bit[19] << 6) +
++ (ecc_bit[17] << 5) +
++ (ecc_bit[15] << 4) +
++ (ecc_bit[13] << 3) +
++ (ecc_bit[11] << 2) +
++ (ecc_bit[9] << 1) +
++ ecc_bit[7];
++
++ find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
++
++ DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit);
++
++ page_data[find_byte] ^= (1 << find_bit);
++
++ return 0;
++
++ default:
++ if (isEccFF) {
++ if (ecc_data2[0] == 0 && ecc_data2[1] == 0 && ecc_data2[2] == 0)
++ return 0;
++ }
++ DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
++ return -1;
++ }
++}
++
++static int nand_dm355evm_correct_data(struct mtd_info *mtd, u_char *dat,
++ u_char *read_ecc, u_char *calc_ecc)
++{
++ int r = 0;
++#if 0
++ if (memcmp(read_ecc, calc_ecc, 3) != 0) {
++ u_char read_ecc_copy[3], calc_ecc_copy[3];
++ int i;
++
++ for (i = 0; i < 3; i++) {
++ read_ecc_copy[i] = read_ecc[i];
++ calc_ecc_copy[i] = calc_ecc[i];
++ }
++ r = nand_dm355_1bit_compare_ecc(read_ecc_copy, calc_ecc_copy,
++ dat);
++ }
++#endif
++ return r;
++}
++
++/*
++ * 4-bit ECC routines
++ */
++
++/*
++ * Instead of placing the spare data at the end of the page, the 4-bit ECC
++ * hardware generator requires that the page be subdivided into 4 subpages,
++ * each with its own spare data area. This structure defines the format of
++ * each of these subpages.
++ */
++static struct page_layout_item nand_dm355_hw10_512_layout[] = {
++ {.type = ITEM_TYPE_DATA,.length = 512},
++ {.type = ITEM_TYPE_OOB,.length = 6,},
++ {.type = ITEM_TYPE_ECC,.length = 10,},
++ {.type = 0,.length = 0,},
++};
++
++static struct nand_oobinfo nand_dm355_hw10_512_oobinfo = {
++ .useecc = MTD_NANDECC_AUTOPLACE,
++ .eccbytes = 10,
++ .eccpos = {6,7,8,9,10,11,12,13,14,15,
++ },
++ .oobfree ={0, 6},
++};
++
++static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
++/*
++ * We should always have a flash-based bad block table. However, if one isn't
++ * found then all blocks will be scanned to look for factory-marked bad blocks.
++ * We supply a null pattern so that no blocks will be detected as bad.
++ */
++static struct nand_bbt_descr nand_dm355_hw10_512_badblock_pattern = {
++ .options = 0, //NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
++ .offs = 5,
++ .len = 1,
++ .pattern = scan_ff_pattern
++};
++
++
++/* Generic flash bbt decriptors
++*/
++static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
++static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
++
++static struct nand_bbt_descr bbt_main_descr = {
++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
++ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
++ .offs = 0,
++ .len = 4,
++ .veroffs = 5,
++ .maxblocks = 4,
++ .pattern = bbt_pattern
++};
++
++static struct nand_bbt_descr bbt_mirror_descr = {
++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
++ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
++ .offs = 0,
++ .len = 4,
++ .veroffs = 5,
++ .maxblocks = 4,
++ .pattern = mirror_pattern
++};
++
++/*
++ * When using 4-bit ECC with a 2048-byte data + 64-byte spare page size, the
++ * oob is scattered throughout the page in 4 16-byte chunks instead of being
++ * grouped together at the end of the page. This means that the factory
++ * bad-block markers at offsets 2048 and 2049 will be overwritten when data
++ * is written to the flash. Thus, we cannot use the factory method to mark
++ * or detect bad blocks and must rely on a flash-based bad block table instead.
++ *
++ */
++static int nand_dm355_hw10_512_block_bad(struct mtd_info *mtd, loff_t ofs,
++ int getchip)
++{
++ return 0;
++}
++
++static int nand_dm355_hw10_512_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct nand_chip *this = mtd->priv;
++ int block;
++
++ /* Get block number */
++ block = ((int)ofs) >> this->bbt_erase_shift;
++ if (this->bbt)
++ this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
++
++ /* Do we have a flash based bad block table ? */
++ if (this->options & NAND_USE_FLASH_BBT)
++ return nand_update_bbt(mtd, ofs);
++
++ return 0;
++}
++
++static void nand_dm355_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ struct nand_chip *this = mtd->priv;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++
++ switch (mode) {
++ case NAND_ECC_WRITE:
++ case NAND_ECC_READ:
++ /*
++ * Start a new ECC calculation for reading or writing 512 bytes
++ * of data.
++ */
++ val = (emif_addr->NANDFCR & ~(3 << 4))
++ | (1 << 12);
++ emif_addr->NANDFCR = val;
++ break;
++ case NAND_ECC_WRITEOOB:
++ case NAND_ECC_READOOB:
++ /*
++ * Terminate ECC calculation by performing a dummy read of an
++ * ECC register. Our hardware ECC generator supports including
++ * the OOB in the ECC calculation, but the NAND core code
++ * doesn't really support that. We will only calculate the ECC
++ * on the data; errors in the non-ECC bytes in the OOB will not
++ * be detected or corrected.
++ */
++ val =(*(dv_reg_p) NAND4BITECC1);
++ break;
++ case NAND_ECC_WRITESYN:
++ case NAND_ECC_READSYN:
++ /*
++ * Our ECC calculation has already been terminated, so no need
++ * to do anything here.
++ */
++ break;
++ default:
++ break;
++ }
++}
++
++static u32 nand_dm355_4bit_readecc(struct mtd_info *mtd, unsigned int *ecc)
++{
++ unsigned int ecc_temp[4];
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++
++ ecc[0] = (*(dv_reg_p) NAND4BITECC1) & NAND_4BITECC_MASK;
++ ecc[1] = (*(dv_reg_p) NAND4BITECC2) & NAND_4BITECC_MASK;
++ ecc[2] = (*(dv_reg_p) NAND4BITECC3) & NAND_4BITECC_MASK;
++ ecc[3] = (*(dv_reg_p) NAND4BITECC4) & NAND_4BITECC_MASK;
++
++ return 0;
++}
++
++static int nand_dm355_4bit_calculate_ecc(struct mtd_info *mtd,
++ const u_char * dat,
++ u_char * ecc_code)
++{
++ unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
++ unsigned int const1 = 0, const2 = 0;
++ unsigned char count1 = 0;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++ /*
++ * Since the NAND_HWECC_SYNDROME option is enabled, this routine is
++ * only called just after the data and oob have been written. The
++ * ECC value calculated by the hardware ECC generator is available
++ * for us to read.
++ */
++ nand_dm355_4bit_readecc(mtd, hw_4ecc);
++
++ /*Convert 10 bit ecc value to 8 bit */
++ for (count1 = 0; count1 < 2; count1++) {
++ const2 = count1 * 5;
++ const1 = count1 * 2;
++
++ /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
++ ecc_code[const2] = hw_4ecc[const1] & 0xFF;
++
++ /*
++ * Take 2 bits as LSB bits from val1 (count1=0) or val5
++ * (count1=1) and 6 bits from val2 (count1=0) or val5 (count1=1)
++ */
++ ecc_code[const2 + 1] =
++ ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
++ 0xFC);
++
++ /*
++ * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
++ * 4 bits from val3 (count1=0) or val6 (count1=1)
++ */
++ ecc_code[const2 + 2] =
++ ((hw_4ecc[const1] >> 22) & 0xF) |
++ ((hw_4ecc[const1 + 1] << 4) & 0xF0);
++
++ /*
++ * Take 6 bits from val3(count1=0) or val6 (count1=1) and
++ * 2 bits from val4 (count1=0) or val7 (count1=1)
++ */
++ ecc_code[const2 + 3] =
++ ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
++ ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
++
++ /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
++ ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
++ }
++
++ return 0;
++}
++
++static int nand_dm355_4bit_compare_ecc(struct mtd_info *mtd, u8 * read_ecc, /* read from NAND */
++ u8 * page_data)
++{
++ struct nand_chip *this = mtd->priv;
++ struct nand_dm355_info *info = this->priv;
++ unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
++ int i;
++ unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
++ unsigned short *pspare = NULL, *pspare1 = NULL;
++ unsigned int numErrors, errorAddress, errorValue;
++ emifregs emif_addr = (emifregs)CSL_EMIF_1_REGS;
++ u32 val;
++
++ /*
++ * Check for an ECC where all bytes are 0xFF. If this is the case, we
++ * will assume we are looking at an erased page and we should ignore the
++ * ECC.
++ */
++ for (i = 0; i < 10; i++) {
++ if (read_ecc[i] != 0xFF)
++ break;
++ }
++ if (i == 10)
++ return 0;
++
++ /* Convert 8 bit in to 10 bit */
++ pspare = (unsigned short *)&read_ecc[2];
++ pspare1 = (unsigned short *)&read_ecc[0];
++ /* Take 10 bits from 0th and 1st bytes */
++ ecc_10bit[0] = (*pspare1) & 0x3FF; /* 10 */
++ /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
++ ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
++ | (((pspare[0]) << 6) & 0x3C0); /* 6 + 4 */
++ /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
++ ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF; /* 10 */
++ /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
++ ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
++ | ((((pspare[1])) << 2) & 0x3FC); /* 2 + 8 */
++ /* Take 8 bits from 5th byte and 2 bits from 6th byte */
++ ecc_10bit[4] = ((pspare[1]) >> 8)
++ | ((((pspare[2])) << 8) & 0x300); /* 8 + 2 */
++ /* Take 6 bits from 6th byte and 4 bits from 7th byte */
++ ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF; /* 10 */
++ /* Take 4 bits from 7th byte and 6 bits from 8th byte */
++ ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
++ | ((((pspare[3])) << 4) & 0x3F0); /* 4 + 6 */
++ /*Take 2 bits from 8th byte and 8 bits from 9th byte */
++ ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF; /* 10 */
++
++ /*
++ * Write the parity values in the NAND Flash 4-bit ECC Load register.
++ * Write each parity value one at a time starting from 4bit_ecc_val8
++ * to 4bit_ecc_val1.
++ */
++ for (i = 7; i >= 0; i--)
++ {
++ *(dv_reg_p)NAND4BITECCLOAD = ecc_10bit[i];
++ }
++
++ /*
++ * Perform a dummy read to the EMIF Revision Code and Status register.
++ * This is required to ensure time for syndrome calculation after
++ * writing the ECC values in previous step.
++ */
++ val = emif_addr->ERCSR;
++
++ /*
++ * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
++ * A syndrome value of 0 means no bit errors. If the syndrome is
++ * non-zero then go further otherwise return.
++ */
++ nand_dm355_4bit_readecc(mtd, hw_4ecc);
++
++ if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
++ hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR){
++ return 0;
++ }
++
++
++ /*
++ * Clear any previous address calculation by doing a dummy read of an
++ * error address register.
++ */
++ val = *(dv_reg_p)NANDERRADD1;
++
++ /*
++ * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
++ * register to 1.
++ */
++
++ emif_addr->NANDFCR |= (1 << 13);
++
++ /*
++ * Wait for the corr_state field (bits 8 to 11)in the
++ * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
++ */
++ do {
++ iserror = emif_addr->NANDFSR & 0xC00;
++ } while (iserror);
++
++ iserror = emif_addr->NANDFSR;
++ iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
++ iserror = iserror >> 8;
++
++#if 0
++ do {
++ iserror = emif_addr->NANDFSR;
++ iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
++ iserror = iserror >> 8;
++ } while ((ECC_STATE_NO_ERR != iserror) &&
++ (ECC_STATE_TOO_MANY_ERRS != iserror) &&
++ (ECC_STATE_ERR_CORR_COMP_P != iserror) &&
++ (ECC_STATE_ERR_CORR_COMP_N != iserror));
++#endif
++ /*
++ * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
++ * corrected (five or more errors). The number of errors
++ * calculated (err_num field) differs from the number of errors
++ * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
++ * correction complete (errors on bit 8 or 9).
++ * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
++ * complete (error exists).
++ */
++
++ if (iserror == ECC_STATE_NO_ERR)
++ return 0;
++ else if (iserror == ECC_STATE_TOO_MANY_ERRS)
++ {
++ printf("too many erros to be corrected!\n");
++ return -1;
++ }
++
++#if 1
++ numErrors = ((emif_addr->NANDFSR >> 16) & 0x3) + 1;
++// printf("numErrors =%d\n",numErrors);
++ if(numErrors==4)
++ return numErrors;
++ /* Read the error address, error value and correct */
++ for (i = 0; i < numErrors; i++) {
++ if (i > 1) {
++ errorAddress =
++ ((*(dv_reg_p)(NANDERRADD2) >>
++ (16 * (i & 1))) & 0x3FF);
++ errorAddress = ((512 + 7) - errorAddress);
++ errorValue =
++ ((*(dv_reg_p)(NANDERRVAL2) >>
++ (16 * (i & 1))) & 0xFF);
++ } else {
++ errorAddress =
++ ((*(dv_reg_p)(NANDERRADD1) >>
++ (16 * (i & 1))) & 0x3FF);
++ errorAddress = ((512 + 7) - errorAddress);
++ errorValue =
++ ((*(dv_reg_p)(NANDERRVAL1) >>
++ (16 * (i & 1))) & 0xFF);
++ }
++ /* xor the corrupt data with error value */
++ if (errorAddress < 512)
++ page_data[errorAddress] ^= errorValue;
++ }
++#else
++ numErrors = ((emif_addr->NANDFSR >> 16) & 0x3);
++ // bit 9:0
++ errorAddress = 519 - (*(dv_reg_p)NANDERRADD1 & (0x3FF));
++ errorValue = (*(dv_reg_p)NANDERRVAL1) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if(numErrors == 0)
++ return numErrors;
++ else {
++ // bit 25:16
++ errorAddress = 519 - ( (*(dv_reg_p)NANDERRADD1 & (0x3FF0000))>>16 );
++ errorValue = (*(dv_reg_p)NANDERRVAL1) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if(numErrors == 1)
++ return numErrors;
++ else {
++ // bit 9:0
++ errorAddress = 519 - (*(dv_reg_p)NANDERRADD2 & (0x3FF));
++ errorValue = (*(dv_reg_p)NANDERRVAL2) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++
++ if (numErrors == 2)
++ return numErrors;
++ else {
++ // bit 25:16
++ errorAddress = 519 - ( (*(dv_reg_p)NANDERRADD2 & (0x3FF0000))>>16 );
++ errorValue = (*(dv_reg_p)NANDERRVAL2) & (0x3FF);
++ page_data[errorAddress] ^= (char)errorValue;
++ }
++ }
++ }
++#endif
++
++ return numErrors;
++}
++
++static int nand_dm355_4bit_correct_data(struct mtd_info *mtd, u_char * dat,
++ u_char * read_ecc, u_char * calc_ecc)
++{
++ int r = 0;
++
++ /*
++ * dat points to 512 bytes of data. read_ecc points to the start of the
++ * oob area for this subpage, so the ecc values start at offset 6.
++ * The calc_ecc pointer is not needed since our caclulated ECC is
++ * already latched in the hardware ECC generator.
++ */
++#if 1
++ r = nand_dm355_4bit_compare_ecc(mtd, read_ecc + 6, dat);
++#endif
++
++ return r;
++}
++int board_nand_init(struct nand_chip *nand)
++{
++#if 0
++ nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
++ nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
++#endif
++ nand->chip_delay = 0;
++ nand->options = NAND_USE_FLASH_BBT /*| NAND_BBT_LASTBLOCK*/;
++// nand->eccmode = NAND_ECC_SOFT;
++#if 0
++ nand->eccmode = NAND_ECC_HW3_512;
++ nand->calculate_ecc = nand_dm355evm_calculate_ecc;
++ nand->correct_data = nand_dm355evm_correct_data;
++ nand->enable_hwecc = nand_dm355evm_enable_hwecc;
++#else
++ nand->eccmode = NAND_ECC_HW10_512;
++ nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME;
++ nand->autooob = &nand_dm355_hw10_512_oobinfo;
++ nand->layout = nand_dm355_hw10_512_layout;
++ nand->calculate_ecc = nand_dm355_4bit_calculate_ecc;
++ nand->correct_data = nand_dm355_4bit_correct_data;
++ nand->enable_hwecc = nand_dm355_4bit_enable_hwecc;
++ //nand->block_bad = nand_dm355_hw10_512_block_bad;
++ nand->block_markbad = nand_dm355_hw10_512_block_markbad;
++ nand->badblock_pattern = &nand_dm355_hw10_512_badblock_pattern;
++ nand->bbt_td =&bbt_main_descr;
++ nand->bbt_md = &bbt_mirror_descr;
++
++#endif
++ /* Set address of hardware control function */
++ nand->hwcontrol = nand_dm350evm_hwcontrol;
++
++ //nand->dev_ready = nand_dm350evm_dev_ready;
++ //nand->waitfunc = nand_dm350evm_waitfunc;
++
++ return 0;
++}
++
++#else
++#error "U-Boot legacy NAND support not available for DaVinci chips"
++#endif
++#endif /* CFG_USE_NAND */
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/timer.c u-boot-1.2.0-leopard/board/dm355_leopard/timer.c
+--- u-boot-1.2.0/board/dm355_leopard/timer.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/timer.c 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,72 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++
++#include "timer.h"
++
++/* Use Timer 3&4 (Timer 2) */
++#define TIMER_BASE_ADDR 0x01C21400
++
++dm350_timer_reg *dm350_timer = (dm350_timer_reg *) TIMER_BASE_ADDR;
++
++/* Timer Initialize */
++void inittimer(void)
++{
++ /* disable Timer 1 & 2 timers */
++ dm350_timer->tcr = 0;
++
++ /* Set timers to unchained dual 32 bit timers, Unreset timer34 */
++ dm350_timer->tgcr = 0x0;
++ dm350_timer->tgcr = 0x6;
++
++ /* Program the timer12 counter register - set the prd12 for right count */
++ dm350_timer->tim34 = 0;
++
++ /* The timer is programmed to expire after 0xFFFFFFFF ticks */
++ dm350_timer->prd34 = 0xFFFFFFFF;
++
++ /* Enable timer34 */
++ dm350_timer->tcr = (0x80 << 16); /* Timer34 continously enabled, Timer12 disabled */
++}
++
++/************************************************************
++********************** Reset Processor **********************
++************************************************************/
++#define WDT_BASE_ADDR 0x01C21C00
++
++
++void reset_processor(void)
++{
++ dm350_timer_reg *dm350_wdt = (dm350_timer_reg *) WDT_BASE_ADDR;
++ dm350_wdt->tgcr = 0x00000008;
++ dm350_wdt->tgcr |= 0x00000003;
++ dm350_wdt->tim12 = 0x00000000;
++ dm350_wdt->tim34 = 0x00000000;
++ dm350_wdt->prd12 = 0x00000000;
++ dm350_wdt->prd34 = 0x00000000;
++ dm350_wdt->tcr |= 0x00000040;
++ dm350_wdt->wdtcr |= 0x00004000;
++ dm350_wdt->wdtcr = 0xA5C64000;
++ dm350_wdt->wdtcr = 0xDA7E4000;
++}
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/timer.h u-boot-1.2.0-leopard/board/dm355_leopard/timer.h
+--- u-boot-1.2.0/board/dm355_leopard/timer.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/timer.h 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,51 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Modifications:
++ * ver. 1.0: Oct 2005, Swaminathan S
++ *
++ */
++#ifndef __TIMER_H__
++#define __TIMER_H__
++
++typedef volatile struct dm350_timer_reg_t
++{
++ unsigned int pid12; /* 0x0 */
++ unsigned int emumgt_clksped;/* 0x4 */
++ unsigned int gpint_en; /* 0x8 */
++ unsigned int gpdir_dat; /* 0xC */
++ unsigned int tim12; /* 0x10 */
++ unsigned int tim34; /* 0x14 */
++ unsigned int prd12; /* 0x18 */
++ unsigned int prd34; /* 0x1C */
++ unsigned int tcr; /* 0x20 */
++ unsigned int tgcr; /* 0x24 */
++ unsigned int wdtcr; /* 0x28 */
++ unsigned int tlgc; /* 0x2C */
++ unsigned int tlmr; /* 0x30 */
++} dm350_timer_reg;
++
++#endif /* __TIMER_H__ */
++
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/types.h u-boot-1.2.0-leopard/board/dm355_leopard/types.h
+--- u-boot-1.2.0/board/dm355_leopard/types.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/types.h 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,46 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ *
++ */
++#ifndef _TYPESH_
++#define _TYPESH_
++
++typedef unsigned long ULONG;
++typedef unsigned short USHORT;
++typedef unsigned long BOOL;
++typedef unsigned int WORD;
++typedef char CHAR;
++typedef unsigned char BYTE, *LPBYTE, UCHAR, *PUCHAR, PBYTE;
++
++#define FALSE 0
++#define TRUE 1
++
++#define NULL 0
++
++typedef unsigned short int Hwd;
++typedef volatile unsigned short int vHwd;
++typedef unsigned short int * Hwdptr;
++typedef volatile unsigned short int * vHwdptr;
++//typedef volatile unsigned int * vHwdptr;
++
++
++#endif
++
+diff -Nurd u-boot-1.2.0/board/dm355_leopard/u-boot.lds u-boot-1.2.0-leopard/board/dm355_leopard/u-boot.lds
+--- u-boot-1.2.0/board/dm355_leopard/u-boot.lds 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm355_leopard/u-boot.lds 2009-03-01 04:24:26.000000000 -0300
+@@ -0,0 +1,52 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm926ejs/start.o (.text)
++ *(.text)
++ }
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++ . = ALIGN(4);
++ .data : { *(.data) }
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ . = .;
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -Nurd u-boot-1.2.0/board/dm700/Makefile u-boot-1.2.0-leopard/board/dm700/Makefile
+--- u-boot-1.2.0/board/dm700/Makefile 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm700/Makefile 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := davinci_hd.o flash.o nand.o timer.o dm646x_emac.o
++SOBJS := lowlevel_init.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -Nurd u-boot-1.2.0/board/dm700/config.mk u-boot-1.2.0-leopard/board/dm700/config.mk
+--- u-boot-1.2.0/board/dm700/config.mk 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm700/config.mk 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,26 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++#
++# (C) Copyright 2003
++# Texas Instruments, <www.ti.com>
++#
++# Davinci_HD EVM board (ARM925EJS) cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# Davinci_HD EVM base board provides 1 bank of 64M x 32 bit words (256 MB)
++# DDR2 SDRAM (Has support up to 512 MB)
++# Physical Address:
++# 0x8000'0000 to 0x9000'0000
++#
++# Linux-Kernel is expected to be at 0x8000'8000, entry 0x8000'8000
++# (mem base + reserved)
++#
++# we load ourself to 0x8100'0000
++#
++#
++# Provide atleast 16MB spacing between us and the Linux Kernel image
++
++TEXT_BASE = 0x81080000
++BOARD_LIBS = drivers/nand/libnand.a
+diff -Nurd u-boot-1.2.0/board/dm700/davinci_hd.c u-boot-1.2.0-leopard/board/dm700/davinci_hd.c
+--- u-boot-1.2.0/board/dm700/davinci_hd.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm700/davinci_hd.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,203 @@
++/*
++ *
++ * Copyright (C) 2004 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++ Modifications:
++ ver. 1.0: Mar 2007, Suresh Rajashekara (Based on the file davinci.c by
++ * Swaminathan S)
++ *
++ */
++
++#include <common.h>
++#include <i2c.h>
++
++#define PLL0_PLLM *(volatile unsigned int *)0x01C40910
++#define PLL1_PLLM *(volatile unsigned int *)0x01C40D10
++#define PLL1_DIV1 *(volatile unsigned char *)0x01C40D18
++
++void davinci_hd_psc_enable(void);
++
++/*******************************************
++ Routine: delay
++ Description: Delay function
++*******************************************/
++static inline void delay (unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*******************************************
++ Routine: board_init
++ Description: Board Initialization routine
++*******************************************/
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* Arch Number. __Need to register__ */
++ gd->bd->bi_arch_number = 1500;
++ /* 1500 is a random number chosen at the time of development. We have
++ not yet registered ourselves with the ARM development community. Once
++ thats done, please change the number to the one supplied by the ARM
++ development community and replace it with a macro.*/
++
++ /* Adress of boot parameters */
++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
++
++ /* Configure MUX settings ? */
++
++ /* Power on required peripherals */
++ davinci_hd_psc_enable();
++
++ inittimer ();
++
++ return 0;
++}
++
++#define PTCMD *( volatile unsigned int* )( 0x01C41120 )
++#define PTSTAT *( volatile unsigned int* )( 0x01C41128 )
++#define PDSTAT *( volatile unsigned int* )( 0x01C41200 )
++#define PDCTL *( volatile unsigned int* )( 0x01C41300 )
++
++/* PSC Registers */
++#define PSC_ADDR 0x01C41000
++
++#define PTCMD ( PSC_ADDR + 0x120 ) /* Power domain transition
++ * commmand register */
++#define PTSTAT ( PSC_ADDR + 0x128 ) /* Power domain transition status
++ * register */
++
++/**************************************
++ Routine: davinci_hd_psc_enable
++ Description: Enable PSC domains
++**************************************/
++void davinci_hd_psc_enable ( void )
++{
++ unsigned int alwaysOnPdNum = 0, dspPdNum = 1, i;
++ int waiting;
++ unsigned int state;
++
++ /* Note this function assumes that the Power Domains are already on */
++
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x003; /* EMAC */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*20) = *(unsigned int*) (PSC_ADDR+0xA00+4*20) | 0x003; /* DDR2 */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*21) = *(unsigned int*) (PSC_ADDR+0xA00+4*21) | 0x003; /* EMIFA */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) | 0x003; /* UART0 */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*31) = *(unsigned int*) (PSC_ADDR+0xA00+4*31) | 0x003; /* I2C */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*35) = *(unsigned int*) (PSC_ADDR+0xA00+4*34) | 0x003; /* TIMER0 */
++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*35) = *(unsigned int*) (PSC_ADDR+0xA00+4*35) | 0x003; /* TIMER1 */
++
++ /* Set PTCMD.GO to 0x1 to initiate the state transtion for Modules in
++ * the ALWAYSON Power Domain */
++ *(volatile unsigned int*) PTCMD = (1<<alwaysOnPdNum);
++
++ /* Wait for PTSTAT.GOSTAT0 to clear to 0x0 */
++ while(! (((*(volatile unsigned int*) PTSTAT >> alwaysOnPdNum) & 0x00000001) == 0));
++
++ /* Enable GIO3.3V cells used for EMAC (???) */
++#define VDD3P3V_PWDN 0x01c40048
++ *(volatile unsigned int*) VDD3P3V_PWDN = 0;
++
++#define PINMUX0 0x01C40000
++#define PINMUX1 0x01C40004
++
++ /* Select UART function on UART0 */
++ *(volatile unsigned int *)PINMUX0 &= ~(0x0000003f << 18);
++ *(volatile unsigned int *)PINMUX1 &= ~(0x00000003);
++
++ /* Enable AEMIF pins */
++ *(volatile unsigned int*) PINMUX0 &= ~(0x00000007);
++}
++
++/******************************
++ Routine: misc_init_r
++ Description: Misc. init
++******************************/
++int misc_init_r (void)
++{
++ char temp[20];
++ char rtcdata[10] = { 2, 1, 0, 0, 0, 0, 0, 0, 0, 0};
++ char emac_read_addr [10] = { 0x7f, 0 }, i= 0;
++ int clk = 0;
++
++ clk = ((PLL1_PLLM + 1) * 27) / (PLL1_DIV1 + 1);
++
++ printf ("ARM Clock :- %dMHz\n", ((((PLL0_PLLM + 1) * 27 ) / 2)) );
++ printf ("DDR Clock :- %dMHz\n", (clk/2));
++
++ i2c_write (0x50, 0x00, 1, emac_read_addr, 2); /* ?? */
++ i2c_read (0x50, 0x00, 1, emac_read_addr, 6);
++ temp[0] = (emac_read_addr[0] & 0xF0) >> 4;
++ temp[1] = (emac_read_addr[0] & 0x0F);
++ temp[2] = ':';
++ temp[3] = (emac_read_addr[1] & 0xF0) >> 4;
++ temp[4] = (emac_read_addr[1] & 0x0F);
++ temp[5] = ':';
++ temp[6] = (emac_read_addr[2] & 0xF0) >> 4;
++ temp[7] = (emac_read_addr[2] & 0x0F);
++ temp[8] = ':';
++ temp[9] = (emac_read_addr[3] & 0xF0) >> 4;
++ temp[10]= (emac_read_addr[3] & 0x0F);
++ temp[11]= ':';
++ temp[12]= (emac_read_addr[4] & 0xF0) >> 4;
++ temp[13]= (emac_read_addr[4] & 0x0F);
++ temp[14]= ':';
++ temp[15]= (emac_read_addr[5] & 0xF0) >> 4;
++ temp[16]= (emac_read_addr[5] & 0x0F);
++
++ for (i = 0; i < 17; i++)
++ {
++ if (temp[i] == ':')
++ continue;
++ else if (temp[i] >= 0 && temp[i] <= 9)
++ temp[i] = temp[i] + 48;
++ else
++ temp[i] = temp[i] + 87;
++ }
++
++ temp [17] = 0;
++ if ((emac_read_addr [0] != 0xFF) ||
++ (emac_read_addr [1] != 0xFF) ||
++ (emac_read_addr [2] != 0xFF) ||
++ (emac_read_addr [3] != 0xFF) ||
++ (emac_read_addr [4] != 0xFF) ||
++ (emac_read_addr [5] != 0xFF))
++ {
++ setenv ("ethaddr", temp);
++ }
++
++ return (0);
++}
++
++/******************************
++ Routine: dram_init
++ Description: Memory Info
++******************************/
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
+diff -Nurd u-boot-1.2.0/board/dm700/dm646x_emac.c u-boot-1.2.0-leopard/board/dm700/dm646x_emac.c
+--- u-boot-1.2.0/board/dm700/dm646x_emac.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm700/dm646x_emac.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,506 @@
++/*
++ * dm644x_emac.c
++ *
++ * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
++ *
++ * Copyright (C) 2005 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++
++ * Modifications:
++ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
++ * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
++ *
++ */
++
++#include <common.h>
++#include <command.h>
++#include <net.h>
++#include "dm646x_emac.h"
++
++#ifdef CONFIG_DRIVER_TI_EMAC
++
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
++
++unsigned int emac_dbg = 0;
++#define debug_emac(fmt,args...) if (emac_dbg) printf (fmt ,##args)
++
++/* EMAC internal functions - called when eth_xxx functions are invoked by the kernel */
++static int emac_hw_init (void);
++static int emac_open (void);
++static int emac_close (void);
++static int emac_send_packet (volatile void *packet, int length);
++static int emac_rcv_packet (void);
++
++/* The driver can be entered at any of the following entry points */
++extern int eth_init (bd_t * bd);
++extern void eth_halt (void);
++extern int eth_rx (void);
++extern int eth_send (volatile void *packet, int length);
++
++int eth_hw_init (void)
++{
++ return emac_hw_init();
++}
++
++int eth_init (bd_t * bd)
++{
++ return emac_open ();
++}
++
++void eth_halt ()
++{
++ emac_close ();
++}
++
++int eth_send (volatile void *packet, int length)
++{
++ return emac_send_packet (packet, length);
++}
++
++int eth_rx ()
++{
++ return emac_rcv_packet ();
++}
++
++
++static char emac_mac_addr[] = { 0x00, 0x00, 0x5b, 0xee, 0xde, 0xad };
++
++/*
++ * This function must be called before emac_open() if you want to override
++ * the default mac address.
++ */
++
++void emac_set_mac_addr (const char *addr)
++{
++ int i;
++
++ for (i = 0; i < sizeof (emac_mac_addr); i++) {
++ emac_mac_addr[i] = addr[i];
++ }
++}
++
++/***************************
++ * EMAC Global variables
++ ***************************/
++
++/* EMAC Addresses */
++static volatile emac_regs* adap_emac = (emac_regs *) EMAC_BASE_ADDR;
++static volatile ewrap_regs* adap_ewrap = (ewrap_regs *) EMAC_WRAPPER_BASE_ADDR;
++static volatile mdio_regs* adap_mdio = (mdio_regs *) EMAC_MDIO_BASE_ADDR;
++
++/* EMAC descriptors */
++static volatile emac_desc *emac_rx_desc = (emac_desc *) (EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
++static volatile emac_desc *emac_tx_desc = (emac_desc *) (EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
++static volatile emac_desc *emac_rx_active_head = 0;
++static volatile emac_desc *emac_rx_active_tail = 0;
++static int emac_rx_queue_active = 0;
++
++/* EMAC link status */
++static int emac_link_status = 0; /* 0 = link down, 1 = link up */
++
++/* Receive packet buffers */
++static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
++
++/* This function initializes the emac hardware */
++static int emac_hw_init (void)
++{
++ /* Enabling power and reset from outside the module is required */
++ return (0);
++}
++
++/* Read a PHY register via MDIO inteface */
++static int mdio_read(int phy_addr, int reg_num)
++{
++ adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
++ ((reg_num & 0x1F) << 21) |
++ ((phy_addr & 0x1F) << 16);
++
++ /* Wait for command to complete */
++ while ((adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) != 0);
++
++ return (adap_mdio->USERACCESS0 & 0xFFFF);
++}
++
++/* Write to a PHY register via MDIO inteface */
++void mdio_write(int phy_addr, int reg_num, unsigned int data)
++{
++ /* Wait for User access register to be ready */
++ while ((adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) != 0);
++
++ adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
++ ((reg_num & 0x1F) << 21) |
++ ((phy_addr & 0x1F) << 16) |
++ (data & 0xFFFF);
++}
++
++
++/* Get PHY link state - this function accepts a PHY mask for the caller to
++ * find out if any of the passed PHY addresses is connected
++ */
++int mdio_get_link_state(unsigned int phy_mask)
++{
++ unsigned int act_phy, phy_addr = 0, link_state = 0;
++ unsigned int config;
++
++ act_phy = (adap_mdio->ALIVE & phy_mask);
++
++ if (act_phy)
++ {
++ /* find the phy number */
++ while(act_phy)
++ {
++ while(!(act_phy & 0x1))
++ {
++ phy_addr++;
++ act_phy >>= 1;
++ }
++ /* Read the status register from PHY */
++ link_state = ((mdio_read(phy_addr, MII_STATUS_REG) & 0x4) >> 2);
++ if(link_state == 1)
++ {
++ /* The link can break off anytime, hence adding the fix for boosting the PHY signal
++ * strength here so that everytime the link is found, this can be done and ensured
++ * that we dont miss it
++ */
++ config = mdio_read(phy_addr, MII_DIGITAL_CONFIG_REG);
++ config |= 0x800;
++ mdio_write(phy_addr, MII_DIGITAL_CONFIG_REG, config);
++ /* Read back to verify */
++ config = mdio_read(phy_addr, MII_DIGITAL_CONFIG_REG);
++
++ break;
++ }
++ else
++ {
++ /* If no link, go to next phy. */
++ act_phy >>= 1;
++ phy_addr++;
++ }
++ }
++ }
++ return link_state;
++}
++
++/*
++ * The kernel calls this function when someone wants to use the device,
++ * typically 'ifconfig ethX up'.
++ */
++static int emac_open (void)
++{
++ volatile unsigned int *addr;
++ unsigned int clkdiv, cnt;
++ volatile emac_desc *rx_desc;
++
++ debug_emac("+ emac_open\n");
++
++ /* Reset EMAC module and disable interrupts in wrapper */
++ adap_emac->SOFTRESET = 1;
++ while (adap_emac->SOFTRESET != 0);
++ /* after soft reset of wrapper blocks, all Interrupt enables are off
++ * off by default */
++ adap_ewrap->SOFTRST = 1;
++ while (adap_ewrap->SOFTRST != 0);
++
++ #if 0
++ /* check why this is required */
++ for (cnt=0; cnt < 5; cnt++) {
++ clkdiv = adap_ewrap->INTCTRL;
++ }
++ #endif
++
++ rx_desc = emac_rx_desc;
++
++ adap_emac->TXCONTROL = 0x1;
++ adap_emac->RXCONTROL = 0x1;
++
++ /* Init multicast Hash to 0 (disable any multicast receive) */
++ adap_emac->MACHASH1 = 0;
++ adap_emac->MACHASH2 = 0;
++
++ /* Set MAC Address ,Using channel 0 only - other channels are disabled */
++ adap_emac->MACINDEX = 0;
++ adap_emac->MACADDRHI = (emac_mac_addr[3] << 24) | (emac_mac_addr[2] << 16) |
++ (emac_mac_addr[1] << 8) | (emac_mac_addr[0]);
++ /* wew are using CFIG3, set control bits before writing MACADDR_LO */
++ adap_emac->MACADDRLO = ((emac_mac_addr[5] << 8) | emac_mac_addr[4] | (0<<16)|(1<<19) |(1<<20));
++
++ #if 0
++ /* Set source MAC address - REQUIRED */
++ adap_emac->MACSRCADDRHI = (emac_mac_addr[3] << 24) | (emac_mac_addr[2] << 16) |
++ (emac_mac_addr[1] << 8) | (emac_mac_addr[0]);
++ adap_emac->MACSRCADDRLO = ((emac_mac_addr[4] << 8) | emac_mac_addr[5]);
++ #endif
++
++ /* Set DMA 8 TX / 8 RX Head pointers to 0 */
++ addr = &adap_emac->TX0HDP;
++ for( cnt=0; cnt<16; cnt++ )
++ *addr++ = 0;
++ addr = &adap_emac->RX0HDP;
++ for( cnt=0; cnt<16; cnt++ )
++ *addr++ = 0;
++
++ /* Clear Statistics (do this before setting MacControl register) */
++ addr = &adap_emac->RXGOODFRAMES;
++ for( cnt=0; cnt < EMAC_NUM_STATS; cnt++ )
++ *addr++ = 0;
++
++ /* No multicast addressing */
++ adap_emac->MACHASH1 = 0 ;
++ adap_emac->MACHASH2 = 0 ;
++
++ /* Create RX queue and set receive process in place */
++ emac_rx_active_head = emac_rx_desc;
++ for (cnt=0; cnt < EMAC_MAX_RX_BUFFERS; cnt++)
++ {
++ rx_desc->next = (unsigned int) (rx_desc + 1);
++ rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
++ rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
++ rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
++ ++rx_desc;
++ }
++
++ /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */
++ --rx_desc;
++ rx_desc->next = 0;
++ emac_rx_active_tail = rx_desc;
++ emac_rx_queue_active = 1;
++
++ /* Enable TX/RX */
++ adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE;
++ adap_emac->RXBUFFEROFFSET = 0;
++
++ /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */
++ adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN ;
++
++ /* Enable ch 0 only */
++ adap_emac->RXUNICASTSET = 0x1;
++
++ /* Enable MII interface and Full duplex mode */
++ /* This is the only register used in the code, which has changed in
++ Davinci-HD. That change (only a bit) might not affect the working here at
++ the bootloader level. If something is not working as expected, then look
++ here first. - Suresh */
++ adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE);
++
++ /* Init MDIO & get link state */
++ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
++ adap_mdio->CONTROL = ((clkdiv & 0xFF) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT);
++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK);
++
++ /* Start receive process */
++ adap_emac->RX0HDP = (unsigned int) emac_rx_desc;
++
++ debug_emac("- emac_open\n");
++
++ return (1);
++}
++
++/* EMAC Channel Teardown */
++void emac_ch_teardown(int ch)
++{
++ volatile unsigned int dly = 0xFF;
++ volatile unsigned int cnt;
++
++ debug_emac("+ emac_ch_teardown\n");
++
++ if (ch == EMAC_CH_TX)
++ {
++ /* Init TX channel teardown */
++ adap_emac->TXTEARDOWN = 1;
++ for( cnt = 0; cnt != 0xFFFFFFFC; cnt = adap_emac->TX0CP){
++ /* Wait here for Tx teardown completion interrupt to occur
++ * Note: A task delay can be called here to pend rather than
++ * occupying CPU cycles - anyway it has been found that teardown
++ * takes very few cpu cycles and does not affect functionality */
++ --dly;
++ udelay(1);
++ if (dly == 0) break;
++ }
++ adap_emac->TX0CP = cnt;
++ adap_emac->TX0HDP = 0;
++ }
++ else
++ {
++ /* Init RX channel teardown */
++ adap_emac->RXTEARDOWN = 1;
++ for( cnt = 0; cnt != 0xFFFFFFFC; cnt = adap_emac->RX0CP){
++ /* Wait here for Tx teardown completion interrupt to occur
++ * Note: A task delay can be called here to pend rather than
++ * occupying CPU cycles - anyway it has been found that teardown
++ * takes very few cpu cycles and does not affect functionality */
++ --dly;
++ udelay(1);
++ if (dly == 0) break;
++ }
++ adap_emac->RX0CP = cnt;
++ adap_emac->RX0HDP = 0;
++ }
++
++ debug_emac("- emac_ch_teardown\n");
++}
++
++/*
++ * This is called by the kernel in response to 'ifconfig ethX down'. It
++ * is responsible for cleaning up everything that the open routine
++ * does, and maybe putting the card into a powerdown state.
++ */
++static int emac_close (void)
++{
++ debug_emac("+ emac_close\n");
++
++ emac_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
++ emac_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
++
++ /* Reset EMAC module and disable interrupts in wrapper */
++ adap_emac->SOFTRESET = 1;
++ /* HD change, put wrapper in reset */
++ adap_ewrap->SOFTRST = 1;
++
++ debug_emac("- emac_close\n");
++ return (1);
++}
++
++static int tx_send_loop = 0;
++
++/*
++ * This function sends a single packet on the network and returns
++ * positive number (number of bytes transmitted) or negative for error
++ */
++static int emac_send_packet (volatile void *packet, int length)
++{
++ int ret_status = -1;
++ tx_send_loop = 0;
++
++ /* Return error if no link */
++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK);
++ if (emac_link_status == 0)
++ {
++ printf("WARN: emac_send_packet: No link\n");
++ return (ret_status);
++ }
++
++ /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
++ if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
++ {
++ length = EMAC_MIN_ETHERNET_PKT_SIZE;
++ }
++
++ /* Populate the TX descriptor */
++ emac_tx_desc->next = 0;
++ emac_tx_desc->buffer = (unsigned char *)packet;
++ emac_tx_desc->buff_off_len = (length & 0xFFFF);
++ emac_tx_desc->pkt_flag_len = ((length & 0xFFFF) |
++ EMAC_CPPI_SOP_BIT |
++ EMAC_CPPI_OWNERSHIP_BIT |
++ EMAC_CPPI_EOP_BIT);
++ /* Send the packet */
++ adap_emac->TX0HDP = (unsigned int) emac_tx_desc;
++
++ /* Wait for packet to complete or link down */
++ while (1)
++ {
++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK);
++ if (emac_link_status == 0)
++ {
++ emac_ch_teardown(EMAC_CH_TX);
++ return (ret_status);
++ }
++ if (adap_emac->TXINTSTATRAW & 0x1)
++ {
++ ret_status = length;
++ break;
++ }
++ ++tx_send_loop;
++ }
++
++ return (ret_status);
++
++}
++
++/*
++ * This function handles receipt of a packet from the network
++ */
++static int emac_rcv_packet (void)
++{
++ volatile emac_desc *rx_curr_desc;
++ volatile emac_desc *curr_desc;
++ volatile emac_desc *tail_desc;
++ unsigned int status, ret= -1;
++
++ rx_curr_desc = emac_rx_active_head;
++ status = rx_curr_desc->pkt_flag_len;
++ if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0))
++ {
++ if (status & EMAC_CPPI_RX_ERROR_FRAME) {
++ /* Error in packet - discard it and requeue desc */
++ printf("WARN: emac_rcv_pkt: Error in packet\n");
++ }
++ else {
++ NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xFFFF));
++ ret = rx_curr_desc->buff_off_len & 0xFFFF;
++ }
++
++ /* Ack received packet descriptor */
++ adap_emac->RX0CP = (unsigned int) rx_curr_desc;
++ curr_desc = rx_curr_desc;
++ emac_rx_active_head = rx_curr_desc->next;
++
++ if (status & EMAC_CPPI_EOQ_BIT) {
++ if (emac_rx_active_head) {
++ adap_emac->RX0HDP = (unsigned int) emac_rx_active_head;
++ } else {
++ emac_rx_queue_active = 0;
++ printf("INFO:emac_rcv_packet: RX Queue not active\n");
++ }
++ }
++
++ /* Recycle RX descriptor */
++ rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
++ rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
++ rx_curr_desc->next = 0;
++
++ if (emac_rx_active_head == 0) {
++ printf("INFO: emac_rcv_pkt: active queue head = 0\n");
++ emac_rx_active_head = curr_desc;
++ emac_rx_active_tail = curr_desc;
++ if (emac_rx_queue_active != 0) {
++ adap_emac->RX0HDP = (unsigned int) emac_rx_active_head;
++ printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
++ emac_rx_queue_active = 1;
++ }
++ } else {
++
++ tail_desc = emac_rx_active_tail;
++ emac_rx_active_tail = curr_desc;
++ tail_desc->next = curr_desc;
++ status = tail_desc->pkt_flag_len;
++ if (status & EMAC_CPPI_EOQ_BIT) {
++ adap_emac->RX0HDP = (unsigned int) curr_desc;
++ status &= ~EMAC_CPPI_EOQ_BIT;
++ tail_desc->pkt_flag_len = status;
++ }
++ }
++ return ret;
++ }
++ return (0);
++}
++
++#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
++
++#endif /* CONFIG_DRIVER_TI_EMAC */
+diff -Nurd u-boot-1.2.0/board/dm700/dm646x_emac.h u-boot-1.2.0-leopard/board/dm700/dm646x_emac.h
+--- u-boot-1.2.0/board/dm700/dm646x_emac.h 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm700/dm646x_emac.h 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,321 @@
++/*
++ * dm644x_emac.h
++ *
++ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
++ *
++ * Copyright (C) 2005 Texas Instruments.
++ *
++ * ----------------------------------------------------------------------------
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ * ----------------------------------------------------------------------------
++
++ * Modifications:
++ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
++ *
++ */
++
++#ifndef _DM644X_EMAC_H_
++#define _DM644X_EMAC_H_
++
++/***********************************************
++ ********** Configurable items *****************
++ ***********************************************/
++
++/* Addresses of EMAC module in DaVinci */
++#define EMAC_BASE_ADDR (0x01C80000)
++#define EMAC_WRAPPER_BASE_ADDR (0x01C81000)
++#define EMAC_WRAPPER_RAM_ADDR (0x01C82000)
++#define EMAC_MDIO_BASE_ADDR (0x01C84000)
++
++/* MDIO module input frequency */
++#define EMAC_MDIO_BUS_FREQ 76500000 /* PLL/6 - 76.5 MHz */
++/* MDIO clock output frequency */
++#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
++
++/* PHY mask - set only those phy number bits where phy is/can be connected */
++#define EMAC_MDIO_PHY_MASK 0xFFFFFFFF
++
++/* Ethernet Min/Max packet size */
++#define EMAC_MIN_ETHERNET_PKT_SIZE 60
++#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
++#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
++
++/* Number of RX packet buffers
++ * NOTE: Only 1 buffer supported as of now
++ */
++#define EMAC_MAX_RX_BUFFERS 10
++
++/***********************************************
++ ******** Internally used macros ***************
++ ***********************************************/
++
++#define EMAC_CH_TX 1
++#define EMAC_CH_RX 0
++
++/* Each descriptor occupies 4, lets start RX desc's at 0 and
++ * reserve space for 64 descriptors max
++ */
++#define EMAC_RX_DESC_BASE 0x0
++#define EMAC_TX_DESC_BASE 0x1000
++
++/* EMAC Teardown value */
++#define EMAC_TEARDOWN_VALUE 0xFFFFFFFC
++
++/* MII Status Register */
++#define MII_STATUS_REG 1
++
++/* Intel LXT971 Digtal Config Register */
++#define MII_DIGITAL_CONFIG_REG 26
++
++/* Number of statistics registers */
++#define EMAC_NUM_STATS 36
++
++/* EMAC Descriptor */
++typedef volatile struct _emac_desc
++{
++ unsigned int next; /* Pointer to next descriptor in chain */
++ unsigned char *buffer; /* Pointer to data buffer */
++ unsigned int buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
++ unsigned int pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
++} emac_desc;
++
++/* CPPI bit positions */
++#define EMAC_CPPI_SOP_BIT (0x80000000) /*(1 << 31)*/
++#define EMAC_CPPI_EOP_BIT (0x40000000) /*(1 << 30*/
++#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) /*(1 << 29)*/
++#define EMAC_CPPI_EOQ_BIT (0x10000000) /*(1 << 28)*/
++#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) /*(1 << 27)*/
++#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) /*(1 << 26)*/
++
++#define EMAC_CPPI_RX_ERROR_FRAME (0x03FC0000)
++
++#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
++#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
++
++#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
++#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
++
++
++#define MDIO_CONTROL_ENABLE (0x40000000)
++#define MDIO_CONTROL_FAULT (0x80000)
++#define MDIO_USERACCESS0_GO (0x80000000)
++#define MDIO_USERACCESS0_WRITE_READ (0x0)
++#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
++
++
++
++/* EMAC Register overlay */
++
++/* Ethernet MAC control register overlay structure */
++typedef volatile struct {
++ unsigned int TXIDVER;
++ unsigned int TXCONTROL;
++ unsigned int TXTEARDOWN;
++ unsigned char RSVD0[4];
++ unsigned int RXIDVER;
++ unsigned int RXCONTROL;
++ unsigned int RXTEARDOWN;
++ unsigned char RSVD1[100];
++ unsigned int TXINTSTATRAW;
++ unsigned int TXINTSTATMASKED;
++ unsigned int TXINTMASKSET;
++ unsigned int TXINTMASKCLEAR;
++ unsigned int MACINVECTOR;
++ unsigned char RSVD2[12];
++ unsigned int RXINTSTATRAW;
++ unsigned int RXINTSTATMASKED;
++ unsigned int RXINTMASKSET;
++ unsigned int RXINTMASKCLEAR;
++ unsigned int MACINTSTATRAW;
++ unsigned int MACINTSTATMASKED;
++ unsigned int MACINTMASKSET;
++ unsigned int MACINTMASKCLEAR;
++ unsigned char RSVD3[64];
++ unsigned int RXMBPENABLE;
++ unsigned int RXUNICASTSET;
++ unsigned int RXUNICASTCLEAR;
++ unsigned int RXMAXLEN;
++ unsigned int RXBUFFEROFFSET;
++ unsigned int RXFILTERLOWTHRESH;
++ unsigned char RSVD4[8];
++ unsigned int RX0FLOWTHRESH;
++ unsigned int RX1FLOWTHRESH;
++ unsigned int RX2FLOWTHRESH;
++ unsigned int RX3FLOWTHRESH;
++ unsigned int RX4FLOWTHRESH;
++ unsigned int RX5FLOWTHRESH;
++ unsigned int RX6FLOWTHRESH;
++ unsigned int RX7FLOWTHRESH;
++ unsigned int RX0FREEBUFFER;
++ unsigned int RX1FREEBUFFER;
++ unsigned int RX2FREEBUFFER;
++ unsigned int RX3FREEBUFFER;
++ unsigned int RX4FREEBUFFER;
++ unsigned int RX5FREEBUFFER;
++ unsigned int RX6FREEBUFFER;
++ unsigned int RX7FREEBUFFER;
++ unsigned int MACCONTROL;
++ unsigned int MACSTATUS;
++ unsigned int EMCONTROL;
++ unsigned int FIFOCONTROL;
++ unsigned int MACCONFIG;
++ unsigned int SOFTRESET;
++ unsigned char RSVD5[88];
++ unsigned int MACSRCADDRLO;
++ unsigned int MACSRCADDRHI;
++ unsigned int MACHASH1;
++ unsigned int MACHASH2;
++ unsigned int BOFFTEST;
++ unsigned int TPACETEST;
++ unsigned int RXPAUSE;
++ unsigned int TXPAUSE;
++ unsigned char RSVD6[16];
++ unsigned int RXGOODFRAMES; /* EMAC Statistics Registers - Start */
++ unsigned int RXBCASTFRAMES;
++ unsigned int RXMCASTFRAMES;
++ unsigned int RXPAUSEFRAMES;
++ unsigned int RXCRCERRORS;
++ unsigned int RXALIGNCODEERRORS;
++ unsigned int RXOVERSIZED;
++ unsigned int RXJABBER;
++ unsigned int RXUNDERSIZED;
++ unsigned int RXFRAGMENTS;
++ unsigned int RXFILTERED;
++ unsigned int RXQOSFILTERED;
++ unsigned int RXOCTETS;
++ unsigned int TXGOODFRAMES;
++ unsigned int TXBCASTFRAMES;
++ unsigned int TXMCASTFRAMES;
++ unsigned int TXPAUSEFRAMES;
++ unsigned int TXDEFERRED;
++ unsigned int TXCOLLISION;
++ unsigned int TXSINGLECOLL;
++ unsigned int TXMULTICOLL;
++ unsigned int TXEXCESSIVECOLL;
++ unsigned int TXLATECOLL;
++ unsigned int TXUNDERRUN;
++ unsigned int TXCARRIERSENSE;
++ unsigned int TXOCTETS;
++ unsigned int FRAME64;
++ unsigned int FRAME65T127;
++ unsigned int FRAME128T255;
++ unsigned int FRAME256T511;
++ unsigned int FRAME512T1023;
++ unsigned int FRAME1024TUP;
++ unsigned int NETOCTETS;
++ unsigned int RXSOFOVERRUNS;
++ unsigned int RXMOFOVERRUNS;
++ unsigned int RXDMAOVERRUNS; /* EMAC Statistics register - End */
++ unsigned char RSVD7[624];
++ unsigned int MACADDRLO;
++ unsigned int MACADDRHI;
++ unsigned int MACINDEX;
++ unsigned char RSVD8[244];
++ unsigned int TX0HDP;
++ unsigned int TX1HDP;
++ unsigned int TX2HDP;
++ unsigned int TX3HDP;
++ unsigned int TX4HDP;
++ unsigned int TX5HDP;
++ unsigned int TX6HDP;
++ unsigned int TX7HDP;
++ unsigned int RX0HDP;
++ unsigned int RX1HDP;
++ unsigned int RX2HDP;
++ unsigned int RX3HDP;
++ unsigned int RX4HDP;
++ unsigned int RX5HDP;
++ unsigned int RX6HDP;
++ unsigned int RX7HDP;
++ unsigned int TX0CP;
++ unsigned int TX1CP;
++ unsigned int TX2CP;
++ unsigned int TX3CP;
++ unsigned int TX4CP;
++ unsigned int TX5CP;
++ unsigned int TX6CP;
++ unsigned int TX7CP;
++ unsigned int RX0CP;
++ unsigned int RX1CP;
++ unsigned int RX2CP;
++ unsigned int RX3CP;
++ unsigned int RX4CP;
++ unsigned int RX5CP;
++ unsigned int RX6CP;
++ unsigned int RX7CP;
++} emac_regs;
++
++/* EMAC Wrapper (control module) Register Overlay */
++typedef volatile struct {
++ volatile unsigned int IDVER;
++ volatile unsigned int SOFTRST;
++ volatile unsigned int EMCTRL;
++ volatile unsigned int INTCTRL;
++ volatile unsigned int C0_RXTHRESHEN;
++ volatile unsigned int C0_RXINTEN;
++ volatile unsigned int C0_TXINTEN;
++ volatile unsigned int C0_MISCEN;
++ volatile unsigned int C1_RXTHRESHEN;
++ volatile unsigned int C1_RXINTEN;
++ volatile unsigned int C1_TXINTEN;
++ volatile unsigned int C1_MISCEN;
++ volatile unsigned int C2_RXTHRESHEN;
++ volatile unsigned int C2_RXINTEN;
++ volatile unsigned int C2_TXINTEN;
++ volatile unsigned int C2_MISCEN;
++ volatile unsigned int C0_RXTHRESHSTAT;
++ volatile unsigned int C0_RXINTSTAT;
++ volatile unsigned int C0_TXINTSTAT;
++ volatile unsigned int C0_MISCSTAT;
++ volatile unsigned int C1_RXTHRESHSTAT;
++ volatile unsigned int C1_RXINTSTAT;
++ volatile unsigned int C1_TXINTSTAT;
++ volatile unsigned int C1_MISCSTAT;
++ volatile unsigned int C2_RXTHRESHSTAT;
++ volatile unsigned int C2_RXINTSTAT;
++ volatile unsigned int C2_TXINTSTAT;
++ volatile unsigned int C2_MISCSTAT;
++ volatile unsigned int C0_RXIMAX;
++ volatile unsigned int C0_TXIMAX;
++ volatile unsigned int C1_RXIMAX;
++ volatile unsigned int C1_TXIMAX;
++ volatile unsigned int C2_RXIMAX;
++ volatile unsigned int C2_TXIMAX;
++} ewrap_regs;
++
++
++/* EMAC MDIO Register Overlay */
++typedef volatile struct {
++ volatile unsigned int VERSION;
++ volatile unsigned int CONTROL;
++ volatile unsigned int ALIVE;
++ volatile unsigned int LINK;
++ volatile unsigned int LINKINTRAW;
++ volatile unsigned int LINKINTMASKED;
++ volatile unsigned char RSVD0[8];
++ volatile unsigned int USERINTRAW;
++ volatile unsigned int USERINTMASKED;
++ volatile unsigned int USERINTMASKSET;
++ volatile unsigned int USERINTMASKCLEAR;
++ volatile unsigned char RSVD1[80];
++ volatile unsigned int USERACCESS0;
++ volatile unsigned int USERPHYSEL0;
++ volatile unsigned int USERACCESS1;
++ volatile unsigned int USERPHYSEL1;
++} mdio_regs;
++
++
++#endif /* _DM644X_EMAC_H_ */
+diff -Nurd u-boot-1.2.0/board/dm700/flash.c u-boot-1.2.0-leopard/board/dm700/flash.c
+--- u-boot-1.2.0/board/dm700/flash.c 1969-12-31 21:00:00.000000000 -0300
++++ u-boot-1.2.0-leopard/board/dm700/flash.c 2007-12-04 07:50:28.000000000 -0300
+@@ -0,0 +1,686 @@
++/*
++ * (C) Copyright 2003
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * (C) Copyright 2003
++ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include "types.h"
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++#if defined (CFG_DAVINCI_HD)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++ #define SWAP(x) __swab16(x)
++#endif
++
++#if defined (CONFIG_TOP860)
++ typedef unsigned short FLASH_PORT_WIDTH;
++ typedef volatile unsigned short FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0e
++ #define FLASH_ID4 0x0F
++#endif
++
++#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0aaa
++ #define FLASH_CYCLE2 0x0555
++ #define FLASH_ID1 0
++ #define FLASH_ID2 2
++ #define FLASH_ID3 0x1c
++ #define FLASH_ID4 0x1E
++#endif
++
++#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
++ typedef unsigned char FLASH_PORT_WIDTH;
++ typedef volatile unsigned char FLASH_PORT_WIDTHV;
++ #define FLASH_ID_MASK 0xFF
++
++ #define FPW FLASH_PORT_WIDTH
++ #define FPWV FLASH_PORT_WIDTHV
++
++ #define FLASH_CYCLE1 0x0555
++ #define FLASH_CYCLE2 0x02aa
++ #define FLASH_ID1 0
++ #define FLASH_ID2 1
++ #define FLASH_ID3 0x0E
++ #define FLASH_ID4 0x0F
++#endif
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size(FPWV *addr, flash_info_t *info);
++static void flash_reset(flash_info_t *info);
++static int write_word(flash_info_t *info, FPWV *dest, FPW data);
++static flash_info_t *flash_get_info(ulong base);
++void inline spin_wheel (void);
++
++/*-----------------------------------------------------------------------
++ * flash_init()
++ *
++ * sets up flash_info and returns size of FLASH (bytes)
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size = 0;
++ int i = 0;
++ extern void flash_preinit(void);
++ extern void flash_afterinit(uint, ulong, ulong);
++ ulong flashbase = CFG_FLASH_BASE;
++
++ /*flash_preinit();*/
++
++ /* There is only ONE FLASH device */
++ memset(&flash_info[i], 0, sizeof(flash_info_t));
++ flash_info[i].size =
++ flash_get_size((FPW *)flashbase, &flash_info[i]);
++ size += flash_info[i].size;
++
++#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
++ /* monitor protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_MONITOR_BASE,
++ CFG_MONITOR_BASE+monitor_flash_len-1,
++ flash_get_info(CFG_MONITOR_BASE));
++#endif
++
++#ifdef CFG_ENV_IS_IN_FLASH
++ /* ENV protection ON by default */
++ flash_protect(FLAG_PROTECT_SET,
++ CFG_ENV_ADDR,
++ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
++ flash_get_info(CFG_ENV_ADDR));
++#endif
++
++
++ /*flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);*/
++ return size ? size : 1;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_reset(flash_info_t *info)
++{
++ FPWV *base = (FPWV *)(info->start[0]);
++
++ /* Put FLASH back in read mode */
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *base = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++
++void flash_reset_sector(flash_info_t *info, ULONG addr)
++{
++ // Reset Flash to be in Read Array Mode
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
++ *(FPWV *)addr = (FPW)0x00FF00FF; /* Intel Read Mode */
++ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
++ *(FPWV *)addr = (FPW)0x00F000F0; /* AMD Read Mode */
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++static flash_info_t *flash_get_info(ulong base)
++{
++ int i;
++ flash_info_t * info;
++
++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
++ info = & flash_info[i];
++ if (info->size &&
++ info->start[0] <= base && base <= info->start[0] + info->size - 1)
++ break;
++ }
++
++ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++ uchar *boottype;
++ uchar *bootletter;
++ uchar *fmt;
++ uchar botbootletter[] = "B";
++ uchar topbootletter[] = "T";
++ uchar botboottype[] = "bottom boot sector";
++ uchar topboottype[] = "top boot sector";
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_AMD: printf ("MY AMD "); break;
++#if 0
++ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
++ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
++ case FLASH_MAN_SST: printf ("SST "); break;
++ case FLASH_MAN_STM: printf ("STM "); break;
++#endif
++ case FLASH_MAN_INTEL: printf ("INTEL "); break;
++ default: printf ("Unknown Vendor "); break;
++ }
++
++ /* check for top or bottom boot, if it applies */
++ if (info->flash_id & FLASH_BTYPE) {
++ boottype = botboottype;
++ bootletter = botbootletter;
++ }
++ else {
++ boottype = topboottype;
++ bootletter = topbootletter;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_AM160T:
++ case FLASH_AM160B:
++ fmt = "29LV160%s (16 Mbit, %s)\n";
++ break;
++ case FLASH_AMLV640U:
++ fmt = "29LV640M (64 Mbit)\n";
++ break;
++ case FLASH_AMDLV065D:
++ fmt = "29LV065D (64 Mbit)\n";
++ break;
++ case FLASH_AMLV256U:
++ fmt = "29LV256M (256 Mbit)\n";
++ break;
++ case FLASH_28F128P30T:
++ fmt = "28F128P30T\n";
++ break;
++ default:
++ fmt = "Unknown Chip Type\n";
++ break;
++ }
++
++ printf (fmt, bootletter, boottype);
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20,
++ info->sector_count);
++
++ printf (" Sector Start Addresses:");
++
++ for (i=0; i<info->sector_count; ++i) {
++ ulong size;
++ int erased;
++ ulong *flash = (unsigned long *) info->start[i];
++
++ if ((i % 5) == 0) {
++ printf ("\n ");
++ }
++
++ /*
++ * Check if whole sector is erased
++ */
++ size =
++ (i != (info->sector_count - 1)) ?
++ (info->start[i + 1] - info->start[i]) >> 2 :
++ (info->start[0] + info->size - info->start[i]) >> 2;
++
++ for (
++ flash = (unsigned long *) info->start[i], erased = 1;
++ (flash != (unsigned long *) info->start[i] + size) && erased;
++ flash++
++ )
++ erased = *flash == ~0x0UL;
++
++ printf (" %08lX %s %s",
++ info->start[i],
++ erased ? "E": " ",
++ info->protect[i] ? "(RO)" : " ");
++ }
++
++ printf ("\n");
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++
++ulong flash_get_size (FPWV *addr, flash_info_t *info)
++{
++ int i;
++
++ /* Write auto select command: read Manufacturer ID */
++ /* Write auto select command sequence and test FLASH answer */
++ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
++ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
++
++ /* The manufacturer codes are only 1 byte, so just use 1 byte.
++ * This works for any bus width and any FLASH device width.
++ */
++ udelay(100);
++ switch (addr[FLASH_ID1] & 0xff) {
++
++ case (uchar)AMD_MANUFACT:
++ printf ("MY AMD ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_AMD;
++ break;
++
++ case (uchar)INTEL_MANUFACT:
++ printf ("INTEL ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++ printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++ break;
++ }
++
++ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
++ if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
++
++ case (FPW)AMD_ID_LV160B:
++ info->flash_id += FLASH_AM160B;
++ info->sector_count = 35;
++ info->size = 0x00200000;
++ info->start[0] = (ulong)addr;
++ info->start[1] = (ulong)addr + 0x4000;
++ info->start[2] = (ulong)addr + 0x6000;
++ info->start[3] = (ulong)addr + 0x8000;
++ for (i = 4; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * (i-3);
++ }
++ break;
++
++ case (FPW)AMD_ID_LV065D:
++ info->flash_id += FLASH_AMDLV065D;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++
++ case (FPW)AMD_ID_MIRROR:
++ /* MIRROR BIT FLASH, read more ID bytes */
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
++ {
++ info->flash_id += FLASH_AMLV640U;
++ info->sector_count = 128;
++ info->size = 0x00800000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
++ (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
++ {
++ /* attention: only the first 16 MB will be used in u-boot */
++ info->flash_id += FLASH_AMLV256U;
++ info->sector_count = 256;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ info->start[i] = (ulong)addr + 0x10000 * i;
++ }
++ break;
++ }
++ case (FPW)INTEL_ID_28F128P30T:
++ /* Intel StrataFlash 28F128P30T */
++ info->flash_id += FLASH_28F128P30T;
++ info->sector_count = 131;
++ info->size = 0x01000000;
++ for (i = 0; i < info->sector_count; i++)
++ {
++ if (i < 127)
++ info->start[i] = (ulong)addr + 0x20000 * i;
++ else
++ info->start[i] = (ulong)addr + 0xfe0000 + 0x8000 * (i-127);
++ }
++ break;
++
++ /* fall thru to here ! */
++ default:
++ printf ("unknown AMD device=%x %x %x",
++ (FPW)addr[FLASH_ID2],
++ (FPW)addr[FLASH_ID3],
++ (FPW)addr[FLASH_ID4]);
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0x800000;
++ break;
++ }
++
++ /* Put FLASH back in read mode */
++ flash_reset(info);
++
++ return (info->size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ FPWV *addr;
++ int flag, prot, sect;
++ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
++ ulong start, now, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf (