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authorKoen Kooi <koen@openembedded.org>2007-09-04 12:07:11 +0000
committerKoen Kooi <koen@openembedded.org>2007-09-04 12:07:11 +0000
commit1c24210e3f0b3f6a5a5783ed597252d453e6bd64 (patch)
tree92a51cdf31cca39b866e3f818a799fa4fd6b570e
parentadc0e34177df635be3bec485a184e5573f13383e (diff)
parentb144d7d083863cb10a7d9219ddcede338f6e839a (diff)
downloadopenembedded-1c24210e3f0b3f6a5a5783ed597252d453e6bd64.tar.gz
openembedded-1c24210e3f0b3f6a5a5783ed597252d453e6bd64.tar.bz2
openembedded-1c24210e3f0b3f6a5a5783ed597252d453e6bd64.zip
propagate from branch 'org.openembedded.dev' (head 3fed235384e32b1c9ba26c86ff39b2ffb928fbed)
to branch 'org.openembedded.dev.avr32' (head 50c56d6b5b2d15f6bc9c32b4f9907bc0d1c3564b)
-rw-r--r--conf/machine/at32stk1000.conf4
-rw-r--r--conf/machine/atngw100.conf5
-rw-r--r--packages/binutils/binutils-2.17/503-avr32-fix-got-offset-init.patch12
-rw-r--r--packages/binutils/binutils_2.17.bb3
-rw-r--r--packages/busybox/busybox-1.2.1/install-should-unlink-dest-if-it-exists.patch53
-rw-r--r--packages/busybox/busybox_1.2.1.bb4
-rw-r--r--packages/busybox/files/install-should-unlink-dest-if-it-exists.patch53
-rw-r--r--packages/gcc/avr32-gcc-cross_4.1.2.bb22
-rw-r--r--packages/gcc/avr32-gcc_4.1.2.bb22
-rw-r--r--packages/libmad/files/.mtn2git_empty0
-rw-r--r--packages/libmad/files/libmad-0.15.1b-avr32-optimization.patch2922
-rw-r--r--packages/libmad/libmad_0.15.1b.bb4
-rw-r--r--packages/linux/linux-2.6.18/.mtn2git_empty0
-rwxr-xr-xpackages/linux/linux-2.6.18/0001-AVR32-Fix-compile-error-with-gcc-4.1.patch71
-rw-r--r--packages/linux/linux-2.6.18/add-all-parameters-to-smc-driver.patch73
-rw-r--r--packages/linux/linux-2.6.18/add-default-atngw-defconfig.patch975
-rw-r--r--packages/linux/linux-2.6.18/add-flush_buffer-operation-to-uart_ops.patch71
-rw-r--r--packages/linux/linux-2.6.18/add-hmatrix-support.patch414
-rw-r--r--packages/linux/linux-2.6.18/add-ide-header.patch41
-rw-r--r--packages/linux/linux-2.6.18/add-intc_pending_irq-to-intc.patch10
-rw-r--r--packages/linux/linux-2.6.18/add-mach-specific-kconfig.patch30
-rw-r--r--packages/linux/linux-2.6.18/at32-dac-oss-driver-clk-fix.patch175
-rw-r--r--packages/linux/linux-2.6.18/at32-dac-oss-driver.patch819
-rw-r--r--packages/linux/linux-2.6.18/at32ap7000-dmac-driver.patch855
-rw-r--r--packages/linux/linux-2.6.18/at32ap7000-platform_device-definitions.patch445
-rw-r--r--packages/linux/linux-2.6.18/at32stk1000/.mtn2git_empty0
-rw-r--r--packages/linux/linux-2.6.18/at32stk1000/defconfig990
-rw-r--r--packages/linux/linux-2.6.18/at73c213-alsa-driver.patch1485
-rw-r--r--packages/linux/linux-2.6.18/atmel-ac97c-alsa-driver.patch1383
-rw-r--r--packages/linux/linux-2.6.18/atmel-husb2-udc-driver.patch2488
-rw-r--r--packages/linux/linux-2.6.18/atmel-lcdc-framebuffer-driver.patch1192
-rw-r--r--packages/linux/linux-2.6.18/atmel-macb-ethernet-driver.patch1614
-rw-r--r--packages/linux/linux-2.6.18/atmel-mci-debugfs.patch278
-rw-r--r--packages/linux/linux-2.6.18/atmel-mci-init-nr_blocks-in-dma-request.patch47
-rw-r--r--packages/linux/linux-2.6.18/atmel-mmc-host-driver.patch986
-rw-r--r--packages/linux/linux-2.6.18/atmel-spi-master-driver.patch990
-rw-r--r--packages/linux/linux-2.6.18/atmel-twi-driver.patch521
-rw-r--r--packages/linux/linux-2.6.18/atmel-usart3-driver.patch1443
-rw-r--r--packages/linux/linux-2.6.18/atmel-version.patch17
-rw-r--r--packages/linux/linux-2.6.18/atmel_spi-handle-rx-overrun.patch200
-rw-r--r--packages/linux/linux-2.6.18/atmel_spi-send-zeroes-when-tx_buf-is-not-set.patch48
-rw-r--r--packages/linux/linux-2.6.18/atngw100/.mtn2git_empty0
-rw-r--r--packages/linux/linux-2.6.18/atngw100/defconfig970
-rw-r--r--packages/linux/linux-2.6.18/atstk1000-add-platform-data-for-mmc.patch25
-rw-r--r--packages/linux/linux-2.6.18/atstk1000-board-fix-fbmem-setup.patch14
-rw-r--r--packages/linux/linux-2.6.18/atstk1000-instantiate-devices.patch103
-rw-r--r--packages/linux/linux-2.6.18/avr32-arch-neutral-gpio-api.patch598
-rw-r--r--packages/linux/linux-2.6.18/avr32-arch.patch19628
-rw-r--r--packages/linux/linux-2.6.18/avr32-checkstack.patch35
-rw-r--r--packages/linux/linux-2.6.18/avr32-dma-controller-framework.patch241
-rw-r--r--packages/linux/linux-2.6.18/avr32-dont-include-asm-delay-h.patch47
-rw-r--r--packages/linux/linux-2.6.18/avr32-drop-GFP_COMP-for-DMA-memory-allocations.patch27
-rw-r--r--packages/linux/linux-2.6.18/avr32-fix-oprofile-interrupts.patch109
-rw-r--r--packages/linux/linux-2.6.18/avr32-gpio-dev.patch548
-rw-r--r--packages/linux/linux-2.6.18/avr32-increment-pointer-when-parsing-for-fbmem_start.patch16
-rw-r--r--packages/linux/linux-2.6.18/avr32-little-endian-read-write-bwl.patch128
-rw-r--r--packages/linux/linux-2.6.18/avr32-move-ethernet-tag-parsing-to-board-specific-code.patch94
-rw-r--r--packages/linux/linux-2.6.18/avr32-network-gateway-support.patch233
-rw-r--r--packages/linux/linux-2.6.18/avr32-oprofile.patch610
-rw-r--r--packages/linux/linux-2.6.18/avr32-sound.patch51
-rw-r--r--packages/linux/linux-2.6.18/avr32-time-add-shared-interrupts.patch30
-rw-r--r--packages/linux/linux-2.6.18/avr32-unistd-h-move-ifdef-kernel.patch39
-rw-r--r--packages/linux/linux-2.6.18/avr32_defconfig1036
-rw-r--r--packages/linux/linux-2.6.18/dmac-add-explicit-blockcount-to-dma_request_sg.patch66
-rw-r--r--packages/linux/linux-2.6.18/dmac-stopping-idle-channel-is-not-fatal.patch93
-rw-r--r--packages/linux/linux-2.6.18/dont-include-map-h-from-physmap-h.patch33
-rw-r--r--packages/linux/linux-2.6.18/fix-alpha-color-bitfield.patch21
-rw-r--r--packages/linux/linux-2.6.18/fix-gpio-prototypes.patch75
-rw-r--r--packages/linux/linux-2.6.18/fix-lcd-display-off-by-two-problem.patch17
-rw-r--r--packages/linux/linux-2.6.18/fix-usart3-rx-BUG.patch25
-rw-r--r--packages/linux/linux-2.6.18/gpio-define-pio-none.patch11
-rw-r--r--packages/linux/linux-2.6.18/gpio-dev-blocking-read.patch187
-rw-r--r--packages/linux/linux-2.6.18/gpio-dev-robustness.patch204
-rw-r--r--packages/linux/linux-2.6.18/husb2_udc-test-mode.patch267
-rw-r--r--packages/linux/linux-2.6.18/jffs2_can_mark_obsolete-should-return-0-for-dataflash.patch37
-rw-r--r--packages/linux/linux-2.6.18/kbuild-add-unifdef.patch1020
-rw-r--r--packages/linux/linux-2.6.18/kbuild-replace-use-of-strlcpy-with-a-dedicated-implmentation-in-unifdef.patch30
-rw-r--r--packages/linux/linux-2.6.18/kbuild-use-in-kernel-unifdef.patch56
-rw-r--r--packages/linux/linux-2.6.18/lcdc-do-not-clear-mem-if-fbmem_start-is-set.patch16
-rw-r--r--packages/linux/linux-2.6.18/lcdc-fix-possible-null-pointer-and-match-guard-time-to-uboot.patch38
-rw-r--r--packages/linux/linux-2.6.18/lcdc-wait-for-vsync.patch152
-rw-r--r--packages/linux/linux-2.6.18/ltv350qv-add-initial_power_state-param.patch25
-rw-r--r--packages/linux/linux-2.6.18/ltv350qv-lcd-driver.patch355
-rw-r--r--packages/linux/linux-2.6.18/mmc-add-bit-manipulating-macros.patch321
-rw-r--r--packages/linux/linux-2.6.18/mmc-add-detect-card-and-wp-support.patch159
-rw-r--r--packages/linux/linux-2.6.18/mmc-add-platform-data.patch185
-rw-r--r--packages/linux/linux-2.6.18/mmc-core-dma-fix.patch33
-rw-r--r--packages/linux/linux-2.6.18/mtd-fix-atmel-pri-for-cmdset-0001-and-cmdset-0002.patch99
-rw-r--r--packages/linux/linux-2.6.18/mtd-unlock-nor-flash-automatically-where-necessary.patch75
-rw-r--r--packages/linux/linux-2.6.18/ngw-fix-usart-initialization.patch32
-rw-r--r--packages/linux/linux-2.6.18/ngw100-change-spi-clock-on-dataflash.patch13
-rw-r--r--packages/linux/linux-2.6.18/pio-deglitch.patch40
-rw-r--r--packages/linux/linux-2.6.18/pio-interrupt-controller.patch108
-rw-r--r--packages/linux/linux-2.6.18/rename-ttyUS-to-ttyS-or-ttyAT.patch74
-rw-r--r--packages/linux/linux-2.6.18/renumber-usart-devices.patch228
-rw-r--r--packages/linux/linux-2.6.18/spi-fix-spi-busnum-to-master-buffer-and-bus_num-0.patch50
-rw-r--r--packages/linux/linux-2.6.18/spi-reduce-dlybs-and-dlybct.patch19
-rw-r--r--packages/linux/linux-2.6.18/spi-set-kset-of-master-class-dev-explicitly.patch34
-rw-r--r--packages/linux/linux-2.6.18/update-atstk1002_defconfig.patch563
-rw-r--r--packages/linux/linux-2.6.18/usart-make-rx-timeout-baudrate-independent.patch83
-rw-r--r--packages/linux/linux-2.6.18/usb-ethernet-align-all-descriptors-on-a-word-boundary.patch171
-rw-r--r--packages/linux/linux-2.6.18/usb-ethernet-define-cdc-capability-for-husb2.patch27
-rw-r--r--packages/linux/linux-2.6.18/usb-file-storage-align-all-descriptors-on-a-word-boundary.patch107
-rw-r--r--packages/linux/linux-2.6.18/usb-serial-align-all-descriptors-on-a-word-boundary.patch140
-rw-r--r--packages/linux/linux-2.6.18/usb-zero-align-all-descriptors-on-a-word-boundary.patch107
-rw-r--r--packages/linux/linux/atngw100/.mtn2git_empty0
-rw-r--r--packages/linux/linux/atngw100/defconfig849
-rw-r--r--packages/linux/linux_2.6.18.bb108
-rw-r--r--packages/mplayer/files/mplayer-1.0rc1-atmel.2.patch6444
-rw-r--r--packages/mplayer/mplayer_0.0+1.0rc1.bb8
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/avr32-arch-2.patch2135
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/avr32-linkrelax-option.patch40
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/avr32-string-ops.patch1139
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/fix-__libc_fcntl64-varargs-prototype.patch24
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/fix-broken-__libc_open-declaration.patch30
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/fix-getrusage-argument-type.patch19
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/ldd-avr32-support.patch25
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/ldso-always-inline-_dl_memcpy.patch24
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/ldso-always-inline-syscalls.patch107
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/ldso-avr32-2.patch526
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/ldso-avr32-needs-CONSTANT_STRING_GOT_FIXUP.patch23
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/ldso-avr32-startup-hack.patch40
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/let-optimized-stringops-override-default-ones.patch28
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/libpthread-avr32.patch105
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/no-create_module-on-avr32.patch27
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/remove-bogus-version-hack-and-just-use-asm-generic-if-it-exists.patch48
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/sync-fcntl-h-with-linux-kernel.patch54
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/uClibc-0.9.28-avr32-20060621.patch4322
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/uClibc-0.9.28-avr32-20061019.patch4080
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/uClibc.config31
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/uclibc-avr32-kernheaders.spec41
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/uclibc-avr32-no-msoft-float.patch14
-rw-r--r--packages/uclibc/uclibc-0.9.28/avr32/uclibc-makefile.patch16
-rw-r--r--packages/uclibc/uclibc.inc15
-rw-r--r--packages/uclibc/uclibc/.mtn2git_empty0
-rw-r--r--packages/uclibc/uclibc_0.9.28.bb30
-rw-r--r--site/avr32-common15
137 files changed, 71073 insertions, 37 deletions
diff --git a/conf/machine/at32stk1000.conf b/conf/machine/at32stk1000.conf
index 2231f80ed2..21ffdda843 100644
--- a/conf/machine/at32stk1000.conf
+++ b/conf/machine/at32stk1000.conf
@@ -11,7 +11,7 @@ PREFERRED_PROVIDER_xserver = "xserver-kdrive"
#don't try to access tty1
USE_VT = "0"
-MACHINE_FEATURES = "kernel26 alsa ext2 usbhost usbgadget screen"
+MACHINE_FEATURES = "kernel26 alsa ext2 usbgadget touchscreen screen"
# used by sysvinit_2
SERIAL_CONSOLE = "115200"
@@ -21,3 +21,5 @@ ROOT_FLASH_SIZE = "8"
EXTRA_IMAGECMD_jffs2 = " --big-endian --pagesize=4096 --eraseblock=65536"
KERNEL_IMAGETYPE = "uImage"
+
+PREFERRED_VERSION_u-boot = "1.1.4" \ No newline at end of file
diff --git a/conf/machine/atngw100.conf b/conf/machine/atngw100.conf
index 4df1030570..76453323ff 100644
--- a/conf/machine/atngw100.conf
+++ b/conf/machine/atngw100.conf
@@ -9,7 +9,7 @@ PREFERRED_PROVIDER_xserver = "xserver-kdrive"
#don't try to access tty1
USE_VT = "0"
-MACHINE_FEATURES = "kernel26 ext2 usbhost usbgadget"
+MACHINE_FEATURES = "kernel26 ext2 usbgadget"
# used by sysvinit_2
SERIAL_CONSOLE = "115200"
@@ -18,4 +18,5 @@ SERIAL_CONSOLE = "115200"
ROOT_FLASH_SIZE = "8"
EXTRA_IMAGECMD_jffs2 = " --big-endian --pagesize=4096 --eraseblock=65536"
-KERNEL_IMAGETYPE = "uImage"
+PREFERRED_VERSION_u-boot = "1.1.4"
+KERNEL_IMAGETYPE = "uImage" \ No newline at end of file
diff --git a/packages/binutils/binutils-2.17/503-avr32-fix-got-offset-init.patch b/packages/binutils/binutils-2.17/503-avr32-fix-got-offset-init.patch
new file mode 100644
index 0000000000..66add3a47b
--- /dev/null
+++ b/packages/binutils/binutils-2.17/503-avr32-fix-got-offset-init.patch
@@ -0,0 +1,12 @@
+stelios@Athena:~/proj/oplinux-0.2/org.openembedded.dev/packages/binutils$ cat binutils-2.17/503-avr32-fix-got-offset-init.patch
+--- a/bfd/elf32-avr32.c 2007-05-31 17:00:13.000000000 +0200
++++ b/bfd/elf32-avr32.c 2007-05-30 14:07:25.000000000 +0200
+@@ -395,6 +395,8 @@ avr32_elf_link_hash_table_create(bfd *ab
+ /* Prevent the BFD core from creating bogus got_entry pointers */
+ ret->root.init_got_refcount.glist = NULL;
+ ret->root.init_plt_refcount.glist = NULL;
++ ret->root.init_got_offset.glist = NULL;
++ ret->root.init_plt_offset.glist = NULL;
+
+ return &ret->root.root;
+ } \ No newline at end of file
diff --git a/packages/binutils/binutils_2.17.bb b/packages/binutils/binutils_2.17.bb
index 8d38f3a459..69e11497c2 100644
--- a/packages/binutils/binutils_2.17.bb
+++ b/packages/binutils/binutils_2.17.bb
@@ -1,6 +1,6 @@
require binutils.inc
-PR = "r1"
+PR = "r2"
SRC_URI = \
"http://ftp.gnu.org/gnu/binutils/binutils-${PV}.tar.bz2 \
@@ -21,6 +21,7 @@ SRC_URI += "\
http://avr32linux.org/twiki/pub/Main/DevelopmentTools/500-avr32.patch.gz;patch=1 \
http://avr32linux.org/twiki/pub/Main/DevelopmentTools/501-avr32-sreldyn-fix.patch.gz;patch=1 \
http://avr32linux.org/twiki/pub/Main/DevelopmentTools/502-avr32-bfd-dont-allow-direct-refs-to-bss.patch.gz;patch=1 \
+ file://503-avr32-fix-got-offset-init.patch;patch=1 \
"
# Zecke's OSX fixes
diff --git a/packages/busybox/busybox-1.2.1/install-should-unlink-dest-if-it-exists.patch b/packages/busybox/busybox-1.2.1/install-should-unlink-dest-if-it-exists.patch
new file mode 100644
index 0000000000..4bec313f0e
--- /dev/null
+++ b/packages/busybox/busybox-1.2.1/install-should-unlink-dest-if-it-exists.patch
@@ -0,0 +1,53 @@
+---
+ coreutils/install.c | 2 +-
+ include/libbb.h | 3 ++-
+ libbb/copy_file.c | 9 +++++++++
+ 3 files changed, 12 insertions(+), 2 deletions(-)
+
+Index: busybox-1.2.1/coreutils/install.c
+===================================================================
+--- busybox-1.2.1.orig/coreutils/install.c 2006-10-19 16:33:48.000000000 +0200
++++ busybox-1.2.1/coreutils/install.c 2006-10-19 16:35:58.000000000 +0200
+@@ -59,7 +59,7 @@ int install_main(int argc, char **argv)
+ char *gid_str = "-1";
+ char *uid_str = "-1";
+ char *mode_str = "0755";
+- int copy_flags = FILEUTILS_DEREFERENCE | FILEUTILS_FORCE;
++ int copy_flags = FILEUTILS_DEREFERENCE | FILEUTILS_FORCE | FILEUTILS_NO_TRUNC;
+ int ret = EXIT_SUCCESS, flags, i, isdir;
+
+ #if ENABLE_FEATURE_INSTALL_LONG_OPTIONS
+Index: busybox-1.2.1/include/libbb.h
+===================================================================
+--- busybox-1.2.1.orig/include/libbb.h 2006-10-19 16:24:50.000000000 +0200
++++ busybox-1.2.1/include/libbb.h 2006-10-19 16:32:40.000000000 +0200
+@@ -345,7 +345,8 @@ enum { /* DO NOT CHANGE THESE VALUES! c
+ FILEUTILS_DEREFERENCE = 2,
+ FILEUTILS_RECUR = 4,
+ FILEUTILS_FORCE = 8,
+- FILEUTILS_INTERACTIVE = 16
++ FILEUTILS_INTERACTIVE = 16,
++ FILEUTILS_NO_TRUNC = 32
+ };
+
+ extern const char *bb_applet_name;
+Index: busybox-1.2.1/libbb/copy_file.c
+===================================================================
+--- busybox-1.2.1.orig/libbb/copy_file.c 2006-10-19 16:26:53.000000000 +0200
++++ busybox-1.2.1/libbb/copy_file.c 2006-10-19 16:32:28.000000000 +0200
+@@ -136,6 +136,15 @@ int copy_file(const char *source, const
+ }
+ }
+
++ if (flags & FILEUTILS_NO_TRUNC) {
++ if (unlink(dest) < 0) {
++ bb_perror_msg("unable to remove `%s'", dest);
++ close(src_fd);
++ return -1;
++ }
++ goto dest_removed;
++ }
++
+ dst_fd = open(dest, O_WRONLY|O_TRUNC);
+ if (dst_fd == -1) {
+ if (!(flags & FILEUTILS_FORCE)) {
diff --git a/packages/busybox/busybox_1.2.1.bb b/packages/busybox/busybox_1.2.1.bb
index 054649e9df..773c5e1a7e 100644
--- a/packages/busybox/busybox_1.2.1.bb
+++ b/packages/busybox/busybox_1.2.1.bb
@@ -1,11 +1,13 @@
require busybox.inc
-PR = "r13"
+PR = "r14"
SRC_URI += "file://wget-long-options.patch;patch=1 \
file://df_rootfs.patch;patch=1 \
file://defconfig"
+SRC_URI_append_avr32 = " file://install-should-unlink-dest-if-it-exists.patch;patch=1"
+
do_configure () {
install -m 0644 ${WORKDIR}/defconfig ${S}/.config.oe
diff --git a/packages/busybox/files/install-should-unlink-dest-if-it-exists.patch b/packages/busybox/files/install-should-unlink-dest-if-it-exists.patch
new file mode 100644
index 0000000000..4bec313f0e
--- /dev/null
+++ b/packages/busybox/files/install-should-unlink-dest-if-it-exists.patch
@@ -0,0 +1,53 @@
+---
+ coreutils/install.c | 2 +-
+ include/libbb.h | 3 ++-
+ libbb/copy_file.c | 9 +++++++++
+ 3 files changed, 12 insertions(+), 2 deletions(-)
+
+Index: busybox-1.2.1/coreutils/install.c
+===================================================================
+--- busybox-1.2.1.orig/coreutils/install.c 2006-10-19 16:33:48.000000000 +0200
++++ busybox-1.2.1/coreutils/install.c 2006-10-19 16:35:58.000000000 +0200
+@@ -59,7 +59,7 @@ int install_main(int argc, char **argv)
+ char *gid_str = "-1";
+ char *uid_str = "-1";
+ char *mode_str = "0755";
+- int copy_flags = FILEUTILS_DEREFERENCE | FILEUTILS_FORCE;
++ int copy_flags = FILEUTILS_DEREFERENCE | FILEUTILS_FORCE | FILEUTILS_NO_TRUNC;
+ int ret = EXIT_SUCCESS, flags, i, isdir;
+
+ #if ENABLE_FEATURE_INSTALL_LONG_OPTIONS
+Index: busybox-1.2.1/include/libbb.h
+===================================================================
+--- busybox-1.2.1.orig/include/libbb.h 2006-10-19 16:24:50.000000000 +0200
++++ busybox-1.2.1/include/libbb.h 2006-10-19 16:32:40.000000000 +0200
+@@ -345,7 +345,8 @@ enum { /* DO NOT CHANGE THESE VALUES! c
+ FILEUTILS_DEREFERENCE = 2,
+ FILEUTILS_RECUR = 4,
+ FILEUTILS_FORCE = 8,
+- FILEUTILS_INTERACTIVE = 16
++ FILEUTILS_INTERACTIVE = 16,
++ FILEUTILS_NO_TRUNC = 32
+ };
+
+ extern const char *bb_applet_name;
+Index: busybox-1.2.1/libbb/copy_file.c
+===================================================================
+--- busybox-1.2.1.orig/libbb/copy_file.c 2006-10-19 16:26:53.000000000 +0200
++++ busybox-1.2.1/libbb/copy_file.c 2006-10-19 16:32:28.000000000 +0200
+@@ -136,6 +136,15 @@ int copy_file(const char *source, const
+ }
+ }
+
++ if (flags & FILEUTILS_NO_TRUNC) {
++ if (unlink(dest) < 0) {
++ bb_perror_msg("unable to remove `%s'", dest);
++ close(src_fd);
++ return -1;
++ }
++ goto dest_removed;
++ }
++
+ dst_fd = open(dest, O_WRONLY|O_TRUNC);
+ if (dst_fd == -1) {
+ if (!(flags & FILEUTILS_FORCE)) {
diff --git a/packages/gcc/avr32-gcc-cross_4.1.2.bb b/packages/gcc/avr32-gcc-cross_4.1.2.bb
new file mode 100644
index 0000000000..e34098f840
--- /dev/null
+++ b/packages/gcc/avr32-gcc-cross_4.1.2.bb
@@ -0,0 +1,22 @@
+require avr32-gcc_${PV}.bb
+# path mangling, needed by the cross packaging
+require gcc-paths-cross.inc
+inherit cross
+FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}"
+# NOTE: split PR. If the main .oe changes something that affects its *build*
+# remember to increment this one too.
+PR = "r0"
+
+DEPENDS = "virtual/${TARGET_PREFIX}binutils virtual/${TARGET_PREFIX}libc-for-gcc gmp-native mpfr-native"
+PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++"
+
+# cross build
+require gcc3-build-cross.inc
+# cross packaging
+require gcc-package-cross.inc
+
+SRC_URI_append_fail-fast = " file://zecke-no-host-includes.patch;patch=1 "
+
+EXTRA_OECONF += " --disable-libmudflap \
+ --disable-libunwind-exceptions \
+ --with-mpfr=${STAGING_DIR}/${BUILD_SYS}"
diff --git a/packages/gcc/avr32-gcc_4.1.2.bb b/packages/gcc/avr32-gcc_4.1.2.bb
new file mode 100644
index 0000000000..60254db87e
--- /dev/null
+++ b/packages/gcc/avr32-gcc_4.1.2.bb
@@ -0,0 +1,22 @@
+require gcc_${PV}.bb
+
+FILESPATH = "${@base_set_filespath([ '${FILE_DIRNAME}/gcc-4.1.2', '${FILE_DIRNAME}/gcc', '${FILE_DIRNAME}/files', '${FILE_DIRNAME}' ], d)}"
+
+SRC_URI = "http://www.angstrom-distribution.org/unstable/sources/gcc-4.1.2-atmel.1.0.0.tar.gz \
+# file://100-uclibc-conf.patch;patch=1 \
+# file://200-uclibc-locale.patch;patch=1 \
+# file://300-libstdc++-pic.patch;patch=1 \
+ file://301-missing-execinfo_h.patch;patch=1 \
+ file://302-c99-snprintf.patch;patch=1 \
+ file://303-c99-complex-ugly-hack.patch;patch=1 \
+ file://304-index_macro.patch;patch=1 \
+ file://602-sdk-libstdc++-includes.patch;patch=1 \
+ file://gcc41-configure.in.patch;patch=1 \
+ file://ldflags.patch;patch=1 \
+ file://zecke-xgcc-cpp.patch;patch=1 \
+ file://cache-amnesia.patch;patch=1 \
+ "
+
+do_compile_prepend() {
+ln -sf ${S}/libstdc++-v3/config/os/uclibc/ ${S}/libstdc++-v3/config/os/uclibc-linux
+}
diff --git a/packages/libmad/files/.mtn2git_empty b/packages/libmad/files/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/libmad/files/.mtn2git_empty
diff --git a/packages/libmad/files/libmad-0.15.1b-avr32-optimization.patch b/packages/libmad/files/libmad-0.15.1b-avr32-optimization.patch
new file mode 100644
index 0000000000..f6620f591a
--- /dev/null
+++ b/packages/libmad/files/libmad-0.15.1b-avr32-optimization.patch
@@ -0,0 +1,2922 @@
+diff --git a/bit.c b/bit.c
+index c2bfb24..262ce3a 100644
+--- a/bit.c
++++ b/bit.c
+@@ -25,12 +25,6 @@
+
+ # include "global.h"
+
+-# ifdef HAVE_LIMITS_H
+-# include <limits.h>
+-# else
+-# define CHAR_BIT 8
+-# endif
+-
+ # include "bit.h"
+
+ /*
+@@ -81,6 +75,8 @@ unsigned short const crc_table[256] = {
+
+ # define CRC_POLY 0x8005
+
++#ifndef FPM_AVR32
++
+ /*
+ * NAME: bit->init()
+ * DESCRIPTION: initialize bit pointer struct
+@@ -190,6 +186,8 @@ void mad_bit_write(struct mad_bitptr *bitptr, unsigned int len,
+ }
+ # endif
+
++#endif
++
+ /*
+ * NAME: bit->crc()
+ * DESCRIPTION: compute CRC-check word
+diff --git a/bit.h b/bit.h
+index 5a51570..70f550a 100644
+--- a/bit.h
++++ b/bit.h
+@@ -22,6 +22,92 @@
+ # ifndef LIBMAD_BIT_H
+ # define LIBMAD_BIT_H
+
++# ifdef HAVE_LIMITS_H
++# include <limits.h>
++# else
++# define CHAR_BIT 8
++# endif
++
++#ifdef FPM_AVR32
++
++struct mad_bitptr {
++ unsigned char const *byte;
++ unsigned int read_bytes;
++};
++
++/*
++ * NAME: bit->init()
++ * DESCRIPTION: initialize bit pointer struct
++ */
++static void mad_bit_init(struct mad_bitptr *bitptr, unsigned char const *byte)
++{
++ bitptr->byte = byte;
++ bitptr->read_bytes = 0;
++}
++
++/*
++ * NAME: bit->length()
++ * DESCRIPTION: return number of bits between start and end points
++ */
++static unsigned int mad_bit_length(struct mad_bitptr const *begin,
++ struct mad_bitptr const *end)
++{
++ return (end->read_bytes - begin->read_bytes) +
++ 8 * (end->byte - begin->byte);
++}
++
++/*
++ * NAME: bit->nextbyte()
++ * DESCRIPTION: return pointer to next unprocessed byte
++ */
++static unsigned char const *mad_bit_nextbyte(struct mad_bitptr const *bitptr)
++{
++ return bitptr->byte + ((bitptr->read_bytes + 0x7) >> 3);
++}
++
++/*
++ * NAME: bit->skip()
++ * DESCRIPTION: advance bit pointer
++ */
++static void mad_bit_skip(struct mad_bitptr *bitptr, unsigned int len)
++{
++ bitptr->read_bytes += len;
++ bitptr->byte += (bitptr->read_bytes >> 3);
++ bitptr->read_bytes &= 0x7;
++}
++
++/*
++ * NAME: bit->read()
++ * DESCRIPTION: read an arbitrary number of bits and return their UIMSBF value
++ */
++static unsigned long mad_bit_read(struct mad_bitptr *bitptr, unsigned int len)
++{
++ register unsigned long value;
++
++ if (!len)
++ return 0;
++
++ value = *(unsigned int *)bitptr->byte;
++
++ value <<= bitptr->read_bytes;
++ value >>= (32 - len);
++
++ bitptr->read_bytes += len;
++ bitptr->byte += (bitptr->read_bytes >> 3);
++ bitptr->read_bytes &= 0x7;
++
++ return value;
++}
++
++# define mad_bit_finish(bitptr) /* nothing */
++
++static unsigned long mad_bit_bitsleft(struct mad_bitptr *bitptr)
++{
++ return (8 - (bitptr)->read_bytes);
++}
++
++#else /* #ifdef FPM_AVR32 */
++
+ struct mad_bitptr {
+ unsigned char const *byte;
+ unsigned short cache;
+@@ -42,6 +128,8 @@ void mad_bit_skip(struct mad_bitptr *, unsigned int);
+ unsigned long mad_bit_read(struct mad_bitptr *, unsigned int);
+ void mad_bit_write(struct mad_bitptr *, unsigned int, unsigned long);
+
++#endif
++
+ unsigned short mad_bit_crc(struct mad_bitptr, unsigned int, unsigned short);
+
+ # endif
+diff --git a/configure b/configure
+index ee421cc..7a9f0c8 100755
+--- a/configure
++++ b/configure
+@@ -1048,7 +1048,7 @@ Optional Features:
+ --enable-speed optimize for speed over accuracy
+ --enable-accuracy optimize for accuracy over speed
+ --enable-fpm=ARCH use ARCH-specific fixed-point math routines (one of:
+- intel, arm, mips, sparc, ppc, 64bit, default)
++ intel, arm, avr32, mips, sparc, ppc, 64bit, default)
+ --enable-sso use subband synthesis optimization
+ --disable-aso disable architecture-specific optimizations
+ --enable-strict-iso use strict ISO/IEC interpretations
+@@ -21477,6 +21477,7 @@ if test "${enable_fpm+set}" = set; then
+ no|default|approx) FPM="DEFAULT" ;;
+ intel|i?86) FPM="INTEL" ;;
+ arm) FPM="ARM" ;;
++ avr32) FPM="AVR32" ;;
+ mips) FPM="MIPS" ;;
+ sparc) FPM="SPARC" ;;
+ ppc|powerpc) FPM="PPC" ;;
+@@ -21498,6 +21499,7 @@ then
+ case "$host" in
+ i?86-*) FPM="INTEL" ;;
+ arm*-*) FPM="ARM" ;;
++ avr32*-*) FPM="AVR32" ;;
+ mips*-*) FPM="MIPS" ;;
+ sparc*-*) FPM="SPARC" ;;
+ powerpc*-*) FPM="PPC" ;;
+@@ -21554,6 +21556,11 @@ then
+ ASO="$ASO -DASO_IMDCT"
+ ASO_OBJS="imdct_l_arm.lo"
+ ;;
++ avr32*-*)
++ ASO="$ASO -DASO_INTERLEAVE2"
++ ASO="$ASO -DASO_ZEROCHECK"
++ ASO_OBJS="dct32_avr32.lo synth_avr32.lo imdct_avr32.lo"
++ ;;
+ mips*-*)
+ ASO="$ASO -DASO_INTERLEAVE2"
+ ASO="$ASO -DASO_ZEROCHECK"
+diff --git a/configure.ac b/configure.ac
+index 9b79399..063cb9b 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -274,13 +274,14 @@ fi
+ AC_MSG_CHECKING(for architecture-specific fixed-point math routines)
+ AC_ARG_ENABLE(fpm, AC_HELP_STRING([--enable-fpm=ARCH],
+ [use ARCH-specific fixed-point math routines
+- (one of: intel, arm, mips, sparc, ppc, 64bit, default)]),
++ (one of: intel, arm, avr32, mips, sparc, ppc, 64bit, default)]),
+ [
+ case "$enableval" in
+ yes) ;;
+ no|default|approx) FPM="DEFAULT" ;;
+ intel|i?86) FPM="INTEL" ;;
+ arm) FPM="ARM" ;;
++ avr32) FPM="AVR32" ;;
+ mips) FPM="MIPS" ;;
+ sparc) FPM="SPARC" ;;
+ ppc|powerpc) FPM="PPC" ;;
+@@ -298,6 +299,7 @@ then
+ case "$host" in
+ i?86-*) FPM="INTEL" ;;
+ arm*-*) FPM="ARM" ;;
++ avr32*-*) FPM="AVR32" ;;
+ mips*-*) FPM="MIPS" ;;
+ sparc*-*) FPM="SPARC" ;;
+ powerpc*-*) FPM="PPC" ;;
+@@ -343,6 +345,11 @@ then
+ ASO="$ASO -DASO_IMDCT"
+ ASO_OBJS="imdct_l_arm.lo"
+ ;;
++ avr32*-*)
++ ASO="$ASO -DASO_INTERLEAVE2"
++ ASO="$ASO -DASO_ZEROCHECK"
++ ASO_OBJS="dct32_avr32.lo synth_avr32.lo imdct_avr32.lo"
++ ;;
+ mips*-*)
+ ASO="$ASO -DASO_INTERLEAVE2"
+ ASO="$ASO -DASO_ZEROCHECK"
+diff --git a/dct32_avr32.S b/dct32_avr32.S
+new file mode 100644
+index 0000000..7513340
+--- /dev/null
++++ b/dct32_avr32.S
+@@ -0,0 +1,780 @@
++/*
++ Optimized 32-point Discrete Cosine Transform (DCT)
++ Copyright 2003-2006 Atmel Corporation.
++
++ Written by Ronny Pedersen, Atmel Norway
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
++
++#define SHIFT 12
++#define MAD_F_SCALEBITS 28
++#define SLOTS 8
++
++#define MAD_F(x) ((x + (1 << 15)) >> 16)
++
++# define costab1 MAD_F(0x7fd8878e)
++# define costab2 MAD_F(0x7f62368f)
++# define costab3 MAD_F(0x7e9d55fc)
++# define costab4 MAD_F(0x7d8a5f40)
++# define costab5 MAD_F(0x7c29fbee)
++# define costab6 MAD_F(0x7a7d055b)
++# define costab7 MAD_F(0x78848414)
++# define costab8 MAD_F(0x7641af3d)
++# define costab9 MAD_F(0x73b5ebd1)
++# define costab10 MAD_F(0x70e2cbc6)
++# define costab11 MAD_F(0x6dca0d14)
++# define costab12 MAD_F(0x6a6d98a4)
++# define costab13 MAD_F(0x66cf8120)
++# define costab14 MAD_F(0x62f201ac)
++# define costab15 MAD_F(0x5ed77c8a)
++# define costab16 MAD_F(0x5a82799a)
++# define costab17 MAD_F(0x55f5a4d2)
++# define costab18 MAD_F(0x5133cc94)
++# define costab19 MAD_F(0x4c3fdff4)
++# define costab20 MAD_F(0x471cece7)
++# define costab21 MAD_F(0x41ce1e65)
++# define costab22 MAD_F(0x3c56ba70)
++# define costab23 MAD_F(0x36ba2014)
++# define costab24 MAD_F(0x30fbc54d)
++# define costab25 MAD_F(0x2b1f34eb)
++# define costab26 MAD_F(0x25280c5e)
++# define costab27 MAD_F(0x1f19f97b)
++# define costab28 MAD_F(0x18f8b83c)
++# define costab29 MAD_F(0x12c8106f)
++# define costab30 MAD_F(0x0c8bd35e)
++# define costab31 MAD_F(0x0647d97c)
++
++
++ .macro butterfly2_in out1, out2, out3, out4, in, idx_in1, idx_in2, idx_in3, idx_in4, coeff1, coeff2, tmplo, tmphi
++ mov \tmplo, \coeff1
++ ld.w \out1, \in[\idx_in1 * 4]
++ ld.w \out2, \in[\idx_in2 * 4]
++ ld.w \out3, \in[\idx_in3 * 4]
++ ld.w \out4, \in[\idx_in4 * 4]
++ sub \tmphi, \out1, \out2
++ add \out1, \out2
++ mulsatrndwh.w \out2, \tmphi, \tmplo:b
++
++ sub \tmphi, \out3, \out4
++ mov \tmplo, \coeff2
++ add \out3, \out4
++ mulsatrndwh.w \out4, \tmphi, \tmplo:b
++ .endm
++
++ .macro butterfly2 in1, in2, in3, in4, coeff1, tmplo, tmphi, tmp
++ mov \tmp, \coeff1
++ sub \tmphi, \in1, \in2
++ add \in1, \in2
++ mulsatrndwh.w \in2, \tmphi, \tmp:b
++
++ sub \tmphi, \in3, \in4
++ add \in3, \in4
++ mulsatrndwh.w \in4, \tmphi, \tmp:b
++ .endm
++
++ .macro butterfly4 in1, in2, in3, in4, in5, in6, in7, in8, coeff1, tmplo, tmphi, tmp
++ mov \tmp, \coeff1
++ sub \tmphi, \in1, \in2
++ add \in1, \in2
++ mulsatrndwh.w \in2, \tmphi, \tmp:b
++
++ sub \tmphi, \in3, \in4
++ add \in3, \in4
++ mulsatrndwh.w \in4, \tmphi, \tmp:b
++
++ sub \tmphi, \in5, \in6
++ add \in5, \in6
++ mulsatrndwh.w \in6, \tmphi, \tmp:b
++
++ sub \tmphi, \in7, \in8
++ add \in7, \in8
++ mulsatrndwh.w \in8, \tmphi, \tmp:b
++ .endm
++
++ .macro scale reg
++ .endm
++
++/*void dct32( mad_fixed_t const in[32], unsigned int slot,
++ mad_fixed_t lo[16][8], mad_fixed_t hi[16][8]) */
++
++ .global dct32_avr32
++dct32_avr32:
++ stm --sp, r0-r7, r9-r11, lr
++
++ sub sp, 32*4
++
++/* t0 = in[0] + in[31]; t16 = MUL(in[0] - in[31], costab1);
++ t1 = in[15] + in[16]; t17 = MUL(in[15] - in[16], costab31); */
++ butterfly2_in r4/*t0*/, r5/*t16*/, r6/*t1*/, r7/*t17*/, r12, 0, 31, 15, 16, costab1, costab31, r10, r11
++
++/* t41 = t16 + t17;
++ t59 = MUL(t16 - t17, costab2);
++ t33 = t0 + t1;
++ t50 = MUL(t0 - t1, costab2);*/
++ butterfly2 r5/*t41*/, r7/*t59*/, r4/*t33*/, r6/*t50*/, costab2, r10, r11, lr
++
++/* t2 = in[7] + in[24]; t18 = MUL(in[7] - in[24], costab15);
++ t3 = in[8] + in[23]; t19 = MUL(in[8] - in[23], costab17); */
++ butterfly2_in r0/*t2*/, r1/*t18*/, r2/*t3*/, r3/*t19*/, r12, 7, 24, 8, 23, costab15, costab17, r10, r11
++
++/* t42 = t18 + t19;
++ t60 = MUL(t18 - t19, costab30);
++ t34 = t2 + t3;
++ t51 = MUL(t2 - t3, costab30); */
++ butterfly2 r1/*t42*/, r3/*t60*/, r0/*t34*/, r2/*t51*/, costab30, r10, r11, lr
++
++/* t73 = t41 + t42; t94 = MUL(t41 - t42, costab4);
++ t83 = t59 + t60; t106 = MUL(t59 - t60, costab4); */
++
++
++/* t69 = t33 + t34; t89 = MUL(t33 - t34, costab4);
++ t78 = t50 + t51; t100 = MUL(t50 - t51, costab4); */
++ butterfly4 r5/*t73*/, r1/*t94*/, r7/*t83*/, r3/*t106*/,r4/*t69*/, r0/*t89*/, r6/*t78*/, r2/*t100*/, costab4, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[0-7] = t83, t78, t73, t69, t106, t100, t94, t89 */
++ stm sp, r0-r7
++
++
++/* t4 = in[3] + in[28]; t20 = MUL(in[3] - in[28], costab7);
++ t5 = in[12] + in[19]; t21 = MUL(in[12] - in[19], costab25); */
++ butterfly2_in r4/*t4*/, r5/*t20*/, r6/*t5*/, r7/*t21*/, r12, 3, 28, 12, 19, costab7, costab25, r10, r11
++
++/* t43 = t20 + t21;
++ t61 = MUL(t20 - t21, costab14);
++ t35 = t4 + t5;
++ t52 = MUL(t4 - t5, costab14); */
++ butterfly2 r5/*t43*/, r7/*t61*/, r4/*t35*/, r6/*t52*/, costab14, r10, r11, lr
++
++/* t6 = in[4] + in[27]; t22 = MUL(in[4] - in[27], costab9);
++ t7 = in[11] + in[20]; t23 = MUL(in[11] - in[20], costab23); */
++ butterfly2_in r0/*t6*/, r1/*t22*/, r2/*t7*/, r3/*t23*/, r12, 4, 27, 11, 20, costab9, costab23, r10, r11
++
++/* t44 = t22 + t23;
++ t62 = MUL(t22 - t23, costab18);
++ t36 = t6 + t7;
++ t53 = MUL(t6 - t7, costab18); */
++ butterfly2 r1/*t44*/, r3/*t62*/, r0/*t36*/, r2/*t53*/, costab18, r10, r11, lr
++
++/* t74 = t43 + t44; t95 = MUL(t43 - t44, costab28);
++ t84 = t61 + t62; t107 = MUL(t61 - t62, costab28); */
++
++/* t70 = t35 + t36; t90 = MUL(t35 - t36, costab28);
++ t79 = t52 + t53; t101 = MUL(t52 - t53, costab28); */
++ butterfly4 r5/*t74*/, r1/*t95*/, r7/*t84*/, r3/*t107*/, r4/*t70*/, r0/*t90*/, r6/*t79*/, r2/*t101*/, costab28, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[8-15] = t84, t79, t74, t70, t107, t101, t95, t90 */
++ sub r10, sp, -8*4
++ stm r10, r0-r7
++
++
++/* t8 = in[1] + in[30]; t24 = MUL(in[1] - in[30], costab3);
++ t9 = in[14] + in[17]; t25 = MUL(in[14] - in[17], costab29); */
++ butterfly2_in r4/*t8*/, r5/*t24*/, r6/*t9*/, r7/*t25*/, r12, 1, 30, 14, 17, costab3, costab29, r10, r11
++
++
++/* t45 = t24 + t25;
++ t63 = MUL(t24 - t25, costab6);
++ t37 = t8 + t9;
++ t54 = MUL(t8 - t9, costab6); */
++ butterfly2 r5/*t45*/, r7/*t63*/, r4/*t37*/, r6/*t54*/, costab6, r10, r11, lr
++
++/* t10 = in[6] + in[25]; t26 = MUL(in[6] - in[25], costab13);
++ t11 = in[9] + in[22]; t27 = MUL(in[9] - in[22], costab19); */
++ butterfly2_in r0/*t10*/, r1/*t26*/, r2/*t11*/, r3/*t27*/, r12, 6, 25, 9, 22, costab13, costab19, r10, r11
++
++/* t46 = t26 + t27;
++ t64 = MUL(t26 - t27, costab26);
++ t38 = t10 + t11;
++ t55 = MUL(t10 - t11, costab26); */
++ butterfly2 r1/*t46*/, r3/*t64*/, r0/*t38*/, r2/*t55*/, costab26, r10, r11, lr
++
++/* t75 = t45 + t46; t96 = MUL(t45 - t46, costab12);
++ t85 = t63 + t64; t108 = MUL(t63 - t64, costab12); */
++
++/* t71 = t37 + t38; t91 = MUL(t37 - t38, costab12);
++ t80 = t54 + t55; t102 = MUL(t54 - t55, costab12); */
++ butterfly4 r5/*t75*/, r1/*t96*/, r7/*t85*/, r3/*t108*/, r4/*t71*/, r0/*t91*/, r6/*t80*/, r2/*t102*/, costab12, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[16-23] = t85, t80, t75, t71, t108, t102, t96, t91 */
++ sub r10, sp, -16*4
++ stm r10, r0-r7
++
++/* t12 = in[2] + in[29]; t28 = MUL(in[2] - in[29], costab5);
++ t13 = in[13] + in[18]; t29 = MUL(in[13] - in[18], costab27); */
++ butterfly2_in r4/*t12*/, r5/*t28*/, r6/*t13*/, r7/*t29*/, r12, 2, 29, 13, 18, costab5, costab27, r10, r11
++
++/* t47 = t28 + t29;
++ t65 = MUL(t28 - t29, costab10);
++ t39 = t12 + t13;
++ t56 = MUL(t12 - t13, costab10); */
++ butterfly2 r5/*t47*/, r7/*t65*/, r4/*t39*/, r6/*t56*/, costab10, r10, r11, lr
++
++/* t14 = in[5] + in[26]; t30 = MUL(in[5] - in[26], costab11);
++ t15 = in[10] + in[21]; t31 = MUL(in[10] - in[21], costab21);*/
++ butterfly2_in r0/*t14*/, r1/*t30*/, r2/*t15*/, r3/*t31*/, r12, 5, 26, 10, 21, costab11, costab21, r10, r11
++
++/* t48 = t30 + t31;
++ t66 = MUL(t30 - t31, costab22);
++ t40 = t14 + t15;
++ t57 = MUL(t14 - t15, costab22);*/
++ butterfly2 r1/*t48*/, r3/*t66*/, r0/*t40*/, r2/*t57*/, costab22, r10, r11, lr
++
++/* t76 = t47 + t48; t97 = MUL(t47 - t48, costab20);
++ t86 = t65 + t66; t109 = MUL(t65 - t66, costab20);*/
++
++/* t72 = t39 + t40; t92 = MUL(t39 - t40, costab20);
++ t81 = t56 + t57; t103 = MUL(t56 - t57, costab20);*/
++ butterfly4 r5/*t76*/, r1/*t97*/, r7/*t86*/, r3/*t109*/,r4/*t72*/, r0/*t92*/, r6/*t81*/, r2/*t103*/, costab20, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[24-31] = t86, t81, t76, t72, t109, t103, t97, t92 */
++ sub r10, sp, -24*4
++ stm r10, r0-r7
++
++/* We now have the following on the stack:
++
++ sp[0-7] = t83, t78, t73, t69, t106, t100, t94, t89
++ sp[8-15] = t84, t79, t74, t70, t107, t101, t95, t90
++ sp[16-23] = t85, t80, t75, t71, t108, t102, t96, t91
++ sp[24-31] = t86, t81, t76, t72, t109, t103, t97, t92 */
++
++/* Load {r0...r7} = { t72, t76, t71, t75, t70, t74, t69, t73 } */
++ ld.d r6, sp[2*4]
++ ld.d r4, sp[10*4]
++ ld.d r2, sp[18*4]
++ ld.d r0, sp[26*4]
++
++
++/* t113 = t69 + t70;
++ t141 = MUL(t69 - t70, costab8);
++
++ t115 = t73 + t74;
++ t144 = MUL(t73 - t74, costab8); */
++ butterfly2 r6/*t113*/, r4/*t141*/, r7/*t115*/, r5/*t144*/, costab8, r10, r11, lr
++
++/* t114 = t71 + t72;
++ t142 = MUL(t71 - t72, costab24);
++
++ t116 = t75 + t76;
++ t145 = MUL(t75 - t76, costab24); */
++ butterfly2 r2/*t114*/, r0/*t142*/, r3/*t116*/, r1/*t145*/, costab24, r10, r11, lr
++
++
++/*
++ t191 = t113 + t114;
++ t192 = MUL(t113 - t114, costab16)
++
++ t32 = t115 + t116;
++ t177 = MUL(t115 - t116, costab16) ;
++
++ t143 = t141 + t142;
++ t190 = MUL(t141 - t142, costab16) ;
++
++ t146 = t144 + t145;
++ t184 = MUL(t144 - t145, costab16) ; */
++ butterfly4 r6/*t191*/, r2/*t192*/, r7/*t32*/, r3/*t177*/, r4/*t143*/, r0/*190*/, r5/*t146*/, r1/*t184*/, costab16, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[2-3] = t32, t191
++ sp[10-11] = t146, t143
++ sp[18-19] = t177, t192
++ sp[26-27] = t184, t190 */
++ st.d sp[2*4] , r6
++ st.d sp[10*4], r4
++ st.d sp[18*4], r2
++ st.d sp[26*4], r0
++
++/* Load {r0...r7} = { t81, t86, t80, t85, t79, t84, t78, t83 } */
++ ld.d r6, sp[0*4]
++ ld.d r4, sp[8*4]
++ ld.d r2, sp[16*4]
++ ld.d r0, sp[24*4]
++
++
++/* t118 = t78 + t79;
++ t148 = MUL(t78 - t79, costab8);
++
++ t121 = t83 + t84;
++ t152 = MUL(t83 - t84, costab8); */
++ butterfly2 r6/*t118*/, r4/*t148*/, r7/*t121*/, r5/*t152*/, costab8, r10, r11, lr
++
++/* t119 = t80 + t81;
++ t149 = MUL(t80 - t81, costab24);
++
++ t122 = t85 + t86;
++ t153 = MUL(t85 - t86, costab24); */
++ butterfly2 r2/*t119*/, r0/*t149*/, r3/*t122*/, r1/*t153*/, costab24, r10, r11, lr
++
++
++
++/* t58 = t118 + t119;
++ t178 = MUL(t118 - t119, costab16) ;
++
++ t67 = t121 + t122;
++ t179 = MUL(t121 - t122, costab16) ;
++
++ t150 = t148 + t149;
++ t185 = MUL(t148 - t149, costab16) ;
++
++ t154 = t152 + t153;
++ t186 = MUL(t152 - t153, costab16) ; */
++ butterfly4 r6/*t58*/, r2/*t178*/, r7/*t67*/, r3/*t179*/, r4/*t150*/, r0/*185*/, r5/*t154*/, r1/*t186*/, costab16, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[0-1] = t67, t58
++ sp[8-9] = t154, t150
++ sp[16-17] = t179, t178
++ sp[24-25] = t186, t185 */
++ st.d sp[0*4] , r6
++ st.d sp[8*4], r4
++ st.d sp[16*4], r2
++ st.d sp[24*4], r0
++
++/* Load {r0...r7} = { t92, t97, t91, t96, t90, t95, t89, t94 } */
++ ld.d r6, sp[6*4]
++ ld.d r4, sp[14*4]
++ ld.d r2, sp[22*4]
++ ld.d r0, sp[30*4]
++
++
++/* t125 = t89 + t90;
++ t157 = MUL(t89 - t90, costab8);
++
++ t128 = t94 + t95;
++ t161 = MUL(t94 - t95, costab8); */
++ butterfly2 r6/*t125*/, r4/*t157*/, r7/*t128*/, r5/*t161*/, costab8, r10, r11, lr
++
++/* t126 = t91 + t92;
++ t158 = MUL(t91 - t92, costab24);
++
++ t129 = t96 + t97;
++ t162 = MUL(t96 - t97, costab24); */
++ butterfly2 r2/*t126*/, r0/*t158*/, r3/*t129*/, r1/*t162*/, costab24, r10, r11, lr
++
++
++/*
++ t93 = t125 + t126;
++ t180 = MUL(t125 - t126, costab16) ;
++
++ t98 = t128 + t129;
++ t181 = MUL(t128 - t129, costab16) ;
++
++ t159 = t157 + t158;
++ t187 = MUL(t157 - t158, costab16) ;
++
++ t163 = t161 + t162;
++ t188 = MUL(t161 - t162, costab16) ; */
++ butterfly4 r6/*t93*/, r2/*t180*/, r7/*t98*/, r3/*t181*/, r4/*t159*/, r0/*187*/, r5/*t163*/, r1/*t188*/, costab16, r10, r11, lr
++
++
++/* Store away the computed butterflies:
++ sp[6-7] = t98, t93
++ sp[14-15] = t163, t159
++ sp[22-23] = t181, t180
++ sp[30-31] = t188, t187 */
++ st.d sp[6*4] , r6
++ st.d sp[14*4], r4
++ st.d sp[22*4], r2
++ st.d sp[30*4], r0
++
++/* Load {r0...r7} = { t103, t109, t102, t108, t101, t107, t100, t106 } */
++ ld.d r6, sp[4*4]
++ ld.d r4, sp[12*4]
++ ld.d r2, sp[20*4]
++ ld.d r0, sp[28*4]
++
++
++
++/* t132 = t100 + t101;
++ t166 = MUL(t100 - t101, costab8);
++
++ t136 = t106 + t107;
++ t171 = MUL(t106 - t107, costab8); */
++ butterfly2 r6/*t132*/, r4/*t166*/, r7/*t136*/, r5/*t171*/, costab8, r10, r11, lr
++
++/* t133 = t102 + t103;
++ t167 = MUL(t102 - t103, costab24);
++
++ t137 = t108 + t109;
++ t172 = MUL(t108 - t109, costab24);*/
++ butterfly2 r2/*t133*/, r0/*t167*/, r3/*t137*/, r1/*t172*/, costab24, r10, r11, lr
++
++
++/* t104 = t132 + t133;
++ t182 = MUL(t132 - t133, costab16) ;
++
++ t110 = t136 + t137;
++ t183 = MUL(t136 - t137, costab16) ;
++
++ t168 = t166 + t167;
++ t189 = MUL(t166 - t167, costab16) ;
++
++ t173 = t171 + t172;
++ t208 = MUL(t171 - t172, costab16) ; */
++ butterfly4 r6/*t104*/, r2/*t182*/, r7/*t110*/, r3/*t183*/, r4/*t168*/, r0/*189*/, r5/*t173*/, r1/*t208*/, costab16, r10, r11, lr
++
++/* Store away the computed butterflies:
++ sp[4-5] = t110, t104
++ sp[12-13] = t173, t168
++ sp[20-21] = t183, t182
++ sp[28-29] = t208, t189 */
++ st.d sp[4*4] , r6
++ st.d sp[12*4], r4
++ st.d sp[20*4], r2
++ st.d sp[28*4], r0
++
++/* Now we have the following stack
++
++ sp[0-7] = t67, t58 , t32, t191, t110, t104, t98, t93
++ sp[8-15] = t154, t150, t146, t143, t173, t168, t163, t159
++ sp[16-23] = t179, t178, t177, t192, t183, t182, t181, t180
++ sp[24-31] = t186, t185, t184, t190, t208, t189, t188, t187
++*/
++
++ /* Get slot, lo and hi from stack */
++ lddsp lr, sp[32*4 + 4] /*slot*/
++ lddsp r12, sp[32*4 + 8] /*lo*/
++ lddsp r11, sp[32*4 + 12] /*hi*/
++
++ add r12, r12, lr << 2
++ add r11, r11, lr << 2
++
++
++/* t49 = -(t67 * 2) + t32;
++ hi[14][slot] = SHIFT(t32);
++ t87 = -(t110 * 2) + t67;
++ t138 = -(t173 * 2) + t110;
++ t203 = -(t208 * 2) + t173; */
++
++ lddsp r0/*t67*/, sp[0]
++ lddsp r1/*t32*/, sp[2*4]
++ lddsp r2/*t110*/, sp[4*4]
++ lddsp r3/*t173*/, sp[12*4]
++ lddsp r5/*t208*/, sp[28*4]
++
++ sub r4/*t49*/, r1, r0 << 1
++ scale r1
++ sub r0/*t87*/, r0, r2 << 1
++ st.w r11[14*SLOTS*4], r1
++ sub r2/*t138*/, r2, r3 << 1
++ sub r1/*t203*/, r3, r5 << 1
++
++/* Live: r0 = t87, r1= t203, r2= t138, r4 = t49
++ Free: r3, r5, r6, r7, r8, r9, r10, lr */
++
++/* t68 = (t98 * 2) + t49;
++ hi[12][slot] = SHIFT(-t49);
++ t130 = -(t163 * 2) + t98;
++ t201 = -(t188 * 2) + t163;
++ t200 = -(t186 * 2) + t154;
++ t111 = (t154 * 2) + t87;
++ t77 = -(-(t87 * 2) - t68);
++ t88 = (t146 * 2) + t77;
++ t199 = -(t184 * 2) + t146;
++ hi[ 8][slot] = SHIFT(-t77);
++ hi[10][slot] = SHIFT(t68);*/
++ lddsp r3/*t98*/, sp[6*4]
++ lddsp r5/*t163*/, sp[14*4]
++ lddsp r6/*t188*/, sp[30*4]
++ lddsp r10/*t186*/, sp[24*4]
++
++ add r7/*t68*/, r4, r3 << 1
++ neg r4
++ scale r4
++ lddsp r9/*t154*/, sp[8*4]
++ sub r3/*t130*/, r3, r5 << 1
++ st.w r11[12*SLOTS*4], r4
++ sub r8/*t201*/, r5, r6 << 1
++ sub r4/*t200*/, r9, r10 << 1
++ lddsp lr/*t146*/, sp[10*4]
++ lddsp r6/*t184*/, sp[26*4]
++ add r10/*t111*/, r0, r9 << 1
++ add r5/*t77*/,r7, r0 << 1
++ add r0/*t88*/, r5, lr << 1
++ sub r6/*t199*/, lr, r6 << 1
++ neg r5
++ scale r5
++ scale r7
++ st.w r11[8*SLOTS*4], r5
++ st.w r11[10*SLOTS*4], r7
++
++/* Live: r0 = t88, r1= t203, r2= t138, r3 = t130, r4 = t200,
++ r6 = 199, r8 = t201, r10 = t111
++ Free: r5, r7, r9, lr */
++
++
++/*
++ t123 = -(-(t138 * 2) - t111);
++ t174 = (t183 * 2) + t138;
++ t99 = -(t111 * 2) + t88;
++ hi[ 6][slot] = SHIFT(t88); */
++ lddsp r5/*t183*/, sp[20*4]
++
++ add r7/*t123*/, r10, r2 << 1
++ sub r10/*t99*/, r0, r10 << 1
++ scale r0
++ add r2/*t174*/, r2, r5 << 1
++ st.w r11[6*SLOTS*4], r0
++
++/* Live: r1 = t203, r2 = t174, r3 = t130, r4 = t200,
++ r6 = t199, r7 = t123, r8 = t201, r10 = t99
++ Free: r0, r5, r9, lr */
++
++/* t112 = -(t130 * 2) + t99;
++ t164 = (t181 * 2) + t130;
++ hi[ 4][slot] = SHIFT(-t99); */
++ lddsp r0/*t181*/, sp[22*4]
++
++ sub r5/*t112*/, r10, r3 << 1
++ neg r10
++ scale r10
++ add r3/*164*/, r3, r0 << 1
++ st.w r11[4*SLOTS*4], r10
++
++/* Live: r1 = t203, r2 = t174, r3 = t164, r4 = t200,
++ r5 = t112, r6 = t199, r7 = t123, r8 = t201
++ Free: r0, r9, r10, lr */
++
++
++/* t117 = -(-(t123 * 2) - t112);
++ t139 = (t179 * 2) + t123;
++ hi[ 2][slot] = SHIFT(t112); */
++ lddsp r0/*t179*/, sp[16*4]
++
++ add r9/*t117*/, r5, r7 << 1
++ scale r5
++ add r7/*t139*/, r7, r0 << 1
++ st.w r11[2*SLOTS*4], r5
++
++/* Live: r1 = t203, r2 = t174, r3 = t164, r4 = t200,
++ r6 = t199, r7 = t139, r8 = t201, r9 = t117
++ Free: r0, r5, r10, lr */
++
++/* t155 = -(t174 * 2) + t139;
++ t204 = -(-(t203 * 2) - t174);
++ t124 = (t177 * 2) + t117;
++ hi[ 0][slot] = SHIFT(-t117);
++ t131 = -(t139 * 2) + t124;
++ lo[ 1][slot] = SHIFT(t124);*/
++ lddsp r0/*t177*/, sp[18*4]
++
++ sub r5/*t155*/, r7, r2 << 1
++ add r2/*t204*/, r2, r1 << 1
++ add r0/*t124*/, r9, r0 << 1
++ neg r9
++ scale r9
++ sub r7/*t131*/, r0, r7 << 1
++ scale r0
++ st.w r11[0*SLOTS*4], r9
++ st.w r12[1*SLOTS*4], r0
++
++/* Live: r2 = t204, r3 = t164, r4 = t200,
++ r5 = t155, r6 = t199, r7 = t131, r8 = t201
++ Free: r0, r1, r9, r10, lr */
++
++/* t140 = (t164 * 2) + t131;
++ lo[ 3][slot] = SHIFT(-t131);
++ t202 = -(-(t201 * 2) - t164); */
++ add r0/*t140*/, r7, r3 << 1
++ neg r7
++ scale r7
++ add r3/*t202*/, r3, r8 << 1
++ st.w r12[3*SLOTS*4], r7
++
++/* Live: r0 = t140, r2 = t204, r3 = t202, r4 = t200,
++ r5 = t155, r6 = t199
++ Free: r1, r7, r8, r9, r10, lr */
++
++
++/* t147 = -(-(t155 * 2) - t140);
++ lo[ 5][slot] = SHIFT(t140);
++ t175 = -(t200 * 2) + t155;
++ t156 = -(t199 * 2) + t147;
++ lo[ 7][slot] = SHIFT(-t147); */
++ add r1/*t147*/, r0, r5 << 1
++ scale r0
++ sub r5/*t175*/, r5, r4 << 1
++ sub r4/*156*/, r1, r6 << 1
++ neg r1
++ scale r1
++ st.w r12[5*SLOTS*4], r0
++ st.w r12[7*SLOTS*4], r1
++
++/* Live: r2 = t204, r3 = t202,
++ r4 = t156, r5 = t175
++ Free: r0, r1, r6, r7, r8, r9, r10, lr */
++
++
++/* t205 = -(-(t204 * 2) - t175);
++ t165 = -(t175 * 2) + t156;
++ lo[ 9][slot] = SHIFT(t156);
++ t176 = -(t202 * 2) + t165;
++ lo[11][slot] = SHIFT(-t165);
++ t206 = -(-(t205 * 2) - t176);
++ lo[15][slot] = SHIFT(-t206)
++ lo[13][slot] = SHIFT(t176) */
++ add r0/*t205*/, r5, r2 << 1
++ sub r1/*t165*/, r4, r5 << 1
++ scale r4
++ sub r3/*t176*/, r1, r3 << 1
++ st.w r12[9*SLOTS*4], r4
++ neg r1
++ scale r1
++ add r6/*t206*/, r3, r0 << 1
++ neg r6
++ scale r6
++ scale r3
++ st.w r12[11*SLOTS*4], r1
++ st.w r12[15*SLOTS*4], r6
++ st.w r12[13*SLOTS*4], r3
++
++/* t193 = -((t190 * 2) - t143)
++ hi[ 7][slot] = SHIFT(t143);
++ lo[ 8][slot] = SHIFT(-t193);
++ t82 = -(t104 * 2) + t58;
++ hi[13][slot] = SHIFT(t58);
++ t134 = -(t168 * 2) + t104;
++ t196 = -(t189 * 2) + t168; */
++
++ lddsp r0/*t190*/, sp[27*4]
++ lddsp r1/*t143*/, sp[11*4]
++ lddsp r2/*t104*/, sp[5*4]
++ lddsp r3/*t58*/, sp[1*4]
++ lddsp r4/*t168*/, sp[13*4]
++ lddsp r5/*t189*/, sp[29*4]
++ sub r0/*t193*/, r1, r0 << 1
++ neg r0
++ scale r1
++ scale r0
++ st.w r11[7*SLOTS*4], r1
++ st.w r12[8*SLOTS*4], r0
++ sub r0/*t82*/, r3, r2 << 1
++ scale r3
++ sub r2/*t134*/, r2, r4 << 1
++ sub r4/*t196*/, r4, r5 << 1
++ st.w r11[13*SLOTS*4], r3
++
++/* Live: r0 = t82, r2 = t134,
++ r4 = t196
++ Free: r1, r3, r5, r6, r7, r8, r9, r10, lr */
++
++
++
++/*
++
++ t207 = -(t185 * 2) + t150;
++ t105 = (t150 * 2) + t82;
++ hi[ 9][slot] = SHIFT(-t82);
++ t120 = -(-(t134 * 2) - t105);
++ hi[ 5][slot] = SHIFT(t105);
++ t169 = (t182 * 2) + t134;
++
++ t135 = (t178 * 2) + t120;
++ hi[ 1][slot] = SHIFT(-t120);
++ t197 = -(-(t196 * 2) - t169);
++ t151 = -(t169 * 2) + t135;
++ lo[ 2][slot] = SHIFT(t135); */
++ lddsp r1/*t185*/, sp[25*4]
++ lddsp r3/*t150*/, sp[9*4]
++ lddsp r5/*t182*/, sp[21*4]
++ lddsp r8/*t178*/, sp[17*4]
++
++ sub r6/*t207*/, r3, r1 << 1
++ add r3/*t105*/, r0, r3 << 1
++ neg r0
++ scale r0
++ add r7/*t120*/, r3, r2 << 1
++ scale r3
++ st.w r11[9*SLOTS*4], r0
++ st.w r11[5*SLOTS*4], r3
++ add r2/*t169*/, r2, r5 << 1
++ add r8/*t135*/, r7, r8 << 1
++ neg r7
++ scale r7
++ add r4/*t197*/, r2, r4 << 1
++ sub r2/*t151*/, r8, r2 << 1
++ scale r8
++ st.w r11[1*SLOTS*4], r7
++ st.w r12[2*SLOTS*4], r8
++
++/* Live: r2 = t151, r4 = t197, r6 = t207
++
++ Free: r0, r1, r3, r5, r7, r8, r9, r10, lr */
++
++
++
++/* t170 = -(t207 * 2) + t151;
++ lo[ 6][slot] = SHIFT(-t151);
++
++ t198 = -(-(t197 * 2) - t170);
++ lo[10][slot] = SHIFT(t170);
++ lo[14][slot] = SHIFT(-t198);
++
++ t127 = -(t159 * 2) + t93;
++ hi[11][slot] = SHIFT(t93);
++ t194 = -(t187 * 2) + t159; */
++ lddsp r0/*t159*/, sp[15*4]
++ lddsp r1/*t93*/, sp[7*4]
++ lddsp r3/*t187*/, sp[31*4]
++ sub r5/*t170*/, r2, r6 << 1
++ neg r2
++ scale r2
++ add r4/*t198*/,r5, r4 << 1
++ neg r4
++ scale r5
++ scale r4
++ st.w r12[6*SLOTS*4], r2
++ st.w r12[10*SLOTS*4], r5
++ st.w r12[14*SLOTS*4], r4
++ sub r7/*t127*/, r1, r0 << 1
++ scale r1
++ sub r0/*t194*/, r0, r3 << 1
++ st.w r11[11*SLOTS*4], r1
++
++
++/* Live: r0 = t194, r7 = t127
++ Free: r1, r2, r3, r4, r6, r5, r8, r9, r10, lr */
++
++/* t160 = (t180 * 2) + t127;
++ hi[ 3][slot] = SHIFT(-t127);
++ t195 = -(-(t194 * 2) - t160);
++ lo[ 4][slot] = SHIFT(t160);
++ lo[12][slot] = SHIFT(-t195);
++
++ hi[15][slot] = SHIFT(t191);
++ lo[ 0][slot] = SHIFT(t192); */
++ lddsp r1/*t180*/, sp[23*4]
++ lddsp r2/*t191*/, sp[3*4]
++ lddsp r3/*t192*/, sp[19*4]
++ add r4/*t160*/, r7, r1 << 1
++ neg r7
++ scale r7
++ add r6/*t195*/, r4, r0 << 1
++ scale r4
++ neg r6
++ scale r6
++ st.w r11[3*SLOTS*4], r7
++ st.w r12[4*SLOTS*4], r4
++ st.w r12[12*SLOTS*4], r6
++ scale r2
++ scale r3
++ st.w r11[15*SLOTS*4], r2
++ st.w r12[0*SLOTS*4], r3
++
++ sub sp, -32*4
++ ldm sp++,r0-r7, r9-r11, pc
+diff --git a/fixed.h b/fixed.h
+index 4b58abf..0a1350a 100644
+--- a/fixed.h
++++ b/fixed.h
+@@ -237,6 +237,46 @@ mad_fixed_t mad_f_mul_inline(mad_fixed_t x, mad_fixed_t y)
+ # define MAD_F_SCALEBITS MAD_F_FRACBITS
+ # endif
+
++/* --- AVR32 ----------------------------------------------------------------- */
++
++# elif defined(FPM_AVR32)
++
++typedef signed short mad_coeff_t;
++
++struct DWstruct {int high, low;};
++
++typedef union {
++ struct DWstruct s;
++ long long ll;
++} DWunion;
++
++# define MAD_F_MLX(hi, lo, x, y) \
++ { register DWunion __res; \
++ __res.ll = (long long)x * (long long)y; \
++ /* asm ("muls.d\t%0, %1, %2" : "=r" (__res.ll) : "r" (x), "r" (y));*/ \
++ hi = __res.s.high; \
++ lo = __res.s.low; }
++
++# define MAD_F_MLA(hi, lo, x, y) \
++ { register DWunion __res; \
++ __res.s.high = hi; \
++ __res.s.low = lo; \
++ __res.ll += (long long)x * (long long)y; \
++/* asm ("macs.d\t%0, %1, %2" : "+r" (__res.ll) : "r" (x), "r" (y));*/ \
++ hi = __res.s.high; \
++ lo = __res.s.low; }
++
++
++# define MAD_F_MLN(hi, lo) \
++ asm ("neg %0\n" \
++ "acr %1\n" \
++ "neg %1" \
++ : "+r" (lo), "+r" (hi) \
++ :: "cc")
++
++
++# define MAD_F_SCALEBITS MAD_F_FRACBITS
++
+ /* --- ARM ----------------------------------------------------------------- */
+
+ # elif defined(FPM_ARM)
+@@ -433,6 +473,8 @@ mad_fixed_t mad_f_mul_inline(mad_fixed_t x, mad_fixed_t y)
+ *
+ * Pre-rounding is required to stay within the limits of compliance.
+ */
++typedef signed int mad_coeff_t;
++
+ # if defined(OPT_SPEED)
+ # define mad_f_mul(x, y) (((x) >> 12) * ((y) >> 16))
+ # else
+diff --git a/imdct_avr32.S b/imdct_avr32.S
+new file mode 100644
+index 0000000..d0ee6b4
+--- /dev/null
++++ b/imdct_avr32.S
+@@ -0,0 +1,789 @@
++/*
++ Optimized 36-point Inverse Modified Cosine Transform (IMDCT)
++ Copyright 2003-2006 Atmel Corporation.
++
++ Written by Ronny Pedersen, Atmel Norway
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
++
++#define MAD_F(x) ((x + (1 << 13)) >> 14)
++
++ .public imdct36_avr32
++
++/*
++ void imdct36(mad_fixed_t const x[18], mad_fixed_t y[36])
++ {
++ mad_fixed_t tmp[18];
++ int i;
++*/
++/* DCT-IV */
++imdct36_avr32:
++ pushm r0-r7,r11,lr
++ sub sp, 4*18
++/*
++ {
++ mad_fixed_t tmp2[18];
++ int i;
++
++ /* scale[i] = 2 * cos(PI * (2 * i + 1) / (4 * 18)) */
++/*
++ static mad_fixed_t const scale[18] = {
++ MAD_F(0x1ff833fa), MAD_F(0x1fb9ea93), MAD_F(0x1f3dd120),
++ MAD_F(0x1e84d969), MAD_F(0x1d906bcf), MAD_F(0x1c62648b),
++ MAD_F(0x1afd100f), MAD_F(0x1963268b), MAD_F(0x1797c6a4),
++ MAD_F(0x159e6f5b), MAD_F(0x137af940), MAD_F(0x11318ef3),
++ MAD_F(0x0ec6a507), MAD_F(0x0c3ef153), MAD_F(0x099f61c5),
++ MAD_F(0x06ed12c5), MAD_F(0x042d4544), MAD_F(0x0165547c)
++ };
++*/
++
++ /* scaling */
++
++/*
++ for (i = 0; i < 18; i += 3) {
++ tmp2[i + 0] = mad_f_mul(x[i + 0], scale[i + 0]);
++ tmp2[i + 1] = mad_f_mul(x[i + 1], scale[i + 1]);
++ tmp2[i + 2] = mad_f_mul(x[i + 2], scale[i + 2]);
++ }
++*/
++ /* even input butterfly */
++
++/*
++ for (i = 0; i < 9; i += 3) {
++ tmp3[i + 0] = tmp2[i + 0] + tmp2[18 - (i + 0) - 1];
++ tmp3[i + 1] = tmp2[i + 1] + tmp2[18 - (i + 1) - 1];
++ tmp3[i + 2] = tmp2[i + 2] + tmp2[18 - (i + 2) - 1];
++ }
++ for (i = 0; i < 9; i += 3) {
++ tmp4[i + 0] = tmp2[i + 0] - tmp2[18 - (i + 0) - 1];
++ tmp4[i + 1] = tmp2[i + 1] - tmp2[18 - (i + 1) - 1];
++ tmp4[i + 2] = tmp2[i + 2] - tmp2[18 - (i + 2) - 1];
++ }
++*/
++
++ ld.d r8, r12[0] /*r8 = x[1], r9 = x[0]*/
++ ld.d r0, pc[scale_dctIV - .] /*r0 = {scale[2], scale[3]}, r1 = { scale[0], scale[1] }*/
++ ld.d r2, r12[2*4] /*r2 = x[3], r3 = x[2]*/
++ ld.d r4, pc[scale_dctIV - . + 14*2] /*r4 = {scale[16], scale[17]}, r5 = { scale[14], scale[15] }*/
++ mulsatrndwh.w r9/*tmp2[0]*/, r9, r1:t /*tmp2[0] = mad_f_mul(x[0], scale[0]) */
++ ld.d r6, r12[16*4] /*r6 = x[17], r7 = x[16]*/
++ mulsatrndwh.w r8/*tmp2[1]*/, r8, r1:b /*tmp2[1] = mad_f_mul(x[1], scale[1]) */
++ mulsatrndwh.w r3/*tmp2[2]*/, r3, r0:t /*tmp2[2] = mad_f_mul(x[2], scale[2]) */
++ mulsatrndwh.w r2/*tmp2[3]*/, r2, r0:b /*tmp2[3] = mad_f_mul(x[3], scale[3]) */
++ ld.d r0, r12[14*4] /*r0 = x[15], r1 = x[14]*/
++ mulsatrndwh.w r7/*tmp2[16]*/, r7, r4:t /*tmp2[16] = mad_f_mul(x[16], scale[16]) */
++ mulsatrndwh.w r6/*tmp2[17]*/, r6, r4:b /*tmp2[17] = mad_f_mul(x[17], scale[17]) */
++ mulsatrndwh.w r1/*tmp2[14]*/, r1, r5:t /*tmp2[14] = mad_f_mul(x[14], scale[14]) */
++ mulsatrndwh.w r0/*tmp2[15]*/, r0, r5:b /*tmp2[15] = mad_f_mul(x[15], scale[15]) */
++
++ ld.d r4, r12[4*4] /*r4 = x[5], r5 = x[4]*/
++
++ sub lr/*tmp4[0]*/, r9, r6
++ add r6/*tmp3[0]*/, r9, r6
++ sub r10/*tmp4[1]*/, r8, r7
++ add r7/*tmp3[1]*/, r8, r7
++ sub r9/*tmp4[2]*/, r3, r0
++ add r0/*tmp3[2]*/, r3, r0
++ sub r8/*tmp4[3]*/, r2, r1
++ add r1/*tmp3[3]*/, r2, r1
++
++ ld.d r2, pc[scale_dctIV - . + 4*2] /*r2 = {scale[6], scale[7]}, r3 = { scale[4], scale[5] }*/
++
++ stm --sp, r8-r10, lr /*sp[0] = tmp4[0],sp[1] = tmp4[1],
++ sp[2] = tmp4[2],sp[3] = tmp4[3] */
++
++ /* Registers used: r0 = tmp3[2], r1 = tmp3[3], r6 = tmp3[0], r7 = tmp3[1], r12 = x
++ Free registers: r2-r5, r8-r11, lr
++ */
++ ld.d r8, r12[6*4] /*r8 = x[7], r9 = x[6]*/
++ ld.d r10, pc[scale_dctIV - . + 10*2] /*r10 = {scale[12], scale[13]}, r11 = { scale[10], scale[11] }*/
++ mulsatrndwh.w r5/*tmp2[4]*/, r5, r3:t /*tmp2[4] = mad_f_mul(x[4], scale[4]) */
++ mulsatrndwh.w r4/*tmp2[5]*/, r4, r3:b /*tmp2[5] = mad_f_mul(x[5], scale[5]) */
++ mulsatrndwh.w r9/*tmp2[6]*/, r9, r2:t /*tmp2[6] = mad_f_mul(x[6], scale[6]) */
++ mulsatrndwh.w r8/*tmp2[7]*/, r8, r2:b /*tmp2[7] = mad_f_mul(x[7], scale[7]) */
++
++ ld.d r2, r12[12*4] /*r2 = x[13], r3 = x[12]*/
++ ld.w lr, r12[11*4] /*lr = x[11] */
++ mulsatrndwh.w r3/*tmp2[12]*/, r3, r10:t /*tmp2[12] = mad_f_mul(x[12], scale[12]) */
++ mulsatrndwh.w r2/*tmp2[13]*/, r2, r10:b /*tmp2[13] = mad_f_mul(x[13], scale[13]) */
++ ld.w r10, r12[10*4] /*r10 = x[10] */
++ mulsatrndwh.w lr/*tmp2[11]*/, lr, r11:b /*tmp2[11] = mad_f_mul(x[11], scale[11]) */
++ mulsatrndwh.w r10/*tmp2[10]*/, r10, r11:t /*tmp2[10] = mad_f_mul(x[10], scale[10]) */
++
++ sub r11/*tmp4[4]*/, r5, r2
++ add r2/*tmp3[4]*/, r5, r2
++ sub r5/*tmp4[5]*/, r4, r3
++ add r3/*tmp3[5]*/, r4, r3
++ sub r4/*tmp4[6]*/, r9, lr
++ add lr/*tmp3[6]*/, r9, lr
++ sub r9/*tmp4[7]*/, r8, r10
++ add r10/*tmp3[7]*/, r8, r10
++ lddpc r8, scale_dctIV + 8*2 /*r8 = {scale[8], scale[9]} */
++
++ stm --sp, r4, r5, r9, r11 /*sp[0] = tmp4[4],sp[1] = tmp4[7],
++ sp[2] = tmp4[5],sp[3] = tmp4[6] */
++ ld.d r4, r12[8*4] /*r4 = x[9], r5 = x[8]*/
++ mulsatrndwh.w r5/*tmp2[8]*/, r5, r8:t /*tmp2[8] = mad_f_mul(x[8], scale[8]) */
++ mulsatrndwh.w r4/*tmp2[9]*/, r4, r8:b /*tmp2[9] = mad_f_mul(x[9], scale[9]) */
++ sub r9/*tmp4[8]*/, r5, r4
++ add r5/*tmp3[8]*/, r5, r4
++
++ st.w --sp, r9 /* sp[0] = tmp4[8] */
++
++ /* Registers used:
++
++ r0=tmp3[2], r1=tmp3[3], r2=tmp3[4], r3=tmp3[5], r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r10=tmp3[7], lr=tmp3[6]
++ Free registers:
++ r4, r8, r9, r11, r12
++ */
++
++
++ /* SDCT-II */
++/*
++
++ {
++ mad_fixed_t tmp3[9];
++ int i;
++*/
++ /* scale[i] = 2 * cos(PI * (2 * i + 1) / (2 * 18)) */
++/*
++ static mad_fixed_t const scale[9] = {
++ MAD_F(0x1fe0d3b4), MAD_F(0x1ee8dd47), MAD_F(0x1d007930),
++ MAD_F(0x1a367e59), MAD_F(0x16a09e66), MAD_F(0x125abcf8),
++ MAD_F(0x0d8616bc), MAD_F(0x08483ee1), MAD_F(0x02c9fad7)
++ };
++*/
++ /* divide the 18-point SDCT-II into two 9-point SDCT-IIs */
++
++
++ /* fastdct */
++
++/*
++ {
++ mad_fixed_t a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12;
++ mad_fixed_t a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25;
++ mad_fixed_t m0, m1, m2, m3, m4, m5, m6, m7;
++*/
++// enum {
++// c0 = MAD_F(0x1f838b8d), /* 2 * cos( 1 * PI / 18) */
++// c1 = MAD_F(0x1bb67ae8), /* 2 * cos( 3 * PI / 18) */
++// c2 = MAD_F(0x18836fa3), /* 2 * cos( 4 * PI / 18) */
++// c3 = MAD_F(0x1491b752), /* 2 * cos( 5 * PI / 18) */
++// c4 = MAD_F(0x0af1d43a), /* 2 * cos( 7 * PI / 18) */
++// c5 = MAD_F(0x058e86a0), /* 2 * cos( 8 * PI / 18) */
++// c6 = -MAD_F(0x1e11f642) /* 2 * cos(16 * PI / 18) */
++// };
++
++/*
++ a2 = tmp3[6] + tmp3[2];
++ a6 = tmp3[8] + tmp3[0];
++ a11 = a2 - a6;
++ m5 = mad_f_mul(a11, -c6) ;
++ a4 = tmp3[1] + tmp3[7];
++
++ a18 = tmp3[4] + a4;
++ a19 = -2 * tmp3[4] + a4;
++
++ a0 = tmp3[3] + tmp3[5];
++
++*/
++ add r11/*a4*/, r7, r10
++ add r12/*a18*/, r2, r11
++ sub r11/*a19*/, r11, r2<<1
++
++ add r4/*a2*/, lr, r0
++ add r8/*a6*/, r5, r6
++ sub r9/*a11*/, r4, r8
++
++ st.d --sp, r0 /* sp[0] = tmp3[3], sp1[1] = tmp3[2]*/
++
++ mov r2, MAD_F(0x1e11f642)
++ mulsatrndwh.w r9/*m5*/, r9, r2:b
++
++ add r2/*a0*/, r1, r3
++
++ /* Registers used:
++
++ r2=a0, r3=tmp3[5], r4=a2, r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r8=a6, r10=tmp3[7], r9=m5, r11=a19, r12=a18,lr=tmp3[6]
++ Free registers:
++ r0, r1
++ */
++
++/*
++ a8 = a0 + a2;
++ a12 = a8 + a6;
++ a10 = a0 - a6;
++ a9 = a0 - a2;
++ m7 = mad_f_mul(a9, -c2) ;
++ m6 = mad_f_mul(a10, -c5) ;
++*/
++
++ add r0/*a8*/, r2, r4
++ add r0/*a12*/, r8
++ rsub r8/*a10*/, r2
++ sub r2/*a9*/, r4
++ mov r1, -MAD_F(0x18836fa3)
++ mulsatrndwh.w r2/*m7*/, r2, r1:b
++ mov r1, -MAD_F(0x058e86a0)
++ mulsatrndwh.w r8/*m6*/, r8, r1:b
++
++ /* Registers used:
++
++ r0=a12, r2=m7, r3=tmp3[5], r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r8=m6, r10=tmp3[7], r9=m5, r11=a19, r12=a18,lr=tmp3[6]
++ Free registers:
++ r1, r4
++ */
++
++
++/*
++ a21 = -a19 - (m5 << 1);
++ tmp[ 8] = a21 - (m6 << 1);
++
++ a20 = a19 - (m5 << 1);
++ tmp[ 4] = (m7 << 1) + a20;
++ a22 = -a19 + (m6 << 1);
++ tmp[16] = a22 + (m7 << 1);
++ tmp[ 0] = a18 + a12;
++ tmp[12] = a12 - 2 * a18;
++*/
++ add r1/*a21*/, r11, r9 << 1
++ neg r1
++ sub r1/*tmp[8]*/, r1, r8 << 1
++ stdsp sp[4*11/*tmp3[..] on the stack*/ + 8*4], r1
++ sub r4/*a20*/, r11, r9 << 1
++ add r4/*tmp[4]*/, r4, r2 << 1
++ stdsp sp[4*11/*tmp3[..] on the stack*/ + 4*4], r4
++ neg r11
++ add r1/*a22*/, r11, r8 << 1
++ add r1/*tmp[16]*/, r1, r2 << 1
++ stdsp sp[4*11/*tmp3[..] on the stack*/ + 16*4], r1
++ add r4, r12, r0
++ sub r1, r0, r12 << 1
++ stdsp sp[4*11/*tmp3[..] on the stack*/ + 0*4], r4
++ stdsp sp[4*11/*tmp3[..] on the stack*/ + 12*4], r1
++
++ ld.d r0, sp++
++
++ /* Registers used:
++
++ r0 = tmp3[2], r1 = tmp3[3], r3=tmp3[5], r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r10=tmp3[7], r11=a19, lr=tmp3[6]
++ Free registers:
++ r2,r4,r8,r9,r12
++ */
++
++/*
++ a5 = tmp3[1] - tmp3[7];
++ a7 = tmp3[8] - tmp3[0];
++ a3 = tmp3[6] - tmp3[2];
++ a1 = tmp3[3] - tmp3[5];
++ a13 = a1 - a3;
++ a14 = a13 + a7;
++ m3 = mad_f_mul(a14, -c1) ;
++ m4 = mad_f_mul(a5, -c1) ;
++ tmp[ 6] = m3 << 1;
++*/
++ sub r7/*a5*/, r10
++ sub r2/*a7*/, r5, r6
++ sub r4/*a3*/, lr, r0
++ sub r8/*a1*/, r1, r3
++ sub r9/*a13*/, r8, r4
++ add r12/*a14*/, r9, r2
++ mov r0, -MAD_F(0x1bb67ae8)
++ mulsatrndwh.w r12/*m3*/, r12, r0:b
++ mulsatrndwh.w r7/*m4*/, r7, r0:b
++ lsl r12, 1
++ stdsp sp[4*9/*tmp3[..] on the stack*/ + 6*4], r12
++
++ /* Registers used:
++ r2 = a7, r4 = a3, r7 = m4, r8 = a1, r12 = m3
++
++ Free registers:
++ r0, r1, r3, r5, r6, r10, r9, r11, lr
++ */
++
++
++/*
++ a15 = a3 + a7;
++ m2 = mad_f_mul(a15, -c4) ;
++ a17 = a1 + a3;
++ m0 = mad_f_mul(a17, -c3) ;
++ a23 = (m4 << 1) + (m2 << 1);
++ tmp[14] = a23 + (m0 << 1); */
++ add r0/*a15*/, r4, r2
++ mov r1, -MAD_F(0x0af1d43a)
++ mulsatrndwh.w r0/*m2*/, r0, r1:b
++ mov r3, -MAD_F(0x1491b752)
++ add r5/*a17*/, r8, r4
++ mulsatrndwh.w r5/*m0*/, r5, r3:b
++ lsl r7, 1
++ add r6/*a23*/, r7, r0 << 1
++ add r6/*tmp[14]*/, r6, r5 << 1
++ stdsp sp[4*9/*tmp3[..] on the stack*/ + 14*4], r6
++
++ /* Registers used:
++ r0 = m2, r2 = a7, r5 = m0, r7 = m4, r8 = a1
++
++ Free registers:
++ r1, r3, r4, r6, r10, r9, r11, lr
++ */
++
++/*
++ a16 = a1 - a7;
++ m1 = mad_f_mul(a16, -c0) ;
++ a24 = (m4 << 1) - (m2 << 1);
++ tmp[10] = a24 - (m1 << 1);
++
++ a25 = (m4 << 1) + (m1 << 1);
++ tmp[ 2] = (m0 << 1) - a25;
++*/
++ sub r3/*a16*/, r8, r2
++ mov r4, -MAD_F(0x1f838b8d)
++ mulsatrndwh.w r3/*m1*/, r3, r4:b
++ sub r1/*a24*/, r7, r0 << 1
++ sub r1/*tmp[10]*/, r1, r3 << 1
++ stdsp sp[4*9/*tmp3[..] on the stack*/ + 10*4], r1
++ add r7/*a25*/, r7, r3 << 1
++ sub r7, r7, r5 << 1
++ neg r7
++ stdsp sp[4*9/*tmp3[..] on the stack*/ + 2*4], r7
++
++
++
++
++ /* output to every other slot for convenience */
++
++ /*} */
++ /* End fastdct */
++
++ /* odd input butterfly and scaling */
++
++
++ /* On the stack:
++ sp[0] = tmp4[8], sp[1] = tmp4[4],sp[2] = tmp4[7], sp[3] = tmp4[5],sp[4] = tmp4[6]
++ sp[5] = tmp4[0], sp[6] = tmp4[1],sp[7] = tmp4[2],sp[8] = tmp4[3]
++ */
++
++ /*
++ tmp3[0] = mad_f_mul(tmp4[0], scale[0]);
++ tmp3[1] = mad_f_mul(tmp4[1], scale[1]) << 1;
++ tmp3[2] = mad_f_mul(tmp4[2], scale[2]);
++ tmp3[3] = mad_f_mul(tmp4[3], scale[3]) << 1;
++ tmp3[4] = mad_f_mul(tmp4[4], scale[4]);
++ tmp3[5] = mad_f_mul(tmp4[5], scale[5]);
++ tmp3[6] = mad_f_mul(tmp4[6], scale[6]) << 1;
++ tmp3[7] = mad_f_mul(tmp4[7], scale[7]);
++ tmp3[8] = mad_f_mul(tmp4[8], scale[8]) << 1;
++ */
++ /* Registers used:
++ r1 = tmp4[3], r2 = tmp4[2], r3 = tmp4[1], r4 = tmp4[0], r7 = tmp4[6]
++ r10 = tmp4[5], r11 = tmp4[7], r12 = tmp4[4], lr = tmp4[8]
++
++ Free registers:
++ r0, r5, r6, r8, r9
++ */
++ ld.d r8, pc[ scale_sdctII - . + 4*2] /* r8 = { scale[6], scale[7] }, r9 = { scale[4], scale[5]} */
++ ldm sp++, r1, r2, r3, r4, r7, r10, r11, r12, lr
++ mov r5, MAD_F(0x02c9fad7) /* r3 = scale[8] */
++ mulsatrndwh.w r5/*tmp3[8]*/, lr, r5:b
++ mulsatrndwh.w lr/*tmp3[6]*/, r7, r8:t
++ ld.d r6, pc[ scale_sdctII - . + 0*2] /* r6 = { scale[2], scale[3] }, r7 = { scale[0], scale[1]} */
++ lsl lr, 1
++ lsl r5, 1
++ mulsatrndwh.w r0/*tmp3[2]*/, r2, r6:t
++ mulsatrndwh.w r1/*tmp3[3]*/, r1, r6:b
++ mulsatrndwh.w r6/*tmp3[0]*/, r4, r7:t
++ mulsatrndwh.w r7/*tmp3[1]*/, r3, r7:b
++ mulsatrndwh.w r3/*tmp3[5]*/, r10, r9:b
++ mulsatrndwh.w r2/*tmp3[4]*/, r12, r9:t
++ mulsatrndwh.w r9/*tmp3[7]*/, r11, r8:b
++ lsl r1, 1
++ lsl r7, 1
++
++
++ /* fastdct */
++
++/*
++ {
++ mad_fixed_t a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12;
++ mad_fixed_t a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25;
++ mad_fixed_t m0, m1, m2, m3, m4, m5, m6, m7;
++*/
++// enum {
++// c0 = MAD_F(0x1f838b8d), /* 2 * cos( 1 * PI / 18) */
++// c1 = MAD_F(0x1bb67ae8), /* 2 * cos( 3 * PI / 18) */
++// c2 = MAD_F(0x18836fa3), /* 2 * cos( 4 * PI / 18) */
++// c3 = MAD_F(0x1491b752), /* 2 * cos( 5 * PI / 18) */
++// c4 = MAD_F(0x0af1d43a), /* 2 * cos( 7 * PI / 18) */
++// c5 = MAD_F(0x058e86a0), /* 2 * cos( 8 * PI / 18) */
++// c6 = -MAD_F(0x1e11f642) /* 2 * cos(16 * PI / 18) */
++// };
++
++ /* Registers used:
++
++ r0=tmp3[2], r1=tmp3[3], r2=tmp3[4], r3=tmp3[5], r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r9=tmp3[7], lr=tmp3[6]
++ Free registers:
++ r4, r8, r10, r11, r12
++ */
++
++/*
++ a2 = tmp3[6] + (tmp3[2] << 1);
++ a6 = tmp3[8] + (tmp3[0] << 1);
++ a11 = a2 - a6;
++ m5 = mad_f_mul(a11, c6) ;
++ a4 = tmp3[1] + (tmp3[7] << 1);
++
++ a18 = (tmp3[4] << 1) + a4;
++ a19 = -2 * (tmp3[4] << 1) + a4;
++
++ a0 = tmp3[3] + (tmp3[5] << 1);
++
++*/
++ add r11/*a4*/, r7, r9 << 1
++ add r12/*a18*/, r11, r2 << 1
++ sub r11/*a19*/, r11, r2 << 2
++
++ add r4/*a2*/, lr, r0 << 1
++ add r8/*a6*/, r5, r6 << 1
++ sub r10/*a11*/, r4, r8
++
++ st.d --sp, r0 /* sp[0] = tmp3[3], sp1[1] = tmp3[2]*/
++
++ mov r2, -MAD_F(0x1e11f642)
++ mulsatrndwh.w r10/*m5*/, r10, r2:b
++
++ add r2/*a0*/, r1, r3 << 1
++
++ /* Registers used:
++
++ r2=a0, r3=tmp3[5], r4=a2, r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r8=a6, r9=tmp3[7], r10=m5, r11=a19, r12=a18,lr=tmp3[6]
++ Free registers:
++ r0, r1
++ */
++
++/*
++ a8 = a0 + a2;
++ a12 = a8 + a6;
++ a10 = a0 - a6;
++ a9 = a0 - a2;
++ m7 = mad_f_mul(a9, -c2) ;
++ m6 = mad_f_mul(a10, -c5) ;
++*/
++
++ add r0/*a8*/, r2, r4
++ add r0/*a12*/, r8
++ rsub r8/*a10*/, r2
++ sub r2/*a9*/, r4
++ mov r1, -MAD_F(0x18836fa3)
++ mulsatrndwh.w r2/*m7*/, r2, r1:b
++ mov r1, -MAD_F(0x058e86a0)
++ mulsatrndwh.w r8/*m6*/, r8, r1:b
++
++ /* Registers used:
++
++ r0=a12, r2=m7, r3=tmp3[5], r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r8=m6, r9=tmp3[7], r10=m5, r11=a19, r12=a18,lr=tmp3[6]
++ Free registers:
++ r1, r4
++ */
++
++
++/*
++ a21 = -a19 + (m5 << 1);
++ tmp[ 9] = a21 - (m6 << 1);
++
++ a20 = -(-a19 - (m5 << 1));
++ tmp[ 5] = (m7 << 1) + a20;
++ a22 = -a19 + (m6 << 1);
++ tmp[17] = a22 + (m7 << 1);
++ tmp[ 1] = a18 + a12;
++ tmp[13] = a12 - 2 * a18;
++*/
++ sub r1/*a21*/, r11, r10 << 1
++ neg r1
++ sub r1/*tmp[9]*/, r1, r8 << 1
++ stdsp sp[4*2/*tmp3[..] on the stack*/ + 9*4], r1
++ add r4/*a20*/, r11, r10 << 1
++ add r4/*tmp[5]*/, r4, r2 << 1
++ stdsp sp[4*2/*tmp3[..] on the stack*/ + 5*4], r4
++ neg r11
++ add r1/*a22*/, r11, r8 << 1
++ add r1/*tmp[17]*/, r1, r2 << 1
++ stdsp sp[4*2/*tmp3[..] on the stack*/ + 17*4], r1
++ add r4, r12, r0
++ sub r1, r0, r12 << 1
++ stdsp sp[4*2/*tmp3[..] on the stack*/ + 1*4], r4
++ stdsp sp[4*2/*tmp3[..] on the stack*/ + 13*4], r1
++
++ ld.d r0, sp++
++
++ /* Registers used:
++
++ r0 = tmp3[2], r1 = tmp3[3], r3=tmp3[5], r5=tmp3[8], r6 = tmp3[0],
++ r7 = tmp3[1], r9=tmp3[7], r11=a19, lr=tmp3[6]
++ Free registers:
++ r2,r4,r8,r10,r12
++ */
++
++/*
++ a5 = tmp3[1] - (tmp3[7] << 1);
++ a7 = tmp3[8] - (tmp3[0] << 1);
++ a3 = tmp3[6] - (tmp3[2] << 1);
++ a1 = tmp3[3] - (tmp3[5] << 1);
++ a13 = a1 - a3;
++ a14 = a13 + a7;
++ m3 = mad_f_mul(a14, -c1) ;
++ m4 = mad_f_mul(a5, -c1) ;
++ tmp[ 7] = m3 << 1;
++*/
++ sub r7/*a5*/, r7, r9 << 1
++ sub r2/*a7*/, r5, r6 << 1
++ sub r4/*a3*/, lr, r0 << 1
++ sub r8/*a1*/, r1, r3 << 1
++ sub r10/*a13*/, r8, r4
++ add r12/*a14*/, r10, r2
++ mov r0, -MAD_F(0x1bb67ae8)
++ mulsatrndwh.w r12/*m3*/, r12, r0:b
++ mulsatrndwh.w r7/*m4*/, r7, r0:b
++ lsl r12, 1
++ stdsp sp[7*4], r12
++
++ /* Registers used:
++ r2 = a7, r4 = a3, r7 = m4, r8 = a1, r12 = m3
++
++ Free registers:
++ r0, r1, r3, r5, r6, r9, r10, r11, lr
++ */
++
++
++/*
++ a15 = a3 + a7;
++ m2 = mad_f_mul(a15, -c4) ;
++ a17 = a1 + a3;
++ m0 = mad_f_mul(a17, -c3) ;
++ a23 = (m4 << 1) + (m2 << 1);
++ tmp[15] = a23 + (m0 << 1); */
++ add r0/*a15*/, r4, r2
++ mov r1, -MAD_F(0x0af1d43a)
++ mulsatrndwh.w r0/*m2*/, r0, r1:b
++ mov r3, -MAD_F(0x1491b752)
++ add r5/*a17*/, r8, r4
++ mulsatrndwh.w r5/*m0*/, r5, r3:b
++ lsl r7, 1
++ add r6/*a23*/, r7, r0 << 1
++ add r6/*tmp[15]*/, r6, r5 << 1
++ stdsp sp[15*4], r6
++
++ /* Registers used:
++ r0 = m2, r2 = a7, r5 = m0, r7 = m4, r8 = a1
++
++ Free registers:
++ r1, r3, r4, r6, r9, r10, r11, lr
++ */
++
++/*
++ a16 = a1 - a7;
++ m1 = mad_f_mul(a16, -c0) ;
++ a24 = (m4 << 1) - (m2 << 1);
++ tmp[11] = a24 - (m1 << 1);
++
++ a25 = (m4 << 1) + (m1 << 1);
++ tmp[ 3] = (m0 << 1) - a25;
++*/
++ sub r3/*a16*/, r8, r2
++ mov r4, -MAD_F(0x1f838b8d)
++ mulsatrndwh.w r3/*m1*/, r3, r4:b
++ sub r1/*a24*/, r7, r0 << 1
++ sub r1/*tmp[11]*/, r1, r3 << 1
++ stdsp sp[11*4], r1
++ add r7/*a25*/, r7, r3 << 1
++ sub r7, r7, r5 << 1
++ neg r7
++ lddsp r12, sp[4*18+4] /* Get y from stack */
++ stdsp sp[3*4], r7
++
++
++ /* output to every other slot for convenience */
++
++ /* End fastdct */
++
++ /* output accumulation */
++
++/* for (i = 3; i < 18; i += 8) {
++ tmp[i + 0] -= tmp[(i + 0) - 2];
++ tmp[i + 2] -= tmp[(i + 2) - 2];
++ tmp[i + 4] -= tmp[(i + 4) - 2];
++ tmp[i + 6] -= tmp[(i + 6) - 2];
++ }
++ }
++*/
++
++/* End SDCT-II */
++
++
++
++ /* scale reduction and output accumulation */
++
++/*
++ for (i = 1; i < 17; i += 4) {
++ tmp[i + 0] = tmp[i + 0] - tmp[(i + 0) - 1];
++ tmp[i + 1] = tmp[i + 1] - tmp[(i + 1) - 1];
++ tmp[i + 2] = tmp[i + 2] - tmp[(i + 2) - 1];
++ tmp[i + 3] = tmp[i + 3] - tmp[(i + 3) - 1];
++ }
++ tmp[17] = tmp[17] - tmp[16];
++ }
++*/
++/* End DCT-IV */
++
++
++ /* convert 18-point DCT-IV to 36-point IMDCT */
++
++/*
++ for (i = 0; i < 9; i += 3) {
++ y[i + 0] = tmp[9 + (i + 0)];
++ y[i + 1] = tmp[9 + (i + 1)];
++ y[i + 2] = tmp[9 + (i + 2)];
++ }
++ for (i = 9; i < 27; i += 3) {
++ y[i + 0] = -tmp[36 - (9 + (i + 0)) - 1];
++ y[i + 1] = -tmp[36 - (9 + (i + 1)) - 1];
++ y[i + 2] = -tmp[36 - (9 + (i + 2)) - 1];
++ }
++ for (i = 27; i < 36; i += 3) {
++ y[i + 0] = -tmp[(i + 0) - 27];
++ y[i + 1] = -tmp[(i + 1) - 27];
++ y[i + 2] = -tmp[(i + 2) - 27];
++ }
++ }
++*/
++
++ /* Registers used:
++ r0 = tmp[8], r1 = tmp[7], r2 = tmp[6], r3 = tmp[5], r4 = tmp[4]
++ r5 = tmp[3], r6 = tmp[2], r7 = tmp[1], r8 = tmp[0], r12 = y
++
++ Free registers:
++ r9, r10, r11, lr
++ */
++
++ ldm sp++, r0-r8 /* Get tmp[0]-tmp[8] from stack */
++ sub r5, r7 /* tmp[3] -= tmp[1]*/
++ sub r3, r5 /* tmp[5] -= tmp[3]*/
++ sub r1, r3 /* tmp[7] -= tmp[5]*/
++
++ sub r7, r8 /* tmp[1] -= tmp[0]*/
++ sub r6, r7 /* tmp[2] -= tmp[1]*/
++ sub r5, r6 /* tmp[3] -= tmp[2]*/
++ neg r8
++ st.w r12[26*4], r8 /* y[26] = -tmp[0] */
++ st.w r12[27*4], r8 /* y[27] = -tmp[0] */
++ neg r7
++ neg r6
++ st.w r12[25*4], r7 /* y[25] = -tmp[1] */
++ st.w r12[24*4], r6 /* y[24] = -tmp[2] */
++ st.d r12[28*4], r6 /* y[28] = -tmp[1], y[29] = -tmp[2]*/
++
++ sub r4, r5 /* tmp[4] -= tmp[3]*/
++ sub r3, r4 /* tmp[5] -= tmp[4]*/
++ neg r5
++ neg r4
++ st.w r12[23*4], r5 /* y[23] = -tmp[3] */
++ st.w r12[22*4], r4 /* y[22] = -tmp[4] */
++ st.d r12[30*4], r4 /* y[30] = -tmp[3], y[31] = -tmp[4]*/
++
++ ldm sp++, r4-r11,lr /* Get tmp[9]-tmp[17] from stack */
++
++ sub r2, r3 /* tmp[6] -= tmp[5]*/
++
++ sub lr, r1 /* tmp[9] -= tmp[7]*/
++ sub r10, lr /* tmp[11] -= tmp[9]*/
++ sub r8, r10 /* tmp[13] -= tmp[11]*/
++ sub r6, r8 /* tmp[15] -= tmp[13]*/
++ sub r4, r6 /* tmp[17] -= tmp[15]*/
++
++ sub r1, r2 /* tmp[7] -= tmp[6]*/
++ sub r0, r1 /* tmp[8] -= tmp[7]*/
++ neg r3
++ neg r2
++ st.w r12[21*4], r3 /* y[21] = -tmp[5] */
++ st.w r12[20*4], r2 /* y[20] = -tmp[6] */
++ st.d r12[32*4], r2 /* y[32] = -tmp[5], y[33] = -tmp[6]*/
++
++ sub lr, r0 /* tmp[9] -= tmp[8]*/
++ sub r11, lr /* tmp[10] -= tmp[9]*/
++ neg r1
++ neg r0
++ st.w r12[19*4], r1 /* y[19] = -tmp[7] */
++ st.w r12[18*4], r0 /* y[18] = -tmp[8] */
++ st.d r12[34*4], r0 /* y[34] = -tmp[7], y[35] = -tmp[8]*/
++
++ sub r10, r11 /* tmp[11] -= tmp[10]*/
++ sub r9, r10 /* tmp[12] -= tmp[11]*/
++
++ st.w r12[0*4], lr /* y[0] = tmp[9]*/
++ neg lr
++ st.w r12[17*4], lr /* y[17] = -tmp[9]*/
++ st.d r12[1*4], r10 /* y[1] = tmp[10], y[2] = tmp[11] */
++ neg r11
++ neg r10
++ st.w r12[16*4], r11 /* y[16] = -tmp[10] */
++ st.w r12[15*4], r10 /* y[15] = -tmp[11] */
++
++
++ sub r8, r9 /* tmp[13] -= tmp[12]*/
++ sub r7, r8 /* tmp[14] -= tmp[13]*/
++ st.d r12[3*4], r8 /* y[3] = tmp[12], y[4] = tmp[13] */
++ neg r9
++ neg r8
++ st.w r12[14*4], r9 /* y[14] = -tmp[12] */
++ st.w r12[13*4], r8 /* y[13] = -tmp[13] */
++
++ sub r6, r7 /* tmp[15] -= tmp[14]*/
++ sub r5, r6 /* tmp[16] -= tmp[15]*/
++ sub r4, r5 /* tmp[17] -= tmp[16]*/
++
++ st.d r12[5*4], r6 /* y[5] = tmp[14], y[6] = tmp[15] */
++ neg r7
++ neg r6
++ st.w r12[12*4], r7 /* y[12] = -tmp[14] */
++ st.w r12[11*4], r6 /* y[11] = -tmp[15] */
++
++ st.d r12[7*4], r4 /* y[7] = tmp[16], y[8] = tmp[17] */
++ neg r5
++ neg r4
++ st.w r12[10*4], r5 /* y[10] = -tmp[16] */
++ st.w r12[9*4], r4 /* y[9] = -tmp[17] */
++
++ popm r0-r7,r11,pc
++
++ .align 2
++scale_dctIV:
++ .short MAD_F(0x1ff833fa), MAD_F(0x1fb9ea93), MAD_F(0x1f3dd120)
++ .short MAD_F(0x1e84d969), MAD_F(0x1d906bcf), MAD_F(0x1c62648b)
++ .short MAD_F(0x1afd100f), MAD_F(0x1963268b), MAD_F(0x1797c6a4)
++ .short MAD_F(0x159e6f5b), MAD_F(0x137af940), MAD_F(0x11318ef3)
++ .short MAD_F(0x0ec6a507), MAD_F(0x0c3ef153), MAD_F(0x099f61c5)
++ .short MAD_F(0x06ed12c5), MAD_F(0x042d4544), MAD_F(0x0165547c)
++
++ .align 2
++scale_sdctII:
++ .short MAD_F(0x1fe0d3b4), MAD_F(0x1ee8dd47), MAD_F(0x1d007930)
++ .short MAD_F(0x1a367e59), MAD_F(0x16a09e66), MAD_F(0x125abcf8)
++ .short MAD_F(0x0d8616bc), MAD_F(0x08483ee1), MAD_F(0x02c9fad7)
+diff --git a/layer3.c b/layer3.c
+index 4e5d3fa..dffdab3 100644
+--- a/layer3.c
++++ b/layer3.c
+@@ -378,6 +378,11 @@ mad_fixed_t const ca[8] = {
+ -MAD_F(0x003a2847) /* -0.014198569 */, -MAD_F(0x000f27b4) /* -0.003699975 */
+ };
+
++#ifdef FPM_AVR32
++# undef MAD_F
++# define MAD_F(x) ((x + (1 << 12)) >> 13)
++#endif
++
+ /*
+ * IMDCT coefficients for short blocks
+ * derived from section 2.4.3.4.10.2 of ISO/IEC 11172-3
+@@ -386,7 +391,7 @@ mad_fixed_t const ca[8] = {
+ * imdct_s[i /odd][k] = cos((PI / 24) * (2 * (6 + (i-1)/2) + 7) * (2 * k + 1))
+ */
+ static
+-mad_fixed_t const imdct_s[6][6] = {
++mad_coeff_t const imdct_s[6][6] = {
+ # include "imdct_s.dat"
+ };
+
+@@ -398,7 +403,7 @@ mad_fixed_t const imdct_s[6][6] = {
+ * window_l[i] = sin((PI / 36) * (i + 1/2))
+ */
+ static
+-mad_fixed_t const window_l[36] = {
++mad_coeff_t const window_l[36] = {
+ MAD_F(0x00b2aa3e) /* 0.043619387 */, MAD_F(0x0216a2a2) /* 0.130526192 */,
+ MAD_F(0x03768962) /* 0.216439614 */, MAD_F(0x04cfb0e2) /* 0.300705800 */,
+ MAD_F(0x061f78aa) /* 0.382683432 */, MAD_F(0x07635284) /* 0.461748613 */,
+@@ -429,7 +434,7 @@ mad_fixed_t const window_l[36] = {
+ * window_s[i] = sin((PI / 12) * (i + 1/2))
+ */
+ static
+-mad_fixed_t const window_s[12] = {
++mad_coeff_t const window_s[12] = {
+ MAD_F(0x0216a2a2) /* 0.130526192 */, MAD_F(0x061f78aa) /* 0.382683432 */,
+ MAD_F(0x09bd7ca0) /* 0.608761429 */, MAD_F(0x0cb19346) /* 0.793353340 */,
+ MAD_F(0x0ec835e8) /* 0.923879533 */, MAD_F(0x0fdcf549) /* 0.991444861 */,
+@@ -438,6 +443,11 @@ mad_fixed_t const window_s[12] = {
+ MAD_F(0x061f78aa) /* 0.382683432 */, MAD_F(0x0216a2a2) /* 0.130526192 */,
+ };
+
++#ifdef FPM_AVR32
++# undef MAD_F
++# define MAD_F(x) ((mad_fixed_t) (x##L))
++#endif
++
+ /*
+ * coefficients for intensity stereo processing
+ * derived from section 2.4.3.4.9.3 of ISO/IEC 11172-3
+@@ -879,6 +889,42 @@ void III_exponents(struct channel const *channel,
+ * NAME: III_requantize()
+ * DESCRIPTION: requantize one (positive) value
+ */
++
++#if 0
++/*static*/
++mad_fixed_t III_requantize(unsigned int value, signed int exp)
++{
++ register mad_fixed_t tmp2, tmp3;
++ long long tmp_d;
++
++ asm ("asr\t%0, %1, 2\n"
++ "ld.w\t%2, %4[%5 << 2]\n"
++ "sub\t%1, %1, %0 << 2\n"
++ "asr\t%3, %2, 7\n"
++ "andl\t%2, 0x7f, COH\n"
++ "add\t%0, %2\n"
++ "lsl\t%m0,%3,%0\n"
++ "neg\t%0\n"
++ "asr\t%3,%3,%0\n"
++ "add\t%2, %6, %1 << 2\n"
++ "ld.w\t%2, %2[12]\n"
++ "cp.w\t%0, 0\n"
++ "movlt\t%3, %m0\n"
++ "muls.d\t%0, %3, %2\n"
++ "cp.w\t%1, 0\n"
++ "breq\t0f\n"
++ "lsr\t%0, %0, 28\n"
++ "or\t%3, %0, %m0 << 4\n"
++ "0:\n"
++ : "=&r"(tmp_d), "+r"(exp), "=&r"(tmp2), "=&r"(tmp3)
++ : "r"(&rq_table), "r"(value), "r"(root_table));
++
++
++ return tmp3;
++}
++
++#else
++
+ static
+ mad_fixed_t III_requantize(unsigned int value, signed int exp)
+ {
+@@ -918,6 +964,7 @@ mad_fixed_t III_requantize(unsigned int value, signed int exp)
+
+ return frac ? mad_f_mul(requantized, root_table[3 + frac]) : requantized;
+ }
++#endif
+
+ /* we must take care that sz >= bits and sz < sizeof(long) lest bits == 0 */
+ # define MASK(cache, sz, bits) \
+@@ -2054,27 +2101,42 @@ void imdct36(mad_fixed_t const X[18], mad_fixed_t x[36])
+ }
+ # endif
+
++
++#ifdef FPM_AVR32
++# undef mad_f_mul
++# define mad_f_mul(x, y) __builtin_mulsatrndwh_w(x, y)
++#endif
++
+ /*
+ * NAME: III_imdct_l()
+ * DESCRIPTION: perform IMDCT and windowing for long blocks
+ */
+ static
+-void III_imdct_l(mad_fixed_t const X[18], mad_fixed_t z[36],
++void III_imdct_l(mad_fixed_t /*const*/ X[18], mad_fixed_t z[36],
+ unsigned int block_type)
+ {
+ unsigned int i;
++ mad_fixed_t *z_ptr;
++ mad_coeff_t *w_ptr;
+
+ /* IMDCT */
+
++#ifdef FPM_AVR32
++ imdct36_avr32(X, z);
++#else
+ imdct36(X, z);
++#endif
+
+ /* windowing */
+
++ z_ptr = &z[0];
++ w_ptr = &window_l[0];
++
+ switch (block_type) {
+ case 0: /* normal window */
+ # if defined(ASO_INTERLEAVE1)
+ {
+- register mad_fixed_t tmp1, tmp2;
++ register mad_coeff_t tmp1, tmp2;
+
+ tmp1 = window_l[0];
+ tmp2 = window_l[1];
+@@ -2091,15 +2153,16 @@ void III_imdct_l(mad_fixed_t const X[18], mad_fixed_t z[36],
+ }
+ # elif defined(ASO_INTERLEAVE2)
+ {
+- register mad_fixed_t tmp1, tmp2;
++ register mad_fixed_t tmp1;
++ register mad_coeff_t tmp2;
+
+- tmp1 = z[0];
+- tmp2 = window_l[0];
++ tmp1 = *z_ptr;
++ tmp2 = *w_ptr++;
+
+ for (i = 0; i < 35; ++i) {
+- z[i] = mad_f_mul(tmp1, tmp2);
+- tmp1 = z[i + 1];
+- tmp2 = window_l[i + 1];
++ *z_ptr++ = mad_f_mul(tmp1, tmp2);
++ tmp1 = *z_ptr;
++ tmp2 = *w_ptr++;
+ }
+
+ z[35] = mad_f_mul(tmp1, tmp2);
+@@ -2118,23 +2181,28 @@ void III_imdct_l(mad_fixed_t const X[18], mad_fixed_t z[36],
+
+ case 1: /* start block */
+ for (i = 0; i < 18; i += 3) {
+- z[i + 0] = mad_f_mul(z[i + 0], window_l[i + 0]);
+- z[i + 1] = mad_f_mul(z[i + 1], window_l[i + 1]);
+- z[i + 2] = mad_f_mul(z[i + 2], window_l[i + 2]);
++ *(z_ptr++) = mad_f_mul(*z_ptr, *w_ptr++);
++ *(z_ptr++) = mad_f_mul(*z_ptr, *w_ptr++);
++ *(z_ptr++) = mad_f_mul(*z_ptr, *w_ptr++);
+ }
++ z_ptr += 6;
++ w_ptr = &window_s[6];
+ /* (i = 18; i < 24; ++i) z[i] unchanged */
+- for (i = 24; i < 30; ++i) z[i] = mad_f_mul(z[i], window_s[i - 18]);
+- for (i = 30; i < 36; ++i) z[i] = 0;
++ for (i = 24; i < 30; ++i) *z_ptr++ = mad_f_mul(*z_ptr, *w_ptr++);
++ for (i = 30; i < 36; ++i) *z_ptr++ = 0;
+ break;
+
+ case 3: /* stop block */
+- for (i = 0; i < 6; ++i) z[i] = 0;
+- for (i = 6; i < 12; ++i) z[i] = mad_f_mul(z[i], window_s[i - 6]);
++ w_ptr = &window_s[0];
++ for (i = 0; i < 6; ++i) *z_ptr++ = 0;
++ for (i = 6; i < 12; ++i) *z_ptr++ = mad_f_mul(*z_ptr, *w_ptr++);
+ /* (i = 12; i < 18; ++i) z[i] unchanged */
++ w_ptr = &window_l[18];
++ z_ptr += 6;
+ for (i = 18; i < 36; i += 3) {
+- z[i + 0] = mad_f_mul(z[i + 0], window_l[i + 0]);
+- z[i + 1] = mad_f_mul(z[i + 1], window_l[i + 1]);
+- z[i + 2] = mad_f_mul(z[i + 2], window_l[i + 2]);
++ *z_ptr++ = mad_f_mul(*z_ptr, *w_ptr++ );
++ *z_ptr++ = mad_f_mul(*z_ptr, *w_ptr++);
++ *z_ptr++ = mad_f_mul(*z_ptr, *w_ptr++);
+ }
+ break;
+ }
+@@ -2146,10 +2214,10 @@ void III_imdct_l(mad_fixed_t const X[18], mad_fixed_t z[36],
+ * DESCRIPTION: perform IMDCT and windowing for short blocks
+ */
+ static
+-void III_imdct_s(mad_fixed_t const X[18], mad_fixed_t z[36])
++void III_imdct_s(mad_fixed_t /*const*/ X[18], mad_fixed_t z[36])
+ {
+ mad_fixed_t y[36], *yptr;
+- mad_fixed_t const *wptr;
++ mad_coeff_t const *wptr;
+ int w, i;
+ register mad_fixed64hi_t hi;
+ register mad_fixed64lo_t lo;
+@@ -2159,11 +2227,56 @@ void III_imdct_s(mad_fixed_t const X[18], mad_fixed_t z[36])
+ yptr = &y[0];
+
+ for (w = 0; w < 3; ++w) {
+- register mad_fixed_t const (*s)[6];
++ register mad_coeff_t const (*s)[6];
+
+ s = imdct_s;
+
+ for (i = 0; i < 3; ++i) {
++#ifdef FPM_AVR32
++ register long long int acc, tmp1, tmp2, tmp3, tmp4;
++ asm volatile ("ld.d\t%0, %5++\n"
++ "ld.d\t%1, %6[0]\n"
++ "ld.d\t%2, %6[2*4]\n"
++ "ld.d\t%3, %6[4*4]\n"
++ "mulwh.d\t%4, %m1, %m0:t\n"
++ "macwh.d\t%4, %1, %m0:b\n"
++ "ld.w\t%m0, %5++\n"
++ "macwh.d\t%4, %m2, %0:t\n"
++ "macwh.d\t%4, %2, %0:b\n"
++ "macwh.d\t%4, %m3, %m0:t\n"
++ "macwh.d\t%4, %3, %m0:b\n"
++ "ld.d\t%0, %5++\n"
++ "rol\t%4\n"
++ "rol\t%m4\n"
++ : "=&r"(tmp1), "=&r"(tmp2), "=&r"(tmp3), "=&r"(tmp4),
++ "=&r"(acc), "+r"(s)
++ : "r"(X));
++
++ asm volatile ("st.w\t%1[0], %m0\n"
++ "neg\t%m0\n"
++ "st.w\t%2[5*4], %m0\n"
++ : "+r"(acc)
++ : "r"(&yptr[i]), "r"(&yptr[-i]));
++
++ asm volatile ("mulwh.d\t%4, %m1, %m0:t\n"
++ "macwh.d\t%4, %1, %m0:b\n"
++ "ld.w\t%m0, %5++\n"
++ "macwh.d\t%4, %m2, %0:t\n"
++ "macwh.d\t%4, %2, %0:b\n"
++ "macwh.d\t%4, %m3, %m0:t\n"
++ "macwh.d\t%4, %3, %m0:b\n"
++ "rol\t%4\n"
++ "rol\t%m4\n"
++ : "+r"(tmp1), "+r"(tmp2), "+r"(tmp3), "+r"(tmp4),
++ "=&r"(acc), "+r"(s)
++ : "r"(X));
++
++ asm volatile ( "st.w\t%1[6*4], %m0\n"
++ "st.w\t%2[11*4], %m0\n"
++ :: "r"(acc), "r"(&yptr[i]), "r"(&yptr[-i]));
++
++
++#else
+ MAD_F_ML0(hi, lo, X[0], (*s)[0]);
+ MAD_F_MLA(hi, lo, X[1], (*s)[1]);
+ MAD_F_MLA(hi, lo, X[2], (*s)[2]);
+@@ -2187,6 +2300,7 @@ void III_imdct_s(mad_fixed_t const X[18], mad_fixed_t z[36])
+ yptr[11 - i] = yptr[i + 6];
+
+ ++s;
++#endif
+ }
+
+ yptr += 12;
+@@ -2198,6 +2312,196 @@ void III_imdct_s(mad_fixed_t const X[18], mad_fixed_t z[36])
+ yptr = &y[0];
+ wptr = &window_s[0];
+
++#ifdef FPM_AVR32
++ /* z[0] = 0;
++ z[1] = 0;
++ z[2] = 0;
++ z[3] = 0;
++ z[4] = 0;
++ z[5] = 0;
++ z[30] = 0;
++ z[31] = 0;
++ z[32] = 0;
++ z[33] = 0;
++ z[34] = 0;
++ z[35] = 0;
++ */
++ {
++ register long long int tmp, tmp2, tmp3, w0123, w4567, w891011;
++ asm volatile ("mov\t%m0, 0\n"
++ "mov\t%0, %m0\n"
++ "st.d\t%1[0], %0\n"
++ "st.d\t%1[2*4], %0\n"
++ "st.d\t%1[4*4], %0\n"
++ "st.d\t%1[30*4], %0\n"
++ "st.d\t%1[32*4], %0\n"
++ "st.d\t%1[34*4], %0\n"
++ : "=&r"(tmp) : "r"(z));
++
++
++
++ /*
++ z[6] = mad_f_mul(yptr [0], wptr[0]);
++ z[7] = mad_f_mul(yptr [1], wptr[1]);
++ z[8] = mad_f_mul(yptr [2], wptr[2]);
++ z[9] = mad_f_mul(yptr [3], wptr[3]);
++ z[10] = mad_f_mul(yptr[4], wptr[4]);
++ z[11] = mad_f_mul(yptr[5], wptr[5]);
++ z[24] = mad_f_mul(yptr [30], wptr[6]);
++ z[25] = mad_f_mul(yptr [31], wptr[7]);
++ z[26] = mad_f_mul(yptr [32], wptr[8]);
++ z[27] = mad_f_mul(yptr [33], wptr[9]);
++ z[28] = mad_f_mul(yptr[34], wptr[10]);
++ z[29] = mad_f_mul(yptr[35], wptr[11]);
++ */
++
++
++ asm volatile ("ld.d\t%0, %5[0*4]\n"
++ "ld.d\t%3, %6[0*4]\n"
++ "ld.d\t%1, %5[2*4]\n"
++ "ld.d\t%2, %5[4*4]\n"
++ "mulsatrndwh.w\t%m3, %m3, %m0:t\n"
++ "mulsatrndwh.w\t%3, %3, %m0:b\n"
++ "ld.d\t%4, %6[2*4]\n"
++ "st.d\t%7[6*4], %3\n"
++
++ "mulsatrndwh.w\t%m4, %m4, %0:t\n"
++ "mulsatrndwh.w\t%4, %4, %0:b\n"
++ "ld.d\t%3, %6[4*4]\n"
++ "st.d\t%7[8*4], %4\n"
++
++ "mulsatrndwh.w\t%m3, %m3, %m1:t\n"
++ "mulsatrndwh.w\t%3, %3, %m1:b\n"
++ "ld.d\t%4, %6[30*4]\n"
++ "st.d\t%7[10*4], %3\n"
++
++ "mulsatrndwh.w\t%m4, %m4, %1:t\n"
++ "mulsatrndwh.w\t%4, %4, %1:b\n"
++ "ld.d\t%3, %6[32*4]\n"
++ "st.d\t%7[24*4], %4\n"
++
++ "mulsatrndwh.w\t%m3, %m3, %m2:t\n"
++ "mulsatrndwh.w\t%3, %3, %m2:b\n"
++ "ld.d\t%4, %6[34*4]\n"
++ "st.d\t%7[26*4], %3\n"
++
++ "mulsatrndwh.w\t%m4, %m4, %2:t\n"
++ "mulsatrndwh.w\t%4, %4, %2:b\n"
++ "st.d\t%7[28*4], %4\n"
++
++ : "=&r"(w0123), "=&r"(w4567), "=&r"(w891011), "=&r"(tmp), "=&r"(tmp2)
++ : "r"(wptr), "r"(yptr), "r"(z));
++ /*
++ MAD_F_ML0(hi, lo, yptr[6], wptr[6]);
++ MAD_F_MLA(hi, lo, yptr[12], wptr[0]);
++ z[12] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[7], wptr[7]);
++ MAD_F_MLA(hi, lo, yptr[13], wptr[1]);
++ z[13] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[8], wptr[8]);
++ MAD_F_MLA(hi, lo, yptr[14], wptr[2]);
++ z[14] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[9], wptr[9]);
++ MAD_F_MLA(hi, lo, yptr[15], wptr[3]);
++ z[15] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[10], wptr[10]);
++ MAD_F_MLA(hi, lo, yptr[16], wptr[4]);
++ z[16] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[11], wptr[11]);
++ MAD_F_MLA(hi, lo, yptr[17], wptr[5]);
++ z[17] = MAD_F_MLZ(hi, lo);
++
++ MAD_F_ML0(hi, lo, yptr[18], wptr[6]);
++ MAD_F_MLA(hi, lo, yptr[24], wptr[0]);
++ z[18] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[19], wptr[7]);
++ MAD_F_MLA(hi, lo, yptr[25], wptr[1]);
++ z[19] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[20], wptr[8]);
++ MAD_F_MLA(hi, lo, yptr[26], wptr[2]);
++ z[20] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[21], wptr[9]);
++ MAD_F_MLA(hi, lo, yptr[27], wptr[3]);
++ z[21] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[22], wptr[10]);
++ MAD_F_MLA(hi, lo, yptr[28], wptr[4]);
++ z[22] = MAD_F_MLZ(hi, lo);
++ MAD_F_ML0(hi, lo, yptr[23], wptr[11]);
++ MAD_F_MLA(hi, lo, yptr[29], wptr[5]);
++ z[23] = MAD_F_MLZ(hi, lo);*/
++
++
++ asm volatile ("ld.d\t%0, %3[6*4]\n"
++ "ld.d\t%1, %3[12*4]\n"
++ "mulwh.d\t%2, %m0, %5:t\n"
++ "macwh.d\t%2, %m1, %m4:t\n"
++ "mulwh.d\t%0, %0, %5:b\n"
++ "macwh.d\t%0, %1, %m4:b\n"
++ "lsl\t%m2, 1\n"
++ "lsl\t%2, %m0, 1\n"
++ "st.d\t%6[12*4], %2\n"
++
++ "ld.d\t%0, %3[18*4]\n"
++ "ld.d\t%1, %3[24*4]\n"
++ "mulwh.d\t%2, %m0, %5:t\n"
++ "macwh.d\t%2, %m1, %m4:t\n"
++ "mulwh.d\t%0, %0, %5:b\n"
++ "macwh.d\t%0, %1, %m4:b\n"
++ "lsl\t%m2, 1\n"
++ "lsl\t%2, %m0, 1\n"
++ "st.d\t%6[18*4], %2\n"
++
++ : "=&r"(tmp), "=&r"(tmp2), "=&r"(tmp3)
++ : "r"(yptr), "r"(w0123), "r"(w4567), "r"(z));
++
++ asm volatile ("ld.d\t%0, %3[8*4]\n"
++ "ld.d\t%1, %3[14*4]\n"
++ "mulwh.d\t%2, %m0, %m5:t\n"
++ "macwh.d\t%2, %m1, %4:t\n"
++ "mulwh.d\t%0, %0, %m5:b\n"
++ "macwh.d\t%0, %1, %4:b\n"
++ "lsl\t%m2, 1\n"
++ "lsl\t%2, %m0, 1\n"
++ "st.d\t%6[14*4], %2\n"
++
++ "ld.d\t%0, %3[20*4]\n"
++ "ld.d\t%1, %3[26*4]\n"
++ "mulwh.d\t%2, %m0, %m5:t\n"
++ "macwh.d\t%2, %m1, %4:t\n"
++ "mulwh.d\t%0, %0, %m5:b\n"
++ "macwh.d\t%0, %1, %4:b\n"
++ "lsl\t%m2, 1\n"
++ "lsl\t%2, %m0, 1\n"
++ "st.d\t%6[20*4], %2\n"
++
++ : "=&r"(tmp), "=&r"(tmp2), "=&r"(tmp3)
++ : "r"(yptr), "r"(w0123), "r"(w891011), "r"(z));
++
++ asm volatile ("ld.d\t%0, %3[10*4]\n"
++ "ld.d\t%1, %3[16*4]\n"
++ "mulwh.d\t%2, %m0, %5:t\n"
++ "macwh.d\t%2, %m1, %m4:t\n"
++ "mulwh.d\t%0, %0, %5:b\n"
++ "macwh.d\t%0, %1, %m4:b\n"
++ "lsl\t%m2, 1\n"
++ "lsl\t%2, %m0, 1\n"
++ "st.d\t%6[16*4], %2\n"
++
++ "ld.d\t%0, %3[22*4]\n"
++ "ld.d\t%1, %3[28*4]\n"
++ "mulwh.d\t%2, %m0, %5:t\n"
++ "macwh.d\t%2, %m1, %m4:t\n"
++ "mulwh.d\t%0, %0, %5:b\n"
++ "macwh.d\t%0, %1, %m4:b\n"
++ "lsl\t%m2, 1\n"
++ "lsl\t%2, %m0, 1\n"
++ "st.d\t%6[22*4], %2\n"
++
++ : "=&r"(tmp), "=&r"(tmp2), "=&r"(tmp3)
++ : "r"(yptr), "r"(w4567), "r"(w891011), "r"(z));
++
++ }
++#else
+ for (i = 0; i < 6; ++i) {
+ z[i + 0] = 0;
+ z[i + 6] = mad_f_mul(yptr[ 0 + 0], wptr[0]);
+@@ -2218,8 +2522,15 @@ void III_imdct_s(mad_fixed_t const X[18], mad_fixed_t z[36])
+ ++yptr;
+ ++wptr;
+ }
++#endif
+ }
+
++#ifdef FPM_AVR32
++# undef mad_f_mul
++# define mad_f_mul(x, y) ((((x) + (1L << 11)) >> 12) * \
++ (((y) + (1L << 15)) >> 16))
++#endif
++
+ /*
+ * NAME: III_overlap()
+ * DESCRIPTION: perform overlap-add of windowed IMDCT outputs
+diff --git a/synth.c b/synth.c
+index 1d28d43..f42d49b 100644
+--- a/synth.c
++++ b/synth.c
+@@ -29,20 +29,6 @@
+ # include "frame.h"
+ # include "synth.h"
+
+-/*
+- * NAME: synth->init()
+- * DESCRIPTION: initialize synth struct
+- */
+-void mad_synth_init(struct mad_synth *synth)
+-{
+- mad_synth_mute(synth);
+-
+- synth->phase = 0;
+-
+- synth->pcm.samplerate = 0;
+- synth->pcm.channels = 0;
+- synth->pcm.length = 0;
+-}
+
+ /*
+ * NAME: synth->mute()
+@@ -88,6 +74,10 @@ void mad_synth_mute(struct mad_synth *synth)
+
+ /* FPM_DEFAULT without OPT_SSO will actually lose accuracy and performance */
+
++# if defined(FPM_AVR32)
++# define OPT_SSO
++# endif
++
+ # if defined(FPM_DEFAULT) && !defined(OPT_SSO)
+ # define OPT_SSO
+ # endif
+@@ -522,9 +512,15 @@ void dct32(mad_fixed_t const in[32], unsigned int slot,
+ # endif
+ # define ML0(hi, lo, x, y) ((lo) = (x) * (y))
+ # define MLA(hi, lo, x, y) ((lo) += (x) * (y))
+-# define MLN(hi, lo) ((lo) = -(lo))
+-# define MLZ(hi, lo) ((void) (hi), (mad_fixed_t) (lo))
+-# define SHIFT(x) ((x) >> 2)
++# if defined(FPM_AVR32)
++# define MLN(hi, lo) MAD_F_MLN((hi), (lo))
++# define MLZ(hi, lo) (hi)
++# define SHIFT(x) ((x) << 2)
++# else
++# define MLN(hi, lo) ((lo) = -(lo))
++# define MLZ(hi, lo) ((void) (hi), (mad_fixed_t) (lo))
++# define SHIFT(x) ((x) >> 2)
++# endif
+ # define PRESHIFT(x) ((MAD_F(x) + (1L << 13)) >> 14)
+ # else
+ # define ML0(hi, lo, x, y) MAD_F_ML0((hi), (lo), (x), (y))
+@@ -541,11 +537,54 @@ void dct32(mad_fixed_t const in[32], unsigned int slot,
+ # endif
+ # endif
+
++/*
++ * NAME: synth->init()
++ * DESCRIPTION: initialize synth struct
++ */
++
++#ifdef FPM_AVR32
++short Dmod[17][33];
++#endif
++
+ static
++#ifdef FPM_AVR32
++short const D[17][32] = {
++#else
+ mad_fixed_t const D[17][32] = {
++#endif
+ # include "D.dat"
+ };
+
++void mad_synth_init(struct mad_synth *synth)
++{
++
++ mad_synth_mute(synth);
++
++ synth->phase = 0;
++
++ synth->pcm.samplerate = 0;
++ synth->pcm.channels = 0;
++ synth->pcm.length = 0;
++
++#ifdef FPM_AVR32
++ {
++ int i, j;
++ for ( i = 0; i < 17; i++ ){
++ for ( j = 0; j < 32; j++ ){
++ if ( j & 1 ){
++ Dmod[i][17 + (j >> 1)]= D[i][j];
++ } else {
++ Dmod[i][(j >> 1)]= D[i][j];
++ }
++ }
++
++ Dmod[i][16]= Dmod[i][16+8];
++ }
++ }
++#endif
++
++}
++
+ # if defined(ASO_SYNTH)
+ void synth_full(struct mad_synth *, struct mad_frame const *,
+ unsigned int, unsigned int);
+@@ -560,9 +599,13 @@ void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
+ {
+ unsigned int phase, ch, s, sb, pe, po;
+ mad_fixed_t *pcm1, *pcm2, (*filter)[2][2][16][8];
+- mad_fixed_t const (*sbsample)[36][32];
++ mad_fixed_t /*const*/ (*sbsample)[36][32];
+ register mad_fixed_t (*fe)[8], (*fx)[8], (*fo)[8];
++#ifdef FPM_AVR32
++ register short const (*Dptr)[32], *ptr;
++#else
+ register mad_fixed_t const (*Dptr)[32], *ptr;
++#endif
+ register mad_fixed64hi_t hi;
+ register mad_fixed64lo_t lo;
+
+@@ -573,6 +616,20 @@ void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
+ pcm1 = synth->pcm.samples[ch];
+
+ for (s = 0; s < ns; ++s) {
++# ifdef FPM_AVR32
++/*
++ int i;
++ for ( i = 0; i < 32; i++ ){
++ (*sbsample)[s][i] = ((*sbsample)[s][i] + (1 << 13)) & 0xFFFFC000;
++ }
++*/
++ dct32_avr32((*sbsample)[s], phase >> 1,
++ (*filter)[0][phase & 1], (*filter)[1][phase & 1]);
++ /* printf("dct32: %d\n", GET_CYCLES);*/
++ pcm1 = synth_avr32(phase, (mad_fixed_t *)filter, \
++ pcm1, (short *)&Dmod[0]);
++ /* printf("synth_window: %d\n", GET_CYCLES);*/
++# else
+ dct32((*sbsample)[s], phase >> 1,
+ (*filter)[0][phase & 1], (*filter)[1][phase & 1]);
+
+@@ -679,6 +736,7 @@ void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
+ MLA(hi, lo, (*fo)[7], ptr[ 2]);
+
+ *pcm1 = SHIFT(-MLZ(hi, lo));
++# endif
+ pcm1 += 16;
+
+ phase = (phase + 1) % 16;
+diff --git a/synth_avr32.S b/synth_avr32.S
+new file mode 100644
+index 0000000..701077b
+--- /dev/null
++++ b/synth_avr32.S
+@@ -0,0 +1,394 @@
++/*
++ Optimized function for speeding up synthesis filter
++ in MPEG Audio Decoding.
++ Copyright 2003-2006 Atmel Corporation.
++
++ Written by Ronny Pedersen and Lars Even Almås, Atmel Norway
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
++
++
++/* *****************
++ Defining macros
++ ***************** */
++
++ .macro window_1 f, ptr, acc, ptr_offset, mul, tmp1_lo, tmp1_hi, tmp2_lo, tmp2_hi, tmp3_lo, tmp3_hi
++ ld.d \tmp1_lo, \f[0*4] /* tmp1 = { f[0], f[1] } */
++ ld.w \tmp2_lo, \ptr[0*2+\ptr_offset*2] /* tmp2_lo = { ptr[0], ptr[1] }*/
++ ld.d \tmp3_lo, \f[6*4] /* tmp3 = { f[6], f[7] } */
++ ld.w \tmp2_hi, \ptr[6*2+\ptr_offset*2] /* tmp2_hi = { ptr[6], ptr[7] }*/
++ .if \mul
++ mulwh.d \acc, \tmp1_hi, \tmp2_lo:t /* f[0] * ptr[0]*/
++ .else
++ macwh.d \acc, \tmp1_hi, \tmp2_lo:t /* f[0] * ptr[0]*/
++ .endif
++ macwh.d \acc, \tmp3_lo, \tmp2_lo:b /* f[7] * ptr[1]*/
++ ld.w \tmp2_lo, \ptr[2*2+\ptr_offset*2] /* tmp2_lo = { ptr[2], ptr[3] }*/
++ macwh.d \acc, \tmp1_lo, \tmp2_hi:b /* f[1] * ptr[7]*/
++ ld.d \tmp1_lo, \f[2*4] /* tmp1 = { f[2], f[3] } */
++
++ macwh.d \acc, \tmp3_hi, \tmp2_lo:t /* f[6] * ptr[2]*/
++ macwh.d \acc, \tmp1_hi, \tmp2_hi:t /* f[2] * ptr[6]*/
++ ld.d \tmp3_lo, \f[4*4] /* tmp3 = { f[4], f[5] } */
++ ld.w \tmp2_hi, \ptr[4*2+\ptr_offset*2] /* tmp2_hi = { ptr[4], ptr[5] }*/
++ macwh.d \acc, \tmp3_lo, \tmp2_lo:b /* f[5] * ptr[3]*/
++
++ macwh.d \acc, \tmp1_lo, \tmp2_hi:b /* f[3] * ptr[5]*/
++ macwh.d \acc, \tmp3_hi, \tmp2_hi:t /* f[4] * ptr[4]*/
++ .endm
++
++ .macro window_2 f, ptr, acc, ptr_offset, mul, tmp1_lo, tmp1_hi, tmp2_lo, tmp2_hi, tmp3_lo, tmp3_hi
++ ld.d \tmp1_lo, \f[0*4] /* tmp1 = { f[0], f[1] } */
++ ld.w \tmp2_lo, \ptr[7*2+\ptr_offset*2] /* tmp2_lo = { ptr[7], ptr[8] }*/
++ ld.d \tmp3_lo, \f[2*4] /* tmp3 = { f[2], f[3] } */
++ ld.w \tmp2_hi, \ptr[9*2+\ptr_offset*2] /* tmp2_hi = { ptr[9], ptr[10] }*/
++ .if \mul
++ mulwh.d \acc, \tmp1_hi, \tmp2_lo:t /* f[0] * ptr[7]*/
++ .else
++ macwh.d \acc, \tmp1_hi, \tmp2_lo:t /* f[0] * ptr[7]*/
++ .endif
++ macwh.d \acc, \tmp1_lo, \tmp2_lo:b /* f[1] * ptr[8]*/
++
++ ld.d \tmp1_lo, \f[4*4] /* tmp1 = { f[4], f[5] } */
++ ld.w \tmp2_lo, \ptr[11*2+\ptr_offset*2] /* tmp2_lo = { ptr[11], ptr[12] }*/
++
++ macwh.d \acc, \tmp3_hi, \tmp2_hi:t /* f[2] * ptr[9]*/
++ macwh.d \acc, \tmp3_lo, \tmp2_hi:b /* f[3] * ptr[10]*/
++
++ ld.d \tmp3_lo, \f[6*4] /* tmp3 = { f[6], f[7] } */
++ ld.w \tmp2_hi, \ptr[13*2+\ptr_offset*2] /* tmp2_hi = { ptr[13], ptr[14] }*/
++
++ macwh.d \acc, \tmp1_hi, \tmp2_lo:t /* f[4] * ptr[11]*/
++ macwh.d \acc, \tmp1_lo, \tmp2_lo:b /* f[5] * ptr[12]*/
++ macwh.d \acc, \tmp3_hi, \tmp2_hi:t /* f[6] * ptr[13]*/
++ macwh.d \acc, \tmp3_lo, \tmp2_hi:b /* f[7] * ptr[14]*/
++ .endm
++
++ .macro scale res, d_lo, d_hi
++ lsl \d_hi, 2
++ .endm
++
++/* **********************
++ Starting main function
++ ********************** */
++
++/* Function synth_avr32 is called from synth.c with arguments:
++ phase, filter, *pcm1, &D[0] */
++
++ .global synth_avr32
++synth_avr32:
++ pushm r0-r7, lr
++ sub sp, 8
++
++ /* R12 = phase, R11 = filter, R10 = pcm1, r9 = D*/
++ bld r12, 0
++ brcc synth_even
++
++ /* Filter for odd phases */
++
++ /* fe = &(*filter)[0][1][0];
++ fx = &(*filter)[0][0][0];
++ fo = &(*filter)[1][0][0]; */
++ sub lr /*fe*/, r11, -16*8*4
++ sub r8 /*fo*/, r11, -16*8*4*2
++
++ /* pe = phase >> 1; */
++ lsr r12, 1
++ stdsp sp[4], r12
++ /* ptr = (short const *)Dmod + pe; */
++ add r12, r9, r12 << 1
++
++ /* ML0(hi, lo, (*fx)[0], ptr[0 + 17]);
++ MLA(hi, lo, (*fx)[1], ptr[7 + 17]);
++ MLA(hi, lo, (*fx)[2], ptr[6 + 17]);
++ MLA(hi, lo, (*fx)[3], ptr[5 + 17]);
++ MLA(hi, lo, (*fx)[4], ptr[4 + 17]);
++ MLA(hi, lo, (*fx)[5], ptr[3 + 17]);
++ MLA(hi, lo, (*fx)[6], ptr[2 + 17]);
++ MLA(hi, lo, (*fx)[7], ptr[1 + 17]); */
++ window_1 r11/*fx*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++
++ /* MLN(hi, lo); */
++ neg r0
++ acr r1
++ neg r1
++
++ /* MLA(hi, lo, (*fe)[0], ptr[0]);
++ MLA(hi, lo, (*fe)[1], ptr[7]);
++ MLA(hi, lo, (*fe)[2], ptr[6]);
++ MLA(hi, lo, (*fe)[3], ptr[5]);
++ MLA(hi, lo, (*fe)[4], ptr[4]);
++ MLA(hi, lo, (*fe)[5], ptr[3]);
++ MLA(hi, lo, (*fe)[6], ptr[2]);
++ MLA(hi, lo, (*fe)[7], ptr[1]); */
++ window_1 lr/*fe*/,r12/*ptr*/,r0/*acc*/,0/*off*/,0/*mac*/,r2,r3,r4,r5,r6,r7
++
++ /* *pcm1++ = SHIFT(MLZ(hi, lo));
++
++ pcm2 = pcm1 + 31; */
++ scale r1, r0, r1
++ st.w r10/*pcm_1*/++, r1
++ sub r11/*pcm2*/, r10, -4*31
++
++ /* for (sb = 1; sb < 16; ++sb) { */
++ mov r2, 15
++ stdsp sp[0], r2
++odd_loop:
++ /* ++fe;
++ ptr += 33; */
++ sub lr /*fe*/, -8*4
++ sub r12, -33*2
++
++ /* ML0(hi, lo, (*fo)[0], ptr[0 + 17]);
++ MLA(hi, lo, (*fo)[1], ptr[7 + 17]);
++ MLA(hi, lo, (*fo)[2], ptr[6 + 17]);
++ MLA(hi, lo, (*fo)[3], ptr[5 + 17]);
++ MLA(hi, lo, (*fo)[4], ptr[4 + 17]);
++ MLA(hi, lo, (*fo)[5], ptr[3 + 17]);
++ MLA(hi, lo, (*fo)[6], ptr[2 + 17]);
++ MLA(hi, lo, (*fo)[7], ptr[1 + 17]); */
++ window_1 r8/*fo*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++ /* MLN(hi, lo); */
++
++ neg r0
++ acr r1
++ neg r1
++
++ /* MLA(hi, lo, (*fe)[7], ptr[1]);
++ MLA(hi, lo, (*fe)[6], ptr[2]);
++ MLA(hi, lo, (*fe)[5], ptr[3]);
++ MLA(hi, lo, (*fe)[4], ptr[4]);
++ MLA(hi, lo, (*fe)[3], ptr[5]);
++ MLA(hi, lo, (*fe)[2], ptr[6]);
++ MLA(hi, lo, (*fe)[1], ptr[7]);
++ MLA(hi, lo, (*fe)[0], ptr[0]); */
++ window_1 lr/*fe*/,r12/*ptr*/,r0/*acc*/,0/*off*/,0/*mac*/,r2,r3,r4,r5,r6,r7
++
++ /* ptr -= 2*pe; */
++ lddsp r2, sp[4]
++
++ /* *pcm1++ = SHIFT(MLZ(hi, lo)); */
++
++ scale r1, r0, r1
++ sub r12/*ptr*/, r12, r2/*pe*/<< 2
++ st.w r10/*pcm_1*/++, r1
++
++
++ /* ML0(hi, lo, (*fe)[0], ptr[7 + 17]);
++ MLA(hi, lo, (*fe)[1], ptr[8 + 17]);
++ MLA(hi, lo, (*fe)[2], ptr[9 + 17]);
++ MLA(hi, lo, (*fe)[3], ptr[10 + 17]);
++ MLA(hi, lo, (*fe)[4], ptr[11 + 17]);
++ MLA(hi, lo, (*fe)[5], ptr[12 + 17]);
++ MLA(hi, lo, (*fe)[6], ptr[13 + 17]);
++ MLA(hi, lo, (*fe)[7], ptr[14 + 17]); */
++ window_2 lr/*fe*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++ /* MLA(hi, lo, (*fo)[7], ptr[14]);
++ MLA(hi, lo, (*fo)[6], ptr[13]);
++ MLA(hi, lo, (*fo)[5], ptr[12]);
++ MLA(hi, lo, (*fo)[4], ptr[11]);
++ MLA(hi, lo, (*fo)[3], ptr[10]);
++ MLA(hi, lo, (*fo)[2], ptr[9]);
++ MLA(hi, lo, (*fo)[1], ptr[8]);
++ MLA(hi, lo, (*fo)[0], ptr[7]); */
++ window_2 r8/*fo*/,r12/*ptr*/,r0/*acc*/,0/*off*/,0/*mac*/,r2,r3,r4,r5,r6,r7
++
++
++ /* *pcm2-- = SHIFT(MLZ(hi, lo)); */
++ lddsp r3, sp[4]
++ lddsp r2, sp[0]
++ scale r1, r0, r1
++ st.w --r11/*pcm_2*/, r1
++
++ /* ptr += 2*pe; */
++ add r12/*ptr*/, r12, r3/*pe*/<< 2
++
++ /* ++fo;
++ } */
++ sub r8/*fo*/, -8*4
++
++ sub r2, 1
++ stdsp sp[0], r2
++ brne odd_loop
++
++ /* ptr += 33; */
++ sub r12/*ptr*/, -33*2
++
++ /* ML0(hi, lo, (*fo)[0], ptr[0 + 17]);
++ MLA(hi, lo, (*fo)[1], ptr[7 + 17]);
++ MLA(hi, lo, (*fo)[2], ptr[6 + 17]);
++ MLA(hi, lo, (*fo)[3], ptr[5 + 17]);
++ MLA(hi, lo, (*fo)[4], ptr[4 + 17]);
++ MLA(hi, lo, (*fo)[5], ptr[3 + 17]);
++ MLA(hi, lo, (*fo)[6], ptr[2 + 17]);
++ MLA(hi, lo, (*fo)[7], ptr[1 + 17]); */
++ window_1 r8/*fo*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++
++ rjmp synth_end
++synth_even:
++ /* Filter for even phases */
++
++ /* fe = &(*filter)[0][0][0];
++ fx = &(*filter)[0][1][0];
++ fo = &(*filter)[1][1][0]; */
++ sub lr /*fx*/, r11, -16*8*4
++ sub r8 /*fo*/, r11, -(16*8*4*2 + 16*8*4)
++
++ /* po = ((phase - 1) & 0xF) >> 1; */
++ sub r12, 1
++ andl r12, 0xe, COH
++ stdsp sp[4], r12
++ /* ptr = (short const *)Dmod + po; */
++ add r12, r9, r12
++
++ /* ML0(hi, lo, (*fx)[0], ptr[0 + 17]);
++ MLA(hi, lo, (*fx)[1], ptr[7 + 17]);
++ MLA(hi, lo, (*fx)[2], ptr[6 + 17]);
++ MLA(hi, lo, (*fx)[3], ptr[5 + 17]);
++ MLA(hi, lo, (*fx)[4], ptr[4 + 17]);
++ MLA(hi, lo, (*fx)[5], ptr[3 + 17]);
++ MLA(hi, lo, (*fx)[6], ptr[2 + 17]);
++ MLA(hi, lo, (*fx)[7], ptr[1 + 17]); */
++ window_1 lr/*fx*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++
++ /* MLN(hi, lo); */
++ neg r0
++ acr r1
++ neg r1
++
++ /* MLA(hi, lo, (*fe)[0], ptr[0 + 1]);
++ MLA(hi, lo, (*fe)[1], ptr[7 + 1]);
++ MLA(hi, lo, (*fe)[2], ptr[6 + 1]);
++ MLA(hi, lo, (*fe)[3], ptr[5 + 1]);
++ MLA(hi, lo, (*fe)[4], ptr[4 + 1]);
++ MLA(hi, lo, (*fe)[5], ptr[3 + 1]);
++ MLA(hi, lo, (*fe)[6], ptr[2 + 1]);
++ MLA(hi, lo, (*fe)[7], ptr[1 + 1]); */
++ window_1 r11/*fe*/,r12/*ptr*/,r0/*acc*/,1/*off*/,0/*mac*/,r2,r3,r4,r5,r6,r7
++
++ /* *pcm1++ = SHIFT(MLZ(hi, lo));
++
++ pcm2 = pcm1 + 31; */
++ scale r1, r0, r1
++ st.w r10/*pcm_1*/++, r1
++ sub lr/*pcm2*/, r10, -4*31
++
++ /* for (sb = 1; sb < 16; ++sb) { */
++ mov r2, 15
++ stdsp sp[0], r2
++even_loop:
++ /* ++fe;
++ ptr += 33; */
++ sub r11 /*fe*/, -8*4
++ sub r12, -33*2
++
++ /* ML0(hi, lo, (*fo)[0], ptr[0 + 17]);
++ MLA(hi, lo, (*fo)[1], ptr[7 + 17]);
++ MLA(hi, lo, (*fo)[2], ptr[6 + 17]);
++ MLA(hi, lo, (*fo)[3], ptr[5 + 17]);
++ MLA(hi, lo, (*fo)[4], ptr[4 + 17]);
++ MLA(hi, lo, (*fo)[5], ptr[3 + 17]);
++ MLA(hi, lo, (*fo)[6], ptr[2 + 17]);
++ MLA(hi, lo, (*fo)[7], ptr[1 + 17]); */
++ window_1 r8/*fo*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++ /* MLN(hi, lo); */
++ neg r0
++ acr r1
++ neg r1
++
++ /* MLA(hi, lo, (*fe)[7], ptr[1 + 1]);
++ MLA(hi, lo, (*fe)[6], ptr[2 + 1]);
++ MLA(hi, lo, (*fe)[5], ptr[3 + 1]);
++ MLA(hi, lo, (*fe)[4], ptr[4 + 1]);
++ MLA(hi, lo, (*fe)[3], ptr[5 + 1]);
++ MLA(hi, lo, (*fe)[2], ptr[6 + 1]);
++ MLA(hi, lo, (*fe)[1], ptr[7 + 1]);
++ MLA(hi, lo, (*fe)[0], ptr[0 + 1]); */
++ window_1 r11/*fe*/,r12/*ptr*/,r0/*acc*/,1/*off*/,0/*mac*/,r2,r3,r4,r5,r6,r7
++
++ /* *pcm1++ = SHIFT(MLZ(hi, lo)); */
++ lddsp r2, sp[4]
++ scale r1, r0, r1
++ /* ptr -= 2*po; */
++ sub r12/*ptr*/, r12, r2/*po*/<< 1
++ st.w r10/*pcm_1*/++, r1
++
++
++ /* ML0(hi, lo, (*fe)[0], ptr[7 + 17 - 1]);
++ MLA(hi, lo, (*fe)[1], ptr[8 + 17 - 1]);
++ MLA(hi, lo, (*fe)[2], ptr[9 + 17 - 1]);
++ MLA(hi, lo, (*fe)[3], ptr[10 + 17 - 1]);
++ MLA(hi, lo, (*fe)[4], ptr[11 + 17 - 1]);
++ MLA(hi, lo, (*fe)[5], ptr[12 + 17 - 1]);
++ MLA(hi, lo, (*fe)[6], ptr[13 + 17 - 1]);
++ MLA(hi, lo, (*fe)[7], ptr[14 + 17 - 1]); */
++ window_2 r11/*fe*/,r12/*ptr*/,r0/*acc*/,16/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++ /* MLA(hi, lo, (*fo)[7], ptr[14]);
++ MLA(hi, lo, (*fo)[6], ptr[13]);
++ MLA(hi, lo, (*fo)[5], ptr[12]);
++ MLA(hi, lo, (*fo)[4], ptr[11]);
++ MLA(hi, lo, (*fo)[3], ptr[10]);
++ MLA(hi, lo, (*fo)[2], ptr[9]);
++ MLA(hi, lo, (*fo)[1], ptr[8]);
++ MLA(hi, lo, (*fo)[0], ptr[7]); */
++ window_2 r8/*fo*/,r12/*ptr*/,r0/*acc*/,0/*off*/,0/*mac*/,r2,r3,r4,r5,r6,r7
++
++
++ /* *pcm2-- = SHIFT(MLZ(hi, lo)); */
++ lddsp r3, sp[4]
++ lddsp r2, sp[0]
++ scale r1, r0, r1
++ st.w --lr/*pcm_2*/, r1
++
++ /* ptr += 2*po; */
++ add r12/*ptr*/, r12, r3/*po*/<< 1
++
++ /* ++fo;
++ } */
++ sub r8/*fo*/, -8*4
++
++ sub r2, 1
++ stdsp sp[0], r2
++ brne even_loop
++
++ /* ptr += 33; */
++ sub r12/*ptr*/, -33*2
++
++ /* ML0(hi, lo, (*fo)[0], ptr[0 + 17]);
++ MLA(hi, lo, (*fo)[1], ptr[7 + 17]);
++ MLA(hi, lo, (*fo)[2], ptr[6 + 17]);
++ MLA(hi, lo, (*fo)[3], ptr[5 + 17]);
++ MLA(hi, lo, (*fo)[4], ptr[4 + 17]);
++ MLA(hi, lo, (*fo)[5], ptr[3 + 17]);
++ MLA(hi, lo, (*fo)[6], ptr[2 + 17]);
++ MLA(hi, lo, (*fo)[7], ptr[1 + 17]); */
++ window_1 r8/*fo*/,r12/*ptr*/,r0/*acc*/,17/*off*/,1/*mul*/,r2,r3,r4,r5,r6,r7
++
++
++
++synth_end:
++ /* *pcm1 = SHIFT(-MLZ(hi, lo)); */
++ scale r1, r0, r1
++ neg r1
++ st.w r10/*pcm_1*/, r1
++
++ mov r12, r10
++ sub sp, -8
++ popm r0-r7, pc
++
++
++
++
++
diff --git a/packages/libmad/libmad_0.15.1b.bb b/packages/libmad/libmad_0.15.1b.bb
index 9de296635e..5393f822cf 100644
--- a/packages/libmad/libmad_0.15.1b.bb
+++ b/packages/libmad/libmad_0.15.1b.bb
@@ -4,9 +4,13 @@ PRIORITY = "optional"
DEPENDS = "libid3tag"
LICENSE = "GPL"
+PR = "r1"
+
SRC_URI = "ftp://ftp.mars.org/pub/mpeg/libmad-${PV}.tar.gz"
S = "${WORKDIR}/libmad-${PV}"
+SRC_URI_append_avr32 = " file://libmad-0.15.1b-avr32-optimization.patch;patch=1"
+
inherit autotools
EXTRA_OECONF = "-enable-speed --enable-shared"
diff --git a/packages/linux/linux-2.6.18/.mtn2git_empty b/packages/linux/linux-2.6.18/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/linux-2.6.18/.mtn2git_empty
diff --git a/packages/linux/linux-2.6.18/0001-AVR32-Fix-compile-error-with-gcc-4.1.patch b/packages/linux/linux-2.6.18/0001-AVR32-Fix-compile-error-with-gcc-4.1.patch
new file mode 100755
index 0000000000..2b430450d9
--- /dev/null
+++ b/packages/linux/linux-2.6.18/0001-AVR32-Fix-compile-error-with-gcc-4.1.patch
@@ -0,0 +1,71 @@
+From 8224ca195874525533665bbcd23b6da1e575aa4d Mon Sep 17 00:00:00 2001
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri, 27 Apr 2007 14:21:47 +0200
+Subject: [AVR32] Fix compile error with gcc 4.1
+
+gcc 4.1 doesn't seem to like const variables as inline assembly
+outputs. Drop support for reading 64-bit values using get_user() so
+that we can use an unsigned long to hold the result regardless of the
+actual size. This should be safe since many architectures, including
+i386, doesn't support reading 64-bit values with get_user().
+
+Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+---
+ include/asm-avr32/uaccess.h | 13 ++++---------
+ 1 files changed, 4 insertions(+), 9 deletions(-)
+
+diff --git a/include/asm-avr32/uaccess.h b/include/asm-avr32/uaccess.h
+index 74a679e..ed09239 100644
+--- a/include/asm-avr32/uaccess.h
++++ b/include/asm-avr32/uaccess.h
+@@ -181,24 +181,23 @@ extern int __put_user_bad(void);
+
+ #define __get_user_nocheck(x, ptr, size) \
+ ({ \
+- typeof(*(ptr)) __gu_val = (typeof(*(ptr)) __force)0; \
++ unsigned long __gu_val = 0; \
+ int __gu_err = 0; \
+ \
+ switch (size) { \
+ case 1: __get_user_asm("ub", __gu_val, ptr, __gu_err); break; \
+ case 2: __get_user_asm("uh", __gu_val, ptr, __gu_err); break; \
+ case 4: __get_user_asm("w", __gu_val, ptr, __gu_err); break; \
+- case 8: __get_user_asm("d", __gu_val, ptr, __gu_err); break; \
+ default: __gu_err = __get_user_bad(); break; \
+ } \
+ \
+- x = __gu_val; \
++ x = (typeof(*(ptr)))__gu_val; \
+ __gu_err; \
+ })
+
+ #define __get_user_check(x, ptr, size) \
+ ({ \
+- typeof(*(ptr)) __gu_val = (typeof(*(ptr)) __force)0; \
++ unsigned long __gu_val = 0; \
+ const typeof(*(ptr)) __user * __gu_addr = (ptr); \
+ int __gu_err = 0; \
+ \
+@@ -216,10 +215,6 @@ extern int __put_user_bad(void);
+ __get_user_asm("w", __gu_val, __gu_addr, \
+ __gu_err); \
+ break; \
+- case 8: \
+- __get_user_asm("d", __gu_val, __gu_addr, \
+- __gu_err); \
+- break; \
+ default: \
+ __gu_err = __get_user_bad(); \
+ break; \
+@@ -227,7 +222,7 @@ extern int __put_user_bad(void);
+ } else { \
+ __gu_err = -EFAULT; \
+ } \
+- x = __gu_val; \
++ x = (typeof(*(ptr)))__gu_val; \
+ __gu_err; \
+ })
+
+--
+1.4.4.4
+
diff --git a/packages/linux/linux-2.6.18/add-all-parameters-to-smc-driver.patch b/packages/linux/linux-2.6.18/add-all-parameters-to-smc-driver.patch
new file mode 100644
index 0000000000..ec4de30cc8
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-all-parameters-to-smc-driver.patch
@@ -0,0 +1,73 @@
+--- linux-2.6.18-orig/arch/avr32/mach-at32ap/hsmc.c 2006-09-26 15:01:28.000000000 +0200
++++ linux-2.6.18/arch/avr32/mach-at32ap/hsmc.c 2006-10-18 14:03:35.000000000 +0200
+@@ -75,12 +75,35 @@ int smc_set_configuration(int cs, const
+ return -EINVAL;
+ }
+
++ switch (config->nwait_mode) {
++ case 0:
++ mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_DISABLED);
++ break;
++ case 1:
++ mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_RESERVED);
++ break;
++ case 2:
++ mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_FROZEN);
++ break;
++ case 3:
++ mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_READY);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (config->tdf_cycles) {
++ mode |= HSMC_BF(TDF_CYCLES, config->tdf_cycles);
++ }
++
+ if (config->nrd_controlled)
+ mode |= HSMC_BIT(READ_MODE);
+ if (config->nwe_controlled)
+ mode |= HSMC_BIT(WRITE_MODE);
+ if (config->byte_write)
+ mode |= HSMC_BIT(BAT);
++ if (config->tdf_mode)
++ mode |= HSMC_BIT(TDF_MODE);
+
+ pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n",
+ cs, setup, pulse, cycle, mode);
+--- linux-2.6.18-orig/include/asm-avr32/arch-at32ap/smc.h 2006-09-26 15:01:30.000000000 +0200
++++ linux-2.6.18/include/asm-avr32/arch-at32ap/smc.h 2006-10-18 13:36:06.000000000 +0200
+@@ -48,10 +48,32 @@ struct smc_config {
+ unsigned int nwe_controlled:1;
+
+ /*
++ * 0: NWAIT is disabled
++ * 1: Reserved
++ * 2: NWAIT is frozen mode
++ * 3: NWAIT in ready mode
++ */
++ unsigned int nwait_mode:2;
++
++ /*
+ * 0: Byte select access type
+ * 1: Byte write access type
+ */
+ unsigned int byte_write:1;
++
++ /*
++ * Number of clock cycles before data is released after
++ * the rising edge of the read controlling signal
++ *
++ * Total cycles from SMC is tdf_cycles + 1
++ */
++ unsigned int tdf_cycles:4;
++
++ /*
++ * 0: TDF optimization disabled
++ * 1: TDF optimization enabled
++ */
++ unsigned int tdf_mode:1;
+ };
+
+ extern int smc_set_configuration(int cs, const struct smc_config *config);
diff --git a/packages/linux/linux-2.6.18/add-default-atngw-defconfig.patch b/packages/linux/linux-2.6.18/add-default-atngw-defconfig.patch
new file mode 100644
index 0000000000..233416e0ca
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-default-atngw-defconfig.patch
@@ -0,0 +1,975 @@
+Index: linux-2.6.18/arch/avr32/configs/atngw_defconfig
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18/arch/avr32/configs/atngw_defconfig 2007-01-10 10:15:54.000000000 +0100
+@@ -0,0 +1,970 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.18-at0
++# Wed Jan 10 10:13:31 2007
++#
++CONFIG_AVR32=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++# CONFIG_RELAY is not set
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_EMBEDDED=y
++CONFIG_SYSCTL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++# CONFIG_BASE_FULL is not set
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SHMEM=y
++CONFIG_SLAB=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=1
++# CONFIG_SLOB is not set
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++
++#
++# Block layer
++#
++# CONFIG_BLK_DEV_IO_TRACE is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_AS is not set
++# CONFIG_IOSCHED_DEADLINE is not set
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++
++#
++# System Type and features
++#
++CONFIG_SUBARCH_AVR32B=y
++CONFIG_MMU=y
++CONFIG_PERFORMANCE_COUNTERS=y
++CONFIG_PLATFORM_AT32AP=y
++CONFIG_CPU_AT32AP7000=y
++# CONFIG_BOARD_ATSTK1000 is not set
++CONFIG_BOARD_ATNGW=y
++CONFIG_LOADER_U_BOOT=y
++
++#
++# Atmel AVR32 AP options
++#
++CONFIG_PIO_DEV=y
++CONFIG_LOAD_ADDRESS=0x10000000
++CONFIG_ENTRY_ADDRESS=0x90000000
++CONFIG_PHYS_OFFSET=0x10000000
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
++# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
++# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
++CONFIG_ARCH_FLATMEM_ENABLE=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++# CONFIG_OWNERSHIP_TRACE is not set
++CONFIG_DW_DMAC=y
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_250=y
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=250
++CONFIG_CMDLINE=""
++
++#
++# Bus options
++#
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++# CONFIG_PCCARD is not set
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_ASK_IP_FIB_HASH=y
++# CONFIG_IP_FIB_TRIE is not set
++CONFIG_IP_FIB_HASH=y
++# CONFIG_IP_MULTIPLE_TABLES is not set
++# CONFIG_IP_ROUTE_MULTIPATH is not set
++# CONFIG_IP_ROUTE_VERBOSE is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_BIC=y
++
++#
++# IP: Virtual Server Configuration
++#
++# CONFIG_IP_VS is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++
++#
++# Core Netfilter Configuration
++#
++# CONFIG_NETFILTER_NETLINK is not set
++CONFIG_NETFILTER_XTABLES=y
++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
++# CONFIG_NETFILTER_XT_TARGET_MARK is not set
++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
++# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
++# CONFIG_NETFILTER_XT_MATCH_ESP is not set
++# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
++# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_MAC is not set
++# CONFIG_NETFILTER_XT_MATCH_MARK is not set
++# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
++# CONFIG_NETFILTER_XT_MATCH_REALM is not set
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++CONFIG_NETFILTER_XT_MATCH_STATE=y
++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
++# CONFIG_NETFILTER_XT_MATCH_STRING is not set
++# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
++
++#
++# IP: Netfilter Configuration
++#
++CONFIG_IP_NF_CONNTRACK=y
++# CONFIG_IP_NF_CT_ACCT is not set
++# CONFIG_IP_NF_CONNTRACK_MARK is not set
++# CONFIG_IP_NF_CONNTRACK_EVENTS is not set
++# CONFIG_IP_NF_CT_PROTO_SCTP is not set
++# CONFIG_IP_NF_FTP is not set
++# CONFIG_IP_NF_IRC is not set
++# CONFIG_IP_NF_NETBIOS_NS is not set
++# CONFIG_IP_NF_TFTP is not set
++# CONFIG_IP_NF_AMANDA is not set
++# CONFIG_IP_NF_PPTP is not set
++# CONFIG_IP_NF_H323 is not set
++# CONFIG_IP_NF_SIP is not set
++# CONFIG_IP_NF_QUEUE is not set
++CONFIG_IP_NF_IPTABLES=y
++# CONFIG_IP_NF_MATCH_IPRANGE is not set
++# CONFIG_IP_NF_MATCH_TOS is not set
++# CONFIG_IP_NF_MATCH_RECENT is not set
++# CONFIG_IP_NF_MATCH_ECN is not set
++# CONFIG_IP_NF_MATCH_DSCP is not set
++# CONFIG_IP_NF_MATCH_AH is not set
++# CONFIG_IP_NF_MATCH_TTL is not set
++# CONFIG_IP_NF_MATCH_OWNER is not set
++# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
++# CONFIG_IP_NF_MATCH_HASHLIMIT is not set
++CONFIG_IP_NF_FILTER=y
++CONFIG_IP_NF_TARGET_REJECT=y
++CONFIG_IP_NF_TARGET_LOG=y
++# CONFIG_IP_NF_TARGET_ULOG is not set
++# CONFIG_IP_NF_TARGET_TCPMSS is not set
++CONFIG_IP_NF_NAT=y
++CONFIG_IP_NF_NAT_NEEDED=y
++CONFIG_IP_NF_TARGET_MASQUERADE=y
++CONFIG_IP_NF_TARGET_REDIRECT=y
++# CONFIG_IP_NF_TARGET_NETMAP is not set
++# CONFIG_IP_NF_TARGET_SAME is not set
++# CONFIG_IP_NF_NAT_SNMP_BASIC is not set
++# CONFIG_IP_NF_MANGLE is not set
++# CONFIG_IP_NF_RAW is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_IEEE80211 is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_SYS_HYPERVISOR is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_CFI_INTELEXT is not set
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++# CONFIG_MTD_OBSOLETE_CHIPS is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_PHYSMAP_START=0x80000000
++CONFIG_MTD_PHYSMAP_LEN=0x0
++CONFIG_MTD_PHYSMAP_BANKWIDTH=2
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++CONFIG_MTD_DATAFLASH=y
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++
++#
++# NAND Flash Device Drivers
++#
++# CONFIG_MTD_NAND is not set
++
++#
++# OneNAND Flash Device Drivers
++#
++# CONFIG_MTD_ONENAND is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++
++#
++# Block devices
++#
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_RAM=m
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++CONFIG_BLK_DEV_INITRD=y
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# ATA/ATAPI/MFM/RLL support
++#
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# I2O device support
++#
++
++#
++# Network device support
++#
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++
++#
++# PHY device support
++#
++# CONFIG_PHYLIB is not set
++
++#
++# Ethernet (10 or 100Mbit)
++#
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++CONFIG_MACB=y
++
++#
++# Ethernet (1000 Mbit)
++#
++
++#
++# Ethernet (10000 Mbit)
++#
++
++#
++# Token Ring devices
++#
++
++#
++# Wireless LAN (non-hamradio)
++#
++# CONFIG_NET_RADIO is not set
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Telephony Support
++#
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++# CONFIG_INPUT is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++# CONFIG_VT is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_ATMEL=y
++CONFIG_SERIAL_ATMEL_CONSOLE=y
++# CONFIG_SERIAL_ATMEL_TTYAT is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++# CONFIG_WATCHDOG is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_RTC is not set
++# CONFIG_GEN_RTC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++# CONFIG_TELCLOCK is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=m
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++CONFIG_I2C_ATMELTWI=m
++CONFIG_I2C_ATMELTWI_BAUDRATE=100000
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_ATMEL=y
++# CONFIG_SPI_BITBANG is not set
++
++#
++# SPI Protocol Masters
++#
++
++#
++# Dallas's 1-wire bus
++#
++
++#
++# Hardware Monitoring support
++#
++# CONFIG_HWMON is not set
++# CONFIG_HWMON_VID is not set
++
++#
++# Misc devices
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++CONFIG_VIDEO_V4L2=y
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++
++#
++# Graphics support
++#
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++
++#
++# USB support
++#
++# CONFIG_USB_ARCH_HAS_HCD is not set
++# CONFIG_USB_ARCH_HAS_OHCI is not set
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# USB Gadget Support
++#
++CONFIG_USB_GADGET=m
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_PXA2XX is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++CONFIG_USB_GADGET_HUSB2DEV=y
++CONFIG_USB_HUSB2DEV=m
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_GADGETFS is not set
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_FILE_STORAGE_TEST is not set
++# CONFIG_USB_G_SERIAL is not set
++
++#
++# MMC/SD Card support
++#
++CONFIG_MMC=m
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_BLOCK=m
++CONFIG_MMC_ATMELMCI=m
++
++#
++# LED devices
++#
++# CONFIG_NEW_LEDS is not set
++
++#
++# LED drivers
++#
++
++#
++# LED Triggers
++#
++
++#
++# InfiniBand support
++#
++
++#
++# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
++#
++
++#
++# Real Time Clock
++#
++# CONFIG_RTC_CLASS is not set
++
++#
++# DMA Engine support
++#
++# CONFIG_DMA_ENGINE is not set
++
++#
++# DMA Clients
++#
++
++#
++# DMA Devices
++#
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_FS_XATTR is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_INOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++CONFIG_FUSE_FS=m
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=m
++CONFIG_FAT_DEFAULT_CODEPAGE=850
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++CONFIG_CONFIGFS_FS=y
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_JFFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++CONFIG_SMB_FS=m
++# CONFIG_SMB_NLS_DEFAULT is not set
++CONFIG_CIFS=m
++# CONFIG_CIFS_STATS is not set
++# CONFIG_CIFS_WEAK_PW_HASH is not set
++# CONFIG_CIFS_XATTR is not set
++# CONFIG_CIFS_DEBUG2 is not set
++# CONFIG_CIFS_EXPERIMENTAL is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++
++#
++# Native Language Support
++#
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++# CONFIG_NLS_CODEPAGE_437 is not set
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++CONFIG_NLS_CODEPAGE_850=y
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++CONFIG_NLS_UTF8=y
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++# CONFIG_PRINTK_TIME is not set
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_KERNEL=y
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_RWSEMS is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_DEBUG_VM is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_UNWIND_INFO is not set
++# CONFIG_FORCED_INLINING is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_KPROBES is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++# CONFIG_CRYPTO is not set
++
++#
++# Hardware crypto devices
++#
++
++#
++# Library routines
++#
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++CONFIG_CRC32=y
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
diff --git a/packages/linux/linux-2.6.18/add-flush_buffer-operation-to-uart_ops.patch b/packages/linux/linux-2.6.18/add-flush_buffer-operation-to-uart_ops.patch
new file mode 100644
index 0000000000..0c9b919900
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-flush_buffer-operation-to-uart_ops.patch
@@ -0,0 +1,71 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: HÃ¥vard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Feb 2 15:48:50 2006 +0100
+Subject: [PATCH] Add flush_buffer() operation to uart_ops
+
+Serial drivers using DMA (like the Atmel USART3 driver) tend to get
+very confused when the xmit buffer is flushed and nobody told them.
+They also tend to spew a lot of garbage since the DMA engine keeps
+running after the buffer is flushed and possibly refilled with
+unrelated data.
+
+This patch adds a new flush_buffer operation to the uart_ops struct,
+along with a call to it from uart_flush_buffer() right after the xmit
+buffer has been cleared. The driver can implement this in order to
+syncronize its internal DMA state with the xmit buffer when the buffer
+is flushed.
+
+---
+
+ Documentation/serial/driver | 11 +++++++++++
+ drivers/serial/serial_core.c | 2 ++
+ include/linux/serial_core.h | 1 +
+ 3 files changed, 14 insertions(+)
+
+Index: linux-2.6.16-avr32/Documentation/serial/driver
+===================================================================
+--- linux-2.6.16-avr32.orig/Documentation/serial/driver 2006-03-20 06:53:29.000000000 +0100
++++ linux-2.6.16-avr32/Documentation/serial/driver 2006-04-03 18:57:11.000000000 +0200
+@@ -186,6 +186,17 @@ hardware.
+ Locking: port_sem taken.
+ Interrupts: caller dependent.
+
++ flush_buffer(port)
++ Flush any write buffers, reset any DMA state and stop any
++ ongoing DMA transfers.
++
++ This will be called whenever the port->info->xmit circular
++ buffer is cleared.
++
++ Locking: port->lock taken.
++ Interrupts: locally disabled.
++ This call must not sleep
++
+ set_termios(port,termios,oldtermios)
+ Change the port parameters, including word length, parity, stop
+ bits. Update read_status_mask and ignore_status_mask to indicate
+Index: linux-2.6.16-avr32/drivers/serial/serial_core.c
+===================================================================
+--- linux-2.6.16-avr32.orig/drivers/serial/serial_core.c 2006-03-20 06:53:29.000000000 +0100
++++ linux-2.6.16-avr32/drivers/serial/serial_core.c 2006-04-03 18:57:11.000000000 +0200
+@@ -556,6 +556,8 @@ static void uart_flush_buffer(struct tty
+
+ spin_lock_irqsave(&port->lock, flags);
+ uart_circ_clear(&state->info->xmit);
++ if (port->ops->flush_buffer)
++ port->ops->flush_buffer(port);
+ spin_unlock_irqrestore(&port->lock, flags);
+ tty_wakeup(tty);
+ }
+Index: linux-2.6.16-avr32/include/linux/serial_core.h
+===================================================================
+--- linux-2.6.16-avr32.orig/include/linux/serial_core.h 2006-03-20 06:53:29.000000000 +0100
++++ linux-2.6.16-avr32/include/linux/serial_core.h 2006-04-03 18:57:11.000000000 +0200
+@@ -164,6 +164,7 @@ struct uart_ops {
+ void (*break_ctl)(struct uart_port *, int ctl);
+ int (*startup)(struct uart_port *);
+ void (*shutdown)(struct uart_port *);
++ void (*flush_buffer)(struct uart_port *);
+ void (*set_termios)(struct uart_port *, struct termios *new,
+ struct termios *old);
+ void (*pm)(struct uart_port *, unsigned int state,
diff --git a/packages/linux/linux-2.6.18/add-hmatrix-support.patch b/packages/linux/linux-2.6.18/add-hmatrix-support.patch
new file mode 100644
index 0000000000..4387cac0b8
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-hmatrix-support.patch
@@ -0,0 +1,414 @@
+---
+ arch/avr32/mach-at32ap/hmatrix2.h | 377 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 377 insertions(+)
+
+Index: linux-2.6.18/arch/avr32/mach-at32ap/hmatrix2.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18/arch/avr32/mach-at32ap/hmatrix2.h 2006-11-03 14:57:10.000000000 +0100
+@@ -0,0 +1,377 @@
++/*
++ * Register definitions for HMATRIX2
++ *
++ * AHB Matrix
++ */
++#ifndef __ASM_AVR32_HMATRIX2_H__
++#define __ASM_AVR32_HMATRIX2_H__
++
++/* HMATRIX2 base address */
++#define HMATRIX2_BASE (void *)0xfff00800
++
++/* HMATRIX2 register offsets */
++#define HMATRIX2_MCFG0 0x0000
++#define HMATRIX2_MCFG1 0x0004
++#define HMATRIX2_MCFG2 0x0008
++#define HMATRIX2_MCFG3 0x000c
++#define HMATRIX2_MCFG4 0x0010
++#define HMATRIX2_MCFG5 0x0014
++#define HMATRIX2_MCFG6 0x0018
++#define HMATRIX2_MCFG7 0x001c
++#define HMATRIX2_MCFG8 0x0020
++#define HMATRIX2_MCFG9 0x0024
++#define HMATRIX2_MCFG10 0x0028
++#define HMATRIX2_MCFG11 0x002c
++#define HMATRIX2_MCFG12 0x0030
++#define HMATRIX2_MCFG13 0x0034
++#define HMATRIX2_MCFG14 0x0038
++#define HMATRIX2_MCFG15 0x003c
++#define HMATRIX2_SCFG0 0x0040
++#define HMATRIX2_SCFG1 0x0044
++#define HMATRIX2_SCFG2 0x0048
++#define HMATRIX2_SCFG3 0x004c
++#define HMATRIX2_SCFG4 0x0050
++#define HMATRIX2_SCFG5 0x0054
++#define HMATRIX2_SCFG6 0x0058
++#define HMATRIX2_SCFG7 0x005c
++#define HMATRIX2_SCFG8 0x0060
++#define HMATRIX2_SCFG9 0x0064
++#define HMATRIX2_SCFG10 0x0068
++#define HMATRIX2_SCFG11 0x006c
++#define HMATRIX2_SCFG12 0x0070
++#define HMATRIX2_SCFG13 0x0074
++#define HMATRIX2_SCFG14 0x0078
++#define HMATRIX2_SCFG15 0x007c
++#define HMATRIX2_PRAS 0x0080
++#define HMATRIX2_PRBS 0x0084
++#define HMATRIX2_PRAS1 0x0088
++#define HMATRIX2_PRBS1 0x008c
++#define HMATRIX2_PRAS2 0x0090
++#define HMATRIX2_PRBS2 0x0094
++#define HMATRIX2_PRAS3 0x0098
++#define HMATRIX2_PRBS3 0x009c
++#define HMATRIX2_PRAS4 0x00a0
++#define HMATRIX2_PRBS4 0x00a4
++#define HMATRIX2_PRAS5 0x00a8
++#define HMATRIX2_PRBS5 0x00ac
++#define HMATRIX2_PRAS6 0x00b0
++#define HMATRIX2_PRBS6 0x00b4
++#define HMATRIX2_PRAS7 0x00b8
++#define HMATRIX2_PRBS7 0x00bc
++#define HMATRIX2_PRAS8 0x00c0
++#define HMATRIX2_PRBS8 0x00c4
++#define HMATRIX2_PRAS9 0x00c8
++#define HMATRIX2_PRBS9 0x00cc
++#define HMATRIX2_PRAS10 0x00d0
++#define HMATRIX2_PRBS10 0x00d4
++#define HMATRIX2_PRAS11 0x00d8
++#define HMATRIX2_PRBS11 0x00dc
++#define HMATRIX2_PRAS12 0x00e0
++#define HMATRIX2_PRBS12 0x00e4
++#define HMATRIX2_PRAS13 0x00e8
++#define HMATRIX2_PRBS13 0x00ec
++#define HMATRIX2_PRAS14 0x00f0
++#define HMATRIX2_PRBS14 0x00f4
++#define HMATRIX2_PRAS15 0x00f8
++#define HMATRIX2_PRBS15 0x00fc
++#define HMATRIX2_MRCR 0x0100
++#define HMATRIX2_SFR0 0x0110
++#define HMATRIX2_SFR1 0x0114
++#define HMATRIX2_SFR2 0x0118
++#define HMATRIX2_SFR3 0x011c
++#define HMATRIX2_SFR4 0x0120
++#define HMATRIX2_SFR5 0x0124
++#define HMATRIX2_SFR6 0x0128
++#define HMATRIX2_SFR7 0x012c
++#define HMATRIX2_SFR8 0x0130
++#define HMATRIX2_SFR9 0x0134
++#define HMATRIX2_SFR10 0x0138
++#define HMATRIX2_SFR11 0x013c
++#define HMATRIX2_SFR12 0x0140
++#define HMATRIX2_SFR13 0x0144
++#define HMATRIX2_SFR14 0x0148
++#define HMATRIX2_SFR15 0x014c
++#define HMATRIX2_VERSION 0x01fc
++
++/* Bitfields in MCFG0 */
++#define HMATRIX2_ULBT_OFFSET 0
++#define HMATRIX2_ULBT_SIZE 3
++
++/* Bitfields in MCFG1 */
++
++/* Bitfields in MCFG2 */
++
++/* Bitfields in MCFG3 */
++
++/* Bitfields in MCFG4 */
++
++/* Bitfields in MCFG5 */
++
++/* Bitfields in MCFG6 */
++
++/* Bitfields in MCFG7 */
++
++/* Bitfields in MCFG8 */
++
++/* Bitfields in MCFG9 */
++
++/* Bitfields in MCFG10 */
++
++/* Bitfields in MCFG11 */
++
++/* Bitfields in MCFG12 */
++
++/* Bitfields in MCFG13 */
++
++/* Bitfields in MCFG14 */
++
++/* Bitfields in MCFG15 */
++
++/* Bitfields in SCFG0 */
++#define HMATRIX2_SLOT_CYCLE_OFFSET 0
++#define HMATRIX2_SLOT_CYCLE_SIZE 8
++#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
++#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
++#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
++#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
++#define HMATRIX2_ARBT_OFFSET 24
++#define HMATRIX2_ARBT_SIZE 2
++
++/* Bitfields in SCFG1 */
++
++/* Bitfields in SCFG2 */
++
++/* Bitfields in SCFG3 */
++
++/* Bitfields in SCFG4 */
++
++/* Bitfields in SCFG5 */
++
++/* Bitfields in SCFG6 */
++
++/* Bitfields in SCFG7 */
++
++/* Bitfields in SCFG8 */
++
++/* Bitfields in SCFG9 */
++
++/* Bitfields in SCFG10 */
++
++/* Bitfields in SCFG11 */
++
++/* Bitfields in SCFG12 */
++
++/* Bitfields in SCFG13 */
++
++/* Bitfields in SCFG14 */
++
++/* Bitfields in SCFG15 */
++
++/* Bitfields in PRAS */
++#define HMATRIX2_M0PR_OFFSET 0
++#define HMATRIX2_M0PR_SIZE 4
++#define HMATRIX2_M1PR_OFFSET 4
++#define HMATRIX2_M1PR_SIZE 4
++#define HMATRIX2_M2PR_OFFSET 8
++#define HMATRIX2_M2PR_SIZE 4
++#define HMATRIX2_M3PR_OFFSET 12
++#define HMATRIX2_M3PR_SIZE 4
++#define HMATRIX2_M4PR_OFFSET 16
++#define HMATRIX2_M4PR_SIZE 4
++#define HMATRIX2_M5PR_OFFSET 20
++#define HMATRIX2_M5PR_SIZE 4
++#define HMATRIX2_M6PR_OFFSET 24
++#define HMATRIX2_M6PR_SIZE 4
++#define HMATRIX2_M7PR_OFFSET 28
++#define HMATRIX2_M7PR_SIZE 4
++
++/* Bitfields in PRBS */
++#define HMATRIX2_M8PR_OFFSET 0
++#define HMATRIX2_M8PR_SIZE 4
++#define HMATRIX2_M9PR_OFFSET 4
++#define HMATRIX2_M9PR_SIZE 4
++#define HMATRIX2_M10PR_OFFSET 8
++#define HMATRIX2_M10PR_SIZE 4
++#define HMATRIX2_M11PR_OFFSET 12
++#define HMATRIX2_M11PR_SIZE 4
++#define HMATRIX2_M12PR_OFFSET 16
++#define HMATRIX2_M12PR_SIZE 4
++#define HMATRIX2_M13PR_OFFSET 20
++#define HMATRIX2_M13PR_SIZE 4
++#define HMATRIX2_M14PR_OFFSET 24
++#define HMATRIX2_M14PR_SIZE 4
++#define HMATRIX2_M15PR_OFFSET 28
++#define HMATRIX2_M15PR_SIZE 4
++
++/* Bitfields in PRAS1 */
++
++/* Bitfields in PRBS1 */
++
++/* Bitfields in PRAS2 */
++
++/* Bitfields in PRBS2 */
++
++/* Bitfields in PRAS3 */
++
++/* Bitfields in PRBS3 */
++
++/* Bitfields in PRAS4 */
++
++/* Bitfields in PRBS4 */
++
++/* Bitfields in PRAS5 */
++
++/* Bitfields in PRBS5 */
++
++/* Bitfields in PRAS6 */
++
++/* Bitfields in PRBS6 */
++
++/* Bitfields in PRAS7 */
++
++/* Bitfields in PRBS7 */
++
++/* Bitfields in PRAS8 */
++
++/* Bitfields in PRBS8 */
++
++/* Bitfields in PRAS9 */
++
++/* Bitfields in PRBS9 */
++
++/* Bitfields in PRAS10 */
++
++/* Bitfields in PRBS10 */
++
++/* Bitfields in PRAS11 */
++
++/* Bitfields in PRBS11 */
++
++/* Bitfields in PRAS12 */
++
++/* Bitfields in PRBS12 */
++
++/* Bitfields in PRAS13 */
++
++/* Bitfields in PRBS13 */
++
++/* Bitfields in PRAS14 */
++
++/* Bitfields in PRBS14 */
++
++/* Bitfields in PRAS15 */
++
++/* Bitfields in PRBS15 */
++
++/* Bitfields in MRCR */
++#define HMATRIX2_RBC0_OFFSET 0
++#define HMATRIX2_RBC0_SIZE 1
++#define HMATRIX2_RBC1_OFFSET 1
++#define HMATRIX2_RBC1_SIZE 1
++#define HMATRIX2_RBC2_OFFSET 2
++#define HMATRIX2_RBC2_SIZE 1
++#define HMATRIX2_RBC3_OFFSET 3
++#define HMATRIX2_RBC3_SIZE 1
++#define HMATRIX2_RBC4_OFFSET 4
++#define HMATRIX2_RBC4_SIZE 1
++#define HMATRIX2_RBC5_OFFSET 5
++#define HMATRIX2_RBC5_SIZE 1
++#define HMATRIX2_RBC6_OFFSET 6
++#define HMATRIX2_RBC6_SIZE 1
++#define HMATRIX2_RBC7_OFFSET 7
++#define HMATRIX2_RBC7_SIZE 1
++#define HMATRIX2_RBC8_OFFSET 8
++#define HMATRIX2_RBC8_SIZE 1
++#define HMATRIX2_RBC9_OFFSET 9
++#define HMATRIX2_RBC9_SIZE 1
++#define HMATRIX2_RBC10_OFFSET 10
++#define HMATRIX2_RBC10_SIZE 1
++#define HMATRIX2_RBC11_OFFSET 11
++#define HMATRIX2_RBC11_SIZE 1
++#define HMATRIX2_RBC12_OFFSET 12
++#define HMATRIX2_RBC12_SIZE 1
++#define HMATRIX2_RBC13_OFFSET 13
++#define HMATRIX2_RBC13_SIZE 1
++#define HMATRIX2_RBC14_OFFSET 14
++#define HMATRIX2_RBC14_SIZE 1
++#define HMATRIX2_RBC15_OFFSET 15
++#define HMATRIX2_RBC15_SIZE 1
++
++/* Bitfields in SFR0 */
++#define HMATRIX2_SFR_OFFSET 0
++#define HMATRIX2_SFR_SIZE 32
++
++/* Bitfields in SFR1 */
++
++/* Bitfields in SFR2 */
++
++/* Bitfields in SFR3 */
++
++/* Bitfields in SFR4 */
++#define HMATRIX2_CS1A_OFFSET 1
++#define HMATRIX2_CS1A_SIZE 1
++#define HMATRIX2_CS3A_OFFSET 3
++#define HMATRIX2_CS3A_SIZE 1
++#define HMATRIX2_CS4A_OFFSET 4
++#define HMATRIX2_CS4A_SIZE 1
++#define HMATRIX2_CS5A_OFFSET 5
++#define HMATRIX2_CS5A_SIZE 1
++#define HMATRIX2_DBPUC_OFFSET 8
++#define HMATRIX2_DBPUC_SIZE 1
++
++/* Bitfields in SFR5 */
++
++/* Bitfields in SFR6 */
++
++/* Bitfields in SFR7 */
++
++/* Bitfields in SFR8 */
++
++/* Bitfields in SFR9 */
++
++/* Bitfields in SFR10 */
++
++/* Bitfields in SFR11 */
++
++/* Bitfields in SFR12 */
++
++/* Bitfields in SFR13 */
++
++/* Bitfields in SFR14 */
++
++/* Bitfields in SFR15 */
++
++/* Bitfields in VERSION */
++#define HMATRIX2_VERSION_OFFSET 0
++#define HMATRIX2_VERSION_SIZE 12
++#define HMATRIX2_MFN_OFFSET 16
++#define HMATRIX2_MFN_SIZE 3
++
++/* Constants for ULBT */
++#define HMATRIX2_ULBT_INFINITE 0
++#define HMATRIX2_ULBT_SINGLE 1
++#define HMATRIX2_ULBT_FOUR_BEAT 2
++#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
++
++/* Constants for DEFMSTR_TYPE */
++#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
++#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
++#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
++
++/* Constants for ARBT */
++#define HMATRIX2_ARBT_ROUND_ROBIN 0
++#define HMATRIX2_ARBT_FIXED_PRIORITY 1
++
++/* Bit manipulation macros */
++#define HMATRIX2_BIT(name) (1 << HMATRIX2_##name##_OFFSET)
++#define HMATRIX2_BF(name,value) (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) << HMATRIX2_##name##_OFFSET)
++#define HMATRIX2_BFEXT(name,value) (((value) >> HMATRIX2_##name##_OFFSET) & ((1 << HMATRIX2_##name##_SIZE) - 1))
++#define HMATRIX2_BFINS(name,value,old) (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) << HMATRIX2_##name##_OFFSET)) | HMATRIX2_BF(name,value))
++
++/* Register access macros */
++#define hmatrix2_readl(base,reg) \
++ __raw_readl(base + HMATRIX2_##reg)
++#define hmatrix2_writel(base,reg,value) \
++ __raw_writel((value), base + HMATRIX2_##reg)
++
++#endif /* __ASM_AVR32_HMATRIX2_H__ */
+Index: linux-2.6.18/arch/avr32/mach-at32ap/at32ap7000.c
+===================================================================
+--- linux-2.6.18.orig/arch/avr32/mach-at32ap/at32ap7000.c 2006-11-03 14:57:26.000000000 +0100
++++ linux-2.6.18/arch/avr32/mach-at32ap/at32ap7000.c 2006-11-03 15:25:01.000000000 +0100
+@@ -466,6 +466,15 @@
+ .users = 1,
+ };
+
++static struct clk hmatrix2_clk = {
++ .name = "hmatrix2",
++ .parent = &pbb_clk,
++ .mode = pbb_clk_mode,
++ .get_rate = pbb_clk_get_rate,
++ .users = 1,
++ .index = 2,
++};
++
+ static struct resource dmac0_resource[] = {
+ {
+ .start = 0xff200000,
+@@ -1096,6 +1096,7 @@
+ &pdc_pclk,
+ &dmac0_hclk,
+ &pico_clk,
++ &hmatrix2_clk,
+ &pio0_mck,
+ &pio1_mck,
+ &pio2_mck,
diff --git a/packages/linux/linux-2.6.18/add-ide-header.patch b/packages/linux/linux-2.6.18/add-ide-header.patch
new file mode 100644
index 0000000000..76bd35bfac
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-ide-header.patch
@@ -0,0 +1,41 @@
+Index: linux-2.6.18/include/asm-avr32/ide.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18/include/asm-avr32/ide.h 2006-10-24 15:12:02.000000000 +0200
+@@ -0,0 +1,36 @@
++/*
++ * linux/include/asm-arm/ide.h
++ *
++ * Copyright (C) 1994-1996 Linus Torvalds & authors
++ */
++
++/*
++ * This file contains the ARM architecture specific IDE code.
++ */
++
++#ifndef __ASMAVR32_IDE_H
++#define __ASMAVR32_IDE_H
++
++#ifdef __KERNEL__
++
++#ifndef MAX_HWIFS
++#define MAX_HWIFS 4
++#endif
++
++#if !defined(CONFIG_ARCH_L7200)
++# define IDE_ARCH_OBSOLETE_INIT
++# ifdef CONFIG_ARCH_CLPS7500
++# define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
++# else
++# define ide_default_io_ctl(base) (0)
++# endif
++#endif /* !ARCH_L7200 */
++
++#define __ide_mm_insw(port,addr,len) readsw(port,addr,len)
++#define __ide_mm_insl(port,addr,len) readsl(port,addr,len)
++#define __ide_mm_outsw(port,addr,len) writesw(port,addr,len)
++#define __ide_mm_outsl(port,addr,len) writesl(port,addr,len)
++
++#endif /* __KERNEL__ */
++
++#endif /* __ASMAVR32_IDE_H */
diff --git a/packages/linux/linux-2.6.18/add-intc_pending_irq-to-intc.patch b/packages/linux/linux-2.6.18/add-intc_pending_irq-to-intc.patch
new file mode 100644
index 0000000000..6d99de84b1
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-intc_pending_irq-to-intc.patch
@@ -0,0 +1,10 @@
+--- linux-2.6.18.orig/arch/avr32/mach-at32ap/intc.c 2006-11-06 14:36:50.000000000 +0100
++++ linux-2.6.18/arch/avr32/mach-at32ap/intc.c 2006-11-06 15:09:39.000000000 +0100
+@@ -131,3 +131,7 @@
+ panic("Interrupt controller initialization failed!\n");
+ }
+
++unsigned long intc_get_pending(int group)
++{
++ return intc_readl(&intc0, INTREQ0 + 4 * group);
++}
diff --git a/packages/linux/linux-2.6.18/add-mach-specific-kconfig.patch b/packages/linux/linux-2.6.18/add-mach-specific-kconfig.patch
new file mode 100644
index 0000000000..6f6e8f4833
--- /dev/null
+++ b/packages/linux/linux-2.6.18/add-mach-specific-kconfig.patch
@@ -0,0 +1,30 @@
+---
+ arch/avr32/Kconfig | 2 ++
+ arch/avr32/mach-at32ap/Kconfig | 7 +++++++
+ 2 files changed, 9 insertions(+)
+
+Index: linux-2.6.18-avr32/arch/avr32/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/arch/avr32/Kconfig 2006-10-24 13:30:29.000000000 +0200
++++ linux-2.6.18-avr32/arch/avr32/Kconfig 2006-10-24 13:32:07.000000000 +0200
+@@ -107,6 +107,8 @@ config LOADER_U_BOOT
+ bool "U-Boot (or similar) bootloader"
+ endchoice
+
++source "arch/avr32/mach-at32ap/Kconfig"
++
+ config LOAD_ADDRESS
+ hex
+ default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP7000=y
+Index: linux-2.6.18-avr32/arch/avr32/mach-at32ap/Kconfig
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/arch/avr32/mach-at32ap/Kconfig 2006-10-24 13:46:51.000000000 +0200
+@@ -0,0 +1,7 @@
++if PLATFORM_AT32AP
++
++menu "Atmel AVR32 AP options"
++
++endmenu
++
++endif
diff --git a/packages/linux/linux-2.6.18/at32-dac-oss-driver-clk-fix.patch b/packages/linux/linux-2.6.18/at32-dac-oss-driver-clk-fix.patch
new file mode 100644
index 0000000000..927cdc5ece
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at32-dac-oss-driver-clk-fix.patch
@@ -0,0 +1,175 @@
+---
+ sound/oss/at32dac.c | 72 +++++++++++++++++++++++++++++++---------------------
+ 1 file changed, 43 insertions(+), 29 deletions(-)
+
+Index: linux-2.6.18-avr32/sound/oss/at32dac.c
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/oss/at32dac.c 2006-11-01 14:30:47.000000000 +0100
++++ linux-2.6.18-avr32/sound/oss/at32dac.c 2006-11-01 14:32:05.000000000 +0100
+@@ -71,6 +71,7 @@ struct at32_dac {
+ struct dma_request_cyclic req;
+
+ struct clk *mck;
++ struct clk *sample_clk;
+ struct platform_device *pdev;
+ int busy;
+ int playing;
+@@ -116,24 +117,6 @@ static void at32dac_update_dma_tail(stru
+ }
+ }
+
+-static int at32dac_start_genclock(struct at32_dac *dac)
+-{
+- unsigned int div;
+-
+- div = ((clk_get_rate(boot_cpu_data.clk) + 256 * dac->dsp_settings.sample_rate)
+- / (512 * dac->dsp_settings.sample_rate) - 1);
+- pr_debug("Real sample rate: %llu (div=%u)\n",
+- boot_cpu_data.cpu_hz / (512 * (div + 1)), div);
+- writel((div << 8) | 0x16, (void __iomem *)(0xfff00060 + 4 * 6));
+-
+- return 0;
+-}
+-
+-static void at32dac_stop_genclock(struct at32_dac *dac)
+-{
+- writel(0, (void __iomem *)(0xfff00060 + 4 * 6));
+-}
+-
+ static int at32dac_start(struct at32_dac *dac)
+ {
+ int ret;
+@@ -143,13 +126,11 @@ static int at32dac_start(struct at32_dac
+
+ memset(dac->dma.buf, 0, DMA_BUFFER_SIZE);
+
+- ret = at32dac_start_genclock(dac);
+- if (ret)
+- return ret;
++ clk_enable(dac->sample_clk);
+
+ ret = dma_prepare_request_cyclic(dac->req.req.dmac, &dac->req);
+ if (ret)
+- goto out_stop_genclock;
++ goto out_stop_clock;
+
+ pr_debug("Starting DMA...\n");
+ ret = dma_start_request(dac->req.req.dmac, dac->req.req.channel);
+@@ -164,8 +145,8 @@ static int at32dac_start(struct at32_dac
+ out_stop_request:
+ dma_stop_request(dac->req.req.dmac,
+ dac->req.req.channel);
+-out_stop_genclock:
+- at32dac_stop_genclock(dac);
++out_stop_clock:
++ clk_disable(dac->sample_clk);
+ return ret;
+ }
+
+@@ -176,7 +157,7 @@ static int at32dac_stop(struct at32_dac
+ dac_writel(dac, DATA, 0);
+ dac_writel(dac, CTRL, 0);
+ dac->playing = 0;
+- at32dac_stop_genclock(dac);
++ clk_disable(dac->sample_clk);
+ }
+
+ return 0;
+@@ -360,6 +341,26 @@ static int at32dac_set_format(struct at3
+ return 0;
+ }
+
++static int at32dac_set_sample_rate(struct at32_dac *dac, unsigned long rate)
++{
++ unsigned long new_rate;
++ int ret;
++
++ ret = clk_set_rate(dac->sample_clk, 256 * rate);
++ if (ret < 0)
++ return ret;
++
++ /* TODO: mplayer seems to have a problem with this */
++#if 0
++ new_rate = clk_get_rate(dac->sample_clk);
++ dac->dsp_settings.sample_rate = new_rate / 256;
++#else
++ dac->dsp_settings.sample_rate = rate;
++#endif
++
++ return 0;
++}
++
+ static ssize_t at32dac_dsp_write(struct file *file,
+ const char __user *buffer,
+ size_t count, loff_t *ppos)
+@@ -449,7 +450,9 @@ static int at32dac_dsp_ioctl(struct inod
+ return -EFAULT;
+ if (val >= 0) {
+ at32dac_stop(dac);
+- dac->dsp_settings.sample_rate = val;
++ ret = at32dac_set_sample_rate(dac, val);
++ if (ret)
++ return ret;
+ }
+ return put_user(dac->dsp_settings.sample_rate, up);
+
+@@ -534,10 +537,11 @@ static int at32dac_dsp_open(struct inode
+ dac->dma.head = dac->dma.tail = 0;
+
+ /* FIXME: What are the correct defaults? */
+- dac->dsp_settings.format = AFMT_S16_BE;
+ dac->dsp_settings.channels = 2;
+- dac->dsp_settings.sample_rate = 8000;
+- dac->dsp_settings.input_order = 2;
++ at32dac_set_format(dac, AFMT_S16_BE);
++ ret = at32dac_set_sample_rate(dac, 8000);
++ if (ret)
++ goto out;
+
+ file->private_data = dac;
+ dac->busy = 1;
+@@ -578,6 +582,7 @@ static int __devinit at32dac_probe(struc
+ struct at32_dac *dac;
+ struct resource *regs;
+ struct clk *mck;
++ struct clk *sample_clk;
+ int irq;
+ int ret;
+
+@@ -594,6 +599,11 @@ static int __devinit at32dac_probe(struc
+ mck = clk_get(&pdev->dev, "mck");
+ if (IS_ERR(mck))
+ return PTR_ERR(mck);
++ sample_clk = clk_get(&pdev->dev, "sample_clk");
++ if (IS_ERR(sample_clk)) {
++ ret = PTR_ERR(sample_clk);
++ goto out_put_mck;
++ }
+ clk_enable(mck);
+
+ ret = -ENOMEM;
+@@ -606,6 +616,7 @@ static int __devinit at32dac_probe(struc
+ init_waitqueue_head(&dac->write_wait);
+ dac->pdev = pdev;
+ dac->mck = mck;
++ dac->sample_clk = sample_clk;
+
+ dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
+ if (!dac->regs)
+@@ -658,6 +669,8 @@ out_free_dac:
+ kfree(dac);
+ out_disable_clk:
+ clk_disable(mck);
++ clk_put(sample_clk);
++out_put_mck:
+ clk_put(mck);
+ return ret;
+ }
+@@ -673,6 +686,7 @@ static int __devexit at32dac_remove(stru
+ free_irq(platform_get_irq(pdev, 0), dac);
+ iounmap(dac->regs);
+ clk_disable(dac->mck);
++ clk_put(dac->sample_clk);
+ clk_put(dac->mck);
+ kfree(dac);
+ platform_set_drvdata(pdev, NULL);
diff --git a/packages/linux/linux-2.6.18/at32-dac-oss-driver.patch b/packages/linux/linux-2.6.18/at32-dac-oss-driver.patch
new file mode 100644
index 0000000000..92a17f9af3
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at32-dac-oss-driver.patch
@@ -0,0 +1,819 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: HÃ¥vard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Apr 3 17:38:29 2006 +0200
+Subject: [PATCH] OSS driver for the AT32 on-chip digital DAC
+
+---
+
+ sound/oss/Kconfig | 4
+ sound/oss/Makefile | 1
+ sound/oss/at32dac.c | 707 ++++++++++++++++++++++++++++++++++++++++++++++++++++
+ sound/oss/at32dac.h | 65 ++++
+ 4 files changed, 777 insertions(+)
+
+Index: linux-2.6.18-avr32/sound/oss/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/oss/Kconfig 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/sound/oss/Kconfig 2006-11-02 15:56:20.000000000 +0100
+@@ -869,3 +869,7 @@ config SOUND_SH_DAC_AUDIO_CHANNEL
+ int "DAC channel"
+ default "1"
+ depends on SOUND_SH_DAC_AUDIO
++
++config SOUND_AT32_DAC
++ tristate "Atmel AT32 On-chip DAC support"
++ depends on SOUND_PRIME && AVR32
+Index: linux-2.6.18-avr32/sound/oss/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/oss/Makefile 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/sound/oss/Makefile 2006-11-02 15:56:20.000000000 +0100
+@@ -10,6 +10,7 @@ obj-$(CONFIG_SOUND_CS4232) += cs4232.o a
+
+ # Please leave it as is, cause the link order is significant !
+
++obj-$(CONFIG_SOUND_AT32_DAC) += at32dac.o
+ obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
+ obj-$(CONFIG_SOUND_HAL2) += hal2.o
+ obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
+Index: linux-2.6.18-avr32/sound/oss/at32dac.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/sound/oss/at32dac.c 2006-11-02 15:56:20.000000000 +0100
+@@ -0,0 +1,707 @@
++/*
++ * OSS Sound Driver for the Atmel AT32 on-chip DAC.
++ *
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/clk.h>
++#include <linux/dma-mapping.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/sound.h>
++#include <linux/soundcard.h>
++
++#include <asm/byteorder.h>
++#include <asm/dma-controller.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++/* We want to use the "bizarre" swap-bytes-in-each-halfword macro */
++#include <linux/byteorder/swabb.h>
++
++#include "at32dac.h"
++
++#define DMA_BUFFER_SIZE 32768
++#define DMA_PERIOD_SHIFT 10
++#define DMA_PERIOD_SIZE (1 << DMA_PERIOD_SHIFT)
++#define DMA_WRITE_THRESHOLD DMA_PERIOD_SIZE
++
++struct sound_settings {
++ unsigned int format;
++ unsigned int channels;
++ unsigned int sample_rate;
++ /* log2(bytes per sample) */
++ unsigned int input_order;
++};
++
++struct at32_dac {
++ spinlock_t lock;
++ void __iomem *regs;
++
++ /* head and tail refer to number of words */
++ struct {
++ u32 *buf;
++ int head;
++ int tail;
++ } dma;
++
++ struct semaphore sem;
++ wait_queue_head_t write_wait;
++
++ /*
++ * Read at most ucount bytes from ubuf, translate to 2-channel
++ * signed 16-bit big endian format and write to the DMA buffer
++ * as long as there is room left. Return the number of bytes
++ * successfully copied from ubuf, or -EFAULT if the first
++ * sample from ubuf couldn't be read. This function is not
++ * called unless there is room for at least one sample (4
++ * bytes) in the DMA buffer.
++ */
++ int (*trans)(struct at32_dac *dac, const char __user *ubuf,
++ size_t ucount);
++
++ struct sound_settings dsp_settings;
++ struct dma_request_cyclic req;
++
++ struct clk *mck;
++ struct platform_device *pdev;
++ int busy;
++ int playing;
++ int dev_dsp;
++};
++static struct at32_dac *the_dac;
++
++static inline unsigned int at32dac_get_head(struct at32_dac *dac)
++{
++ return dac->dma.head & ((DMA_BUFFER_SIZE / 4) - 1);
++}
++
++static inline unsigned int at32dac_get_tail(struct at32_dac *dac)
++{
++ return dac->dma.tail & ((DMA_BUFFER_SIZE / 4) - 1);
++}
++
++static inline unsigned int at32dac_dma_space(struct at32_dac *dac)
++{
++ unsigned int space;
++
++ space = ((dac->dma.tail - dac->dma.head - 1)
++ & ((DMA_BUFFER_SIZE / 4) - 1));
++ return space;
++}
++
++static void at32dac_update_dma_tail(struct at32_dac *dac)
++{
++ dma_addr_t dma_addr;
++ unsigned int new_tail;
++
++ if (dac->playing) {
++ dma_addr = dma_get_current_pos(dac->req.req.dmac,
++ dac->req.req.channel);
++ new_tail = (dma_addr - dac->req.buffer_start) / 4;
++ if (new_tail >= dac->dma.head
++ && (dac->dma.tail < dac->dma.head
++ || dac->dma.tail > new_tail))
++ printk(KERN_NOTICE "at32dac: underrun\n");
++ dac->dma.tail = new_tail;
++ pr_debug("update tail: 0x%x - 0x%x = %u\n",
++ dma_addr, dac->req.buffer_start, dac->dma.tail);
++ }
++}
++
++static int at32dac_start_genclock(struct at32_dac *dac)
++{
++ unsigned int div;
++
++ div = ((clk_get_rate(boot_cpu_data.clk) + 256 * dac->dsp_settings.sample_rate)
++ / (512 * dac->dsp_settings.sample_rate) - 1);
++ pr_debug("Real sample rate: %llu (div=%u)\n",
++ boot_cpu_data.cpu_hz / (512 * (div + 1)), div);
++ writel((div << 8) | 0x16, (void __iomem *)(0xfff00060 + 4 * 6));
++
++ return 0;
++}
++
++static void at32dac_stop_genclock(struct at32_dac *dac)
++{
++ writel(0, (void __iomem *)(0xfff00060 + 4 * 6));
++}
++
++static int at32dac_start(struct at32_dac *dac)
++{
++ int ret;
++
++ if (dac->playing)
++ return 0;
++
++ memset(dac->dma.buf, 0, DMA_BUFFER_SIZE);
++
++ ret = at32dac_start_genclock(dac);
++ if (ret)
++ return ret;
++
++ ret = dma_prepare_request_cyclic(dac->req.req.dmac, &dac->req);
++ if (ret)
++ goto out_stop_genclock;
++
++ pr_debug("Starting DMA...\n");
++ ret = dma_start_request(dac->req.req.dmac, dac->req.req.channel);
++ if (ret)
++ goto out_stop_request;
++
++ dac_writel(dac, CTRL, DAC_BIT(EN));
++ dac->playing = 1;
++
++ return 0;
++
++out_stop_request:
++ dma_stop_request(dac->req.req.dmac,
++ dac->req.req.channel);
++out_stop_genclock:
++ at32dac_stop_genclock(dac);
++ return ret;
++}
++
++static int at32dac_stop(struct at32_dac *dac)
++{
++ if (dac->playing) {
++ dma_stop_request(dac->req.req.dmac, dac->req.req.channel);
++ dac_writel(dac, DATA, 0);
++ dac_writel(dac, CTRL, 0);
++ dac->playing = 0;
++ at32dac_stop_genclock(dac);
++ }
++
++ return 0;
++}
++
++static int at32dac_dma_prepare(struct at32_dac *dac)
++{
++ dac->dma.buf = dma_alloc_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
++ &dac->req.buffer_start, GFP_KERNEL);
++ if (!dac->dma.buf)
++ return -ENOMEM;
++
++ dac->dma.head = dac->dma.tail = 0;
++ dac->req.periods = DMA_BUFFER_SIZE / DMA_PERIOD_SIZE;
++ dac->req.buffer_size = DMA_BUFFER_SIZE;
++
++ return 0;
++}
++
++static void at32dac_dma_cleanup(struct at32_dac *dac)
++{
++ if (dac->dma.buf)
++ dma_free_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
++ dac->dma.buf, dac->req.buffer_start);
++ dac->dma.buf = NULL;
++}
++
++static void at32dac_dma_block_complete(struct dma_request *req)
++{
++ struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
++ struct at32_dac *dac = container_of(creq, struct at32_dac, req);
++
++ wake_up(&dac->write_wait);
++}
++
++static void at32dac_dma_error(struct dma_request *req)
++{
++ printk(KERN_ERR "at32dac: DMA error\n");
++}
++
++static irqreturn_t at32dac_interrupt(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct at32_dac *dac = dev_id;
++ u32 status;
++
++ status = dac_readl(dac, INT_STATUS);
++ if (status & DAC_BIT(UNDERRUN)) {
++ printk(KERN_ERR "at32dac: Underrun detected\n");
++ dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
++ } else {
++ printk(KERN_ERR "at32dac: Spurious interrupt: status=0x%x\n",
++ status);
++ dac_writel(dac, INT_CLR, status);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static ssize_t trans_s16be(struct at32_dac *dac, const char __user *ubuf,
++ size_t ucount)
++{
++ ssize_t ret;
++
++ if (dac->dsp_settings.channels == 2) {
++ const u32 __user *up = (const u32 __user *)ubuf;
++ u32 sample;
++
++ for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
++ if (!at32dac_dma_space(dac))
++ break;
++
++ if (unlikely(__get_user(sample, up++))) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++ dac->dma.buf[at32dac_get_head(dac)] = sample;
++ dac->dma.head++;
++ }
++ } else {
++ const u16 __user *up = (const u16 __user *)ubuf;
++ u16 sample;
++
++ for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
++ if (!at32dac_dma_space(dac))
++ break;
++
++ if (unlikely(__get_user(sample, up++))) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++ dac->dma.buf[at32dac_get_head(dac)]
++ = (sample << 16) | sample;
++ dac->dma.head++;
++ }
++ }
++
++ return ret;
++}
++
++static ssize_t trans_s16le(struct at32_dac *dac, const char __user *ubuf,
++ size_t ucount)
++{
++ ssize_t ret;
++
++ if (dac->dsp_settings.channels == 2) {
++ const u32 __user *up = (const u32 __user *)ubuf;
++ u32 sample;
++
++ for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
++ if (!at32dac_dma_space(dac))
++ break;
++
++ if (unlikely(__get_user(sample, up++))) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++ /* Swap bytes in each halfword */
++ dac->dma.buf[at32dac_get_head(dac)] = swahb32(sample);
++ dac->dma.head++;
++ }
++ } else {
++ const u16 __user *up = (const u16 __user *)ubuf;
++ u16 sample;
++
++ for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
++ if (!at32dac_dma_space(dac))
++ break;
++
++ if (unlikely(__get_user(sample, up++))) {
++ if (ret == 0)
++ ret = -EFAULT;
++ break;
++ }
++ sample = swab16(sample);
++ dac->dma.buf[at32dac_get_head(dac)]
++ = (sample << 16) | sample;
++ dac->dma.head++;
++ }
++ }
++
++ return ret;
++}
++
++static ssize_t at32dac_dma_translate_from_user(struct at32_dac *dac,
++ const char __user *buffer,
++ size_t count)
++{
++ /* At least one buffer must be available at this point */
++ pr_debug("at32dac: Copying %zu bytes from user...\n", count);
++
++ return dac->trans(dac, buffer, count);
++}
++
++static int at32dac_set_format(struct at32_dac *dac, int format)
++{
++ unsigned int order;
++
++ switch (format) {
++ case AFMT_S16_BE:
++ order = 1;
++ dac->trans = trans_s16be;
++ break;
++ case AFMT_S16_LE:
++ order = 1;
++ dac->trans = trans_s16le;
++ break;
++ default:
++ printk("at32dac: Unsupported format: %d\n", format);
++ return -EINVAL;
++ }
++
++ if (dac->dsp_settings.channels == 2)
++ order++;
++
++ dac->dsp_settings.input_order = order;
++ dac->dsp_settings.format = format;
++ return 0;
++}
++
++static ssize_t at32dac_dsp_write(struct file *file,
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct at32_dac *dac = file->private_data;
++ DECLARE_WAITQUEUE(wait, current);
++ unsigned int avail;
++ ssize_t copied;
++ ssize_t ret;
++
++ /* Avoid address space checking in the translation functions */
++ if (!access_ok(buffer, count, VERIFY_READ))
++ return -EFAULT;
++
++ down(&dac->sem);
++
++ if (!dac->dma.buf) {
++ ret = at32dac_dma_prepare(dac);
++ if (ret)
++ goto out;
++ }
++
++ add_wait_queue(&dac->write_wait, &wait);
++ ret = 0;
++ while (count > 0) {
++ do {
++ at32dac_update_dma_tail(dac);
++ avail = at32dac_dma_space(dac);
++ set_current_state(TASK_INTERRUPTIBLE);
++ if (avail >= DMA_WRITE_THRESHOLD)
++ break;
++
++ if (file->f_flags & O_NONBLOCK) {
++ if (!ret)
++ ret = -EAGAIN;
++ goto out;
++ }
++
++ pr_debug("Going to wait (avail = %u, count = %zu)\n",
++ avail, count);
++
++ up(&dac->sem);
++ schedule();
++ if (signal_pending(current)) {
++ if (!ret)
++ ret = -ERESTARTSYS;
++ goto out_nosem;
++ }
++ down(&dac->sem);
++ } while (1);
++
++ copied = at32dac_dma_translate_from_user(dac, buffer, count);
++ if (copied < 0) {
++ if (!ret)
++ ret = -EFAULT;
++ goto out;
++ }
++
++ at32dac_start(dac);
++
++ count -= copied;
++ ret += copied;
++ }
++
++out:
++ up(&dac->sem);
++out_nosem:
++ remove_wait_queue(&dac->write_wait, &wait);
++ set_current_state(TASK_RUNNING);
++ return ret;
++}
++
++static int at32dac_dsp_ioctl(struct inode *inode, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ struct at32_dac *dac = file->private_data;
++ int __user *up = (int __user *)arg;
++ struct audio_buf_info abinfo;
++ int val, ret;
++
++ switch (cmd) {
++ case OSS_GETVERSION:
++ return put_user(SOUND_VERSION, up);
++
++ case SNDCTL_DSP_SPEED:
++ if (get_user(val, up))
++ return -EFAULT;
++ if (val >= 0) {
++ at32dac_stop(dac);
++ dac->dsp_settings.sample_rate = val;
++ }
++ return put_user(dac->dsp_settings.sample_rate, up);
++
++ case SNDCTL_DSP_STEREO:
++ if (get_user(val, up))
++ return -EFAULT;
++ at32dac_stop(dac);
++ if (val && dac->dsp_settings.channels == 1)
++ dac->dsp_settings.input_order++;
++ else if (!val && dac->dsp_settings.channels != 1)
++ dac->dsp_settings.input_order--;
++ dac->dsp_settings.channels = val ? 2 : 1;
++ return 0;
++
++ case SNDCTL_DSP_CHANNELS:
++ if (get_user(val, up))
++ return -EFAULT;
++
++ if (val) {
++ if (val < 0 || val > 2)
++ return -EINVAL;
++
++ at32dac_stop(dac);
++ dac->dsp_settings.input_order
++ += val - dac->dsp_settings.channels;
++ dac->dsp_settings.channels = val;
++ }
++ return put_user(val, (int *)arg);
++
++ case SNDCTL_DSP_GETFMTS:
++ return put_user(AFMT_S16_BE | AFMT_S16_BE, up);
++
++ case SNDCTL_DSP_SETFMT:
++ if (get_user(val, up))
++ return -EFAULT;
++
++ if (val == AFMT_QUERY) {
++ val = dac->dsp_settings.format;
++ } else {
++ ret = at32dac_set_format(dac, val);
++ if (ret)
++ return ret;
++ }
++ return put_user(val, up);
++
++ case SNDCTL_DSP_GETOSPACE:
++ at32dac_update_dma_tail(dac);
++ abinfo.fragsize = ((1 << dac->dsp_settings.input_order)
++ * (DMA_PERIOD_SIZE / 4));
++ abinfo.bytes = (at32dac_dma_space(dac)
++ << dac->dsp_settings.input_order);
++ abinfo.fragstotal = ((DMA_BUFFER_SIZE * 4)
++ >> (DMA_PERIOD_SHIFT
++ + dac->dsp_settings.input_order));
++ abinfo.fragments = ((abinfo.bytes
++ >> dac->dsp_settings.input_order)
++ / (DMA_PERIOD_SIZE / 4));
++ pr_debug("fragments=%d fragstotal=%d fragsize=%d bytes=%d\n",
++ abinfo.fragments, abinfo.fragstotal, abinfo.fragsize,
++ abinfo.bytes);
++ return copy_to_user(up, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
++
++ default:
++ printk("at32dac: Unimplemented ioctl cmd: 0x%x\n", cmd);
++ return -EINVAL;
++ }
++}
++
++static int at32dac_dsp_open(struct inode *inode, struct file *file)
++{
++ struct at32_dac *dac = the_dac;
++ int ret;
++
++ if (file->f_mode & FMODE_READ)
++ return -ENXIO;
++
++ down(&dac->sem);
++ ret = -EBUSY;
++ if (dac->busy)
++ goto out;
++
++ dac->dma.head = dac->dma.tail = 0;
++
++ /* FIXME: What are the correct defaults? */
++ dac->dsp_settings.format = AFMT_S16_BE;
++ dac->dsp_settings.channels = 2;
++ dac->dsp_settings.sample_rate = 8000;
++ dac->dsp_settings.input_order = 2;
++
++ file->private_data = dac;
++ dac->busy = 1;
++
++ ret = 0;
++
++out:
++ up(&dac->sem);
++ return ret;
++}
++
++static int at32dac_dsp_release(struct inode *inode, struct file *file)
++{
++ struct at32_dac *dac = file->private_data;
++
++ down(&dac->sem);
++
++ at32dac_stop(dac);
++ at32dac_dma_cleanup(dac);
++ dac->busy = 0;
++
++ up(&dac->sem);
++
++ return 0;
++}
++
++static struct file_operations at32dac_dsp_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .write = at32dac_dsp_write,
++ .ioctl = at32dac_dsp_ioctl,
++ .open = at32dac_dsp_open,
++ .release = at32dac_dsp_release,
++};
++
++static int __devinit at32dac_probe(struct platform_device *pdev)
++{
++ struct at32_dac *dac;
++ struct resource *regs;
++ struct clk *mck;
++ int irq;
++ int ret;
++
++ if (the_dac)
++ return -EBUSY;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++
++ mck = clk_get(&pdev->dev, "mck");
++ if (IS_ERR(mck))
++ return PTR_ERR(mck);
++ clk_enable(mck);
++
++ ret = -ENOMEM;
++ dac = kzalloc(sizeof(struct at32_dac), GFP_KERNEL);
++ if (!dac)
++ goto out_disable_clk;
++
++ spin_lock_init(&dac->lock);
++ init_MUTEX(&dac->sem);
++ init_waitqueue_head(&dac->write_wait);
++ dac->pdev = pdev;
++ dac->mck = mck;
++
++ dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!dac->regs)
++ goto out_free_dac;
++
++ ret = request_irq(irq, at32dac_interrupt, 0, "dac", dac);
++ if (ret)
++ goto out_unmap_regs;
++
++ /* FIXME */
++ dac->req.req.dmac = find_dma_controller(0);
++ if (!dac->req.req.dmac)
++ goto out_free_irq;
++
++ ret = dma_alloc_channel(dac->req.req.dmac);
++ if (ret < 0)
++ goto out_free_irq;
++
++ dac->req.req.channel = ret;
++ dac->req.req.block_complete = at32dac_dma_block_complete;
++ dac->req.req.error = at32dac_dma_error;
++ dac->req.data_reg = regs->start + DAC_DATA;
++ dac->req.periph_id = 2; /* FIXME */
++ dac->req.direction = DMA_DIR_MEM_TO_PERIPH;
++ dac->req.width = DMA_WIDTH_32BIT;
++
++ /* Make sure the DAC is silent and disabled */
++ dac_writel(dac, DATA, 0);
++ dac_writel(dac, CTRL, 0);
++
++ ret = register_sound_dsp(&at32dac_dsp_fops, -1);
++ if (ret < 0)
++ goto out_free_dma;
++ dac->dev_dsp = ret;
++
++ /* TODO: Register mixer */
++
++ the_dac = dac;
++ platform_set_drvdata(pdev, dac);
++
++ return 0;
++
++out_free_dma:
++ dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
++out_free_irq:
++ free_irq(irq, dac);
++out_unmap_regs:
++ iounmap(dac->regs);
++out_free_dac:
++ kfree(dac);
++out_disable_clk:
++ clk_disable(mck);
++ clk_put(mck);
++ return ret;
++}
++
++static int __devexit at32dac_remove(struct platform_device *pdev)
++{
++ struct at32_dac *dac;
++
++ dac = platform_get_drvdata(pdev);
++ if (dac) {
++ unregister_sound_dsp(dac->dev_dsp);
++ dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
++ free_irq(platform_get_irq(pdev, 0), dac);
++ iounmap(dac->regs);
++ clk_disable(dac->mck);
++ clk_put(dac->mck);
++ kfree(dac);
++ platform_set_drvdata(pdev, NULL);
++ the_dac = NULL;
++ }
++
++ return 0;
++}
++
++static struct platform_driver at32dac_driver = {
++ .probe = at32dac_probe,
++ .remove = __devexit_p(at32dac_remove),
++ .driver = {
++ .name = "dac",
++ },
++};
++
++static int __init at32dac_init(void)
++{
++ return platform_driver_register(&at32dac_driver);
++}
++module_init(at32dac_init);
++
++static void __exit at32dac_exit(void)
++{
++ platform_driver_unregister(&at32dac_driver);
++}
++module_exit(at32dac_exit);
++
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_DESCRIPTION("DMA Sound Driver for the Atmel AT32 on-chip DAC");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.18-avr32/sound/oss/at32dac.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/sound/oss/at32dac.h 2006-11-02 15:57:01.000000000 +0100
+@@ -0,0 +1,65 @@
++/*
++ * Register definitions for the Atmel AT32 on-chip DAC.
++ *
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ASM_AVR32_DAC_H__
++#define __ASM_AVR32_DAC_H__
++
++/* DAC register offsets */
++#define DAC_DATA 0x0000
++#define DAC_CTRL 0x0008
++#define DAC_INT_MASK 0x000c
++#define DAC_INT_EN 0x0010
++#define DAC_INT_DIS 0x0014
++#define DAC_INT_CLR 0x0018
++#define DAC_INT_STATUS 0x001c
++#define DAC_PDC_DATA 0x0020
++
++/* Bitfields in DATA */
++#define DAC_DATA_OFFSET 0
++#define DAC_DATA_SIZE 32
++
++/* Bitfields in CTRL */
++#define DAC_SWAP_OFFSET 30
++#define DAC_SWAP_SIZE 1
++#define DAC_EN_OFFSET 31
++#define DAC_EN_SIZE 1
++
++/* Bitfields in INT_MASK */
++
++/* Bitfields in INT_EN */
++
++/* Bitfields in INT_DIS */
++#define DAC_TX_READY_OFFSET 29
++#define DAC_TX_READY_SIZE 1
++#define DAC_TX_BUFFER_EMPTY_OFFSET 30
++#define DAC_TX_BUFFER_EMPTY_SIZE 1
++#define DAC_CHANNEL_TX_END_OFFSET 31
++#define DAC_CHANNEL_TX_END_SIZE 1
++
++/* Bitfields in INT_CLR */
++#define DAC_UNDERRUN_OFFSET 28
++#define DAC_UNDERRUN_SIZE 1
++
++/* Bitfields in INT_STATUS */
++
++/* Bitfields in PDC_DATA */
++
++/* Bit manipulation macros */
++#define DAC_BIT(name) (1 << DAC_##name##_OFFSET)
++#define DAC_BF(name,value) (((value) & ((1 << DAC_##name##_SIZE) - 1)) << DAC_##name##_OFFSET)
++#define DAC_BFEXT(name,value) (((value) >> DAC_##name##_OFFSET) & ((1 << DAC_##name##_SIZE) - 1))
++#define DAC_BFINS(name,value,old) (((old) & ~(((1 << DAC_##name##_SIZE) - 1) << DAC_##name##_OFFSET)) | DAC_BF(name,value))
++
++/* Register access macros */
++#define dac_readl(port,reg) \
++ __raw_readl((port)->regs + DAC_##reg)
++#define dac_writel(port,reg,value) \
++ __raw_writel((value), (port)->regs + DAC_##reg)
++
++#endif /* __ASM_AVR32_DAC_H__ */
diff --git a/packages/linux/linux-2.6.18/at32ap7000-dmac-driver.patch b/packages/linux/linux-2.6.18/at32ap7000-dmac-driver.patch
new file mode 100644
index 0000000000..dfe5f6abd5
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at32ap7000-dmac-driver.patch
@@ -0,0 +1,855 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: Håvard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Dec 2 13:24:24 2005 +0100
+Subject: [PATCH] AVR32: DesignWare DMA Controller
+
+This patch adds a driver for the Synopsys DesignWare DMA Controller.
+
+---
+
+ arch/avr32/Kconfig | 4
+ arch/avr32/Makefile | 1
+ arch/avr32/drivers/Makefile | 1
+ arch/avr32/drivers/dw-dmac.c | 754 +++++++++++++++++++++++++++++++++++++++++++
+ arch/avr32/drivers/dw-dmac.h | 42 ++
+ 5 files changed, 802 insertions(+)
+
+Index: linux-2.6.18-avr32/arch/avr32/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/arch/avr32/Makefile 2006-11-02 14:17:29.000000000 +0100
++++ linux-2.6.18-avr32/arch/avr32/Makefile 2006-11-02 15:53:13.000000000 +0100
+@@ -30,6 +30,7 @@ core-$(CONFIG_BOARD_ATSTK1000) += arch/
+ core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/
+ core-y += arch/avr32/kernel/
+ core-y += arch/avr32/mm/
++drivers-y += arch/avr32/drivers/
+ drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
+ libs-y += arch/avr32/lib/
+
+Index: linux-2.6.18-avr32/arch/avr32/drivers/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/arch/avr32/drivers/Makefile 2006-11-02 14:17:29.000000000 +0100
+@@ -0,0 +1 @@
++obj-$(CONFIG_DW_DMAC) += dw-dmac.o
+Index: linux-2.6.18-avr32/arch/avr32/drivers/dw-dmac.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/arch/avr32/drivers/dw-dmac.c 2006-11-02 15:55:35.000000000 +0100
+@@ -0,0 +1,754 @@
++/*
++ * Driver for the Synopsys DesignWare DMA Controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <asm/dma-controller.h>
++#include <asm/io.h>
++
++#include "dw-dmac.h"
++
++#define DMAC_NR_CHANNELS 3
++#define DMAC_MAX_BLOCKSIZE 4095
++
++enum {
++ CH_STATE_FREE = 0,
++ CH_STATE_ALLOCATED,
++ CH_STATE_BUSY,
++};
++
++struct dw_dma_lli {
++ dma_addr_t sar;
++ dma_addr_t dar;
++ dma_addr_t llp;
++ u32 ctllo;
++ u32 ctlhi;
++ u32 sstat;
++ u32 dstat;
++};
++
++struct dw_dma_block {
++ struct dw_dma_lli *lli_vaddr;
++ dma_addr_t lli_dma_addr;
++};
++
++struct dw_dma_channel {
++ unsigned int state;
++ int is_cyclic;
++ struct dma_request_sg *req_sg;
++ struct dma_request_cyclic *req_cyclic;
++ unsigned int nr_blocks;
++ int direction;
++ struct dw_dma_block *block;
++};
++
++struct dw_dma_controller {
++ spinlock_t lock;
++ void * __iomem regs;
++ struct dma_pool *lli_pool;
++ struct clk *hclk;
++ struct dma_controller dma;
++ struct dw_dma_channel channel[DMAC_NR_CHANNELS];
++};
++#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
++
++#define dmac_writel_hi(dmac, reg, value) \
++ __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
++#define dmac_readl_hi(dmac, reg) \
++ __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
++#define dmac_writel_lo(dmac, reg, value) \
++ __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
++#define dmac_readl_lo(dmac, reg) \
++ __raw_readl((dmac)->regs + DW_DMAC_##reg)
++#define dmac_chan_writel_hi(dmac, chan, reg, value) \
++ __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
++ + DW_DMAC_CHAN_##reg + 4))
++#define dmac_chan_readl_hi(dmac, chan, reg) \
++ __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
++#define dmac_chan_writel_lo(dmac, chan, reg, value) \
++ __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
++#define dmac_chan_readl_lo(dmac, chan, reg) \
++ __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
++#define set_channel_bit(dmac, reg, chan) \
++ dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
++#define clear_channel_bit(dmac, reg, chan) \
++ dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
++
++static int dmac_alloc_channel(struct dma_controller *_dmac)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long flags;
++ int i;
++
++ spin_lock_irqsave(&dmac->lock, flags);
++ for (i = 0; i < DMAC_NR_CHANNELS; i++)
++ if (dmac->channel[i].state == CH_STATE_FREE)
++ break;
++
++ if (i < DMAC_NR_CHANNELS) {
++ chan = &dmac->channel[i];
++ chan->state = CH_STATE_ALLOCATED;
++ } else {
++ i = -EBUSY;
++ }
++
++ spin_unlock_irqrestore(&dmac->lock, flags);
++
++ return i;
++}
++
++static void dmac_release_channel(struct dma_controller *_dmac, int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS
++ || dmac->channel[channel].state != CH_STATE_ALLOCATED);
++
++ dmac->channel[channel].state = CH_STATE_FREE;
++}
++
++static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
++ unsigned int nr_blocks)
++{
++ struct dw_dma_block *block;
++ void *p;
++ unsigned int i;
++
++ block = kmalloc(nr_blocks * sizeof(*block),
++ GFP_KERNEL);
++ if (unlikely(!block))
++ return NULL;
++
++ for (i = 0; i < nr_blocks; i++) {
++ p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
++ &block[i].lli_dma_addr);
++ block[i].lli_vaddr = p;
++ if (unlikely(!p))
++ goto fail;
++ }
++
++ return block;
++
++fail:
++ for (i = 0; i < nr_blocks; i++) {
++ if (!block[i].lli_vaddr)
++ break;
++ dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
++ block[i].lli_dma_addr);
++ }
++ kfree(block);
++ return NULL;
++}
++
++static int dmac_prepare_request_sg(struct dma_controller *_dmac,
++ struct dma_request_sg *req)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long ctlhi, ctllo, cfghi, cfglo;
++ unsigned long block_size;
++ int ret, i, nr_blocks, direction;
++ unsigned long flags;
++
++ spin_lock_irqsave(&dmac->lock, flags);
++
++ ret = -EINVAL;
++ if (req->req.channel >= DMAC_NR_CHANNELS
++ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
++ || req->block_size > DMAC_MAX_BLOCKSIZE) {
++ spin_unlock_irqrestore(&dmac->lock, flags);
++ return -EINVAL;
++ }
++
++ chan = &dmac->channel[req->req.channel];
++ chan->state = CH_STATE_BUSY;
++ chan->req_sg = req;
++ chan->is_cyclic = 0;
++
++ /*
++ * We have marked the channel as busy, so no need to keep the
++ * lock as long as we only touch the channel-specific
++ * registers
++ */
++ spin_unlock_irqrestore(&dmac->lock, flags);
++
++ /*
++ * There may be limitations in the driver and/or the DMA
++ * controller that prevents us from sending a whole
++ * scatterlist item in one go. Taking this into account,
++ * calculate the number of block transfers we need to set up.
++ *
++ * FIXME: Let the peripheral driver know about the maximum
++ * block size we support. We really don't want to use a
++ * different block size than what was suggested by the
++ * peripheral.
++ *
++ * Each block will get its own Linked List Item (LLI) below.
++ */
++ block_size = req->block_size;
++ pr_debug("block_size = %lu, nr_sg = %u\n", block_size, req->nr_sg);
++ for (i = 0, nr_blocks = 0; i < req->nr_sg; i++) {
++ pr_debug("sg[i].length = %u\n", req->sg[i].length);
++ BUG_ON(req->sg[i].length % block_size);
++ nr_blocks += req->sg[i].length / block_size;
++ }
++
++ BUG_ON(nr_blocks == 0);
++ chan->nr_blocks = nr_blocks;
++
++ ret = -EINVAL;
++ cfglo = cfghi = 0;
++ switch (req->direction) {
++ case DMA_DIR_MEM_TO_PERIPH:
++ direction = DMA_TO_DEVICE;
++ cfghi = req->periph_id << (43 - 32);
++ break;
++
++ case DMA_DIR_PERIPH_TO_MEM:
++ direction = DMA_FROM_DEVICE;
++ cfghi = req->periph_id << (39 - 32);
++ break;
++ default:
++ goto out_unclaim_channel;
++ }
++
++ chan->direction = direction;
++
++ dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
++ dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
++
++ ctlhi = block_size >> req->width;
++ ctllo = ((req->direction << 20)
++ // | (1 << 14) | (1 << 11) // source/dest burst trans len
++ | (req->width << 4) | (req->width << 1)
++ | (1 << 0)); // interrupt enable
++
++ if (nr_blocks == 1) {
++ /* Only one block: No need to use block chaining */
++ if (direction == DMA_TO_DEVICE) {
++ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
++ req->sg->dma_address);
++ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
++ req->data_reg);
++ ctllo |= 2 << 7; // no dst increment
++ } else {
++ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
++ req->data_reg);
++ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
++ req->sg->dma_address);
++ ctllo |= 2 << 9; // no src increment
++ }
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
++ dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
++ } else {
++ struct dw_dma_lli *lli, *lli_prev = NULL;
++ int j = 0, offset = 0;
++
++ ret = -ENOMEM;
++ chan->block = allocate_blocks(dmac, nr_blocks);
++ if (!chan->block)
++ goto out_unclaim_channel;
++
++ if (direction == DMA_TO_DEVICE)
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
++ else
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
++
++ /*
++ * Map scatterlist items to blocks. One scatterlist
++ * item may need more than one block for the reasons
++ * mentioned above.
++ */
++ for (i = 0; i < nr_blocks; i++) {
++ lli = chan->block[i].lli_vaddr;
++ if (lli_prev) {
++ lli_prev->llp = chan->block[i].lli_dma_addr;
++ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr,
++ lli_prev->sar, lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);
++ }
++ lli->llp = 0;
++ lli->ctllo = ctllo;
++ lli->ctlhi = ctlhi;
++ if (direction == DMA_TO_DEVICE) {
++ lli->sar = req->sg[j].dma_address + offset;
++ lli->dar = req->data_reg;
++ } else {
++ lli->sar = req->data_reg;
++ lli->dar = req->sg[j].dma_address + offset;
++ }
++ lli_prev = lli;
++
++ offset += block_size;
++ if (offset > req->sg[j].length) {
++ j++;
++ offset = 0;
++ }
++ }
++
++ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
++ lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);
++
++ /*
++ * SAR, DAR and CTL are initialized from the LLI. We
++ * only have to enable the LLI bits in CTL.
++ */
++ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
++ chan->block[0].lli_dma_addr);
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
++ }
++
++ set_channel_bit(dmac, MASK_XFER, req->req.channel);
++ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
++ if (req->req.block_complete)
++ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++ else
++ clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++
++ return 0;
++
++out_unclaim_channel:
++ chan->state = CH_STATE_ALLOCATED;
++ return ret;
++}
++
++static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
++ struct dma_request_cyclic *req)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long ctlhi, ctllo, cfghi, cfglo;
++ unsigned long block_size;
++ int ret, i, direction;
++ unsigned long flags;
++
++ spin_lock_irqsave(&dmac->lock, flags);
++
++ block_size = (req->buffer_size/req->periods) >> req->width;
++
++ ret = -EINVAL;
++ if (req->req.channel >= DMAC_NR_CHANNELS
++ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
++ || (req->periods == 0)
++ || block_size > DMAC_MAX_BLOCKSIZE) {
++ spin_unlock_irqrestore(&dmac->lock, flags);
++ return -EINVAL;
++ }
++
++ chan = &dmac->channel[req->req.channel];
++ chan->state = CH_STATE_BUSY;
++ chan->is_cyclic = 1;
++ chan->req_cyclic = req;
++
++ /*
++ * We have marked the channel as busy, so no need to keep the
++ * lock as long as we only touch the channel-specific
++ * registers
++ */
++ spin_unlock_irqrestore(&dmac->lock, flags);
++
++ /*
++ Setup
++ */
++ BUG_ON(req->buffer_size % req->periods);
++ /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
++
++ chan->nr_blocks = req->periods;
++
++ ret = -EINVAL;
++ cfglo = cfghi = 0;
++ switch (req->direction) {
++ case DMA_DIR_MEM_TO_PERIPH:
++ direction = DMA_TO_DEVICE;
++ cfghi = req->periph_id << (43 - 32);
++ break;
++
++ case DMA_DIR_PERIPH_TO_MEM:
++ direction = DMA_FROM_DEVICE;
++ cfghi = req->periph_id << (39 - 32);
++ break;
++ default:
++ goto out_unclaim_channel;
++ }
++
++ chan->direction = direction;
++
++ dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
++ dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
++
++ ctlhi = block_size;
++ ctllo = ((req->direction << 20)
++ | (req->width << 4) | (req->width << 1)
++ | (1 << 0)); // interrupt enable
++
++ {
++ struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
++
++ ret = -ENOMEM;
++ chan->block = allocate_blocks(dmac, req->periods);
++ if (!chan->block)
++ goto out_unclaim_channel;
++
++ if (direction == DMA_TO_DEVICE)
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
++ else
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
++
++ /*
++ * Set up a linked list items where each period gets
++ * an item. The linked list item for the last period
++ * points back to the star of the buffer making a
++ * cyclic buffer.
++ */
++ for (i = 0; i < req->periods; i++) {
++ lli = chan->block[i].lli_vaddr;
++ if (lli_prev) {
++ lli_prev->llp = chan->block[i].lli_dma_addr;
++ /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr,
++ lli_prev->sar, lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);*/
++ }
++ lli->llp = 0;
++ lli->ctllo = ctllo;
++ lli->ctlhi = ctlhi;
++ if (direction == DMA_TO_DEVICE) {
++ lli->sar = req->buffer_start + i*(block_size << req->width);
++ lli->dar = req->data_reg;
++ } else {
++ lli->sar = req->data_reg;
++ lli->dar = req->buffer_start + i*(block_size << req->width);
++ }
++ lli_prev = lli;
++ }
++ lli->llp = chan->block[0].lli_dma_addr;
++
++ /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
++ lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi); */
++
++ /*
++ * SAR, DAR and CTL are initialized from the LLI. We
++ * only have to enable the LLI bits in CTL.
++ */
++ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
++ chan->block[0].lli_dma_addr);
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
++ }
++
++ clear_channel_bit(dmac, MASK_XFER, req->req.channel);
++ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
++ if (req->req.block_complete)
++ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++ else
++ clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++
++ return 0;
++
++out_unclaim_channel:
++ chan->state = CH_STATE_ALLOCATED;
++ return ret;
++}
++
++static int dmac_start_request(struct dma_controller *_dmac,
++ unsigned int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
++
++ set_channel_bit(dmac, CH_EN, channel);
++
++ return 0;
++}
++
++static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
++ unsigned int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ dma_addr_t current_pos;
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
++
++ chan = &dmac->channel[channel];
++
++ switch (chan->direction) {
++ case DMA_TO_DEVICE:
++ current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
++ break;
++ case DMA_FROM_DEVICE:
++ current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
++ break;
++ default:
++ return 0;
++ }
++
++
++ if (!current_pos) {
++ if (chan->is_cyclic) {
++ current_pos = chan->req_cyclic->buffer_start;
++ } else {
++ current_pos = chan->req_sg->sg->dma_address;
++ }
++ }
++
++ return current_pos;
++}
++
++
++static void cleanup_channel(struct dw_dma_controller *dmac,
++ struct dw_dma_channel *chan)
++{
++ unsigned int i;
++
++ if (chan->nr_blocks > 1) {
++ for (i = 0; i < chan->nr_blocks; i++)
++ dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
++ chan->block[i].lli_dma_addr);
++ kfree(chan->block);
++ }
++
++ chan->state = CH_STATE_ALLOCATED;
++}
++
++static int dmac_stop_request(struct dma_controller *_dmac,
++ unsigned int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
++
++ BUG_ON(dmac->channel[channel].state != CH_STATE_BUSY);
++
++ clear_channel_bit(dmac, CH_EN, channel);
++
++ cleanup_channel(dmac, &dmac->channel[channel]);
++
++ return 0;
++}
++
++
++static void dmac_block_complete(struct dw_dma_controller *dmac)
++{
++ struct dw_dma_channel *chan;
++ unsigned long status, chanid;
++
++ status = dmac_readl_lo(dmac, STATUS_BLOCK);
++
++ while (status) {
++ struct dma_request *req;
++ chanid = __ffs(status);
++ chan = &dmac->channel[chanid];
++
++ if (chan->is_cyclic) {
++ BUG_ON(!chan->req_cyclic
++ || !chan->req_cyclic->req.block_complete);
++ req = &chan->req_cyclic->req;
++ } else {
++ BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
++ req = &chan->req_sg->req;
++ }
++ dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
++ req->block_complete(req);
++ status = dmac_readl_lo(dmac, STATUS_BLOCK);
++ }
++}
++
++static void dmac_xfer_complete(struct dw_dma_controller *dmac)
++{
++ struct dw_dma_channel *chan;
++ struct dma_request *req;
++ unsigned long status, chanid;
++
++ status = dmac_readl_lo(dmac, STATUS_XFER);
++
++ while (status) {
++ chanid = __ffs(status);
++ chan = &dmac->channel[chanid];
++
++ dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
++
++ req = &chan->req_sg->req;
++ BUG_ON(!req);
++ cleanup_channel(dmac, chan);
++ if (req->xfer_complete)
++ req->xfer_complete(req);
++
++ status = dmac_readl_lo(dmac, STATUS_XFER);
++ }
++}
++
++static void dmac_error(struct dw_dma_controller *dmac)
++{
++ struct dw_dma_channel *chan;
++ unsigned long status, chanid;
++
++ status = dmac_readl_lo(dmac, STATUS_ERROR);
++
++ while (status) {
++ struct dma_request *req;
++
++ chanid = __ffs(status);
++ chan = &dmac->channel[chanid];
++
++ dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
++ clear_channel_bit(dmac, CH_EN, chanid);
++
++ if (chan->is_cyclic) {
++ BUG_ON(!chan->req_cyclic);
++ req = &chan->req_cyclic->req;
++ } else {
++ BUG_ON(!chan->req_sg);
++ req = &chan->req_sg->req;
++ }
++
++ cleanup_channel(dmac, chan);
++ if (req->error)
++ req->error(req);
++
++ status = dmac_readl_lo(dmac, STATUS_XFER);
++ }
++}
++
++static irqreturn_t dmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++ struct dw_dma_controller *dmac = dev_id;
++ unsigned long status;
++ int ret = IRQ_NONE;
++
++ spin_lock(&dmac->lock);
++
++ status = dmac_readl_lo(dmac, STATUS_INT);
++
++ while (status) {
++ ret = IRQ_HANDLED;
++ if (status & 0x10)
++ dmac_error(dmac);
++ if (status & 0x02)
++ dmac_block_complete(dmac);
++ if (status & 0x01)
++ dmac_xfer_complete(dmac);
++
++ status = dmac_readl_lo(dmac, STATUS_INT);
++ }
++
++ spin_unlock(&dmac->lock);
++ return ret;
++}
++
++static int __devinit dmac_probe(struct platform_device *pdev)
++{
++ struct dw_dma_controller *dmac;
++ struct resource *regs;
++ int ret;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++
++ dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
++ if (!dmac)
++ return -ENOMEM;
++ memset(dmac, 0, sizeof(*dmac));
++
++ dmac->hclk = clk_get(&pdev->dev, "hclk");
++ if (IS_ERR(dmac->hclk)) {
++ ret = PTR_ERR(dmac->hclk);
++ goto out_free_dmac;
++ }
++ clk_enable(dmac->hclk);
++
++ ret = -ENOMEM;
++ dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
++ sizeof(struct dw_dma_lli), 4, 0);
++ if (!dmac->lli_pool)
++ goto out_disable_clk;
++
++ spin_lock_init(&dmac->lock);
++ dmac->dma.dev = &pdev->dev;
++ dmac->dma.alloc_channel = dmac_alloc_channel;
++ dmac->dma.release_channel = dmac_release_channel;
++ dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
++ dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
++ dmac->dma.start_request = dmac_start_request;
++ dmac->dma.stop_request = dmac_stop_request;
++ dmac->dma.get_current_pos = dmac_get_current_pos;
++
++ dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!dmac->regs)
++ goto out_free_pool;
++
++ ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
++ SA_SAMPLE_RANDOM, pdev->name, dmac);
++ if (ret)
++ goto out_unmap_regs;
++
++ /* Enable the DMA controller */
++ dmac_writel_lo(dmac, CFG, 1);
++
++ register_dma_controller(&dmac->dma);
++
++ printk(KERN_INFO
++ "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
++ dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
++
++ return 0;
++
++out_unmap_regs:
++ iounmap(dmac->regs);
++out_free_pool:
++ dma_pool_destroy(dmac->lli_pool);
++out_disable_clk:
++ clk_disable(dmac->hclk);
++ clk_put(dmac->hclk);
++out_free_dmac:
++ kfree(dmac);
++ return ret;
++}
++
++static struct platform_driver dmac_driver = {
++ .probe = dmac_probe,
++ .driver = {
++ .name = "dmac",
++ },
++};
++
++static int __init dmac_init(void)
++{
++ return platform_driver_register(&dmac_driver);
++}
++subsys_initcall(dmac_init);
++
++static void __exit dmac_exit(void)
++{
++ platform_driver_unregister(&dmac_driver);
++}
++module_exit(dmac_exit);
++
++MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.18-avr32/arch/avr32/drivers/dw-dmac.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/arch/avr32/drivers/dw-dmac.h 2006-11-02 14:17:29.000000000 +0100
+@@ -0,0 +1,42 @@
++/*
++ * Driver for the Synopsys DesignWare DMA Controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __AVR32_DW_DMAC_H__
++#define __AVR32_DW_DMAC_H__
++
++#define DW_DMAC_CFG 0x398
++#define DW_DMAC_CH_EN 0x3a0
++
++#define DW_DMAC_STATUS_XFER 0x2e8
++#define DW_DMAC_STATUS_BLOCK 0x2f0
++#define DW_DMAC_STATUS_ERROR 0x308
++
++#define DW_DMAC_MASK_XFER 0x310
++#define DW_DMAC_MASK_BLOCK 0x318
++#define DW_DMAC_MASK_ERROR 0x330
++
++#define DW_DMAC_CLEAR_XFER 0x338
++#define DW_DMAC_CLEAR_BLOCK 0x340
++#define DW_DMAC_CLEAR_ERROR 0x358
++
++#define DW_DMAC_STATUS_INT 0x360
++
++#define DW_DMAC_CHAN_SAR 0x000
++#define DW_DMAC_CHAN_DAR 0x008
++#define DW_DMAC_CHAN_LLP 0x010
++#define DW_DMAC_CHAN_CTL 0x018
++#define DW_DMAC_CHAN_SSTAT 0x020
++#define DW_DMAC_CHAN_DSTAT 0x028
++#define DW_DMAC_CHAN_SSTATAR 0x030
++#define DW_DMAC_CHAN_DSTATAR 0x038
++#define DW_DMAC_CHAN_CFG 0x040
++#define DW_DMAC_CHAN_SGR 0x048
++#define DW_DMAC_CHAN_DSR 0x050
++
++#endif /* __AVR32_DW_DMAC_H__ */
+Index: linux-2.6.18-avr32/arch/avr32/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/arch/avr32/Kconfig 2006-11-02 14:17:29.000000000 +0100
++++ linux-2.6.18-avr32/arch/avr32/Kconfig 2006-11-02 15:53:13.000000000 +0100
+@@ -157,6 +157,10 @@ config OWNERSHIP_TRACE
+ enabling Nexus-compliant debuggers to keep track of the PID of the
+ currently executing task.
+
++config DW_DMAC
++ tristate "Synopsys DesignWare DMA Controller support"
++ default y if CPU_AT32AP7000
++
+ # FPU emulation goes here
+
+ source "kernel/Kconfig.hz"
diff --git a/packages/linux/linux-2.6.18/at32ap7000-platform_device-definitions.patch b/packages/linux/linux-2.6.18/at32ap7000-platform_device-definitions.patch
new file mode 100644
index 0000000000..6f1e98a70c
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at32ap7000-platform_device-definitions.patch
@@ -0,0 +1,445 @@
+---
+ arch/avr32/mach-at32ap/at32ap7000.c | 325 ++++++++++++++++++++++++++++++++--
+ include/asm-avr32/arch-at32ap/board.h | 6
+ 2 files changed, 313 insertions(+), 18 deletions(-)
+
+Index: linux-2.6.18-avr32/arch/avr32/mach-at32ap/at32ap7000.c
+===================================================================
+--- linux-2.6.18-avr32.orig/arch/avr32/mach-at32ap/at32ap7000.c 2006-11-29 16:31:03.000000000 +0100
++++ linux-2.6.18-avr32/arch/avr32/mach-at32ap/at32ap7000.c 2006-11-29 16:44:49.000000000 +0100
+@@ -9,6 +9,8 @@
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+
++#include <linux/spi/spi.h>
++
+ #include <asm/io.h>
+
+ #include <asm/arch/at32ap7000.h>
+@@ -464,6 +466,17 @@ static struct clk pico_clk = {
+ .users = 1,
+ };
+
++static struct resource dmac0_resource[] = {
++ {
++ .start = 0xff200000,
++ .end = 0xff20ffff,
++ .flags = IORESOURCE_MEM,
++ },
++ IRQ(2),
++};
++DEFINE_DEV(dmac, 0);
++DEV_CLK(hclk, dmac0, hsb, 10);
++
+ /* --------------------------------------------------------------------
+ * PIO
+ * -------------------------------------------------------------------- */
+@@ -504,6 +517,7 @@ void __init at32_add_system_devices(void
+ platform_device_register(&at32_intc0_device);
+ platform_device_register(&smc0_device);
+ platform_device_register(&pdc_device);
++ platform_device_register(&dmac0_device);
+
+ platform_device_register(&pio0_device);
+ platform_device_register(&pio1_device);
+@@ -644,6 +658,15 @@ DEFINE_DEV_DATA(macb, 0);
+ DEV_CLK(hclk, macb0, hsb, 8);
+ DEV_CLK(pclk, macb0, pbb, 6);
+
++static struct eth_platform_data macb1_data;
++static struct resource macb1_resource[] = {
++ PBMEM(0xfff01c00),
++ IRQ(26),
++};
++DEFINE_DEV_DATA(macb, 1);
++DEV_CLK(hclk, macb1, hsb, 9);
++DEV_CLK(pclk, macb1, pbb, 7);
++
+ struct platform_device *__init
+ at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
+ {
+@@ -677,6 +700,33 @@ at32_add_device_eth(unsigned int id, str
+ }
+ break;
+
++ case 1:
++ pdev = &macb1_device;
++
++ select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
++ select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
++ select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
++ select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
++ select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
++ select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
++ select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
++ select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
++ select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
++ select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
++
++ if (!data->is_rmii) {
++ select_peripheral(PC(19), PERIPH_B, 0); /* COL */
++ select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
++ select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
++ select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
++ select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
++ select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
++ select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
++ select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
++ select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
++ }
++ break;
++
+ default:
+ return NULL;
+ }
+@@ -688,14 +738,53 @@ at32_add_device_eth(unsigned int id, str
+ }
+
+ /* --------------------------------------------------------------------
++ * MMC
++ * -------------------------------------------------------------------- */
++static struct resource mmci0_resource[] = {
++ PBMEM(0xfff02400),
++ IRQ(28),
++};
++DEFINE_DEV(mmci, 0);
++DEV_CLK(mck, mmci0, pbb, 9);
++
++struct platform_device *__init at32_add_device_mmci(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ switch (id) {
++ case 0:
++ pdev = &mmci0_device;
++ select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
++ select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
++ select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
++ select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
++ select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
++ select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
++ break;
++ default:
++ return NULL;
++ }
++
++ platform_device_register(pdev);
++ return pdev;
++}
++
++/* --------------------------------------------------------------------
+ * SPI
+ * -------------------------------------------------------------------- */
+-static struct resource spi0_resource[] = {
++static struct resource atmel_spi0_resource[] = {
+ PBMEM(0xffe00000),
+ IRQ(3),
+ };
+-DEFINE_DEV(spi, 0);
+-DEV_CLK(mck, spi0, pba, 0);
++DEFINE_DEV(atmel_spi, 0);
++DEV_CLK(pclk, atmel_spi0, pba, 0);
++
++static struct resource atmel_spi1_resource[] = {
++ PBMEM(0xffe00400),
++ IRQ(4),
++};
++DEFINE_DEV(atmel_spi, 1);
++DEV_CLK(pclk, atmel_spi1, pba, 1);
+
+ struct platform_device *__init at32_add_device_spi(unsigned int id)
+ {
+@@ -703,13 +792,96 @@ struct platform_device *__init at32_add_
+
+ switch (id) {
+ case 0:
+- pdev = &spi0_device;
++ pdev = &atmel_spi0_device;
+ select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
+ select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
+ select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
+- select_peripheral(PA(3), PERIPH_A, 0); /* NPCS0 */
+- select_peripheral(PA(4), PERIPH_A, 0); /* NPCS1 */
+- select_peripheral(PA(5), PERIPH_A, 0); /* NPCS2 */
++
++ /* NPCS[2:0] */
++ at32_select_gpio(GPIO_PIN_PA(3),
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++ at32_select_gpio(GPIO_PIN_PA(4),
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++ at32_select_gpio(GPIO_PIN_PA(5),
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++ break;
++
++ case 1:
++ pdev = &atmel_spi1_device;
++ select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
++ select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
++ select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
++
++ /* NPCS[2:0] */
++ at32_select_gpio(GPIO_PIN_PA(2),
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++ at32_select_gpio(GPIO_PIN_PA(3),
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++ at32_select_gpio(GPIO_PIN_PA(4),
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++
++ default:
++ return NULL;
++ }
++
++ platform_device_register(pdev);
++ return pdev;
++}
++
++/* --------------------------------------------------------------------
++ * USB Device Controller
++ * -------------------------------------------------------------------- */
++static struct resource usb0_resource[] = {
++ {
++ .start = 0xff300000,
++ .end = 0xff3fffff,
++ .flags = IORESOURCE_MEM,
++ },
++ PBMEM(0xfff03000),
++ IRQ(31),
++};
++DEFINE_DEV(usb, 0);
++DEV_CLK(pclk, usb0, pbb, 12);
++DEV_CLK(hclk, usb0, hsb, 6);
++
++struct platform_device *__init at32_add_device_usb(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ switch (id) {
++ case 0:
++ pdev = &usb0_device;
++ /* USB pads are not multiplexed */
++ break;
++ default:
++ return NULL;
++ }
++
++ platform_device_register(pdev);
++ return pdev;
++}
++
++/* --------------------------------------------------------------------
++ * TWI
++ * -------------------------------------------------------------------- */
++
++static struct resource atmel_twi0_resource[] = {
++ PBMEM(0xffe00800),
++ IRQ(5),
++};
++DEFINE_DEV(atmel_twi, 0);
++DEV_CLK(pclk,atmel_twi0,pba,2);
++
++struct platform_device *__init
++at32_add_device_twi(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ switch (id) {
++ case 0:
++ pdev = &atmel_twi0_device;
++ select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
++ select_peripheral(PA(7), PERIPH_A, 0); /* SCL */
+ break;
+
+ default:
+@@ -765,16 +937,16 @@ at32_add_device_lcdc(unsigned int id, st
+ select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
+ select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
+ select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
+- select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
+- select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
+- select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
+- select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
+- select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
+- select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
+- select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
+- select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
+- select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
+- select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
++ select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
++ select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
++ select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
++ select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
++ select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
++ select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
++ select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
++ select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
++ select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
++ select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
+ select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
+ select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
+ select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
+@@ -799,6 +971,111 @@ at32_add_device_lcdc(unsigned int id, st
+ return pdev;
+ }
+
++/* --------------------------------------------------------------------
++ * Sound
++ * -------------------------------------------------------------------- */
++static struct resource ac97c0_resource[] = {
++ PBMEM(0xfff02800),
++ IRQ(29),
++};
++DEFINE_DEV(ac97c, 0);
++DEV_CLK(mck, ac97c0, pbb, 10);
++
++struct platform_device *__init
++at32_add_device_ac97c(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ switch (id) {
++ case 0:
++ pdev = &ac97c0_device;
++ select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
++ select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
++ select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
++ select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
++ break;
++ default:
++ return NULL;
++ }
++
++ platform_device_register(pdev);
++ return pdev;
++}
++
++static struct spi_board_info at73c2130_data = {
++ .max_speed_hz = 200000,
++ .controller_data = (void *)GPIO_PIN_PA(3),
++ .modalias = "at73c213",
++ .bus_num = 0,
++ .chip_select = 0,
++};
++static struct resource at73c2130_resource[] = {
++ PBMEM(0xffe01c00),
++ IRQ(10),
++};
++DEFINE_DEV_DATA(at73c213, 0);
++DEV_CLK(mck, at73c2130, pba, 7);
++
++struct platform_device *__init
++at32_add_device_at73c213(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ switch (id) {
++ case 0:
++ pdev = &at73c2130_device;
++ select_peripheral(PA(21), PERIPH_A, 0); /* RX_FSYNC */
++ select_peripheral(PA(22), PERIPH_A, 0); /* RX_CLOCK */
++ select_peripheral(PA(23), PERIPH_A, 0); /* TX_CLOCK */
++ select_peripheral(PA(24), PERIPH_A, 0); /* TX_FSYNC */
++ select_peripheral(PA(25), PERIPH_A, 0); /* TX_DATA */
++ select_peripheral(PA(26), PERIPH_A, 0); /* RX_DATA */
++ break;
++ default:
++ return NULL;
++ }
++
++ platform_device_register(pdev);
++ return pdev;
++}
++
++static struct resource dac0_resource[] = {
++ PBMEM(0xfff02000),
++ IRQ(27),
++};
++DEFINE_DEV(dac, 0);
++DEV_CLK(mck, dac0, pbb, 8);
++static struct clk dac0_sample_clk = {
++ .name = "sample_clk",
++ .dev = &dac0_device.dev,
++ .mode = genclk_mode,
++ .get_rate = genclk_get_rate,
++ .set_rate = genclk_set_rate,
++ .set_parent = genclk_set_parent,
++ .index = 6,
++};
++
++struct platform_device *__init
++at32_add_device_dac(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ switch (id) {
++ case 0:
++ pdev = &dac0_device;
++ select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
++ select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
++ select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
++ select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
++ break;
++ default:
++ return NULL;
++ }
++
++ platform_device_register(pdev);
++ return pdev;
++}
++
+ struct clk *at32_clock_list[] = {
+ &osc32k,
+ &osc0,
+@@ -817,6 +1094,7 @@ struct clk *at32_clock_list[] = {
+ &smc0_mck,
+ &pdc_hclk,
+ &pdc_pclk,
++ &dmac0_hclk,
+ &pico_clk,
+ &pio0_mck,
+ &pio1_mck,
+@@ -828,9 +1106,20 @@ struct clk *at32_clock_list[] = {
+ &usart3_usart,
+ &macb0_hclk,
+ &macb0_pclk,
+- &spi0_mck,
++ &macb1_hclk,
++ &macb1_pclk,
++ &atmel_spi0_pclk,
++ &atmel_spi1_pclk,
++ &atmel_twi0_pclk,
++ &mmci0_mck,
++ &usb0_pclk,
++ &usb0_hclk,
+ &lcdc0_hclk,
+ &lcdc0_pixclk,
++ &ac97c0_mck,
++ &at73c2130_mck,
++ &dac0_mck,
++ &dac0_sample_clk,
+ };
+ unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
+
+Index: linux-2.6.18-avr32/include/asm-avr32/arch-at32ap/board.h
+===================================================================
+--- linux-2.6.18-avr32.orig/include/asm-avr32/arch-at32ap/board.h 2006-11-29 16:31:03.000000000 +0100
++++ linux-2.6.18-avr32/include/asm-avr32/arch-at32ap/board.h 2006-11-29 16:31:42.000000000 +0100
+@@ -24,13 +24,19 @@ struct eth_platform_data {
+ struct platform_device *
+ at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
+
++struct platform_device *at32_add_device_mmci(unsigned int id);
+ struct platform_device *at32_add_device_spi(unsigned int id);
++struct platform_device *at32_add_device_twi(unsigned int id);
+
+ struct lcdc_platform_data {
+ unsigned long fbmem_start;
+ unsigned long fbmem_size;
+ };
++struct platform_device *__init at32_add_device_usb(unsigned int id);
+ struct platform_device *
+ at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data);
++struct platform_device *__init at32_add_device_dac(unsigned int id);
++struct platform_device *__init at32_add_device_at73c213(unsigned int id);
++struct platform_device *__init at32_add_device_ac97c(unsigned int id);
+
+ #endif /* __ASM_ARCH_BOARD_H */
diff --git a/packages/linux/linux-2.6.18/at32stk1000/.mtn2git_empty b/packages/linux/linux-2.6.18/at32stk1000/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at32stk1000/.mtn2git_empty
diff --git a/packages/linux/linux-2.6.18/at32stk1000/defconfig b/packages/linux/linux-2.6.18/at32stk1000/defconfig
new file mode 100644
index 0000000000..b4aced9f16
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at32stk1000/defconfig
@@ -0,0 +1,990 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.18-at0
+# Thu Jan 11 15:37:42 2007
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+# CONFIG_BLK_DEV_IO_TRACE is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+
+#
+# System Type and features
+#
+CONFIG_SUBARCH_AVR32B=y
+CONFIG_MMU=y
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATSTK1002=y
+CONFIG_BOARD_ATSTK1000=y
+# CONFIG_BOARD_ATNGW is not set
+CONFIG_LOADER_U_BOOT=y
+
+#
+# Atmel AVR32 AP options
+#
+CONFIG_PIO_DEV=y
+CONFIG_LOAD_ADDRESS=0x10000000
+CONFIG_ENTRY_ADDRESS=0x90000000
+CONFIG_PHYS_OFFSET=0x10000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_OWNERSHIP_TRACE is not set
+CONFIG_DW_DMAC=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_CMDLINE=""
+
+#
+# Bus options
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=m
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPPOE=m
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=m
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_ATMELTWI=m
+CONFIG_I2C_ATMELTWI_BAUDRATE=100000
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+CONFIG_SENSORS_EEPROM=m
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+
+#
+# Dallas's 1-wire bus
+#
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_V4L2=y
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+CONFIG_FB_SIDSA=y
+CONFIG_FB_SIDSA_DEFAULT_BPP=24
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+
+#
+# Logo configuration
+#
+# CONFIG_LOGO is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_AC97_BUS=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA AVR32 devices
+#
+CONFIG_SND_ATMEL_AC97=m
+# CONFIG_SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS is not set
+# CONFIG_SND_ATMEL_AC97C_USE_PDC is not set
+CONFIG_SND_AT73C213=m
+# CONFIG_SND_AT73C213_USE_ALSA_MALLOC_CALLS is not set
+
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=m
+# CONFIG_OSS_OBSOLETE_DRIVER is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+CONFIG_SOUND_AT32_DAC=m
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+CONFIG_USB_GADGET_HUSB2DEV=y
+CONFIG_USB_HUSB2DEV=m
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+
+#
+# MMC/SD Card support
+#
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_ATMELMCI=y
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_UNWIND_INFO is not set
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
diff --git a/packages/linux/linux-2.6.18/at73c213-alsa-driver.patch b/packages/linux/linux-2.6.18/at73c213-alsa-driver.patch
new file mode 100644
index 0000000000..ceb12cc950
--- /dev/null
+++ b/packages/linux/linux-2.6.18/at73c213-alsa-driver.patch
@@ -0,0 +1,1485 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date: Fri Apr 28 15:30:44 2006 +0200
+Subject: [PATCH] at73c213 ALSA driver
+
+This driver uses the SSC and SPI modules to communicate with an at73c213
+sound chip on the AT32STK1000.
+
+---
+
+ sound/avr32/Kconfig | 20
+ sound/avr32/Makefile | 3
+ sound/avr32/at73c213.c | 1296 +++++++++++++++++++++++++++++++++++++++++++++++++
+ sound/avr32/at73c213.h | 120 ++++
+ 4 files changed, 1439 insertions(+)
+ create mode 100644 sound/avr32/at73c213.c
+ create mode 100644 sound/avr32/at73c213.h
+
+859730d5cbe00b7935c4e30d179c5c5b096deb3c
+Index: linux-2.6.18-avr32/sound/avr32/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/avr32/Kconfig 2006-11-02 15:56:20.000000000 +0100
++++ linux-2.6.18-avr32/sound/avr32/Kconfig 2006-11-02 15:56:20.000000000 +0100
+@@ -28,4 +28,24 @@ config SND_ATMEL_AC97C_USE_PDC
+ Say Y if PDC (Peripheral DMA Controller) is used for DMA transfers
+ to/from the Atmel AC97C instead of using the generic DMA framework.
+
++config SND_AT73C213
++ tristate "Atmel AT73C213 DAC driver"
++ depends on SND && SPI_ATMEL
++ select SND_PCM
++ help
++ Say Y here if you want to use the Atmel AT73C213 external
++ DAC on the ATSTK1000 development board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called snd-at73c213.
++
++config SND_AT73C213_USE_ALSA_MALLOC_CALLS
++ bool "Use the built-in malloc calls in the alsa driver"
++ default n
++ depends on SND_AT73C213
++ help
++ Say Y if the built-in malloc calls in the alsa driver should be
++ used instead of the native dma_alloc_coherent and dma_free_coherent
++ function calls. Enabling this feature may brake the rmmod feature.
++
+ endmenu
+Index: linux-2.6.18-avr32/sound/avr32/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/avr32/Makefile 2006-11-02 15:56:20.000000000 +0100
++++ linux-2.6.18-avr32/sound/avr32/Makefile 2006-11-02 15:56:20.000000000 +0100
+@@ -4,3 +4,6 @@
+
+ snd-atmel-ac97-objs := ac97c.o
+ obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
++
++snd-at73c213-objs := at73c213.o
++obj-$(CONFIG_SND_AT73C213) += snd-at73c213.o
+Index: linux-2.6.18-avr32/sound/avr32/at73c213.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/sound/avr32/at73c213.c 2006-11-02 16:01:55.000000000 +0100
+@@ -0,0 +1,1296 @@
++/*
++ * Driver for the at73c213 16-bit stereo DAC on Atmel ATSTK1000
++ *
++ * Copyright (C) 2006 Atmel Norway
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++ * 02111-1307, USA.
++ *
++ * The full GNU General Public License is included in this
++ * distribution in the file called COPYING.
++ */
++#undef DEBUG
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/kmod.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/initval.h>
++#include <sound/driver.h>
++#include <sound/control.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#ifndef SND_AT73C213_USE_ALSA_MALLOC_CALLS
++#include <sound/memalloc.h>
++#endif
++
++#include <linux/spi/spi.h>
++
++#include <asm/io.h>
++#include <asm/processor.h>
++
++#include "at73c213.h"
++
++/* module parameters */
++static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
++static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
++static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
++
++/* Register defines */
++#define PIOA_BASE 0xFFE02800
++#define SSC0_BASE 0xFFE01C00
++#define PM_BASE 0xFFF00000
++
++#define PM_CKSEL 0x04
++#define PM_APBAMASK 0x10
++#define PM_GCCTRL 0x60
++
++#define PIO_PER 0x00
++#define PIO_PDR 0x04
++#define PIO_PUER 0x64
++#define PIO_ASR 0x70
++#define PIO_BSR 0x74
++
++#define SSC_CMR 0x04
++#define SSC_CR 0x00
++#define SSC_TCMR 0x18
++#define SSC_TFMR 0x1C
++
++/* SSC register definitions */
++#define SSC_CR 0x00
++#define SSC_CMR 0x04
++#define SSC_TCMR 0x18
++#define SSC_TFMR 0x1C
++#define SSC_THR 0x24
++#define SSC_SR 0x40
++#define SSC_IER 0x44
++#define SSC_IDR 0x48
++#define SSC_IMR 0x4C
++
++/* SSC fields definitions */
++#define SSC_CR_TXEN 0x00000100
++#define SSC_CR_TXDIS 0x00000200
++#define SSC_CR_SWRST 0x00008000
++
++/* SSC interrupt definitions */
++#define SSC0_IRQ 10
++#define SSC_INT_ENDTX 0x00000004
++#define SSC_INT_TXBUFE 0x00000008
++
++/* PDC register definitions */
++#define PDC_RPR 0x100
++#define PDC_RCR 0x104
++#define PDC_TPR 0x108
++#define PDC_TCR 0x10c
++#define PDC_RNPR 0x110
++#define PDC_RNCR 0x114
++#define PDC_TNPR 0x118
++#define PDC_TNCR 0x11c
++#define PDC_PTCR 0x120
++#define PDC_PTSR 0x124
++
++/* PDC fields definitions */
++#define PDC_PTCR_RXTEN 0x0001
++#define PDC_PTCR_RXTDIS 0x0002
++#define PDC_PTCR_TXTEN 0x0100
++#define PDC_PTCR_TXTDIS 0x0200
++
++static int bitrate;
++static int gclk_div;
++static int ssc_div;
++static int spi = 0;
++static int ssc = 1;
++
++module_param(spi, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
++MODULE_PARM_DESC(spi, "Which SPI interface to use to communicate with the at73c213");
++module_param(ssc, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
++MODULE_PARM_DESC(ssc, "Which SSC interface to use to communicate with the at73c213");
++
++/* Initial AT73C213 register values */
++static unsigned char snd_at73c213_original_image[18] =
++{
++ 0x00, /* 00 - CTRL */
++ 0x05, /* 01 - LLIG */
++ 0x05, /* 02 - RLIG */
++ 0x08, /* 03 - LPMG */
++ 0x08, /* 04 - RPMG */
++ 0x00, /* 05 - LLOG */
++ 0x00, /* 06 - RLOG */
++ 0x22, /* 07 - OLC */
++ 0x09, /* 08 - MC */
++ 0x00, /* 09 - CSFC */
++ 0x00, /* 0A - MISC */
++ 0x00, /* 0B - */
++ 0x00, /* 0C - PRECH */
++ 0x05, /* 0D - AUXG */
++ 0x00, /* 0E - */
++ 0x00, /* 0F - */
++ 0x00, /* 10 - RST */
++ 0x00, /* 11 - PA_CTRL */
++};
++
++/* chip-specific data */
++struct snd_at73c213 {
++ snd_card_t *card;
++ snd_pcm_t *pcm;
++ snd_pcm_substream_t *substream;
++ int irq;
++ int period;
++ void __iomem *regs;
++ struct clk *ssc_clk;
++ struct spi_device *spi;
++ u8 spi_wbuffer[2];
++ u8 spi_rbuffer[2];
++ /* image of the SPI registers in AT73C213 */
++ u8 image[18];
++ spinlock_t lock;
++ struct platform_device *pdev;
++};
++
++#define get_chip(card) ((struct snd_at73c213 *)card->private_data)
++
++static int
++snd_at73c213_write_reg(struct snd_at73c213 *chip, u8 reg, u8 val)
++{
++ struct spi_message msg;
++ struct spi_transfer msg_xfer = {
++ .len = 2,
++ .cs_change = 0,
++ };
++
++ spi_message_init(&msg);
++
++ chip->spi_wbuffer[0] = reg;
++ chip->spi_wbuffer[1] = val;
++
++ msg_xfer.tx_buf = chip->spi_wbuffer;
++ msg_xfer.rx_buf = chip->spi_rbuffer;
++ spi_message_add_tail(&msg_xfer, &msg);
++
++ return spi_sync(chip->spi, &msg);
++}
++
++#define write_reg(_spi, reg, val) \
++ do { \
++ retval = snd_at73c213_write_reg(_spi, reg, val); \
++ if (retval) \
++ goto out; \
++ } while (0)
++
++static snd_pcm_hardware_t snd_at73c213_playback_hw = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER,
++ .formats = SNDRV_PCM_FMTBIT_S16_BE,
++ .rates = SNDRV_PCM_RATE_CONTINUOUS,
++ .rate_min = 8000, /* This will be overwritten with bitrate */
++ .rate_max = 50000, /* This will be overwritten with bitrate */
++ .channels_min = 2,
++ .channels_max = 2,
++ .buffer_bytes_max = 64 * 1024 - 1,
++ .period_bytes_min = 512,
++ .period_bytes_max = 64 * 1024 - 1,
++ .periods_min = 4,
++ .periods_max = 1024,
++};
++
++/* calculate and set bitrate and divisions */
++static int snd_at73c213_set_bitrate_and_div(void)
++{
++ extern struct avr32_cpuinfo boot_cpu_data;
++ unsigned long pll0_hz, apba_hz;
++ unsigned long apba_realdiv, gclk_realdiv, ssc_realdiv, wanted_bitrate;
++ char cpusel, ahbsel, apbasel;
++ int regval;
++
++ regval = __raw_readl((void __iomem *)PM_BASE + PM_CKSEL);
++ wanted_bitrate = 48000;
++
++ cpusel = regval & 0x07;
++ ahbsel = (regval>>8) & 0x07;
++ apbasel = (regval>>16) & 0x07;
++
++ /* FIXME: Use the clk framework for this */
++ if ((regval&(1<<7)) != 0) {
++ pll0_hz = clk_get_rate(boot_cpu_data.clk)/(1<<(cpusel+1));
++ } else {
++ pll0_hz = clk_get_rate(boot_cpu_data.clk);
++ }
++
++ if ((regval&(1<<23)) != 0) {
++ apba_hz = pll0_hz/(1<<(apbasel+1));
++ apba_realdiv = (1<<(apbasel+1));
++ } else {
++ apba_hz = pll0_hz;
++ apba_realdiv = 1;
++ }
++
++calculate:
++ /* Adjust bitrate as close as possible to 48000 Hz */
++ gclk_realdiv = pll0_hz/(wanted_bitrate*256);
++ ssc_realdiv = 2 * apba_realdiv * gclk_realdiv;
++
++ if ((gclk_realdiv % 2) == 0)
++ goto setbitrates;
++
++ if(wanted_bitrate >= 22050 && wanted_bitrate <= 48000)
++ wanted_bitrate -= 50;
++ else if (wanted_bitrate < 22050)
++ wanted_bitrate = 48050;
++ else if (wanted_bitrate <= 50000)
++ wanted_bitrate += 50;
++ else {
++ printk(KERN_ERR "at73c213 could not set dividers for a valid bitrate\n");
++ return -EINVAL;
++ }
++
++ goto calculate;
++
++setbitrates:
++ bitrate = pll0_hz/(gclk_realdiv*256);
++ gclk_div = (gclk_realdiv/2)-1;
++ ssc_realdiv = 2*apba_realdiv*gclk_realdiv;
++ ssc_div = ssc_realdiv/(2*apba_realdiv);
++
++ printk(KERN_INFO "at73c213: bitrate is %d Hz\n", bitrate);
++
++ return 0;
++}
++
++/* open callback */
++static int snd_at73c213_pcm_open(snd_pcm_substream_t *substream)
++{
++ struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
++ snd_pcm_runtime_t *runtime = substream->runtime;
++
++ snd_at73c213_playback_hw.rate_min = bitrate;
++ snd_at73c213_playback_hw.rate_max = bitrate;
++ runtime->hw = snd_at73c213_playback_hw;
++ chip->substream = substream;
++
++ return 0;
++}
++
++/* close callback */
++static int snd_at73c213_pcm_close(snd_pcm_substream_t *substream)
++{
++ struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
++ chip->substream = NULL;
++ return 0;
++}
++
++/* hw_params callback */
++static int snd_at73c213_pcm_hw_params(snd_pcm_substream_t *substream,
++ snd_pcm_hw_params_t *hw_params)
++{
++#ifdef SND_AT73C213_USE_ALSA_MALLOC_CALLS
++ return snd_pcm_lib_malloc_pages(substream,
++ params_buffer_bytes(hw_params));
++#else
++ int pg;
++ size_t size = params_buffer_bytes(hw_params);
++ struct snd_pcm_runtime *runtime;
++ struct snd_dma_buffer *dmab = NULL;
++
++ substream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV;
++ snd_assert(substream != NULL, return -EINVAL);
++ runtime = substream->runtime;
++ snd_assert(runtime != NULL, return -EINVAL);
++
++ /* check if buffer is already allocated */
++ if (runtime->dma_buffer_p) {
++ size_t size_previouse;
++ int pg_previouse;
++
++ /* new buffer is smaler than previouse allocated buffer */
++ if (runtime->dma_buffer_p->bytes >= size) {
++ runtime->dma_bytes = size;
++ return 0; /* don't change buffer size */
++ }
++
++ size_previouse = runtime->dma_buffer_p->bytes;
++ pg_previouse = get_order(size_previouse);
++
++ dma_free_coherent(runtime->dma_buffer_p->dev.dev,
++ PAGE_SIZE << pg_previouse,
++ runtime->dma_buffer_p->area,
++ runtime->dma_buffer_p->addr);
++
++ kfree(runtime->dma_buffer_p);
++ }
++
++ dmab = kzalloc(sizeof(*dmab), GFP_KERNEL);
++ if (!dmab)
++ return -ENOMEM;
++
++ dmab->dev = substream->dma_buffer.dev;
++ dmab->bytes = 0;
++
++ pg = get_order(size);
++
++ dmab->area = dma_alloc_coherent(
++ substream->dma_buffer.dev.dev,
++ PAGE_SIZE << pg,
++ (dma_addr_t *)&dmab->addr,
++ GFP_KERNEL);
++
++ if (!dmab->area) {
++ kfree(dmab);
++ return -ENOMEM;
++ }
++
++ dmab->bytes = size;
++ snd_pcm_set_runtime_buffer(substream, dmab);
++ runtime->dma_bytes = size;
++ return 1;
++#endif
++}
++
++/* hw_free callback */
++static int snd_at73c213_pcm_hw_free(snd_pcm_substream_t *substream)
++{
++#ifdef SND_AT73C213_USE_ALSA_MALLOC_CALLS
++ return snd_pcm_lib_free_pages(substream);
++#else
++ int pg;
++ struct snd_pcm_runtime *runtime;
++ struct snd_dma_buffer *dmab = NULL;
++
++ snd_assert(substream != NULL, return -EINVAL);
++ runtime = substream->runtime;
++ snd_assert(runtime != NULL, return -EINVAL);
++ dmab = runtime->dma_buffer_p;
++
++ if (!dmab)
++ return 0;
++
++ if (!dmab->area)
++ return 0;
++
++ pg = get_order(dmab->bytes);
++ dma_free_coherent(dmab->dev.dev, PAGE_SIZE << pg, dmab->area, dmab->addr);
++ kfree(runtime->dma_buffer_p);
++ snd_pcm_set_runtime_buffer(substream, NULL);
++ return 0;
++#endif
++}
++
++/* prepare callback */
++static int snd_at73c213_pcm_prepare(snd_pcm_substream_t *substream)
++{
++ struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
++ struct platform_device *pdev = chip->pdev;
++ snd_pcm_runtime_t *runtime = substream->runtime;
++ int block_size;
++
++ block_size = frames_to_bytes(runtime, runtime->period_size);
++
++ chip->period = 0;
++
++ /* Make sure that our data are actually readable by the SSC */
++ dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
++ block_size, DMA_TO_DEVICE);
++ dma_sync_single_for_device(&pdev->dev, runtime->dma_addr + block_size,
++ block_size, DMA_TO_DEVICE);
++
++ __raw_writel(runtime->dma_addr, chip->regs + PDC_TPR);
++ __raw_writel(runtime->period_size * 2, chip->regs + PDC_TCR);
++ __raw_writel(runtime->dma_addr + block_size, chip->regs + PDC_TNPR);
++ __raw_writel(runtime->period_size * 2, chip->regs + PDC_TNCR);
++
++ return 0;
++}
++
++/* trigger callback */
++static int snd_at73c213_pcm_trigger(snd_pcm_substream_t *substream,
++ int cmd)
++{
++ struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
++ int retval = 0;
++ int flags = 0;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ __raw_writel(SSC_INT_ENDTX, chip->regs + SSC_IER);
++ __raw_writel(PDC_PTCR_TXTEN, chip->regs + PDC_PTCR);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ __raw_writel(PDC_PTCR_TXTDIS, chip->regs + PDC_PTCR);
++ __raw_writel(SSC_INT_ENDTX, chip->regs + SSC_IDR);
++ break;
++ default:
++ printk(KERN_WARNING "at73c213: spuriouse command %x\n", cmd);
++ retval = -EINVAL;
++ break;
++ }
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return retval;
++}
++
++/* pointer callback */
++static snd_pcm_uframes_t snd_at73c213_pcm_pointer(snd_pcm_substream_t *substream)
++{
++ struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
++ snd_pcm_runtime_t *runtime = substream->runtime;
++ snd_pcm_uframes_t pos;
++ unsigned long bytes;
++
++ bytes = __raw_readl(chip->regs + PDC_TPR) - runtime->dma_addr;
++
++ pos = bytes_to_frames(runtime, bytes);
++ if (pos >= runtime->buffer_size)
++ pos -= runtime->buffer_size;
++
++ return pos;
++}
++
++/* operators */
++static snd_pcm_ops_t at73c213_playback_ops = {
++ .open = snd_at73c213_pcm_open,
++ .close = snd_at73c213_pcm_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = snd_at73c213_pcm_hw_params,
++ .hw_free = snd_at73c213_pcm_hw_free,
++ .prepare = snd_at73c213_pcm_prepare,
++ .trigger = snd_at73c213_pcm_trigger,
++ .pointer = snd_at73c213_pcm_pointer,
++};
++
++/* free a pcm device */
++static void snd_at73c213_pcm_free(snd_pcm_t *pcm)
++{
++ struct snd_at73c213 *chip = snd_pcm_chip(pcm);
++ if (chip->pcm != 0 ) {
++#ifdef SND_AT73C213_USE_ALSA_MALLOC_CALLS
++ snd_pcm_lib_preallocate_free_for_all(chip->pcm);
++#endif
++ chip->pcm = NULL;
++ }
++}
++
++/* create a new pcm device */
++static int __devinit snd_at73c213_new_pcm(struct snd_at73c213 *chip, int device)
++{
++ snd_pcm_t *pcm;
++ int retval;
++
++ retval = snd_pcm_new(chip->card, chip->card->shortname, device, 1, 0, &pcm);
++ if (retval < 0)
++ return retval;
++
++ pcm->private_data = chip;
++ pcm->private_free = snd_at73c213_pcm_free;
++ pcm->info_flags = SNDRV_PCM_INFO_BLOCK_TRANSFER;
++ strcpy(pcm->name, "at73c213");
++ chip->pcm = pcm;
++
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &at73c213_playback_ops);
++
++#ifdef SND_AT73C213_USE_ALSA_MALLOC_CALLS
++ snd_pcm_lib_preallocate_pages_for_all(chip->pcm, SNDRV_DMA_TYPE_DEV,
++ &chip->pdev->dev, 64 * 1024, 64 * 1024);
++#endif
++
++ return 0;
++}
++
++static irqreturn_t snd_at73c213_interrupt(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct snd_at73c213 *chip = dev_id;
++ struct platform_device *pdev = chip->pdev;
++ snd_pcm_runtime_t *runtime = chip->substream->runtime;
++ u32 status;
++ int offset, next_period, block_size;
++
++ spin_lock(&chip->lock);
++
++ block_size = frames_to_bytes(runtime, runtime->period_size);
++
++ status = __raw_readl(chip->regs + SSC_IMR);
++
++ if (status & SSC_INT_ENDTX) {
++ chip->period++;
++ if (chip->period == runtime->periods)
++ chip->period = 0;
++ next_period = chip->period + 1;
++ if (next_period == runtime->periods)
++ next_period = 0;
++
++ offset = block_size * next_period;
++
++ /* Make sure that our data are actually readable by the SSC */
++ dma_sync_single_for_device(&pdev->dev, runtime->dma_addr + offset,
++ block_size, DMA_TO_DEVICE);
++ __raw_writel(runtime->dma_addr + offset, chip->regs + PDC_TNPR);
++ __raw_writel(runtime->period_size * 2, chip->regs + PDC_TNCR);
++
++ if (next_period == 0) {
++ (void)__raw_readl(chip->regs + PDC_TPR);
++ (void)__raw_readl(chip->regs + PDC_TCR);
++ }
++ } else {
++ printk(KERN_WARNING
++ "Spurious SSC interrupt, status = 0x%08lx\n",
++ (unsigned long)status);
++ __raw_writel(status, chip->regs + SSC_IDR);
++ }
++
++ (void)__raw_readl(chip->regs + SSC_IMR);
++ spin_unlock(&chip->lock);
++
++ if (status & SSC_INT_ENDTX)
++ snd_pcm_period_elapsed(chip->substream);
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * Mixer functions
++ */
++#if 0 /* Function not in use */
++static int snd_at73c213_mono_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ unsigned long mask = (kcontrol->private_value >> 16) & 0xff;
++
++ uinfo->type = (mask == 1) ?
++ SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = mask;
++
++ return 0;
++}
++#endif
++
++static int snd_at73c213_mono_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
++ unsigned long flags;
++ int reg = kcontrol->private_value & 0xff;
++ int shift = (kcontrol->private_value >> 8) & 0xff;
++ int mask = (kcontrol->private_value >> 16) & 0xff;
++ int invert = (kcontrol->private_value >> 24) & 0xff;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
++
++ if (invert)
++ ucontrol->value.integer.value[0] =
++ (mask - ucontrol->value.integer.value[0]);
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return 0;
++}
++
++static int snd_at73c213_mono_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
++ unsigned long flags;
++ int reg = kcontrol->private_value & 0xff;
++ int shift = (kcontrol->private_value >> 8) & 0xff;
++ int mask = (kcontrol->private_value >> 16) & 0xff;
++ int invert = (kcontrol->private_value >> 24) & 0xff;
++ int change, retval;
++ unsigned short val;
++
++ val = (ucontrol->value.integer.value[0] & mask);
++ if (invert)
++ val = mask - val;
++ val <<= shift;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ val = (chip->image[reg] & ~(mask << shift)) | val;
++ change = val != chip->image[reg];
++ write_reg(chip, reg, val);
++
++ chip->image[reg] = val;
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return change;
++
++out:
++ return retval;
++}
++
++static int snd_at73c213_stereo_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ int mask = (kcontrol->private_value >> 24) & 0xFF;
++
++ uinfo->type = mask == 1 ?
++ SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 2;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = mask;
++
++ return 0;
++}
++
++static int snd_at73c213_stereo_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
++ unsigned long flags;
++ int left_reg = kcontrol->private_value & 0xff;
++ int right_reg = (kcontrol->private_value >> 8) & 0xff;
++ int shift_left = (kcontrol->private_value >> 16) & 0x07;
++ int shift_right = (kcontrol->private_value >> 19) & 0x07;
++ int mask = (kcontrol->private_value >> 24) & 0xff;
++ int invert = (kcontrol->private_value >> 22) & 1;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ ucontrol->value.integer.value[0] =
++ (chip->image[left_reg] >> shift_left) & mask;
++ ucontrol->value.integer.value[1] =
++ (chip->image[right_reg] >> shift_right) & mask;
++
++ if (invert) {
++ ucontrol->value.integer.value[0] =
++ (mask - ucontrol->value.integer.value[0]);
++ ucontrol->value.integer.value[1] =
++ (mask - ucontrol->value.integer.value[1]);
++ }
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return 0;
++}
++
++static int snd_at73c213_stereo_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
++ unsigned long flags;
++ int left_reg = kcontrol->private_value & 0xff;
++ int right_reg = (kcontrol->private_value >> 8) & 0xff;
++ int shift_left = (kcontrol->private_value >> 16) & 0x07;
++ int shift_right = (kcontrol->private_value >> 19) & 0x07;
++ int mask = (kcontrol->private_value >> 24) & 0xff;
++ int invert = (kcontrol->private_value >> 22) & 1;
++ int change, retval;
++ unsigned short val1, val2;
++
++ val1 = ucontrol->value.integer.value[0] & mask;
++ val2 = ucontrol->value.integer.value[1] & mask;
++ if (invert) {
++ val1 = mask - val1;
++ val2 = mask - val2;
++ }
++ val1 <<= shift_left;
++ val2 <<= shift_right;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
++ val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
++ change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
++ write_reg(chip, left_reg, val1);
++ write_reg(chip, right_reg, val2);
++
++ chip->image[left_reg] = val1;
++ chip->image[right_reg] = val2;
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return change;
++
++out:
++ return retval;
++}
++
++static int snd_at73c213_mono_switch_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = 1;
++
++ return 0;
++}
++
++static int snd_at73c213_mono_switch_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
++ unsigned long flags;
++ int reg = kcontrol->private_value & 0xff;
++ int shift = (kcontrol->private_value >> 8) & 0xff;
++ int invert = (kcontrol->private_value >> 24) & 0xff;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & 0x01;
++
++ if (invert)
++ ucontrol->value.integer.value[0] =
++ (0x01 - ucontrol->value.integer.value[0]);
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return 0;
++}
++
++static int snd_at73c213_mono_switch_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
++ unsigned long flags;
++ int reg = kcontrol->private_value & 0xff;
++ int shift = (kcontrol->private_value >> 8) & 0xff;
++ int mask = (kcontrol->private_value >> 16) & 0xff;
++ int invert = (kcontrol->private_value >> 24) & 0xff;
++ int change, retval;
++ unsigned short val;
++
++ if (ucontrol->value.integer.value[0])
++ val = mask;
++ else
++ val = 0;
++
++ if (invert)
++ val = mask - val;
++ val <<= shift;
++
++ spin_lock_irqsave(&chip->lock, flags);
++
++ val |= (chip->image[reg] & ~(mask << shift));
++ change = val != chip->image[reg];
++
++ write_reg(chip, reg, val);
++
++ chip->image[reg] = val;
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++
++ return change;
++
++out:
++ return retval;
++}
++
++static int snd_at73c213_pa_volume_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = ((kcontrol->private_value >> 16) & 0xFF) - 1;
++
++ return 0;
++}
++
++static int snd_at73c213_line_capture_volume_info(
++ struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 2;
++ uinfo->value.integer.min = 14;
++ uinfo->value.integer.max = 31;
++
++ return 0;
++}
++
++static int snd_at73c213_aux_capture_volume_info(
++ struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 14;
++ uinfo->value.integer.max = 31;
++
++ return 0;
++}
++
++#define AT73C213_MONO(xname, xindex, reg, shift, mask, invert) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
++ .info = snd_at73c213_mono_info, \
++ .get = snd_at73c213_mono_get, .put = snd_at73c213_mono_put, \
++ .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
++
++#define AT73C213_MONO_SWITCH(xname, xindex, reg, shift, mask, invert) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
++ .info = snd_at73c213_mono_switch_info, \
++ .get = snd_at73c213_mono_switch_get, .put = snd_at73c213_mono_switch_put, \
++ .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
++
++#define AT73C213_STEREO(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
++ .info = snd_at73c213_stereo_info, \
++ .get = snd_at73c213_stereo_get, .put = snd_at73c213_stereo_put, \
++ .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
++
++static struct snd_kcontrol_new snd_at73c213_controls[] __devinitdata = {
++AT73C213_STEREO("Master Playback Volume", 0, DAC_LMPG, DAC_RMPG, 0, 0, 0x1F, 1),
++AT73C213_STEREO("Master Playback Switch", 0, DAC_LMPG, DAC_RMPG, 5, 5, 1, 1),
++AT73C213_STEREO("PCM Playback Volume", 0, DAC_LLOG, DAC_RLOG, 0, 0, 0x1F, 1),
++AT73C213_STEREO("PCM Playback Switch", 0, DAC_LLOG, DAC_RLOG, 5, 5, 1, 1),
++AT73C213_MONO_SWITCH("Mono PA Playback Switch", 0, DAC_CTRL, DAC_CTRL_ONPADRV, 0x01, 0),
++{
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "PA Playback Volume",
++ .index = 0,
++ .info = snd_at73c213_pa_volume_info,
++ .get = snd_at73c213_mono_get,
++ .put = snd_at73c213_mono_put,
++ .private_value = PA_CTRL|(PA_CTRL_APAGAIN<<8)|(0x0F<<16)|(1<<24),
++},
++AT73C213_MONO_SWITCH("PA High Gain Playback Switch", 0, PA_CTRL, PA_CTRL_APALP, 0x01, 1),
++AT73C213_MONO_SWITCH("PA Playback Switch", 0, PA_CTRL, PA_CTRL_APAON, 0x01, 0),
++{
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "Aux Capture Volume",
++ .index = 0,
++ .info = snd_at73c213_aux_capture_volume_info,
++ .get = snd_at73c213_mono_get,
++ .put = snd_at73c213_mono_put,
++ .private_value = DAC_AUXG|(0<<8)|(0x1F<<16)|(1<<24),
++},
++AT73C213_MONO_SWITCH("Aux Capture Switch", 0, DAC_CTRL, DAC_CTRL_ONAUXIN, 0x01, 0),
++{
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "Line Capture Volume",
++ .index = 0,
++ .info = snd_at73c213_line_capture_volume_info,
++ .get = snd_at73c213_stereo_get,
++ .put = snd_at73c213_stereo_put,
++ .private_value = DAC_LLIG|(DAC_RLIG<<8)|(0<<16)|(0<<19)|(0x1F<<24)|(1<<22),
++},
++AT73C213_MONO_SWITCH("Line Capture Switch", 0, DAC_CTRL, 0, 0x03, 0),
++};
++
++static int __devinit snd_at73c213_mixer(struct snd_at73c213 *chip)
++{
++ struct snd_card *card;
++ int errval, idx;
++
++ if (chip == NULL || chip->pcm == NULL)
++ return -EINVAL;
++
++ card = chip->card;
++
++ strcpy(card->mixername, chip->pcm->name);
++
++ for (idx = 0; idx < ARRAY_SIZE(snd_at73c213_controls); idx++) {
++ if ((errval = snd_ctl_add(card,
++ snd_ctl_new1(&snd_at73c213_controls[idx],
++ chip))) < 0)
++ return errval;
++ }
++
++ return 0;
++}
++
++/*
++ * Device functions
++ */
++static int snd_at73c213_chip_init(struct snd_at73c213 *chip)
++{
++ int retval;
++ unsigned char dac_ctrl = 0;
++
++ /* XXX: Unmask the APB clock for SSC0 */
++ __raw_writel(__raw_readl((void __iomem *)PM_BASE + PM_APBAMASK)|(1<<7),
++ (void __iomem *)PM_BASE + PM_APBAMASK);
++
++ /* Wait for clock to be stable */
++ msleep(10);
++
++ retval = snd_at73c213_set_bitrate_and_div();
++ if (retval)
++ goto out;
++
++ /* Reset the SSC */
++ __raw_writel(SSC_CR_SWRST, chip->regs + SSC_CR);
++
++ /* Enable GCLK0 */
++ __raw_writel((1<<30), (void __iomem *)(PIOA_BASE + PIO_PDR));
++ __raw_writel((1<<30), (void __iomem *)(PIOA_BASE + PIO_ASR));
++ __raw_writel(((gclk_div<<8)|0x10|0x04|0x02), (void __iomem *)(PM_BASE + PM_GCCTRL));
++
++ /* Enable SSC and setup for I2S */
++ __raw_writel(ssc_div, chip->regs + SSC_CMR);
++
++ /* CKO, START, STTDLY, PERIOD */
++ __raw_writel((1<<2)|(4<<8)|(1<<16)|(15<<24), chip->regs + SSC_TCMR);
++
++ /* DATLEN, MSBF, DATNB, FSLEN, FSOS */
++ __raw_writel((15<<0)|(1<<7)|(1<<8)|(15<<16)|(1<<20), chip->regs + SSC_TFMR);
++
++ /* Initialize at73c213 on SPI bus */
++ /* Reset the device */
++ write_reg(chip, DAC_RST, 0x04);
++ msleep(1);
++ write_reg(chip, DAC_RST, 0x03);
++
++ /* Turn on precharge */
++ write_reg(chip, DAC_PRECH, 0xFF);
++ write_reg(chip, PA_CTRL, (1<<PA_CTRL_APAPRECH));
++ write_reg(chip, DAC_CTRL, (1<<DAC_CTRL_ONLNOL)|(1<<DAC_CTRL_ONLNOR));
++
++ msleep(50);
++
++ /* Stop precharging PA */
++ write_reg(chip, PA_CTRL, (1<<PA_CTRL_APALP)|0x0F);
++ chip->image[PA_CTRL] = (1<<PA_CTRL_APALP)|0x0F;
++
++ msleep(450);
++
++ /* Stop precharging, turn on master power */
++ write_reg(chip, DAC_PRECH, (1<<DAC_PRECH_ONMSTR));
++ chip->image[DAC_PRECH] = (1<<DAC_PRECH_ONMSTR);
++
++ msleep(1);
++
++ /* Turn on DAC */
++ dac_ctrl = (1<<DAC_CTRL_ONDACL)|(1<<DAC_CTRL_ONDACR)|
++ (1<<DAC_CTRL_ONLNOL)|(1<<DAC_CTRL_ONLNOR);
++
++ write_reg(chip, DAC_CTRL, dac_ctrl);
++ chip->image[DAC_CTRL] = dac_ctrl;
++
++ /* Mute sound */
++ write_reg(chip, DAC_LMPG, 0x3F);
++ chip->image[DAC_LMPG] = 0x3F;
++ write_reg(chip, DAC_RMPG, 0x3F);
++ chip->image[DAC_RMPG] = 0x3F;
++ write_reg(chip, DAC_LLOG, 0x3F);
++ chip->image[DAC_LLOG] = 0x3F;
++ write_reg(chip, DAC_RLOG, 0x3F);
++ chip->image[DAC_RLOG] = 0x3F;
++ write_reg(chip, DAC_LLIG, 0x11);
++ chip->image[DAC_LLIG] = 0x11;
++ write_reg(chip, DAC_RLIG, 0x11);
++ chip->image[DAC_RLIG] = 0x11;
++ write_reg(chip, DAC_AUXG, 0x11);
++ chip->image[DAC_AUXG] = 0x11;
++
++ /* Turn on SSC transmitter */
++ __raw_writel(SSC_CR_TXEN, chip->regs + SSC_CR);
++
++out:
++ return retval;
++}
++
++static int snd_at73c213_dev_free(snd_device_t *device)
++{
++ struct snd_at73c213 *chip = device->device_data;
++
++ if (chip->regs) {
++ __raw_writel(SSC_CR_TXDIS, chip->regs + SSC_CR);
++ iounmap(chip->regs);
++ }
++
++ if (chip->irq >= 0)
++ free_irq(chip->irq, chip);
++
++ if (chip->ssc_clk) {
++ clk_disable(chip->ssc_clk);
++ clk_put(chip->ssc_clk);
++ }
++
++ return 0;
++}
++
++static int __devinit snd_at73c213_create(snd_card_t *card,
++ struct platform_device *pdev)
++{
++ static snd_device_ops_t ops = {
++ .dev_free = snd_at73c213_dev_free,
++ };
++ struct snd_at73c213 *chip = get_chip(card);
++ struct resource *regs;
++ struct clk *ssc_clk;
++ int irq, retval;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++
++ ssc_clk = clk_get(&pdev->dev, "mck");
++ if (IS_ERR(ssc_clk))
++ return PTR_ERR(ssc_clk);
++ clk_enable(ssc_clk);
++ chip->ssc_clk = ssc_clk;
++
++ spin_lock_init(&chip->lock);
++ chip->card = card;
++ chip->pdev = pdev;
++ chip->irq = -1;
++
++ retval = -ENOMEM;
++
++ retval = spi_setup(chip->spi);
++ if (retval)
++ goto out;
++
++ chip->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!chip->regs)
++ goto out;
++
++ retval = request_irq(irq, snd_at73c213_interrupt, 0, "at73c213", chip);
++ if (retval) {
++ snd_printk("unable to request IRQ%d\n", irq);
++ goto out;
++ }
++ chip->irq = irq;
++
++ memcpy(&chip->image, &snd_at73c213_original_image,
++ sizeof(snd_at73c213_original_image));
++
++ retval = snd_at73c213_chip_init(chip);
++ if (retval)
++ goto out;
++
++ retval = snd_at73c213_new_pcm(chip, 0);
++ if (retval)
++ goto out;
++
++ retval = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
++ if (retval)
++ goto out;
++
++ retval = snd_at73c213_mixer(chip);
++ if (retval)
++ goto out;
++
++ snd_card_set_dev(card, &pdev->dev);
++
++out:
++ return retval;
++}
++
++static int __devinit snd_at73c213_probe(struct platform_device *pdev)
++{
++ static int dev;
++ struct spi_board_info *binfo;
++ struct spi_master *smaster;
++ struct snd_at73c213 *chip;
++ snd_card_t *card;
++ int retval;
++
++ if (dev >= SNDRV_CARDS)
++ return -ENODEV;
++ if (!enable[dev]) {
++ dev++;
++ return -ENOENT;
++ }
++
++ if (spi < 0 || ssc < 0)
++ return -ENODEV;
++
++ retval = -ENOMEM;
++ card = snd_card_new(index[dev], id[dev], THIS_MODULE,
++ sizeof(struct snd_at73c213));
++ if (!card)
++ goto out;
++
++ chip = card->private_data;
++
++ retval = -ENODEV;
++
++ /* Get the SPI bus */
++ binfo = pdev->dev.platform_data;
++ if (!binfo) {
++ printk(KERN_WARNING "at73c213: could not get platform data\n");
++ goto out;
++ }
++
++ smaster = spi_busnum_to_master(spi);
++ if (!smaster) {
++ request_module("spi1");
++ smaster = spi_busnum_to_master(spi);
++ if (!smaster) {
++ printk(KERN_WARNING
++ "at73c213: could not get "
++ "SPI bus %d, remembered to load "
++ "the spi_atmel module?\n", spi);
++ goto out;
++ }
++ }
++
++ chip->spi = spi_new_device(smaster, binfo);
++ if (!chip->spi) {
++ printk(KERN_WARNING "at73c213: could not get SPI device %d\n", spi);
++ goto out;
++ }
++
++ chip->spi->mode = SPI_MODE_1;
++ chip->spi->bits_per_word = 8;
++
++ retval = snd_at73c213_create(card, pdev);
++ if (retval)
++ goto out_free_card;
++
++ strcpy(card->driver, "at73c213");
++ strcpy(card->shortname, "at73c213 (AVR32 STK1000)");
++ sprintf(card->longname, "%s at %p (irq %i)", card->shortname, chip->regs, chip->irq);
++
++ retval = snd_card_register(card);
++ if (retval)
++ goto out_free_card;
++
++ platform_set_drvdata(pdev, card);
++ dev++;
++ return 0;
++
++out_free_card:
++ snd_card_free(card);
++out:
++ return retval;
++}
++
++static int __devexit snd_at73c213_remove(struct platform_device *pdev)
++{
++ struct snd_card *card = platform_get_drvdata(pdev);
++ struct snd_at73c213 *chip = card->private_data;
++ int retval;
++
++ /* Stop playback */
++ __raw_writel(SSC_CR_TXDIS, chip->regs + SSC_CR);
++
++ /* Stop GLCK0 */
++ __raw_writel(0, (void __iomem *)PM_BASE + PM_GCCTRL);
++
++ /* Mute sound */
++ write_reg(chip, DAC_LMPG, 0x3F);
++ chip->image[DAC_LMPG] = 0x3F;
++ write_reg(chip, DAC_RMPG, 0x3F);
++ chip->image[DAC_RMPG] = 0x3F;
++ write_reg(chip, DAC_LLOG, 0x3F);
++ chip->image[DAC_LLOG] = 0x3F;
++ write_reg(chip, DAC_RLOG, 0x3F);
++ chip->image[DAC_RLOG] = 0x3F;
++ write_reg(chip, DAC_LLIG, 0x11);
++ chip->image[DAC_LLIG] = 0x11;
++ write_reg(chip, DAC_RLIG, 0x11);
++ chip->image[DAC_RLIG] = 0x11;
++ write_reg(chip, DAC_AUXG, 0x11);
++ chip->image[DAC_AUXG] = 0x11;
++
++ /* Turn off PA */
++ write_reg(chip, PA_CTRL, (chip->image[PA_CTRL]|0x0F));
++ chip->image[PA_CTRL] |= 0x0F;
++ msleep(10);
++ write_reg(chip, PA_CTRL, (1<<PA_CTRL_APALP)|0x0F);
++ chip->image[PA_CTRL] = (1<<PA_CTRL_APALP)|0x0F;
++
++ /* Turn off external DAC */
++ write_reg(chip, DAC_CTRL, 0x0C);
++ chip->image[DAC_CTRL] = 0x0C;
++ msleep(2);
++ write_reg(chip, DAC_CTRL, 0x00);
++ chip->image[DAC_CTRL] = 0x00;
++
++ /* Turn off master power */
++ write_reg(chip, DAC_PRECH, 0x00);
++ chip->image[DAC_PRECH] = 0x00;
++
++ msleep(10);
++
++out:
++ if (chip->spi)
++ spi_unregister_device(chip->spi);
++
++ if (card) {
++ snd_card_free(card);
++ platform_set_drvdata(pdev, NULL);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int snd_at73c213_suspend(struct platform_device *pdev, pm_message_t state, u32 level)
++{
++ struct snd_card *card = at32_get_drvdata(pdev);
++ struct snd_at73c213 *chip = card->private_data;
++
++ printk(KERN_DEBUG "at73c213: suspending\n");
++
++ /* Stop SSC and GCLK0 */
++
++ spi_suspend(chip->spi, state);
++
++ return 0;
++}
++
++static int snd_at73c213_resume(struct platform_device *pdev, u32 level)
++{
++ struct snd_card *card = at32_get_drvdata(pdev);
++ struct snd_at73c213 *chip = card->private_data;
++
++ printk(KERN_DEBUG "at73c213: resuming\n");
++
++ /* Start GLCK0 and SSC */
++
++ spi_resume(chip->spi);
++
++ return 0;
++}
++#endif /* CONFIG_PM */
++
++/* Driver core initialization */
++static struct platform_driver at73c213_driver = {
++ .probe = snd_at73c213_probe,
++ .remove = __devexit_p(snd_at73c213_remove),
++ .driver = {
++ .name = "at73c213",
++ }
++#ifdef CONFIG_PM
++ .resume = snd_at73c213_resume,
++ .suspend = snd_at73c213_suspend,
++#endif
++};
++
++static int __init at73c213_init(void)
++{
++ return platform_driver_register(&at73c213_driver);
++}
++
++static void __exit at73c213_exit(void)
++{
++ platform_driver_unregister(&at73c213_driver);
++}
++
++MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
++MODULE_DESCRIPTION("Sound driver for at73c213 on STK1000");
++MODULE_LICENSE("GPL");
++
++module_init(at73c213_init);
++module_exit(at73c213_exit);
++
+Index: linux-2.6.18-avr32/sound/avr32/at73c213.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/sound/avr32/at73c213.h 2006-11-02 15:56:20.000000000 +0100
+@@ -0,0 +1,120 @@
++/*
++ * Driver for the AT73C213 16-bit stereo DAC on Atmel ATSTK1000
++ *
++ * Copyright (C) 2006 Atmel Norway
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++ * 02111-1307, USA.
++ *
++ * The full GNU General Public License is included in this
++ * distribution in the file called COPYING.
++ */
++
++#ifndef _SND_AT73C213_MIXER_H_
++#define _SND_AT73C213_MIXER_H_
++
++/* DAC control register */
++#define DAC_CTRL 0x00
++#define DAC_CTRL_ONPADRV 7
++#define DAC_CTRL_ONAUXIN 6
++#define DAC_CTRL_ONDACR 5
++#define DAC_CTRL_ONDACL 4
++#define DAC_CTRL_ONLNOR 3
++#define DAC_CTRL_ONLNOL 2
++#define DAC_CTRL_ONLNIR 1
++#define DAC_CTRL_ONLNIL 0
++
++/* DAC left line in gain register */
++#define DAC_LLIG 0x01
++#define DAC_LLIG_LLIG 0
++
++/* DAC right line in gain register */
++#define DAC_RLIG 0x02
++#define DAC_RLIG_RLIG 0
++
++/* DAC Left Master Playback Gain Register */
++#define DAC_LMPG 0x03
++#define DAC_LMPG_LMPG 0
++
++/* DAC Right Master Playback Gain Register */
++#define DAC_RMPG 0x04
++#define DAC_RMPG_RMPG 0
++
++/* DAC Left Line Out Gain Register */
++#define DAC_LLOG 0x05
++#define DAC_LLOG_LLOG 0
++
++/* DAC Right Line Out Gain Register */
++#define DAC_RLOG 0x06
++#define DAC_RLOG_RLOG 0
++
++/* DAC Output Level Control Register */
++#define DAC_OLC 0x07
++#define DAC_OLC_RSHORT 7
++#define DAC_OLC_ROLC 4
++#define DAC_OLC_LSHORT 3
++#define DAC_OLC_LOLC 0
++
++/* DAC Mixer Control Register */
++#define DAC_MC 0x08
++#define DAC_MC_INVR 5
++#define DAC_MC_INVL 4
++#define DAC_MC_RMSMIN2 3
++#define DAC_MC_RMSMIN1 2
++#define DAC_MC_LMSMIN2 1
++#define DAC_MC_LMSMIN1 0
++
++/* DAC Clock and Sampling Frequency Control Register */
++#define DAC_CSFC 0x09
++#define DAC_CSFC_OVRSEL 4
++
++/* DAC Miscellaneous Register */
++#define DAC_MISC 0x0A
++#define DAC_MISC_VCMCAPSEL 7
++#define DAC_MISC_DINTSEL 4
++#define DAC_MISC_DITHEN 3
++#define DAC_MISC_DEEMPEN 2
++#define DAC_MISC_NBITS 0
++
++/* DAC Precharge Control Register */
++#define DAC_PRECH 0x0C
++#define DAC_PRECH_PRCHGPDRV 7
++#define DAC_PRECH_PRCHGAUX1 6
++#define DAC_PRECH_PRCHGLNOR 5
++#define DAC_PRECH_PRCHGLNOL 4
++#define DAC_PRECH_PRCHGLNIR 3
++#define DAC_PRECH_PRCHGLNIL 2
++#define DAC_PRECH_PRCHG 1
++#define DAC_PRECH_ONMSTR 0
++
++/* DAC Auxiliary Input Gain Control Register */
++#define DAC_AUXG 0x0D
++#define DAC_AUXG_AUXG 0
++
++/* DAC Reset Register */
++#define DAC_RST 0x10
++#define DAC_RST_RESMASK 2
++#define DAC_RST_RESFILZ 1
++#define DAC_RST_RSTZ 0
++
++/* Power Amplifier Control Register */
++#define PA_CTRL 0x11
++#define PA_CTRL_APAON 6
++#define PA_CTRL_APAPRECH 5
++#define PA_CTRL_APALP 4
++#define PA_CTRL_APAGAIN 0
++
++#endif
++
diff --git a/packages/linux/linux-2.6.18/atmel-ac97c-alsa-driver.patch b/packages/linux/linux-2.6.18/atmel-ac97c-alsa-driver.patch
new file mode 100644
index 0000000000..fe3d2ee209
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-ac97c-alsa-driver.patch
@@ -0,0 +1,1383 @@
+---
+ sound/avr32/Kconfig | 25 +
+ sound/avr32/Makefile | 3
+ sound/avr32/ac97c.c | 1250 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ sound/avr32/ac97c.h | 71 ++
+ 4 files changed, 1349 insertions(+)
+
+Index: linux-2.6.18-avr32/sound/avr32/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/avr32/Kconfig 2006-11-02 15:56:20.000000000 +0100
++++ linux-2.6.18-avr32/sound/avr32/Kconfig 2006-11-02 16:02:29.000000000 +0100
+@@ -3,4 +3,29 @@
+ menu "ALSA AVR32 devices"
+ depends on SND != n && AVR32
+
++config SND_ATMEL_AC97
++ tristate "Atmel AC97 Controller Driver"
++ depends on SND
++ select SND_PCM
++ select SND_AC97_CODEC
++ help
++ ALSA sound driver for the Atmel AC97 controller.
++
++config SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++ bool "Use the built-in malloc calls in the alsa driver"
++ default n
++ depends on SND_ATMEL_AC97
++ help
++ Say Y if the built-in malloc calls in the alsa driver should be
++ used instead of the native dma_alloc_coherent and dma_free_coherent
++ function calls. Enabling this feature may break the rmmod feature.
++
++config SND_ATMEL_AC97C_USE_PDC
++ bool "Use PDC for DMA transfers to/from the Atmel AC97 Controller"
++ default n
++ depends on SND_ATMEL_AC97
++ help
++ Say Y if PDC (Peripheral DMA Controller) is used for DMA transfers
++ to/from the Atmel AC97C instead of using the generic DMA framework.
++
+ endmenu
+Index: linux-2.6.18-avr32/sound/avr32/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/sound/avr32/Makefile 2006-11-02 15:56:20.000000000 +0100
++++ linux-2.6.18-avr32/sound/avr32/Makefile 2006-11-02 16:02:29.000000000 +0100
+@@ -1,3 +1,6 @@
+ #
+ # Makefile for ALSA
+ #
++
++snd-atmel-ac97-objs := ac97c.o
++obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
+Index: linux-2.6.18-avr32/sound/avr32/ac97c.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/sound/avr32/ac97c.c 2006-11-02 16:02:56.000000000 +0100
+@@ -0,0 +1,1250 @@
++/*
++ * Driver for the Atmel AC97 Controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/mutex.h>
++
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/initval.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/ac97_codec.h>
++#ifndef SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++#include <sound/memalloc.h>
++#endif
++
++#include <asm/io.h>
++
++#include "ac97c.h"
++
++static DEFINE_MUTEX(opened_mutex);
++
++/* module parameters */
++static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
++static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
++static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
++
++module_param_array(index, int, NULL, 0444);
++MODULE_PARM_DESC(index, "Index value for AC97 controller");
++module_param_array(id, charp, NULL, 0444);
++MODULE_PARM_DESC(id, "ID string for AC97 controller");
++module_param_array(enable, bool, NULL, 0444);
++MODULE_PARM_DESC(enable, "Enable AC97 controller");
++
++#ifndef CONFIG_SND_ATMEL_AC97C_USE_PDC
++#include <asm/dma-controller.h>
++
++struct atmel_ac97_dma_info {
++ struct dma_request_cyclic req_tx;
++ struct dma_request_cyclic req_rx;
++ unsigned short rx_periph_id;
++ unsigned short tx_periph_id;
++};
++#endif
++
++
++typedef struct atmel_ac97 {
++ spinlock_t lock;
++ void __iomem *regs;
++ int period;
++
++ snd_pcm_substream_t *playback_substream;
++ snd_pcm_substream_t *capture_substream;
++ snd_card_t *card;
++ snd_pcm_t *pcm;
++ ac97_t *ac97;
++ ac97_bus_t *ac97_bus;
++ int irq;
++ int opened;
++ u64 cur_format;
++ unsigned int cur_rate;
++ struct clk *mck;
++ struct platform_device *pdev;
++ struct atmel_ac97_dma_info dma;
++} atmel_ac97_t;
++#define get_chip(card) ((atmel_ac97_t *)(card)->private_data)
++
++#define ac97c_writel(chip, reg, val) \
++ __raw_writel((val), (chip)->regs + AC97C_##reg)
++#define ac97c_readl(chip, reg) \
++ __raw_readl((chip)->regs + AC97C_##reg)
++
++/* PCM part */
++
++static snd_pcm_hardware_t snd_atmel_ac97_playback_hw = {
++ .info = (SNDRV_PCM_INFO_INTERLEAVED
++ |SNDRV_PCM_INFO_MMAP
++ |SNDRV_PCM_INFO_MMAP_VALID
++ |SNDRV_PCM_INFO_BLOCK_TRANSFER
++ |SNDRV_PCM_INFO_JOINT_DUPLEX),
++ .formats = (SNDRV_PCM_FMTBIT_S16_BE|SNDRV_PCM_FMTBIT_S16_LE),
++ .rates = (SNDRV_PCM_RATE_CONTINUOUS),
++ .rate_min = 4000,
++ .rate_max = 48000,
++ .channels_min = 1,
++ .channels_max = 6,
++ .buffer_bytes_max = 64*1024,
++ .period_bytes_min = 512,
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ .period_bytes_max = 64*1024,
++#else
++ .period_bytes_max = 4095,
++#endif
++ .periods_min = 8,
++ .periods_max = 1024,
++};
++
++static snd_pcm_hardware_t snd_atmel_ac97_capture_hw = {
++ .info = (SNDRV_PCM_INFO_INTERLEAVED
++ |SNDRV_PCM_INFO_MMAP
++ |SNDRV_PCM_INFO_MMAP_VALID
++ |SNDRV_PCM_INFO_BLOCK_TRANSFER
++ |SNDRV_PCM_INFO_JOINT_DUPLEX),
++ .formats = (SNDRV_PCM_FMTBIT_S16_BE|SNDRV_PCM_FMTBIT_S16_LE),
++ .rates = (SNDRV_PCM_RATE_CONTINUOUS),
++ .rate_min = 4000,
++ .rate_max = 48000,
++ .channels_min = 1,
++ .channels_max = 2,
++ .buffer_bytes_max = 64*1024,
++ .period_bytes_min = 512,
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ .period_bytes_max = 64*1024,
++#else
++ .period_bytes_max = 4095,
++#endif
++ .periods_min = 8,
++ .periods_max = 1024,
++};
++
++/* Joint full duplex variables */
++unsigned int hw_rates[1];
++unsigned int hw_formats[1];
++struct snd_pcm_hw_constraint_list hw_constraint_rates;
++struct snd_pcm_hw_constraint_list hw_constraint_formats;
++
++/*
++ * PCM functions
++ */
++static int
++snd_atmel_ac97_playback_open(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ snd_pcm_runtime_t *runtime = substream->runtime;
++
++ mutex_lock(&opened_mutex);
++ chip->opened++;
++ runtime->hw = snd_atmel_ac97_playback_hw;
++ if (chip->cur_rate) {
++ runtime->hw.rate_min = chip->cur_rate;
++ runtime->hw.rate_max = chip->cur_rate;
++ }
++ if (chip->cur_format)
++ runtime->hw.formats = (1ULL<<chip->cur_format);
++ mutex_unlock(&opened_mutex);
++ chip->playback_substream = substream;
++ chip->period = 0;
++ return 0;
++}
++
++static int
++snd_atmel_ac97_capture_open(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ snd_pcm_runtime_t *runtime = substream->runtime;
++
++ mutex_lock(&opened_mutex);
++ chip->opened++;
++ runtime->hw = snd_atmel_ac97_capture_hw;
++ if (chip->cur_rate) {
++ runtime->hw.rate_min = chip->cur_rate;
++ runtime->hw.rate_max = chip->cur_rate;
++ }
++ if (chip->cur_format)
++ runtime->hw.formats = (1ULL<<chip->cur_format);
++ mutex_unlock(&opened_mutex);
++ chip->capture_substream = substream;
++ chip->period = 0;
++ return 0;
++}
++
++static int snd_atmel_ac97_playback_close(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ mutex_lock(&opened_mutex);
++ chip->opened--;
++ if (!chip->opened) {
++ chip->cur_rate = 0;
++ chip->cur_format = 0;
++ }
++ mutex_unlock(&opened_mutex);
++ return 0;
++}
++
++static int snd_atmel_ac97_capture_close(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ mutex_lock(&opened_mutex);
++ chip->opened--;
++ if (!chip->opened) {
++ chip->cur_rate = 0;
++ chip->cur_format = 0;
++ }
++ mutex_unlock(&opened_mutex);
++ return 0;
++}
++
++static int snd_atmel_ac97_playback_hw_params(snd_pcm_substream_t *substream,
++ snd_pcm_hw_params_t *hw_params)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++#ifdef SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++ int err;
++ err = snd_pcm_lib_malloc_pages(substream,
++ params_buffer_bytes(hw_params));
++
++ if (err < 0)
++ return err;
++
++ /* Set restrictions to params */
++ mutex_lock(&opened_mutex);
++ chip->cur_rate = params_rate(hw_params);
++ chip->cur_format = params_format(hw_params);
++ mutex_unlock(&opened_mutex);
++
++ return err;
++#else
++ int pg;
++ size_t size = params_buffer_bytes(hw_params);
++ struct snd_pcm_runtime *runtime;
++ struct snd_dma_buffer *dmab = NULL;
++
++ substream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV;
++ snd_assert(substream != NULL, return -EINVAL);
++ runtime = substream->runtime;
++ snd_assert(runtime != NULL, return -EINVAL);
++
++ /* Set restrictions to params */
++ mutex_lock(&opened_mutex);
++ chip->cur_rate = params_rate(hw_params);
++ chip->cur_format = params_format(hw_params);
++ mutex_unlock(&opened_mutex);
++
++ /* check if buffer is already allocated */
++ if (runtime->dma_buffer_p) {
++ size_t size_previouse;
++ int pg_previouse;
++
++ /* new buffer is smaler than previouse allocated buffer */
++ if (runtime->dma_buffer_p->bytes >= size) {
++ runtime->dma_bytes = size;
++ return 0; /* don't change buffer size */
++ }
++
++ size_previouse = runtime->dma_buffer_p->bytes;
++ pg_previouse = get_order(size_previouse);
++
++ dma_free_coherent(runtime->dma_buffer_p->dev.dev,
++ PAGE_SIZE << pg_previouse,
++ runtime->dma_buffer_p->area,
++ runtime->dma_buffer_p->addr);
++
++ kfree(runtime->dma_buffer_p);
++ }
++
++ dmab = kzalloc(sizeof(*dmab), GFP_KERNEL);
++ if (!dmab)
++ return -ENOMEM;
++
++ dmab->dev = substream->dma_buffer.dev;
++ dmab->bytes = 0;
++
++ pg = get_order(size);
++
++ dmab->area = dma_alloc_coherent(
++ substream->dma_buffer.dev.dev,
++ PAGE_SIZE << pg,
++ (dma_addr_t *)&dmab->addr,
++ GFP_KERNEL);
++
++ if (!dmab->area) {
++ kfree(dmab);
++ return -ENOMEM;
++ }
++
++ dmab->bytes = size;
++
++ snd_pcm_set_runtime_buffer(substream, dmab);
++ runtime->dma_bytes = size;
++ return 1;
++#endif
++}
++
++static int snd_atmel_ac97_capture_hw_params(snd_pcm_substream_t *substream,
++ snd_pcm_hw_params_t *hw_params)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++#ifdef SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++ int err;
++ err = snd_pcm_lib_malloc_pages(substream,
++ params_buffer_bytes(hw_params));
++
++ if (err < 0)
++ return err;
++
++ /* Set restrictions to params */
++ mutex_lock(&opened_mutex);
++ chip->cur_rate = params_rate(hw_params);
++ chip->cur_format = params_format(hw_params);
++ mutex_unlock(&opened_mutex);
++
++ return err;
++#else
++ int pg;
++ size_t size = params_buffer_bytes(hw_params);
++ struct snd_pcm_runtime *runtime;
++ struct snd_dma_buffer *dmab = NULL;
++
++ substream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV;
++ snd_assert(substream != NULL, return -EINVAL);
++ runtime = substream->runtime;
++ snd_assert(runtime != NULL, return -EINVAL);
++
++ /* Set restrictions to params */
++ mutex_lock(&opened_mutex);
++ chip->cur_rate = params_rate(hw_params);
++ chip->cur_format = params_format(hw_params);
++ mutex_unlock(&opened_mutex);
++
++ /* check if buffer is already allocated */
++ if (runtime->dma_buffer_p) {
++ size_t size_previouse;
++ int pg_previouse;
++
++ /* new buffer is smaler than previouse allocated buffer */
++ if (runtime->dma_buffer_p->bytes >= size) {
++ runtime->dma_bytes = size;
++ return 0; /* don't change buffer size */
++ }
++
++ size_previouse = runtime->dma_buffer_p->bytes;
++ pg_previouse = get_order(size_previouse);
++
++ dma_free_coherent(runtime->dma_buffer_p->dev.dev,
++ PAGE_SIZE << pg_previouse,
++ runtime->dma_buffer_p->area,
++ runtime->dma_buffer_p->addr);
++
++ kfree(runtime->dma_buffer_p);
++ }
++
++ dmab = kzalloc(sizeof(*dmab), GFP_KERNEL);
++ if (!dmab)
++ return -ENOMEM;
++
++ dmab->dev = substream->dma_buffer.dev;
++ dmab->bytes = 0;
++
++ pg = get_order(size);
++
++ dmab->area = dma_alloc_coherent(
++ substream->dma_buffer.dev.dev,
++ PAGE_SIZE << pg,
++ (dma_addr_t *)&dmab->addr,
++ GFP_KERNEL);
++
++ if (!dmab->area) {
++ kfree(dmab);
++ return -ENOMEM;
++ }
++
++ dmab->bytes = size;
++
++ snd_pcm_set_runtime_buffer(substream, dmab);
++ runtime->dma_bytes = size;
++ return 1;
++#endif
++}
++
++static int snd_atmel_ac97_playback_hw_free(snd_pcm_substream_t *substream)
++{
++#ifdef SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++ return snd_pcm_lib_free_pages(substream);
++#else
++ int pg;
++ struct snd_pcm_runtime *runtime;
++ struct snd_dma_buffer *dmab = NULL;
++
++ snd_assert(substream != NULL, return -EINVAL);
++ runtime = substream->runtime;
++ snd_assert(runtime != NULL, return -EINVAL);
++ dmab = runtime->dma_buffer_p;
++
++ if (!dmab)
++ return 0;
++
++ if (!dmab->area)
++ return 0;
++
++ pg = get_order(dmab->bytes);
++ dma_free_coherent(dmab->dev.dev, PAGE_SIZE << pg, dmab->area, dmab->addr);
++ kfree(runtime->dma_buffer_p);
++ snd_pcm_set_runtime_buffer(substream, NULL);
++ return 0;
++#endif
++}
++
++static int snd_atmel_ac97_capture_hw_free(snd_pcm_substream_t *substream)
++{
++
++#ifdef SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++ return snd_pcm_lib_free_pages(substream);
++#else
++ int pg;
++ struct snd_pcm_runtime *runtime;
++ struct snd_dma_buffer *dmab = NULL;
++
++ snd_assert(substream != NULL, return -EINVAL);
++ runtime = substream->runtime;
++ snd_assert(runtime != NULL, return -EINVAL);
++ dmab = runtime->dma_buffer_p;
++
++ if (!dmab)
++ return 0;
++
++ if (!dmab->area)
++ return 0;
++
++ pg = get_order(dmab->bytes);
++ dma_free_coherent(dmab->dev.dev, PAGE_SIZE << pg, dmab->area, dmab->addr);
++ kfree(runtime->dma_buffer_p);
++ snd_pcm_set_runtime_buffer(substream, NULL);
++ return 0;
++#endif
++}
++
++static int snd_atmel_ac97_playback_prepare(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ struct platform_device *pdev = chip->pdev;
++ snd_pcm_runtime_t *runtime = substream->runtime;
++ int block_size = frames_to_bytes(runtime, runtime->period_size);
++ unsigned long word = 0;
++ unsigned long buffer_size = 0;
++
++ dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
++ block_size * 2, DMA_TO_DEVICE);
++
++ /* Assign slots to channels */
++ switch (substream->runtime->channels) {
++ case 1:
++ word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
++ break;
++ case 2:
++ /* Assign Left and Right slot to Channel A */
++ word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
++ | AC97C_CH_ASSIGN(PCM_RIGHT, A);
++ break;
++ default:
++ /* TODO: support more than two channels */
++ return -EINVAL;
++ break;
++ }
++ ac97c_writel(chip, OCA, word);
++
++ /* Configure sample format and size */
++ word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
++
++ switch (runtime->format){
++ case SNDRV_PCM_FORMAT_S16_LE:
++ word |= AC97C_CMR_CEM_LITTLE;
++ break;
++ case SNDRV_PCM_FORMAT_S16_BE:
++ default:
++ word &= ~AC97C_CMR_CEM_LITTLE;
++ break;
++ }
++
++ ac97c_writel(chip, CAMR, word);
++
++ /* Set variable rate if needed */
++ if (runtime->rate != 48000) {
++ word = ac97c_readl(chip, MR);
++ word |= AC97C_MR_VRA;
++ ac97c_writel(chip, MR, word);
++ } else {
++ /* Clear Variable Rate Bit */
++ word = ac97c_readl(chip, MR);
++ word &= ~AC97C_MR_VRA;
++ ac97c_writel(chip, MR, word);
++ }
++
++ /* Set rate */
++ snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ /* Initialize and start the PDC */
++ ac97c_writel(chip, CATPR, runtime->dma_addr);
++ ac97c_writel(chip, CATCR, block_size / 4);
++ ac97c_writel(chip, CATNPR, runtime->dma_addr + block_size);
++ ac97c_writel(chip, CATNCR, block_size / 4);
++ ac97c_writel(chip, PTCR, PDC_PTCR_TXTEN);
++ /* Enable Channel A interrupts */
++ ac97c_writel(chip, IER, AC97C_SR_CAEVT);
++#else
++ buffer_size = frames_to_bytes(runtime, runtime->period_size) *
++ runtime->periods;
++
++ chip->dma.req_tx.buffer_size = buffer_size;
++ chip->dma.req_tx.periods = runtime->periods;
++
++ BUG_ON(chip->dma.req_tx.buffer_size !=
++ (chip->dma.req_tx.periods *
++ frames_to_bytes(runtime, runtime->period_size)));
++
++ chip->dma.req_tx.buffer_start = runtime->dma_addr;
++ chip->dma.req_tx.data_reg = (dma_addr_t)(chip->regs + AC97C_CATHR + 2);
++ chip->dma.req_tx.periph_id = chip->dma.tx_periph_id;
++ chip->dma.req_tx.direction = DMA_DIR_MEM_TO_PERIPH;
++ chip->dma.req_tx.width = DMA_WIDTH_16BIT;
++ chip->dma.req_tx.dev_id = chip;
++#endif
++
++ return 0;
++}
++
++static int snd_atmel_ac97_capture_prepare(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ struct platform_device *pdev = chip->pdev;
++ snd_pcm_runtime_t *runtime = substream->runtime;
++ int block_size = frames_to_bytes(runtime, runtime->period_size);
++ unsigned long word = 0;
++ unsigned long buffer_size = 0;
++
++ dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
++ block_size * 2, DMA_FROM_DEVICE);
++
++ /* Assign slots to channels */
++ switch (substream->runtime->channels) {
++ case 1:
++ word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
++ break;
++ case 2:
++ /* Assign Left and Right slot to Channel A */
++ word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
++ | AC97C_CH_ASSIGN(PCM_RIGHT, A);
++ break;
++ default:
++ /* TODO: support more than two channels */
++ return -EINVAL;
++ break;
++ }
++ ac97c_writel(chip, ICA, word);
++
++ /* Configure sample format and size */
++ word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
++
++ switch (runtime->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ word |= AC97C_CMR_CEM_LITTLE;
++ break;
++ case SNDRV_PCM_FORMAT_S16_BE:
++ default:
++ word &= ~(AC97C_CMR_CEM_LITTLE);
++ break;
++ }
++
++ ac97c_writel(chip, CAMR, word);
++
++ /* Set variable rate if needed */
++ if (runtime->rate != 48000) {
++ word = ac97c_readl(chip, MR);
++ word |= AC97C_MR_VRA;
++ ac97c_writel(chip, MR, word);
++ } else {
++ /* Clear Variable Rate Bit */
++ word = ac97c_readl(chip, MR);
++ word &= ~(AC97C_MR_VRA);
++ ac97c_writel(chip, MR, word);
++ }
++
++ /* Set rate */
++ snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ /* Initialize and start the PDC */
++ ac97c_writel(chip, CARPR, runtime->dma_addr);
++ ac97c_writel(chip, CARCR, block_size / 4);
++ ac97c_writel(chip, CARNPR, runtime->dma_addr + block_size);
++ ac97c_writel(chip, CARNCR, block_size / 4);
++ ac97c_writel(chip, PTCR, PDC_PTCR_RXEN);
++ /* Enable Channel A interrupts */
++ ac97c_writel(chip, IER, AC97C_SR_CAEVT);
++#else
++ buffer_size = frames_to_bytes(runtime, runtime->period_size) *
++ runtime->periods;
++
++ chip->dma.req_rx.buffer_size = buffer_size;
++ chip->dma.req_rx.periods = runtime->periods;
++
++ BUG_ON(chip->dma.req_rx.buffer_size !=
++ (chip->dma.req_rx.periods *
++ frames_to_bytes(runtime, runtime->period_size)));
++
++ chip->dma.req_rx.buffer_start = runtime->dma_addr;
++ chip->dma.req_rx.data_reg = (dma_addr_t)(chip->regs + AC97C_CARHR + 2);
++ chip->dma.req_rx.periph_id = chip->dma.rx_periph_id;
++ chip->dma.req_rx.direction = DMA_DIR_PERIPH_TO_MEM;
++ chip->dma.req_rx.width = DMA_WIDTH_16BIT;
++ chip->dma.req_rx.dev_id = chip;
++#endif
++
++ return 0;
++}
++
++static int snd_atmel_ac97_playback_trigger(snd_pcm_substream_t *substream, int cmd)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ unsigned long camr;
++ int flags, err = 0;
++
++ spin_lock_irqsave(&chip->lock, flags);
++ camr = ac97c_readl(chip, CAMR);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ err = dma_prepare_request_cyclic(chip->dma.req_tx.req.dmac,
++ &chip->dma.req_tx);
++ dma_start_request(chip->dma.req_tx.req.dmac,
++ chip->dma.req_tx.req.channel);
++ camr |= (AC97C_CMR_CENA
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ |AC97C_CMR_TXRDY
++#endif
++ );
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ err = dma_stop_request(chip->dma.req_tx.req.dmac,
++ chip->dma.req_tx.req.channel);
++ if (chip->opened <= 1) {
++ camr &= ~(AC97C_CMR_CENA
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ |AC97C_CMR_TXRDY
++#endif
++ );
++ }
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ else {
++ camr &= ~(AC97C_CMR_TXRDY);
++ }
++#endif
++ break;
++ default:
++ err = -EINVAL;
++ break;
++ }
++
++ ac97c_writel(chip, CAMR, camr);
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++ return err;
++}
++
++static int snd_atmel_ac97_capture_trigger(snd_pcm_substream_t *substream, int cmd)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ unsigned long camr;
++ int flags, err = 0;
++
++ spin_lock_irqsave(&chip->lock, flags);
++ camr = ac97c_readl(chip, CAMR);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ err = dma_prepare_request_cyclic(chip->dma.req_rx.req.dmac,
++ &chip->dma.req_rx);
++ dma_start_request(chip->dma.req_rx.req.dmac,
++ chip->dma.req_rx.req.channel);
++ camr |= (AC97C_CMR_CENA
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ | AC97C_CMR_RXRDY
++#endif
++ );
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ err = dma_stop_request(chip->dma.req_rx.req.dmac,
++ chip->dma.req_rx.req.channel);
++ mutex_lock(&opened_mutex);
++ if (chip->opened <= 1) {
++ camr &= ~(AC97C_CMR_CENA
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ | AC97C_CMR_RXRDY
++#endif
++ );
++ }
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ else {
++ camr &= ~(AC97C_CSR_RXRDY);
++ }
++#endif
++ mutex_unlock(&opened_mutex);
++ break;
++ default:
++ err = -EINVAL;
++ break;
++ }
++
++ ac97c_writel(chip, CAMR, camr);
++
++ spin_unlock_irqrestore(&chip->lock, flags);
++ return err;
++}
++
++static snd_pcm_uframes_t snd_atmel_ac97_playback_pointer(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ snd_pcm_runtime_t *runtime = substream->runtime;
++ snd_pcm_uframes_t pos;
++ unsigned long bytes;
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ bytes = ac97c_readl(chip, CATPR) - runtime->dma_addr;
++#else
++ bytes = (dma_get_current_pos
++ (chip->dma.req_tx.req.dmac,
++ chip->dma.req_tx.req.channel) - runtime->dma_addr);
++#endif
++ pos = bytes_to_frames(runtime, bytes);
++ if (pos >= runtime->buffer_size)
++ pos -= runtime->buffer_size;
++
++ return pos;
++}
++
++static snd_pcm_uframes_t snd_atmel_ac97_capture_pointer(snd_pcm_substream_t *substream)
++{
++ atmel_ac97_t *chip = snd_pcm_substream_chip(substream);
++ snd_pcm_runtime_t *runtime = substream->runtime;
++ snd_pcm_uframes_t pos;
++ unsigned long bytes;
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ bytes = ac97c_readl(chip, CARPR) - runtime->dma_addr;
++#else
++ bytes = (dma_get_current_pos
++ (chip->dma.req_rx.req.dmac,chip->dma.req_rx.req.channel) -
++ runtime->dma_addr);
++#endif
++ pos = bytes_to_frames(runtime, bytes);
++ if (pos >= runtime->buffer_size)
++ pos -= runtime->buffer_size;
++
++
++ return pos;
++}
++
++static snd_pcm_ops_t atmel_ac97_playback_ops = {
++ .open = snd_atmel_ac97_playback_open,
++ .close = snd_atmel_ac97_playback_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = snd_atmel_ac97_playback_hw_params,
++ .hw_free = snd_atmel_ac97_playback_hw_free,
++ .prepare = snd_atmel_ac97_playback_prepare,
++ .trigger = snd_atmel_ac97_playback_trigger,
++ .pointer = snd_atmel_ac97_playback_pointer,
++};
++
++static snd_pcm_ops_t atmel_ac97_capture_ops = {
++ .open = snd_atmel_ac97_capture_open,
++ .close = snd_atmel_ac97_capture_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = snd_atmel_ac97_capture_hw_params,
++ .hw_free = snd_atmel_ac97_capture_hw_free,
++ .prepare = snd_atmel_ac97_capture_prepare,
++ .trigger = snd_atmel_ac97_capture_trigger,
++ .pointer = snd_atmel_ac97_capture_pointer,
++};
++
++static struct ac97_pcm atmel_ac97_pcm_defs[] __devinitdata = {
++ /* Playback */
++ {
++ .exclusive = 1,
++ .r = { {
++ .slots = ((1 << AC97_SLOT_PCM_LEFT)
++ | (1 << AC97_SLOT_PCM_RIGHT)
++ | (1 << AC97_SLOT_PCM_CENTER)
++ | (1 << AC97_SLOT_PCM_SLEFT)
++ | (1 << AC97_SLOT_PCM_SRIGHT)
++ | (1 << AC97_SLOT_LFE)),
++ } }
++ },
++ /* PCM in */
++ {
++ .stream = 1,
++ .exclusive = 1,
++ .r = { {
++ .slots = ((1 << AC97_SLOT_PCM_LEFT)
++ | (1 << AC97_SLOT_PCM_RIGHT)),
++ } }
++ },
++ /* Mic in */
++ {
++ .stream = 1,
++ .exclusive = 1,
++ .r = { {
++ .slots = (1<<AC97_SLOT_MIC),
++ } }
++ },
++};
++
++static int __devinit snd_atmel_ac97_pcm_new(atmel_ac97_t *chip)
++{
++ snd_pcm_t *pcm;
++ int err;
++
++ err = snd_ac97_pcm_assign(chip->ac97_bus,
++ ARRAY_SIZE(atmel_ac97_pcm_defs),
++ atmel_ac97_pcm_defs);
++ if (err)
++ return err;
++
++ err = snd_pcm_new(chip->card, "Atmel-AC97", 0, 1, 1, &pcm);
++ if (err)
++ return err;
++
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
++ &atmel_ac97_playback_ops);
++
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
++ &atmel_ac97_capture_ops);
++
++#ifdef SND_ATMEL_AC97_USE_ALSA_MALLOC_CALLS
++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
++ &chip->pdev->dev,
++ 128 * 1024, 128 * 1024);
++#endif
++
++ pcm->private_data = chip;
++ pcm->info_flags = 0;
++ strcpy(pcm->name, "Atmel-AC97");
++ chip->pcm = pcm;
++
++ return 0;
++}
++
++/* Mixer part */
++static int snd_atmel_ac97_mixer_new(atmel_ac97_t *chip)
++{
++ int err;
++ ac97_template_t template;
++
++ memset(&template, 0, sizeof(template));
++ template.private_data = chip;
++ err = snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
++
++ return err;
++}
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++static irqreturn_t snd_atmel_ac97_interrupt(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ atmel_ac97_t *chip = dev_id;
++ unsigned long status;
++
++ status = ac97c_readl(chip, SR);
++
++ if (status & AC97C_SR_CAEVT) {
++ snd_pcm_runtime_t *runtime;
++ int offset, next_period, block_size;
++ unsigned long casr;
++
++ /* FIXME: separate playback from capture */
++ runtime = chip->playback_substream->runtime;
++ block_size = frames_to_bytes(runtime, runtime->period_size);
++
++ casr = ac97c_readl(chip, CASR);
++
++ if (casr & AC97C_CSR_ENDTX) {
++ chip->period++;
++ if (chip->period == runtime->periods)
++ chip->period = 0;
++ next_period = chip->period + 1;
++ if (next_period == runtime->periods)
++ next_period = 0;
++
++ offset = block_size * next_period;
++
++ ac97c_writel(chip, CATNPR,
++ runtime->dma_addr + offset);
++ ac97c_writel(chip, CATNCR, block_size / 4);
++
++ snd_pcm_period_elapsed(chip->playback_substream);
++ }
++ else if (casr & AC97C_CSR_ENDRX) {
++ chip->period++;
++ if (chip->period == runtime->periods)
++ chip->period = 0;
++ next_period = chip->period + 1;
++ if (next_period == runtime->periods)
++ next_period = 0;
++
++ offset = block_size * next_period;
++
++ ac97c_writel(chip, CARNPR,
++ runtime->dma_addr + offset);
++ ac97c_writel(chip, CARNCR, block_size / 4);
++
++ snd_pcm_period_elapsed(chip->capture_substream);
++ } else {
++ snd_printk(KERN_INFO
++ "atmel-ac97: spurious interrupt, status = 0x%08lx\n",
++ (unsigned long)casr);
++ }
++ } else {
++ snd_printk(KERN_INFO
++ "atmel-ac97: spurious interrupt, status = 0x%08lx\n",
++ status);
++ }
++
++ (volatile int)ac97c_readl(chip, SR);
++
++ return IRQ_HANDLED;
++}
++
++#else
++
++static void atmel_ac97_error(struct dma_request *_req)
++{
++ struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
++
++ printk(KERN_WARNING
++ "DMA Controller error, channel %d (AC97C)\n",
++ req->req.channel);
++}
++
++static void atmel_ac97_block_complete(struct dma_request *_req)
++{
++ struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
++ atmel_ac97_t *chip = req->dev_id;
++ if (req->periph_id == chip->dma.tx_periph_id)
++ snd_pcm_period_elapsed(chip->playback_substream);
++ else
++ snd_pcm_period_elapsed(chip->capture_substream);
++}
++
++#endif
++
++/* CODEC part */
++
++static void snd_atmel_ac97_write(ac97_t *ac97, unsigned short reg,
++ unsigned short val)
++{
++ atmel_ac97_t *chip = ac97->private_data;
++ unsigned long word;
++ int timeout = 40;
++
++ word = (reg & 0x7f) << 16 | val;
++
++ do {
++ if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
++ ac97c_writel(chip, COTHR, word);
++ return;
++ }
++ udelay(1);
++ } while (--timeout);
++
++ snd_printk(KERN_WARNING "atmel-ac97: codec write timeout\n");
++}
++
++static unsigned short snd_atmel_ac97_read(ac97_t *ac97,
++ unsigned short reg)
++{
++ atmel_ac97_t *chip = ac97->private_data;
++ unsigned long word;
++ int timeout = 40;
++ int write = 10;
++
++ word = (0x80 | (reg & 0x7f)) << 16;
++
++ if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
++ ac97c_readl(chip, CORHR);
++
++retry_write:
++ timeout = 40;
++
++ do {
++ if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
++ ac97c_writel(chip, COTHR, word);
++ goto read_reg;
++ }
++ mdelay(10);
++ } while (--timeout);
++
++ if (!--write)
++ goto timed_out;
++ goto retry_write;
++
++read_reg:
++ do {
++ if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0){
++ unsigned short val = ac97c_readl(chip, CORHR);
++ return val;
++ }
++ mdelay(10);
++ } while (--timeout);
++
++ if (!--write)
++ goto timed_out;
++ goto retry_write;
++
++timed_out:
++ snd_printk(KERN_INFO "atmel-ac97: codec read timeout\n");
++ return 0xffff;
++}
++
++static void snd_atmel_ac97_reset(atmel_ac97_t *chip)
++{
++ /* TODO: Perform hard reset of codec as well */
++ ac97c_writel(chip, MR, AC97C_MR_WRST);
++ mdelay(1);
++ ac97c_writel(chip, MR, AC97C_MR_ENA);
++}
++
++static void snd_atmel_ac97_destroy(snd_card_t *card)
++{
++ atmel_ac97_t *chip = get_chip(card);
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ if (chip->irq != -1)
++ free_irq(chip->irq, chip);
++#endif
++ if (chip->regs)
++ iounmap(chip->regs);
++
++ if (chip->mck) {
++ clk_disable(chip->mck);
++ clk_put(chip->mck);
++ }
++
++#ifndef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ if (chip->dma.req_tx.req.dmac){
++ dma_release_channel(chip->dma.req_tx.req.dmac,
++ chip->dma.req_tx.req.channel);
++ }
++ if (chip->dma.req_rx.req.dmac) {
++ dma_release_channel(chip->dma.req_rx.req.dmac,
++ chip->dma.req_rx.req.channel);
++ }
++#endif
++}
++
++static int __devinit snd_atmel_ac97_create(snd_card_t *card,
++ struct platform_device *pdev)
++{
++ static ac97_bus_ops_t ops = {
++ .write = snd_atmel_ac97_write,
++ .read = snd_atmel_ac97_read,
++ };
++ atmel_ac97_t *chip = get_chip(card);
++ struct resource *regs;
++ struct clk *mck;
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ int irq;
++#endif
++ int err;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++#endif
++
++ mck = clk_get(&pdev->dev, "mck");
++ if (IS_ERR(mck))
++ return PTR_ERR(mck);
++ clk_enable(mck);
++ chip->mck = mck;
++
++ card->private_free = snd_atmel_ac97_destroy;
++
++ spin_lock_init(&chip->lock);
++ chip->card = card;
++ chip->pdev = pdev;
++ chip->irq = -1;
++
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ err = request_irq(irq, snd_atmel_ac97_interrupt, 0,
++ "ac97", chip);
++ if (err) {
++ snd_printk("unable to request IRQ%d\n", irq);
++ return err;
++ }
++ chip->irq = irq;
++#endif
++
++ chip->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!chip->regs)
++ return -ENOMEM;
++
++ snd_card_set_dev(card, &pdev->dev);
++
++ err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
++
++ return err;
++}
++
++static int __devinit snd_atmel_ac97_probe(struct platform_device *pdev)
++{
++ static int dev;
++ snd_card_t *card;
++ atmel_ac97_t *chip;
++ int err;
++ int ch;
++
++ if (dev >= SNDRV_CARDS)
++ return -ENODEV;
++ if (!enable[dev]) {
++ dev++;
++ return -ENOENT;
++ }
++
++ err = -ENOMEM;
++
++ mutex_init(&opened_mutex);
++
++ card = snd_card_new(index[dev], id[dev], THIS_MODULE,
++ sizeof(atmel_ac97_t));
++ if (!card)
++ goto out;
++ chip = get_chip(card);
++
++ err = snd_atmel_ac97_create(card, pdev);
++ if (err)
++ goto out_free_card;
++
++ snd_atmel_ac97_reset(chip);
++
++ err = snd_atmel_ac97_mixer_new(chip);
++ if (err)
++ goto out_free_card;
++
++ err = snd_atmel_ac97_pcm_new(chip);
++ if (err)
++ goto out_free_card;
++
++#ifndef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ /* TODO: Get this information from the platform device */
++ chip->dma.req_tx.req.dmac = find_dma_controller(0);
++ if (!chip->dma.req_tx.req.dmac) {
++ printk(KERN_ERR
++ "atmel-ac97c: No DMA controller for TX, aborting\n");
++ goto out_free_card;
++ }
++ chip->dma.req_rx.req.dmac = find_dma_controller(0);
++ if (!chip->dma.req_rx.req.dmac) {
++ snd_printk(KERN_ERR
++ "atmel-ac97c: No DMA controller available for RX, aborting\n");
++ goto out_free_card;
++ }
++
++ chip->dma.rx_periph_id = 3;
++ chip->dma.tx_periph_id = 4;
++
++ ch = dma_alloc_channel(chip->dma.req_tx.req.dmac);
++ if (ch < 0) {
++ printk(KERN_ERR
++ "atmel-ac97c: Unable to allocate TX DMA channel, aborting\n");
++ goto out_free_card;
++ }
++ chip->dma.req_tx.req.channel = ch;
++ chip->dma.req_tx.width = DMA_WIDTH_16BIT;
++ chip->dma.req_tx.req.block_complete = atmel_ac97_block_complete;
++ chip->dma.req_tx.req.error = atmel_ac97_error;
++
++ ch = dma_alloc_channel(chip->dma.req_rx.req.dmac);
++ if (ch < 0) {
++ snd_printk(KERN_ERR
++ "atmel-ac97c: Unable to allocate RX DMA channel, aborting\n");
++ goto out_free_card;
++ }
++ chip->dma.req_rx.req.channel = ch;
++ chip->dma.req_rx.width = DMA_WIDTH_16BIT;
++ chip->dma.req_rx.req.block_complete = atmel_ac97_block_complete;
++ chip->dma.req_rx.req.error = atmel_ac97_error;
++#endif
++
++ strcpy(card->driver, "ac97c");
++ strcpy(card->shortname, "Atmel-AC97");
++#ifdef CONFIG_SND_ATMEL_AC97C_USE_PDC
++ sprintf(card->longname, "Atmel AVR32 AC97 Controller at 0x%p, irq %i",
++ chip->regs, chip->irq);
++#else
++ sprintf(card->longname, "Atmel AVR32 AC97 Controller at 0x%p, dma rx %i and tx %i",
++ chip->regs, chip->dma.rx_periph_id, chip->dma.tx_periph_id);
++#endif
++
++ err = snd_card_register(card);
++ if (err)
++ goto out_free_card;
++
++ platform_set_drvdata(pdev, card);
++ dev++;
++ return 0;
++
++out_free_card:
++ snd_card_free(card);
++out:
++ return err;
++}
++
++static int __devexit snd_atmel_ac97_remove(struct platform_device *pdev)
++{
++ snd_card_t *card = platform_get_drvdata(pdev);
++
++ snd_card_free(card);
++ platform_set_drvdata(pdev, NULL);
++ return 0;
++}
++
++static struct platform_driver atmel_ac97_driver = {
++ .probe = snd_atmel_ac97_probe,
++ .remove = __devexit_p(snd_atmel_ac97_remove),
++ .driver = {
++ .name = "ac97c",
++ },
++};
++
++static int __init atmel_ac97_init(void)
++{
++ return platform_driver_register(&atmel_ac97_driver);
++}
++
++static void __exit atmel_ac97_exit(void)
++{
++ platform_driver_unregister(&atmel_ac97_driver);
++}
++
++module_init(atmel_ac97_init);
++module_exit(atmel_ac97_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Driver for Atmel AC97 Controller");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
+Index: linux-2.6.18-avr32/sound/avr32/ac97c.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/sound/avr32/ac97c.h 2006-11-02 15:56:20.000000000 +0100
+@@ -0,0 +1,71 @@
++/*
++ * Register definitions for the Atmel AC97 Controller.
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __SOUND_AVR32_AC97C_H
++#define __SOUND_AVR32_AC97C_H
++
++#define AC97C_MR 0x08
++#define AC97C_ICA 0x10
++#define AC97C_OCA 0x14
++#define AC97C_CARHR 0x20
++#define AC97C_CATHR 0x24
++#define AC97C_CASR 0x28
++#define AC97C_CAMR 0x2c
++#define AC97C_CBRHR 0x30
++#define AC97C_CBTHR 0x34
++#define AC97C_CBSR 0x38
++#define AC97C_CBMR 0x3c
++#define AC97C_CORHR 0x40
++#define AC97C_COTHR 0x44
++#define AC97C_COSR 0x48
++#define AC97C_COMR 0x4c
++#define AC97C_SR 0x50
++#define AC97C_IER 0x54
++#define AC97C_IDR 0x58
++#define AC97C_IMR 0x5c
++#define AC97C_VERSION 0xfc
++
++#define AC97C_CATPR PDC_TPR
++#define AC97C_CATCR PDC_TCR
++#define AC97C_CATNPR PDC_TNPR
++#define AC97C_CATNCR PDC_TNCR
++#define AC97C_CARPR PDC_RPR
++#define AC97C_CARCR PDC_RCR
++#define AC97C_CARNPR PDC_RNPR
++#define AC97C_CARNCR PDC_RNCR
++#define AC97C_PTCR PDC_PTCR
++
++#define AC97C_MR_ENA (1 << 0)
++#define AC97C_MR_WRST (1 << 1)
++#define AC97C_MR_VRA (1 << 2)
++
++#define AC97C_CSR_TXRDY (1 << 0)
++#define AC97C_CSR_UNRUN (1 << 2)
++#define AC97C_CSR_RXRDY (1 << 4)
++#define AC97C_CSR_ENDTX (1 << 10)
++#define AC97C_CSR_ENDRX (1 << 14)
++
++#define AC97C_CMR_SIZE_20 (0 << 16)
++#define AC97C_CMR_SIZE_18 (1 << 16)
++#define AC97C_CMR_SIZE_16 (2 << 16)
++#define AC97C_CMR_SIZE_10 (3 << 16)
++#define AC97C_CMR_CEM_LITTLE (1 << 18)
++#define AC97C_CMR_CEM_BIG (0 << 18)
++#define AC97C_CMR_CENA (1 << 21)
++#define AC97C_CMR_PDCEN (1 << 22)
++
++#define AC97C_SR_CAEVT (1 << 3)
++
++#define AC97C_CH_ASSIGN(slot, channel) \
++ (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3)))
++#define AC97C_CHANNEL_NONE 0x0
++#define AC97C_CHANNEL_A 0x1
++#define AC97C_CHANNEL_B 0x2
++
++#endif /* __SOUND_AVR32_AC97C_H */
diff --git a/packages/linux/linux-2.6.18/atmel-husb2-udc-driver.patch b/packages/linux/linux-2.6.18/atmel-husb2-udc-driver.patch
new file mode 100644
index 0000000000..f46a8f1dd8
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-husb2-udc-driver.patch
@@ -0,0 +1,2488 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: HÃ¥vard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Nov 18 18:13:25 2005 +0100
+Subject: [PATCH] Driver for the Atmel HUSB2 Device Controller
+
+This adds the driver for the Atmel HUSB2 Device Controller.
+
+---
+
+ drivers/usb/gadget/Kconfig | 10
+ drivers/usb/gadget/Makefile | 1
+ drivers/usb/gadget/gadget_chips.h | 8
+ drivers/usb/gadget/husb2_udc.c | 1998 ++++++++++++++++++++++++++++++++++++++
+ drivers/usb/gadget/husb2_udc.h | 406 +++++++
+ 5 files changed, 2423 insertions(+)
+
+Index: linux-2.6.18-avr32/drivers/usb/gadget/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/usb/gadget/Kconfig 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/drivers/usb/gadget/Kconfig 2006-11-02 15:56:20.000000000 +0100
+@@ -154,6 +154,16 @@ config USB_LH7A40X
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
++config USB_GADGET_HUSB2DEV
++ boolean "Atmel HUSB2DEVICE"
++ select USB_GADGET_DUALSPEED
++ depends on AVR32
++
++config USB_HUSB2DEV
++ tristate
++ depends on USB_GADGET_HUSB2DEV
++ default USB_GADGET
++ select USB_GADGET_SELECTED
+
+ config USB_GADGET_OMAP
+ boolean "OMAP USB Device Controller"
+Index: linux-2.6.18-avr32/drivers/usb/gadget/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/usb/gadget/Makefile 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/drivers/usb/gadget/Makefile 2006-11-02 15:56:20.000000000 +0100
+@@ -8,6 +8,7 @@ obj-$(CONFIG_USB_GOKU) += goku_udc.o
+ obj-$(CONFIG_USB_OMAP) += omap_udc.o
+ obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
+ obj-$(CONFIG_USB_AT91) += at91_udc.o
++obj-$(CONFIG_USB_HUSB2DEV) += husb2_udc.o
+
+ #
+ # USB gadget drivers
+Index: linux-2.6.18-avr32/drivers/usb/gadget/gadget_chips.h
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/usb/gadget/gadget_chips.h 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/drivers/usb/gadget/gadget_chips.h 2006-11-02 15:56:20.000000000 +0100
+@@ -75,6 +75,12 @@
+ #define gadget_is_pxa27x(g) 0
+ #endif
+
++#ifdef CONFIG_USB_GADGET_HUSB2DEV
++#define gadget_is_husb2dev(g) !strcmp("husb2_udc", (g)->name)
++#else
++#define gadget_is_husb2dev(g) 0
++#endif
++
+ #ifdef CONFIG_USB_GADGET_S3C2410
+ #define gadget_is_s3c2410(g) !strcmp("s3c2410_udc", (g)->name)
+ #else
+@@ -169,5 +175,7 @@ static inline int usb_gadget_controller_
+ return 0x16;
+ else if (gadget_is_mpc8272(gadget))
+ return 0x17;
++ else if (gadget_is_husb2dev(gadget))
++ return 0x80;
+ return -ENOENT;
+ }
+Index: linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.c 2006-11-02 16:06:40.000000000 +0100
+@@ -0,0 +1,1998 @@
++/*
++ * Driver for the Atmel HUSB2device high speed USB device controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#undef DEBUG
++
++#include <linux/config.h>
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++#include <linux/usb_ch9.h>
++#include <linux/usb_gadget.h>
++#include <linux/dmapool.h>
++#include <linux/delay.h>
++
++#include <asm/io.h>
++
++#include "husb2_udc.h"
++
++#define DRIVER_VERSION "0.9"
++
++#define DMA_ADDR_INVALID (~(dma_addr_t)0)
++
++#define FIFO_IOMEM_ID 0
++#define CTRL_IOMEM_ID 1
++
++#ifdef DEBUG
++#define DBG_ERR 0x0001 /* report all error returns */
++#define DBG_HW 0x0002 /* debug hardware initialization */
++#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
++#define DBG_INT 0x0008 /* interrupts */
++#define DBG_BUS 0x0010 /* report changes in bus state */
++#define DBG_QUEUE 0x0020 /* debug request queue processing */
++#define DBG_FIFO 0x0040 /* debug FIFO contents */
++#define DBG_DMA 0x0080 /* debug DMA handling */
++#define DBG_REQ 0x0100 /* print out queued request length */
++#define DBG_ALL 0xffff
++#define DBG_NONE 0x0000
++
++#define DEBUG_LEVEL (DBG_ERR|DBG_REQ)
++#define DBG(level, fmt, ...) \
++ do { \
++ if ((level) & DEBUG_LEVEL) \
++ printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__); \
++ } while (0)
++#else
++#define DBG(level, fmt...)
++#endif
++
++static struct husb2_udc the_udc;
++
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++#include <asm/uaccess.h>
++
++static int queue_dbg_open(struct inode *inode, struct file *file)
++{
++ struct husb2_ep *ep = inode->u.generic_ip;
++ struct husb2_request *req, *req_copy;
++ struct list_head *queue_data;
++
++ queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
++ if (!queue_data)
++ return -ENOMEM;
++ INIT_LIST_HEAD(queue_data);
++
++ spin_lock_irq(&ep->udc->lock);
++ list_for_each_entry(req, &ep->queue, queue) {
++ req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
++ if (!req_copy)
++ goto fail;
++ memcpy(req_copy, req, sizeof(*req_copy));
++ list_add_tail(&req_copy->queue, queue_data);
++ }
++ spin_unlock_irq(&ep->udc->lock);
++
++ file->private_data = queue_data;
++ return 0;
++
++fail:
++ spin_unlock_irq(&ep->udc->lock);
++ list_for_each_entry_safe(req, req_copy, queue_data, queue) {
++ list_del(&req->queue);
++ kfree(req);
++ }
++ kfree(queue_data);
++ return -ENOMEM;
++}
++
++/*
++ * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
++ *
++ * b: buffer address
++ * l: buffer length
++ * I/i: interrupt/no interrupt
++ * Z/z: zero/no zero
++ * S/s: short ok/short not ok
++ * s: status
++ * n: nr_packets
++ * F/f: submitted/not submitted to FIFO
++ * D/d: using/not using DMA
++ * L/l: last transaction/not last transaction
++ */
++static ssize_t queue_dbg_read(struct file *file, char __user *buf,
++ size_t nbytes, loff_t *ppos)
++{
++ struct list_head *queue = file->private_data;
++ struct husb2_request *req, *tmp_req;
++ size_t len, remaining, actual = 0;
++ char tmpbuf[38];
++
++ if (!access_ok(VERIFY_WRITE, buf, nbytes))
++ return -EFAULT;
++
++ mutex_lock(&file->f_dentry->d_inode->i_mutex);
++ list_for_each_entry_safe(req, tmp_req, queue, queue) {
++ len = snprintf(tmpbuf, sizeof(tmpbuf),
++ "%8p %08x %c%c%c %5d %4u %c%c%c\n",
++ req->req.buf, req->req.length,
++ req->req.no_interrupt ? 'i' : 'I',
++ req->req.zero ? 'Z' : 'z',
++ req->req.short_not_ok ? 's' : 'S',
++ req->req.status,
++ req->nr_pkts,
++ req->submitted ? 'F' : 'f',
++ req->using_dma ? 'D' : 'd',
++ req->last_transaction ? 'L' : 'l');
++ len = min(len, sizeof(tmpbuf));
++ if (len > nbytes)
++ break;
++
++ list_del(&req->queue);
++ kfree(req);
++
++ remaining = __copy_to_user(buf, tmpbuf, len);
++ actual += len - remaining;
++ if (remaining)
++ break;
++
++ nbytes -= len;
++ buf += len;
++ }
++ mutex_unlock(&file->f_dentry->d_inode->i_mutex);
++
++ return actual;
++}
++
++static int queue_dbg_release(struct inode *inode, struct file *file)
++{
++ struct list_head *queue_data = file->private_data;
++ struct husb2_request *req, *tmp_req;
++
++ list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
++ list_del(&req->queue);
++ kfree(req);
++ }
++ kfree(queue_data);
++ return 0;
++}
++
++static int regs_dbg_open(struct inode *inode, struct file *file)
++{
++ struct husb2_udc *udc;
++ unsigned int i;
++ u32 *data;
++ int ret = -ENOMEM;
++
++ mutex_lock(&inode->i_mutex);
++ udc = inode->u.generic_ip;
++ data = kmalloc(inode->i_size, GFP_KERNEL);
++ if (!data)
++ goto out;
++
++ spin_lock_irq(&udc->lock);
++ for (i = 0; i < inode->i_size / 4; i++)
++ data[i] = __raw_readl(udc->regs + i * 4);
++ spin_unlock_irq(&udc->lock);
++
++ file->private_data = data;
++ ret = 0;
++
++out:
++ mutex_unlock(&inode->i_mutex);
++
++ return ret;
++}
++
++static ssize_t regs_dbg_read(struct file *file, char __user *buf,
++ size_t nbytes, loff_t *ppos)
++{
++ struct inode *inode = file->f_dentry->d_inode;
++ int ret;
++
++ mutex_lock(&inode->i_mutex);
++ ret = simple_read_from_buffer(buf, nbytes, ppos,
++ file->private_data,
++ file->f_dentry->d_inode->i_size);
++ mutex_unlock(&inode->i_mutex);
++
++ return ret;
++}
++
++static int regs_dbg_release(struct inode *inode, struct file *file)
++{
++ kfree(file->private_data);
++ return 0;
++}
++
++const struct file_operations queue_dbg_fops = {
++ .owner = THIS_MODULE,
++ .open = queue_dbg_open,
++ .llseek = no_llseek,
++ .read = queue_dbg_read,
++ .release = queue_dbg_release,
++};
++
++const struct file_operations regs_dbg_fops = {
++ .owner = THIS_MODULE,
++ .open = regs_dbg_open,
++ .llseek = generic_file_llseek,
++ .read = regs_dbg_read,
++ .release = regs_dbg_release,
++};
++
++static void husb2_ep_init_debugfs(struct husb2_udc *udc,
++ struct husb2_ep *ep)
++{
++ struct dentry *ep_root;
++
++ ep_root = debugfs_create_dir(ep_name(ep), udc->debugfs_root);
++ if (!ep_root)
++ goto err_root;
++ ep->debugfs_dir = ep_root;
++
++ ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
++ ep, &queue_dbg_fops);
++ if (!ep->debugfs_queue)
++ goto err_queue;
++
++ if (ep_can_dma(ep)) {
++ ep->debugfs_dma_status
++ = debugfs_create_u32("dma_status", 0400, ep_root,
++ &ep->last_dma_status);
++ if (!ep->debugfs_dma_status)
++ goto err_dma_status;
++ }
++
++ return;
++
++err_dma_status:
++ debugfs_remove(ep->debugfs_queue);
++err_queue:
++ debugfs_remove(ep_root);
++err_root:
++ dev_err(&ep->udc->pdev->dev,
++ "failed to create debugfs directory for %s\n", ep_name(ep));
++}
++
++static void husb2_ep_cleanup_debugfs(struct husb2_ep *ep)
++{
++ debugfs_remove(ep->debugfs_queue);
++ debugfs_remove(ep->debugfs_dma_status);
++ debugfs_remove(ep->debugfs_dir);
++ ep->debugfs_dma_status = NULL;
++ ep->debugfs_dir = NULL;
++}
++
++static void husb2_init_debugfs(struct husb2_udc *udc)
++{
++ struct dentry *root, *regs;
++ struct resource *regs_resource;
++
++ root = debugfs_create_dir(udc->gadget.name, NULL);
++ if (IS_ERR(root) || !root)
++ goto err_root;
++ udc->debugfs_root = root;
++
++ regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
++ if (!regs)
++ goto err_regs;
++
++ regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
++ CTRL_IOMEM_ID);
++ regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
++ udc->debugfs_regs = regs;
++
++ husb2_ep_init_debugfs(udc, to_husb2_ep(udc->gadget.ep0));
++
++ return;
++
++err_regs:
++ debugfs_remove(root);
++err_root:
++ udc->debugfs_root = NULL;
++ dev_err(&udc->pdev->dev, "debugfs is not available\n");
++}
++
++static void husb2_cleanup_debugfs(struct husb2_udc *udc)
++{
++ husb2_ep_cleanup_debugfs(to_husb2_ep(udc->gadget.ep0));
++ debugfs_remove(udc->debugfs_regs);
++ debugfs_remove(udc->debugfs_root);
++ udc->debugfs_regs = NULL;
++ udc->debugfs_root = NULL;
++}
++#else
++static inline void husb2_ep_init_debugfs(struct husb2_udc *udc,
++ struct husb2_ep *ep)
++{
++
++}
++
++static inline void husb2_ep_cleanup_debugfs(struct husb2_ep *ep)
++{
++
++}
++
++static inline void husb2_init_debugfs(struct husb2_udc *udc)
++{
++
++}
++
++static inline void husb2_cleanup_debugfs(struct husb2_udc *udc)
++{
++
++}
++#endif
++
++static void copy_to_fifo(void __iomem *fifo, void *buf, int len)
++{
++ unsigned long tmp;
++
++ DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
++ for (; len > 0; len -= 4, buf += 4, fifo += 4) {
++ tmp = *(unsigned long *)buf;
++ if (len >= 4) {
++ DBG(DBG_FIFO, " -> %08lx\n", tmp);
++ __raw_writel(tmp, fifo);
++ } else {
++ do {
++ DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
++ __raw_writeb(tmp >> 24, fifo);
++ fifo++;
++ tmp <<= 8;
++ } while (--len);
++ break;
++ }
++ }
++}
++
++static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
++{
++ union {
++ unsigned long *w;
++ unsigned char *b;
++ } p;
++ unsigned long tmp;
++
++ DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
++ for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
++ if (len >= 4) {
++ tmp = __raw_readl(fifo);
++ *p.w = tmp;
++ DBG(DBG_FIFO, " -> %08lx\n", tmp);
++ } else {
++ do {
++ tmp = __raw_readb(fifo);
++ *p.b = tmp;
++ DBG(DBG_FIFO, " -> %02lx\n", tmp);
++ fifo++, p.b++;
++ } while (--len);
++ }
++ }
++}
++
++static void next_fifo_transaction(struct husb2_ep *ep,
++ struct husb2_request *req)
++{
++ unsigned int transaction_len;
++
++ transaction_len = req->req.length - req->req.actual;
++ req->last_transaction = 1;
++ if (transaction_len > ep->ep.maxpacket) {
++ transaction_len = ep->ep.maxpacket;
++ req->last_transaction = 0;
++ } else if (transaction_len == ep->ep.maxpacket
++ && req->req.zero) {
++ req->last_transaction = 0;
++ }
++ DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
++ ep_name(ep), req, transaction_len,
++ req->last_transaction ? ", done" : "");
++
++ copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
++ husb2_ep_writel(ep, SET_STA, HUSB2_BIT(TX_PK_RDY));
++ req->req.actual += transaction_len;
++}
++
++static void submit_request(struct husb2_ep *ep, struct husb2_request *req)
++{
++ DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
++ ep_name(ep), req, req->req.length);
++
++ req->req.actual = 0;
++ req->submitted = 1;
++
++ if (req->using_dma) {
++ if (req->req.length == 0) {
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
++ } else {
++ husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(TX_PK_RDY));
++ husb2_dma_writel(ep, NXT_DSC,
++ req->packet[0].desc_dma);
++ husb2_dma_writel(ep, CONTROL, HUSB2_BIT(DMA_LINK));
++ }
++ } else {
++ next_fifo_transaction(ep, req);
++ if (req->last_transaction)
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_COMPLETE));
++ else
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
++ }
++}
++
++static void submit_next_request(struct husb2_ep *ep)
++{
++ struct husb2_request *req;
++
++ if (list_empty(&ep->queue)) {
++ husb2_ep_writel(ep, CTL_DIS, (HUSB2_BIT(TX_PK_RDY)
++ | HUSB2_BIT(RX_BK_RDY)));
++ return;
++ }
++
++ req = list_entry(ep->queue.next, struct husb2_request, queue);
++ if (!req->submitted)
++ submit_request(ep, req);
++}
++
++static void send_status(struct husb2_udc *udc, struct husb2_ep *ep)
++{
++ ep->state = STATUS_STAGE_IN;
++ husb2_ep_writel(ep, SET_STA, HUSB2_BIT(TX_PK_RDY));
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_COMPLETE));
++}
++
++static void receive_data(struct husb2_ep *ep)
++{
++ struct husb2_udc *udc = ep->udc;
++ struct husb2_request *req;
++ unsigned long status;
++ unsigned int bytecount, nr_busy;
++ int is_complete = 0;
++
++ status = husb2_ep_readl(ep, STA);
++ nr_busy = HUSB2_BFEXT(BUSY_BANKS, status);
++
++ DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
++
++ while (nr_busy > 0) {
++ if (list_empty(&ep->queue)) {
++ husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(RX_BK_RDY));
++ break;
++ }
++ req = list_entry(ep->queue.next,
++ struct husb2_request, queue);
++
++ bytecount = HUSB2_BFEXT(BYTE_COUNT, status);
++
++ if (status & (1 << 31))
++ is_complete = 1;
++ if (req->req.actual + bytecount >= req->req.length) {
++ is_complete = 1;
++ bytecount = req->req.length - req->req.actual;
++ }
++
++ copy_from_fifo(req->req.buf + req->req.actual,
++ ep->fifo, bytecount);
++ req->req.actual += bytecount;
++
++ husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
++
++ if (is_complete) {
++ DBG(DBG_QUEUE, "%s: request done\n", ep_name(ep));
++ req->req.status = 0;
++ list_del_init(&req->queue);
++ req->req.complete(&ep->ep, &req->req);
++ }
++
++ status = husb2_ep_readl(ep, STA);
++ nr_busy = HUSB2_BFEXT(BUSY_BANKS, status);
++
++ if (is_complete && ep_is_control(ep)) {
++ BUG_ON(nr_busy != 0);
++ send_status(udc, ep);
++ break;
++ }
++ }
++}
++
++static void request_complete(struct husb2_ep *ep,
++ struct husb2_request *req,
++ int status)
++{
++ struct husb2_udc *udc = ep->udc;
++ int i;
++
++ BUG_ON(!list_empty(&req->queue));
++
++ if (req->req.status == -EINPROGRESS)
++ req->req.status = status;
++
++ if (req->packet) {
++ for (i = 0; i < req->nr_pkts; i++)
++ dma_pool_free(udc->desc_pool, req->packet[i].desc,
++ req->packet[i].desc_dma);
++ kfree(req->packet);
++ req->packet = NULL;
++ dma_unmap_single(&udc->pdev->dev,
++ req->req.dma, req->req.length,
++ (ep_is_in(ep)
++ ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
++ req->req.dma = DMA_ADDR_INVALID;
++ }
++
++ DBG(DBG_GADGET | DBG_REQ,
++ "%s: req %p complete: status %d, actual %u\n",
++ ep_name(ep), req, req->req.status, req->req.actual);
++ req->req.complete(&ep->ep, &req->req);
++}
++
++static void request_complete_list(struct husb2_ep *ep,
++ struct list_head *list,
++ int status)
++{
++ struct husb2_request *req, *tmp_req;
++
++ list_for_each_entry_safe(req, tmp_req, list, queue) {
++ list_del_init(&req->queue);
++ request_complete(ep, req, status);
++ }
++}
++
++static int husb2_ep_enable(struct usb_ep *_ep,
++ const struct usb_endpoint_descriptor *desc)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ struct husb2_udc *udc = ep->udc;
++ unsigned long flags, ept_cfg, maxpacket;
++
++ DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep_name(ep), desc);
++
++ maxpacket = le16_to_cpu(desc->wMaxPacketSize);
++
++ if (ep->index == 0
++ || desc->bDescriptorType != USB_DT_ENDPOINT
++ || ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
++ != ep->index)
++ || maxpacket == 0
++ || maxpacket > ep->fifo_size) {
++ DBG(DBG_ERR, "ep_enable: Invalid argument");
++ return -EINVAL;
++ }
++
++ if (((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
++ == USB_ENDPOINT_XFER_ISOC)
++ && !(ep->capabilities & HUSB2_EP_CAP_ISOC)) {
++ DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
++ ep_name(ep));
++ return -EINVAL;
++ }
++
++ if (maxpacket <= 8)
++ ept_cfg = HUSB2_BF(EPT_SIZE, HUSB2_EPT_SIZE_8);
++ else
++ /* LSB is bit 1, not 0 */
++ ept_cfg = HUSB2_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
++ DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
++ ep_name(ep), ept_cfg, maxpacket);
++
++ if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
++ ept_cfg |= HUSB2_BIT(EPT_DIR);
++
++ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
++ case USB_ENDPOINT_XFER_CONTROL:
++ ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_CONTROL);
++ break;
++ case USB_ENDPOINT_XFER_ISOC:
++ ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_ISO);
++ break;
++ case USB_ENDPOINT_XFER_BULK:
++ ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_BULK);
++ break;
++ case USB_ENDPOINT_XFER_INT:
++ ept_cfg |= HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_INT);
++ break;
++ }
++ ept_cfg |= HUSB2_BF(BK_NUMBER, ep->nr_banks);
++
++ spin_lock_irqsave(&ep->udc->lock, flags);
++
++ if (ep->desc) {
++ spin_unlock_irqrestore(&ep->udc->lock, flags);
++ DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
++ return -EBUSY;
++ }
++
++ ep->desc = desc;
++ ep->ep.maxpacket = maxpacket;
++
++ husb2_ep_writel(ep, CFG, ept_cfg);
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(EPT_ENABLE));
++
++ if (ep_can_dma(ep)) {
++ husb2_writel(udc, INT_ENB,
++ (husb2_readl(udc, INT_ENB)
++ | HUSB2_BF(EPT_INT, 1 << ep->index)
++ | HUSB2_BF(DMA_INT, 1 << ep->index)));
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(AUTO_VALID));
++ } else {
++ husb2_writel(udc, INT_ENB,
++ (husb2_readl(udc, INT_ENB)
++ | HUSB2_BF(EPT_INT, 1 << ep->index)));
++ }
++
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
++ (unsigned long)husb2_ep_readl(ep, CFG));
++ DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
++ (unsigned long)husb2_readl(udc, INT_ENB));
++
++ husb2_ep_init_debugfs(udc, ep);
++
++ return 0;
++}
++
++static int husb2_ep_disable(struct usb_ep *_ep)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ struct husb2_udc *udc = ep->udc;
++ LIST_HEAD(req_list);
++ unsigned long flags;
++
++ DBG(DBG_GADGET, "ep_disable: %s\n", ep_name(ep));
++
++ husb2_ep_cleanup_debugfs(ep);
++
++ spin_lock_irqsave(&udc->lock, flags);
++
++ if (!ep->desc) {
++ spin_unlock_irqrestore(&udc->lock, flags);
++ DBG(DBG_ERR, "ep_disable: %s not enabled\n",
++ ep_name(ep));
++ return -EINVAL;
++ }
++ ep->desc = NULL;
++
++ list_splice_init(&ep->queue, &req_list);
++ if (ep_can_dma(ep)) {
++ husb2_dma_writel(ep, CONTROL, 0);
++ husb2_dma_writel(ep, ADDRESS, 0);
++ husb2_dma_readl(ep, STATUS);
++ }
++ husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(EPT_ENABLE));
++ husb2_writel(udc, INT_ENB, (husb2_readl(udc, INT_ENB)
++ & ~HUSB2_BF(EPT_INT, 1 << ep->index)));
++
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ request_complete_list(ep, &req_list, -ESHUTDOWN);
++
++ return 0;
++}
++
++static struct usb_request *
++husb2_ep_alloc_request(struct usb_ep *_ep, unsigned gfp_flags)
++{
++ struct husb2_request *req;
++
++ DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
++
++ req = kzalloc(sizeof(*req), gfp_flags);
++ if (!req)
++ return NULL;
++
++ INIT_LIST_HEAD(&req->queue);
++ req->req.dma = DMA_ADDR_INVALID;
++
++ return &req->req;
++}
++
++static void
++husb2_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
++{
++ struct husb2_request *req = to_husb2_req(_req);
++
++ DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
++
++ kfree(req);
++}
++
++static void *husb2_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
++ dma_addr_t *dma, unsigned gfp_flags)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ void *buf;
++
++ /*
++ * We depend on kmalloc() returning cache-aligned memory. This
++ * is normally guaranteed as long as we allocate a whole
++ * cacheline or more.
++ *
++ * When CONFIG_DEBUG_SLAB is enabled, however, the slab
++ * allocator inserts red zones and ownership information,
++ * causing the slab objects to be misaligned.
++ *
++ * One alternative would be to use dma_alloc_coherent, but
++ * that would make us unable to allocate anything less than a
++ * page at a time.
++ */
++#ifdef CONFIG_DEBUG_SLAB
++# error The HUSB2 UDC driver breaks with SLAB debugging enabled
++#endif
++
++ if (bytes < L1_CACHE_BYTES)
++ bytes = L1_CACHE_BYTES;
++
++ buf = kmalloc(bytes, gfp_flags);
++
++ /*
++ * Seems like we have to map the buffer any chance we get.
++ * ether.c wants us to initialize the dma member of a
++ * different request than the one receiving the buffer, so one
++ * never knows...
++ *
++ * Ah, screw it. The ether driver is probably wrong, and this
++ * is not the right place to do the mapping. The driver
++ * shouldn't mess with our DMA mappings anyway.
++ */
++ *dma = DMA_ADDR_INVALID;
++
++ DBG(DBG_GADGET, "ep_alloc_buffer: %s, %u, 0x%x -> %p\n",
++ ep_name(ep), bytes, gfp_flags, buf);
++
++ return buf;
++}
++
++static void husb2_ep_free_buffer(struct usb_ep *_ep, void *buf,
++ dma_addr_t dma, unsigned bytes)
++{
++ DBG(DBG_GADGET, "ep_free_buffer: %s, buf %p (size %u)\n",
++ _ep->name, buf, bytes);
++ kfree(buf);
++}
++
++static int queue_dma(struct husb2_udc *udc, struct husb2_ep *ep,
++ struct husb2_request *req, unsigned int direction,
++ gfp_t gfp_flags)
++{
++ struct husb2_packet *pkt, *prev_pkt;
++ unsigned int pkt_size, nr_pkts, i;
++ unsigned int residue;
++ dma_addr_t addr;
++ unsigned long flags;
++ u32 ctrl;
++
++ req->using_dma = 1;
++
++ if (req->req.length == 0) {
++ if (!req->req.zero)
++ return -EINVAL;
++ req->send_zlp = 1;
++
++ spin_lock_irqsave(&udc->lock, flags);
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
++ list_add_tail(&req->queue, &ep->queue);
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ return 0;
++ }
++
++ if (req->req.dma == DMA_ADDR_INVALID)
++ req->req.dma = dma_map_single(&udc->pdev->dev,
++ req->req.buf,
++ req->req.length,
++ direction);
++ else
++ dma_sync_single_for_device(&udc->pdev->dev,
++ req->req.dma,
++ req->req.length,
++ direction);
++
++ pkt_size = ep->ep.maxpacket;
++ nr_pkts = req->req.length / pkt_size;
++ residue = req->req.length % pkt_size;
++ if (residue != 0)
++ nr_pkts++;
++ else if (req->req.zero && ep_is_in(ep))
++ /* ensure last packet is short */
++ req->send_zlp = 1;
++
++ req->nr_pkts = nr_pkts;
++
++ req->packet = kzalloc(sizeof(*req->packet) * nr_pkts, gfp_flags);
++ if (!req->packet)
++ goto out_of_memory;
++
++ addr = req->req.dma;
++ ctrl = (HUSB2_BF(DMA_BUF_LEN, pkt_size)
++ | HUSB2_BIT(DMA_CH_EN) | HUSB2_BIT(DMA_LINK)
++ | HUSB2_BIT(DMA_END_TR_EN) | HUSB2_BIT(DMA_END_TR_IE));
++ prev_pkt = NULL;
++ pkt = NULL;
++ DBG(DBG_DMA, "DMA descriptors:\n");
++ for (i = 0; i < nr_pkts; i++) {
++ pkt = &req->packet[i];
++ pkt->desc = dma_pool_alloc(udc->desc_pool, gfp_flags,
++ &pkt->desc_dma);
++ if (!pkt->desc)
++ goto out_of_memory;
++
++ if (prev_pkt) {
++ prev_pkt->desc->next = pkt->desc_dma;
++ DBG(DBG_DMA, "[%d] n%08x a%08x c%08x\n",
++ i - 1, prev_pkt->desc->next, prev_pkt->desc->addr,
++ prev_pkt->desc->ctrl);
++ }
++ prev_pkt = pkt;
++
++ pkt->desc->addr = addr;
++ pkt->desc->ctrl = ctrl;
++ addr += pkt_size;
++ }
++
++ /* special care is needed for the last packet... */
++ ctrl = (HUSB2_BIT(DMA_CH_EN)
++ | HUSB2_BIT(DMA_END_TR_EN) | HUSB2_BIT(DMA_END_TR_IE)
++ | HUSB2_BIT(DMA_END_BUF_IE));
++ if (ep_is_in(ep))
++ ctrl |= HUSB2_BIT(DMA_END_BUF_EN);
++ if (req->req.zero || residue)
++ ctrl |= HUSB2_BF(DMA_BUF_LEN, residue);
++ else
++ ctrl |= HUSB2_BF(DMA_BUF_LEN, pkt_size);
++ pkt->desc->ctrl = ctrl;
++
++ DBG(DBG_DMA, "[%d] n%08x a%08x c%08x\n",
++ i - 1, prev_pkt->desc->next, prev_pkt->desc->addr,
++ prev_pkt->desc->ctrl);
++
++ /* Add this request to the queue and try to chain the DMA descriptors */
++ spin_lock_irqsave(&udc->lock, flags);
++
++ /* If the DMA controller is idle, start it */
++ if (list_empty(&ep->queue)) {
++ husb2_dma_writel(ep, NXT_DSC, req->packet[0].desc_dma);
++ husb2_dma_writel(ep, CONTROL, HUSB2_BIT(DMA_LINK));
++ }
++
++ list_add_tail(&req->queue, &ep->queue);
++
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ return 0;
++
++out_of_memory:
++ printk(KERN_ERR "ERROR: Could not allocate DMA memory for endpoint %s\n",
++ ep_name(ep));
++ if (req->packet) {
++ for (i = 0; i < nr_pkts; i++)
++ if (req->packet[i].desc)
++ dma_pool_free(udc->desc_pool,
++ req->packet[i].desc,
++ req->packet[i].desc_dma);
++ kfree(req->packet);
++ }
++
++ return -ENOMEM;
++}
++
++static int husb2_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
++ gfp_t gfp_flags)
++{
++ struct husb2_request *req = to_husb2_req(_req);
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ struct husb2_udc *udc = ep->udc;
++ unsigned long flags;
++ int direction_in = 0;
++
++ DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ,
++ "%s: queue req %p, len %u\n", ep_name(ep), req, _req->length);
++
++ if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
++ return -ESHUTDOWN;
++ if (!ep->desc)
++ return -ENODEV;
++
++ req->nr_pkts = 0;
++ req->submitted = 0;
++ req->using_dma = 0;
++ req->last_transaction = 0;
++ req->send_zlp = 0;
++
++ BUG_ON(req->packet);
++
++ if (ep_is_in(ep)
++ || (ep_is_control(ep) && (ep->state == DATA_STAGE_IN
++ || ep->state == STATUS_STAGE_IN)))
++ direction_in = 1;
++
++ _req->status = -EINPROGRESS;
++ _req->actual = 0;
++
++ if (ep_can_dma(ep)) {
++ return queue_dma(udc, ep, req, (direction_in
++ ? DMA_TO_DEVICE
++ : DMA_FROM_DEVICE),
++ gfp_flags);
++ } else {
++ spin_lock_irqsave(&udc->lock, flags);
++ list_add_tail(&req->queue, &ep->queue);
++
++ if (direction_in)
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
++ else
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(RX_BK_RDY));
++ spin_unlock_irqrestore(&udc->lock, flags);
++ }
++
++ return 0;
++}
++
++static void husb2_update_req(struct husb2_ep *ep, struct husb2_request *req,
++ u32 status)
++{
++ struct husb2_dma_desc *desc;
++ dma_addr_t from;
++ dma_addr_t addr;
++ size_t size;
++ unsigned int i;
++
++ addr = husb2_dma_readl(ep, ADDRESS);
++ req->req.actual = 0;
++
++ for (i = 0; i < req->nr_pkts; i++) {
++ desc = req->packet[i].desc;
++ from = desc->addr;
++ size = HUSB2_BFEXT(DMA_BUF_LEN, desc->ctrl);
++
++ req->req.actual += size;
++
++ DBG(DBG_DMA, " from=%#08x, size=%#zx\n", from, size);
++
++ if (from <= addr && (from + size) >= addr)
++ break;
++ }
++
++ req->req.actual -= HUSB2_BFEXT(DMA_BUF_LEN, status);
++}
++
++static int stop_dma(struct husb2_ep *ep, u32 *pstatus)
++{
++ unsigned int timeout;
++ u32 status;
++
++ /*
++ * Stop the DMA controller. When writing both CH_EN
++ * and LINK to 0, the other bits are not affected.
++ */
++ husb2_dma_writel(ep, CONTROL, 0);
++
++ /* Wait for the FIFO to empty */
++ for (timeout = 40; timeout; --timeout) {
++ status = husb2_dma_readl(ep, STATUS);
++ if (!(status & HUSB2_BIT(DMA_CH_EN)))
++ break;
++ udelay(1);
++ }
++
++ if (pstatus)
++ *pstatus = status;
++
++ if (timeout == 0) {
++ dev_err(&ep->udc->pdev->dev,
++ "%s: timed out waiting for DMA FIFO to empty\n",
++ ep_name(ep));
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++static int husb2_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ struct husb2_udc *udc = ep->udc;
++ struct husb2_request *req = to_husb2_req(_req);
++ unsigned long flags;
++ u32 status;
++
++ DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n", ep_name(ep), req);
++
++ spin_lock_irqsave(&udc->lock, flags);
++
++ if (req->using_dma) {
++ /*
++ * If this request is currently being transferred,
++ * stop the DMA controller and reset the FIFO.
++ */
++ if (ep->queue.next == &req->queue) {
++ status = husb2_dma_readl(ep, STATUS);
++ if (status & HUSB2_BIT(DMA_CH_EN))
++ stop_dma(ep, &status);
++
++#ifdef CONFIG_DEBUG_FS
++ ep->last_dma_status = status;
++#endif
++
++ husb2_writel(udc, EPT_RST,
++ 1 << ep_index(ep));
++
++ husb2_update_req(ep, req, status);
++ }
++ }
++
++ /*
++ * Errors should stop the queue from advancing until the
++ * completion function returns.
++ */
++ list_del_init(&req->queue);
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ request_complete(ep, req, -ECONNRESET);
++
++ /* Process the next request if any */
++ spin_lock_irqsave(&udc->lock, flags);
++ submit_next_request(ep);
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ return 0;
++}
++
++static int husb2_ep_set_halt(struct usb_ep *_ep, int value)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ struct husb2_udc *udc = ep->udc;
++ unsigned long flags;
++ int ret = 0;
++
++ DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep_name(ep),
++ value ? "set" : "clear");
++
++ if (!ep->desc) {
++ DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
++ ep_name(ep));
++ return -ENODEV;
++ }
++ if (ep_is_isochronous(ep)) {
++ DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
++ ep_name(ep));
++ return -ENOTTY;
++ }
++
++ spin_lock_irqsave(&udc->lock, flags);
++
++ /*
++ * We can't halt IN endpoints while there are still data to be
++ * transferred
++ */
++ if (!list_empty(&ep->queue)
++ || ((value && ep_is_in(ep)
++ && (husb2_ep_readl(ep, STA)
++ & HUSB2_BF(BUSY_BANKS, -1L))))) {
++ ret = -EAGAIN;
++ } else {
++ if (value)
++ husb2_ep_writel(ep, SET_STA, HUSB2_BIT(FORCE_STALL));
++ else
++ husb2_ep_writel(ep, CLR_STA, (HUSB2_BIT(FORCE_STALL)
++ | HUSB2_BIT(TOGGLE_SEQ)));
++ husb2_ep_readl(ep, STA);
++ }
++
++ spin_unlock_irqrestore(&udc->lock, flags);
++
++ return ret;
++}
++
++static int husb2_ep_fifo_status(struct usb_ep *_ep)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++
++ return HUSB2_BFEXT(BYTE_COUNT, husb2_ep_readl(ep, STA));
++}
++
++static void husb2_ep_fifo_flush(struct usb_ep *_ep)
++{
++ struct husb2_ep *ep = to_husb2_ep(_ep);
++ struct husb2_udc *udc = ep->udc;
++
++ husb2_writel(udc, EPT_RST, 1 << ep->index);
++}
++
++struct usb_ep_ops husb2_ep_ops = {
++ .enable = husb2_ep_enable,
++ .disable = husb2_ep_disable,
++ .alloc_request = husb2_ep_alloc_request,
++ .free_request = husb2_ep_free_request,
++ .alloc_buffer = husb2_ep_alloc_buffer,
++ .free_buffer = husb2_ep_free_buffer,
++ .queue = husb2_ep_queue,
++ .dequeue = husb2_ep_dequeue,
++ .set_halt = husb2_ep_set_halt,
++ .fifo_status = husb2_ep_fifo_status,
++ .fifo_flush = husb2_ep_fifo_flush,
++};
++
++static int husb2_udc_get_frame(struct usb_gadget *gadget)
++{
++ struct husb2_udc *udc = to_husb2_udc(gadget);
++
++ return HUSB2_BFEXT(FRAME_NUMBER, husb2_readl(udc, FNUM));
++}
++
++struct usb_gadget_ops husb2_udc_ops = {
++ .get_frame = husb2_udc_get_frame,
++};
++
++#define EP(nam, type, idx, caps) { \
++ .ep = { \
++ .ops = &husb2_ep_ops, \
++ .name = nam, \
++ .maxpacket = type##_FIFO_SIZE, \
++ }, \
++ .udc = &the_udc, \
++ .queue = LIST_HEAD_INIT(husb2_ep[idx].queue), \
++ .fifo_size = type##_FIFO_SIZE, \
++ .nr_banks = type##_NR_BANKS, \
++ .index = idx, \
++ .capabilities = caps, \
++}
++
++static struct husb2_ep husb2_ep[] = {
++ EP("ep0", EP0, 0, 0),
++ EP("ep1in-bulk", BULK, 1, HUSB2_EP_CAP_DMA),
++ EP("ep2out-bulk", BULK, 2, HUSB2_EP_CAP_DMA),
++ EP("ep3in-iso", ISO, 3, HUSB2_EP_CAP_DMA | HUSB2_EP_CAP_ISOC),
++ EP("ep4out-iso", ISO, 4, HUSB2_EP_CAP_DMA | HUSB2_EP_CAP_ISOC),
++ EP("ep5in-int", INT, 5, HUSB2_EP_CAP_DMA),
++ EP("ep6out-int", INT, 6, HUSB2_EP_CAP_DMA),
++};
++#undef EP
++
++static struct usb_endpoint_descriptor husb2_ep0_desc = {
++ .bLength = USB_DT_ENDPOINT_SIZE,
++ .bDescriptorType = USB_DT_ENDPOINT,
++ .bEndpointAddress = 0,
++ .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
++ .wMaxPacketSize = __constant_cpu_to_le16(64),
++ /* FIXME: I have no idea what to put here */
++ .bInterval = 1,
++};
++
++static void nop_release(struct device *dev)
++{
++
++}
++
++static struct husb2_udc the_udc = {
++ .gadget = {
++ .ops = &husb2_udc_ops,
++ .ep0 = &husb2_ep[0].ep,
++ .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
++ .is_dualspeed = 1,
++ .name = "husb2_udc",
++ .dev = {
++ .bus_id = "gadget",
++ .release = nop_release,
++ },
++ },
++
++ .lock = SPIN_LOCK_UNLOCKED,
++};
++
++static void udc_enable(struct husb2_udc *udc)
++{
++ struct husb2_ep *ep0 = &husb2_ep[0];
++
++ /* Enable the controller */
++ husb2_writel(udc, CTRL, HUSB2_BIT(EN_HUSB2));
++
++ /* Reset all endpoints and enable basic interrupts */
++ husb2_writel(udc, EPT_RST, ~0UL);
++ husb2_writel(udc, INT_ENB, (HUSB2_BIT(DET_SUSPEND)
++ | HUSB2_BIT(END_OF_RESET)
++ | HUSB2_BIT(END_OF_RESUME)));
++
++ /* Configure endpoint 0 */
++ ep0->desc = &husb2_ep0_desc;
++
++ husb2_writel(udc, EPT_RST, 1 << 0);
++ husb2_ep_writel(ep0, CTL_ENB, HUSB2_BIT(EPT_ENABLE));
++ husb2_ep_writel(ep0, CFG, (HUSB2_BF(EPT_SIZE, EP0_EPT_SIZE)
++ | HUSB2_BF(EPT_TYPE, HUSB2_EPT_TYPE_CONTROL)
++ | HUSB2_BF(BK_NUMBER, HUSB2_BK_NUMBER_ONE)));
++
++ husb2_ep_writel(ep0, CTL_ENB, HUSB2_BIT(RX_SETUP));
++ husb2_writel(udc, INT_ENB, (husb2_readl(udc, INT_ENB)
++ | HUSB2_BF(EPT_INT, 1)));
++
++ if (!(husb2_ep_readl(ep0, CFG) & HUSB2_BIT(EPT_MAPPED)))
++ dev_warn(&udc->pdev->dev,
++ "WARNING: EP0 configuration is invalid!\n");
++}
++
++static void udc_disable(struct husb2_udc *udc)
++{
++ udc->gadget.speed = USB_SPEED_UNKNOWN;
++
++ husb2_writel(udc, CTRL, 0);
++}
++
++/*
++ * Called with interrupts disabled and udc->lock held.
++ */
++static void reset_all_endpoints(struct husb2_udc *udc)
++{
++ struct husb2_ep *ep;
++ struct husb2_request *req, *tmp_req;
++
++ husb2_writel(udc, EPT_RST, ~0UL);
++
++ ep = to_husb2_ep(udc->gadget.ep0);
++ list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
++ list_del_init(&req->queue);
++ request_complete(ep, req, -ECONNRESET);
++ }
++ BUG_ON(!list_empty(&ep->queue));
++
++ list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
++ if (ep->desc)
++ husb2_ep_disable(&ep->ep);
++ }
++}
++
++static struct husb2_ep *get_ep_by_addr(struct husb2_udc *udc, u16 wIndex)
++{
++ struct husb2_ep *ep;
++
++ if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
++ return to_husb2_ep(udc->gadget.ep0);
++
++ list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
++ u8 bEndpointAddress;
++
++ if (!ep->desc)
++ continue;
++ bEndpointAddress = ep->desc->bEndpointAddress;
++ if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
++ continue;
++ if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
++ == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
++ return ep;
++ }
++
++ return NULL;
++}
++
++/* Called with interrupts disabled and udc->lock held */
++static inline void set_protocol_stall(struct husb2_udc *udc,
++ struct husb2_ep *ep)
++{
++ husb2_ep_writel(ep, SET_STA, HUSB2_BIT(FORCE_STALL));
++ ep->state = WAIT_FOR_SETUP;
++}
++
++static inline int is_stalled(struct husb2_udc *udc, struct husb2_ep *ep)
++{
++ if (husb2_ep_readl(ep, STA) & HUSB2_BIT(FORCE_STALL))
++ return 1;
++ return 0;
++}
++
++static inline void set_address(struct husb2_udc *udc, unsigned int addr)
++{
++ u32 regval;
++
++ DBG(DBG_BUS, "setting address %u...\n", addr);
++ regval = husb2_readl(udc, CTRL);
++ regval = HUSB2_BFINS(DEV_ADDR, addr, regval);
++ husb2_writel(udc, CTRL, regval);
++}
++
++static int handle_ep0_setup(struct husb2_udc *udc, struct husb2_ep *ep,
++ struct usb_ctrlrequest *crq)
++{
++ switch (crq->bRequest) {
++ case USB_REQ_GET_STATUS: {
++ u16 status;
++
++ if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
++ /* Self-powered, no remote wakeup */
++ status = __constant_cpu_to_le16(1 << 0);
++ } else if (crq->bRequestType
++ == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
++ status = __constant_cpu_to_le16(0);
++ } else if (crq->bRequestType
++ == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
++ struct husb2_ep *target;
++
++ target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
++ if (!target)
++ goto stall;
++
++ status = 0;
++ if (is_stalled(udc, target))
++ status |= __constant_cpu_to_le16(1);
++ } else {
++ goto delegate;
++ }
++
++ /* Write directly to the FIFO. No queueing is done. */
++ if(crq->wLength != __constant_cpu_to_le16(sizeof(status)))
++ goto stall;
++ ep->state = DATA_STAGE_IN;
++ __raw_writew(status, ep->fifo);
++ husb2_ep_writel(ep, SET_STA, HUSB2_BIT(TX_PK_RDY));
++ break;
++ }
++
++ case USB_REQ_CLEAR_FEATURE: {
++ if (crq->bRequestType == USB_RECIP_DEVICE) {
++ /* We don't support TEST_MODE */
++ goto stall;
++ } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
++ struct husb2_ep *target;
++
++ if (crq->wValue != __constant_cpu_to_le16(USB_ENDPOINT_HALT)
++ || crq->wLength != __constant_cpu_to_le16(0))
++ goto stall;
++ target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
++ if (!target)
++ goto stall;
++
++ husb2_ep_writel(target, CLR_STA, (HUSB2_BIT(FORCE_STALL)
++ | HUSB2_BIT(TOGGLE_SEQ)));
++ } else {
++ goto delegate;
++ }
++
++ send_status(udc, ep);
++ break;
++ }
++
++ case USB_REQ_SET_FEATURE: {
++ if (crq->bRequestType == USB_RECIP_DEVICE) {
++ /* We don't support TEST_MODE */
++ goto stall;
++ } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
++ struct husb2_ep *target;
++
++ if (crq->wValue != __constant_cpu_to_le16(USB_ENDPOINT_HALT)
++ || crq->wLength != __constant_cpu_to_le16(0))
++ goto stall;
++
++ target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
++ if (!target)
++ goto stall;
++
++ husb2_ep_writel(target, SET_STA, HUSB2_BIT(FORCE_STALL));
++ } else
++ goto delegate;
++
++ send_status(udc, ep);
++ break;
++ }
++
++ case USB_REQ_SET_ADDRESS:
++ if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
++ goto delegate;
++
++ set_address(udc, le16_to_cpu(crq->wValue));
++ send_status(udc, ep);
++ ep->state = STATUS_STAGE_ADDR;
++ break;
++
++ default:
++ delegate:
++ return udc->driver->setup(&udc->gadget, crq);
++ }
++
++ return 0;
++
++stall:
++ printk(KERN_ERR
++ "udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
++ "halting endpoint...\n",
++ ep_name(ep), crq->bRequestType, crq->bRequest,
++ le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
++ le16_to_cpu(crq->wLength));
++ set_protocol_stall(udc, ep);
++ return -1;
++}
++
++static void husb2_control_irq(struct husb2_udc *udc, struct husb2_ep *ep)
++{
++ struct husb2_request *req;
++ u32 epstatus;
++ u32 epctrl;
++
++restart:
++ epstatus = husb2_ep_readl(ep, STA);
++ epctrl = husb2_ep_readl(ep, CTL);
++
++ DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n",
++ ep_name(ep), epstatus);
++
++ req = NULL;
++ if (!list_empty(&ep->queue))
++ req = list_entry(ep->queue.next,
++ struct husb2_request, queue);
++
++ if ((epctrl & HUSB2_BIT(TX_PK_RDY))
++ && !(epstatus & HUSB2_BIT(TX_PK_RDY))) {
++ DBG(DBG_BUS, "tx pk rdy: %d\n", ep->state);
++
++ if (req->submitted)
++ next_fifo_transaction(ep, req);
++ else
++ submit_request(ep, req);
++
++ if (req->last_transaction) {
++ husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(TX_PK_RDY));
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_COMPLETE));
++ }
++ goto restart;
++ }
++ if ((epstatus & epctrl) & HUSB2_BIT(TX_COMPLETE)) {
++ husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(TX_COMPLETE));
++ DBG(DBG_BUS, "txc: %d\n", ep->state);
++
++ switch (ep->state) {
++ case DATA_STAGE_IN:
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(RX_BK_RDY));
++ husb2_ep_writel(ep, CTL_DIS,
++ HUSB2_BIT(TX_COMPLETE));
++ ep->state = STATUS_STAGE_OUT;
++ break;
++ case STATUS_STAGE_ADDR:
++ /* Activate our new address */
++ husb2_writel(udc, CTRL, (husb2_readl(udc, CTRL)
++ | HUSB2_BIT(FADDR_EN)));
++ husb2_ep_writel(ep, CTL_DIS,
++ HUSB2_BIT(TX_COMPLETE));
++ ep->state = WAIT_FOR_SETUP;
++ break;
++ case STATUS_STAGE_IN:
++ if (req) {
++ list_del_init(&req->queue);
++ request_complete(ep, req, 0);
++ submit_next_request(ep);
++ }
++ BUG_ON(!list_empty(&ep->queue));
++ husb2_ep_writel(ep, CTL_DIS,
++ HUSB2_BIT(TX_COMPLETE));
++ ep->state = WAIT_FOR_SETUP;
++ break;
++ default:
++ printk(KERN_ERR
++ "udc: %s: TXCOMP: Invalid endpoint state %d, "
++ "halting endpoint...\n",
++ ep_name(ep), ep->state);
++ set_protocol_stall(udc, ep);
++ break;
++ }
++
++ goto restart;
++ }
++ if ((epstatus & epctrl) & HUSB2_BIT(RX_BK_RDY)) {
++ DBG(DBG_BUS, "rxc: %d\n", ep->state);
++
++ switch (ep->state) {
++ case STATUS_STAGE_OUT:
++ husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
++
++ if (req) {
++ list_del_init(&req->queue);
++ request_complete(ep, req, 0);
++ }
++ husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(RX_BK_RDY));
++ ep->state = WAIT_FOR_SETUP;
++ break;
++
++ case DATA_STAGE_OUT:
++ receive_data(ep);
++ break;
++
++ default:
++ husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
++ set_protocol_stall(udc, ep);
++ printk(KERN_ERR
++ "udc: %s: RXRDY: Invalid endpoint state %d, "
++ "halting endpoint...\n",
++ ep_name(ep), ep->state);
++ break;
++ }
++
++ goto restart;
++ }
++ if (epstatus & HUSB2_BIT(RX_SETUP)) {
++ union {
++ struct usb_ctrlrequest crq;
++ unsigned long data[2];
++ } crq;
++ unsigned int pkt_len;
++ int ret;
++
++ if (ep->state != WAIT_FOR_SETUP) {
++ /*
++ * Didn't expect a SETUP packet at this
++ * point. Clean up any pending requests (which
++ * may be successful).
++ */
++ int status = -EPROTO;
++
++ /*
++ * RXRDY is dropped when SETUP packets arrive.
++ * Just pretend we received the status packet.
++ */
++ if (ep->state == STATUS_STAGE_OUT)
++ status = 0;
++
++ if (req) {
++ list_del_init(&req->queue);
++ request_complete(ep, req, status);
++ }
++ BUG_ON(!list_empty(&ep->queue));
++ }
++
++ pkt_len = HUSB2_BFEXT(BYTE_COUNT, husb2_ep_readl(ep, STA));
++ DBG(DBG_HW, "Packet length: %u\n", pkt_len);
++ BUG_ON(pkt_len != sizeof(crq));
++
++ DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
++ copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
++
++ /* Free up one bank in the FIFO so that we can
++ * generate or receive a reply right away. */
++ husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_SETUP));
++
++ /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
++ ep->state, crq.crq.bRequestType,
++ crq.crq.bRequest); */
++
++ if (crq.crq.bRequestType & USB_DIR_IN) {
++ /*
++ * The USB 2.0 spec states that "if wLength is
++ * zero, there is no data transfer phase."
++ * However, testusb #14 seems to actually
++ * expect a data phase even if wLength = 0...
++ */
++ ep->state = DATA_STAGE_IN;
++ } else {
++ if (crq.crq.wLength != __constant_cpu_to_le16(0))
++ ep->state = DATA_STAGE_OUT;
++ else
++ ep->state = STATUS_STAGE_IN;
++ }
++
++ ret = -1;
++ if (ep->index == 0)
++ ret = handle_ep0_setup(udc, ep, &crq.crq);
++ else
++ ret = udc->driver->setup(&udc->gadget, &crq.crq);
++
++ DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
++ crq.crq.bRequestType, crq.crq.bRequest,
++ le16_to_cpu(crq.crq.wLength), ep->state, ret);
++
++ if (ret < 0) {
++ /* Let the host know that we failed */
++ set_protocol_stall(udc, ep);
++ }
++ }
++}
++
++static void husb2_ep_irq(struct husb2_udc *udc, struct husb2_ep *ep)
++{
++ struct husb2_request *req;
++ u32 epstatus;
++ u32 epctrl;
++
++ epstatus = husb2_ep_readl(ep, STA);
++ epctrl = husb2_ep_readl(ep, CTL);
++
++ DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n",
++ ep_name(ep), epstatus);
++
++ while ((epctrl & HUSB2_BIT(TX_PK_RDY))
++ && !(epstatus & HUSB2_BIT(TX_PK_RDY))) {
++ BUG_ON(!ep_is_in(ep));
++
++ DBG(DBG_BUS, "%s: TX PK ready\n", ep_name(ep));
++
++ if (list_empty(&ep->queue)) {
++ dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
++ husb2_ep_writel(ep, CTL_DIS, HUSB2_BIT(TX_PK_RDY));
++ return;
++ }
++
++ req = list_entry(ep->queue.next, struct husb2_request, queue);
++
++ if (req->using_dma) {
++ BUG_ON(!req->send_zlp);
++
++ /* Send a zero-length packet */
++ husb2_ep_writel(ep, SET_STA,
++ HUSB2_BIT(TX_PK_RDY));
++ husb2_ep_writel(ep, CTL_DIS,
++ HUSB2_BIT(TX_PK_RDY));
++ list_del_init(&req->queue);
++ submit_next_request(ep);
++ request_complete(ep, req, 0);
++ } else {
++ if (req->submitted)
++ next_fifo_transaction(ep, req);
++ else
++ submit_request(ep, req);
++
++ if (req->last_transaction) {
++ list_del_init(&req->queue);
++ submit_next_request(ep);
++ request_complete(ep, req, 0);
++ }
++ }
++
++ epstatus = husb2_ep_readl(ep, STA);
++ epctrl = husb2_ep_readl(ep, CTL);
++ }
++ if ((epstatus & epctrl) & HUSB2_BIT(RX_BK_RDY)) {
++ BUG_ON(ep_is_in(ep));
++
++ DBG(DBG_BUS, "%s: RX data ready\n", ep_name(ep));
++ receive_data(ep);
++ husb2_ep_writel(ep, CLR_STA, HUSB2_BIT(RX_BK_RDY));
++ }
++}
++
++static void husb2_dma_irq(struct husb2_udc *udc, struct husb2_ep *ep)
++{
++ struct husb2_request *req;
++ u32 status, control, pending;
++
++ status = husb2_dma_readl(ep, STATUS);
++ control = husb2_dma_readl(ep, CONTROL);
++#ifdef CONFIG_DEBUG_FS
++ ep->last_dma_status = status;
++#endif
++ pending = status & control;
++ DBG(DBG_INT, "dma irq, status=%#08x, pending=%#08x, control=%#08x\n",
++ status, pending, control);
++
++ BUG_ON(status & HUSB2_BIT(DMA_CH_EN));
++
++ if (list_empty(&ep->queue))
++ /* Might happen if a reset comes along at the right moment */
++ return;
++
++ if (pending & (HUSB2_BIT(DMA_END_TR_ST) | HUSB2_BIT(DMA_END_BUF_ST))) {
++ req = list_entry(ep->queue.next, struct husb2_request, queue);
++ husb2_update_req(ep, req, status);
++
++ if (req->send_zlp) {
++ husb2_ep_writel(ep, CTL_ENB, HUSB2_BIT(TX_PK_RDY));
++ } else {
++ list_del_init(&req->queue);
++ submit_next_request(ep);
++ request_complete(ep, req, 0);
++ }
++ }
++}
++
++static irqreturn_t husb2_udc_irq(int irq, void *devid, struct pt_regs *regs)
++{
++ struct husb2_udc *udc = devid;
++ u32 status;
++ u32 dma_status;
++ u32 ep_status;
++
++ spin_lock(&udc->lock);
++
++ status = husb2_readl(udc, INT_STA);
++ DBG(DBG_INT, "irq, status=%#08x\n", status);
++
++ if (status & HUSB2_BIT(DET_SUSPEND)) {
++ husb2_writel(udc, INT_CLR, HUSB2_BIT(DET_SUSPEND));
++ //DBG(DBG_BUS, "Suspend detected\n");
++ if (udc->gadget.speed != USB_SPEED_UNKNOWN
++ && udc->driver && udc->driver->suspend)
++ udc->driver->suspend(&udc->gadget);
++ }
++
++ if (status & HUSB2_BIT(WAKE_UP)) {
++ husb2_writel(udc, INT_CLR, HUSB2_BIT(WAKE_UP));
++ //DBG(DBG_BUS, "Wake Up CPU detected\n");
++ }
++
++ if (status & HUSB2_BIT(END_OF_RESUME)) {
++ husb2_writel(udc, INT_CLR, HUSB2_BIT(END_OF_RESUME));
++ DBG(DBG_BUS, "Resume detected\n");
++ if (udc->gadget.speed != USB_SPEED_UNKNOWN
++ && udc->driver && udc->driver->resume)
++ udc->driver->resume(&udc->gadget);
++ }
++
++ dma_status = HUSB2_BFEXT(DMA_INT, status);
++ if (dma_status) {
++ int i;
++
++ for (i = 1; i < HUSB2_NR_ENDPOINTS; i++)
++ if (dma_status & (1 << i))
++ husb2_dma_irq(udc, &husb2_ep[i]);
++ }
++
++ ep_status = HUSB2_BFEXT(EPT_INT, status);
++ if (ep_status) {
++ int i;
++
++ for (i = 0; i < HUSB2_NR_ENDPOINTS; i++)
++ if (ep_status & (1 << i)) {
++ if (ep_is_control(&husb2_ep[i]))
++ husb2_control_irq(udc, &husb2_ep[i]);
++ else
++ husb2_ep_irq(udc, &husb2_ep[i]);
++ }
++ }
++
++ if (status & HUSB2_BIT(END_OF_RESET)) {
++ husb2_writel(udc, INT_CLR, HUSB2_BIT(END_OF_RESET));
++ if (status & HUSB2_BIT(HIGH_SPEED)) {
++ DBG(DBG_BUS, "High-speed bus reset detected\n");
++ udc->gadget.speed = USB_SPEED_HIGH;
++ } else {
++ DBG(DBG_BUS, "Full-speed bus reset detected\n");
++ udc->gadget.speed = USB_SPEED_FULL;
++ }
++ /* Better start from scratch... */
++ reset_all_endpoints(udc);
++ husb2_ep[0].state = WAIT_FOR_SETUP;
++ udc_enable(udc);
++ }
++
++ spin_unlock(&udc->lock);
++
++ return IRQ_HANDLED;
++}
++
++int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++{
++ struct husb2_udc *udc = &the_udc;
++ int ret;
++
++ spin_lock(&udc->lock);
++
++ ret = -ENODEV;
++ if (!udc->pdev)
++ goto out;
++ ret = -EBUSY;
++ if (udc->driver)
++ goto out;
++
++ udc->driver = driver;
++ udc->gadget.dev.driver = &driver->driver;
++
++ device_add(&udc->gadget.dev);
++ ret = driver->bind(&udc->gadget);
++ if (ret) {
++ DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
++ driver->driver.name, ret);
++ device_del(&udc->gadget.dev);
++
++ udc->driver = NULL;
++ udc->gadget.dev.driver = NULL;
++ goto out;
++ }
++
++ /* TODO: Create sysfs files */
++
++ DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
++ udc_enable(udc);
++
++out:
++ spin_unlock(&udc->lock);
++ return ret;
++}
++EXPORT_SYMBOL(usb_gadget_register_driver);
++
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++{
++ struct husb2_udc *udc = &the_udc;
++ int ret;
++
++ spin_lock(&udc->lock);
++
++ ret = -ENODEV;
++ if (!udc->pdev)
++ goto out;
++ ret = -EINVAL;
++ if (driver != udc->driver)
++ goto out;
++
++ local_irq_disable();
++ udc_disable(udc);
++ local_irq_enable();
++
++ driver->unbind(&udc->gadget);
++ udc->driver = NULL;
++
++ device_del(&udc->gadget.dev);
++
++ /* TODO: Remove sysfs files */
++
++ DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
++
++out:
++ spin_unlock(&udc->lock);
++ return ret;
++}
++EXPORT_SYMBOL(usb_gadget_unregister_driver);
++
++static int __devinit husb2_udc_probe(struct platform_device *pdev)
++{
++ struct resource *regs, *fifo;
++ struct clk *pclk, *hclk;
++ struct husb2_udc *udc = &the_udc;
++ int irq, ret, i;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
++ fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
++ if (!regs || !fifo)
++ return -ENXIO;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++
++ pclk = clk_get(&pdev->dev, "pclk");
++ if (IS_ERR(pclk))
++ return PTR_ERR(pclk);
++ hclk = clk_get(&pdev->dev, "hclk");
++ if (IS_ERR(hclk)) {
++ ret = PTR_ERR(hclk);
++ goto out_put_pclk;
++ }
++
++ clk_enable(pclk);
++ clk_enable(hclk);
++
++ udc->pdev = pdev;
++ udc->pclk = pclk;
++ udc->hclk = hclk;
++
++ ret = -ENOMEM;
++ udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!udc->regs) {
++ dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
++ goto out_disable_clocks;
++ }
++ dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
++ (unsigned long)regs->start, udc->regs);
++ udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
++ if (!udc->fifo) {
++ dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
++ goto out_unmap_regs;
++ }
++ dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
++ (unsigned long)fifo->start, udc->fifo);
++
++ device_initialize(&udc->gadget.dev);
++ udc->gadget.dev.parent = &pdev->dev;
++ udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
++
++ /* The 3-word descriptors must be 4-word aligned... */
++ udc->desc_pool = dma_pool_create("husb2-desc", &pdev->dev,
++ sizeof(struct husb2_dma_desc),
++ 16, 0);
++ if (!udc->desc_pool) {
++ dev_err(&pdev->dev, "Cannot create descriptor DMA pool\n");
++ goto out_unmap_fifo;
++ }
++
++ platform_set_drvdata(pdev, udc);
++
++ udc_disable(udc);
++
++ INIT_LIST_HEAD(&husb2_ep[0].ep.ep_list);
++ husb2_ep[0].ep_regs = udc->regs + HUSB2_EPT_BASE(0);
++ husb2_ep[0].dma_regs = udc->regs + HUSB2_DMA_BASE(0);
++ husb2_ep[0].fifo = udc->fifo + HUSB2_FIFO_BASE(0);
++ for (i = 1; i < ARRAY_SIZE(husb2_ep); i++) {
++ struct husb2_ep *ep = &husb2_ep[i];
++
++ ep->ep_regs = udc->regs + HUSB2_EPT_BASE(i);
++ ep->dma_regs = udc->regs + HUSB2_DMA_BASE(i);
++ ep->fifo = udc->fifo + HUSB2_FIFO_BASE(i);
++
++ list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
++ }
++
++ ret = request_irq(irq, husb2_udc_irq, SA_SAMPLE_RANDOM,
++ "husb2_udc", udc);
++ if (ret) {
++ dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
++ irq, ret);
++ goto out_free_pool;
++ }
++ udc->irq = irq;
++
++ husb2_init_debugfs(udc);
++
++ return 0;
++
++out_free_pool:
++ dma_pool_destroy(udc->desc_pool);
++out_unmap_fifo:
++ iounmap(udc->fifo);
++out_unmap_regs:
++ iounmap(udc->regs);
++out_disable_clocks:
++ clk_disable(hclk);
++ clk_disable(pclk);
++ clk_put(hclk);
++out_put_pclk:
++ clk_put(pclk);
++
++ platform_set_drvdata(pdev, NULL);
++
++ return ret;
++}
++
++static int __devexit husb2_udc_remove(struct platform_device *pdev)
++{
++ struct husb2_udc *udc;
++
++ udc = platform_get_drvdata(pdev);
++ if (!udc)
++ return 0;
++
++ husb2_cleanup_debugfs(udc);
++
++ free_irq(udc->irq, udc);
++ dma_pool_destroy(udc->desc_pool);
++ iounmap(udc->fifo);
++ iounmap(udc->regs);
++ clk_disable(udc->hclk);
++ clk_disable(udc->pclk);
++ clk_put(udc->hclk);
++ clk_put(udc->pclk);
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver udc_driver = {
++ .probe = husb2_udc_probe,
++ .remove = __devexit_p(husb2_udc_remove),
++ .driver = {
++ .name = "usb",
++ },
++};
++
++static int __init udc_init(void)
++{
++ printk(KERN_INFO "husb2device: Driver version %s\n", DRIVER_VERSION);
++ return platform_driver_register(&udc_driver);
++}
++module_init(udc_init);
++
++static void __exit udc_exit(void)
++{
++ platform_driver_unregister(&udc_driver);
++}
++module_exit(udc_exit);
++
++MODULE_DESCRIPTION("Atmel HUSB2 Device Controller driver");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/usb/gadget/husb2_udc.h 2006-11-02 16:03:44.000000000 +0100
+@@ -0,0 +1,406 @@
++/*
++ * Driver for the Atmel HUSB2device high speed USB device controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __LINUX_USB_GADGET_HUSB2_UDC_H__
++#define __LINUX_USB_GADGET_HUSB2_UDC_H__
++
++/* USB register offsets */
++#define HUSB2_CTRL 0x0000
++#define HUSB2_FNUM 0x0004
++#define HUSB2_INT_ENB 0x0010
++#define HUSB2_INT_STA 0x0014
++#define HUSB2_INT_CLR 0x0018
++#define HUSB2_EPT_RST 0x001c
++#define HUSB2_TST_SOF_CNT 0x00d0
++#define HUSB2_TST_CNT_A 0x00d4
++#define HUSB2_TST_CNT_B 0x00d8
++#define HUSB2_TST_MODE_REG 0x00dc
++#define HUSB2_TST 0x00f0
++
++/* USB endpoint register offsets */
++#define HUSB2_EPT_CFG 0x0000
++#define HUSB2_EPT_CTL_ENB 0x0004
++#define HUSB2_EPT_CTL_DIS 0x0008
++#define HUSB2_EPT_CTL 0x000c
++#define HUSB2_EPT_SET_STA 0x0014
++#define HUSB2_EPT_CLR_STA 0x0018
++#define HUSB2_EPT_STA 0x001c
++
++/* USB DMA register offsets */
++#define HUSB2_DMA_NXT_DSC 0x0000
++#define HUSB2_DMA_ADDRESS 0x0004
++#define HUSB2_DMA_CONTROL 0x0008
++#define HUSB2_DMA_STATUS 0x000c
++
++/* Bitfields in CTRL */
++#define HUSB2_DEV_ADDR_OFFSET 0
++#define HUSB2_DEV_ADDR_SIZE 7
++#define HUSB2_FADDR_EN_OFFSET 7
++#define HUSB2_FADDR_EN_SIZE 1
++#define HUSB2_EN_HUSB2_OFFSET 8
++#define HUSB2_EN_HUSB2_SIZE 1
++#define HUSB2_DETACH_OFFSET 9
++#define HUSB2_DETACH_SIZE 1
++#define HUSB2_REMOTE_WAKE_UP_OFFSET 10
++#define HUSB2_REMOTE_WAKE_UP_SIZE 1
++
++/* Bitfields in FNUM */
++#define HUSB2_MICRO_FRAME_NUM_OFFSET 0
++#define HUSB2_MICRO_FRAME_NUM_SIZE 3
++#define HUSB2_FRAME_NUMBER_OFFSET 3
++#define HUSB2_FRAME_NUMBER_SIZE 11
++#define HUSB2_FRAME_NUM_ERROR_OFFSET 31
++#define HUSB2_FRAME_NUM_ERROR_SIZE 1
++
++/* Bitfields in INT_ENB/INT_STA/INT_CLR */
++#define HUSB2_HIGH_SPEED_OFFSET 0
++#define HUSB2_HIGH_SPEED_SIZE 1
++#define HUSB2_DET_SUSPEND_OFFSET 1
++#define HUSB2_DET_SUSPEND_SIZE 1
++#define HUSB2_MICRO_SOF_OFFSET 2
++#define HUSB2_MICRO_SOF_SIZE 1
++#define HUSB2_SOF_OFFSET 3
++#define HUSB2_SOF_SIZE 1
++#define HUSB2_END_OF_RESET_OFFSET 4
++#define HUSB2_END_OF_RESET_SIZE 1
++#define HUSB2_WAKE_UP_OFFSET 5
++#define HUSB2_WAKE_UP_SIZE 1
++#define HUSB2_END_OF_RESUME_OFFSET 6
++#define HUSB2_END_OF_RESUME_SIZE 1
++#define HUSB2_UPSTREAM_RESUME_OFFSET 7
++#define HUSB2_UPSTREAM_RESUME_SIZE 1
++#define HUSB2_EPT_INT_OFFSET 8
++#define HUSB2_EPT_INT_SIZE 16
++#define HUSB2_DMA_INT_OFFSET 24
++#define HUSB2_DMA_INT_SIZE 8
++
++/* Bitfields in EPT_RST */
++#define HUSB2_RST_OFFSET 0
++#define HUSB2_RST_SIZE 16
++
++/* Bitfields in TST_SOF_CNT */
++#define HUSB2_SOF_CNT_MAX_OFFSET 0
++#define HUSB2_SOF_CNT_MAX_SIZE 7
++#define HUSB2_SOF_CNT_LOAD_OFFSET 7
++#define HUSB2_SOF_CNT_LOAD_SIZE 1
++
++/* Bitfields in TST_CNT_A */
++#define HUSB2_CNT_A_MAX_OFFSET 0
++#define HUSB2_CNT_A_MAX_SIZE 7
++#define HUSB2_CNT_A_LOAD_OFFSET 7
++#define HUSB2_CNT_A_LOAD_SIZE 1
++
++/* Bitfields in TST_CNT_B */
++#define HUSB2_CNT_B_MAX_OFFSET 0
++#define HUSB2_CNT_B_MAX_SIZE 7
++#define HUSB2_CNT_B_LOAD_OFFSET 7
++#define HUSB2_CNT_B_LOAD_SIZE 1
++
++/* Bitfields in TST_MODE_REG */
++#define HUSB2_TST_MODE_OFFSET 0
++#define HUSB2_TST_MODE_SIZE 6
++
++/* Bitfields in HUSB2_TST */
++#define HUSB2_SPEED_CFG_OFFSET 0
++#define HUSB2_SPEED_CFG_SIZE 2
++#define HUSB2_TST_J_MODE_OFFSET 2
++#define HUSB2_TST_J_MODE_SIZE 1
++#define HUSB2_TST_K_MODE_OFFSET 3
++#define HUSB2_TST_K_MODE_SIZE 1
++#define HUSB2_TST_PKT_MODE_OFFSE 4
++#define HUSB2_TST_PKT_MODE_SIZE 1
++#define HUSB2_OPMODE2_OFFSET 5
++#define HUSB2_OPMODE2_SIZE 1
++
++/* Bitfields in EPT_CFG */
++#define HUSB2_EPT_SIZE_OFFSET 0
++#define HUSB2_EPT_SIZE_SIZE 3
++#define HUSB2_EPT_DIR_OFFSET 3
++#define HUSB2_EPT_DIR_SIZE 1
++#define HUSB2_EPT_TYPE_OFFSET 4
++#define HUSB2_EPT_TYPE_SIZE 2
++#define HUSB2_BK_NUMBER_OFFSET 6
++#define HUSB2_BK_NUMBER_SIZE 2
++#define HUSB2_NB_TRANS_OFFSET 8
++#define HUSB2_NB_TRANS_SIZE 2
++#define HUSB2_EPT_MAPPED_OFFSET 31
++#define HUSB2_EPT_MAPPED_SIZE 1
++
++/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
++#define HUSB2_EPT_ENABLE_OFFSET 0
++#define HUSB2_EPT_ENABLE_SIZE 1
++#define HUSB2_AUTO_VALID_OFFSET 1
++#define HUSB2_AUTO_VALID_SIZE 1
++#define HUSB2_INT_DIS_DMA_OFFSET 3
++#define HUSB2_INT_DIS_DMA_SIZE 1
++#define HUSB2_NYET_DIS_OFFSET 4
++#define HUSB2_NYET_DIS_SIZE 1
++#define HUSB2_DATAX_RX_OFFSET 6
++#define HUSB2_DATAX_RX_SIZE 1
++#define HUSB2_MDATA_RX_OFFSET 7
++#define HUSB2_MDATA_RX_SIZE 1
++/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
++#define HUSB2_BUSY_BANK_IE_OFFSET 18
++#define HUSB2_BUSY_BANK_IE_SIZE 1
++
++/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
++#define HUSB2_FORCE_STALL_OFFSET 5
++#define HUSB2_FORCE_STALL_SIZE 1
++#define HUSB2_TOGGLE_SEQ_OFFSET 6
++#define HUSB2_TOGGLE_SEQ_SIZE 2
++#define HUSB2_ERR_OVFLW_OFFSET 8
++#define HUSB2_ERR_OVFLW_SIZE 1
++#define HUSB2_RX_BK_RDY_OFFSET 9
++#define HUSB2_RX_BK_RDY_SIZE 1
++#define HUSB2_KILL_BANK_OFFSET 9
++#define HUSB2_KILL_BANK_SIZE 1
++#define HUSB2_TX_COMPLETE_OFFSET 10
++#define HUSB2_TX_COMPLETE_SIZE 1
++#define HUSB2_TX_PK_RDY_OFFSET 11
++#define HUSB2_TX_PK_RDY_SIZE 1
++#define HUSB2_ISO_ERR_TRANS_OFFSET 11
++#define HUSB2_ISO_ERR_TRANS_SIZE 1
++#define HUSB2_RX_SETUP_OFFSET 12
++#define HUSB2_RX_SETUP_SIZE 1
++#define HUSB2_ISO_ERR_FLOW_OFFSET 12
++#define HUSB2_ISO_ERR_FLOW_SIZE 1
++#define HUSB2_STALL_SENT_OFFSET 13
++#define HUSB2_STALL_SENT_SIZE 1
++#define HUSB2_ISO_ERR_CRC_OFFSET 13
++#define HUSB2_ISO_ERR_CRC_SIZE 1
++#define HUSB2_ISO_ERR_NBTRANS_OFFSET 13
++#define HUSB2_ISO_ERR_NBTRANS_SIZE 1
++#define HUSB2_NAK_IN_OFFSET 14
++#define HUSB2_NAK_IN_SIZE 1
++#define HUSB2_ISO_ERR_FLUSH_OFFSET 14
++#define HUSB2_ISO_ERR_FLUSH_SIZE 1
++#define HUSB2_NAK_OUT_OFFSET 15
++#define HUSB2_NAK_OUT_SIZE 1
++#define HUSB2_CURRENT_BANK_OFFSET 16
++#define HUSB2_CURRENT_BANK_SIZE 2
++#define HUSB2_BUSY_BANKS_OFFSET 18
++#define HUSB2_BUSY_BANKS_SIZE 2
++#define HUSB2_BYTE_COUNT_OFFSET 20
++#define HUSB2_BYTE_COUNT_SIZE 11
++#define HUSB2_SHORT_PACKET_OFFSET 31
++#define HUSB2_SHORT_PACKET_SIZE 1
++
++/* Bitfields in DMA_CONTROL */
++#define HUSB2_DMA_CH_EN_OFFSET 0
++#define HUSB2_DMA_CH_EN_SIZE 1
++#define HUSB2_DMA_LINK_OFFSET 1
++#define HUSB2_DMA_LINK_SIZE 1
++#define HUSB2_DMA_END_TR_EN_OFFSET 2
++#define HUSB2_DMA_END_TR_EN_SIZE 1
++#define HUSB2_DMA_END_BUF_EN_OFFSET 3
++#define HUSB2_DMA_END_BUF_EN_SIZE 1
++#define HUSB2_DMA_END_TR_IE_OFFSET 4
++#define HUSB2_DMA_END_TR_IE_SIZE 1
++#define HUSB2_DMA_END_BUF_IE_OFFSET 5
++#define HUSB2_DMA_END_BUF_IE_SIZE 1
++#define HUSB2_DMA_DESC_LOAD_IE_OFFSET 6
++#define HUSB2_DMA_DESC_LOAD_IE_SIZE 1
++#define HUSB2_DMA_BURST_LOCK_OFFSET 7
++#define HUSB2_DMA_BURST_LOCK_SIZE 1
++#define HUSB2_DMA_BUF_LEN_OFFSET 16
++#define HUSB2_DMA_BUF_LEN_SIZE 16
++
++/* Bitfields in DMA_STATUS */
++#define HUSB2_DMA_CH_ACTIVE_OFFSET 1
++#define HUSB2_DMA_CH_ACTIVE_SIZE 1
++#define HUSB2_DMA_END_TR_ST_OFFSET 4
++#define HUSB2_DMA_END_TR_ST_SIZE 1
++#define HUSB2_DMA_END_BUF_ST_OFFSET 5
++#define HUSB2_DMA_END_BUF_ST_SIZE 1
++#define HUSB2_DMA_DESC_LOAD_ST_OFFSET 6
++#define HUSB2_DMA_DESC_LOAD_ST_SIZE 1
++
++/* Constants for SPEED_CFG */
++#define HUSB2_SPEED_CFG_NORMAL 0
++#define HUSB2_SPEED_CFG_FORCE_HIGH 2
++#define HUSB2_SPEED_CFG_FORCE_FULL 3
++
++/* Constants for EPT_SIZE */
++#define HUSB2_EPT_SIZE_8 0
++#define HUSB2_EPT_SIZE_16 1
++#define HUSB2_EPT_SIZE_32 2
++#define HUSB2_EPT_SIZE_64 3
++#define HUSB2_EPT_SIZE_128 4
++#define HUSB2_EPT_SIZE_256 5
++#define HUSB2_EPT_SIZE_512 6
++#define HUSB2_EPT_SIZE_1024 7
++
++/* Constants for EPT_TYPE */
++#define HUSB2_EPT_TYPE_CONTROL 0
++#define HUSB2_EPT_TYPE_ISO 1
++#define HUSB2_EPT_TYPE_BULK 2
++#define HUSB2_EPT_TYPE_INT 3
++
++/* Constants for BK_NUMBER */
++#define HUSB2_BK_NUMBER_ZERO 0
++#define HUSB2_BK_NUMBER_ONE 1
++#define HUSB2_BK_NUMBER_DOUBLE 2
++#define HUSB2_BK_NUMBER_TRIPLE 3
++
++/* Bit manipulation macros */
++#define HUSB2_BIT(name) \
++ (1 << HUSB2_##name##_OFFSET)
++#define HUSB2_BF(name,value) \
++ (((value) & ((1 << HUSB2_##name##_SIZE) - 1)) \
++ << HUSB2_##name##_OFFSET)
++#define HUSB2_BFEXT(name,value) \
++ (((value) >> HUSB2_##name##_OFFSET) \
++ & ((1 << HUSB2_##name##_SIZE) - 1))
++#define HUSB2_BFINS(name,value,old) \
++ (((old) & ~(((1 << HUSB2_##name##_SIZE) - 1) \
++ << HUSB2_##name##_OFFSET)) \
++ | HUSB2_BF(name,value))
++
++/* Register access macros */
++#define husb2_readl(udc,reg) \
++ __raw_readl((udc)->regs + HUSB2_##reg)
++#define husb2_writel(udc,reg,value) \
++ __raw_writel((value), (udc)->regs + HUSB2_##reg)
++#define husb2_ep_readl(ep,reg) \
++ __raw_readl((ep)->ep_regs + HUSB2_EPT_##reg)
++#define husb2_ep_writel(ep,reg,value) \
++ __raw_writel((value), (ep)->ep_regs + HUSB2_EPT_##reg)
++#define husb2_dma_readl(ep,reg) \
++ __raw_readl((ep)->dma_regs + HUSB2_DMA_##reg)
++#define husb2_dma_writel(ep,reg,value) \
++ __raw_writel((value), (ep)->dma_regs + HUSB2_DMA_##reg)
++
++/* Calculate base address for a given endpoint or DMA controller */
++#define HUSB2_EPT_BASE(x) (0x100 + (x) * 0x20)
++#define HUSB2_DMA_BASE(x) (0x300 + (x) * 0x10)
++#define HUSB2_FIFO_BASE(x) ((x) << 16)
++
++/* Synth parameters */
++#define HUSB2_NR_ENDPOINTS 7
++
++#define EP0_FIFO_SIZE 64
++#define EP0_EPT_SIZE HUSB2_EPT_SIZE_64
++#define EP0_NR_BANKS 1
++#define BULK_FIFO_SIZE 512
++#define BULK_EPT_SIZE HUSB2_EPT_SIZE_512
++#define BULK_NR_BANKS 2
++#define ISO_FIFO_SIZE 1024
++#define ISO_EPT_SIZE HUSB2_EPT_SIZE_1024
++#define ISO_NR_BANKS 3
++#define INT_FIFO_SIZE 64
++#define INT_EPT_SIZE HUSB2_EPT_SIZE_64
++#define INT_NR_BANKS 3
++
++enum husb2_ctrl_state {
++ WAIT_FOR_SETUP,
++ DATA_STAGE_IN,
++ DATA_STAGE_OUT,
++ STATUS_STAGE_IN,
++ STATUS_STAGE_OUT,
++ STATUS_STAGE_ADDR,
++};
++/*
++ EP_STATE_IDLE,
++ EP_STATE_SETUP,
++ EP_STATE_IN_DATA,
++ EP_STATE_OUT_DATA,
++ EP_STATE_SET_ADDR_STATUS,
++ EP_STATE_RX_STATUS,
++ EP_STATE_TX_STATUS,
++ EP_STATE_HALT,
++*/
++
++struct husb2_dma_desc {
++ dma_addr_t next;
++ dma_addr_t addr;
++ u32 ctrl;
++};
++
++struct husb2_ep {
++ int state;
++ void __iomem *ep_regs;
++ void __iomem *dma_regs;
++ void __iomem *fifo;
++ struct usb_ep ep;
++ struct husb2_udc *udc;
++
++ struct list_head queue;
++ const struct usb_endpoint_descriptor *desc;
++
++ u16 fifo_size;
++ u8 nr_banks;
++ u8 index;
++ u8 capabilities;
++
++#ifdef CONFIG_DEBUG_FS
++ u32 last_dma_status;
++ struct dentry *debugfs_dir;
++ struct dentry *debugfs_queue;
++ struct dentry *debugfs_dma_status;
++#endif
++};
++#define HUSB2_EP_CAP_ISOC 0x0001
++#define HUSB2_EP_CAP_DMA 0x0002
++
++struct husb2_packet {
++ struct husb2_dma_desc *desc;
++ dma_addr_t desc_dma;
++};
++
++struct husb2_request {
++ struct usb_request req;
++ struct list_head queue;
++
++ struct husb2_packet *packet;
++ unsigned int nr_pkts;
++
++ unsigned int submitted:1;
++ unsigned int using_dma:1;
++ unsigned int last_transaction:1;
++ unsigned int send_zlp:1;
++};
++
++struct husb2_udc {
++ spinlock_t lock;
++
++ void __iomem *regs;
++ void __iomem *fifo;
++
++ struct dma_pool *desc_pool;
++
++ struct usb_gadget gadget;
++ struct usb_gadget_driver *driver;
++ struct platform_device *pdev;
++ int irq;
++ struct clk *pclk;
++ struct clk *hclk;
++
++#ifdef CONFIG_DEBUG_FS
++ struct dentry *debugfs_root;
++ struct dentry *debugfs_regs;
++#endif
++};
++
++#define to_husb2_ep(x) container_of((x), struct husb2_ep, ep)
++#define to_husb2_req(x) container_of((x), struct husb2_request, req)
++#define to_husb2_udc(x) container_of((x), struct husb2_udc, gadget)
++
++#define ep_index(ep) ((ep)->index)
++#define ep_can_dma(ep) ((ep)->capabilities & HUSB2_EP_CAP_DMA)
++#define ep_is_in(ep) (((ep)->desc->bEndpointAddress \
++ & USB_ENDPOINT_DIR_MASK) \
++ == USB_DIR_IN)
++#define ep_is_isochronous(ep) \
++ (((ep)->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) \
++ == USB_ENDPOINT_XFER_ISOC)
++#define ep_is_control(ep) (ep_index(ep) == 0)
++#define ep_name(ep) ((ep)->ep.name)
++#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
++
++#endif /* __LINUX_USB_GADGET_HUSB2_H */
diff --git a/packages/linux/linux-2.6.18/atmel-lcdc-framebuffer-driver.patch b/packages/linux/linux-2.6.18/atmel-lcdc-framebuffer-driver.patch
new file mode 100644
index 0000000000..d4c9204059
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-lcdc-framebuffer-driver.patch
@@ -0,0 +1,1192 @@
+---
+ drivers/video/Kconfig | 22 +
+ drivers/video/Makefile | 1
+ drivers/video/fbmem.c | 6
+ drivers/video/sidsafb.c | 805 ++++++++++++++++++++++++++++++++++++++++
+ include/asm-avr32/periph/lcdc.h | 271 +++++++++++++
+ include/linux/fb.h | 3
+ 6 files changed, 1107 insertions(+), 1 deletion(-)
+
+Index: linux-2.6.18-avr32/drivers/video/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/video/Kconfig 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/drivers/video/Kconfig 2006-11-02 15:56:20.000000000 +0100
+@@ -271,6 +271,28 @@ config FB_SA1100
+ If you plan to use the LCD display with your SA-1100 system, say
+ Y here.
+
++config FB_SIDSA
++ tristate "SIDSA LCDC support"
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ depends on FB && AVR32
++ help
++ This enables support for the SIDSA LCD Controller.
++
++config FB_SIDSA_DEFAULT_BPP
++ int "SIDSA LCDC default color depth"
++ default 24
++ depends on FB_SIDSA
++ help
++ Specify the maximum color depth you want to be able to
++ support. This, together with the resolution of the LCD
++ panel, determines the amount of framebuffer memory allocated
++ when the driver is initialized.
++
++ Allowable values are 1, 2, 4, 8, 16, 24 and 32. If unsure,
++ say 24.
++
+ config FB_IMX
+ tristate "Motorola i.MX LCD support"
+ depends on FB && ARM && ARCH_IMX
+Index: linux-2.6.18-avr32/drivers/video/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/video/Makefile 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/drivers/video/Makefile 2006-11-02 15:56:20.000000000 +0100
+@@ -75,6 +75,7 @@ obj-$(CONFIG_FB_HP300) += hpf
+ obj-$(CONFIG_FB_G364) += g364fb.o
+ obj-$(CONFIG_FB_SA1100) += sa1100fb.o
+ obj-$(CONFIG_FB_SUN3) += sun3fb.o
++obj-$(CONFIG_FB_SIDSA) += sidsafb.o
+ obj-$(CONFIG_FB_HIT) += hitfb.o
+ obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o
+ obj-$(CONFIG_FB_PVR2) += pvr2fb.o
+Index: linux-2.6.18-avr32/drivers/video/fbmem.c
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/video/fbmem.c 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/drivers/video/fbmem.c 2006-11-02 15:56:20.000000000 +0100
+@@ -1153,6 +1153,7 @@ fb_mmap(struct file *file, struct vm_are
+ /* frame buffer memory */
+ start = info->fix.smem_start;
+ len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.smem_len);
++ pr_debug("fb_mmap: start = 0x%08lx, len = 0x%08lx\n", start, len);
+ if (off >= len) {
+ /* memory mapped io */
+ off -= len;
+@@ -1168,6 +1169,7 @@ fb_mmap(struct file *file, struct vm_are
+ if ((vma->vm_end - vma->vm_start + off) > len)
+ return -EINVAL;
+ off += start;
++ pr_debug("fb_mmap: off = 0x%08lx\n", off);
+ vma->vm_pgoff = off >> PAGE_SHIFT;
+ /* This is an IO map - tell maydump to skip this VMA */
+ vma->vm_flags |= VM_IO | VM_RESERVED;
+@@ -1198,6 +1200,10 @@ fb_mmap(struct file *file, struct vm_are
+ pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
+ #elif defined(__arm__) || defined(__sh__) || defined(__m32r__)
+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++#elif defined(__avr32__)
++ vma->vm_page_prot = __pgprot((pgprot_val(vma->vm_page_prot)
++ & ~_PAGE_CACHABLE)
++ | (_PAGE_BUFFER | _PAGE_DIRTY));
+ #elif defined(__ia64__)
+ if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+Index: linux-2.6.18-avr32/drivers/video/sidsafb.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/video/sidsafb.c 2006-11-02 16:07:55.000000000 +0100
+@@ -0,0 +1,805 @@
++/*
++ * Framebuffer Driver for Atmel/SIDSA LCD Controller
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#undef DEBUG
++
++#include <linux/config.h>
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/board.h>
++
++#include <asm/periph/lcdc.h>
++
++/* More or less configurable parameters */
++#define SIDSAFB_FIFO_SIZE 512
++#define SIDSAFB_DMA_BURST_LEN 8
++
++/* TODO: These should be autogenerated from part description file */
++#define LCDC_DISTYPE_STN_MONO 0
++#define LCDC_DISTYPE_STN_COLOR 1
++#define LCDC_DISTYPE_TFT 2
++#define LCDC_LUT 0xc00
++
++struct sidsafb_info {
++ spinlock_t lock;
++ struct fb_info * info;
++ void __iomem * regs;
++ unsigned long irq_base;
++ wait_queue_head_t vsync_wait;
++ unsigned int guard_time;
++ struct clk *hclk;
++ struct clk *pixclk;
++ struct platform_device *pdev;
++ u32 pseudo_palette[16];
++};
++
++/*
++ * How large framebuffer to allocate if none was provided by the
++ * platform. This default is the smallest we can possibly get away
++ * with.
++ */
++static unsigned long fb_size = (320 * 240);
++
++#if 0
++static struct fb_videomode sony_modes[] = {
++ {
++ .refresh = 48,
++ .xres = 240, .yres = 160,
++ .pixclock = 520833,
++
++ .left_margin = 7, .right_margin = 9,
++ .upper_margin = 19, .lower_margin = 20,
++ .hsync_len = 9, .vsync_len = 2,
++
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ },
++};
++#endif
++
++#if 0
++static struct fb_videomode vga_modes[] = {
++ {
++ .refresh = 122,
++ .xres = 320, .yres = 240,
++ .pixclock = 80000,
++
++ .left_margin = 10, .right_margin = 20,
++ .upper_margin = 30, .lower_margin = 5,
++ .hsync_len = 20, .vsync_len = 3,
++
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ },
++ {
++ .refresh = 70,
++ .xres = 640, .yres = 480,
++ .pixclock = 40000,
++
++ .left_margin = 10, .right_margin = 20,
++ .upper_margin = 30, .lower_margin = 5,
++ .hsync_len = 20, .vsync_len = 3,
++
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ },
++};
++#else
++static struct fb_videomode samsung_modes[] = {
++ {
++ .refresh = 75,
++ .xres = 320, .yres = 240,
++ .pixclock = 145111,
++
++ .left_margin = 17, .right_margin = 33,
++ .upper_margin = 8, .lower_margin = 10,
++ .hsync_len = 16, .vsync_len = 1,
++
++ .sync = FB_SYNC_PCLK_RISING,
++ .vmode = FB_VMODE_NONINTERLACED,
++ },
++};
++#endif
++
++#if 1
++static struct fb_monspecs default_monspecs = {
++ .modedb = samsung_modes,
++ .manufacturer = "SNG",
++ .monitor = "LCD panel",
++ .serial_no = "xxxx",
++ .ascii = "yyyy",
++ .modedb_len = ARRAY_SIZE(samsung_modes),
++ .hfmin = 14820,
++ .hfmax = 22230,
++ .vfmin = 60,
++ .vfmax = 90,
++ .dclkmax = 30000000,
++};
++#endif
++
++#if 0
++static struct fb_monspecs default_monspecs = {
++ .modedb = sony_modes,
++ .manufacturer = "SNY", /* 4 chars?!? */
++ .monitor = "LCD panel",
++ .serial_no = "xxxx",
++ .ascii = "yyyy",
++ .modedb_len = ARRAY_SIZE(sony_modes),
++ .hfmin = 7000,
++ .hfmax = 8000,
++ .vfmin = 45,
++ .vfmax = 50,
++};
++// #else
++static struct fb_monspecs default_monspecs = {
++ .modedb = vga_modes,
++ .manufacturer = "VGA",
++ .monitor = "Generic VGA",
++ .serial_no = "xxxx",
++ .ascii = "yyyy",
++ .modedb_len = ARRAY_SIZE(vga_modes),
++ .hfmin = 30000,
++ .hfmax = 64000,
++ .vfmin = 50,
++ .vfmax = 150,
++};
++#endif
++
++/* Driver defaults */
++static struct fb_fix_screeninfo sidsafb_fix __devinitdata = {
++ .id = "sidsafb",
++ .type = FB_TYPE_PACKED_PIXELS,
++ .visual = FB_VISUAL_TRUECOLOR,
++ .xpanstep = 1,
++ .ypanstep = 1,
++ .ywrapstep = 0,
++ .accel = FB_ACCEL_NONE,
++};
++
++static void sidsafb_update_dma(struct fb_info *info,
++ struct fb_var_screeninfo *var)
++{
++ struct sidsafb_info *sinfo = info->par;
++ struct fb_fix_screeninfo *fix = &info->fix;
++ unsigned long dma_addr;
++ unsigned long pixeloff;
++ unsigned long dma2dcfg;
++
++ dma_addr = (fix->smem_start + var->yoffset * fix->line_length
++ + var->xoffset * var->bits_per_pixel / 8);
++
++ dma_addr &= ~3UL;
++ pixeloff = LCDC_MKBF(DMA2DCFG_PIXELOFF, var->xoffset * var->bits_per_pixel);
++
++ /* Set framebuffer DMA base address and pixel offset */
++ lcdc_writel(sinfo, DMABADDR1, dma_addr);
++ dma2dcfg = lcdc_readl(sinfo, DMA2DCFG);
++ dma2dcfg = LCDC_INSBF(DMA2DCFG_PIXELOFF, pixeloff, dma2dcfg);
++ lcdc_writel(sinfo, DMA2DCFG, dma2dcfg);
++
++ /* Update configuration */
++ lcdc_writel(sinfo, DMACON, (lcdc_readl(sinfo, DMACON)
++ | LCDC_BIT(DMACON_DMAUPDT)));
++}
++
++/**
++ * sidsafb_check_var - Validates a var passed in.
++ * @var: frame buffer variable screen structure
++ * @info: frame buffer structure that represents a single frame buffer
++ *
++ * Checks to see if the hardware supports the state requested by
++ * var passed in. This function does not alter the hardware
++ * state!!! This means the data stored in struct fb_info and
++ * struct sidsafb_info do not change. This includes the var
++ * inside of struct fb_info. Do NOT change these. This function
++ * can be called on its own if we intent to only test a mode and
++ * not actually set it. The stuff in modedb.c is a example of
++ * this. If the var passed in is slightly off by what the
++ * hardware can support then we alter the var PASSED in to what
++ * we can do. If the hardware doesn't support mode change a
++ * -EINVAL will be returned by the upper layers. You don't need
++ * to implement this function then. If you hardware doesn't
++ * support changing the resolution then this function is not
++ * needed. In this case the driver would just provide a var that
++ * represents the static state the screen is in.
++ *
++ * Returns negative errno on error, or zero on success.
++ */
++static int sidsafb_check_var(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ unsigned long new_fb_size;
++
++ pr_debug("sidsafb_check_var:\n");
++ pr_debug(" resolution: %ux%u\n", var->xres, var->yres);
++ pr_debug(" pixclk: %llu Hz\n", 1000000000000ULL / var->pixclock);
++ pr_debug(" bpp: %u\n", var->bits_per_pixel);
++
++ new_fb_size = (var->xres_virtual * var->yres_virtual
++ * ((var->bits_per_pixel + 7) / 8));
++ if (new_fb_size > info->fix.smem_len) {
++ printk(KERN_NOTICE
++ "sidsafb: %uB framebuffer too small for %ux%ux%u\n",
++ info->fix.smem_len, var->xres_virtual,
++ var->yres_virtual, var->bits_per_pixel);
++ return -EINVAL;
++ }
++
++ /* Force same alignment for each line */
++ var->xres = (var->xres + 3) & ~3UL;
++ var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
++
++ var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
++ var->transp.offset = var->transp.length = 0;
++
++ switch (var->bits_per_pixel) {
++ case 2:
++ case 4:
++ case 8:
++ var->red.offset = var->green.offset = var->blue.offset = 0;
++ var->red.length = var->green.length = var->blue.length
++ = var->bits_per_pixel;
++ break;
++ case 15:
++ case 16:
++ /*
++ * Bit 16 is the "intensity" bit, I think. Not sure
++ * what we're going to use that for...
++ */
++ var->red.offset = 0;
++ var->green.offset = 5;
++ var->blue.offset = 10;
++ var->red.length = 5;
++ var->green.length = 5;
++ var->blue.length = 5;
++ break;
++ case 24:
++ case 32:
++ var->red.offset = 16;
++ var->green.offset = 8;
++ var->blue.offset = 0;
++ var->red.length = var->green.length = var->blue.length = 8;
++ break;
++ default:
++ printk(KERN_NOTICE "sidsafb: color depth %d not supported\n",
++ var->bits_per_pixel);
++ return -EINVAL;
++ }
++
++ var->xoffset = var->yoffset = 0;
++ var->red.msb_right = var->green.msb_right = var->blue.msb_right =
++ var->transp.msb_right = 0;
++
++ return 0;
++}
++
++/**
++ * sidsafb_set_par - Alters the hardware state.
++ * @info: frame buffer structure that represents a single frame buffer
++ *
++ * Using the fb_var_screeninfo in fb_info we set the resolution
++ * of the this particular framebuffer. This function alters the
++ * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
++ * not alter var in fb_info since we are using that data. This
++ * means we depend on the data in var inside fb_info to be
++ * supported by the hardware. sidsafb_check_var is always called
++ * before sidsafb_set_par to ensure this. Again if you can't
++ * change the resolution you don't need this function.
++ *
++ */
++static int sidsafb_set_par(struct fb_info *info)
++{
++ struct sidsafb_info *sinfo = info->par;
++ unsigned long value;
++
++ pr_debug("sidsafb_set_par:\n");
++ pr_debug(" * resolution: %ux%u (%ux%u virtual)\n",
++ info->var.xres, info->var.yres,
++ info->var.xres_virtual, info->var.yres_virtual);
++
++ /* Turn off the LCD controller and the DMA controller */
++ pr_debug("writing 0x%08x to %p\n",
++ LCDC_MKBF(PWRCON_GUARD_TIME, sinfo->guard_time),
++ sinfo->regs + LCDC_PWRCON);
++ lcdc_writel(sinfo, PWRCON,
++ LCDC_MKBF(PWRCON_GUARD_TIME, sinfo->guard_time));
++ pr_debug("writing 0 to %p\n", sinfo->regs + LCDC_DMACON);
++ lcdc_writel(sinfo, DMACON, 0);
++
++ info->fix.line_length = (info->var.xres_virtual
++ * (info->var.bits_per_pixel / 8));
++
++ if (info->var.bits_per_pixel <= 8)
++ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
++ else
++ info->fix.visual = FB_VISUAL_TRUECOLOR;
++
++ /* Re-initialize the DMA engine... */
++ pr_debug(" * update DMA engine\n");
++ sidsafb_update_dma(info, &info->var);
++
++ /* ...set frame size and burst length = 8 words (?) */
++ value = LCDC_MKBF(DMAFRMCFG_FRMSIZE,
++ (info->var.yres * info->fix.line_length + 3) / 4);
++ value |= LCDC_MKBF(DMAFRMCFG_BRSTLEN, (SIDSAFB_DMA_BURST_LEN - 1));
++ lcdc_writel(sinfo, DMAFRMCFG, value);
++
++ /* ...set 2D configuration (necessary for xres_virtual != xres) */
++ value = LCDC_MKBF(DMA2DCFG_ADDRINC,
++ info->var.xres_virtual - info->var.xres);
++ lcdc_writel(sinfo, DMA2DCFG, value);
++
++ /* ...wait for DMA engine to become idle... */
++ while (lcdc_readl(sinfo, DMACON) & LCDC_BIT(DMACON_DMABUSY))
++ msleep(10);
++
++ pr_debug(" * re-enable DMA engine\n");
++ /* ...and enable it with updated configuration */
++ lcdc_writel(sinfo, DMACON, (LCDC_BIT(DMACON_DMAEN)
++ | LCDC_BIT(DMACON_DMAUPDT)
++ | LCDC_BIT(DMACON_DMA2DEN)));
++
++ /* Now, the LCD core... */
++
++ /* Set pixel clock. */
++ value = (clk_get_rate(sinfo->pixclk) / 100000) * info->var.pixclock;
++ value /= 10000000;
++ value = (value + 1) / 2;
++ if (value == 0) {
++ printk("sidsafb: Bypassing lcdc_pclk divider\n");
++ lcdc_writel(sinfo, LCDCON1, LCDC_BIT(LCDCON1_BYPASS));
++ } else {
++ lcdc_writel(sinfo, LCDCON1, LCDC_MKBF(LCDCON1_CLKVAL, value - 1));
++ }
++
++ /* Initialize control register 2 */
++ value = (LCDC_BIT(LCDCON2_CLKMOD)
++ | LCDC_MKBF(LCDCON2_DISTYPE, LCDC_DISTYPE_TFT));
++ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
++ value |= LCDC_BIT(LCDCON2_INVLINE);
++ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
++ value |= LCDC_BIT(LCDCON2_INVFRAME);
++ if (info->var.sync & FB_SYNC_PCLK_RISING)
++ value |= LCDC_BIT(LCDCON2_INVCLK);
++
++ switch (info->var.bits_per_pixel) {
++ case 1: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 0); break;
++ case 2: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 1); break;
++ case 4: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 2); break;
++ case 8: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 3); break;
++ case 15: /* fall through */
++ case 16: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 4); break;
++ case 24: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 5); break;
++ case 32: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 6); break;
++ default: BUG(); break;
++ }
++ pr_debug(" * LCDCON2 = %08lx\n", value);
++ lcdc_writel(sinfo, LCDCON2, value);
++
++ /* Vertical timing */
++ value = LCDC_MKBF(LCDTIM1_VPW, info->var.vsync_len - 1);
++ value |= LCDC_MKBF(LCDTIM1_VBP, info->var.upper_margin);
++ value |= LCDC_MKBF(LCDTIM1_VFP, info->var.lower_margin);
++ pr_debug(" * LCDTIM1 = %08lx\n", value);
++ lcdc_writel(sinfo, LCDTIM1, value);
++
++ /* Horizontal timing */
++ value = LCDC_MKBF(LCDTIM2_HFP, info->var.right_margin - 1);
++ value |= LCDC_MKBF(LCDTIM2_HPW, info->var.hsync_len - 1);
++ value |= LCDC_MKBF(LCDTIM2_HBP, info->var.left_margin - 1);
++ pr_debug(" * LCDTIM2 = %08lx\n", value);
++ lcdc_writel(sinfo, LCDTIM2, value);
++
++ /* Display size */
++ value = LCDC_MKBF(LCDFRMCFG_LINESIZE, info->var.xres - 1);
++ value |= LCDC_MKBF(LCDFRMCFG_LINEVAL, info->var.yres - 1);
++ lcdc_writel(sinfo, LCDFRMCFG, value);
++
++ /* FIFO Threshold: Use formula from data sheet */
++ value = SIDSAFB_FIFO_SIZE - (2 * SIDSAFB_DMA_BURST_LEN + 3);
++ lcdc_writel(sinfo, LCDFIFO, value);
++
++ /* Toggle LCD_MODE every frame */
++ lcdc_writel(sinfo, LCDMVAL, 0);
++
++ /* Disable all interrupts */
++ lcdc_writel(sinfo, LCD_IDR, ~0UL);
++
++ /* Wait for the LCDC core to become idle and enable it */
++ while(lcdc_readl(sinfo, PWRCON) & LCDC_BIT(PWRCON_LCD_BUSY))
++ msleep(10);
++
++ pr_debug(" * re-enable LCD core\n");
++ lcdc_writel(sinfo, PWRCON,
++ LCDC_MKBF(PWRCON_GUARD_TIME, sinfo->guard_time)
++ | LCDC_BIT(PWRCON_LCD_PWR));
++
++ pr_debug(" * DONE\n");
++ return 0;
++}
++
++static inline u_int chan_to_field(u_int chan, const struct fb_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++/**
++ * sidsafb_setcolreg - Optional function. Sets a color register.
++ * @regno: Which register in the CLUT we are programming
++ * @red: The red value which can be up to 16 bits wide
++ * @green: The green value which can be up to 16 bits wide
++ * @blue: The blue value which can be up to 16 bits wide.
++ * @transp: If supported the alpha value which can be up to 16 bits wide.
++ * @info: frame buffer info structure
++ *
++ * Set a single color register. The values supplied have a 16 bit
++ * magnitude which needs to be scaled in this function for the hardware.
++ * Things to take into consideration are how many color registers, if
++ * any, are supported with the current color visual. With truecolor mode
++ * no color palettes are supported. Here a psuedo palette is created
++ * which we store the value in pseudo_palette in struct fb_info. For
++ * pseudocolor mode we have a limited color palette. To deal with this
++ * we can program what color is displayed for a particular pixel value.
++ * DirectColor is similar in that we can program each color field. If
++ * we have a static colormap we don't need to implement this function.
++ *
++ * Returns negative errno on error, or zero on success. In an
++ * ideal world, this would have been the case, but as it turns
++ * out, the other drivers return 1 on failure, so that's what
++ * we're going to do.
++ */
++static int sidsafb_setcolreg(unsigned int regno, unsigned int red,
++ unsigned int green, unsigned int blue,
++ unsigned int transp, struct fb_info *info)
++{
++ struct sidsafb_info *sinfo = info->par;
++ unsigned int val;
++ u32 *pal;
++ int ret = 1;
++
++ if (info->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green
++ + 7471 * blue) >> 16;
++
++ switch (info->fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ if (regno < 16) {
++ pal = info->pseudo_palette;
++
++ val = chan_to_field(red, &info->var.red);
++ val |= chan_to_field(green, &info->var.green);
++ val |= chan_to_field(blue, &info->var.blue);
++
++ pal[regno] = val;
++ ret = 0;
++ }
++ break;
++
++ case FB_VISUAL_PSEUDOCOLOR:
++ if (regno < 256) {
++ val = ((red >> 11) & 0x001f);
++ val |= ((green >> 6) & 0x03e0);
++ val |= ((blue >> 1) & 0x7c00);
++
++ /*
++ * TODO: intensity bit. Maybe something like
++ * ~(red[10] ^ green[10] ^ blue[10]) & 1
++ */
++
++ lcdc_writel(sinfo, LUT + regno * 4, val);
++ ret = 0;
++ }
++ break;
++ }
++
++ return ret;
++}
++
++static int sidsafb_pan_display(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ pr_debug("sidsafb_pan_display\n");
++
++ sidsafb_update_dma(info, var);
++
++ return 0;
++}
++
++static struct fb_ops sidsafb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = sidsafb_check_var,
++ .fb_set_par = sidsafb_set_par,
++ .fb_setcolreg = sidsafb_setcolreg,
++ .fb_pan_display = sidsafb_pan_display,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++};
++
++static irqreturn_t sidsafb_interrupt(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct fb_info *info = dev_id;
++ struct sidsafb_info *sinfo = info->par;
++ u32 status;
++
++ status = lcdc_readl(sinfo, LCD_ISR);
++ while (status) {
++ if (status & LCDC_BIT(LCD_ISR_EOFIS)) {
++ pr_debug("sidsafb: DMA End Of Frame interrupt\n");
++
++ lcdc_writel(sinfo, LCD_ICR, LCDC_BIT(LCD_ICR_EOFIC));
++ status &= ~LCDC_BIT(LCD_ISR_EOFIS);
++ wake_up(&sinfo->vsync_wait);
++ }
++
++ if (status) {
++ printk(KERN_ERR
++ "LCDC: Interrupts still pending: 0x%x\n",
++ status);
++ lcdc_writel(sinfo, LCD_IDR, status);
++ }
++
++ status = lcdc_readl(sinfo, LCD_ISR);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static void __devinit init_pseudo_palette(u32 *palette)
++{
++ static const u32 init_palette[16] = {
++ 0x000000,
++ 0xaa0000,
++ 0x00aa00,
++ 0xaa5500,
++ 0x0000aa,
++ 0xaa00aa,
++ 0x00aaaa,
++ 0xaaaaaa,
++ 0x555555,
++ 0xff5555,
++ 0x55ff55,
++ 0xffff55,
++ 0x5555ff,
++ 0xff55ff,
++ 0x55ffff,
++ 0xffffff
++ };
++
++ memcpy(palette, init_palette, sizeof(init_palette));
++}
++
++static int __devinit sidsafb_set_fbinfo(struct sidsafb_info *sinfo)
++{
++ struct fb_info *info = sinfo->info;
++
++ init_pseudo_palette(sinfo->pseudo_palette);
++
++ info->flags = (FBINFO_DEFAULT
++ | FBINFO_PARTIAL_PAN_OK
++ | FBINFO_HWACCEL_XPAN
++ | FBINFO_HWACCEL_YPAN);
++ memcpy(&info->fix, &sidsafb_fix, sizeof(info->fix));
++ memcpy(&info->monspecs, &default_monspecs, sizeof(info->monspecs));
++ info->fbops = &sidsafb_ops;
++ info->pseudo_palette = sinfo->pseudo_palette;
++
++ init_waitqueue_head(&sinfo->vsync_wait);
++
++ return 0;
++}
++
++static int __devinit sidsafb_probe(struct platform_device *pdev)
++{
++ struct lcdc_platform_data *fb_data = pdev->dev.platform_data;
++ struct fb_info *info;
++ struct sidsafb_info *sinfo;
++ const struct resource *mmio_resource;
++ int ret;
++
++ pr_debug("sidsafb_probe BEGIN\n");
++
++ mmio_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!mmio_resource) {
++ dev_err(&pdev->dev, "no MMIO resource found\n");
++ return -ENXIO;
++ }
++
++ ret = -ENOMEM;
++ info = framebuffer_alloc(sizeof(struct sidsafb_info), &pdev->dev);
++ if (!info) {
++ dev_err(&pdev->dev, "failed to allocate memory\n");
++ goto out;
++ }
++
++ sinfo = info->par;
++ sinfo->info = info;
++ sinfo->pdev = pdev;
++ sinfo->guard_time = 1;
++
++ spin_lock_init(&sinfo->lock);
++ sidsafb_set_fbinfo(sinfo);
++ info->fix.mmio_start = mmio_resource->start;
++ info->fix.mmio_len = mmio_resource->end - mmio_resource->start + 1;
++ sinfo->irq_base = platform_get_irq(pdev, 0);
++
++ sinfo->hclk = clk_get(&pdev->dev, "hclk");
++ if (IS_ERR(sinfo->hclk)) {
++ dev_err(&pdev->dev, "failed to get hclk\n");
++ ret = PTR_ERR(sinfo->hclk);
++ goto free_info;
++ }
++ sinfo->pixclk = clk_get(&pdev->dev, "pixclk");
++ if (IS_ERR(sinfo->pixclk)) {
++ dev_err(&pdev->dev, "failed to get pixel clock\n");
++ ret = PTR_ERR(sinfo->hclk);
++ goto put_hclk;
++ }
++
++ clk_enable(sinfo->hclk);
++ clk_enable(sinfo->pixclk);
++
++ /* Use platform-supplied framebuffer memory if available */
++ if (fb_data && fb_data->fbmem_size != 0) {
++ info->fix.smem_start = fb_data->fbmem_start;
++ info->fix.smem_len = fb_data->fbmem_size;
++ info->screen_base = ioremap(info->fix.smem_start,
++ info->fix.smem_len);
++ } else {
++ dma_addr_t paddr;
++
++ info->fix.smem_len = fb_size;
++ info->screen_base = dma_alloc_coherent(&pdev->dev, fb_size,
++ &paddr, GFP_KERNEL);
++ info->fix.smem_start = paddr;
++ }
++
++ if (!info->screen_base) {
++ printk(KERN_ERR "sidsafb: Could not allocate framebuffer\n");
++ goto disable_clocks;
++ }
++
++ sinfo->regs = ioremap(info->fix.mmio_start, info->fix.mmio_len);
++ if (!sinfo->regs) {
++ printk(KERN_ERR "sidsafb: Could not map LCDC registers\n");
++ goto free_fb;
++ }
++
++ ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
++ info->monspecs.modedb_len, info->monspecs.modedb,
++ CONFIG_FB_SIDSA_DEFAULT_BPP);
++ if (!ret) {
++ printk(KERN_ERR "sidsafb: No suitable video mode found\n");
++ goto unmap_regs;
++ }
++
++ ret = request_irq(sinfo->irq_base, sidsafb_interrupt, 0,
++ "sidsafb", info);
++ if (ret)
++ goto unmap_regs;
++
++ /* Allocate colormap */
++ if (fb_alloc_cmap(&info->cmap, 256, 0)) {
++ ret = -ENOMEM;
++ goto unregister_irqs;
++ }
++
++ /*
++ * Tell the world that we're ready to go
++ */
++ ret = register_framebuffer(info);
++ if (ret)
++ goto free_cmap;
++
++ printk("fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n",
++ info->node, info->fix.mmio_start, sinfo->regs, sinfo->irq_base);
++
++ platform_set_drvdata(pdev, info);
++
++ memset_io(info->screen_base, 0, info->fix.smem_len);
++ info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
++ ret = fb_set_var(info, &info->var);
++ if (ret)
++ printk(KERN_WARNING
++ "sidsafb: Unable to set display parameters\n");
++ info->var.activate &= ~(FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW);
++
++ pr_debug("sidsafb_probe SUCCESS\n");
++ return 0;
++
++
++free_cmap:
++ fb_dealloc_cmap(&info->cmap);
++unregister_irqs:
++ free_irq(sinfo->irq_base, info);
++unmap_regs:
++ iounmap(sinfo->regs);
++free_fb:
++ if (!fb_data || fb_data->fbmem_size == 0)
++ dma_free_coherent(&pdev->dev, info->fix.smem_len,
++ (void __force *)info->screen_base,
++ info->fix.smem_start);
++disable_clocks:
++ clk_disable(sinfo->pixclk);
++ clk_disable(sinfo->hclk);
++ clk_put(sinfo->pixclk);
++put_hclk:
++ clk_put(sinfo->hclk);
++free_info:
++ framebuffer_release(info);
++out:
++ pr_debug("sidsafb_probe FAILED\n");
++ return ret;
++}
++
++static int __devexit sidsafb_remove(struct platform_device *pdev)
++{
++ struct lcdc_platform_data *fb_data = pdev->dev.platform_data;
++ struct fb_info *info = platform_get_drvdata(pdev);
++ struct sidsafb_info *sinfo;
++
++ if (!info)
++ return 0;
++ sinfo = info->par;
++
++ /* TODO: Restore original state */
++ unregister_framebuffer(info);
++
++ fb_dealloc_cmap(&info->cmap);
++ free_irq(sinfo->irq_base, info);
++ iounmap(sinfo->regs);
++ if (!fb_data || fb_data->fbmem_size == 0)
++ dma_free_coherent(&pdev->dev, info->fix.smem_len,
++ (void __force *)info->screen_base,
++ info->fix.smem_start);
++ clk_disable(sinfo->hclk);
++ clk_put(sinfo->hclk);
++ platform_set_drvdata(pdev, NULL);
++ framebuffer_release(info);
++
++ return 0;
++}
++
++static struct platform_driver sidsafb_driver = {
++ .probe = sidsafb_probe,
++ .remove = __devexit_p(sidsafb_remove),
++ .driver = {
++ .name = "lcdc",
++ },
++};
++
++int __init sidsafb_init(void)
++{
++ return platform_driver_register(&sidsafb_driver);
++}
++
++static void __exit sidsafb_exit(void)
++{
++ platform_driver_unregister(&sidsafb_driver);
++}
++
++module_init(sidsafb_init);
++module_exit(sidsafb_exit);
++
++module_param(fb_size, ulong, 0644);
++MODULE_PARM_DESC(fb_size, "Minimum framebuffer size to allocate");
++
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_DESCRIPTION("Atmel/SIDSA LCD Controller framebuffer driver");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.18-avr32/include/asm-avr32/periph/lcdc.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/include/asm-avr32/periph/lcdc.h 2006-11-02 16:08:35.000000000 +0100
+@@ -0,0 +1,271 @@
++/*
++ * Register definitions for Atmel/SIDSA LCD Controller
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ASM_AVR32_PERIPH_LCDC_H__
++#define __ASM_AVR32_PERIPH_LCDC_H__
++
++#define LCDC_CONTRAST_CTR 0x00000840
++# define LCDC_CONTRAST_CTR_ENA_OFFSET 3
++# define LCDC_CONTRAST_CTR_ENA_SIZE 1
++# define LCDC_CONTRAST_CTR_POL_OFFSET 2
++# define LCDC_CONTRAST_CTR_POL_SIZE 1
++# define LCDC_CONTRAST_CTR_PS_OFFSET 0
++# define LCDC_CONTRAST_CTR_PS_SIZE 2
++#define LCDC_CONTRAST_VAL 0x00000844
++# define LCDC_CONTRAST_VAL_CVAL_OFFSET 0
++# define LCDC_CONTRAST_VAL_CVAL_SIZE 8
++#define LCDC_DMABADDR1 0x00000000
++# define LCDC_DMABADDR1_BADDR_U_OFFSET 0
++# define LCDC_DMABADDR1_BADDR_U_SIZE 32
++#define LCDC_DMABADDR2 0x00000004
++# define LCDC_DMABADDR2_BADDR_L_OFFSET 0
++# define LCDC_DMABADDR2_BADDR_L_SIZE 32
++#define LCDC_DMACON 0x0000001C
++# define LCDC_DMACON_DMABUSY_OFFSET 2
++# define LCDC_DMACON_DMABUSY_SIZE 1
++# define LCDC_DMACON_DMAEN_OFFSET 0
++# define LCDC_DMACON_DMAEN_SIZE 1
++# define LCDC_DMACON_DMARST_OFFSET 1
++# define LCDC_DMACON_DMARST_SIZE 1
++# define LCDC_DMACON_DMAUPDT_OFFSET 3
++# define LCDC_DMACON_DMAUPDT_SIZE 1
++# define LCDC_DMACON_DMA2DEN_OFFSET 4
++# define LCDC_DMACON_DMA2DEN_SIZE 1
++#define LCDC_DMAFRMADD1 0x00000010
++# define LCDC_DMAFRMADD1_FRMADD_U_OFFSET 0
++# define LCDC_DMAFRMADD1_FRMADD_U_SIZE 32
++#define LCDC_DMAFRMADD2 0x00000014
++# define LCDC_DMAFRMADD2_FRMADD_L_OFFSET 0
++# define LCDC_DMAFRMADD2_FRMADD_L_SIZE 32
++#define LCDC_DMAFRMCFG 0x00000018
++# define LCDC_DMAFRMCFG_BRSTLEN_OFFSET 24
++# define LCDC_DMAFRMCFG_BRSTLEN_SIZE 7
++# define LCDC_DMAFRMCFG_FRMSIZE_OFFSET 0
++# define LCDC_DMAFRMCFG_FRMSIZE_SIZE 23
++#define LCDC_DMAFRMPT1 0x00000008
++# define LCDC_DMAFRMPT1_FRMPT_U_OFFSET 0
++# define LCDC_DMAFRMPT1_FRMPT_U_SIZE 23
++#define LCDC_DMAFRMPT2 0x0000000C
++# define LCDC_DMAFRMPT2_FRMPT_L_OFFSET 0
++# define LCDC_DMAFRMPT2_FRMPT_L_SIZE 23
++#define LCDC_DMA2DCFG 0x00000020
++# define LCDC_DMA2DCFG_ADDRINC_OFFSET 0
++# define LCDC_DMA2DCFG_ADDRINC_SIZE 16
++# define LCDC_DMA2DCFG_PIXELOFF_OFFSET 24
++# define LCDC_DMA2DCFG_PIXELOFF_SIZE 5
++#define LCDC_DP1_2 0x0000081C
++# define LCDC_DP1_2_DP1_2_OFFSET 0
++# define LCDC_DP1_2_DP1_2_SIZE 8
++#define LCDC_DP2_3 0x00000828
++# define LCDC_DP2_3_DP2_3_OFFSET 0
++# define LCDC_DP2_3_DP2_3_SIZE 12
++#define LCDC_DP3_4 0x00000830
++# define LCDC_DP3_4_DP3_4_OFFSET 0
++# define LCDC_DP3_4_DP3_4_SIZE 16
++#define LCDC_DP3_5 0x00000824
++# define LCDC_DP3_5_DP3_5_OFFSET 0
++# define LCDC_DP3_5_DP3_5_SIZE 20
++#define LCDC_DP4_5 0x00000834
++# define LCDC_DP4_5_DP4_5_OFFSET 0
++# define LCDC_DP4_5_DP4_5_SIZE 20
++#define LCDC_DP4_7 0x00000820
++# define LCDC_DP4_7_DP4_7_OFFSET 0
++# define LCDC_DP4_7_DP4_7_SIZE 28
++#define LCDC_DP5_7 0x0000082C
++# define LCDC_DP5_7_DP5_7_OFFSET 0
++# define LCDC_DP5_7_DP5_7_SIZE 28
++#define LCDC_DP6_7 0x00000838
++# define LCDC_DP6_7_DP6_7_OFFSET 0
++# define LCDC_DP6_7_DP6_7_SIZE 28
++#define LCDC_LCDCON1 0x00000800
++# define LCDC_LCDCON1_BYPASS_OFFSET 0
++# define LCDC_LCDCON1_BYPASS_SIZE 1
++# define LCDC_LCDCON1_CLKVAL_OFFSET 12
++# define LCDC_LCDCON1_CLKVAL_SIZE 9
++# define LCDC_LCDCON1_LINECNT_OFFSET 21
++# define LCDC_LCDCON1_LINECNT_SIZE 11
++#define LCDC_LCDCON2 0x00000804
++# define LCDC_LCDCON2_CLKMOD_OFFSET 15
++# define LCDC_LCDCON2_CLKMOD_SIZE 1
++# define LCDC_LCDCON2_DISTYPE_OFFSET 0
++# define LCDC_LCDCON2_DISTYPE_SIZE 2
++# define LCDC_LCDCON2_IFWIDTH_OFFSET 3
++# define LCDC_LCDCON2_IFWIDTH_SIZE 2
++# define LCDC_LCDCON2_INVCLK_OFFSET 11
++# define LCDC_LCDCON2_INVCLK_SIZE 1
++# define LCDC_LCDCON2_INVDVAL_OFFSET 12
++# define LCDC_LCDCON2_INVDVAL_SIZE 1
++# define LCDC_LCDCON2_INVFRAME_OFFSET 9
++# define LCDC_LCDCON2_INVFRAME_SIZE 1
++# define LCDC_LCDCON2_INVLINE_OFFSET 10
++# define LCDC_LCDCON2_INVLINE_SIZE 1
++# define LCDC_LCDCON2_INVVD_OFFSET 8
++# define LCDC_LCDCON2_INVVD_SIZE 1
++# define LCDC_LCDCON2_MEMOR_OFFSET 30
++# define LCDC_LCDCON2_MEMOR_SIZE 2
++# define LCDC_LCDCON2_PIXELSIZE_OFFSET 5
++# define LCDC_LCDCON2_PIXELSIZE_SIZE 3
++# define LCDC_LCDCON2_SCANMOD_OFFSET 2
++# define LCDC_LCDCON2_SCANMOD_SIZE 1
++#define LCDC_LCDFIFO 0x00000814
++# define LCDC_LCDFIFO_FIFOTH_OFFSET 0
++# define LCDC_LCDFIFO_FIFOTH_SIZE 16
++#define LCDC_LCDFRMCFG 0x00000810
++# define LCDC_LCDFRMCFG_LINESIZE_OFFSET 21
++# define LCDC_LCDFRMCFG_LINESIZE_SIZE 11
++# define LCDC_LCDFRMCFG_LINEVAL_OFFSET 0
++# define LCDC_LCDFRMCFG_LINEVAL_SIZE 11
++#define LCDC_LCDMVAL 0x00000818
++# define LCDC_LCDMVAL_MMODE_OFFSET 31
++# define LCDC_LCDMVAL_MMODE_SIZE 1
++# define LCDC_LCDMVAL_MVAL_OFFSET 0
++# define LCDC_LCDMVAL_MVAL_SIZE 8
++#define LCDC_LCDTIM1 0x00000808
++# define LCDC_LCDTIM1_VBP_OFFSET 8
++# define LCDC_LCDTIM1_VBP_SIZE 8
++# define LCDC_LCDTIM1_VFP_OFFSET 0
++# define LCDC_LCDTIM1_VFP_SIZE 8
++# define LCDC_LCDTIM1_VHDLY_OFFSET 24
++# define LCDC_LCDTIM1_VHDLY_SIZE 4
++# define LCDC_LCDTIM1_VPW_OFFSET 16
++# define LCDC_LCDTIM1_VPW_SIZE 6
++#define LCDC_LCDTIM2 0x0000080C
++# define LCDC_LCDTIM2_HBP_OFFSET 0
++# define LCDC_LCDTIM2_HBP_SIZE 8
++# define LCDC_LCDTIM2_HFP_OFFSET 21
++# define LCDC_LCDTIM2_HFP_SIZE 11
++# define LCDC_LCDTIM2_HPW_OFFSET 8
++# define LCDC_LCDTIM2_HPW_SIZE 6
++#define LCDC_LCD_GPR 0x0000085C
++# define LCDC_LCD_GPR_GPRB0_OFFSET 0
++# define LCDC_LCD_GPR_GPRB0_SIZE 1
++# define LCDC_LCD_GPR_GPRB1_OFFSET 1
++# define LCDC_LCD_GPR_GPRB1_SIZE 1
++# define LCDC_LCD_GPR_GPRB2_OFFSET 2
++# define LCDC_LCD_GPR_GPRB2_SIZE 1
++# define LCDC_LCD_GPR_GPRB3_OFFSET 3
++# define LCDC_LCD_GPR_GPRB3_SIZE 1
++# define LCDC_LCD_GPR_GPRB4_OFFSET 4
++# define LCDC_LCD_GPR_GPRB4_SIZE 1
++# define LCDC_LCD_GPR_GPRB5_OFFSET 5
++# define LCDC_LCD_GPR_GPRB5_SIZE 1
++# define LCDC_LCD_GPR_GPRB6_OFFSET 6
++# define LCDC_LCD_GPR_GPRB6_SIZE 1
++# define LCDC_LCD_GPR_GPRB7_OFFSET 7
++# define LCDC_LCD_GPR_GPRB7_SIZE 1
++#define LCDC_LCD_ICR 0x00000858
++# define LCDC_LCD_ICR_EOFIC_OFFSET 2
++# define LCDC_LCD_ICR_EOFIC_SIZE 1
++# define LCDC_LCD_ICR_LNIC_OFFSET 0
++# define LCDC_LCD_ICR_LNIC_SIZE 1
++# define LCDC_LCD_ICR_LSTLNIC_OFFSET 1
++# define LCDC_LCD_ICR_LSTLNIC_SIZE 1
++# define LCDC_LCD_ICR_MERIC_OFFSET 6
++# define LCDC_LCD_ICR_MERIC_SIZE 1
++# define LCDC_LCD_ICR_OWRIC_OFFSET 5
++# define LCDC_LCD_ICR_OWRIC_SIZE 1
++# define LCDC_LCD_ICR_UFLWIC_OFFSET 4
++# define LCDC_LCD_ICR_UFLWIC_SIZE 1
++#define LCDC_LCD_IDR 0x0000084C
++# define LCDC_LCD_IDR_EOFID_OFFSET 2
++# define LCDC_LCD_IDR_EOFID_SIZE 1
++# define LCDC_LCD_IDR_LNID_OFFSET 0
++# define LCDC_LCD_IDR_LNID_SIZE 1
++# define LCDC_LCD_IDR_LSTLNID_OFFSET 1
++# define LCDC_LCD_IDR_LSTLNID_SIZE 1
++# define LCDC_LCD_IDR_MERID_OFFSET 6
++# define LCDC_LCD_IDR_MERID_SIZE 1
++# define LCDC_LCD_IDR_OWRID_OFFSET 5
++# define LCDC_LCD_IDR_OWRID_SIZE 1
++# define LCDC_LCD_IDR_UFLWID_OFFSET 4
++# define LCDC_LCD_IDR_UFLWID_SIZE 1
++#define LCDC_LCD_IER 0x00000848
++# define LCDC_LCD_IER_EOFIE_OFFSET 2
++# define LCDC_LCD_IER_EOFIE_SIZE 1
++# define LCDC_LCD_IER_LNIE_OFFSET 0
++# define LCDC_LCD_IER_LNIE_SIZE 1
++# define LCDC_LCD_IER_LSTLNIE_OFFSET 1
++# define LCDC_LCD_IER_LSTLNIE_SIZE 1
++# define LCDC_LCD_IER_MERIE_OFFSET 6
++# define LCDC_LCD_IER_MERIE_SIZE 1
++# define LCDC_LCD_IER_OWRIE_OFFSET 5
++# define LCDC_LCD_IER_OWRIE_SIZE 1
++# define LCDC_LCD_IER_UFLWIE_OFFSET 4
++# define LCDC_LCD_IER_UFLWIE_SIZE 1
++#define LCDC_LCD_IMR 0x00000850
++# define LCDC_LCD_IMR_EOFIM_OFFSET 2
++# define LCDC_LCD_IMR_EOFIM_SIZE 1
++# define LCDC_LCD_IMR_LNIM_OFFSET 0
++# define LCDC_LCD_IMR_LNIM_SIZE 1
++# define LCDC_LCD_IMR_LSTLNIM_OFFSET 1
++# define LCDC_LCD_IMR_LSTLNIM_SIZE 1
++# define LCDC_LCD_IMR_MERIM_OFFSET 6
++# define LCDC_LCD_IMR_MERIM_SIZE 1
++# define LCDC_LCD_IMR_OWRIM_OFFSET 5
++# define LCDC_LCD_IMR_OWRIM_SIZE 1
++# define LCDC_LCD_IMR_UFLWIM_OFFSET 4
++# define LCDC_LCD_IMR_UFLWIM_SIZE 1
++#define LCDC_LCD_IRR 0x00000864
++# define LCDC_LCD_IRR_EOFIR_OFFSET 2
++# define LCDC_LCD_IRR_EOFIR_SIZE 1
++# define LCDC_LCD_IRR_LNIR_OFFSET 0
++# define LCDC_LCD_IRR_LNIR_SIZE 1
++# define LCDC_LCD_IRR_LSTLNIR_OFFSET 1
++# define LCDC_LCD_IRR_LSTLNIR_SIZE 1
++# define LCDC_LCD_IRR_MERIR_OFFSET 6
++# define LCDC_LCD_IRR_MERIR_SIZE 1
++# define LCDC_LCD_IRR_OWRIR_OFFSET 5
++# define LCDC_LCD_IRR_OWRIR_SIZE 1
++# define LCDC_LCD_IRR_UFLWIR_OFFSET 4
++# define LCDC_LCD_IRR_UFLWIR_SIZE 1
++#define LCDC_LCD_ISR 0x00000854
++# define LCDC_LCD_ISR_EOFIS_OFFSET 2
++# define LCDC_LCD_ISR_EOFIS_SIZE 1
++# define LCDC_LCD_ISR_LNIS_OFFSET 0
++# define LCDC_LCD_ISR_LNIS_SIZE 1
++# define LCDC_LCD_ISR_LSTLNIS_OFFSET 1
++# define LCDC_LCD_ISR_LSTLNIS_SIZE 1
++# define LCDC_LCD_ISR_MERIS_OFFSET 6
++# define LCDC_LCD_ISR_MERIS_SIZE 1
++# define LCDC_LCD_ISR_OWRIS_OFFSET 5
++# define LCDC_LCD_ISR_OWRIS_SIZE 1
++# define LCDC_LCD_ISR_UFLWIS_OFFSET 4
++# define LCDC_LCD_ISR_UFLWIS_SIZE 1
++#define LCDC_LCD_ITR 0x00000860
++# define LCDC_LCD_ITR_EOFIT_OFFSET 2
++# define LCDC_LCD_ITR_EOFIT_SIZE 1
++# define LCDC_LCD_ITR_LNIT_OFFSET 0
++# define LCDC_LCD_ITR_LNIT_SIZE 1
++# define LCDC_LCD_ITR_LSTLNIT_OFFSET 1
++# define LCDC_LCD_ITR_LSTLNIT_SIZE 1
++# define LCDC_LCD_ITR_MERIT_OFFSET 6
++# define LCDC_LCD_ITR_MERIT_SIZE 1
++# define LCDC_LCD_ITR_OWRIT_OFFSET 5
++# define LCDC_LCD_ITR_OWRIT_SIZE 1
++# define LCDC_LCD_ITR_UFLWIT_OFFSET 4
++# define LCDC_LCD_ITR_UFLWIT_SIZE 1
++#define LCDC_PWRCON 0x0000083C
++# define LCDC_PWRCON_GUARD_TIME_OFFSET 1
++# define LCDC_PWRCON_GUARD_TIME_SIZE 7
++# define LCDC_PWRCON_LCD_BUSY_OFFSET 31
++# define LCDC_PWRCON_LCD_BUSY_SIZE 1
++# define LCDC_PWRCON_LCD_PWR_OFFSET 0
++# define LCDC_PWRCON_LCD_PWR_SIZE 1
++
++#define LCDC_BIT(name) (1 << LCDC_##name##_OFFSET)
++#define LCDC_MKBF(name,value) (((value) & ((1 << LCDC_##name##_SIZE) - 1)) << LCDC_##name##_OFFSET)
++#define LCDC_GETBF(name,value) (((value) >> LCDC_##name##_OFFSET) & ((1 << LCDC_##name##_SIZE) - 1))
++#define LCDC_INSBF(name,value,old) (((old) & ~(((1 << LCDC_##name##_SIZE) - 1) << LCDC_##name##_OFFSET)) | LCDC_MKBF(name, value))
++
++#define lcdc_readl(port,reg) \
++ __raw_readl((port)->regs + LCDC_##reg)
++#define lcdc_writel(port,reg,value) \
++ __raw_writel((value), (port)->regs + LCDC_##reg)
++
++#endif /* __ASM_AVR32_PERIPH_LCDC_H__ */
+Index: linux-2.6.18-avr32/include/linux/fb.h
+===================================================================
+--- linux-2.6.18-avr32.orig/include/linux/fb.h 2006-11-02 15:54:18.000000000 +0100
++++ linux-2.6.18-avr32/include/linux/fb.h 2006-11-02 15:56:20.000000000 +0100
+@@ -191,6 +191,7 @@ struct fb_bitfield {
+ /* vtotal = 144d/288n/576i => PAL */
+ /* vtotal = 121d/242n/484i => NTSC */
+ #define FB_SYNC_ON_GREEN 32 /* sync on green */
++#define FB_SYNC_PCLK_RISING 64 /* pixel data sampled on rising pclk */
+
+ #define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+ #define FB_VMODE_INTERLACED 1 /* interlaced */
+@@ -825,7 +826,7 @@ struct fb_info {
+ #define fb_writeq sbus_writeq
+ #define fb_memset sbus_memset_io
+
+-#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || (defined(__sh__) && !defined(__SH5__)) || defined(__powerpc__)
++#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || (defined(__sh__) && !defined(__SH5__)) || defined(__powerpc__) || defined(__avr32__)
+
+ #define fb_readb __raw_readb
+ #define fb_readw __raw_readw
diff --git a/packages/linux/linux-2.6.18/atmel-macb-ethernet-driver.patch b/packages/linux/linux-2.6.18/atmel-macb-ethernet-driver.patch
new file mode 100644
index 0000000000..e8c54e141b
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-macb-ethernet-driver.patch
@@ -0,0 +1,1614 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu, 29 Jun 2006 15:02:49 +0200
+Subject: [PATCH] Atmel MACB ethernet driver
+
+This is a network device driver for the Atmel MACB interface, which
+is present on the AT32AP7000 device from Atmel. I think it's basically
+the same as the EMAC interface on AT91, so it should possibly be
+merged with the at91_ether driver some time in the future. At the
+moment, however, the at91_ether driver has quite a lot of at91-
+specific dependencies so it's hard to reuse on AVR32.
+
+This is basically the same patch as the one distributed with the
+AT32STK1000 BSP version 1.0, converted to use platform_device and
+struct clk instead of at32_device.
+
+---
+ drivers/net/Kconfig | 11
+ drivers/net/Makefile | 2
+ drivers/net/macb.c | 1159 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/net/macb.h | 387 +++++++++++++++++
+ 4 files changed, 1559 insertions(+)
+
+Index: linux-2.6.18-avr32/drivers/net/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/net/Kconfig 2006-11-02 14:16:07.000000000 +0100
++++ linux-2.6.18-avr32/drivers/net/Kconfig 2006-11-02 14:17:29.000000000 +0100
+@@ -185,6 +185,17 @@ config MII
+ or internal device. It is safe to say Y or M here even if your
+ ethernet card lack MII.
+
++config MACB
++ tristate "Atmel MACB support"
++ depends on NET_ETHERNET && AVR32
++ select MII
++ help
++ The Atmel MACB ethernet interface is found on many AT32 and AT91
++ parts. Say Y to include support for the MACB chip.
++
++ To compile this driver as a module, choose M here: the module
++ will be called macb.
++
+ source "drivers/net/arm/Kconfig"
+
+ config MACE
+Index: linux-2.6.18-avr32/drivers/net/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/net/Makefile 2006-11-02 14:16:07.000000000 +0100
++++ linux-2.6.18-avr32/drivers/net/Makefile 2006-11-02 14:17:29.000000000 +0100
+@@ -202,6 +202,8 @@ obj-$(CONFIG_SMC911X) += smc911x.o
+ obj-$(CONFIG_DM9000) += dm9000.o
+ obj-$(CONFIG_FEC_8XX) += fec_8xx/
+
++obj-$(CONFIG_MACB) += macb.o
++
+ obj-$(CONFIG_ARM) += arm/
+ obj-$(CONFIG_DEV_APPLETALK) += appletalk/
+ obj-$(CONFIG_TR) += tokenring/
+Index: linux-2.6.18-avr32/drivers/net/macb.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/net/macb.c 2006-11-02 16:33:48.000000000 +0100
+@@ -0,0 +1,1159 @@
++/*
++ * Atmel MACB Ethernet Controller driver
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/mii.h>
++#include <linux/mutex.h>
++#include <linux/dma-mapping.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/board.h>
++
++#include "macb.h"
++
++#define to_net_dev(class) container_of(class, struct net_device, class_dev)
++
++#define RX_BUFFER_SIZE 128
++#define RX_RING_SIZE 512
++#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
++
++/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
++#define RX_OFFSET 2
++
++#define TX_RING_SIZE 128
++#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
++#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
++
++#define TX_RING_GAP(bp) \
++ (TX_RING_SIZE - (bp)->tx_pending)
++#define TX_BUFFS_AVAIL(bp) \
++ (((bp)->tx_tail <= (bp)->tx_head) ? \
++ (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
++ (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
++#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
++
++#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
++
++/* minimum number of free TX descriptors before waking up TX process */
++#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
++
++#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
++ | MACB_BIT(ISR_ROVR))
++
++static void __macb_set_hwaddr(struct macb *bp)
++{
++ u32 bottom;
++ u16 top;
++
++ bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
++ macb_writel(bp, SA1B, bottom);
++ top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
++ macb_writel(bp, SA1T, top);
++}
++
++static void macb_enable_mdio(struct macb *bp)
++{
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&bp->lock, flags);
++ reg = macb_readl(bp, NCR);
++ reg |= MACB_BIT(MPE);
++ macb_writel(bp, NCR, reg);
++ macb_writel(bp, IER, MACB_BIT(MFD));
++ spin_unlock_irqrestore(&bp->lock, flags);
++}
++
++static void macb_disable_mdio(struct macb *bp)
++{
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&bp->lock, flags);
++ reg = macb_readl(bp, NCR);
++ reg &= ~MACB_BIT(MPE);
++ macb_writel(bp, NCR, reg);
++ macb_writel(bp, IDR, MACB_BIT(MFD));
++ spin_unlock_irqrestore(&bp->lock, flags);
++}
++
++static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
++{
++ struct macb *bp = netdev_priv(dev);
++ int value;
++
++ mutex_lock(&bp->mdio_mutex);
++
++ macb_enable_mdio(bp);
++ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
++ | MACB_BF(RW, MACB_MAN_READ)
++ | MACB_BF(PHYA, phy_id)
++ | MACB_BF(REGA, location)
++ | MACB_BF(CODE, MACB_MAN_CODE)));
++
++ wait_for_completion(&bp->mdio_complete);
++
++ value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
++ macb_disable_mdio(bp);
++ mutex_unlock(&bp->mdio_mutex);
++
++ return value;
++}
++
++static void macb_mdio_write(struct net_device *dev, int phy_id,
++ int location, int val)
++{
++ struct macb *bp = netdev_priv(dev);
++
++ dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
++ phy_id, location, val);
++
++ mutex_lock(&bp->mdio_mutex);
++ macb_enable_mdio(bp);
++
++ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
++ | MACB_BF(RW, MACB_MAN_WRITE)
++ | MACB_BF(PHYA, phy_id)
++ | MACB_BF(REGA, location)
++ | MACB_BF(CODE, MACB_MAN_CODE)
++ | MACB_BF(DATA, val)));
++
++ wait_for_completion(&bp->mdio_complete);
++
++ macb_disable_mdio(bp);
++ mutex_unlock(&bp->mdio_mutex);
++}
++
++static void macb_set_media(struct macb *bp, int media)
++{
++ u32 reg;
++
++ spin_lock_irq(&bp->lock);
++ reg = macb_readl(bp, NCFGR);
++ reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
++ if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
++ reg |= MACB_BIT(SPD);
++ if (media & ADVERTISE_FULL)
++ reg |= MACB_BIT(FD);
++ macb_writel(bp, NCFGR, reg);
++ spin_unlock_irq(&bp->lock);
++}
++
++static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
++{
++ struct mii_if_info *mii = &bp->mii;
++ unsigned int old_carrier, new_carrier;
++ int advertise, lpa, media, duplex;
++
++ /* if forced media, go no further */
++ if (mii->force_media)
++ return;
++
++ /* check current and old link status */
++ old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
++ new_carrier = (unsigned int) mii_link_ok(mii);
++
++ /* if carrier state did not change, assume nothing else did */
++ if (!init_media && old_carrier == new_carrier)
++ return;
++
++ /* no carrier, nothing much to do */
++ if (!new_carrier) {
++ netif_carrier_off(mii->dev);
++ printk(KERN_INFO "%s: link down\n", mii->dev->name);
++ return;
++ }
++
++ /*
++ * we have carrier, see who's on the other end
++ */
++ netif_carrier_on(mii->dev);
++
++ /* get MII advertise and LPA values */
++ if (!init_media && mii->advertising) {
++ advertise = mii->advertising;
++ } else {
++ advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
++ mii->advertising = advertise;
++ }
++ lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
++
++ /* figure out media and duplex from advertise and LPA values */
++ media = mii_nway_result(lpa & advertise);
++ duplex = (media & ADVERTISE_FULL) ? 1 : 0;
++
++ if (ok_to_print)
++ printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
++ mii->dev->name,
++ media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
++ duplex ? "full" : "half", lpa);
++
++ mii->full_duplex = duplex;
++
++ /* Let the MAC know about the new link state */
++ macb_set_media(bp, media);
++}
++
++static void macb_update_stats(struct macb *bp)
++{
++ u32 __iomem *reg = bp->regs + MACB_PFR;
++ u32 *p = &bp->hw_stats.rx_pause_frames;
++ u32 *end = &bp->hw_stats.tx_pause_frames + 1;
++
++ WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
++
++ for(; p < end; p++, reg++)
++ *p += __raw_readl(reg);
++}
++
++static void macb_periodic_task(void *arg)
++{
++ struct macb *bp = arg;
++
++ macb_update_stats(bp);
++ macb_check_media(bp, 1, 0);
++
++ schedule_delayed_work(&bp->periodic_task, HZ);
++}
++
++static void macb_tx(struct macb *bp)
++{
++ unsigned int tail;
++ unsigned int head;
++ u32 status;
++
++ status = macb_readl(bp, TSR);
++ macb_writel(bp, TSR, status);
++
++ dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
++ (unsigned long)status);
++
++ if (status & MACB_BIT(UND)) {
++ printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
++ bp->dev->name);
++ bp->tx_head = bp->tx_tail = 0;
++ }
++
++ if (!(status & MACB_BIT(COMP)))
++ /*
++ * This may happen when a buffer becomes complete
++ * between reading the ISR and scanning the
++ * descriptors. Nothing to worry about.
++ */
++ return;
++
++ head = bp->tx_head;
++ for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
++ struct ring_info *rp = &bp->tx_skb[tail];
++ struct sk_buff *skb = rp->skb;
++ u32 bufstat;
++
++ BUG_ON(skb == NULL);
++
++ rmb();
++ bufstat = bp->tx_ring[tail].ctrl;
++
++ if (!(bufstat & MACB_BIT(TX_USED)))
++ break;
++
++ dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
++ tail, skb->data);
++ dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
++ DMA_TO_DEVICE);
++ bp->stats.tx_packets++;
++ bp->stats.tx_bytes += skb->len;
++ rp->skb = NULL;
++ dev_kfree_skb_irq(skb);
++ }
++
++ bp->tx_tail = tail;
++ if (netif_queue_stopped(bp->dev) &&
++ TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
++ netif_wake_queue(bp->dev);
++}
++
++static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
++ unsigned int last_frag)
++{
++ unsigned int len;
++ unsigned int frag;
++ unsigned int offset = 0;
++ struct sk_buff *skb;
++
++ len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
++
++ dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
++ first_frag, last_frag, len);
++
++ skb = dev_alloc_skb(len + RX_OFFSET);
++ if (!skb) {
++ bp->stats.rx_dropped++;
++ for (frag = first_frag; ; frag = NEXT_RX(frag)) {
++ bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
++ if (frag == last_frag)
++ break;
++ }
++ wmb();
++ return 1;
++ }
++
++ skb_reserve(skb, RX_OFFSET);
++ skb->dev = bp->dev;
++ skb->ip_summed = CHECKSUM_NONE;
++ skb_put(skb, len);
++
++ for (frag = first_frag; ; frag = NEXT_RX(frag)) {
++ unsigned int frag_len = RX_BUFFER_SIZE;
++
++ if (offset + frag_len > len) {
++ BUG_ON(frag != last_frag);
++ frag_len = len - offset;
++ }
++ memcpy(skb->data + offset,
++ bp->rx_buffers + (RX_BUFFER_SIZE * frag),
++ frag_len);
++ offset += RX_BUFFER_SIZE;
++ bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
++ wmb();
++
++ if (frag == last_frag)
++ break;
++ }
++
++ skb->protocol = eth_type_trans(skb, bp->dev);
++
++ bp->stats.rx_packets++;
++ bp->stats.rx_bytes += len;
++ bp->dev->last_rx = jiffies;
++ dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
++ skb->len, skb->csum);
++ netif_receive_skb(skb);
++
++ return 0;
++}
++
++/* Mark DMA descriptors from begin up to and not including end as unused */
++static void discard_partial_frame(struct macb *bp, unsigned int begin,
++ unsigned int end)
++{
++ unsigned int frag;
++
++ for (frag = begin; frag != end; frag = NEXT_RX(frag))
++ bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
++ wmb();
++
++ /*
++ * When this happens, the hardware stats registers for
++ * whatever caused this is updated, so we don't have to record
++ * anything.
++ */
++}
++
++static int macb_rx(struct macb *bp, int budget)
++{
++ int received = 0;
++ unsigned int tail = bp->rx_tail;
++ int first_frag = -1;
++
++ for (; budget > 0; tail = NEXT_RX(tail)) {
++ u32 addr, ctrl;
++
++ rmb();
++ addr = bp->rx_ring[tail].addr;
++ ctrl = bp->rx_ring[tail].ctrl;
++
++ if (!(addr & MACB_BIT(RX_USED)))
++ break;
++
++ if (ctrl & MACB_BIT(RX_SOF)) {
++ if (first_frag != -1)
++ discard_partial_frame(bp, first_frag, tail);
++ first_frag = tail;
++ }
++
++ if (ctrl & MACB_BIT(RX_EOF)) {
++ int dropped;
++ BUG_ON(first_frag == -1);
++
++ dropped = macb_rx_frame(bp, first_frag, tail);
++ first_frag = -1;
++ if (!dropped) {
++ received++;
++ budget--;
++ }
++ }
++ }
++
++ if (first_frag != -1)
++ bp->rx_tail = first_frag;
++ else
++ bp->rx_tail = tail;
++
++ return received;
++}
++
++static int macb_poll(struct net_device *dev, int *budget)
++{
++ struct macb *bp = netdev_priv(dev);
++ int orig_budget, work_done, retval = 0;
++ u32 status;
++
++ status = macb_readl(bp, RSR);
++ macb_writel(bp, RSR, status);
++
++ if (!status) {
++ /*
++ * This may happen if an interrupt was pending before
++ * this function was called last time, and no packets
++ * have been received since.
++ */
++ netif_rx_complete(dev);
++ goto out;
++ }
++
++ dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
++ (unsigned long)status, *budget);
++
++ if (!(status & MACB_BIT(REC))) {
++ dev_warn(&bp->pdev->dev,
++ "No RX buffers complete, status = %02lx\n",
++ (unsigned long)status);
++ netif_rx_complete(dev);
++ goto out;
++ }
++
++ orig_budget = *budget;
++ if (orig_budget > dev->quota)
++ orig_budget = dev->quota;
++
++ work_done = macb_rx(bp, orig_budget);
++ if (work_done < orig_budget) {
++ netif_rx_complete(dev);
++ retval = 0;
++ } else {
++ retval = 1;
++ }
++
++ /*
++ * We've done what we can to clean the buffers. Make sure we
++ * get notified when new packets arrive.
++ */
++out:
++ macb_writel(bp, IER, MACB_RX_INT_FLAGS);
++
++ /* TODO: Handle errors */
++
++ return retval;
++}
++
++static irqreturn_t macb_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++ struct net_device *dev = dev_id;
++ struct macb *bp = netdev_priv(dev);
++ u32 status;
++
++ status = macb_readl(bp, ISR);
++
++ if (unlikely(!status))
++ return IRQ_NONE;
++
++ spin_lock(&bp->lock);
++
++ /* close possible race with dev_close */
++ if (unlikely(!netif_running(dev))) {
++ macb_writel(bp, IDR, ~0UL);
++ spin_unlock(&bp->lock);
++ return IRQ_HANDLED;
++ }
++
++ while (status) {
++ if (status & MACB_BIT(MFD))
++ complete(&bp->mdio_complete);
++
++ if (status & MACB_RX_INT_FLAGS) {
++ if (netif_rx_schedule_prep(dev)) {
++ /*
++ * There's no point taking any more interrupts
++ * until we have processed the buffers
++ */
++ macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
++ dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
++ __netif_rx_schedule(dev);
++ }
++ }
++
++ if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
++ macb_tx(bp);
++
++ /*
++ * Link change detection isn't possible with RMII, so we'll
++ * add that if/when we get our hands on a full-blown MII PHY.
++ */
++
++ if (status & MACB_BIT(HRESP)) {
++ /*
++ * TODO: Reset the hardware, and maybe move the printk
++ * to a lower-priority context as well (work queue?)
++ */
++ printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
++ dev->name);
++ }
++
++ status = macb_readl(bp, ISR);
++ }
++
++ spin_unlock(&bp->lock);
++
++ return IRQ_HANDLED;
++}
++
++static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct macb *bp = netdev_priv(dev);
++ dma_addr_t mapping;
++ unsigned int len, entry;
++ u32 ctrl;
++
++#ifdef DEBUG
++ int i;
++ dev_dbg(&bp->pdev->dev,
++ "start_xmit: len %u head %p data %p tail %p end %p\n",
++ skb->len, skb->head, skb->data, skb->tail, skb->end);
++ dev_dbg(&bp->pdev->dev,
++ "data:");
++ for (i = 0; i < 16; i++)
++ printk(" %02x", (unsigned int)skb->data[i]);
++ printk("\n");
++#endif
++
++ len = skb->len;
++ spin_lock_irq(&bp->lock);
++
++ /* This is a hard error, log it. */
++ if (TX_BUFFS_AVAIL(bp) < 1) {
++ netif_stop_queue(dev);
++ spin_unlock_irq(&bp->lock);
++ dev_err(&bp->pdev->dev,
++ "BUG! Tx Ring full when queue awake!\n");
++ dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
++ bp->tx_head, bp->tx_tail);
++ return 1;
++ }
++
++ entry = bp->tx_head;
++ dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
++ mapping = dma_map_single(&bp->pdev->dev, skb->data,
++ len, DMA_TO_DEVICE);
++ bp->tx_skb[entry].skb = skb;
++ bp->tx_skb[entry].mapping = mapping;
++ dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
++ skb->data, (unsigned long)mapping);
++
++ ctrl = MACB_BF(TX_FRMLEN, len);
++ ctrl |= MACB_BIT(TX_LAST);
++ if (entry == (TX_RING_SIZE - 1))
++ ctrl |= MACB_BIT(TX_WRAP);
++
++ bp->tx_ring[entry].addr = mapping;
++ bp->tx_ring[entry].ctrl = ctrl;
++ wmb();
++
++ entry = NEXT_TX(entry);
++ bp->tx_head = entry;
++
++ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
++
++ if (TX_BUFFS_AVAIL(bp) < 1)
++ netif_stop_queue(dev);
++
++ spin_unlock_irq(&bp->lock);
++
++ dev->trans_start = jiffies;
++
++ return 0;
++}
++
++static void macb_free_consistent(struct macb *bp)
++{
++ if (bp->tx_skb) {
++ kfree(bp->tx_skb);
++ bp->tx_skb = NULL;
++ }
++ if (bp->rx_ring) {
++ dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
++ bp->rx_ring, bp->rx_ring_dma);
++ bp->rx_ring = NULL;
++ }
++ if (bp->tx_ring) {
++ dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
++ bp->tx_ring, bp->tx_ring_dma);
++ bp->tx_ring = NULL;
++ }
++ if (bp->rx_buffers) {
++ dma_free_coherent(&bp->pdev->dev,
++ RX_RING_SIZE * RX_BUFFER_SIZE,
++ bp->rx_buffers, bp->rx_buffers_dma);
++ bp->rx_buffers = NULL;
++ }
++}
++
++static int macb_alloc_consistent(struct macb *bp)
++{
++ int size;
++
++ size = TX_RING_SIZE * sizeof(struct ring_info);
++ bp->tx_skb = kmalloc(size, GFP_KERNEL);
++ if (!bp->tx_skb)
++ goto out_err;
++
++ size = RX_RING_BYTES;
++ bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
++ &bp->rx_ring_dma, GFP_KERNEL);
++ if (!bp->rx_ring)
++ goto out_err;
++ dev_dbg(&bp->pdev->dev,
++ "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
++ size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
++
++ size = TX_RING_BYTES;
++ bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
++ &bp->tx_ring_dma, GFP_KERNEL);
++ if (!bp->tx_ring)
++ goto out_err;
++ dev_dbg(&bp->pdev->dev,
++ "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
++ size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
++
++ size = RX_RING_SIZE * RX_BUFFER_SIZE;
++ bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
++ &bp->rx_buffers_dma, GFP_KERNEL);
++ if (!bp->rx_buffers)
++ goto out_err;
++ dev_dbg(&bp->pdev->dev,
++ "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
++ size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
++
++ return 0;
++
++out_err:
++ macb_free_consistent(bp);
++ return -ENOMEM;
++}
++
++static void macb_init_rings(struct macb *bp)
++{
++ int i;
++ dma_addr_t addr;
++
++ addr = bp->rx_buffers_dma;
++ for (i = 0; i < RX_RING_SIZE; i++) {
++ bp->rx_ring[i].addr = addr;
++ bp->rx_ring[i].ctrl = 0;
++ addr += RX_BUFFER_SIZE;
++ }
++ bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
++
++ for (i = 0; i < TX_RING_SIZE; i++) {
++ bp->tx_ring[i].addr = 0;
++ bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
++ }
++ bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
++
++ bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
++}
++
++static void macb_reset_hw(struct macb *bp)
++{
++ /* Make sure we have the write buffer for ourselves */
++ wmb();
++
++ /*
++ * Disable RX and TX (XXX: Should we halt the transmission
++ * more gracefully?)
++ */
++ macb_writel(bp, NCR, 0);
++
++ /* Clear the stats registers (XXX: Update stats first?) */
++ macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
++
++ /* Clear all status flags */
++ macb_writel(bp, TSR, ~0UL);
++ macb_writel(bp, RSR, ~0UL);
++
++ /* Disable all interrupts */
++ macb_writel(bp, IDR, ~0UL);
++ macb_readl(bp, ISR);
++}
++
++static void macb_init_hw(struct macb *bp)
++{
++ unsigned long pclk_hz;
++ u32 config;
++
++ macb_reset_hw(bp);
++ __macb_set_hwaddr(bp);
++
++ /* Set RMII mode */
++ macb_writel(bp, USRIO, MACB_BIT(RMII));
++
++ /* Initialize Network Configuration Register */
++ pclk_hz = clk_get_rate(bp->pclk);
++ if (pclk_hz <= 20000000)
++ config = MACB_BF(CLK, MACB_CLK_DIV8);
++ else if (pclk_hz <= 40000000)
++ config = MACB_BF(CLK, MACB_CLK_DIV16);
++ else if (pclk_hz <= 80000000)
++ config = MACB_BF(CLK, MACB_CLK_DIV32);
++ else
++ config = MACB_BF(CLK, MACB_CLK_DIV64);
++
++ config |= MACB_BIT(PAE); /* PAuse Enable */
++ config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
++ if (bp->dev->flags & IFF_PROMISC)
++ config |= MACB_BIT(CAF); /* Copy All Frames */
++ if (!(bp->dev->flags & IFF_BROADCAST))
++ config |= MACB_BIT(NBC); /* No BroadCast */
++ macb_writel(bp, NCFGR, config);
++
++ /* Initialize TX and RX buffers */
++ macb_writel(bp, RBQP, bp->rx_ring_dma);
++ macb_writel(bp, TBQP, bp->tx_ring_dma);
++
++ /* Enable TX and RX */
++ macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
++
++ /* Enable interrupts */
++ macb_writel(bp, IER, (MACB_BIT(RCOMP)
++ | MACB_BIT(RXUBR)
++ | MACB_BIT(ISR_TUND)
++ | MACB_BIT(ISR_RLE)
++ | MACB_BIT(TXERR)
++ | MACB_BIT(TCOMP)
++ | MACB_BIT(ISR_ROVR)
++ | MACB_BIT(HRESP)));
++}
++
++static void macb_init_phy(struct net_device *dev)
++{
++ struct macb *bp = netdev_priv(dev);
++
++ /* Set some reasonable default settings */
++ macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
++ ADVERTISE_CSMA | ADVERTISE_ALL);
++ macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
++ (BMCR_SPEED100 | BMCR_ANENABLE
++ | BMCR_ANRESTART | BMCR_FULLDPLX));
++}
++
++static int macb_open(struct net_device *dev)
++{
++ struct macb *bp = netdev_priv(dev);
++ int err;
++
++ dev_dbg(&bp->pdev->dev, "open\n");
++
++ err = macb_alloc_consistent(bp);
++ if (err) {
++ printk(KERN_ERR
++ "%s: Unable to allocate DMA memory (error %d)\n",
++ dev->name, err);
++ return err;
++ }
++
++ macb_init_rings(bp);
++ macb_init_hw(bp);
++ macb_init_phy(dev);
++
++ macb_check_media(bp, 1, 1);
++ netif_start_queue(dev);
++
++ schedule_delayed_work(&bp->periodic_task, HZ);
++
++ return 0;
++}
++
++static int macb_close(struct net_device *dev)
++{
++ struct macb *bp = netdev_priv(dev);
++ unsigned long flags;
++
++ cancel_rearming_delayed_work(&bp->periodic_task);
++
++ netif_stop_queue(dev);
++
++ spin_lock_irqsave(&bp->lock, flags);
++ macb_reset_hw(bp);
++ netif_carrier_off(dev);
++ spin_unlock_irqrestore(&bp->lock, flags);
++
++ macb_free_consistent(bp);
++
++ return 0;
++}
++
++static struct net_device_stats *macb_get_stats(struct net_device *dev)
++{
++ struct macb *bp = netdev_priv(dev);
++ struct net_device_stats *nstat = &bp->stats;
++ struct macb_stats *hwstat = &bp->hw_stats;
++
++ /* Convert HW stats into netdevice stats */
++ nstat->rx_errors = (hwstat->rx_fcs_errors +
++ hwstat->rx_align_errors +
++ hwstat->rx_resource_errors +
++ hwstat->rx_overruns +
++ hwstat->rx_oversize_pkts +
++ hwstat->rx_jabbers +
++ hwstat->rx_undersize_pkts +
++ hwstat->sqe_test_errors +
++ hwstat->rx_length_mismatch);
++ nstat->tx_errors = (hwstat->tx_late_cols +
++ hwstat->tx_excessive_cols +
++ hwstat->tx_underruns +
++ hwstat->tx_carrier_errors);
++ nstat->collisions = (hwstat->tx_single_cols +
++ hwstat->tx_multiple_cols +
++ hwstat->tx_excessive_cols);
++ nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
++ hwstat->rx_jabbers +
++ hwstat->rx_undersize_pkts +
++ hwstat->rx_length_mismatch);
++ nstat->rx_over_errors = hwstat->rx_resource_errors;
++ nstat->rx_crc_errors = hwstat->rx_fcs_errors;
++ nstat->rx_frame_errors = hwstat->rx_align_errors;
++ nstat->rx_fifo_errors = hwstat->rx_overruns;
++ /* XXX: What does "missed" mean? */
++ nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
++ nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
++ nstat->tx_fifo_errors = hwstat->tx_underruns;
++ /* Don't know about heartbeat or window errors... */
++
++ return nstat;
++}
++
++static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct macb *bp = netdev_priv(dev);
++ int ret;
++ unsigned long flags;
++
++ spin_lock_irqsave(&bp->lock, flags);
++ ret = mii_ethtool_gset(&bp->mii, cmd);
++ spin_unlock_irqrestore(&bp->lock, flags);
++
++ return ret;
++}
++
++static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct macb *bp = netdev_priv(dev);
++ int ret;
++ unsigned long flags;
++
++ spin_lock_irqsave(&bp->lock, flags);
++ ret = mii_ethtool_sset(&bp->mii, cmd);
++ spin_unlock_irqrestore(&bp->lock, flags);
++
++ return ret;
++}
++
++static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
++{
++ struct macb *bp = netdev_priv(dev);
++
++ strcpy(info->driver, bp->pdev->dev.driver->name);
++ strcpy(info->version, "$Revision: 1.14 $");
++ strcpy(info->bus_info, bp->pdev->dev.bus_id);
++}
++
++static int macb_nway_reset(struct net_device *dev)
++{
++ struct macb *bp = netdev_priv(dev);
++ return mii_nway_restart(&bp->mii);
++}
++
++static struct ethtool_ops macb_ethtool_ops = {
++ .get_settings = macb_get_settings,
++ .set_settings = macb_set_settings,
++ .get_drvinfo = macb_get_drvinfo,
++ .nway_reset = macb_nway_reset,
++ .get_link = ethtool_op_get_link,
++};
++
++static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++ struct macb *bp = netdev_priv(dev);
++ int ret;
++ unsigned long flags;
++
++ if (!netif_running(dev))
++ return -EINVAL;
++
++ spin_lock_irqsave(&bp->lock, flags);
++ ret = generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
++ spin_unlock_irqrestore(&bp->lock, flags);
++
++ return ret;
++}
++
++static ssize_t macb_mii_show(const struct class_device *cd, char *buf,
++ unsigned long addr)
++{
++ struct net_device *dev = to_net_dev(cd);
++ struct macb *bp = netdev_priv(dev);
++ ssize_t ret = -EINVAL;
++
++ if (netif_running(dev)) {
++ int value;
++ value = macb_mdio_read(dev, bp->mii.phy_id, addr);
++ ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
++ }
++
++ return ret;
++}
++
++#define MII_ENTRY(name, addr) \
++static ssize_t show_##name(struct class_device *cd, char *buf) \
++{ \
++ return macb_mii_show(cd, buf, addr); \
++} \
++static CLASS_DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
++
++MII_ENTRY(bmcr, MII_BMCR);
++MII_ENTRY(bmsr, MII_BMSR);
++MII_ENTRY(physid1, MII_PHYSID1);
++MII_ENTRY(physid2, MII_PHYSID2);
++MII_ENTRY(advertise, MII_ADVERTISE);
++MII_ENTRY(lpa, MII_LPA);
++MII_ENTRY(expansion, MII_EXPANSION);
++
++static struct attribute *macb_mii_attrs[] = {
++ &class_device_attr_bmcr.attr,
++ &class_device_attr_bmsr.attr,
++ &class_device_attr_physid1.attr,
++ &class_device_attr_physid2.attr,
++ &class_device_attr_advertise.attr,
++ &class_device_attr_lpa.attr,
++ &class_device_attr_expansion.attr,
++ NULL,
++};
++
++static struct attribute_group macb_mii_group = {
++ .name = "mii",
++ .attrs = macb_mii_attrs,
++};
++
++static void macb_unregister_sysfs(struct net_device *net)
++{
++ struct class_device *class_dev = &net->class_dev;
++
++ sysfs_remove_group(&class_dev->kobj, &macb_mii_group);
++}
++
++static int macb_register_sysfs(struct net_device *net)
++{
++ struct class_device *class_dev = &net->class_dev;
++ int ret;
++
++ ret = sysfs_create_group(&class_dev->kobj, &macb_mii_group);
++ if (ret)
++ printk(KERN_WARNING
++ "%s: sysfs mii attribute registration failed: %d\n",
++ net->name, ret);
++ return ret;
++}
++static int __devinit macb_probe(struct platform_device *pdev)
++{
++ struct eth_platform_data *pdata;
++ struct resource *regs;
++ struct net_device *dev;
++ struct macb *bp;
++ int err = -ENXIO;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs) {
++ dev_err(&pdev->dev, "no mmio resource defined\n");
++ goto err_out;
++ }
++
++ err = -ENOMEM;
++ dev = alloc_etherdev(sizeof(*bp));
++ if (!dev) {
++ dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
++ goto err_out;
++ }
++
++ SET_MODULE_OWNER(dev);
++ SET_NETDEV_DEV(dev, &pdev->dev);
++
++ /* TODO: Actually, we have some interesting features... */
++ dev->features |= 0;
++
++ bp = netdev_priv(dev);
++ bp->pdev = pdev;
++ bp->dev = dev;
++
++ spin_lock_init(&bp->lock);
++
++ bp->pclk = clk_get(&pdev->dev, "pclk");
++ if (IS_ERR(bp->pclk)) {
++ dev_err(&pdev->dev, "failed to get pclk\n");
++ goto err_out_free_dev;
++ }
++ bp->hclk = clk_get(&pdev->dev, "hclk");
++ if (IS_ERR(bp->hclk)) {
++ dev_err(&pdev->dev, "failed to get hclk\n");
++ goto err_out_put_pclk;
++ }
++
++ clk_enable(bp->pclk);
++ clk_enable(bp->hclk);
++
++ bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!bp->regs) {
++ dev_err(&pdev->dev, "failed to map registers, aborting.\n");
++ err = -ENOMEM;
++ goto err_out_disable_clocks;
++ }
++
++ dev->irq = platform_get_irq(pdev, 0);
++ err = request_irq(dev->irq, macb_interrupt, SA_SAMPLE_RANDOM,
++ dev->name, dev);
++ if (err) {
++ printk(KERN_ERR
++ "%s: Unable to request IRQ %d (error %d)\n",
++ dev->name, dev->irq, err);
++ goto err_out_iounmap;
++ }
++
++ dev->open = macb_open;
++ dev->stop = macb_close;
++ dev->hard_start_xmit = macb_start_xmit;
++ dev->get_stats = macb_get_stats;
++ dev->do_ioctl = macb_ioctl;
++ dev->poll = macb_poll;
++ dev->weight = 64;
++ dev->ethtool_ops = &macb_ethtool_ops;
++
++ dev->base_addr = regs->start;
++
++ INIT_WORK(&bp->periodic_task, macb_periodic_task, bp);
++ mutex_init(&bp->mdio_mutex);
++ init_completion(&bp->mdio_complete);
++
++ bp->mii.dev = dev;
++ bp->mii.mdio_read = macb_mdio_read;
++ bp->mii.mdio_write = macb_mdio_write;
++
++ pdata = pdev->dev.platform_data;
++ if (!pdata) {
++ dev_err(&pdev->dev, "Cannot determine hw address\n");
++ goto err_out_free_irq;
++ }
++
++ memcpy(dev->dev_addr, pdata->hw_addr, dev->addr_len);
++ bp->mii.phy_id = pdata->mii_phy_addr;
++ bp->mii.phy_id_mask = 0x1f;
++ bp->mii.reg_num_mask = 0x1f;
++
++ bp->tx_pending = DEF_TX_RING_PENDING;
++
++ err = register_netdev(dev);
++ if (err) {
++ dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
++ goto err_out_free_irq;
++ }
++
++ platform_set_drvdata(pdev, dev);
++
++ macb_register_sysfs(dev);
++
++ printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
++ "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
++ dev->name, dev->base_addr, dev->irq,
++ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
++ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
++
++ return 0;
++
++err_out_free_irq:
++ free_irq(dev->irq, dev);
++err_out_iounmap:
++ iounmap(bp->regs);
++err_out_disable_clocks:
++ clk_disable(bp->hclk);
++ clk_disable(bp->pclk);
++ clk_put(bp->hclk);
++err_out_put_pclk:
++ clk_put(bp->pclk);
++err_out_free_dev:
++ free_netdev(dev);
++err_out:
++ platform_set_drvdata(pdev, NULL);
++ return err;
++}
++
++static int __devexit macb_remove(struct platform_device *pdev)
++{
++ struct net_device *dev;
++ struct macb *bp;
++
++ dev = platform_get_drvdata(pdev);
++
++ if (dev) {
++ bp = netdev_priv(dev);
++ macb_unregister_sysfs(dev);
++ unregister_netdev(dev);
++ free_irq(dev->irq, dev);
++ iounmap(bp->regs);
++ clk_disable(bp->hclk);
++ clk_disable(bp->pclk);
++ clk_put(bp->hclk);
++ clk_put(bp->pclk);
++ free_netdev(dev);
++ platform_set_drvdata(pdev, NULL);
++ }
++
++ return 0;
++}
++
++static struct platform_driver macb_driver = {
++ .probe = macb_probe,
++ .remove = __devexit_p(macb_remove),
++ .driver = {
++ .name = "macb",
++ },
++};
++
++static int __init macb_init(void)
++{
++ return platform_driver_register(&macb_driver);
++}
++
++static void __exit macb_exit(void)
++{
++ platform_driver_unregister(&macb_driver);
++}
++
++module_init(macb_init);
++module_exit(macb_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
+Index: linux-2.6.18-avr32/drivers/net/macb.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/net/macb.h 2006-11-02 16:33:26.000000000 +0100
+@@ -0,0 +1,387 @@
++/*
++ * Atmel MACB Ethernet Controller driver
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef _MACB_H
++#define _MACB_H
++
++/* MACB register offsets */
++#define MACB_NCR 0x0000
++#define MACB_NCFGR 0x0004
++#define MACB_NSR 0x0008
++#define MACB_TSR 0x0014
++#define MACB_RBQP 0x0018
++#define MACB_TBQP 0x001c
++#define MACB_RSR 0x0020
++#define MACB_ISR 0x0024
++#define MACB_IER 0x0028
++#define MACB_IDR 0x002c
++#define MACB_IMR 0x0030
++#define MACB_MAN 0x0034
++#define MACB_PTR 0x0038
++#define MACB_PFR 0x003c
++#define MACB_FTO 0x0040
++#define MACB_SCF 0x0044
++#define MACB_MCF 0x0048
++#define MACB_FRO 0x004c
++#define MACB_FCSE 0x0050
++#define MACB_ALE 0x0054
++#define MACB_DTF 0x0058
++#define MACB_LCOL 0x005c
++#define MACB_EXCOL 0x0060
++#define MACB_TUND 0x0064
++#define MACB_CSE 0x0068
++#define MACB_RRE 0x006c
++#define MACB_ROVR 0x0070
++#define MACB_RSE 0x0074
++#define MACB_ELE 0x0078
++#define MACB_RJA 0x007c
++#define MACB_USF 0x0080
++#define MACB_STE 0x0084
++#define MACB_RLE 0x0088
++#define MACB_TPF 0x008c
++#define MACB_HRB 0x0090
++#define MACB_HRT 0x0094
++#define MACB_SA1B 0x0098
++#define MACB_SA1T 0x009c
++#define MACB_SA2B 0x00a0
++#define MACB_SA2T 0x00a4
++#define MACB_SA3B 0x00a8
++#define MACB_SA3T 0x00ac
++#define MACB_SA4B 0x00b0
++#define MACB_SA4T 0x00b4
++#define MACB_TID 0x00b8
++#define MACB_TPQ 0x00bc
++#define MACB_USRIO 0x00c0
++#define MACB_WOL 0x00c4
++
++/* Bitfields in NCR */
++#define MACB_LB_OFFSET 0
++#define MACB_LB_SIZE 1
++#define MACB_LLB_OFFSET 1
++#define MACB_LLB_SIZE 1
++#define MACB_RE_OFFSET 2
++#define MACB_RE_SIZE 1
++#define MACB_TE_OFFSET 3
++#define MACB_TE_SIZE 1
++#define MACB_MPE_OFFSET 4
++#define MACB_MPE_SIZE 1
++#define MACB_CLRSTAT_OFFSET 5
++#define MACB_CLRSTAT_SIZE 1
++#define MACB_INCSTAT_OFFSET 6
++#define MACB_INCSTAT_SIZE 1
++#define MACB_WESTAT_OFFSET 7
++#define MACB_WESTAT_SIZE 1
++#define MACB_BP_OFFSET 8
++#define MACB_BP_SIZE 1
++#define MACB_TSTART_OFFSET 9
++#define MACB_TSTART_SIZE 1
++#define MACB_THALT_OFFSET 10
++#define MACB_THALT_SIZE 1
++#define MACB_NCR_TPF_OFFSET 11
++#define MACB_NCR_TPF_SIZE 1
++#define MACB_TZQ_OFFSET 12
++#define MACB_TZQ_SIZE 1
++
++/* Bitfields in NCFGR */
++#define MACB_SPD_OFFSET 0
++#define MACB_SPD_SIZE 1
++#define MACB_FD_OFFSET 1
++#define MACB_FD_SIZE 1
++#define MACB_BIT_RATE_OFFSET 2
++#define MACB_BIT_RATE_SIZE 1
++#define MACB_JFRAME_OFFSET 3
++#define MACB_JFRAME_SIZE 1
++#define MACB_CAF_OFFSET 4
++#define MACB_CAF_SIZE 1
++#define MACB_NBC_OFFSET 5
++#define MACB_NBC_SIZE 1
++#define MACB_NCFGR_MTI_OFFSET 6
++#define MACB_NCFGR_MTI_SIZE 1
++#define MACB_UNI_OFFSET 7
++#define MACB_UNI_SIZE 1
++#define MACB_BIG_OFFSET 8
++#define MACB_BIG_SIZE 1
++#define MACB_EAE_OFFSET 9
++#define MACB_EAE_SIZE 1
++#define MACB_CLK_OFFSET 10
++#define MACB_CLK_SIZE 2
++#define MACB_RTY_OFFSET 12
++#define MACB_RTY_SIZE 1
++#define MACB_PAE_OFFSET 13
++#define MACB_PAE_SIZE 1
++#define MACB_RBOF_OFFSET 14
++#define MACB_RBOF_SIZE 2
++#define MACB_RLCE_OFFSET 16
++#define MACB_RLCE_SIZE 1
++#define MACB_DRFCS_OFFSET 17
++#define MACB_DRFCS_SIZE 1
++#define MACB_EFRHD_OFFSET 18
++#define MACB_EFRHD_SIZE 1
++#define MACB_IRXFCS_OFFSET 19
++#define MACB_IRXFCS_SIZE 1
++
++/* Bitfields in NSR */
++#define MACB_NSR_LINK_OFFSET 0
++#define MACB_NSR_LINK_SIZE 1
++#define MACB_MDIO_OFFSET 1
++#define MACB_MDIO_SIZE 1
++#define MACB_IDLE_OFFSET 2
++#define MACB_IDLE_SIZE 1
++
++/* Bitfields in TSR */
++#define MACB_UBR_OFFSET 0
++#define MACB_UBR_SIZE 1
++#define MACB_COL_OFFSET 1
++#define MACB_COL_SIZE 1
++#define MACB_TSR_RLE_OFFSET 2
++#define MACB_TSR_RLE_SIZE 1
++#define MACB_TGO_OFFSET 3
++#define MACB_TGO_SIZE 1
++#define MACB_BEX_OFFSET 4
++#define MACB_BEX_SIZE 1
++#define MACB_COMP_OFFSET 5
++#define MACB_COMP_SIZE 1
++#define MACB_UND_OFFSET 6
++#define MACB_UND_SIZE 1
++
++/* Bitfields in RSR */
++#define MACB_BNA_OFFSET 0
++#define MACB_BNA_SIZE 1
++#define MACB_REC_OFFSET 1
++#define MACB_REC_SIZE 1
++#define MACB_OVR_OFFSET 2
++#define MACB_OVR_SIZE 1
++
++/* Bitfields in ISR/IER/IDR/IMR */
++#define MACB_MFD_OFFSET 0
++#define MACB_MFD_SIZE 1
++#define MACB_RCOMP_OFFSET 1
++#define MACB_RCOMP_SIZE 1
++#define MACB_RXUBR_OFFSET 2
++#define MACB_RXUBR_SIZE 1
++#define MACB_TXUBR_OFFSET 3
++#define MACB_TXUBR_SIZE 1
++#define MACB_ISR_TUND_OFFSET 4
++#define MACB_ISR_TUND_SIZE 1
++#define MACB_ISR_RLE_OFFSET 5
++#define MACB_ISR_RLE_SIZE 1
++#define MACB_TXERR_OFFSET 6
++#define MACB_TXERR_SIZE 1
++#define MACB_TCOMP_OFFSET 7
++#define MACB_TCOMP_SIZE 1
++#define MACB_ISR_LINK_OFFSET 9
++#define MACB_ISR_LINK_SIZE 1
++#define MACB_ISR_ROVR_OFFSET 10
++#define MACB_ISR_ROVR_SIZE 1
++#define MACB_HRESP_OFFSET 11
++#define MACB_HRESP_SIZE 1
++#define MACB_PFR_OFFSET 12
++#define MACB_PFR_SIZE 1
++#define MACB_PTZ_OFFSET 13
++#define MACB_PTZ_SIZE 1
++
++/* Bitfields in MAN */
++#define MACB_DATA_OFFSET 0
++#define MACB_DATA_SIZE 16
++#define MACB_CODE_OFFSET 16
++#define MACB_CODE_SIZE 2
++#define MACB_REGA_OFFSET 18
++#define MACB_REGA_SIZE 5
++#define MACB_PHYA_OFFSET 23
++#define MACB_PHYA_SIZE 5
++#define MACB_RW_OFFSET 28
++#define MACB_RW_SIZE 2
++#define MACB_SOF_OFFSET 30
++#define MACB_SOF_SIZE 2
++
++/* Bitfields in USRIO */
++#define MACB_RMII_OFFSET 0
++#define MACB_RMII_SIZE 1
++#define MACB_EAM_OFFSET 1
++#define MACB_EAM_SIZE 1
++#define MACB_TX_PAUSE_OFFSET 2
++#define MACB_TX_PAUSE_SIZE 1
++#define MACB_TX_PAUSE_ZERO_OFFSET 3
++#define MACB_TX_PAUSE_ZERO_SIZE 1
++
++/* Bitfields in WOL */
++#define MACB_IP_OFFSET 0
++#define MACB_IP_SIZE 16
++#define MACB_MAG_OFFSET 16
++#define MACB_MAG_SIZE 1
++#define MACB_ARP_OFFSET 17
++#define MACB_ARP_SIZE 1
++#define MACB_SA1_OFFSET 18
++#define MACB_SA1_SIZE 1
++#define MACB_WOL_MTI_OFFSET 19
++#define MACB_WOL_MTI_SIZE 1
++
++/* Constants for CLK */
++#define MACB_CLK_DIV8 0
++#define MACB_CLK_DIV16 1
++#define MACB_CLK_DIV32 2
++#define MACB_CLK_DIV64 3
++
++/* Constants for MAN register */
++#define MACB_MAN_SOF 1
++#define MACB_MAN_WRITE 1
++#define MACB_MAN_READ 2
++#define MACB_MAN_CODE 2
++
++/* Bit manipulation macros */
++#define MACB_BIT(name) \
++ (1 << MACB_##name##_OFFSET)
++#define MACB_BF(name,value) \
++ (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
++ << MACB_##name##_OFFSET)
++#define MACB_BFEXT(name,value)\
++ (((value) >> MACB_##name##_OFFSET) \
++ & ((1 << MACB_##name##_SIZE) - 1))
++#define MACB_BFINS(name,value,old) \
++ (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
++ << MACB_##name##_OFFSET)) \
++ | MACB_BF(name,value))
++
++/* Register access macros */
++#define macb_readl(port,reg) \
++ __raw_readl((port)->regs + MACB_##reg)
++#define macb_writel(port,reg,value) \
++ __raw_writel((value), (port)->regs + MACB_##reg)
++
++struct dma_desc {
++ u32 addr;
++ u32 ctrl;
++};
++
++/* DMA descriptor bitfields */
++#define MACB_RX_USED_OFFSET 0
++#define MACB_RX_USED_SIZE 1
++#define MACB_RX_WRAP_OFFSET 1
++#define MACB_RX_WRAP_SIZE 1
++#define MACB_RX_WADDR_OFFSET 2
++#define MACB_RX_WADDR_SIZE 30
++
++#define MACB_RX_FRMLEN_OFFSET 0
++#define MACB_RX_FRMLEN_SIZE 12
++#define MACB_RX_OFFSET_OFFSET 12
++#define MACB_RX_OFFSET_SIZE 2
++#define MACB_RX_SOF_OFFSET 14
++#define MACB_RX_SOF_SIZE 1
++#define MACB_RX_EOF_OFFSET 15
++#define MACB_RX_EOF_SIZE 1
++#define MACB_RX_CFI_OFFSET 16
++#define MACB_RX_CFI_SIZE 1
++#define MACB_RX_VLAN_PRI_OFFSET 17
++#define MACB_RX_VLAN_PRI_SIZE 3
++#define MACB_RX_PRI_TAG_OFFSET 20
++#define MACB_RX_PRI_TAG_SIZE 1
++#define MACB_RX_VLAN_TAG_OFFSET 21
++#define MACB_RX_VLAN_TAG_SIZE 1
++#define MACB_RX_TYPEID_MATCH_OFFSET 22
++#define MACB_RX_TYPEID_MATCH_SIZE 1
++#define MACB_RX_SA4_MATCH_OFFSET 23
++#define MACB_RX_SA4_MATCH_SIZE 1
++#define MACB_RX_SA3_MATCH_OFFSET 24
++#define MACB_RX_SA3_MATCH_SIZE 1
++#define MACB_RX_SA2_MATCH_OFFSET 25
++#define MACB_RX_SA2_MATCH_SIZE 1
++#define MACB_RX_SA1_MATCH_OFFSET 26
++#define MACB_RX_SA1_MATCH_SIZE 1
++#define MACB_RX_EXT_MATCH_OFFSET 28
++#define MACB_RX_EXT_MATCH_SIZE 1
++#define MACB_RX_UHASH_MATCH_OFFSET 29
++#define MACB_RX_UHASH_MATCH_SIZE 1
++#define MACB_RX_MHASH_MATCH_OFFSET 30
++#define MACB_RX_MHASH_MATCH_SIZE 1
++#define MACB_RX_BROADCAST_OFFSET 31
++#define MACB_RX_BROADCAST_SIZE 1
++
++#define MACB_TX_FRMLEN_OFFSET 0
++#define MACB_TX_FRMLEN_SIZE 11
++#define MACB_TX_LAST_OFFSET 15
++#define MACB_TX_LAST_SIZE 1
++#define MACB_TX_NOCRC_OFFSET 16
++#define MACB_TX_NOCRC_SIZE 1
++#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
++#define MACB_TX_BUF_EXHAUSTED_SIZE 1
++#define MACB_TX_UNDERRUN_OFFSET 28
++#define MACB_TX_UNDERRUN_SIZE 1
++#define MACB_TX_ERROR_OFFSET 29
++#define MACB_TX_ERROR_SIZE 1
++#define MACB_TX_WRAP_OFFSET 30
++#define MACB_TX_WRAP_SIZE 1
++#define MACB_TX_USED_OFFSET 31
++#define MACB_TX_USED_SIZE 1
++
++struct ring_info {
++ struct sk_buff *skb;
++ dma_addr_t mapping;
++};
++
++/*
++ * Hardware-collected statistics. Used when updating the network
++ * device stats by a periodic timer.
++ */
++struct macb_stats {
++ u32 rx_pause_frames;
++ u32 tx_ok;
++ u32 tx_single_cols;
++ u32 tx_multiple_cols;
++ u32 rx_ok;
++ u32 rx_fcs_errors;
++ u32 rx_align_errors;
++ u32 tx_deferred;
++ u32 tx_late_cols;
++ u32 tx_excessive_cols;
++ u32 tx_underruns;
++ u32 tx_carrier_errors;
++ u32 rx_resource_errors;
++ u32 rx_overruns;
++ u32 rx_symbol_errors;
++ u32 rx_oversize_pkts;
++ u32 rx_jabbers;
++ u32 rx_undersize_pkts;
++ u32 sqe_test_errors;
++ u32 rx_length_mismatch;
++ u32 tx_pause_frames;
++};
++
++struct macb {
++ void __iomem *regs;
++
++ unsigned int rx_tail;
++ struct dma_desc *rx_ring;
++ void *rx_buffers;
++
++ unsigned int tx_head, tx_tail;
++ struct dma_desc *tx_ring;
++ struct ring_info *tx_skb;
++
++ spinlock_t lock;
++ struct platform_device *pdev;
++ struct clk *pclk;
++ struct clk *hclk;
++ struct net_device *dev;
++ struct net_device_stats stats;
++ struct macb_stats hw_stats;
++
++ dma_addr_t rx_ring_dma;
++ dma_addr_t tx_ring_dma;
++ dma_addr_t rx_buffers_dma;
++
++ unsigned int rx_pending, tx_pending;
++
++ struct work_struct periodic_task;
++
++ struct mutex mdio_mutex;
++ struct completion mdio_complete;
++ struct mii_if_info mii;
++};
++
++#endif /* _MACB_H */
diff --git a/packages/linux/linux-2.6.18/atmel-mci-debugfs.patch b/packages/linux/linux-2.6.18/atmel-mci-debugfs.patch
new file mode 100644
index 0000000000..4570bd8e93
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-mci-debugfs.patch
@@ -0,0 +1,278 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Sun, 14 Jan 2007 19:07:06 +0100
+Subject: [ATMEL MCI] Add debugfs support
+
+Export some of the atmel-mci driver state through debugfs. More
+specifically:
+ * The MCI hardware registers
+ * The request currently being processed
+ * Pending and processed event masks
+
+Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+---
+ drivers/mmc/atmel-mci.c | 230 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 230 insertions(+)
+
+Index: linux-2.6.18-avr32/drivers/mmc/atmel-mci.c
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/mmc/atmel-mci.c 2007-01-15 15:35:45.000000000 +0100
++++ linux-2.6.18-avr32/drivers/mmc/atmel-mci.c 2007-01-15 15:38:05.000000000 +0100
+@@ -79,6 +79,14 @@ struct atmel_mci {
+ struct clk *mck;
+ struct mmci_platform_data *board;
+ struct platform_device *pdev;
++
++#ifdef CONFIG_DEBUG_FS
++ struct dentry *debugfs_root;
++ struct dentry *debugfs_regs;
++ struct dentry *debugfs_req;
++ struct dentry *debugfs_pending_events;
++ struct dentry *debugfs_completed_events;
++#endif
+ };
+
+ /* Those printks take an awful lot of time... */
+@@ -90,6 +98,224 @@ static unsigned int fmax = 1000000U;
+ module_param(fmax, uint, 0444);
+ MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
+
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++
++#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
++
++struct req_dbg_data {
++ unsigned int nbytes;
++ char str[DBG_REQ_BUF_SIZE];
++};
++
++static int req_dbg_open(struct inode *inode, struct file *file)
++{
++ struct atmel_mci *host;
++ struct mmc_request *mrq;
++ struct mmc_command *cmd, *stop;
++ struct mmc_data *data;
++ struct req_dbg_data *priv;
++ char *str;
++ unsigned long n = 0;
++
++ priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++ str = priv->str;
++
++ mutex_lock(&inode->i_mutex);
++ host = inode->u.generic_ip;
++
++ spin_lock_irq(&host->mmc->lock);
++ mrq = host->mrq;
++ if (mrq) {
++ cmd = mrq->cmd;
++ data = mrq->data;
++ stop = mrq->stop;
++ n = snprintf(str, DBG_REQ_BUF_SIZE,
++ "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
++ cmd->opcode, cmd->arg, cmd->flags,
++ cmd->resp[0], cmd->resp[1], cmd->resp[2],
++ cmd->resp[3], cmd->error);
++ if (n < DBG_REQ_BUF_SIZE && data)
++ n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
++ "DATA %u * %u (%u) %x (err %u)\n",
++ data->blocks, data->blksz,
++ data->bytes_xfered, data->flags,
++ data->error);
++ if (n < DBG_REQ_BUF_SIZE && stop)
++ n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
++ "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
++ stop->opcode, stop->arg, stop->flags,
++ stop->resp[0], stop->resp[1],
++ stop->resp[2], stop->resp[3],
++ stop->error);
++ }
++ spin_unlock_irq(&host->mmc->lock);
++ mutex_unlock(&inode->i_mutex);
++
++ priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
++ file->private_data = priv;
++
++ return 0;
++}
++
++static int req_dbg_read(struct file *file, char __user *buf,
++ size_t nbytes, loff_t *ppos)
++{
++ struct req_dbg_data *priv = file->private_data;
++
++ return simple_read_from_buffer(buf, nbytes, ppos,
++ priv->str, priv->nbytes);
++}
++
++static int req_dbg_release(struct inode *inode, struct file *file)
++{
++ kfree(file->private_data);
++ return 0;
++}
++
++static const struct file_operations req_dbg_fops = {
++ .owner = THIS_MODULE,
++ .open = req_dbg_open,
++ .llseek = no_llseek,
++ .read = req_dbg_read,
++ .release = req_dbg_release,
++};
++
++static int regs_dbg_open(struct inode *inode, struct file *file)
++{
++ struct atmel_mci *host;
++ unsigned int i;
++ u32 *data;
++ int ret = -ENOMEM;
++
++ mutex_lock(&inode->i_mutex);
++ host = inode->u.generic_ip;
++ data = kmalloc(inode->i_size, GFP_KERNEL);
++ if (!data)
++ goto out;
++
++ spin_lock_irq(&host->mmc->lock);
++ for (i = 0; i < inode->i_size / 4; i++)
++ data[i] = __raw_readl(host->regs + i * 4);
++ spin_unlock_irq(&host->mmc->lock);
++
++ file->private_data = data;
++ ret = 0;
++
++out:
++ mutex_unlock(&inode->i_mutex);
++
++ return ret;
++}
++
++static ssize_t regs_dbg_read(struct file *file, char __user *buf,
++ size_t nbytes, loff_t *ppos)
++{
++ struct inode *inode = file->f_dentry->d_inode;
++ int ret;
++
++ mutex_lock(&inode->i_mutex);
++ ret = simple_read_from_buffer(buf, nbytes, ppos,
++ file->private_data,
++ file->f_dentry->d_inode->i_size);
++ mutex_unlock(&inode->i_mutex);
++
++ return ret;
++}
++
++static int regs_dbg_release(struct inode *inode, struct file *file)
++{
++ kfree(file->private_data);
++ return 0;
++}
++
++static const struct file_operations regs_dbg_fops = {
++ .owner = THIS_MODULE,
++ .open = regs_dbg_open,
++ .llseek = generic_file_llseek,
++ .read = regs_dbg_read,
++ .release = regs_dbg_release,
++};
++
++static void atmci_init_debugfs(struct atmel_mci *host)
++{
++ struct mmc_host *mmc;
++ struct dentry *root, *regs;
++ struct resource *res;
++
++ mmc = host->mmc;
++ root = debugfs_create_dir(mmc_hostname(mmc), NULL);
++ if (IS_ERR(root) || !root)
++ goto err_root;
++ host->debugfs_root = root;
++
++ regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
++ if (!regs)
++ goto err_regs;
++
++ res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
++ regs->d_inode->i_size = res->end - res->start + 1;
++ host->debugfs_regs = regs;
++
++ host->debugfs_req = debugfs_create_file("req", 0400, root,
++ host, &req_dbg_fops);
++ if (!host->debugfs_req)
++ goto err_req;
++
++ host->debugfs_pending_events
++ = debugfs_create_u32("pending_events", 0400, root,
++ (u32 *)&host->pending_events);
++ if (!host->debugfs_pending_events)
++ goto err_pending_events;
++
++ host->debugfs_completed_events
++ = debugfs_create_u32("completed_events", 0400, root,
++ (u32 *)&host->completed_events);
++ if (!host->debugfs_completed_events)
++ goto err_completed_events;
++
++ return;
++
++err_completed_events:
++ debugfs_remove(host->debugfs_pending_events);
++err_pending_events:
++ debugfs_remove(host->debugfs_req);
++err_req:
++ debugfs_remove(host->debugfs_regs);
++err_regs:
++ debugfs_remove(host->debugfs_root);
++err_root:
++ host->debugfs_root = NULL;
++ dev_err(&host->pdev->dev,
++ "failed to initialize debugfs for %s\n",
++ mmc_hostname(mmc));
++}
++
++static void atmci_cleanup_debugfs(struct atmel_mci *host)
++{
++ if (host->debugfs_root) {
++ debugfs_remove(host->debugfs_completed_events);
++ debugfs_remove(host->debugfs_pending_events);
++ debugfs_remove(host->debugfs_req);
++ debugfs_remove(host->debugfs_regs);
++ debugfs_remove(host->debugfs_root);
++ host->debugfs_root = NULL;
++ }
++}
++#else
++static inline void atmci_init_debugfs(struct atmel_mci *host)
++{
++
++}
++
++static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
++{
++
++}
++#endif /* CONFIG_DEBUG_FS */
++
+ static inline unsigned int ns_to_clocks(struct atmel_mci *host,
+ unsigned int ns)
+ {
+@@ -709,6 +935,8 @@ static int __devinit atmci_probe(struct
+ printk(KERN_INFO "%s: Atmel MCI controller at 0x%08lx irq %d\n",
+ mmc_hostname(mmc), host->mapbase, irq);
+
++ atmci_init_debugfs(host);
++
+ return 0;
+
+ out_free_irq:
+@@ -734,6 +962,8 @@ static int __devexit atmci_remove(struct
+ platform_set_drvdata(pdev, NULL);
+
+ if (host) {
++ atmci_cleanup_debugfs(host);
++
+ mmc_remove_host(host->mmc);
+
+ mci_writel(host, IDR, ~0UL);
diff --git a/packages/linux/linux-2.6.18/atmel-mci-init-nr_blocks-in-dma-request.patch b/packages/linux/linux-2.6.18/atmel-mci-init-nr_blocks-in-dma-request.patch
new file mode 100644
index 0000000000..d6d91ae0e8
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-mci-init-nr_blocks-in-dma-request.patch
@@ -0,0 +1,47 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Sun, 14 Jan 2007 19:07:06 +0100
+Subject: [ATMEL MCI] Initialize the nr_blocks member of the dma request
+
+It seems like the mmc driver might get asked to write less data
+than what is available in the associated scatterlist. Previously,
+the dmac driver assumed that an sg request should transfer all
+the data in the scatterlist, which would break in this case.
+
+Resolve this by passing the number of blocks to transfer explicitly.
+This will probably fix a number of cases where the mmc controller
+seemed to be out of sync with the dma controller.
+
+Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+---
+ drivers/mmc/atmel-mci.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+Index: linux-2.6.18-avr32/drivers/mmc/atmel-mci.c
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/mmc/atmel-mci.c 2007-01-15 15:39:13.000000000 +0100
++++ linux-2.6.18-avr32/drivers/mmc/atmel-mci.c 2007-01-15 15:39:25.000000000 +0100
+@@ -51,7 +51,6 @@ struct atmel_mci_dma {
+ struct dma_request_sg req;
+ unsigned short rx_periph_id;
+ unsigned short tx_periph_id;
+- int blocks_left;
+ };
+
+ struct atmel_mci {
+@@ -428,6 +427,7 @@ static u32 atmci_prepare_data(struct mmc
+ mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
+ | MCI_BF(BLKLEN, data->blksz)));
+ host->dma.req.block_size = data->blksz;
++ host->dma.req.nr_blocks = data->blocks;
+
+ cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
+ if (data->flags & MMC_DATA_STREAM)
+@@ -454,7 +454,6 @@ static u32 atmci_prepare_data(struct mmc
+ host->dma.req.data_reg = host->mapbase + MCI_TDR;
+ }
+ host->dma.req.sg = data->sg;
+- host->dma.blocks_left = data->blocks;
+
+ dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
+
diff --git a/packages/linux/linux-2.6.18/atmel-mmc-host-driver.patch b/packages/linux/linux-2.6.18/atmel-mmc-host-driver.patch
new file mode 100644
index 0000000000..b7d7e8ae3f
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-mmc-host-driver.patch
@@ -0,0 +1,986 @@
+From nobody Mon Sep 17 00:00:00 2001
+From: HÃ¥vard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Nov 18 17:20:29 2005 +0100
+Subject: [PATCH] AVR32: MMC Host Driver
+
+---
+
+ drivers/mmc/Kconfig | 10
+ drivers/mmc/Makefile | 1
+ drivers/mmc/atmel-mci.c | 738 ++++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/mmc/atmel-mci.h | 192 ++++++++++++
+ 4 files changed, 941 insertions(+)
+
+Index: linux-2.6.18-avr32/drivers/mmc/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/mmc/Kconfig 2007-01-15 10:14:40.000000000 +0100
++++ linux-2.6.18-avr32/drivers/mmc/Kconfig 2007-01-15 10:14:46.000000000 +0100
+@@ -71,6 +71,16 @@ config MMC_OMAP
+
+ If unsure, say N.
+
++config MMC_ATMELMCI
++ tristate "Atmel Multimedia Card Interface support"
++ depends on AVR32 && MMC
++ help
++ This selects the Atmel Multimedia Card Interface. If you have
++ a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
++ slot, say Y or M here.
++
++ If unsure, say N.
++
+ config MMC_WBSD
+ tristate "Winbond W83L51xD SD/MMC Card Interface support"
+ depends on MMC && ISA_DMA_API
+Index: linux-2.6.18-avr32/drivers/mmc/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/mmc/Makefile 2007-01-15 10:14:40.000000000 +0100
++++ linux-2.6.18-avr32/drivers/mmc/Makefile 2007-01-15 10:14:46.000000000 +0100
+@@ -23,6 +23,7 @@ obj-$(CONFIG_MMC_WBSD) += wbsd.o
+ obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
+ obj-$(CONFIG_MMC_OMAP) += omap.o
+ obj-$(CONFIG_MMC_AT91RM9200) += at91_mci.o
++obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
+
+ mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o
+
+Index: linux-2.6.18-avr32/drivers/mmc/atmel-mci.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/mmc/atmel-mci.c 2007-01-15 10:31:55.000000000 +0100
+@@ -0,0 +1,738 @@
++/*
++ * Atmel MultiMedia Card Interface driver
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/blkdev.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <linux/mmc/host.h>
++#include <linux/mmc/protocol.h>
++
++#include <asm/dma-controller.h>
++#include <asm/io.h>
++
++#include "atmel-mci.h"
++
++#define DRIVER_NAME "mmci"
++
++#define MCI_CMD_ERROR_FLAGS (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | \
++ MCI_BIT(RCRCE) | MCI_BIT(RENDE) | \
++ MCI_BIT(RTOE))
++#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
++ MCI_BIT(OVRE) | MCI_BIT(UNRE))
++
++enum {
++ EVENT_CMD_COMPLETE = 0,
++ EVENT_CMD_ERROR,
++ EVENT_DATA_COMPLETE,
++ EVENT_DATA_ERROR,
++ EVENT_STOP_SENT,
++ EVENT_STOP_COMPLETE,
++ EVENT_STOP_ERROR,
++ EVENT_DMA_ERROR,
++};
++
++struct atmel_mci_dma {
++ struct dma_request_sg req;
++ unsigned short rx_periph_id;
++ unsigned short tx_periph_id;
++ int blocks_left;
++};
++
++struct atmel_mci {
++ struct mmc_host *mmc;
++ void __iomem *regs;
++ struct atmel_mci_dma dma;
++
++ struct mmc_request *mrq;
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++
++ u32 stop_cmdr;
++ u32 stop_iflags;
++
++ struct tasklet_struct tasklet;
++ unsigned long pending_events;
++ unsigned long completed_events;
++ u32 error_status;
++
++ unsigned long bus_hz;
++ unsigned long mapbase;
++ struct clk *mck;
++ struct platform_device *pdev;
++};
++
++/* Those printks take an awful lot of time... */
++#ifndef DEBUG
++static unsigned int fmax = 15000000U;
++#else
++static unsigned int fmax = 1000000U;
++#endif
++module_param(fmax, uint, 0444);
++MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
++
++static inline unsigned int ns_to_clocks(struct atmel_mci *host,
++ unsigned int ns)
++{
++ return (ns * (host->bus_hz / 1000000) + 999) / 1000;
++}
++
++static void atmci_set_timeout(struct atmel_mci *host,
++ struct mmc_data *data)
++{
++ static unsigned dtomul_to_shift[] = {
++ 0, 4, 7, 8, 10, 12, 16, 20
++ };
++ unsigned timeout;
++ unsigned dtocyc, dtomul;
++
++ timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
++
++ for (dtomul = 0; dtomul < 8; dtomul++) {
++ unsigned shift = dtomul_to_shift[dtomul];
++ dtocyc = (timeout + (1 << shift) - 1) >> shift;
++ if (dtocyc < 15)
++ break;
++ }
++
++ if (dtomul >= 8) {
++ dtomul = 7;
++ dtocyc = 15;
++ }
++
++ pr_debug("%s: setting timeout to %u cycles\n",
++ mmc_hostname(host->mmc),
++ dtocyc << dtomul_to_shift[dtomul]);
++ mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
++ | MCI_BF(DTOCYC, dtocyc)));
++}
++
++/*
++ * Return mask with interrupt flags to be handled for this command.
++ */
++static u32 atmci_prepare_command(struct mmc_host *mmc,
++ struct mmc_command *cmd,
++ u32 *cmd_flags)
++{
++ u32 cmdr;
++ u32 iflags;
++
++ cmd->error = MMC_ERR_NONE;
++
++ cmdr = 0;
++ BUG_ON(MCI_BFEXT(CMDNB, cmdr) != 0);
++ cmdr = MCI_BFINS(CMDNB, cmd->opcode, cmdr);
++
++ if (cmd->flags & MMC_RSP_PRESENT) {
++ if (cmd->flags & MMC_RSP_136)
++ cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
++ else
++ cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
++ }
++
++ /*
++ * This should really be MAXLAT_5 for CMD2 and ACMD41, but
++ * it's too difficult to determine whether this is an ACMD or
++ * not. Better make it 64.
++ */
++ cmdr |= MCI_BIT(MAXLAT);
++
++ if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
++ cmdr |= MCI_BIT(OPDCMD);
++
++ iflags = MCI_BIT(CMDRDY) | MCI_CMD_ERROR_FLAGS;
++ if (!(cmd->flags & MMC_RSP_CRC))
++ iflags &= ~MCI_BIT(RCRCE);
++
++ pr_debug("%s: cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
++ mmc_hostname(mmc), cmd->opcode, cmd->arg, cmd->flags,
++ (unsigned long)cmdr);
++
++ *cmd_flags = cmdr;
++ return iflags;
++}
++
++static void atmci_start_command(struct atmel_mci *host,
++ struct mmc_command *cmd,
++ u32 cmd_flags)
++{
++ WARN_ON(host->cmd);
++ host->cmd = cmd;
++
++ mci_writel(host, ARGR, cmd->arg);
++ mci_writel(host, CMDR, cmd_flags);
++
++ if (cmd->data)
++ dma_start_request(host->dma.req.req.dmac,
++ host->dma.req.req.channel);
++}
++
++/*
++ * Returns a mask of flags to be set in the command register when the
++ * command to start the transfer is to be sent.
++ */
++static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
++{
++ struct atmel_mci *host = mmc_priv(mmc);
++ u32 cmd_flags;
++
++ WARN_ON(host->data);
++ host->data = data;
++
++ atmci_set_timeout(host, data);
++ mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
++ | MCI_BF(BLKLEN, data->blksz)));
++ host->dma.req.block_size = data->blksz;
++
++ cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
++ if (data->flags & MMC_DATA_STREAM)
++ cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
++ else if (data->blocks > 1)
++ cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
++ else
++ cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
++
++ if (data->flags & MMC_DATA_READ) {
++ cmd_flags |= MCI_BIT(TRDIR);
++ host->dma.req.nr_sg
++ = dma_map_sg(&host->pdev->dev, data->sg,
++ data->sg_len, DMA_FROM_DEVICE);
++ host->dma.req.periph_id = host->dma.rx_periph_id;
++ host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
++ host->dma.req.data_reg = host->mapbase + MCI_RDR;
++ } else {
++ host->dma.req.nr_sg
++ = dma_map_sg(&host->pdev->dev, data->sg,
++ data->sg_len, DMA_TO_DEVICE);
++ host->dma.req.periph_id = host->dma.tx_periph_id;
++ host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
++ host->dma.req.data_reg = host->mapbase + MCI_TDR;
++ }
++ host->dma.req.sg = data->sg;
++ host->dma.blocks_left = data->blocks;
++
++ dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
++
++ return cmd_flags;
++}
++
++static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct atmel_mci *host = mmc_priv(mmc);
++ struct mmc_data *data = mrq->data;
++ u32 iflags;
++ u32 cmdflags = 0;
++
++ iflags = mci_readl(host, IMR);
++ if (iflags)
++ printk("WARNING: IMR=0x%08x\n", mci_readl(host, IMR));
++
++ WARN_ON(host->mrq != NULL);
++ host->mrq = mrq;
++ host->pending_events = 0;
++ host->completed_events = 0;
++
++ iflags = atmci_prepare_command(mmc, mrq->cmd, &cmdflags);
++
++ if (mrq->stop) {
++ BUG_ON(!data);
++
++ host->stop_iflags = atmci_prepare_command(mmc, mrq->stop,
++ &host->stop_cmdr);
++ host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
++ if (!(data->flags & MMC_DATA_WRITE))
++ host->stop_cmdr |= MCI_BIT(TRDIR);
++ if (data->flags & MMC_DATA_STREAM)
++ host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
++ else
++ host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
++ }
++ if (data) {
++ cmdflags |= atmci_prepare_data(mmc, data);
++ iflags |= MCI_DATA_ERROR_FLAGS;
++ }
++
++ atmci_start_command(host, mrq->cmd, cmdflags);
++ mci_writel(host, IER, iflags);
++}
++
++static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++ struct atmel_mci *host = mmc_priv(mmc);
++
++ if (ios->clock) {
++ u32 clkdiv;
++
++ clkdiv = host->bus_hz / (2 * ios->clock) - 1;
++ if (clkdiv > 255)
++ clkdiv = 255;
++ mci_writel(host, MR, (clkdiv
++ | MCI_BIT(WRPROOF)
++ | MCI_BIT(RDPROOF)));
++ }
++
++ switch (ios->bus_width) {
++ case MMC_BUS_WIDTH_1:
++ mci_writel(host, SDCR, 0);
++ break;
++ case MMC_BUS_WIDTH_4:
++ mci_writel(host, SDCR, MCI_BIT(SDCBUS));
++ break;
++ }
++
++ switch (ios->power_mode) {
++ case MMC_POWER_OFF:
++ mci_writel(host, CR, MCI_BIT(MCIDIS));
++ break;
++ case MMC_POWER_UP:
++ mci_writel(host, CR, MCI_BIT(SWRST));
++ break;
++ case MMC_POWER_ON:
++ mci_writel(host, CR, MCI_BIT(MCIEN));
++ break;
++ }
++}
++
++static struct mmc_host_ops atmci_ops = {
++ .request = atmci_request,
++ .set_ios = atmci_set_ios,
++};
++
++static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct atmel_mci *host = mmc_priv(mmc);
++
++ WARN_ON(host->cmd || host->data);
++ host->mrq = NULL;
++
++ mmc_request_done(mmc, mrq);
++}
++
++static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
++ u32 flags)
++{
++ struct atmel_mci *host = mmc_priv(mmc);
++
++ atmci_start_command(host, data->stop, host->stop_cmdr | flags);
++ mci_writel(host, IER, host->stop_iflags);
++}
++
++static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
++{
++ host->data = NULL;
++ dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
++ ((data->flags & MMC_DATA_WRITE)
++ ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
++
++ /*
++ * Data might complete before command for very short transfers
++ * (like READ_SCR)
++ */
++ if (test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
++ && (!data->stop
++ || test_bit(EVENT_STOP_COMPLETE, &host->completed_events)))
++ atmci_request_end(host->mmc, data->mrq);
++}
++
++static void atmci_command_error(struct mmc_host *mmc,
++ struct mmc_command *cmd,
++ u32 status)
++{
++ pr_debug("%s: command error: status=0x%08x\n",
++ mmc_hostname(mmc), status);
++
++ if (status & MCI_BIT(RTOE))
++ cmd->error = MMC_ERR_TIMEOUT;
++ else if (status & MCI_BIT(RCRCE))
++ cmd->error = MMC_ERR_BADCRC;
++ else
++ cmd->error = MMC_ERR_FAILED;
++}
++
++static void atmci_tasklet_func(unsigned long priv)
++{
++ struct mmc_host *mmc = (struct mmc_host *)priv;
++ struct atmel_mci *host = mmc_priv(mmc);
++ struct mmc_request *mrq = host->mrq;
++ struct mmc_data *data = host->data;
++
++ pr_debug("atmci_tasklet: pending/completed/mask %lx/%lx/%x\n",
++ host->pending_events, host->completed_events,
++ mci_readl(host, IMR));
++
++ if (test_and_clear_bit(EVENT_CMD_ERROR, &host->pending_events)) {
++ struct mmc_command *cmd;
++
++ set_bit(EVENT_CMD_ERROR, &host->completed_events);
++ clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
++ cmd = host->mrq->cmd;
++
++ if (cmd->data) {
++ dma_stop_request(host->dma.req.req.dmac,
++ host->dma.req.req.channel);
++ host->data = NULL;
++ }
++
++ atmci_command_error(mmc, cmd, host->error_status);
++ atmci_request_end(mmc, cmd->mrq);
++ }
++ if (test_and_clear_bit(EVENT_STOP_ERROR, &host->pending_events)) {
++ set_bit(EVENT_STOP_ERROR, &host->completed_events);
++ clear_bit(EVENT_STOP_COMPLETE, &host->pending_events);
++ atmci_command_error(mmc, host->mrq->stop,
++ host->error_status);
++ if (!host->data)
++ atmci_request_end(mmc, host->mrq);
++ }
++ if (test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
++ set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
++ if (!mrq->data
++ || test_bit(EVENT_DATA_COMPLETE, &host->completed_events))
++ atmci_request_end(mmc, mrq);
++ }
++ if (test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)) {
++ set_bit(EVENT_STOP_COMPLETE, &host->completed_events);
++ if (test_bit(EVENT_DATA_COMPLETE, &host->completed_events))
++ atmci_request_end(mmc, mrq);
++ }
++ if (test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)) {
++ set_bit(EVENT_DMA_ERROR, &host->completed_events);
++ clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
++
++ /* DMA controller got bus error => invalid address */
++ data->error = MMC_ERR_INVALID;
++
++ printk(KERN_DEBUG "%s: dma error after %u bytes xfered\n",
++ mmc_hostname(mmc), host->data->bytes_xfered);
++
++ if (data->stop
++ && !test_and_set_bit(EVENT_STOP_SENT,
++ &host->completed_events))
++ /* TODO: Check if card is still present */
++ send_stop_cmd(host->mmc, data, 0);
++
++ atmci_data_complete(host, data);
++ }
++ if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
++ u32 status = host->error_status;
++
++ set_bit(EVENT_DATA_ERROR, &host->completed_events);
++ clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
++
++ dma_stop_request(host->dma.req.req.dmac,
++ host->dma.req.req.channel);
++
++ printk(KERN_DEBUG "%s: data error: status=0x%08x\n",
++ mmc_hostname(host->mmc), status);
++
++ if (status & MCI_BIT(DCRCE)) {
++ printk(KERN_DEBUG "%s: Data CRC error\n",
++ mmc_hostname(host->mmc));
++ data->error = MMC_ERR_BADCRC;
++ } else if (status & MCI_BIT(DTOE)) {
++ printk(KERN_DEBUG "%s: Data Timeout error\n",
++ mmc_hostname(host->mmc));
++ data->error = MMC_ERR_TIMEOUT;
++ } else {
++ printk(KERN_DEBUG "%s: Data FIFO error\n",
++ mmc_hostname(host->mmc));
++ data->error = MMC_ERR_FIFO;
++ }
++ printk(KERN_DEBUG "%s: Bytes xfered: %u\n",
++ mmc_hostname(host->mmc), data->bytes_xfered);
++
++ if (data->stop
++ && !test_and_set_bit(EVENT_STOP_SENT, &host->completed_events))
++ /* TODO: Check if card is still present */
++ send_stop_cmd(host->mmc, data, 0);
++
++ atmci_data_complete(host, data);
++ }
++ if (test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
++ set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
++ data->bytes_xfered = data->blocks * data->blksz;
++ atmci_data_complete(host, data);
++ }
++}
++
++static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
++{
++ struct atmel_mci *host = mmc_priv(mmc);
++ struct mmc_command *cmd = host->cmd;
++
++ /*
++ * Read the response now so that we're free to send a new
++ * command immediately.
++ */
++ cmd->resp[0] = mci_readl(host, RSPR);
++ cmd->resp[1] = mci_readl(host, RSPR);
++ cmd->resp[2] = mci_readl(host, RSPR);
++ cmd->resp[3] = mci_readl(host, RSPR);
++
++ mci_writel(host, IDR, MCI_BIT(CMDRDY) | MCI_CMD_ERROR_FLAGS);
++ host->cmd = NULL;
++
++ if (test_bit(EVENT_STOP_SENT, &host->completed_events))
++ set_bit(EVENT_STOP_COMPLETE, &host->pending_events);
++ else
++ set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
++
++ tasklet_schedule(&host->tasklet);
++}
++
++static void atmci_xfer_complete(struct dma_request *_req)
++{
++ struct dma_request_sg *req = to_dma_request_sg(_req);
++ struct atmel_mci_dma *dma;
++ struct atmel_mci *host;
++ struct mmc_data *data;
++
++ dma = container_of(req, struct atmel_mci_dma, req);
++ host = container_of(dma, struct atmel_mci, dma);
++ data = host->data;
++
++ if (data->stop && !test_and_set_bit(EVENT_STOP_SENT,
++ &host->completed_events))
++ send_stop_cmd(host->mmc, data, 0);
++
++ if (data->flags & MMC_DATA_READ) {
++ mci_writel(host, IDR, MCI_DATA_ERROR_FLAGS);
++ set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
++ tasklet_schedule(&host->tasklet);
++ } else {
++ /*
++ * For the WRITE case, wait for NOTBUSY. This function
++ * is called when everything has been written to the
++ * controller, not when the card is done programming.
++ */
++ mci_writel(host, IER, MCI_BIT(NOTBUSY));
++ }
++}
++
++static void atmci_dma_error(struct dma_request *_req)
++{
++ struct dma_request_sg *req = to_dma_request_sg(_req);
++ struct atmel_mci_dma *dma;
++ struct atmel_mci *host;
++
++ dma = container_of(req, struct atmel_mci_dma, req);
++ host = container_of(dma, struct atmel_mci, dma);
++
++ mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
++ | MCI_DATA_ERROR_FLAGS));
++
++ set_bit(EVENT_DMA_ERROR, &host->pending_events);
++ tasklet_schedule(&host->tasklet);
++}
++
++static irqreturn_t atmci_interrupt(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct mmc_host *mmc = dev_id;
++ struct atmel_mci *host = mmc_priv(mmc);
++ u32 status, mask, pending;
++
++ spin_lock(&mmc->lock);
++
++ status = mci_readl(host, SR);
++ mask = mci_readl(host, IMR);
++ pending = status & mask;
++
++ do {
++ if (pending & MCI_CMD_ERROR_FLAGS) {
++ mci_writel(host, IDR, (MCI_BIT(CMDRDY)
++ | MCI_BIT(NOTBUSY)
++ | MCI_CMD_ERROR_FLAGS
++ | MCI_DATA_ERROR_FLAGS));
++ host->error_status = status;
++ host->cmd = NULL;
++ if (test_bit(EVENT_STOP_SENT, &host->completed_events))
++ set_bit(EVENT_STOP_ERROR, &host->pending_events);
++ else
++ set_bit(EVENT_CMD_ERROR, &host->pending_events);
++ tasklet_schedule(&host->tasklet);
++ break;
++ }
++ if (pending & MCI_DATA_ERROR_FLAGS) {
++ mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
++ | MCI_DATA_ERROR_FLAGS));
++ host->error_status = status;
++ set_bit(EVENT_DATA_ERROR, &host->pending_events);
++ tasklet_schedule(&host->tasklet);
++ break;
++ }
++ if (pending & MCI_BIT(CMDRDY))
++ atmci_cmd_interrupt(mmc, status);
++ if (pending & MCI_BIT(NOTBUSY)) {
++ mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
++ | MCI_DATA_ERROR_FLAGS));
++ set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
++ tasklet_schedule(&host->tasklet);
++ }
++
++ status = mci_readl(host, SR);
++ mask = mci_readl(host, IMR);
++ pending = status & mask;
++ } while (pending);
++
++ spin_unlock(&mmc->lock);
++
++ return IRQ_HANDLED;
++}
++
++static int __devinit atmci_probe(struct platform_device *pdev)
++{
++ struct atmel_mci *host;
++ struct mmc_host *mmc;
++ struct resource *regs;
++ int irq;
++ int ret;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++
++ mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
++ if (!mmc)
++ return -ENOMEM;
++
++ host = mmc_priv(mmc);
++ host->pdev = pdev;
++ host->mmc = mmc;
++
++ host->mck = clk_get(&pdev->dev, "mck");
++ if (IS_ERR(host->mck)) {
++ ret = PTR_ERR(host->mck);
++ goto out_free_host;
++ }
++ clk_enable(host->mck);
++
++ ret = -ENOMEM;
++ host->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!host->regs)
++ goto out_disable_clk;
++
++ host->bus_hz = clk_get_rate(host->mck);
++ host->mapbase = regs->start;
++
++ mmc->ops = &atmci_ops;
++ mmc->f_min = (host->bus_hz + 511) / 512;
++ mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
++ mmc->ocr_avail = 0x00100000;
++ mmc->caps |= MMC_CAP_4_BIT_DATA;
++
++ tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
++
++ ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
++ if (ret)
++ goto out_unmap;
++
++ /* TODO: Get this information from platform data */
++ ret = -ENOMEM;
++ host->dma.req.req.dmac = find_dma_controller(0);
++ if (!host->dma.req.req.dmac) {
++ printk(KERN_ERR
++ "mmci: No DMA controller available, aborting\n");
++ goto out_free_irq;
++ }
++ ret = dma_alloc_channel(host->dma.req.req.dmac);
++ if (ret < 0) {
++ printk(KERN_ERR
++ "mmci: Unable to allocate DMA channel, aborting\n");
++ goto out_free_irq;
++ }
++ host->dma.req.req.channel = ret;
++ host->dma.req.width = DMA_WIDTH_32BIT;
++ host->dma.req.req.xfer_complete = atmci_xfer_complete;
++ host->dma.req.req.block_complete = NULL; // atmci_block_complete;
++ host->dma.req.req.error = atmci_dma_error;
++ host->dma.rx_periph_id = 0;
++ host->dma.tx_periph_id = 1;
++
++ mci_writel(host, CR, MCI_BIT(SWRST));
++ mci_writel(host, IDR, ~0UL);
++ mci_writel(host, CR, MCI_BIT(MCIEN));
++
++ platform_set_drvdata(pdev, host);
++
++ mmc_add_host(mmc);
++
++ printk(KERN_INFO "%s: Atmel MCI controller at 0x%08lx irq %d\n",
++ mmc_hostname(mmc), host->mapbase, irq);
++
++ return 0;
++
++out_free_irq:
++ free_irq(irq, mmc);
++out_unmap:
++ iounmap(host->regs);
++out_disable_clk:
++ clk_disable(host->mck);
++ clk_put(host->mck);
++out_free_host:
++ mmc_free_host(mmc);
++ return ret;
++}
++
++static int __devexit atmci_remove(struct platform_device *pdev)
++{
++ struct atmel_mci *host = platform_get_drvdata(pdev);
++
++ platform_set_drvdata(pdev, NULL);
++
++ if (host) {
++ mmc_remove_host(host->mmc);
++
++ mci_writel(host, IDR, ~0UL);
++ mci_writel(host, CR, MCI_BIT(MCIDIS));
++ mci_readl(host, SR);
++
++ free_irq(platform_get_irq(pdev, 0), host->mmc);
++ iounmap(host->regs);
++
++ clk_disable(host->mck);
++ clk_put(host->mck);
++
++ mmc_free_host(host->mmc);
++ }
++ return 0;
++}
++
++static struct platform_driver atmci_driver = {
++ .probe = atmci_probe,
++ .remove = __devexit_p(atmci_remove),
++ .driver = {
++ .name = DRIVER_NAME,
++ },
++};
++
++static int __init atmci_init(void)
++{
++ return platform_driver_register(&atmci_driver);
++}
++
++static void __exit atmci_exit(void)
++{
++ platform_driver_unregister(&atmci_driver);
++}
++
++module_init(atmci_init);
++module_exit(atmci_exit);
++
++MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.18-avr32/drivers/mmc/atmel-mci.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/mmc/atmel-mci.h 2007-01-15 10:31:36.000000000 +0100
+@@ -0,0 +1,192 @@
++/*
++ * Atmel MultiMedia Card Interface driver
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
++#define __DRIVERS_MMC_ATMEL_MCI_H__
++
++/* MCI register offsets */
++#define MCI_CR 0x0000
++#define MCI_MR 0x0004
++#define MCI_DTOR 0x0008
++#define MCI_SDCR 0x000c
++#define MCI_ARGR 0x0010
++#define MCI_CMDR 0x0014
++#define MCI_BLKR 0x0018
++#define MCI_RSPR 0x0020
++#define MCI_RSPR1 0x0024
++#define MCI_RSPR2 0x0028
++#define MCI_RSPR3 0x002c
++#define MCI_RDR 0x0030
++#define MCI_TDR 0x0034
++#define MCI_SR 0x0040
++#define MCI_IER 0x0044
++#define MCI_IDR 0x0048
++#define MCI_IMR 0x004c
++
++/* Bitfields in CR */
++#define MCI_MCIEN_OFFSET 0
++#define MCI_MCIEN_SIZE 1
++#define MCI_MCIDIS_OFFSET 1
++#define MCI_MCIDIS_SIZE 1
++#define MCI_PWSEN_OFFSET 2
++#define MCI_PWSEN_SIZE 1
++#define MCI_PWSDIS_OFFSET 3
++#define MCI_PWSDIS_SIZE 1
++#define MCI_SWRST_OFFSET 7
++#define MCI_SWRST_SIZE 1
++
++/* Bitfields in MR */
++#define MCI_CLKDIV_OFFSET 0
++#define MCI_CLKDIV_SIZE 8
++#define MCI_PWSDIV_OFFSET 8
++#define MCI_PWSDIV_SIZE 3
++#define MCI_RDPROOF_OFFSET 11
++#define MCI_RDPROOF_SIZE 1
++#define MCI_WRPROOF_OFFSET 12
++#define MCI_WRPROOF_SIZE 1
++#define MCI_DMAPADV_OFFSET 14
++#define MCI_DMAPADV_SIZE 1
++#define MCI_BLKLEN_OFFSET 16
++#define MCI_BLKLEN_SIZE 16
++
++/* Bitfields in DTOR */
++#define MCI_DTOCYC_OFFSET 0
++#define MCI_DTOCYC_SIZE 4
++#define MCI_DTOMUL_OFFSET 4
++#define MCI_DTOMUL_SIZE 3
++
++/* Bitfields in SDCR */
++#define MCI_SDCSEL_OFFSET 0
++#define MCI_SDCSEL_SIZE 4
++#define MCI_SDCBUS_OFFSET 7
++#define MCI_SDCBUS_SIZE 1
++
++/* Bitfields in ARGR */
++#define MCI_ARG_OFFSET 0
++#define MCI_ARG_SIZE 32
++
++/* Bitfields in CMDR */
++#define MCI_CMDNB_OFFSET 0
++#define MCI_CMDNB_SIZE 6
++#define MCI_RSPTYP_OFFSET 6
++#define MCI_RSPTYP_SIZE 2
++#define MCI_SPCMD_OFFSET 8
++#define MCI_SPCMD_SIZE 3
++#define MCI_OPDCMD_OFFSET 11
++#define MCI_OPDCMD_SIZE 1
++#define MCI_MAXLAT_OFFSET 12
++#define MCI_MAXLAT_SIZE 1
++#define MCI_TRCMD_OFFSET 16
++#define MCI_TRCMD_SIZE 2
++#define MCI_TRDIR_OFFSET 18
++#define MCI_TRDIR_SIZE 1
++#define MCI_TRTYP_OFFSET 19
++#define MCI_TRTYP_SIZE 2
++
++/* Bitfields in BLKR */
++#define MCI_BCNT_OFFSET 0
++#define MCI_BCNT_SIZE 16
++
++/* Bitfields in RSPRn */
++#define MCI_RSP_OFFSET 0
++#define MCI_RSP_SIZE 32
++
++/* Bitfields in SR/IER/IDR/IMR */
++#define MCI_CMDRDY_OFFSET 0
++#define MCI_CMDRDY_SIZE 1
++#define MCI_RXRDY_OFFSET 1
++#define MCI_RXRDY_SIZE 1
++#define MCI_TXRDY_OFFSET 2
++#define MCI_TXRDY_SIZE 1
++#define MCI_BLKE_OFFSET 3
++#define MCI_BLKE_SIZE 1
++#define MCI_DTIP_OFFSET 4
++#define MCI_DTIP_SIZE 1
++#define MCI_NOTBUSY_OFFSET 5
++#define MCI_NOTBUSY_SIZE 1
++#define MCI_ENDRX_OFFSET 6
++#define MCI_ENDRX_SIZE 1
++#define MCI_ENDTX_OFFSET 7
++#define MCI_ENDTX_SIZE 1
++#define MCI_RXBUFF_OFFSET 14
++#define MCI_RXBUFF_SIZE 1
++#define MCI_TXBUFE_OFFSET 15
++#define MCI_TXBUFE_SIZE 1
++#define MCI_RINDE_OFFSET 16
++#define MCI_RINDE_SIZE 1
++#define MCI_RDIRE_OFFSET 17
++#define MCI_RDIRE_SIZE 1
++#define MCI_RCRCE_OFFSET 18
++#define MCI_RCRCE_SIZE 1
++#define MCI_RENDE_OFFSET 19
++#define MCI_RENDE_SIZE 1
++#define MCI_RTOE_OFFSET 20
++#define MCI_RTOE_SIZE 1
++#define MCI_DCRCE_OFFSET 21
++#define MCI_DCRCE_SIZE 1
++#define MCI_DTOE_OFFSET 22
++#define MCI_DTOE_SIZE 1
++#define MCI_OVRE_OFFSET 30
++#define MCI_OVRE_SIZE 1
++#define MCI_UNRE_OFFSET 31
++#define MCI_UNRE_SIZE 1
++
++/* Constants for DTOMUL */
++#define MCI_DTOMUL_1_CYCLE 0
++#define MCI_DTOMUL_16_CYCLES 1
++#define MCI_DTOMUL_128_CYCLES 2
++#define MCI_DTOMUL_256_CYCLES 3
++#define MCI_DTOMUL_1024_CYCLES 4
++#define MCI_DTOMUL_4096_CYCLES 5
++#define MCI_DTOMUL_65536_CYCLES 6
++#define MCI_DTOMUL_1048576_CYCLES 7
++
++/* Constants for RSPTYP */
++#define MCI_RSPTYP_NO_RESP 0
++#define MCI_RSPTYP_48_BIT 1
++#define MCI_RSPTYP_136_BIT 2
++
++/* Constants for SPCMD */
++#define MCI_SPCMD_NO_SPEC_CMD 0
++#define MCI_SPCMD_INIT_CMD 1
++#define MCI_SPCMD_SYNC_CMD 2
++#define MCI_SPCMD_INT_CMD 4
++#define MCI_SPCMD_INT_RESP 5
++
++/* Constants for TRCMD */
++#define MCI_TRCMD_NO_TRANS 0
++#define MCI_TRCMD_START_TRANS 1
++#define MCI_TRCMD_STOP_TRANS 2
++
++/* Constants for TRTYP */
++#define MCI_TRTYP_BLOCK 0
++#define MCI_TRTYP_MULTI_BLOCK 1
++#define MCI_TRTYP_STREAM 2
++
++/* Bit manipulation macros */
++#define MCI_BIT(name) \
++ (1 << MCI_##name##_OFFSET)
++#define MCI_BF(name,value) \
++ (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
++ << MCI_##name##_OFFSET)
++#define MCI_BFEXT(name,value) \
++ (((value) >> MCI_##name##_OFFSET) \
++ & ((1 << MCI_##name##_SIZE) - 1))
++#define MCI_BFINS(name,value,old) \
++ (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
++ << MCI_##name##_OFFSET)) \
++ | MCI_BF(name,value))
++
++/* Register access macros */
++#define mci_readl(port,reg) \
++ __raw_readl((port)->regs + MCI_##reg)
++#define mci_writel(port,reg,value) \
++ __raw_writel((value), (port)->regs + MCI_##reg)
++
++#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
diff --git a/packages/linux/linux-2.6.18/atmel-spi-master-driver.patch b/packages/linux/linux-2.6.18/atmel-spi-master-driver.patch
new file mode 100644
index 0000000000..d45f3c50c9
--- /dev/null
+++ b/packages/linux/linux-2.6.18/atmel-spi-master-driver.patch
@@ -0,0 +1,990 @@
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+On Mon, 5 Jun 2006 06:49:52 -0700
+David Brownell <david-b@pacbell.net> wrote:
+
+> Here's an updated version that compiles and partially runs
+> in the at91 world. If the avr32 code would switch to standard
+> APIs like <linux/platform_device.h> and <linux/clk.h> it should
+> behave there too, somewhat. Ignore the extra debug crap.
+
+Here's another update which includes most of the fixes in Dave's
+version and which has been verified on my STK1000 board.
+
+I had some trouble getting your version to turn on the display
+correctly, so I've reworked it as a series of smaller changes to figure
+out what broke it. You should probably verify that I didn't leave out
+anything important.
+
+Also, I didn't find CONFIG_SPI_AT91_MANUAL_CS defined anywhere, nor did
+I find cpu_is_at91sam9261() so I left out those changes.
+
+Can any of you test this on AT91 somehow? I'm not completely up to
+speed on my AT91RM9200-EK yet. Anyone else I should Cc?
+
+I can send you individual patches if you want. Here's the shortlog:
+
+Atmel SPI Driver
+spi_atmel: convert to platform_device framework
+spi_atmel: fix broken parameter validation in setup() and transfer()
+spi_atmel: Revert core workaround for max_speed_hz=0
+spi_atmel: Divide len by two if bits_per_word > 8
+spi_atmel: Enable ENDRX interrupt when rx_buf is set
+spi_atmel: Fix incorrect locking in interrupt routine
+spi_atmel: Line up variable declarations
+spi_atmel: Add some FIXMEs from David Brownell's patch
+spi_atmel: Header file cleanup
+spi_atmel: Introduce new_1 flag and use in sck speed setting
+spi_atmel: Move SPI_ATMEL above SPI_BITBANG
+Make SPI_ATMEL available to AT91
+
+
+>>From nobody Mon Sep 17 00:00:00 2001
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Apr 6 10:33:21 2006 +0200
+Subject: [PATCH] Atmel SPI Driver
+
+SPI master driver for the Atmel AT32/AT91 SPI Controller.
+
+UPDATED:
+ - against 2.6.17 + latest kernel.org GIT
+ - "at32_device" stuff removed from core of driver
+ - add platform_device glue, so at91 compiles
+ - use clock framework
+ - understand "old" (rm9200) vs "new" (sam9261, ap7000) silicon
+ (only different scbr definition, not csaat etc.)
+ - remove bogus spi core tweaks
+ - various fixes and cleanups
+
+The following changes from atmel-spi-driver-3.patch have been dropped:
+ - CONFIG_SPI_AT91_MANUAL_CS stuff. I can't find the symbol
+ anywhere
+ - DMA IRQ optimization by unmasking TXEMPTY when starting xfer
+ - All the code setting CSAAT.
+
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+On Mon, 5 Jun 2006 06:49:52 -0700
+David Brownell <david-b@pacbell.net> wrote:
+
+> Here's an updated version that compiles and partially runs
+> in the at91 world. If the avr32 code would switch to standard
+> APIs like <linux/platform_device.h> and <linux/clk.h> it should
+> behave there too, somewhat. Ignore the extra debug crap.
+
+Here's another update which includes most of the fixes in Dave's
+version and which has been verified on my STK1000 board.
+
+I had some trouble getting your version to turn on the display
+correctly, so I've reworked it as a series of smaller changes to figure
+out what broke it. You should probably verify that I didn't leave out
+anything important.
+
+Also, I didn't find CONFIG_SPI_AT91_MANUAL_CS defined anywhere, nor did
+I find cpu_is_at91sam9261() so I left out those changes.
+
+Can any of you test this on AT91 somehow? I'm not completely up to
+speed on my AT91RM9200-EK yet. Anyone else I should Cc?
+
+I can send you individual patches if you want. Here's the shortlog:
+
+Atmel SPI Driver
+spi_atmel: convert to platform_device framework
+spi_atmel: fix broken parameter validation in setup() and transfer()
+spi_atmel: Revert core workaround for max_speed_hz=0
+spi_atmel: Divide len by two if bits_per_word > 8
+spi_atmel: Enable ENDRX interrupt when rx_buf is set
+spi_atmel: Fix incorrect locking in interrupt routine
+spi_atmel: Line up variable declarations
+spi_atmel: Add some FIXMEs from David Brownell's patch
+spi_atmel: Header file cleanup
+spi_atmel: Introduce new_1 flag and use in sck speed setting
+spi_atmel: Move SPI_ATMEL above SPI_BITBANG
+Make SPI_ATMEL available to AT91
+
+
+>>From nobody Mon Sep 17 00:00:00 2001
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Apr 6 10:33:21 2006 +0200
+Subject: [PATCH] Atmel SPI Driver
+
+SPI master driver for the Atmel AT32/AT91 SPI Controller.
+
+UPDATED:
+ - against 2.6.17 + latest kernel.org GIT
+ - "at32_device" stuff removed from core of driver
+ - add platform_device glue, so at91 compiles
+ - use clock framework
+ - understand "old" (rm9200) vs "new" (sam9261, ap7000) silicon
+ (only different scbr definition, not csaat etc.)
+ - remove bogus spi core tweaks
+ - various fixes and cleanups
+
+The following changes from atmel-spi-driver-3.patch have been dropped:
+ - CONFIG_SPI_AT91_MANUAL_CS stuff. I can't find the symbol
+ anywhere
+ - DMA IRQ optimization by unmasking TXEMPTY when starting xfer
+ - All the code setting CSAAT.
+
+---
+ drivers/spi/Kconfig | 7
+ drivers/spi/Makefile | 1
+ drivers/spi/atmel_spi.c | 648 ++++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/spi/atmel_spi.h | 167 ++++++++++++
+ 4 files changed, 823 insertions(+)
+
+Index: linux-2.6.18-avr32/drivers/spi/Kconfig
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/spi/Kconfig 2006-11-29 16:55:10.000000000 +0100
++++ linux-2.6.18-avr32/drivers/spi/Kconfig 2006-11-29 16:55:59.000000000 +0100
+@@ -51,6 +51,13 @@ config SPI_MASTER
+ comment "SPI Master Controller Drivers"
+ depends on SPI_MASTER
+
++config SPI_ATMEL
++ tristate "Atmel SPI Controller"
++ depends on (ARCH_AT91 || AVR32) && SPI_MASTER
++ help
++ This selects a driver for the Atmel SPI Controller, present on
++ many AT32 (AVR32) and AT91 (ARM) chips.
++
+ config SPI_BITBANG
+ tristate "Bitbanging SPI master"
+ depends on SPI_MASTER && EXPERIMENTAL
+Index: linux-2.6.18-avr32/drivers/spi/Makefile
+===================================================================
+--- linux-2.6.18-avr32.orig/drivers/spi/Makefile 2006-11-29 16:55:10.000000000 +0100
++++ linux-2.6.18-avr32/drivers/spi/Makefile 2006-11-29 16:55:59.000000000 +0100
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_MASTER) += spi.o
+
+ # SPI master controller drivers (bus)
+ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
++obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
+ obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
+ obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
+ obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o
+Index: linux-2.6.18-avr32/drivers/spi/atmel_spi.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/spi/atmel_spi.c 2006-11-29 17:10:19.000000000 +0100
+@@ -0,0 +1,648 @@
++/*
++ * Driver for Atmel AT32 and AT91 SPI Controllers
++ *
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/spi/spi.h>
++
++#include <asm/io.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++
++#include "atmel_spi.h"
++
++/*
++ * The core SPI transfer engine just talks to a register bank to set up
++ * DMA transfers; transfer queue progress is driven by IRQs. The clock
++ * framework provides the base clock, subdivided for each spi_device.
++ *
++ * Newer controllers, marked with "new_1" flag, have:
++ * - CR.LASTXFER
++ * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
++ * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
++ * - SPI_CSRx.CSAAT
++ * - SPI_CSRx.SBCR allows faster clocking
++ */
++struct atmel_spi {
++ spinlock_t lock;
++
++ void __iomem *regs;
++ int irq;
++ struct clk *clk;
++ struct platform_device *pdev;
++ unsigned new_1:1;
++
++ u8 stopping;
++ struct list_head queue;
++ struct spi_transfer *current_transfer;
++ unsigned long remaining_bytes;
++
++ void *buffer;
++ dma_addr_t buffer_dma;
++};
++
++#define BUFFER_SIZE PAGE_SIZE
++#define INVALID_DMA_ADDRESS 0xffffffff
++
++/*
++ * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
++ * they assume that spi slave device state will not change on deselect, so
++ * that automagic deselection is OK. Not so! Workaround uses nCSx pins
++ * as GPIOs; or newer controllers have CSAAT and friends.
++ *
++ * Since the CSAAT functionality is a bit weird on newer controllers
++ * as well, we use GPIO to control nCSx pins on all controllers.
++ */
++
++static inline void cs_activate(struct spi_device *spi)
++{
++ unsigned gpio = (unsigned) spi->controller_data;
++
++ dev_dbg(&spi->dev, "activate %u\n", gpio);
++ gpio_set_value(gpio, 0);
++}
++
++static inline void cs_deactivate(struct spi_device *spi)
++{
++ unsigned gpio = (unsigned) spi->controller_data;
++
++ dev_dbg(&spi->dev, "DEactivate %u\n", gpio);
++ gpio_set_value(gpio, 1);
++}
++
++/*
++ * Submit next transfer for DMA.
++ * lock is held, spi irq is blocked
++ */
++static void atmel_spi_next_xfer(struct spi_master *master,
++ struct spi_message *msg)
++{
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_transfer *xfer;
++ u32 imr = 0;
++ u32 len;
++ dma_addr_t tx_dma, rx_dma;
++
++ xfer = as->current_transfer;
++ if (!xfer || as->remaining_bytes == 0) {
++ if (xfer)
++ xfer = list_entry(xfer->transfer_list.next,
++ struct spi_transfer, transfer_list);
++ else
++ xfer = list_entry(msg->transfers.next, struct spi_transfer,
++ transfer_list);
++ as->remaining_bytes = xfer->len;
++ as->current_transfer = xfer;
++ }
++
++ len = as->remaining_bytes;
++
++ tx_dma = xfer->tx_dma;
++ rx_dma = xfer->rx_dma;
++
++ if (rx_dma == INVALID_DMA_ADDRESS) {
++ rx_dma = as->buffer_dma;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++ }
++ if (tx_dma == INVALID_DMA_ADDRESS) {
++ if (xfer->tx_buf) {
++ tx_dma = as->buffer_dma;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++ memcpy(as->buffer, xfer->tx_buf, len);
++ dma_sync_single_for_device(&as->pdev->dev,
++ as->buffer_dma, len,
++ DMA_TO_DEVICE);
++ } else {
++ /* Send undefined data; rx_dma is handy */
++ tx_dma = rx_dma;
++ }
++ }
++
++ spi_writel(as, RPR, rx_dma);
++ spi_writel(as, TPR, tx_dma);
++
++ as->remaining_bytes -= len;
++ if (msg->spi->bits_per_word > 8)
++ len >>= 1;
++
++ /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
++ * mechanism might help avoid the IRQ latency between transfers
++ *
++ * We're also waiting for ENDRX before we start the next
++ * transfer because we need to handle some difficult timing
++ * issues otherwise. If we wait for ENDTX in one transfer and
++ * then starts waiting for ENDRX in the next, it's difficult
++ * to tell the difference between the ENDRX interrupt we're
++ * actually waiting for and the ENDRX interrupt of the
++ * previous transfer.
++ *
++ * It should be doable, though. Just not now...
++ */
++ spi_writel(as, TNCR, 0);
++ spi_writel(as, RNCR, 0);
++ imr = SPI_BIT(ENDRX);
++
++ dev_dbg(&msg->spi->dev,
++ "start xfer %p: len %u tx %p/%08x rx %p/%08x imr %08x\n",
++ xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
++ xfer->rx_buf, xfer->rx_dma, imr);
++
++ wmb();
++ spi_writel(as, TCR, len);
++ spi_writel(as, RCR, len);
++ spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
++ spi_writel(as, IER, imr);
++}
++
++static void atmel_spi_next_message(struct spi_master *master)
++{
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_message *msg;
++ u32 mr;
++
++ BUG_ON(as->current_transfer);
++
++ msg = list_entry(as->queue.next, struct spi_message, queue);
++
++ /* Select the chip */
++ mr = spi_readl(as, MR);
++ mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr);
++ spi_writel(as, MR, mr);
++ cs_activate(msg->spi);
++
++ atmel_spi_next_xfer(master, msg);
++}
++
++static void atmel_spi_dma_map_xfer(struct atmel_spi *as,
++ struct spi_transfer *xfer)
++{
++ xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
++ if (!(xfer->len & (L1_CACHE_BYTES - 1))) {
++ if (xfer->tx_buf
++ && !((unsigned long)xfer->tx_buf & (L1_CACHE_BYTES - 1)))
++ xfer->tx_dma = dma_map_single(&as->pdev->dev,
++ xfer->tx_buf,
++ xfer->len,
++ DMA_TO_DEVICE);
++ if (xfer->rx_buf
++ && !((unsigned long)xfer->rx_buf & (L1_CACHE_BYTES - 1)))
++ xfer->rx_dma = dma_map_single(&as->pdev->dev,
++ xfer->rx_buf,
++ xfer->len,
++ DMA_FROM_DEVICE);
++ }
++}
++
++static irqreturn_t
++atmel_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++ struct spi_master *master = dev_id;
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_message *msg;
++ struct spi_transfer *xfer;
++ u32 status, pending, imr;
++ int ret = IRQ_NONE;
++
++ imr = spi_readl(as, IMR);
++ status = spi_readl(as, SR);
++ pending = status & imr;
++pr_debug("spi irq: stat %05x imr %05x pend %05x\n", status, imr, pending);
++
++ if (pending & (SPI_BIT(ENDTX) | SPI_BIT(ENDRX))) {
++ ret = IRQ_HANDLED;
++
++ spi_writel(as, IDR, pending);
++ spin_lock(&as->lock);
++
++ xfer = as->current_transfer;
++ msg = list_entry(as->queue.next, struct spi_message, queue);
++
++ /*
++ * If the rx buffer wasn't aligned, we used a bounce
++ * buffer for the transfer. Copy the data back and
++ * make the bounce buffer ready for re-use.
++ */
++ if (xfer->rx_buf && xfer->rx_dma == INVALID_DMA_ADDRESS) {
++ unsigned int len = xfer->len;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++
++ dma_sync_single_for_cpu(&as->pdev->dev, as->buffer_dma,
++ len, DMA_FROM_DEVICE);
++ memcpy((xfer->rx_buf + xfer->len
++ - len - as->remaining_bytes),
++ as->buffer, len);
++ }
++
++
++ if (as->remaining_bytes == 0) {
++ msg->actual_length += xfer->len;
++
++ if (!msg->is_dma_mapped) {
++ if (xfer->tx_dma != INVALID_DMA_ADDRESS)
++ dma_unmap_single(master->cdev.dev,
++ xfer->tx_dma,
++ xfer->len,
++ DMA_TO_DEVICE);
++ if (xfer->rx_dma != INVALID_DMA_ADDRESS)
++ dma_unmap_single(master->cdev.dev,
++ xfer->rx_dma,
++ xfer->len,
++ DMA_FROM_DEVICE);
++ }
++
++ /* REVISIT: udelay in irq is unfriendly */
++ if (xfer->delay_usecs)
++ udelay(xfer->delay_usecs);
++
++ if (msg->transfers.prev == &xfer->transfer_list) {
++
++ /* report completed message */
++ cs_deactivate(msg->spi);
++ list_del(&msg->queue);
++ msg->status = 0;
++
++ dev_dbg(master->cdev.dev,
++ "xfer complete: %u bytes transferred\n",
++ msg->actual_length);
++
++ spin_unlock(&as->lock);
++ msg->complete(msg->context);
++ spin_lock(&as->lock);
++
++ as->current_transfer = NULL;
++
++ /* continue; complete() may have queued requests */
++ if (list_empty(&as->queue) || as->stopping)
++ spi_writel(as, PTCR, SPI_BIT(RXTDIS)
++ | SPI_BIT(TXTDIS));
++ else
++ atmel_spi_next_message(master);
++ } else {
++ if (xfer->cs_change) {
++ cs_deactivate(msg->spi);
++ udelay(1);
++ cs_activate(msg->spi);
++ }
++
++ /*
++ * Not done yet. Submit the next transfer.
++ *
++ * FIXME handle protocol options for xfer
++ */
++ atmel_spi_next_xfer(master, msg);
++ }
++ } else {
++ /*
++ * Keep going, we still have data to send in
++ * the current transfer.
++ */
++ atmel_spi_next_xfer(master, msg);
++ }
++ spin_unlock(&as->lock);
++ }
++
++ return ret;
++}
++
++static int atmel_spi_setup(struct spi_device *spi)
++{
++ struct atmel_spi *as;
++ u32 scbr, csr;
++ unsigned int bits = spi->bits_per_word;
++ unsigned long bus_hz, sck_hz;
++ unsigned int npcs_pin;
++ int ret;
++
++ as = spi_master_get_devdata(spi->master);
++
++ if (as->stopping)
++ return -ESHUTDOWN;
++
++ if (spi->chip_select > spi->master->num_chipselect) {
++ dev_dbg(&spi->dev,
++ "setup: invalid chipselect %u (%u defined)\n",
++ spi->chip_select, spi->master->num_chipselect);
++ return -EINVAL;
++ }
++
++ if (bits == 0)
++ bits = 8;
++ if (bits < 8 || bits > 16) {
++ dev_dbg(&spi->dev,
++ "setup: invalid bits_per_word %u (8 to 16)\n",
++ bits);
++ return -EINVAL;
++ }
++
++ if (spi->mode & (SPI_CS_HIGH | SPI_LSB_FIRST)) {
++ dev_dbg(&spi->dev, "setup: unsupported mode %u\n", spi->mode);
++ return -EINVAL;
++ }
++
++ /* speed zero convention is used by some upper layers */
++ bus_hz = clk_get_rate(as->clk);
++ if (spi->max_speed_hz) {
++ /* assume div32/fdiv/mbz == 0 */
++ if (!as->new_1)
++ bus_hz /= 2;
++ scbr = ((bus_hz + spi->max_speed_hz - 1)
++ / spi->max_speed_hz);
++ if (scbr >= (1 << SPI_SCBR_SIZE)) {
++ dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
++ spi->max_speed_hz, scbr);
++ return -EINVAL;
++ }
++ } else
++ scbr = 0xff;
++ sck_hz = bus_hz / scbr;
++
++ csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
++ if (spi->mode & SPI_CPOL)
++ csr |= SPI_BIT(CPOL);
++ if (!(spi->mode & SPI_CPHA))
++ csr |= SPI_BIT(NCPHA);
++
++ /* TODO: DLYBS and DLYBCT */
++ csr |= SPI_BF(DLYBS, 10);
++ csr |= SPI_BF(DLYBCT, 10);
++
++ npcs_pin = (unsigned int)spi->controller_data;
++ if (!spi->controller_state) {
++ ret = gpio_request(npcs_pin, "spi_npcs");
++ if (ret)
++ return ret;
++ spi->controller_state = (void *)npcs_pin;
++ }
++
++ gpio_set_value(npcs_pin, 1);
++
++ dev_dbg(&spi->dev,
++ "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
++ sck_hz, bits, spi->mode, spi->chip_select, csr);
++
++ spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
++
++ return 0;
++}
++
++static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
++{
++ struct atmel_spi *as;
++ struct spi_transfer *xfer;
++ unsigned long flags;
++ struct device *controller = spi->master->cdev.dev;
++
++ as = spi_master_get_devdata(spi->master);
++
++ dev_dbg(controller, "new message %p submitted for %s\n",
++ msg, spi->dev.bus_id);
++
++ if (unlikely(list_empty(&msg->transfers)
++ || !spi->max_speed_hz))
++ return -EINVAL;
++
++ if (as->stopping)
++ return -ESHUTDOWN;
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if (!(xfer->tx_buf || xfer->rx_buf)) {
++ dev_dbg(&spi->dev, "missing rx or tx buf\n");
++ return -EINVAL;
++ }
++
++ /* FIXME implement these protocol options!! */
++ if (xfer->bits_per_word || xfer->speed_hz) {
++ dev_dbg(&spi->dev, "no protocol options yet\n");
++ return -ENOPROTOOPT;
++ }
++ }
++
++ /* scrub dcache "early" */
++ if (!msg->is_dma_mapped) {
++ list_for_each_entry(xfer, &msg->transfers, transfer_list)
++ atmel_spi_dma_map_xfer(as, xfer);
++ }
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ dev_dbg(controller,
++ " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
++ xfer, xfer->len,
++ xfer->tx_buf, xfer->tx_dma,
++ xfer->rx_buf, xfer->rx_dma);
++ }
++
++ msg->status = -EINPROGRESS;
++ msg->actual_length = 0;
++
++ spin_lock_irqsave(&as->lock, flags);
++ list_add_tail(&msg->queue, &as->queue);
++ if (!as->current_transfer)
++ atmel_spi_next_message(spi->master);
++ spin_unlock_irqrestore(&as->lock, flags);
++
++ return 0;
++}
++
++static void atmel_spi_cleanup(const struct spi_device *spi)
++{
++ if (spi->controller_state)
++ gpio_free((unsigned int)spi->controller_data);
++}
++
++/*-------------------------------------------------------------------------*/
++
++static int __devinit atmel_spi_probe(struct platform_device *pdev)
++{
++ struct resource *regs;
++ int irq;
++ struct clk *clk;
++ int ret;
++ struct spi_master *master;
++ struct atmel_spi *as;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++
++ clk = clk_get(&pdev->dev, "pclk");
++ if (IS_ERR(clk))
++ return PTR_ERR(clk);
++
++ /* setup spi core then atmel-specific driver state */
++ ret = -ENOMEM;
++ master = spi_alloc_master(&pdev->dev, sizeof *as);
++ if (!master)
++ goto out_free;
++
++ master->bus_num = pdev->id;
++ master->num_chipselect = 4;
++ master->setup = atmel_spi_setup;
++ master->transfer = atmel_spi_transfer;
++ master->cleanup = atmel_spi_cleanup;
++ platform_set_drvdata(pdev, master);
++
++ as = spi_master_get_devdata(master);
++
++ as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
++ &as->buffer_dma, GFP_KERNEL);
++ if (!as->buffer)
++ goto out_free;
++
++ spin_lock_init(&as->lock);
++ INIT_LIST_HEAD(&as->queue);
++ as->pdev = pdev;
++ as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
++ if (!as->regs)
++ goto out_free_buffer;
++ as->irq = irq;
++ as->clk = clk;
++#if !defined(CONFIG_ARCH_AT91RM9200)
++ /* if (!cpu_is_at91rm9200()) */
++ as->new_1 = 1;
++#endif
++
++ ret = request_irq(irq, atmel_spi_interrupt, 0,
++ pdev->dev.bus_id, master);
++ if (ret)
++ goto out_unmap_regs;
++
++ /* Initialize the hardware */
++ clk_enable(clk);
++ spi_writel(as, CR, SPI_BIT(SWRST));
++ spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
++ spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
++ spi_writel(as, CR, SPI_BIT(SPIEN));
++
++ /* go! */
++ dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
++ (unsigned long)regs->start, irq);
++
++ ret = spi_register_master(master);
++ if (ret)
++ goto out_reset_hw;
++
++ return 0;
++
++out_reset_hw:
++ spi_writel(as, CR, SPI_BIT(SWRST));
++ clk_disable(clk);
++ free_irq(irq, master);
++out_unmap_regs:
++ iounmap(as->regs);
++out_free_buffer:
++ dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
++ as->buffer_dma);
++out_free:
++ clk_put(clk);
++ spi_master_put(master);
++ return ret;
++}
++
++static int __devexit atmel_spi_remove(struct platform_device *pdev)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_message *msg;
++
++ /* reset the hardware and block queue progress */
++ spin_lock_irq(&as->lock);
++ as->stopping = 1;
++ spi_writel(as, CR, SPI_BIT(SWRST));
++ spi_readl(as, SR);
++ spin_unlock_irq(&as->lock);
++
++ /* Terminate remaining queued transfers */
++ list_for_each_entry(msg, &as->queue, queue) {
++ /* REVISIT unmapping the dma is sort of a NOP on ARM,
++ * but we shouldn't depend on that...
++ */
++ msg->status = -ESHUTDOWN;
++ msg->complete(msg->context);
++ }
++
++ dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
++ as->buffer_dma);
++
++ clk_disable(as->clk);
++ clk_put(as->clk);
++ free_irq(as->irq, master);
++ iounmap(as->regs);
++
++ spi_unregister_master(master);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++
++static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct atmel_spi *as = spi_master_get_devdata(master);
++
++ clk_disable(as->clk);
++ return 0;
++}
++
++static int atmel_spi_resume(struct platform_device *pdev)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct atmel_spi *as = spi_master_get_devdata(master);
++
++ clk_enable(as->clk);
++ return 0;
++}
++
++#else
++#define atmel_spi_suspend NULL
++#define atmel_spi_resume NULL
++#endif
++
++
++static struct platform_driver atmel_spi_driver = {
++ .driver = {
++ .name = "atmel_spi",
++ .owner = THIS_MODULE,
++ },
++ .probe = atmel_spi_probe,
++ .suspend = atmel_spi_suspend,
++ .resume = atmel_spi_resume,
++ .remove = __devexit_p(atmel_spi_remove),
++};
++
++static int __init atmel_spi_init(void)
++{
++ return platform_driver_register(&atmel_spi_driver);
++}
++module_init(atmel_spi_init);
++
++static void __exit atmel_spi_exit(void)
++{
++ platform_driver_unregister(&atmel_spi_driver);
++}
++module_exit(atmel_spi_exit);
++
++MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.18-avr32/drivers/spi/atmel_spi.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.18-avr32/drivers/spi/atmel_spi.h 2006-11-29 16:55:59.000000000 +0100