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authorMarcin Juszkiewicz <marcin@juszkiewicz.com.pl>2009-09-30 15:06:17 +0200
committerMarcin Juszkiewicz <marcin@juszkiewicz.com.pl>2009-09-30 19:06:36 +0200
commita261b5ea923854b9a84f91cec0177ff57e905c98 (patch)
tree1d2563f24426102c3d6f83873349e79f288f0db3 /recipes/gcc/gcc-4.2.4.inc
parentfe2fa19a4a00b3c7778933c476d57ca46c303c61 (diff)
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gcc: update Maverick Crunch support to 20090908 version
From Martin W. Guy page http://martinwguy.co.uk/martin/crunch/ The 20090908 version * performs single and double precision floating point in the FPU (add, sub, mul, neg, abs, cmp and conversions from single and double precision floats to integral types). * by default, disables the floating point cfnegs and cfnegd instructions, which fail to convert 0 to -0 as they should. You can re-enable them with the -funsafe-math-optimizations flag, which is one of those enabled by -ffast-math (gcc-4.3 has an even more specific -fno-signed-zeros flag, which is one of those enabled by -funsafe-math-optimizations). * by default, does not respect denormalised values, so the smallest representable values are ±2-126 for floats and ±2-1022 for doubles instead of the usual ±2-149 and ±2-1074. * has a -mieee flag, which enables handling of denormalized values by disabling all the buggy instructions. With this, floating point addition, subtraction, negation, absolute value and conversion between floats and integer types are performed in software, leaving only floating point multiplication and comparison performed in hardware. * has no negative impact on regular ARM code generation. * always works round the hardware bugs in the FPU and no longer has the -mcirrus-fix-invalid-insns flag since chip development has stopped and all existing silicon has the same bugs except for the original revision D0 which is not supported. * passes GCC's IEEE testsuite except for the one specific test that checks for correct handling of denormalized values. With -mieee it passes all the math tests. * passes all other testsuites that I've tried (see below) including the stringent "paranoia" floating point IEEE conformance test. * produces the fastest Maverick code yet: 5.94 MFLOPS according to FFTW's tests/bench -opatient cf1024 benchmark and LAME takes 2m25 to encode that 30-second WAV file on a 200MHz EP9307 (compared to 5.4 and 2m30 for the futaris patches for 4.1.2 and 4.2.0). * does not use the FPU's buggy 64-bit integer instructions unless the new -mcirrus-di flag is given. Programs that do a lot of 64-bit integer operations (add, sub, mul, neg, abs, shifts) may be faster using this, but rigorous testing will be necessary to ensure that bad code is not being produced. OpenSSL's testsuite fails if this is enabled. There is more detail at the head of the arm-crunch-cirrus-di-flag.patch file. Known bugs * C: Values held in Maverick registers are not restored when performing a setjmp/longjmp pair. There is a fix to glibc for this in a message to the linux-cirrus mailing list. * C++: Similarly, exception unwinding (performing a throw back to a catch block in a different function) does not restore floating point and 64-bit values held in Maverick registers. * C++: Some C++ files will not compile, saying ".save {mv8}" Error: register expected although the same files will compile with optimization disabled. There is a patch to make binutils recognize these registers in the .save macro in a message to the linux-cirrus mailing list.
Diffstat (limited to 'recipes/gcc/gcc-4.2.4.inc')
-rw-r--r--recipes/gcc/gcc-4.2.4.inc45
1 files changed, 27 insertions, 18 deletions
diff --git a/recipes/gcc/gcc-4.2.4.inc b/recipes/gcc/gcc-4.2.4.inc
index 4638ddcdf1..3249c095b5 100644
--- a/recipes/gcc/gcc-4.2.4.inc
+++ b/recipes/gcc/gcc-4.2.4.inc
@@ -3,7 +3,7 @@ LICENSE = "GPLv3"
DEPENDS = "mpfr gmp"
-INC_PR = "r8"
+INC_PR = "r9"
SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
file://100-uclibc-conf.patch;patch=1 \
@@ -41,23 +41,32 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
"
SRC_URI_append_ep93xx = " \
- file://arm-crunch-saveregs.patch;patch=1 \
- file://arm-crunch-20000320.patch;patch=1 \
- file://arm-crunch-compare.patch;patch=1 \
- file://arm-crunch-compare-unordered.patch;patch=1 \
- file://arm-crunch-compare-geu.patch;patch=1 \
- file://arm-crunch-eabi-ieee754.patch;patch=1 \
- file://arm-crunch-eabi-ieee754-div.patch;patch=1 \
- file://arm-crunch-64bit-disable0.patch;patch=1 \
- file://arm-crunch-offset.patch;patch=1 \
- file://arm-crunch-fp_consts.patch;patch=1 \
- file://arm-crunch-neg2.patch;patch=1 \
- file://arm-crunch-predicates3.patch;patch=1 \
- file://arm-crunch-cfcvtds-disable.patch;patch=1 \
- file://arm-crunch-floatsi-disable.patch;patch=1 \
- file://arm-crunch-truncsi-disable.patch;patch=1 \
- file://arm-crunch-cfcvt64-disable.patch;patch=1 \
- file://arm-crunch-cirrus-bugfixes.patch;patch=1 \
+ file://ep93xx/arm-crunch-readme.patch;patch=1 \
+ file://ep93xx/arm-crunch-saveregs.patch;patch=1 \
+ file://ep93xx/arm-crunch-scratch.patch;patch=1 \
+ file://ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch;patch=1 \
+ file://ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch;patch=1 \
+ file://ep93xx/arm-crunch-20000320.patch;patch=1 \
+ file://ep93xx/arm-crunch-disable-cmpdi.patch;patch=1 \
+ file://ep93xx/arm-crunch-fix-64bit-const-offsets.patch;patch=1 \
+ file://ep93xx/arm-crunch-fp_consts.patch;patch=1 \
+ file://ep93xx/arm-crunch-neg-enable.patch;patch=1 \
+ file://ep93xx/arm-crunch-neg-protect.patch;patch=1 \
+ file://ep93xx/arm-crunch-repair-truncxfsi.patch;patch=1 \
+ file://ep93xx/arm-crunch-floatsi-no-scratch.patch;patch=1 \
+ file://ep93xx/arm-crunch-movsf-movdf-Uy.patch;patch=1 \
+ file://ep93xx/arm-crunch-drop-thumb2.patch;patch=1 \
+ file://ep93xx/arm-crunch-arm_dbx_register_number.patch;patch=1 \
+ file://ep93xx/arm-crunch-pipeline.patch;patch=1 \
+ file://ep93xx/arm-crunch-ccmav-mode.patch;patch=1 \
+ file://ep93xx/arm-crunch-cfcpy-with-cfsh64.patch;patch=1 \
+ file://ep93xx/arm-crunch-mieee.patch;patch=1 \
+ file://ep93xx/arm-size-bugfix.patch;patch=1 \
+ file://ep93xx/arm-prologue_use-length.patch;patch=1 \
+ file://ep93xx/arm-crunch-cftruncd32-attr.patch;patch=1 \
+ file://ep93xx/arm-crunch-fix-cirrus-reorg7.patch;patch=1 \
+ file://ep93xx/arm-crunch-cirrus-di-flag.patch;patch=1 \
+ file://ep93xx/arm-crunch-disable-floatsi.patch;patch=1 \
"
PACKAGE_ARCH_ep93xx = "${MACHINE_ARCH}"