gcc-4.5: Refresh the lately added patches with quilt

Signed-off-by: Khem Raj <raj.khem@gmail.com>

6 files changed, 113 insertions, 131 deletions

diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
index a55ec16952..64e928fba2 100644
--- a/recipes/gcc/gcc-4.5.inc
+++ b/recipes/gcc/gcc-4.5.inc
@@ -8,7 +8,7 @@ DEPENDS = "mpfr gmp libmpc libelf"
 NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
 
 
-INC_PR = "r21"
+INC_PR = "r22"
 
 SRCREV = "167449"
 PV = "4.5"
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch
index 3697bc95b0..72a221b1d2 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch
@@ -14,9 +14,11 @@
 	* gcc.dg/20101010-1.c: New testcase.
 
 === modified file 'gcc/ifcvt.c'
---- a/gcc/ifcvt.c	2010-10-04 00:50:43 +0000
-+++ b/gcc/ifcvt.c	2010-10-15 10:01:07 +0000
-@@ -88,6 +88,8 @@
+Index: gcc-4.5/gcc/ifcvt.c
+===================================================================
+--- gcc-4.5.orig/gcc/ifcvt.c
++++ gcc-4.5/gcc/ifcvt.c
+@@ -88,6 +88,8 @@ static int count_bb_insns (const_basic_b
  static bool cheap_bb_rtx_cost_p (const_basic_block, int);
  static rtx first_active_insn (basic_block);
  static rtx last_active_insn (basic_block, int);
@@ -25,7 +27,7 @@
  static basic_block block_fallthru (basic_block);
  static int cond_exec_process_insns (ce_if_block_t *, rtx, rtx, rtx, rtx, int);
  static rtx cond_exec_get_condition (rtx);
-@@ -230,6 +232,48 @@
+@@ -230,6 +232,48 @@ last_active_insn (basic_block bb, int sk
    return insn;
  }
  
@@ -74,7 +76,7 @@
  /* Return the basic block reached by falling though the basic block BB.  */
  
  static basic_block
-@@ -448,9 +492,9 @@
+@@ -448,9 +492,9 @@ cond_exec_process_if_block (ce_if_block_
        if (n_matching > 0)
  	{
  	  if (then_end)
@@ -86,7 +88,7 @@
  	  n_insns -= 2 * n_matching;
  	}
  
-@@ -488,9 +532,9 @@
+@@ -488,9 +532,9 @@ cond_exec_process_if_block (ce_if_block_
  	  if (n_matching > 0)
  	    {
  	      if (then_start)
@@ -98,7 +100,7 @@
  	      n_insns -= 2 * n_matching;
  	    }
  	}
-@@ -646,7 +690,7 @@
+@@ -646,7 +690,7 @@ cond_exec_process_if_block (ce_if_block_
      {
        rtx from = then_first_tail;
        if (!INSN_P (from))
@@ -107,10 +109,10 @@
        delete_insn_chain (from, BB_END (then_bb), false);
      }
    if (else_last_head)
-
-=== added file 'gcc/testsuite/gcc.dg/20101010-1.c'
---- a/gcc/testsuite/gcc.dg/20101010-1.c	1970-01-01 00:00:00 +0000
-+++ b/gcc/testsuite/gcc.dg/20101010-1.c	2010-10-15 10:01:07 +0000
+Index: gcc-4.5/gcc/testsuite/gcc.dg/20101010-1.c
+===================================================================
+--- /dev/null
++++ gcc-4.5/gcc/testsuite/gcc.dg/20101010-1.c
 @@ -0,0 +1,14 @@
 +/* { dg-do compile } */
 +/* { dg-options "-O2 -fno-crossjumping" } */
@@ -126,4 +128,3 @@
 +    }
 +  return -1;
 +}
-
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch
index 6df93a043a..2ad7e69681 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch
@@ -9,9 +9,11 @@
 	script when relocatable linking.
 
 === modified file 'gcc/testsuite/lib/lto.exp'
---- a/gcc/testsuite/lib/lto.exp	2010-06-29 15:35:54 +0000
-+++ b/gcc/testsuite/lib/lto.exp	2010-10-15 16:08:25 +0000
-@@ -156,6 +156,7 @@
+Index: gcc-4.5/gcc/testsuite/lib/lto.exp
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/lib/lto.exp
++++ gcc-4.5/gcc/testsuite/lib/lto.exp
+@@ -156,6 +156,7 @@ proc lto-link-and-maybe-run { testname o
      global testcase
      global tool
      global compile_type
@@ -19,7 +21,7 @@
  
      # Check that all of the objects were built successfully.
      foreach obj [split $objlist] {
-@@ -170,10 +171,29 @@
+@@ -170,10 +171,29 @@ proc lto-link-and-maybe-run { testname o
      set options ""
      lappend options "additional_flags=$optall $optfile"
  
@@ -49,4 +51,3 @@
      # Prune unimportant visibility warnings before checking output.
      set comp_output [lto_prune_warns $comp_output]
  
-
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch
index ebda1cd231..3ea7956f0f 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch
@@ -7,9 +7,11 @@
 	vector type exists.
 
 === modified file 'gcc/tree-vect-stmts.c'
---- a/gcc/tree-vect-stmts.c	2010-07-23 15:51:08 +0000
-+++ b/gcc/tree-vect-stmts.c	2010-10-20 16:52:04 +0000
-@@ -4650,6 +4650,11 @@
+Index: gcc-4.5/gcc/tree-vect-stmts.c
+===================================================================
+--- gcc-4.5.orig/gcc/tree-vect-stmts.c
++++ gcc-4.5/gcc/tree-vect-stmts.c
+@@ -4867,6 +4867,11 @@ supportable_widening_operation (enum tre
    tree wide_vectype = get_vectype_for_scalar_type (type);
    enum tree_code c1, c2;
  
@@ -21,4 +23,3 @@
    /* The result of a vectorized widening operation usually requires two vectors
       (because the widened results do not fit int one vector). The generated
       vector results would normally be expected to be generated in the same
-
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch
index f5267c743b..cb434082bf 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch
@@ -88,87 +88,66 @@
 	gcc/testsuite/
 	* gcc.target/arm/sync-1.c: New.
 
- 2010-10-20  Yao Qi  <yao@codesourcery.com>
- 
- 	Merge from Sourcery G++ to fix LP:660021
-@@ -110,22 +200,56 @@
  
  	Backport from FSF:
  
--	2010-08-07  Marcus Shawcroft  <marcus.shawcroft@arm.com>
--
--	gcc/
--	* config/arm/linux-atomic.c (SUBWORD_VAL_CAS): Instantiate with
--	'unsigned short' and 'unsigned char' instead of 'short' and
--	'char'. (SUBWORD_BOOL_CAS): Likewise.
--	(SUBWORD_SYNC_OP): Likewise.
--	(SUBWORD_TEST_AND_SET): Likewise.
--	(FETCH_AND_OP_WORD): Parenthesise INF_OP
--	(SUBWORD_SYNC_OP): Likewise.
--	(OP_AND_FETCH_WORD): Likewise.
--
--	gcc/testsuite/
--	* lib/target-supports.exp: (check_effective_target_sync_int_long):
--	Add arm*-*-linux-gnueabi.
--	(check_effective_target_sync_char_short): Likewise.
-+	gcc/
-+	2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+	* config/arm/arm-protos.h (arm_expand_sync): New.
-+	(arm_output_memory_barrier, arm_output_sync_insn): New.
-+	(arm_sync_loop_insns): New.
-+	* config/arm/arm.c (FL_ARCH7): New.
-+	(FL_FOR_ARCH7): Include FL_ARCH7.
-+	(arm_arch7): New.
-+	(arm_print_operand): Support %C markup.
-+	(arm_legitimize_sync_memory): New.
-+	(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
-+	(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
-+	(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
-+	(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
-+	(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
-+	(arm_process_output_sync_insn, arm_output_sync_insn): New.
-+	(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
-+	* config/arm/arm.h (struct arm_sync_generator): New.
-+	(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
-+	(TARGET_HAVE_MEMORY_BARRIER): New.
-+	(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
-+	* config/arm/arm.md: Include sync.md.
-+	(UNSPEC_MEMORY_BARRIER): New.
-+	(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
-+	(VUNSPEC_SYNC_OP):New.
-+	(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
-+	(sync_result, sync_memory, sync_required_value): New attributes.
-+	(sync_new_value, sync_t1, sync_t2): Likewise.
-+	(sync_release_barrier, sync_op): Likewise.
-+	(length): Add logic to length attribute defintion to call
-+	arm_sync_loop_insns when appropriate.
-+	* config/arm/sync.md: New file.
-+
-+	gcc/
-+	2010-09-02  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+	* config/arm/predicates.md (arm_sync_memory_operand): New.
-+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate
-+	to arm_sync_memory_operand and constraint to Q.
-+	(arm_sync_compare_and_swap<mode>): Likewise.
-+	(arm_sync_compare_and_swap<mode>): Likewise.
-+	(arm_sync_lock_test_and_setsi): Likewise.
-+	(arm_sync_lock_test_and_set<mode>): Likewise.
-+	(arm_sync_new_<sync_optab>si): Likewise.
-+	(arm_sync_new_nandsi): Likewise.
-+	(arm_sync_new_<sync_optab><mode>): Likewise.
-+	(arm_sync_new_nand<mode>): Likewise.
-+	(arm_sync_old_<sync_optab>si): Likewise.
-+	(arm_sync_old_nandsi): Likewise.
-+	(arm_sync_old_<sync_optab><mode>): Likewise.
-+	(arm_sync_old_nand<mode>): Likewise.
- 
- 2010-09-30  Jie Zhang  <jie@codesourcery.com>
- 
+	gcc/
+	2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	* config/arm/arm-protos.h (arm_expand_sync): New.
+	(arm_output_memory_barrier, arm_output_sync_insn): New.
+	(arm_sync_loop_insns): New.
+	* config/arm/arm.c (FL_ARCH7): New.
+	(FL_FOR_ARCH7): Include FL_ARCH7.
+	(arm_arch7): New.
+	(arm_print_operand): Support %C markup.
+	(arm_legitimize_sync_memory): New.
+	(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
+	(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
+	(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
+	(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
+	(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
+	(arm_process_output_sync_insn, arm_output_sync_insn): New.
+	(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
+	* config/arm/arm.h (struct arm_sync_generator): New.
+	(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
+	(TARGET_HAVE_MEMORY_BARRIER): New.
+	(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
+	* config/arm/arm.md: Include sync.md.
+	(UNSPEC_MEMORY_BARRIER): New.
+	(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
+	(VUNSPEC_SYNC_OP):New.
+	(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
+	(sync_result, sync_memory, sync_required_value): New attributes.
+	(sync_new_value, sync_t1, sync_t2): Likewise.
+	(sync_release_barrier, sync_op): Likewise.
+	(length): Add logic to length attribute defintion to call
+	arm_sync_loop_insns when appropriate.
+	* config/arm/sync.md: New file.
 
+	gcc/
+	2010-09-02  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	* config/arm/predicates.md (arm_sync_memory_operand): New.
+	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate
+	to arm_sync_memory_operand and constraint to Q.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_compare_and_swap<mode>): Likewise.
+	(arm_sync_lock_test_and_setsi): Likewise.
+	(arm_sync_lock_test_and_set<mode>): Likewise.
+	(arm_sync_new_<sync_optab>si): Likewise.
+	(arm_sync_new_nandsi): Likewise.
+	(arm_sync_new_<sync_optab><mode>): Likewise.
+	(arm_sync_new_nand<mode>): Likewise.
+	(arm_sync_old_<sync_optab>si): Likewise.
+	(arm_sync_old_nandsi): Likewise.
+	(arm_sync_old_<sync_optab><mode>): Likewise.
+	(arm_sync_old_nand<mode>): Likewise.
+ 
 === modified file 'gcc/config/arm/arm-protos.h'
---- a/gcc/config/arm/arm-protos.h	2010-10-14 11:33:26 +0000
-+++ b/gcc/config/arm/arm-protos.h	2010-11-04 10:45:05 +0000
-@@ -151,6 +151,11 @@
+Index: gcc-4.5/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm-protos.h
++++ gcc-4.5/gcc/config/arm/arm-protos.h
+@@ -151,6 +151,11 @@ extern const char *vfp_output_fstmd (rtx
  extern void arm_set_return_address (rtx, rtx);
  extern int arm_eliminable_register (rtx);
  extern const char *arm_output_shift(rtx *, int);
@@ -180,11 +159,11 @@
  
  extern bool arm_output_addr_const_extra (FILE *, rtx);
  
-
-=== modified file 'gcc/config/arm/arm.c'
---- a/gcc/config/arm/arm.c	2010-10-15 06:01:22 +0000
-+++ b/gcc/config/arm/arm.c	2010-11-04 10:45:05 +0000
-@@ -602,6 +602,7 @@
+Index: gcc-4.5/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.c
++++ gcc-4.5/gcc/config/arm/arm.c
+@@ -602,6 +602,7 @@ static int thumb_call_reg_needed;
  #define FL_NEON       (1 << 20)       /* Neon instructions.  */
  #define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
  					 architecture.  */
@@ -192,7 +171,7 @@
  
  #define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
  
-@@ -626,7 +627,7 @@
+@@ -626,7 +627,7 @@ static int thumb_call_reg_needed;
  #define FL_FOR_ARCH6ZK	FL_FOR_ARCH6K
  #define FL_FOR_ARCH6T2	(FL_FOR_ARCH6 | FL_THUMB2)
  #define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
@@ -201,7 +180,7 @@
  #define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
  #define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_DIV)
  #define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_DIV)
-@@ -664,6 +665,9 @@
+@@ -664,6 +665,9 @@ int arm_arch6 = 0;
  /* Nonzero if this chip supports the ARM 6K extensions.  */
  int arm_arch6k = 0;
  
@@ -211,7 +190,7 @@
  /* Nonzero if instructions not present in the 'M' profile can be used.  */
  int arm_arch_notm = 0;
  
-@@ -1602,6 +1606,7 @@
+@@ -1602,6 +1606,7 @@ arm_override_options (void)
    arm_arch6 = (insn_flags & FL_ARCH6) != 0;
    arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
    arm_arch_notm = (insn_flags & FL_NOTM) != 0;
@@ -219,7 +198,7 @@
    arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
    arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
    arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
-@@ -16562,6 +16567,17 @@
+@@ -16562,6 +16567,17 @@ arm_print_operand (FILE *stream, rtx x,
        }
        return;
  
@@ -237,7 +216,7 @@
      /* Translate an S register number into a D register number and element index.  */
      case 'y':
        {
-@@ -22793,4 +22809,372 @@
+@@ -22793,4 +22809,372 @@ arm_builtin_support_vector_misalignment
  						      is_packed);
  }
  
@@ -610,11 +589,11 @@
 +}
 +
  #include "gt-arm.h"
-
-=== modified file 'gcc/config/arm/arm.h'
---- a/gcc/config/arm/arm.h	2010-10-15 10:44:40 +0000
-+++ b/gcc/config/arm/arm.h	2010-11-04 10:45:05 +0000
-@@ -128,6 +128,24 @@
+Index: gcc-4.5/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.h
++++ gcc-4.5/gcc/config/arm/arm.h
+@@ -128,6 +128,24 @@ enum target_cpus
  /* The processor for which instructions should be scheduled.  */
  extern enum processor_type arm_tune;
  
@@ -639,7 +618,7 @@
  typedef enum arm_cond_code
  {
    ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
-@@ -272,6 +290,20 @@
+@@ -272,6 +290,20 @@ extern void (*arm_lang_output_object_att
     for Thumb-2.  */
  #define TARGET_UNIFIED_ASM TARGET_THUMB2
  
@@ -660,7 +639,7 @@
  
  /* True iff the full BPABI is being used.  If TARGET_BPABI is true,
     then TARGET_AAPCS_BASED must be true -- but the converse does not
-@@ -405,6 +437,12 @@
+@@ -405,6 +437,12 @@ extern int arm_arch5e;
  /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
  extern int arm_arch6;
  
@@ -673,10 +652,10 @@
  /* Nonzero if instructions not present in the 'M' profile can be used.  */
  extern int arm_arch_notm;
  
-
-=== modified file 'gcc/config/arm/arm.md'
---- a/gcc/config/arm/arm.md	2010-10-14 11:33:26 +0000
-+++ b/gcc/config/arm/arm.md	2010-11-04 10:45:05 +0000
+Index: gcc-4.5/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.md
++++ gcc-4.5/gcc/config/arm/arm.md
 @@ -103,6 +103,7 @@
     (UNSPEC_RBIT 26)       ; rbit operation.
     (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
@@ -727,10 +706,10 @@
 -
 +;; Synchronization Primitives
 +(include "sync.md")
-
-=== modified file 'gcc/config/arm/predicates.md'
---- a/gcc/config/arm/predicates.md	2010-10-14 11:33:26 +0000
-+++ b/gcc/config/arm/predicates.md	2010-11-04 10:45:05 +0000
+Index: gcc-4.5/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/predicates.md
++++ gcc-4.5/gcc/config/arm/predicates.md
 @@ -573,6 +573,11 @@
  		(and (match_test "TARGET_32BIT")
  		     (match_operand 0 "arm_di_operand"))))
@@ -743,14 +722,13 @@
  ;; Predicates for parallel expanders based on mode.
  (define_special_predicate "vect_par_constant_high" 
    (match_code "parallel")
-
-=== modified file 'gcc/testsuite/gcc.target/arm/synchronize.c'
---- a/gcc/testsuite/gcc.target/arm/synchronize.c	2009-08-12 14:55:19 +0000
-+++ b/gcc/testsuite/gcc.target/arm/synchronize.c	2010-11-04 10:45:05 +0000
+Index: gcc-4.5/gcc/testsuite/gcc.target/arm/synchronize.c
+===================================================================
+--- gcc-4.5.orig/gcc/testsuite/gcc.target/arm/synchronize.c
++++ gcc-4.5/gcc/testsuite/gcc.target/arm/synchronize.c
 @@ -1,4 +1,4 @@
 -/* { dg-final { scan-assembler "__sync_synchronize" { target arm*-*-linux-*eabi } } } */
 +/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi } } } */
  
  void *foo (void)
  {
-
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch
index a2edc4b793..4e63a81890 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch
@@ -11,8 +11,10 @@
 	instruction template.
 
 === modified file 'gcc/config/arm/neon.md'
---- a/gcc/config/arm/neon.md	2010-09-09 14:11:34 +0000
-+++ b/gcc/config/arm/neon.md	2010-11-04 11:47:50 +0000
+Index: gcc-4.5/gcc/config/arm/neon.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/neon.md
++++ gcc-4.5/gcc/config/arm/neon.md
 @@ -5682,9 +5682,9 @@
  ;; Vectorize for non-neon-quad case
  (define_insn "neon_unpack<US>_<mode>"
@@ -34,4 +36,3 @@
    [(set_attr "neon_type" "neon_shift_1")]
  )
  
-