aboutsummaryrefslogtreecommitdiffstats
path: root/recipes/gcc
diff options
context:
space:
mode:
authorKhem Raj <raj.khem@gmail.com>2011-02-15 14:53:41 -0800
committerKhem Raj <raj.khem@gmail.com>2011-02-15 14:53:41 -0800
commit638f45b3908a04be643e5414b9b9c0fe21ccc14c (patch)
treea8ff25eb7cdd06a17dd13e008c12f66762ec61bb /recipes/gcc
parent5a1546f015c1ee3365c8da1ec1067658c7a74250 (diff)
downloadopenembedded-638f45b3908a04be643e5414b9b9c0fe21ccc14c.tar.gz
Revert "gcc-4.5: Bring latest from linaro 4.5 and bump svn SRCREV for upstream"
This reverts commit f76026a6c1a00bd0b2f1ae2b045dee995293edc6. Pushed prematurely Signed-off-by: Khem Raj <raj.khem@gmail.com>
Diffstat (limited to 'recipes/gcc')
-rw-r--r--recipes/gcc/gcc-4.5.inc13
-rw-r--r--recipes/gcc/gcc-4.5/arm-bswapsi2.patch13
-rw-r--r--recipes/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch6
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99448.patch147
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch (renamed from recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch)1033
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch (renamed from recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch)811
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch157
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch94
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch38
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch811
-rw-r--r--recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch409
11 files changed, 1008 insertions, 2524 deletions
diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
index 1f089f6e75..b630528f2d 100644
--- a/recipes/gcc/gcc-4.5.inc
+++ b/recipes/gcc/gcc-4.5.inc
@@ -10,7 +10,7 @@ NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
INC_PR = "r31"
-SRCREV = "170123"
+SRCREV = "168622"
PV = "4.5"
# BINV should be incremented after updating to a revision
# after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made
@@ -29,6 +29,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
file://cache-amnesia.patch \
file://gcc-flags-for-build.patch \
file://libstdc++-emit-__cxa_end_cleanup-in-text.patch \
+ file://arm-bswapsi2.patch \
file://Makefile.in.patch \
file://gcc-armv4-pass-fix-v4bx-to-ld.patch \
file://sh4-multilib.patch \
@@ -153,6 +154,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
file://linaro/gcc-4.5-linaro-r99442.patch \
file://linaro/gcc-4.5-linaro-r99443.patch \
file://linaro/gcc-4.5-linaro-r99444.patch \
+ file://linaro/gcc-4.5-linaro-r99448.patch \
file://linaro/gcc-4.5-linaro-r99449.patch \
file://linaro/gcc-4.5-linaro-r99450.patch \
file://linaro/gcc-4.5-linaro-r99451.patch \
@@ -160,13 +162,8 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
file://linaro/gcc-4.5-linaro-r99453.patch \
file://linaro/gcc-4.5-linaro-r99454.patch \
file://linaro/gcc-4.5-linaro-r99455.patch \
- file://linaro/gcc-4.5-linaro-r99464.patch \
- file://linaro/gcc-4.5-linaro-r99465.patch \
- file://linaro/gcc-4.5-linaro-r99466.patch \
- file://linaro/gcc-4.5-linaro-r99468.patch \
- file://linaro/gcc-4.5-linaro-r99473.patch \
- file://linaro/gcc-4.5-linaro-r99474.patch \
- file://linaro/gcc-4.5-linaro-r99475.patch \
+# file://linaro/gcc-4.5-linaro-r99456.patch \
+# file://linaro/gcc-4.5-linaro-r99457.patch \
file://gcc-scalar-widening-pr45847.patch \
file://gcc-arm-volatile-bitfield-fix.patch \
"
diff --git a/recipes/gcc/gcc-4.5/arm-bswapsi2.patch b/recipes/gcc/gcc-4.5/arm-bswapsi2.patch
new file mode 100644
index 0000000000..7ac61a6d63
--- /dev/null
+++ b/recipes/gcc/gcc-4.5/arm-bswapsi2.patch
@@ -0,0 +1,13 @@
+Index: gcc-4.5/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/arm.md 2010-06-17 09:13:07.000000000 -0700
++++ gcc-4.5/gcc/config/arm/arm.md 2010-06-22 08:08:45.397212002 -0700
+@@ -11267,7 +11267,7 @@
+ (define_expand "bswapsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
+-"TARGET_EITHER"
++"TARGET_EITHER && (arm_arch6 && !optimize_size)"
+ "
+ if (!arm_arch6)
+ {
diff --git a/recipes/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch b/recipes/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch
index f833358172..d5a31d19d8 100644
--- a/recipes/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch
+++ b/recipes/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch
@@ -89,9 +89,9 @@ ChangeLog
Index: gcc-4_5-branch/gcc/expr.c
===================================================================
---- gcc-4_5-branch.orig/gcc/expr.c
-+++ gcc-4_5-branch/gcc/expr.c
-@@ -9033,7 +9033,8 @@ expand_expr_real_1 (tree exp, rtx target
+--- gcc-4_5-branch.orig/gcc/expr.c 2010-12-23 00:42:11.690101002 -0800
++++ gcc-4_5-branch/gcc/expr.c 2010-12-24 15:07:39.400101000 -0800
+@@ -9029,7 +9029,8 @@
&& modifier != EXPAND_INITIALIZER)
/* If the field is volatile, we always want an aligned
access. */
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99448.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99448.patch
new file mode 100644
index 0000000000..9f3d47f38b
--- /dev/null
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99448.patch
@@ -0,0 +1,147 @@
+2010-12-13 Chung-Lin Tang <cltang@codesourcery.com>
+
+ Backport from mainline:
+
+ 2010-12-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/46865
+
+ * rtl.c (rtx_equal_p_cb, rtx_equal_p): For last operand of
+ ASM_OPERANDS and ASM_INPUT if integers are different,
+ call locator_eq.
+ * jump.c (rtx_renumbered_equal_p): Likewise.
+
+ gcc/testsuite/
+ * gcc.target/i386/pr46865-1.c: New test.
+ * gcc.target/i386/pr46865-2.c: New test.
+
+=== modified file 'gcc/jump.c'
+--- old/gcc/jump.c 2009-11-25 10:55:54 +0000
++++ new/gcc/jump.c 2010-12-13 10:05:52 +0000
+@@ -1728,7 +1728,13 @@
+
+ case 'i':
+ if (XINT (x, i) != XINT (y, i))
+- return 0;
++ {
++ if (((code == ASM_OPERANDS && i == 6)
++ || (code == ASM_INPUT && i == 1))
++ && locator_eq (XINT (x, i), XINT (y, i)))
++ break;
++ return 0;
++ }
+ break;
+
+ case 't':
+
+=== modified file 'gcc/rtl.c'
+--- old/gcc/rtl.c 2009-11-25 10:55:54 +0000
++++ new/gcc/rtl.c 2010-12-13 10:05:52 +0000
+@@ -429,7 +429,15 @@
+ case 'n':
+ case 'i':
+ if (XINT (x, i) != XINT (y, i))
+- return 0;
++ {
++#ifndef GENERATOR_FILE
++ if (((code == ASM_OPERANDS && i == 6)
++ || (code == ASM_INPUT && i == 1))
++ && locator_eq (XINT (x, i), XINT (y, i)))
++ break;
++#endif
++ return 0;
++ }
+ break;
+
+ case 'V':
+@@ -549,7 +557,15 @@
+ case 'n':
+ case 'i':
+ if (XINT (x, i) != XINT (y, i))
+- return 0;
++ {
++#ifndef GENERATOR_FILE
++ if (((code == ASM_OPERANDS && i == 6)
++ || (code == ASM_INPUT && i == 1))
++ && locator_eq (XINT (x, i), XINT (y, i)))
++ break;
++#endif
++ return 0;
++ }
+ break;
+
+ case 'V':
+
+=== added file 'gcc/testsuite/gcc.target/i386/pr46865-1.c'
+--- old/gcc/testsuite/gcc.target/i386/pr46865-1.c 1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/i386/pr46865-1.c 2010-12-13 10:05:52 +0000
+@@ -0,0 +1,31 @@
++/* PR rtl-optimization/46865 */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++extern unsigned long f;
++
++#define m1(f) \
++ if (f & 1) \
++ asm volatile ("nop /* asmnop */\n"); \
++ else \
++ asm volatile ("nop /* asmnop */\n");
++
++#define m2(f) \
++ if (f & 1) \
++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \
++ else \
++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
++
++void
++foo (void)
++{
++ m1 (f);
++}
++
++void
++bar (void)
++{
++ m2 (f);
++}
++
++/* { dg-final { scan-assembler-times "asmnop" 2 } } */
+
+=== added file 'gcc/testsuite/gcc.target/i386/pr46865-2.c'
+--- old/gcc/testsuite/gcc.target/i386/pr46865-2.c 1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/i386/pr46865-2.c 2010-12-13 10:05:52 +0000
+@@ -0,0 +1,32 @@
++/* PR rtl-optimization/46865 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -save-temps" } */
++
++extern unsigned long f;
++
++#define m1(f) \
++ if (f & 1) \
++ asm volatile ("nop /* asmnop */\n"); \
++ else \
++ asm volatile ("nop /* asmnop */\n");
++
++#define m2(f) \
++ if (f & 1) \
++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \
++ else \
++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
++
++void
++foo (void)
++{
++ m1 (f);
++}
++
++void
++bar (void)
++{
++ m2 (f);
++}
++
++/* { dg-final { scan-assembler-times "asmnop" 2 } } */
++/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch
index 9b0fb0b488..35f98d24ab 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch
@@ -1,31 +1,3 @@
-2011-01-14 Bernd Schmidt <bernds@codesourcery.com>
-
- gcc/
- * function.c (thread_prologue_and_epilogue_insns): Avoid uninitialized
- variable.
-
-2011-01-12 Bernd Schmidt <bernds@codesourcery.com>
-
- gcc/
- * config/s390/s390.c (s390_emit_epilogue): Don't use gen_rtx_RETURN.
- * config/rx/rx.c (gen_rx_rtsd_vector): Likewise.
- * config/m68hc11/m68hc11.md (return): Likewise.
- * config/cris/cris.c (cris_expand_return): Likewise.
- * config/m68k/m68k.c (m68k_expand_epilogue): Likewise.
- * config/picochip/picochip.c (picochip_expand_epilogue): Likewise.
- * config/h8300/h8300.c (h8300_push_pop, h8300_expand_epilogue):
- Likewise.
- * config/v850/v850.c (expand_epilogue): Likewise.
- * config/bfin/bfin.c (bfin_expand_call): Likewise.
-
-2011-01-04 Catherine Moore <clm@codesourcery.com>
-
- gcc/
- * config/rs6000/rs6000.c (rs6000_make_savres_rtx): Change
- gen_rtx_RETURN to ret_rtx.
- (rs6000_emit_epilogue): Likewise.
- (rs6000_output_mi_thunk): Likewise.
-
2011-01-03 Bernd Schmidt <bernds@codesourcery.com>
gcc/
@@ -152,11 +124,9 @@
* basic-block.h (find_fallthru_edge): New inline function.
=== modified file 'gcc/basic-block.h'
-Index: gcc-4_5-branch/gcc/basic-block.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/basic-block.h
-+++ gcc-4_5-branch/gcc/basic-block.h
-@@ -884,6 +884,7 @@ extern void flow_edge_list_print (const
+--- old/gcc/basic-block.h 2010-09-01 13:29:58 +0000
++++ new/gcc/basic-block.h 2011-01-05 12:12:18 +0000
+@@ -884,6 +884,7 @@
/* In cfgrtl.c */
extern basic_block force_nonfallthru (edge);
@@ -164,7 +134,7 @@ Index: gcc-4_5-branch/gcc/basic-block.h
extern rtx block_label (basic_block);
extern bool purge_all_dead_edges (void);
extern bool purge_dead_edges (basic_block);
-@@ -1004,6 +1005,20 @@ bb_has_abnormal_pred (basic_block bb)
+@@ -1004,6 +1005,20 @@
return false;
}
@@ -185,11 +155,11 @@ Index: gcc-4_5-branch/gcc/basic-block.h
/* In cfgloopmanip.c. */
extern edge mfb_kj_edge;
extern bool mfb_keep_just (edge);
-Index: gcc-4_5-branch/gcc/cfganal.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/cfganal.c
-+++ gcc-4_5-branch/gcc/cfganal.c
-@@ -271,6 +271,37 @@ set_edge_can_fallthru_flag (void)
+
+=== modified file 'gcc/cfganal.c'
+--- old/gcc/cfganal.c 2009-11-25 10:55:54 +0000
++++ new/gcc/cfganal.c 2011-01-05 12:12:18 +0000
+@@ -271,6 +271,37 @@
EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU;
EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU;
}
@@ -227,11 +197,11 @@ Index: gcc-4_5-branch/gcc/cfganal.c
}
/* Find unreachable blocks. An unreachable block will have 0 in
-Index: gcc-4_5-branch/gcc/cfglayout.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/cfglayout.c
-+++ gcc-4_5-branch/gcc/cfglayout.c
-@@ -766,6 +766,7 @@ fixup_reorder_chain (void)
+
+=== modified file 'gcc/cfglayout.c'
+--- old/gcc/cfglayout.c 2010-05-17 16:30:54 +0000
++++ new/gcc/cfglayout.c 2011-01-05 12:12:18 +0000
+@@ -766,6 +766,7 @@
{
edge e_fall, e_taken, e;
rtx bb_end_insn;
@@ -239,7 +209,7 @@ Index: gcc-4_5-branch/gcc/cfglayout.c
basic_block nb;
edge_iterator ei;
-@@ -785,6 +786,7 @@ fixup_reorder_chain (void)
+@@ -785,6 +786,7 @@
bb_end_insn = BB_END (bb);
if (JUMP_P (bb_end_insn))
{
@@ -247,7 +217,7 @@ Index: gcc-4_5-branch/gcc/cfglayout.c
if (any_condjump_p (bb_end_insn))
{
/* This might happen if the conditional jump has side
-@@ -899,7 +901,7 @@ fixup_reorder_chain (void)
+@@ -899,7 +901,7 @@
}
/* We got here if we need to add a new jump insn. */
@@ -256,7 +226,7 @@ Index: gcc-4_5-branch/gcc/cfglayout.c
if (nb)
{
nb->il.rtl->visited = 1;
-@@ -1118,24 +1120,30 @@ extern bool cfg_layout_can_duplicate_bb_
+@@ -1118,24 +1120,30 @@
bool
cfg_layout_can_duplicate_bb_p (const_basic_block bb)
{
@@ -298,9 +268,9 @@ Index: gcc-4_5-branch/gcc/cfglayout.c
}
return true;
-@@ -1180,6 +1188,9 @@ duplicate_insn_chain (rtx from, rtx to)
- break;
- }
+@@ -1167,6 +1175,9 @@
+ || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
+ break;
copy = emit_copy_of_insn_after (insn, get_last_insn ());
+ if (JUMP_P (insn) && JUMP_LABEL (insn) != NULL_RTX
+ && ANY_RETURN_P (JUMP_LABEL (insn)))
@@ -308,11 +278,11 @@ Index: gcc-4_5-branch/gcc/cfglayout.c
maybe_copy_epilogue_insn (insn, copy);
break;
-Index: gcc-4_5-branch/gcc/cfgrtl.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/cfgrtl.c
-+++ gcc-4_5-branch/gcc/cfgrtl.c
-@@ -1107,10 +1107,13 @@ rtl_redirect_edge_and_branch (edge e, ba
+
+=== modified file 'gcc/cfgrtl.c'
+--- old/gcc/cfgrtl.c 2010-09-20 21:30:35 +0000
++++ new/gcc/cfgrtl.c 2011-01-05 12:12:18 +0000
+@@ -1107,10 +1107,13 @@
}
/* Like force_nonfallthru below, but additionally performs redirection
@@ -329,7 +299,7 @@ Index: gcc-4_5-branch/gcc/cfgrtl.c
{
basic_block jump_block, new_bb = NULL, src = e->src;
rtx note;
-@@ -1242,11 +1245,25 @@ force_nonfallthru_and_redirect (edge e,
+@@ -1242,11 +1245,25 @@
e->flags &= ~EDGE_FALLTHRU;
if (target == EXIT_BLOCK_PTR)
{
@@ -337,12 +307,14 @@ Index: gcc-4_5-branch/gcc/cfgrtl.c
+ {
#ifdef HAVE_return
- emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), loc);
+-#else
+- gcc_unreachable ();
+-#endif
+ emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block),
+ loc);
- #else
-- gcc_unreachable ();
++#else
+ gcc_unreachable ();
- #endif
++#endif
+ }
+ else
+ {
@@ -357,7 +329,7 @@ Index: gcc-4_5-branch/gcc/cfgrtl.c
}
else
{
-@@ -1273,7 +1290,7 @@ force_nonfallthru_and_redirect (edge e,
+@@ -1273,7 +1290,7 @@
basic_block
force_nonfallthru (edge e)
{
@@ -366,7 +338,7 @@ Index: gcc-4_5-branch/gcc/cfgrtl.c
}
/* Redirect edge even at the expense of creating new jump insn or
-@@ -1290,7 +1307,7 @@ rtl_redirect_edge_and_branch_force (edge
+@@ -1290,7 +1307,7 @@
/* In case the edge redirection failed, try to force it to be non-fallthru
and redirect newly created simplejump. */
df_set_bb_dirty (e->src);
@@ -375,11 +347,11 @@ Index: gcc-4_5-branch/gcc/cfgrtl.c
}
/* The given edge should potentially be a fallthru edge. If that is in
-Index: gcc-4_5-branch/gcc/common.opt
-===================================================================
---- gcc-4_5-branch.orig/gcc/common.opt
-+++ gcc-4_5-branch/gcc/common.opt
-@@ -1147,6 +1147,11 @@ fshow-column
+
+=== modified file 'gcc/common.opt'
+--- old/gcc/common.opt 2010-12-10 15:33:37 +0000
++++ new/gcc/common.opt 2011-01-05 12:12:18 +0000
+@@ -1147,6 +1147,11 @@
Common C ObjC C++ ObjC++ Report Var(flag_show_column) Init(1)
Show column numbers in diagnostics, when available. Default on
@@ -391,10 +363,10 @@ Index: gcc-4_5-branch/gcc/common.opt
fsignaling-nans
Common Report Var(flag_signaling_nans) Optimization
Disable optimizations observable by IEEE signaling NaNs
-Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h
-+++ gcc-4_5-branch/gcc/config/arm/arm-protos.h
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h 2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/arm-protos.h 2011-01-05 12:12:18 +0000
@@ -26,6 +26,7 @@
extern void arm_override_options (void);
extern void arm_optimization_options (int, int);
@@ -403,7 +375,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
extern enum reg_class arm_regno_class (int);
extern void arm_load_pic_register (unsigned long);
extern int arm_volatile_func (void);
-@@ -137,7 +138,7 @@ extern int arm_address_offset_is_imm (rt
+@@ -137,7 +138,7 @@
extern const char *output_add_immediate (rtx *);
extern const char *arithmetic_instr (rtx, int);
extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
@@ -412,11 +384,11 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
extern void arm_poke_function_name (FILE *, const char *);
extern void arm_print_operand (FILE *, rtx, int);
extern void arm_print_operand_address (FILE *, rtx);
-Index: gcc-4_5-branch/gcc/config/arm/arm.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.c
-+++ gcc-4_5-branch/gcc/config/arm/arm.c
-@@ -2163,6 +2163,18 @@ arm_trampoline_adjust_address (rtx addr)
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c 2011-01-05 11:32:50 +0000
++++ new/gcc/config/arm/arm.c 2011-01-05 12:12:18 +0000
+@@ -2163,6 +2163,18 @@
return addr;
}
@@ -435,7 +407,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* Return 1 if it is possible to return using a single instruction.
If SIBLING is non-null, this is a test for a return before a sibling
call. SIBLING is the call insn, so we can examine its register usage. */
-@@ -11284,6 +11296,7 @@ is_jump_table (rtx insn)
+@@ -11284,6 +11296,7 @@
if (GET_CODE (insn) == JUMP_INSN
&& JUMP_LABEL (insn) != NULL
@@ -443,7 +415,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
&& ((table = next_real_insn (JUMP_LABEL (insn)))
== next_real_insn (insn))
&& table != NULL
-@@ -14168,7 +14181,7 @@ arm_get_vfp_saved_size (void)
+@@ -14168,7 +14181,7 @@
/* Generate a function exit sequence. If REALLY_RETURN is false, then do
everything bar the final return instruction. */
const char *
@@ -452,7 +424,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
{
char conditional[10];
char instr[100];
-@@ -14206,10 +14219,15 @@ output_return_instruction (rtx operand,
+@@ -14206,10 +14219,15 @@
sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
@@ -471,7 +443,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
if (live_regs_mask)
{
-@@ -17108,6 +17126,7 @@ arm_final_prescan_insn (rtx insn)
+@@ -17108,6 +17126,7 @@
/* If we start with a return insn, we only succeed if we find another one. */
int seeking_return = 0;
@@ -479,7 +451,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* START_INSN will hold the insn from where we start looking. This is the
first insn after the following code_label if REVERSE is true. */
-@@ -17146,7 +17165,7 @@ arm_final_prescan_insn (rtx insn)
+@@ -17146,7 +17165,7 @@
else
return;
}
@@ -488,7 +460,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
{
start_insn = next_nonnote_insn (start_insn);
if (GET_CODE (start_insn) == BARRIER)
-@@ -17157,6 +17176,7 @@ arm_final_prescan_insn (rtx insn)
+@@ -17157,6 +17176,7 @@
{
reverse = TRUE;
seeking_return = 1;
@@ -496,7 +468,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
}
else
return;
-@@ -17197,11 +17217,15 @@ arm_final_prescan_insn (rtx insn)
+@@ -17197,11 +17217,15 @@
label = XEXP (XEXP (SET_SRC (body), 2), 0);
then_not_else = FALSE;
}
@@ -515,7 +487,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
then_not_else = FALSE;
}
else
-@@ -17302,8 +17326,7 @@ arm_final_prescan_insn (rtx insn)
+@@ -17302,8 +17326,7 @@
&& !use_return_insn (TRUE, NULL)
&& !optimize_size)
fail = TRUE;
@@ -525,11 +497,11 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
{
arm_ccfsm_state = 2;
succeed = TRUE;
-Index: gcc-4_5-branch/gcc/config/arm/arm.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.h
-+++ gcc-4_5-branch/gcc/config/arm/arm.h
-@@ -2622,6 +2622,8 @@ extern int making_const_table;
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h 2010-11-11 11:12:14 +0000
++++ new/gcc/config/arm/arm.h 2011-01-05 12:12:18 +0000
+@@ -2622,6 +2622,8 @@
#define RETURN_ADDR_RTX(COUNT, FRAME) \
arm_return_addr (COUNT, FRAME)
@@ -538,10 +510,10 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.h
/* Mask of the bits in the PC that contain the real return address
when running in 26-bit mode. */
#define RETURN_ADDR_MASK26 (0x03fffffc)
-Index: gcc-4_5-branch/gcc/config/arm/arm.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.md
-+++ gcc-4_5-branch/gcc/config/arm/arm.md
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md 2011-01-05 11:52:16 +0000
++++ new/gcc/config/arm/arm.md 2011-01-05 12:12:18 +0000
@@ -8882,66 +8882,72 @@
[(set_attr "type" "call")]
)
@@ -674,10 +646,10 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
return arm_output_epilogue (next_nonnote_insn (insn));
"
;; Length is absolute worst case
-Index: gcc-4_5-branch/gcc/config/arm/thumb2.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/thumb2.md
-+++ gcc-4_5-branch/gcc/config/arm/thumb2.md
+
+=== modified file 'gcc/config/arm/thumb2.md'
+--- old/gcc/config/arm/thumb2.md 2010-09-22 05:54:42 +0000
++++ new/gcc/config/arm/thumb2.md 2011-01-05 12:12:18 +0000
@@ -1020,16 +1020,15 @@
;; Note: this is not predicable, to avoid issues with linker-generated
@@ -703,59 +675,11 @@ Index: gcc-4_5-branch/gcc/config/arm/thumb2.md
(define_insn_and_split "thumb2_eh_return"
[(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
-Index: gcc-4_5-branch/gcc/config/bfin/bfin.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/bfin/bfin.c
-+++ gcc-4_5-branch/gcc/config/bfin/bfin.c
-@@ -2359,7 +2359,7 @@ bfin_expand_call (rtx retval, rtx fnaddr
- XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg);
- XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie);
- if (sibcall)
-- XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode);
-+ XVECEXP (pat, 0, n++) = ret_rtx;
- else
- XVECEXP (pat, 0, n++) = gen_rtx_CLOBBER (VOIDmode, retsreg);
- call = emit_call_insn (pat);
-Index: gcc-4_5-branch/gcc/config/cris/cris.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/cris/cris.c
-+++ gcc-4_5-branch/gcc/config/cris/cris.c
-@@ -1771,7 +1771,7 @@ cris_expand_return (bool on_stack)
- we do that until they're fixed. Currently, all return insns in a
- function must be the same (not really a limiting factor) so we need
- to check that it doesn't change half-way through. */
-- emit_jump_insn (gen_rtx_RETURN (VOIDmode));
-+ emit_jump_insn (ret_rtx);
-
- CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
- CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
-Index: gcc-4_5-branch/gcc/config/h8300/h8300.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/h8300/h8300.c
-+++ gcc-4_5-branch/gcc/config/h8300/h8300.c
-@@ -691,7 +691,7 @@ h8300_push_pop (int regno, int nregs, bo
- /* Add the return instruction. */
- if (return_p)
- {
-- RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
-+ RTVEC_ELT (vec, i) = ret_rtx;
- i++;
- }
-
-@@ -975,7 +975,7 @@ h8300_expand_epilogue (void)
- }
-
- if (!returned_p)
-- emit_jump_insn (gen_rtx_RETURN (VOIDmode));
-+ emit_jump_insn (ret_rtx);
- }
-
- /* Return nonzero if the current function is an interrupt
-Index: gcc-4_5-branch/gcc/config/i386/i386.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/i386/i386.c
-+++ gcc-4_5-branch/gcc/config/i386/i386.c
-@@ -9308,13 +9308,13 @@ ix86_expand_epilogue (int style)
+
+=== modified file 'gcc/config/i386/i386.c'
+--- old/gcc/config/i386/i386.c 2010-11-16 18:05:53 +0000
++++ new/gcc/config/i386/i386.c 2011-01-05 12:12:18 +0000
+@@ -9308,13 +9308,13 @@
pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
popc, -1, true);
@@ -772,7 +696,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.c
/* Restore the state back to the state from the prologue,
so that it's correct for the next epilogue. */
-@@ -26615,7 +26615,7 @@ ix86_pad_returns (void)
+@@ -26596,7 +26596,7 @@
rtx prev;
bool replace = false;
@@ -781,7 +705,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.c
|| optimize_bb_for_size_p (bb))
continue;
for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
-@@ -26645,7 +26645,10 @@ ix86_pad_returns (void)
+@@ -26626,7 +26626,10 @@
}
if (replace)
{
@@ -793,11 +717,11 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.c
delete_insn (ret);
}
}
-Index: gcc-4_5-branch/gcc/config/i386/i386.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/i386/i386.md
-+++ gcc-4_5-branch/gcc/config/i386/i386.md
-@@ -13798,24 +13798,29 @@
+
+=== modified file 'gcc/config/i386/i386.md'
+--- old/gcc/config/i386/i386.md 2010-11-27 15:24:12 +0000
++++ new/gcc/config/i386/i386.md 2011-01-05 12:12:18 +0000
+@@ -13797,24 +13797,29 @@
""
[(set_attr "length" "0")])
@@ -833,7 +757,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
"reload_completed"
"ret"
[(set_attr "length" "1")
-@@ -13826,8 +13831,8 @@
+@@ -13825,8 +13830,8 @@
;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
;; instruction Athlon and K8 have.
@@ -844,7 +768,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
(unspec [(const_int 0)] UNSPEC_REP)]
"reload_completed"
"rep\;ret"
-@@ -13837,8 +13842,8 @@
+@@ -13836,8 +13841,8 @@
(set_attr "prefix_rep" "1")
(set_attr "modrm" "0")])
@@ -855,7 +779,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
(use (match_operand:SI 0 "const_int_operand" ""))]
"reload_completed"
"ret\t%0"
-@@ -13847,8 +13852,8 @@
+@@ -13846,8 +13851,8 @@
(set_attr "length_immediate" "2")
(set_attr "modrm" "0")])
@@ -866,46 +790,11 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
(use (match_operand:SI 0 "register_operand" "r"))]
"reload_completed"
"jmp\t%A0"
-Index: gcc-4_5-branch/gcc/config/m68hc11/m68hc11.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/m68hc11/m68hc11.md
-+++ gcc-4_5-branch/gcc/config/m68hc11/m68hc11.md
-@@ -6576,7 +6576,7 @@
- if (ret_size && ret_size <= 2)
- {
- emit_jump_insn (gen_rtx_PARALLEL (VOIDmode,
-- gen_rtvec (2, gen_rtx_RETURN (VOIDmode),
-+ gen_rtvec (2, ret_rtx,
- gen_rtx_USE (VOIDmode,
- gen_rtx_REG (HImode, 1)))));
- DONE;
-@@ -6584,7 +6584,7 @@
- if (ret_size)
- {
- emit_jump_insn (gen_rtx_PARALLEL (VOIDmode,
-- gen_rtvec (2, gen_rtx_RETURN (VOIDmode),
-+ gen_rtvec (2, ret_rtx,
- gen_rtx_USE (VOIDmode,
- gen_rtx_REG (SImode, 0)))));
- DONE;
-Index: gcc-4_5-branch/gcc/config/m68k/m68k.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/m68k/m68k.c
-+++ gcc-4_5-branch/gcc/config/m68k/m68k.c
-@@ -1366,7 +1366,7 @@ m68k_expand_epilogue (bool sibcall_p)
- EH_RETURN_STACKADJ_RTX));
-
- if (!sibcall_p)
-- emit_jump_insn (gen_rtx_RETURN (VOIDmode));
-+ emit_jump_insn (ret_rtx);
- }
-
- /* Return true if X is a valid comparison operator for the dbcc
-Index: gcc-4_5-branch/gcc/config/mips/mips.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/mips/mips.c
-+++ gcc-4_5-branch/gcc/config/mips/mips.c
-@@ -10497,7 +10497,8 @@ mips_expand_epilogue (bool sibcall_p)
+
+=== modified file 'gcc/config/mips/mips.c'
+--- old/gcc/config/mips/mips.c 2010-11-21 10:38:43 +0000
++++ new/gcc/config/mips/mips.c 2011-01-05 12:12:18 +0000
+@@ -10497,7 +10497,8 @@
regno = GP_REG_FIRST + 7;
else
regno = RETURN_ADDR_REGNUM;
@@ -915,10 +804,10 @@ Index: gcc-4_5-branch/gcc/config/mips/mips.c
}
}
-Index: gcc-4_5-branch/gcc/config/mips/mips.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/mips/mips.md
-+++ gcc-4_5-branch/gcc/config/mips/mips.md
+
+=== modified file 'gcc/config/mips/mips.md'
+--- old/gcc/config/mips/mips.md 2010-04-02 18:54:46 +0000
++++ new/gcc/config/mips/mips.md 2011-01-05 12:12:18 +0000
@@ -5815,6 +5815,18 @@
[(set_attr "type" "jump")
(set_attr "mode" "none")])
@@ -953,90 +842,11 @@ Index: gcc-4_5-branch/gcc/config/mips/mips.md
;; Exception return.
(define_insn "mips_eret"
[(return)
-Index: gcc-4_5-branch/gcc/config/picochip/picochip.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/picochip/picochip.c
-+++ gcc-4_5-branch/gcc/config/picochip/picochip.c
-@@ -1996,7 +1996,7 @@ picochip_expand_epilogue (int is_sibling
- rtvec p;
- p = rtvec_alloc (2);
-
-- RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
-+ RTVEC_ELT (p, 0) = ret_rtx;
- RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
- gen_rtx_REG (Pmode, LINK_REGNUM));
- emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
-Index: gcc-4_5-branch/gcc/config/rs6000/rs6000.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/rs6000/rs6000.c
-+++ gcc-4_5-branch/gcc/config/rs6000/rs6000.c
-@@ -18563,7 +18563,7 @@ rs6000_make_savres_rtx (rs6000_stack_t *
- p = rtvec_alloc ((lr ? 4 : 3) + n_regs);
-
- if (!savep && lr)
-- RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode);
-+ RTVEC_ELT (p, offset++) = ret_rtx;
-
- RTVEC_ELT (p, offset++)
- = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65));
-@@ -19638,7 +19638,7 @@ rs6000_emit_epilogue (int sibcall)
- alloc_rname = ggc_strdup (rname);
-
- j = 0;
-- RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
-+ RTVEC_ELT (p, j++) = ret_rtx;
- RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
- gen_rtx_REG (Pmode,
- LR_REGNO));
-@@ -20254,7 +20254,7 @@ rs6000_emit_epilogue (int sibcall)
- else
- p = rtvec_alloc (2);
-
-- RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
-+ RTVEC_ELT (p, 0) = ret_rtx;
- RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
- ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
- : gen_rtx_CLOBBER (VOIDmode,
-@@ -20695,7 +20695,7 @@ rs6000_output_mi_thunk (FILE *file, tree
- gen_rtx_USE (VOIDmode,
- gen_rtx_REG (SImode,
- LR_REGNO)),
-- gen_rtx_RETURN (VOIDmode))));
-+ ret_rtx)));
- SIBLING_CALL_P (insn) = 1;
- emit_barrier ();
-
-Index: gcc-4_5-branch/gcc/config/rx/rx.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/rx/rx.c
-+++ gcc-4_5-branch/gcc/config/rx/rx.c
-@@ -1562,7 +1562,7 @@ gen_rx_rtsd_vector (unsigned int adjust,
- : plus_constant (stack_pointer_rtx,
- i * UNITS_PER_WORD)));
-
-- XVECEXP (vector, 0, count - 1) = gen_rtx_RETURN (VOIDmode);
-+ XVECEXP (vector, 0, count - 1) = ret_rtx;
-
- return vector;
- }
-Index: gcc-4_5-branch/gcc/config/s390/s390.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/s390/s390.c
-+++ gcc-4_5-branch/gcc/config/s390/s390.c
-@@ -8170,7 +8170,7 @@ s390_emit_epilogue (bool sibcall)
-
- p = rtvec_alloc (2);
-
-- RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
-+ RTVEC_ELT (p, 0) = ret_rtx;
- RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
- emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
- }
-Index: gcc-4_5-branch/gcc/config/sh/sh.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/sh/sh.c
-+++ gcc-4_5-branch/gcc/config/sh/sh.c
-@@ -5252,7 +5252,8 @@ barrier_align (rtx barrier_or_label)
+
+=== modified file 'gcc/config/sh/sh.c'
+--- old/gcc/config/sh/sh.c 2010-12-10 15:34:19 +0000
++++ new/gcc/config/sh/sh.c 2011-01-05 12:12:18 +0000
+@@ -5252,7 +5252,8 @@
}
if (prev
&& JUMP_P (prev)
@@ -1046,7 +856,7 @@ Index: gcc-4_5-branch/gcc/config/sh/sh.c
{
rtx x;
if (jump_to_next
-@@ -5951,7 +5952,7 @@ split_branches (rtx first)
+@@ -5951,7 +5952,7 @@
JUMP_LABEL (insn) = far_label;
LABEL_NUSES (far_label)++;
}
@@ -1055,24 +865,11 @@ Index: gcc-4_5-branch/gcc/config/sh/sh.c
far_label = 0;
}
}
-Index: gcc-4_5-branch/gcc/config/v850/v850.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/v850/v850.c
-+++ gcc-4_5-branch/gcc/config/v850/v850.c
-@@ -1832,7 +1832,7 @@ expand_epilogue (void)
- {
- restore_all = gen_rtx_PARALLEL (VOIDmode,
- rtvec_alloc (num_restore + 2));
-- XVECEXP (restore_all, 0, 0) = gen_rtx_RETURN (VOIDmode);
-+ XVECEXP (restore_all, 0, 0) = ret_rtx;
- XVECEXP (restore_all, 0, 1)
- = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
- gen_rtx_PLUS (Pmode,
-Index: gcc-4_5-branch/gcc/df-scan.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/df-scan.c
-+++ gcc-4_5-branch/gcc/df-scan.c
-@@ -3296,6 +3296,7 @@ df_uses_record (enum df_ref_class cl, st
+
+=== modified file 'gcc/df-scan.c'
+--- old/gcc/df-scan.c 2010-11-16 22:17:17 +0000
++++ new/gcc/df-scan.c 2011-01-05 12:12:18 +0000
+@@ -3296,6 +3296,7 @@
}
case RETURN:
@@ -1080,11 +877,11 @@ Index: gcc-4_5-branch/gcc/df-scan.c
break;
case ASM_OPERANDS:
-Index: gcc-4_5-branch/gcc/doc/invoke.texi
-===================================================================
---- gcc-4_5-branch.orig/gcc/doc/invoke.texi
-+++ gcc-4_5-branch/gcc/doc/invoke.texi
-@@ -5751,6 +5751,7 @@ compilation time.
+
+=== modified file 'gcc/doc/invoke.texi'
+--- old/gcc/doc/invoke.texi 2010-11-04 14:29:09 +0000
++++ new/gcc/doc/invoke.texi 2011-01-05 12:12:18 +0000
+@@ -5750,6 +5750,7 @@
-fipa-pure-const @gol
-fipa-reference @gol
-fmerge-constants
@@ -1092,7 +889,7 @@ Index: gcc-4_5-branch/gcc/doc/invoke.texi
-fsplit-wide-types @gol
-ftree-builtin-call-dce @gol
-ftree-ccp @gol
-@@ -6506,6 +6507,12 @@ This option has no effect until one of @
+@@ -6504,6 +6505,12 @@
When pipelining loops during selective scheduling, also pipeline outer loops.
This option has no effect until @option{-fsel-sched-pipelining} is turned on.
@@ -1105,11 +902,11 @@ Index: gcc-4_5-branch/gcc/doc/invoke.texi
@item -fcaller-saves
@opindex fcaller-saves
Enable values to be allocated in registers that will be clobbered by
-Index: gcc-4_5-branch/gcc/doc/md.texi
-===================================================================
---- gcc-4_5-branch.orig/gcc/doc/md.texi
-+++ gcc-4_5-branch/gcc/doc/md.texi
-@@ -4801,7 +4801,19 @@ RTL generation phase. In this case it i
+
+=== modified file 'gcc/doc/md.texi'
+--- old/gcc/doc/md.texi 2009-12-15 18:36:44 +0000
++++ new/gcc/doc/md.texi 2011-01-05 12:12:18 +0000
+@@ -4801,7 +4801,19 @@
multiple instructions are usually needed to return from a function, but
some class of functions only requires one instruction to implement a
return. Normally, the applicable functions are those which do not need
@@ -1130,11 +927,11 @@ Index: gcc-4_5-branch/gcc/doc/md.texi
@findex reload_completed
@findex leaf_function_p
-Index: gcc-4_5-branch/gcc/doc/rtl.texi
-===================================================================
---- gcc-4_5-branch.orig/gcc/doc/rtl.texi
-+++ gcc-4_5-branch/gcc/doc/rtl.texi
-@@ -2888,6 +2888,13 @@ placed in @code{pc} to return to the cal
+
+=== modified file 'gcc/doc/rtl.texi'
+--- old/gcc/doc/rtl.texi 2010-07-06 19:23:53 +0000
++++ new/gcc/doc/rtl.texi 2011-01-05 12:12:18 +0000
+@@ -2888,6 +2888,13 @@
Note that an insn pattern of @code{(return)} is logically equivalent to
@code{(set (pc) (return))}, but the latter form is never used.
@@ -1148,7 +945,7 @@ Index: gcc-4_5-branch/gcc/doc/rtl.texi
@findex call
@item (call @var{function} @var{nargs})
Represents a function call. @var{function} is a @code{mem} expression
-@@ -3017,7 +3024,7 @@ Represents several side effects performe
+@@ -3017,7 +3024,7 @@
brackets stand for a vector; the operand of @code{parallel} is a
vector of expressions. @var{x0}, @var{x1} and so on are individual
side effect expressions---expressions of code @code{set}, @code{call},
@@ -1157,7 +954,7 @@ Index: gcc-4_5-branch/gcc/doc/rtl.texi
``In parallel'' means that first all the values used in the individual
side-effects are computed, and second all the actual side-effects are
-@@ -3656,14 +3663,16 @@ and @code{call_insn} insns:
+@@ -3656,14 +3663,16 @@
@table @code
@findex PATTERN
@item PATTERN (@var{i})
@@ -1182,11 +979,11 @@ Index: gcc-4_5-branch/gcc/doc/rtl.texi
@findex INSN_CODE
@item INSN_CODE (@var{i})
-Index: gcc-4_5-branch/gcc/doc/tm.texi
-===================================================================
---- gcc-4_5-branch.orig/gcc/doc/tm.texi
-+++ gcc-4_5-branch/gcc/doc/tm.texi
-@@ -3287,6 +3287,12 @@ Define this if the return address of a p
+
+=== modified file 'gcc/doc/tm.texi'
+--- old/gcc/doc/tm.texi 2010-09-01 13:29:58 +0000
++++ new/gcc/doc/tm.texi 2011-01-05 12:12:18 +0000
+@@ -3287,6 +3287,12 @@
from the frame pointer of the previous stack frame.
@end defmac
@@ -1199,11 +996,11 @@ Index: gcc-4_5-branch/gcc/doc/tm.texi
@defmac INCOMING_RETURN_ADDR_RTX
A C expression whose value is RTL representing the location of the
incoming return address at the beginning of any function, before the
-Index: gcc-4_5-branch/gcc/dwarf2out.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/dwarf2out.c
-+++ gcc-4_5-branch/gcc/dwarf2out.c
-@@ -1396,7 +1396,7 @@ compute_barrier_args_size_1 (rtx insn, H
+
+=== modified file 'gcc/dwarf2out.c'
+--- old/gcc/dwarf2out.c 2010-12-21 18:46:10 +0000
++++ new/gcc/dwarf2out.c 2011-01-05 12:12:18 +0000
+@@ -1396,7 +1396,7 @@
{
rtx dest = JUMP_LABEL (insn);
@@ -1212,11 +1009,11 @@ Index: gcc-4_5-branch/gcc/dwarf2out.c
{
if (barrier_args_size [INSN_UID (dest)] < 0)
{
-Index: gcc-4_5-branch/gcc/emit-rtl.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/emit-rtl.c
-+++ gcc-4_5-branch/gcc/emit-rtl.c
-@@ -2432,6 +2432,8 @@ verify_rtx_sharing (rtx orig, rtx insn)
+
+=== modified file 'gcc/emit-rtl.c'
+--- old/gcc/emit-rtl.c 2010-10-04 00:50:43 +0000
++++ new/gcc/emit-rtl.c 2011-01-05 12:12:18 +0000
+@@ -2432,6 +2432,8 @@
case CODE_LABEL:
case PC:
case CC0:
@@ -1225,7 +1022,7 @@ Index: gcc-4_5-branch/gcc/emit-rtl.c
case SCRATCH:
return;
/* SCRATCH must be shared because they represent distinct values. */
-@@ -3323,14 +3325,17 @@ prev_label (rtx insn)
+@@ -3323,14 +3325,17 @@
return insn;
}
@@ -1245,7 +1042,7 @@ Index: gcc-4_5-branch/gcc/emit-rtl.c
for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn))
if (LABEL_P (insn))
label = insn;
-@@ -5209,7 +5214,7 @@ classify_insn (rtx x)
+@@ -5209,7 +5214,7 @@
return CODE_LABEL;
if (GET_CODE (x) == CALL)
return CALL_INSN;
@@ -1254,7 +1051,7 @@ Index: gcc-4_5-branch/gcc/emit-rtl.c
return JUMP_INSN;
if (GET_CODE (x) == SET)
{
-@@ -5715,8 +5720,10 @@ init_emit_regs (void)
+@@ -5715,8 +5720,10 @@
init_reg_modes_target ();
/* Assign register numbers to the globally defined register rtx. */
@@ -1267,11 +1064,11 @@ Index: gcc-4_5-branch/gcc/emit-rtl.c
stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
-Index: gcc-4_5-branch/gcc/final.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/final.c
-+++ gcc-4_5-branch/gcc/final.c
-@@ -2428,7 +2428,7 @@ final_scan_insn (rtx insn, FILE *file, i
+
+=== modified file 'gcc/final.c'
+--- old/gcc/final.c 2010-03-26 16:18:51 +0000
++++ new/gcc/final.c 2011-01-05 12:12:18 +0000
+@@ -2428,7 +2428,7 @@
delete_insn (insn);
break;
}
@@ -1280,11 +1077,11 @@ Index: gcc-4_5-branch/gcc/final.c
/* Replace (set (pc) (return)) with (return). */
PATTERN (insn) = body = SET_SRC (body);
-Index: gcc-4_5-branch/gcc/function.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/function.c
-+++ gcc-4_5-branch/gcc/function.c
-@@ -147,9 +147,6 @@ extern tree debug_find_var_in_block_tree
+
+=== modified file 'gcc/function.c'
+--- old/gcc/function.c 2010-08-16 19:18:08 +0000
++++ new/gcc/function.c 2011-01-05 12:12:18 +0000
+@@ -147,9 +147,6 @@
can always export `prologue_epilogue_contains'. */
static void record_insns (rtx, rtx, htab_t *) ATTRIBUTE_UNUSED;
static bool contains (const_rtx, htab_t);
@@ -1294,7 +1091,7 @@ Index: gcc-4_5-branch/gcc/function.c
static void prepare_function_start (void);
static void do_clobber_return_reg (rtx, void *);
static void do_use_return_reg (rtx, void *);
-@@ -4987,35 +4984,190 @@ prologue_epilogue_contains (const_rtx in
+@@ -4987,35 +4984,189 @@
return 0;
}
@@ -1462,7 +1259,6 @@ Index: gcc-4_5-branch/gcc/function.c
rtl_profile_for_bb (ENTRY_BLOCK_PTR);
+
+ epilogue_end = NULL_RTX;
-+ returnjump = NULL_RTX;
+
+ /* Can't deal with multiple successors of the entry block at the
+ moment. Function should always have at least one entry
@@ -1497,7 +1293,7 @@ Index: gcc-4_5-branch/gcc/function.c
#ifdef HAVE_prologue
if (HAVE_prologue)
{
-@@ -5040,20 +5192,169 @@ thread_prologue_and_epilogue_insns (void
+@@ -5040,19 +5191,168 @@
emit_insn (gen_blockage ());
#endif
@@ -1505,17 +1301,21 @@ Index: gcc-4_5-branch/gcc/function.c
+ prologue_seq = get_insns ();
end_sequence ();
set_insn_locators (seq, prologue_locator);
-+ }
-+#endif
-
+-
- /* Can't deal with multiple successors of the entry block
- at the moment. Function should always have at least one
- entry point. */
- gcc_assert (single_succ_p (ENTRY_BLOCK_PTR));
-+ bitmap_initialize (&bb_flags, &bitmap_default_obstack);
-
+-
- insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
- inserted = 1;
+- }
+-#endif
++ }
++#endif
++
++ bitmap_initialize (&bb_flags, &bitmap_default_obstack);
++
+#ifdef HAVE_simple_return
+ /* Try to perform a kind of shrink-wrapping, making sure the
+ prologue/epilogue is emitted only around those parts of the
@@ -1662,19 +1462,18 @@ Index: gcc-4_5-branch/gcc/function.c
+ bitmap_clear (&bb_antic_flags);
+ bitmap_clear (&bb_on_list);
+ VEC_free (basic_block, heap, vec);
- }
- #endif
-
++ }
++#endif
++
+ if (prologue_seq != NULL_RTX)
+ {
+ insert_insn_on_edge (prologue_seq, entry_edge);
+ inserted = true;
+ }
-+
+
/* If the exit block has no non-fake predecessors, we don't need
an epilogue. */
- FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
-@@ -5063,100 +5364,130 @@ thread_prologue_and_epilogue_insns (void
+@@ -5063,100 +5363,130 @@
goto epilogue_done;
rtl_profile_for_bb (EXIT_BLOCK_PTR);
@@ -1709,65 +1508,40 @@ Index: gcc-4_5-branch/gcc/function.c
+ if (exit_fallthru_edge == NULL)
goto epilogue_done;
- last = e->src;
-+ label = BB_HEAD (last_bb);
-
+-
- /* Verify that there are no active instructions in the last block. */
- label = BB_END (last);
- while (label && !LABEL_P (label))
-- {
-- if (active_insn_p (label))
-- break;
-- label = PREV_INSN (label);
-- }
++ label = BB_HEAD (last_bb);
++
+ src_bbs = VEC_alloc (basic_block, heap, EDGE_COUNT (last_bb->preds));
+ FOR_EACH_EDGE (e, ei2, last_bb->preds)
+ if (e->src != ENTRY_BLOCK_PTR)
+ VEC_quick_push (basic_block, src_bbs, e->src);
-
-- if (BB_HEAD (last) == label && LABEL_P (label))
++
+ FOR_EACH_VEC_ELT (basic_block, src_bbs, i, bb)
{
-- edge_iterator ei2;
+- if (active_insn_p (label))
+- break;
+- label = PREV_INSN (label);
+ bool simple_p;
+ rtx jump;
+ e = find_edge (bb, last_bb);
-
-- for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); )
-- {
-- basic_block bb = e->src;
-- rtx jump;
++
+ jump = BB_END (bb);
-
-- if (bb == ENTRY_BLOCK_PTR)
-- {
-- ei_next (&ei2);
-- continue;
-- }
++
+#ifdef HAVE_simple_return
+ simple_p = (entry_edge != orig_entry_edge
+ ? !bitmap_bit_p (&bb_flags, bb->index) : false);
+#else
+ simple_p = false;
+#endif
-
-- jump = BB_END (bb);
-- if (!JUMP_P (jump) || JUMP_LABEL (jump) != label)
-- {
-- ei_next (&ei2);
-- continue;
-- }
++
+ if (!simple_p
+ && (!HAVE_return || !JUMP_P (jump)
+ || JUMP_LABEL (jump) != label))
+ continue;
-
-- /* If we have an unconditional jump, we can replace that
-- with a simple return instruction. */
-- if (simplejump_p (jump))
-- {
-- emit_return_into_block (bb);
-- delete_insn (jump);
-- }
++
+ /* If we have an unconditional jump, we can replace that
+ with a simple return instruction. */
+ if (!JUMP_P (jump))
@@ -1784,16 +1558,7 @@ Index: gcc-4_5-branch/gcc/function.c
+ {
+ basic_block new_bb;
+ edge new_e;
-
-- /* If we have a conditional jump, we can try to replace
-- that with a conditional return instruction. */
-- else if (condjump_p (jump))
-- {
-- if (! redirect_jump (jump, 0, 0))
-- {
-- ei_next (&ei2);
-- continue;
-- }
++
+ gcc_assert (simple_p);
+ new_bb = split_edge (e);
+ emit_barrier_after (BB_END (new_bb));
@@ -1803,16 +1568,7 @@ Index: gcc-4_5-branch/gcc/function.c
+#endif
+ new_e = single_succ_edge (new_bb);
+ redirect_edge_succ (new_e, EXIT_BLOCK_PTR);
-
-- /* If this block has only one successor, it both jumps
-- and falls through to the fallthru block, so we can't
-- delete the edge. */
-- if (single_succ_p (bb))
-- {
-- ei_next (&ei2);
-- continue;
-- }
-- }
++
+ continue;
+ }
+ /* If we have a conditional jump branching to the last
@@ -1823,20 +1579,17 @@ Index: gcc-4_5-branch/gcc/function.c
+ rtx dest;
+ if (simple_p)
+ dest = simple_return_rtx;
- else
++ else
+ dest = ret_rtx;
+ if (! redirect_jump (jump, dest, 0))
- {
-- ei_next (&ei2);
++ {
+#ifdef HAVE_simple_return
+ if (simple_p)
+ unconverted_simple_returns = true;
+#endif
- continue;
- }
-
-- /* Fix up the CFG for the successful change we just made. */
-- redirect_edge_succ (e, EXIT_BLOCK_PTR);
++ continue;
++ }
++
+ /* If this block has only one successor, it both jumps
+ and falls through to the fallthru block, so we can't
+ delete the edge. */
@@ -1850,15 +1603,73 @@ Index: gcc-4_5-branch/gcc/function.c
+ unconverted_simple_returns = true;
+#endif
+ continue;
- }
-
++ }
++
+ /* Fix up the CFG for the successful change we just made. */
+ redirect_edge_succ (e, EXIT_BLOCK_PTR);
-+ }
+ }
+ VEC_free (basic_block, heap, src_bbs);
-+
+
+- if (BB_HEAD (last) == label && LABEL_P (label))
+ if (HAVE_return)
-+ {
+ {
+- edge_iterator ei2;
+-
+- for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); )
+- {
+- basic_block bb = e->src;
+- rtx jump;
+-
+- if (bb == ENTRY_BLOCK_PTR)
+- {
+- ei_next (&ei2);
+- continue;
+- }
+-
+- jump = BB_END (bb);
+- if (!JUMP_P (jump) || JUMP_LABEL (jump) != label)
+- {
+- ei_next (&ei2);
+- continue;
+- }
+-
+- /* If we have an unconditional jump, we can replace that
+- with a simple return instruction. */
+- if (simplejump_p (jump))
+- {
+- emit_return_into_block (bb);
+- delete_insn (jump);
+- }
+-
+- /* If we have a conditional jump, we can try to replace
+- that with a conditional return instruction. */
+- else if (condjump_p (jump))
+- {
+- if (! redirect_jump (jump, 0, 0))
+- {
+- ei_next (&ei2);
+- continue;
+- }
+-
+- /* If this block has only one successor, it both jumps
+- and falls through to the fallthru block, so we can't
+- delete the edge. */
+- if (single_succ_p (bb))
+- {
+- ei_next (&ei2);
+- continue;
+- }
+- }
+- else
+- {
+- ei_next (&ei2);
+- continue;
+- }
+-
+- /* Fix up the CFG for the successful change we just made. */
+- redirect_edge_succ (e, EXIT_BLOCK_PTR);
+- }
+-
/* Emit a return insn for the exit fallthru block. Whether
this is still reachable will be determined later. */
@@ -1875,7 +1686,7 @@ Index: gcc-4_5-branch/gcc/function.c
goto epilogue_done;
}
}
-@@ -5193,15 +5524,10 @@ thread_prologue_and_epilogue_insns (void
+@@ -5193,15 +5523,10 @@
}
#endif
@@ -1894,7 +1705,7 @@ Index: gcc-4_5-branch/gcc/function.c
goto epilogue_done;
#ifdef HAVE_epilogue
-@@ -5217,25 +5543,36 @@ thread_prologue_and_epilogue_insns (void
+@@ -5217,25 +5542,38 @@
set_insn_locators (seq, epilogue_locator);
seq = get_insns ();
@@ -1914,6 +1725,8 @@ Index: gcc-4_5-branch/gcc/function.c
+ else
+ JUMP_LABEL (returnjump) = ret_rtx;
+ }
++ else
++ returnjump = NULL_RTX;
}
else
#endif
@@ -1938,7 +1751,7 @@ Index: gcc-4_5-branch/gcc/function.c
cfg_layout_initialize (0);
FOR_EACH_BB (cur_bb)
if (cur_bb->index >= NUM_FIXED_BLOCKS
-@@ -5244,6 +5581,7 @@ thread_prologue_and_epilogue_insns (void
+@@ -5244,6 +5582,7 @@
cfg_layout_finalize ();
}
epilogue_done:
@@ -1946,7 +1759,7 @@ Index: gcc-4_5-branch/gcc/function.c
default_rtl_profile ();
if (inserted)
-@@ -5260,33 +5598,93 @@ epilogue_done:
+@@ -5260,33 +5599,93 @@
}
}
@@ -2026,6 +1839,14 @@ Index: gcc-4_5-branch/gcc/function.c
- emit_insn (gen_sibcall_epilogue ());
- seq = get_insns ();
- end_sequence ();
+-
+- /* Retain a map of the epilogue insns. Used in life analysis to
+- avoid getting rid of sibcall epilogue insns. Do this before we
+- actually emit the sequence. */
+- record_insns (seq, NULL, &epilogue_insn_hash);
+- set_insn_locators (seq, epilogue_locator);
+-
+- emit_insn_before (seq, insn);
+ ep_seq = gen_sibcall_epilogue ();
+ if (ep_seq)
+ {
@@ -2034,25 +1855,19 @@ Index: gcc-4_5-branch/gcc/function.c
+ emit_insn (ep_seq);
+ seq = get_insns ();
+ end_sequence ();
-
-- /* Retain a map of the epilogue insns. Used in life analysis to
-- avoid getting rid of sibcall epilogue insns. Do this before we
-- actually emit the sequence. */
-- record_insns (seq, NULL, &epilogue_insn_hash);
-- set_insn_locators (seq, epilogue_locator);
++
+ /* Retain a map of the epilogue insns. Used in life analysis to
+ avoid getting rid of sibcall epilogue insns. Do this before we
+ actually emit the sequence. */
+ record_insns (seq, NULL, &epilogue_insn_hash);
+ set_insn_locators (seq, epilogue_locator);
-
-- emit_insn_before (seq, insn);
++
+ emit_insn_before (seq, insn);
+ }
ei_next (&ei);
}
#endif
-@@ -5311,6 +5709,8 @@ epilogue_done:
+@@ -5311,6 +5710,8 @@
}
#endif
@@ -2061,11 +1876,11 @@ Index: gcc-4_5-branch/gcc/function.c
/* Threading the prologue and epilogue changes the artificial refs
in the entry and exit blocks. */
epilogue_completed = 1;
-Index: gcc-4_5-branch/gcc/genemit.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/genemit.c
-+++ gcc-4_5-branch/gcc/genemit.c
-@@ -222,6 +222,12 @@ gen_exp (rtx x, enum rtx_code subroutine
+
+=== modified file 'gcc/genemit.c'
+--- old/gcc/genemit.c 2009-11-27 11:37:06 +0000
++++ new/gcc/genemit.c 2011-01-05 12:12:18 +0000
+@@ -222,6 +222,12 @@
case PC:
printf ("pc_rtx");
return;
@@ -2078,7 +1893,7 @@ Index: gcc-4_5-branch/gcc/genemit.c
case CLOBBER:
if (REG_P (XEXP (x, 0)))
{
-@@ -544,8 +550,8 @@ gen_expand (rtx expand)
+@@ -544,8 +550,8 @@
|| (GET_CODE (next) == PARALLEL
&& ((GET_CODE (XVECEXP (next, 0, 0)) == SET
&& GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC)
@@ -2089,7 +1904,7 @@ Index: gcc-4_5-branch/gcc/genemit.c
printf (" emit_jump_insn (");
else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL)
|| GET_CODE (next) == CALL
-@@ -660,7 +666,7 @@ gen_split (rtx split)
+@@ -660,7 +666,7 @@
|| (GET_CODE (next) == PARALLEL
&& GET_CODE (XVECEXP (next, 0, 0)) == SET
&& GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC)
@@ -2098,11 +1913,11 @@ Index: gcc-4_5-branch/gcc/genemit.c
printf (" emit_jump_insn (");
else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL)
|| GET_CODE (next) == CALL
-Index: gcc-4_5-branch/gcc/gengenrtl.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/gengenrtl.c
-+++ gcc-4_5-branch/gcc/gengenrtl.c
-@@ -146,6 +146,10 @@ special_rtx (int idx)
+
+=== modified file 'gcc/gengenrtl.c'
+--- old/gcc/gengenrtl.c 2007-08-22 23:30:39 +0000
++++ new/gcc/gengenrtl.c 2011-01-05 12:12:18 +0000
+@@ -146,6 +146,10 @@
|| strcmp (defs[idx].enumname, "REG") == 0
|| strcmp (defs[idx].enumname, "SUBREG") == 0
|| strcmp (defs[idx].enumname, "MEM") == 0
@@ -2113,11 +1928,11 @@ Index: gcc-4_5-branch/gcc/gengenrtl.c
|| strcmp (defs[idx].enumname, "CONST_VECTOR") == 0);
}
-Index: gcc-4_5-branch/gcc/haifa-sched.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/haifa-sched.c
-+++ gcc-4_5-branch/gcc/haifa-sched.c
-@@ -4231,7 +4231,7 @@ xrecalloc (void *p, size_t new_nmemb, si
+
+=== modified file 'gcc/haifa-sched.c'
+--- old/gcc/haifa-sched.c 2010-08-12 08:14:47 +0000
++++ new/gcc/haifa-sched.c 2011-01-05 12:12:18 +0000
+@@ -4231,7 +4231,7 @@
/* Helper function.
Find fallthru edge from PRED. */
edge
@@ -2126,7 +1941,7 @@ Index: gcc-4_5-branch/gcc/haifa-sched.c
{
edge e;
edge_iterator ei;
-@@ -4298,7 +4298,7 @@ init_before_recovery (basic_block *befor
+@@ -4298,7 +4298,7 @@
edge e;
last = EXIT_BLOCK_PTR->prev_bb;
@@ -2135,7 +1950,7 @@ Index: gcc-4_5-branch/gcc/haifa-sched.c
if (e)
{
-@@ -5234,6 +5234,11 @@ check_cfg (rtx head, rtx tail)
+@@ -5234,6 +5234,11 @@
gcc_assert (/* Usual case. */
(EDGE_COUNT (bb->succs) > 1
&& !BARRIER_P (NEXT_INSN (head)))
@@ -2147,11 +1962,11 @@ Index: gcc-4_5-branch/gcc/haifa-sched.c
/* Or jump to the next instruction. */
|| (EDGE_COUNT (bb->succs) == 1
&& (BB_HEAD (EDGE_I (bb->succs, 0)->dest)
-Index: gcc-4_5-branch/gcc/ifcvt.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/ifcvt.c
-+++ gcc-4_5-branch/gcc/ifcvt.c
-@@ -105,7 +105,7 @@ static int find_if_case_1 (basic_block,
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c 2010-11-26 12:03:32 +0000
++++ new/gcc/ifcvt.c 2011-01-05 12:12:18 +0000
+@@ -105,7 +105,7 @@
static int find_if_case_2 (basic_block, edge, edge);
static int find_memory (rtx *, void *);
static int dead_or_predicable (basic_block, basic_block, basic_block,
@@ -2160,7 +1975,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
static void noce_emit_move_insn (rtx, rtx);
static rtx block_has_only_trap (basic_block);
-@@ -3791,6 +3791,7 @@ find_if_case_1 (basic_block test_bb, edg
+@@ -3791,6 +3791,7 @@
basic_block then_bb = then_edge->dest;
basic_block else_bb = else_edge->dest;
basic_block new_bb;
@@ -2168,7 +1983,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
int then_bb_index;
/* If we are partitioning hot/cold basic blocks, we don't want to
-@@ -3840,9 +3841,16 @@ find_if_case_1 (basic_block test_bb, edg
+@@ -3840,9 +3841,16 @@
predictable_edge_p (then_edge)))))
return FALSE;
@@ -2186,7 +2001,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
return FALSE;
/* Conversion went ok, including moving the insns and fixing up the
-@@ -3859,6 +3867,9 @@ find_if_case_1 (basic_block test_bb, edg
+@@ -3859,6 +3867,9 @@
redirect_edge_succ (FALLTHRU_EDGE (test_bb), else_bb);
new_bb = 0;
}
@@ -2196,7 +2011,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
else
new_bb = redirect_edge_and_branch_force (FALLTHRU_EDGE (test_bb),
else_bb);
-@@ -3957,7 +3968,7 @@ find_if_case_2 (basic_block test_bb, edg
+@@ -3957,7 +3968,7 @@
return FALSE;
/* Registers set are dead, or are predicable. */
@@ -2205,7 +2020,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
return FALSE;
/* Conversion went ok, including moving the insns and fixing up the
-@@ -3995,12 +4006,34 @@ find_memory (rtx *px, void *data ATTRIBU
+@@ -3995,12 +4006,34 @@
static int
dead_or_predicable (basic_block test_bb, basic_block merge_bb,
@@ -2242,7 +2057,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
jump = BB_END (test_bb);
-@@ -4220,10 +4253,9 @@ dead_or_predicable (basic_block test_bb,
+@@ -4220,10 +4253,9 @@
old_dest = JUMP_LABEL (jump);
if (other_bb != new_dest)
{
@@ -2255,7 +2070,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
goto cancel;
}
-@@ -4234,7 +4266,7 @@ dead_or_predicable (basic_block test_bb,
+@@ -4234,7 +4266,7 @@
if (other_bb != new_dest)
{
@@ -2264,11 +2079,11 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest);
if (reversep)
-Index: gcc-4_5-branch/gcc/jump.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/jump.c
-+++ gcc-4_5-branch/gcc/jump.c
-@@ -29,7 +29,8 @@ along with GCC; see the file COPYING3.
+
+=== modified file 'gcc/jump.c'
+--- old/gcc/jump.c 2010-12-13 10:05:52 +0000
++++ new/gcc/jump.c 2011-01-05 12:12:18 +0000
+@@ -29,7 +29,8 @@
JUMP_LABEL internal field. With this we can detect labels that
become unused because of the deletion of all the jumps that
formerly used them. The JUMP_LABEL info is sometimes looked
@@ -2278,7 +2093,7 @@ Index: gcc-4_5-branch/gcc/jump.c
The subroutines redirect_jump and invert_jump are used
from other passes as well. */
-@@ -742,10 +743,10 @@ condjump_p (const_rtx insn)
+@@ -742,10 +743,10 @@
return (GET_CODE (x) == IF_THEN_ELSE
&& ((GET_CODE (XEXP (x, 2)) == PC
&& (GET_CODE (XEXP (x, 1)) == LABEL_REF
@@ -2291,7 +2106,7 @@ Index: gcc-4_5-branch/gcc/jump.c
}
/* Return nonzero if INSN is a (possibly) conditional jump inside a
-@@ -774,11 +775,11 @@ condjump_in_parallel_p (const_rtx insn)
+@@ -774,11 +775,11 @@
return 0;
if (XEXP (SET_SRC (x), 2) == pc_rtx
&& (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF
@@ -2305,7 +2120,7 @@ Index: gcc-4_5-branch/gcc/jump.c
return 1;
return 0;
}
-@@ -840,8 +841,9 @@ any_condjump_p (const_rtx insn)
+@@ -840,8 +841,9 @@
a = GET_CODE (XEXP (SET_SRC (x), 1));
b = GET_CODE (XEXP (SET_SRC (x), 2));
@@ -2317,7 +2132,7 @@ Index: gcc-4_5-branch/gcc/jump.c
}
/* Return the label of a conditional jump. */
-@@ -878,6 +880,7 @@ returnjump_p_1 (rtx *loc, void *data ATT
+@@ -878,6 +880,7 @@
switch (GET_CODE (x))
{
case RETURN:
@@ -2325,7 +2140,7 @@ Index: gcc-4_5-branch/gcc/jump.c
case EH_RETURN:
return true;
-@@ -1200,7 +1203,7 @@ delete_related_insns (rtx insn)
+@@ -1200,7 +1203,7 @@
/* If deleting a jump, decrement the count of the label,
and delete the label if it is now unused. */
@@ -2334,7 +2149,7 @@ Index: gcc-4_5-branch/gcc/jump.c
{
rtx lab = JUMP_LABEL (insn), lab_next;
-@@ -1331,6 +1334,18 @@ delete_for_peephole (rtx from, rtx to)
+@@ -1331,6 +1334,18 @@
is also an unconditional jump in that case. */
}
@@ -2353,7 +2168,7 @@ Index: gcc-4_5-branch/gcc/jump.c
/* Throughout LOC, redirect OLABEL to NLABEL. Treat null OLABEL or
NLABEL as a return. Accrue modifications into the change group. */
-@@ -1342,37 +1357,19 @@ redirect_exp_1 (rtx *loc, rtx olabel, rt
+@@ -1342,37 +1357,19 @@
int i;
const char *fmt;
@@ -2372,9 +2187,7 @@ Index: gcc-4_5-branch/gcc/jump.c
- }
- }
- else if (code == RETURN && olabel == 0)
-+ if ((code == LABEL_REF && XEXP (x, 0) == olabel)
-+ || x == olabel)
- {
+- {
- if (nlabel)
- x = gen_rtx_LABEL_REF (Pmode, nlabel);
- else
@@ -2382,6 +2195,9 @@ Index: gcc-4_5-branch/gcc/jump.c
- if (loc == &PATTERN (insn))
- x = gen_rtx_SET (VOIDmode, pc_rtx, x);
- validate_change (insn, loc, x, 1);
++ if ((code == LABEL_REF && XEXP (x, 0) == olabel)
++ || x == olabel)
++ {
+ validate_change (insn, loc, redirect_target (nlabel), 1);
return;
}
@@ -2397,7 +2213,7 @@ Index: gcc-4_5-branch/gcc/jump.c
return;
}
-@@ -1409,6 +1406,7 @@ redirect_jump_1 (rtx jump, rtx nlabel)
+@@ -1409,6 +1406,7 @@
int ochanges = num_validated_changes ();
rtx *loc, asmop;
@@ -2405,7 +2221,7 @@ Index: gcc-4_5-branch/gcc/jump.c
asmop = extract_asm_operands (PATTERN (jump));
if (asmop)
{
-@@ -1430,17 +1428,20 @@ redirect_jump_1 (rtx jump, rtx nlabel)
+@@ -1430,17 +1428,20 @@
jump target label is unused as a result, it and the code following
it may be deleted.
@@ -2429,7 +2245,7 @@ Index: gcc-4_5-branch/gcc/jump.c
if (nlabel == olabel)
return 1;
-@@ -1452,7 +1453,7 @@ redirect_jump (rtx jump, rtx nlabel, int
+@@ -1452,7 +1453,7 @@
}
/* Fix up JUMP_LABEL and label ref counts after OLABEL has been replaced with
@@ -2438,7 +2254,7 @@ Index: gcc-4_5-branch/gcc/jump.c
If DELETE_UNUSED is positive, delete related insn to OLABEL if its ref
count has dropped to zero. */
void
-@@ -1468,13 +1469,14 @@ redirect_jump_2 (rtx jump, rtx olabel, r
+@@ -1468,13 +1469,14 @@
about this. */
gcc_assert (delete_unused >= 0);
JUMP_LABEL (jump) = nlabel;
@@ -2455,7 +2271,7 @@ Index: gcc-4_5-branch/gcc/jump.c
remove_note (jump, note);
else
{
-@@ -1483,7 +1485,8 @@ redirect_jump_2 (rtx jump, rtx olabel, r
+@@ -1483,7 +1485,8 @@
}
}
@@ -2465,11 +2281,11 @@ Index: gcc-4_5-branch/gcc/jump.c
/* Undefined labels will remain outside the insn stream. */
&& INSN_UID (olabel))
delete_related_insns (olabel);
-Index: gcc-4_5-branch/gcc/opts.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/opts.c
-+++ gcc-4_5-branch/gcc/opts.c
-@@ -909,6 +909,7 @@ decode_options (unsigned int argc, const
+
+=== modified file 'gcc/opts.c'
+--- old/gcc/opts.c 2010-12-10 15:33:37 +0000
++++ new/gcc/opts.c 2011-01-05 12:12:18 +0000
+@@ -908,6 +908,7 @@
flag_ipa_cp = opt2;
flag_ipa_sra = opt2;
flag_ee = opt2;
@@ -2477,11 +2293,11 @@ Index: gcc-4_5-branch/gcc/opts.c
/* Track fields in field-sensitive alias analysis. */
set_param_value ("max-fields-for-field-sensitive",
-Index: gcc-4_5-branch/gcc/print-rtl.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/print-rtl.c
-+++ gcc-4_5-branch/gcc/print-rtl.c
-@@ -308,9 +308,16 @@ print_rtx (const_rtx in_rtx)
+
+=== modified file 'gcc/print-rtl.c'
+--- old/gcc/print-rtl.c 2010-03-26 16:18:51 +0000
++++ new/gcc/print-rtl.c 2011-01-05 12:12:18 +0000
+@@ -308,9 +308,16 @@
}
}
else if (i == 8 && JUMP_P (in_rtx) && JUMP_LABEL (in_rtx) != NULL)
@@ -2501,11 +2317,11 @@ Index: gcc-4_5-branch/gcc/print-rtl.c
else if (i == 0 && GET_CODE (in_rtx) == VALUE)
{
#ifndef GENERATOR_FILE
-Index: gcc-4_5-branch/gcc/reorg.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/reorg.c
-+++ gcc-4_5-branch/gcc/reorg.c
-@@ -161,8 +161,11 @@ static rtx *unfilled_firstobj;
+
+=== modified file 'gcc/reorg.c'
+--- old/gcc/reorg.c 2010-09-15 22:51:44 +0000
++++ new/gcc/reorg.c 2011-01-05 12:12:18 +0000
+@@ -161,8 +161,11 @@
#define unfilled_slots_next \
((rtx *) obstack_next_free (&unfilled_slots_obstack))
@@ -2519,7 +2335,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* Mapping between INSN_UID's and position in the code since INSN_UID's do
not always monotonically increase. */
-@@ -175,7 +178,7 @@ static int stop_search_p (rtx, int);
+@@ -175,7 +178,7 @@
static int resource_conflicts_p (struct resources *, struct resources *);
static int insn_references_resource_p (rtx, struct resources *, bool);
static int insn_sets_resource_p (rtx, struct resources *, bool);
@@ -2528,7 +2344,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
static rtx emit_delay_sequence (rtx, rtx, int);
static rtx add_to_delay_list (rtx, rtx);
static rtx delete_from_delay_slot (rtx);
-@@ -220,6 +223,15 @@ static void relax_delay_slots (rtx);
+@@ -220,6 +223,15 @@
static void make_return_insns (rtx);
#endif
@@ -2544,7 +2360,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* Return TRUE if this insn should stop the search for insn to fill delay
slots. LABELS_P indicates that labels should terminate the search.
In all cases, jumps terminate the search. */
-@@ -335,23 +347,29 @@ insn_sets_resource_p (rtx insn, struct r
+@@ -335,23 +347,29 @@
??? There may be a problem with the current implementation. Suppose
we start with a bare RETURN insn and call find_end_label. It may set
@@ -2580,7 +2396,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* Otherwise, see if there is a label at the end of the function. If there
is, it must be that RETURN insns aren't needed, so that is our return
-@@ -366,44 +384,44 @@ find_end_label (void)
+@@ -366,44 +384,44 @@
/* When a target threads its epilogue we might already have a
suitable return insn. If so put a label before it for the
@@ -2638,7 +2454,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
}
else
{
-@@ -413,19 +431,16 @@ find_end_label (void)
+@@ -413,19 +431,16 @@
&& ! HAVE_return
#endif
)
@@ -2664,7 +2480,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
#ifdef HAVE_return
/* We don't bother trying to create a return insn if the
epilogue has filled delay-slots; we would have to try and
-@@ -437,19 +452,21 @@ find_end_label (void)
+@@ -437,19 +452,21 @@
/* The return we make may have delay slots too. */
rtx insn = gen_return ();
insn = emit_jump_insn (insn);
@@ -2688,7 +2504,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
}
/* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
-@@ -797,10 +814,8 @@ optimize_skip (rtx insn)
+@@ -797,10 +814,8 @@
if ((next_trial == next_active_insn (JUMP_LABEL (insn))
&& ! (next_trial == 0 && crtl->epilogue_delay_list != 0))
|| (next_trial != 0
@@ -2701,7 +2517,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
{
if (eligible_for_annul_false (insn, 0, trial, flags))
{
-@@ -819,13 +834,11 @@ optimize_skip (rtx insn)
+@@ -819,13 +834,11 @@
branch, thread our jump to the target of that branch. Don't
change this into a RETURN here, because it may not accept what
we have in the delay slot. We'll fix this up later. */
@@ -2718,7 +2534,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
if (target_label)
{
-@@ -866,7 +879,7 @@ get_jump_flags (rtx insn, rtx label)
+@@ -866,7 +879,7 @@
if (JUMP_P (insn)
&& (condjump_p (insn) || condjump_in_parallel_p (insn))
&& INSN_UID (insn) <= max_uid
@@ -2727,7 +2543,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
&& INSN_UID (label) <= max_uid)
flags
= (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
-@@ -1038,7 +1051,7 @@ get_branch_condition (rtx insn, rtx targ
+@@ -1038,7 +1051,7 @@
pat = XVECEXP (pat, 0, 0);
if (GET_CODE (pat) == RETURN)
@@ -2736,7 +2552,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
return 0;
-@@ -1318,7 +1331,11 @@ steal_delay_list_from_target (rtx insn,
+@@ -1318,7 +1331,11 @@
}
/* Show the place to which we will be branching. */
@@ -2749,7 +2565,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* Add any new insns to the delay list and update the count of the
number of slots filled. */
-@@ -1358,8 +1375,7 @@ steal_delay_list_from_fallthrough (rtx i
+@@ -1358,8 +1375,7 @@
/* We can't do anything if SEQ's delay insn isn't an
unconditional branch. */
@@ -2759,7 +2575,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
return delay_list;
for (i = 1; i < XVECLEN (seq, 0); i++)
-@@ -1827,7 +1843,7 @@ own_thread_p (rtx thread, rtx label, int
+@@ -1827,7 +1843,7 @@
rtx insn;
/* We don't own the function end. */
@@ -2768,7 +2584,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
return 0;
/* Get the first active insn, or THREAD, if it is an active insn. */
-@@ -2245,7 +2261,8 @@ fill_simple_delay_slots (int non_jumps_p
+@@ -2245,7 +2261,8 @@
&& (!JUMP_P (insn)
|| ((condjump_p (insn) || condjump_in_parallel_p (insn))
&& ! simplejump_p (insn)
@@ -2778,7 +2594,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
{
/* Invariant: If insn is a JUMP_INSN, the insn's jump
label. Otherwise, zero. */
-@@ -2270,7 +2287,7 @@ fill_simple_delay_slots (int non_jumps_p
+@@ -2270,7 +2287,7 @@
target = JUMP_LABEL (insn);
}
@@ -2787,7 +2603,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
{
next_trial = next_nonnote_insn (trial);
-@@ -2349,6 +2366,7 @@ fill_simple_delay_slots (int non_jumps_p
+@@ -2349,6 +2366,7 @@
&& JUMP_P (trial)
&& simplejump_p (trial)
&& (target == 0 || JUMP_LABEL (trial) == target)
@@ -2795,7 +2611,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
&& (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
&& ! (NONJUMP_INSN_P (next_trial)
&& GET_CODE (PATTERN (next_trial)) == SEQUENCE)
-@@ -2371,7 +2389,7 @@ fill_simple_delay_slots (int non_jumps_p
+@@ -2371,7 +2389,7 @@
if (new_label != 0)
new_label = get_label_before (new_label);
else
@@ -2804,7 +2620,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
if (new_label)
{
-@@ -2503,7 +2521,8 @@ fill_simple_delay_slots (int non_jumps_p
+@@ -2503,7 +2521,8 @@
/* Follow any unconditional jump at LABEL;
return the ultimate label reached by any such chain of jumps.
@@ -2814,7 +2630,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
If LABEL is not followed by a jump, return LABEL.
If the chain loops or we can't find end, return LABEL,
since that tells caller to avoid changing the insn. */
-@@ -2518,6 +2537,7 @@ follow_jumps (rtx label)
+@@ -2518,6 +2537,7 @@
for (depth = 0;
(depth < 10
@@ -2822,7 +2638,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
&& (insn = next_active_insn (value)) != 0
&& JUMP_P (insn)
&& ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn)
-@@ -2527,18 +2547,22 @@ follow_jumps (rtx label)
+@@ -2527,18 +2547,22 @@
&& BARRIER_P (next));
depth++)
{
@@ -2851,7 +2667,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
}
if (depth == 10)
return label;
-@@ -2901,6 +2925,7 @@ fill_slots_from_thread (rtx insn, rtx co
+@@ -2901,6 +2925,7 @@
arithmetic insn after the jump insn and put the arithmetic insn in the
delay slot. If we can't do this, return. */
if (delay_list == 0 && likely && new_thread
@@ -2859,7 +2675,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
&& NONJUMP_INSN_P (new_thread)
&& GET_CODE (PATTERN (new_thread)) != ASM_INPUT
&& asm_noperands (PATTERN (new_thread)) < 0)
-@@ -2985,16 +3010,14 @@ fill_slots_from_thread (rtx insn, rtx co
+@@ -2985,16 +3010,14 @@
gcc_assert (thread_if_true);
@@ -2879,7 +2695,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
else if (LABEL_P (new_thread))
label = new_thread;
else
-@@ -3340,11 +3363,12 @@ relax_delay_slots (rtx first)
+@@ -3340,11 +3363,12 @@
group of consecutive labels. */
if (JUMP_P (insn)
&& (condjump_p (insn) || condjump_in_parallel_p (insn))
@@ -2895,7 +2711,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
if (target_label && next_active_insn (target_label) == next
&& ! condjump_in_parallel_p (insn))
-@@ -3359,9 +3383,8 @@ relax_delay_slots (rtx first)
+@@ -3359,9 +3383,8 @@
/* See if this jump conditionally branches around an unconditional
jump. If so, invert this jump and point it to the target of the
second jump. */
@@ -2906,7 +2722,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
&& target_label
&& next_active_insn (target_label) == next_active_insn (next)
&& no_labels_between_p (insn, next))
-@@ -3403,8 +3426,7 @@ relax_delay_slots (rtx first)
+@@ -3403,8 +3426,7 @@
Don't do this if we expect the conditional branch to be true, because
we would then be making the more common case longer. */
@@ -2916,7 +2732,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
&& (other = prev_active_insn (insn)) != 0
&& any_condjump_p (other)
&& no_labels_between_p (other, insn)
-@@ -3445,10 +3467,10 @@ relax_delay_slots (rtx first)
+@@ -3445,10 +3467,10 @@
Only do so if optimizing for size since this results in slower, but
smaller code. */
if (optimize_function_for_size_p (cfun)
@@ -2929,7 +2745,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
{
rtx after;
int i;
-@@ -3487,14 +3509,16 @@ relax_delay_slots (rtx first)
+@@ -3487,14 +3509,16 @@
continue;
target_label = JUMP_LABEL (delay_insn);
@@ -2948,7 +2764,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
if (trial && trial != target_label
&& redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
-@@ -3517,7 +3541,7 @@ relax_delay_slots (rtx first)
+@@ -3517,7 +3541,7 @@
later incorrectly compute register live/death info. */
rtx tmp = next_active_insn (trial);
if (tmp == 0)
@@ -2957,7 +2773,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
if (tmp)
{
-@@ -3537,14 +3561,12 @@ relax_delay_slots (rtx first)
+@@ -3537,14 +3561,12 @@
delay list and that insn is redundant, thread the jump. */
if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
&& XVECLEN (PATTERN (trial), 0) == 2
@@ -2975,7 +2791,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
if (target_label
&& redirect_with_delay_slots_safe_p (delay_insn, target_label,
-@@ -3622,16 +3644,15 @@ relax_delay_slots (rtx first)
+@@ -3622,16 +3644,15 @@
a RETURN here. */
if (! INSN_ANNULLED_BRANCH_P (delay_insn)
&& any_condjump_p (delay_insn)
@@ -2995,7 +2811,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* find_end_label can generate a new label. Check this first. */
if (label
-@@ -3692,7 +3713,8 @@ static void
+@@ -3692,7 +3713,8 @@
make_return_insns (rtx first)
{
rtx insn, jump_insn, pat;
@@ -3005,7 +2821,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
int slots, i;
#ifdef DELAY_SLOTS_FOR_EPILOGUE
-@@ -3707,18 +3729,25 @@ make_return_insns (rtx first)
+@@ -3707,18 +3729,25 @@
#endif
/* See if there is a RETURN insn in the function other than the one we
@@ -3036,7 +2852,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* Clear the list of insns to fill so we can use it. */
obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
-@@ -3726,13 +3755,27 @@ make_return_insns (rtx first)
+@@ -3726,13 +3755,27 @@
for (insn = first; insn; insn = NEXT_INSN (insn))
{
int flags;
@@ -3066,7 +2882,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
continue;
pat = PATTERN (insn);
-@@ -3740,14 +3783,12 @@ make_return_insns (rtx first)
+@@ -3740,14 +3783,12 @@
/* If we can't make the jump into a RETURN, try to redirect it to the best
RETURN and go on to the next insn. */
@@ -3084,7 +2900,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
continue;
}
-@@ -3787,7 +3828,7 @@ make_return_insns (rtx first)
+@@ -3787,7 +3828,7 @@
RETURN, delete the SEQUENCE and output the individual insns,
followed by the RETURN. Then set things up so we try to find
insns for its delay slots, if it needs some. */
@@ -3093,7 +2909,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
{
rtx prev = PREV_INSN (insn);
-@@ -3804,13 +3845,16 @@ make_return_insns (rtx first)
+@@ -3804,13 +3845,16 @@
else
/* It is probably more efficient to keep this with its current
delay slot as a branch to a RETURN. */
@@ -3112,7 +2928,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
fill_simple_delay_slots (1);
fill_simple_delay_slots (0);
-@@ -3878,7 +3922,7 @@ dbr_schedule (rtx first)
+@@ -3878,7 +3922,7 @@
init_resource_info (epilogue_insn);
/* Show we haven't computed an end-of-function label yet. */
@@ -3121,7 +2937,7 @@ Index: gcc-4_5-branch/gcc/reorg.c
/* Initialize the statistics for this function. */
memset (num_insns_needing_delays, 0, sizeof num_insns_needing_delays);
-@@ -3900,11 +3944,23 @@ dbr_schedule (rtx first)
+@@ -3900,11 +3944,23 @@
/* If we made an end of function label, indicate that it is now
safe to delete it by undoing our prior adjustment to LABEL_NUSES.
If it is now unused, delete it. */
@@ -3148,11 +2964,11 @@ Index: gcc-4_5-branch/gcc/reorg.c
make_return_insns (first);
#endif
-Index: gcc-4_5-branch/gcc/resource.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/resource.c
-+++ gcc-4_5-branch/gcc/resource.c
-@@ -495,6 +495,8 @@ find_dead_or_set_registers (rtx target,
+
+=== modified file 'gcc/resource.c'
+--- old/gcc/resource.c 2009-11-25 10:55:54 +0000
++++ new/gcc/resource.c 2011-01-05 12:12:18 +0000
+@@ -495,6 +495,8 @@
|| GET_CODE (PATTERN (this_jump_insn)) == RETURN)
{
next = JUMP_LABEL (this_jump_insn);
@@ -3161,7 +2977,7 @@ Index: gcc-4_5-branch/gcc/resource.c
if (jump_insn == 0)
{
jump_insn = insn;
-@@ -562,9 +564,10 @@ find_dead_or_set_registers (rtx target,
+@@ -562,9 +564,10 @@
AND_COMPL_HARD_REG_SET (scratch, needed.regs);
AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch);
@@ -3175,7 +2991,7 @@ Index: gcc-4_5-branch/gcc/resource.c
find_dead_or_set_registers (next,
&fallthrough_res, 0, jump_count,
set, needed);
-@@ -1097,6 +1100,8 @@ mark_target_live_regs (rtx insns, rtx ta
+@@ -1097,6 +1100,8 @@
struct resources new_resources;
rtx stop_insn = next_active_insn (jump_insn);
@@ -3184,11 +3000,11 @@ Index: gcc-4_5-branch/gcc/resource.c
mark_target_live_regs (insns, next_active_insn (jump_target),
&new_resources);
CLEAR_RESOURCE (&set);
-Index: gcc-4_5-branch/gcc/rtl.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/rtl.c
-+++ gcc-4_5-branch/gcc/rtl.c
-@@ -256,6 +256,8 @@ copy_rtx (rtx orig)
+
+=== modified file 'gcc/rtl.c'
+--- old/gcc/rtl.c 2010-12-13 10:05:52 +0000
++++ new/gcc/rtl.c 2011-01-05 12:12:18 +0000
+@@ -256,6 +256,8 @@
case CODE_LABEL:
case PC:
case CC0:
@@ -3197,11 +3013,11 @@ Index: gcc-4_5-branch/gcc/rtl.c
case SCRATCH:
/* SCRATCH must be shared because they represent distinct values. */
return orig;
-Index: gcc-4_5-branch/gcc/rtl.def
-===================================================================
---- gcc-4_5-branch.orig/gcc/rtl.def
-+++ gcc-4_5-branch/gcc/rtl.def
-@@ -296,6 +296,10 @@ DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXT
+
+=== modified file 'gcc/rtl.def'
+--- old/gcc/rtl.def 2010-04-02 18:54:46 +0000
++++ new/gcc/rtl.def 2011-01-05 12:12:18 +0000
+@@ -296,6 +296,10 @@
DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
@@ -3212,11 +3028,11 @@ Index: gcc-4_5-branch/gcc/rtl.def
/* Special for EH return from subroutine. */
DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
-Index: gcc-4_5-branch/gcc/rtl.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/rtl.h
-+++ gcc-4_5-branch/gcc/rtl.h
-@@ -411,6 +411,10 @@ struct GTY(()) rtvec_def {
+
+=== modified file 'gcc/rtl.h'
+--- old/gcc/rtl.h 2010-11-16 22:17:17 +0000
++++ new/gcc/rtl.h 2011-01-05 12:12:18 +0000
+@@ -411,6 +411,10 @@
(JUMP_P (INSN) && (GET_CODE (PATTERN (INSN)) == ADDR_VEC || \
GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC))
@@ -3227,7 +3043,7 @@ Index: gcc-4_5-branch/gcc/rtl.h
/* 1 if X is a unary operator. */
#define UNARY_P(X) \
-@@ -1998,6 +2002,8 @@ enum global_rtl_index
+@@ -1998,6 +2002,8 @@
{
GR_PC,
GR_CC0,
@@ -3236,7 +3052,7 @@ Index: gcc-4_5-branch/gcc/rtl.h
GR_STACK_POINTER,
GR_FRAME_POINTER,
/* For register elimination to work properly these hard_frame_pointer_rtx,
-@@ -2032,6 +2038,8 @@ extern GTY(()) rtx global_rtl[GR_MAX];
+@@ -2032,6 +2038,8 @@
/* Standard pieces of rtx, to be substituted directly into things. */
#define pc_rtx (global_rtl[GR_PC])
@@ -3245,11 +3061,11 @@ Index: gcc-4_5-branch/gcc/rtl.h
#define cc0_rtx (global_rtl[GR_CC0])
/* All references to certain hard regs, except those created
-Index: gcc-4_5-branch/gcc/rtlanal.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/rtlanal.c
-+++ gcc-4_5-branch/gcc/rtlanal.c
-@@ -2673,6 +2673,7 @@ tablejump_p (const_rtx insn, rtx *labelp
+
+=== modified file 'gcc/rtlanal.c'
+--- old/gcc/rtlanal.c 2010-11-16 22:17:17 +0000
++++ new/gcc/rtlanal.c 2011-01-05 12:12:18 +0000
+@@ -2673,6 +2673,7 @@
if (JUMP_P (insn)
&& (label = JUMP_LABEL (insn)) != NULL_RTX
@@ -3257,11 +3073,11 @@ Index: gcc-4_5-branch/gcc/rtlanal.c
&& (table = next_active_insn (label)) != NULL_RTX
&& JUMP_TABLE_DATA_P (table))
{
-Index: gcc-4_5-branch/gcc/sched-int.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/sched-int.h
-+++ gcc-4_5-branch/gcc/sched-int.h
-@@ -199,7 +199,7 @@ extern int max_issue (struct ready_list
+
+=== modified file 'gcc/sched-int.h'
+--- old/gcc/sched-int.h 2010-06-02 16:31:39 +0000
++++ new/gcc/sched-int.h 2011-01-05 12:12:18 +0000
+@@ -199,7 +199,7 @@
extern void ebb_compute_jump_reg_dependencies (rtx, regset, regset, regset);
@@ -3270,11 +3086,11 @@ Index: gcc-4_5-branch/gcc/sched-int.h
extern void (* sched_init_only_bb) (basic_block, basic_block);
extern basic_block (* sched_split_block) (basic_block, rtx);
-Index: gcc-4_5-branch/gcc/sched-vis.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/sched-vis.c
-+++ gcc-4_5-branch/gcc/sched-vis.c
-@@ -549,6 +549,9 @@ print_pattern (char *buf, const_rtx x, i
+
+=== modified file 'gcc/sched-vis.c'
+--- old/gcc/sched-vis.c 2009-11-25 10:55:54 +0000
++++ new/gcc/sched-vis.c 2011-01-05 12:12:18 +0000
+@@ -549,6 +549,9 @@
case RETURN:
sprintf (buf, "return");
break;
@@ -3284,11 +3100,11 @@ Index: gcc-4_5-branch/gcc/sched-vis.c
case CALL:
print_exp (buf, x, verbose);
break;
-Index: gcc-4_5-branch/gcc/sel-sched-ir.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/sel-sched-ir.c
-+++ gcc-4_5-branch/gcc/sel-sched-ir.c
-@@ -686,7 +686,7 @@ merge_fences (fence_t f, insn_t insn,
+
+=== modified file 'gcc/sel-sched-ir.c'
+--- old/gcc/sel-sched-ir.c 2010-08-31 11:52:01 +0000
++++ new/gcc/sel-sched-ir.c 2011-01-05 12:12:18 +0000
+@@ -686,7 +686,7 @@
/* Find fallthrough edge. */
gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb);
@@ -3297,11 +3113,11 @@ Index: gcc-4_5-branch/gcc/sel-sched-ir.c
if (!candidate
|| (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn)
-Index: gcc-4_5-branch/gcc/sel-sched.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/sel-sched.c
-+++ gcc-4_5-branch/gcc/sel-sched.c
-@@ -617,8 +617,8 @@ in_fallthru_bb_p (rtx insn, rtx succ)
+
+=== modified file 'gcc/sel-sched.c'
+--- old/gcc/sel-sched.c 2010-11-12 15:47:38 +0000
++++ new/gcc/sel-sched.c 2011-01-05 12:12:18 +0000
+@@ -617,8 +617,8 @@
if (bb == BLOCK_FOR_INSN (succ))
return true;
@@ -3312,7 +3128,7 @@ Index: gcc-4_5-branch/gcc/sel-sched.c
else
return false;
-@@ -4911,7 +4911,7 @@ move_cond_jump (rtx insn, bnd_t bnd)
+@@ -4911,7 +4911,7 @@
next = PREV_INSN (insn);
BND_TO (bnd) = insn;
@@ -3321,11 +3137,11 @@ Index: gcc-4_5-branch/gcc/sel-sched.c
block_next = ft_edge->dest;
/* There must be a fallthrough block (or where should go
control flow in case of false jump predicate otherwise?). */
-Index: gcc-4_5-branch/gcc/vec.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/vec.h
-+++ gcc-4_5-branch/gcc/vec.h
-@@ -188,6 +188,18 @@ along with GCC; see the file COPYING3.
+
+=== modified file 'gcc/vec.h'
+--- old/gcc/vec.h 2010-01-09 14:46:25 +0000
++++ new/gcc/vec.h 2011-01-05 12:12:18 +0000
+@@ -188,6 +188,18 @@
#define VEC_iterate(T,V,I,P) (VEC_OP(T,base,iterate)(VEC_BASE(V),I,&(P)))
@@ -3344,3 +3160,4 @@ Index: gcc-4_5-branch/gcc/vec.h
/* Allocate new vector.
VEC(T,A) *VEC_T_A_alloc(int reserve);
+
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch
index aa9d6aa368..47b897d5e7 100644
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch
@@ -1,25 +1,3 @@
-2011-02-08 Andrew Stubbs <ams@codesourcery.com>
-
- Backport from FSF mainline:
-
- 2010-06-30 H.J. Lu <hongjiu.lu@intel.com>
-
- PR target/44721
- * config/i386/i386.md (peephole2 for arithmetic ops with memory):
- Fix last commit.
-
- 2010-06-30 Richard Guenther <rguenther@suse.de>
-
- PR target/44722
- * config/i386/i386.md (peephole2 for fix:SSEMODEI24): Guard
- against oscillation with reverse peephole2.
-
- 2010-07-01 Bernd Schmidt <bernds@codesourcery.com>
-
- PR target/44727
- * config/i386/i386.md (peephole2 for arithmetic ops with memory):
- Make sure operand 0 dies.
-
2010-12-03 Yao Qi <yao@codesourcery.com>
* config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix
@@ -96,10 +74,8 @@
empty constraint string.
=== added file 'gcc/config/arm/arm-ldmstm.ml'
-Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
-===================================================================
---- /dev/null
-+++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
+--- old/gcc/config/arm/arm-ldmstm.ml 1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/arm-ldmstm.ml 2010-11-16 13:08:47 +0000
@@ -0,0 +1,333 @@
+(* Auto-generate ARM ldm/stm patterns
+ Copyright (C) 2010 Free Software Foundation, Inc.
@@ -434,11 +410,11 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
+" <http://www.gnu.org/licenses/>. */";
+""];
+ patterns ();
-Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h
-+++ gcc-4_5-branch/gcc/config/arm/arm-protos.h
-@@ -100,14 +100,11 @@ extern int symbol_mentioned_p (rtx);
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h 2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm-protos.h 2011-01-05 18:20:37 +0000
+@@ -100,14 +100,11 @@
extern int label_mentioned_p (rtx);
extern RTX_CODE minmax_code (rtx);
extern int adjacent_mem_locations (rtx, rtx);
@@ -458,11 +434,11 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
extern int arm_gen_movmemqi (rtx *);
extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
-Index: gcc-4_5-branch/gcc/config/arm/arm.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.c
-+++ gcc-4_5-branch/gcc/config/arm/arm.c
-@@ -753,6 +753,12 @@ static const char * const arm_condition_
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c 2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm.c 2011-01-05 18:20:37 +0000
+@@ -753,6 +753,12 @@
"hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
};
@@ -475,13 +451,146 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
#define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
#define streq(string1, string2) (strcmp (string1, string2) == 0)
-@@ -9680,24 +9686,125 @@ adjacent_mem_locations (rtx a, rtx b)
+@@ -9680,142 +9686,16 @@
return 0;
}
-int
-load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
- HOST_WIDE_INT *load_offset)
+-{
+- int unsorted_regs[4];
+- HOST_WIDE_INT unsorted_offsets[4];
+- int order[4];
+- int base_reg = -1;
+- int i;
+-
+- if (low_irq_latency)
+- return 0;
+-
+- /* Can only handle 2, 3, or 4 insns at present,
+- though could be easily extended if required. */
+- gcc_assert (nops >= 2 && nops <= 4);
+-
+- memset (order, 0, 4 * sizeof (int));
+-
+- /* Loop over the operands and check that the memory references are
+- suitable (i.e. immediate offsets from the same base register). At
+- the same time, extract the target register, and the memory
+- offsets. */
+- for (i = 0; i < nops; i++)
+- {
+- rtx reg;
+- rtx offset;
+-
+- /* Convert a subreg of a mem into the mem itself. */
+- if (GET_CODE (operands[nops + i]) == SUBREG)
+- operands[nops + i] = alter_subreg (operands + (nops + i));
+-
+- gcc_assert (GET_CODE (operands[nops + i]) == MEM);
+-
+- /* Don't reorder volatile memory references; it doesn't seem worth
+- looking for the case where the order is ok anyway. */
+- if (MEM_VOLATILE_P (operands[nops + i]))
+- return 0;
+-
+- offset = const0_rtx;
+-
+- if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
+- || (GET_CODE (reg) == SUBREG
+- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
+- || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
+- && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
+- == REG)
+- || (GET_CODE (reg) == SUBREG
+- && GET_CODE (reg = SUBREG_REG (reg)) == REG))
+- && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
+- == CONST_INT)))
+- {
+- if (i == 0)
+- {
+- base_reg = REGNO (reg);
+- unsorted_regs[0] = (GET_CODE (operands[i]) == REG
+- ? REGNO (operands[i])
+- : REGNO (SUBREG_REG (operands[i])));
+- order[0] = 0;
+- }
+- else
+- {
+- if (base_reg != (int) REGNO (reg))
+- /* Not addressed from the same base register. */
+- return 0;
+-
+- unsorted_regs[i] = (GET_CODE (operands[i]) == REG
+- ? REGNO (operands[i])
+- : REGNO (SUBREG_REG (operands[i])));
+- if (unsorted_regs[i] < unsorted_regs[order[0]])
+- order[0] = i;
+- }
+-
+- /* If it isn't an integer register, or if it overwrites the
+- base register but isn't the last insn in the list, then
+- we can't do this. */
+- if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
+- || (i != nops - 1 && unsorted_regs[i] == base_reg))
+- return 0;
+-
+- unsorted_offsets[i] = INTVAL (offset);
+- }
+- else
+- /* Not a suitable memory address. */
+- return 0;
+- }
+-
+- /* All the useful information has now been extracted from the
+- operands into unsorted_regs and unsorted_offsets; additionally,
+- order[0] has been set to the lowest numbered register in the
+- list. Sort the registers into order, and check that the memory
+- offsets are ascending and adjacent. */
+-
+- for (i = 1; i < nops; i++)
+- {
+- int j;
+-
+- order[i] = order[i - 1];
+- for (j = 0; j < nops; j++)
+- if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
+- && (order[i] == order[i - 1]
+- || unsorted_regs[j] < unsorted_regs[order[i]]))
+- order[i] = j;
+-
+- /* Have we found a suitable register? if not, one must be used more
+- than once. */
+- if (order[i] == order[i - 1])
+- return 0;
+-
+- /* Is the memory address adjacent and ascending? */
+- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
+- return 0;
+- }
+-
+- if (base)
+- {
+- *base = base_reg;
+-
+- for (i = 0; i < nops; i++)
+- regs[i] = unsorted_regs[order[i]];
+-
+- *load_offset = unsorted_offsets[order[0]];
+- }
+-
+- if (unsorted_offsets[order[0]] == 0)
+- return 1; /* ldmia */
+-
+- if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
+- return 2; /* ldmib */
+-
+- if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
+- return 3; /* ldmda */
+-
+- if (unsorted_offsets[order[nops - 1]] == -4)
+- return 4; /* ldmdb */
+-
+
+/* Return true iff it would be profitable to turn a sequence of NOPS loads
+ or stores (depending on IS_STORE) into a load-multiple or store-multiple
@@ -492,35 +601,14 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
+multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED,
+ int nops, HOST_WIDE_INT add_offset)
+ {
-+ /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
-+ if the offset isn't small enough. The reason 2 ldrs are faster
-+ is because these ARMs are able to do more than one cache access
-+ in a single cycle. The ARM9 and StrongARM have Harvard caches,
-+ whilst the ARM8 has a double bandwidth cache. This means that
-+ these cores can do both an instruction fetch and a data fetch in
-+ a single cycle, so the trick of calculating the address into a
-+ scratch register (one of the result regs) and then doing a load
-+ multiple actually becomes slower (and no smaller in code size).
-+ That is the transformation
-+
-+ ldr rd1, [rbase + offset]
-+ ldr rd2, [rbase + offset + 4]
-+
-+ to
-+
-+ add rd1, rbase, offset
-+ ldmia rd1, {rd1, rd2}
-+
-+ produces worse code -- '3 cycles + any stalls on rd2' instead of
-+ '2 cycles + any stalls on rd2'. On ARMs with only one cache
-+ access per cycle, the first sequence could never complete in less
-+ than 6 cycles, whereas the ldm sequence would only take 5 and
-+ would make better use of sequential accesses if not hitting the
-+ cache.
-+
-+ We cheat here and test 'arm_ld_sched' which we currently know to
-+ only be true for the ARM8, ARM9 and StrongARM. If this ever
-+ changes, then the test below needs to be reworked. */
+ /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
+ if the offset isn't small enough. The reason 2 ldrs are faster
+ is because these ARMs are able to do more than one cache access
+@@ -9845,91 +9725,239 @@
+ We cheat here and test 'arm_ld_sched' which we currently know to
+ only be true for the ARM8, ARM9 and StrongARM. If this ever
+ changes, then the test below needs to be reworked. */
+- if (nops == 2 && arm_ld_sched)
+ if (nops == 2 && arm_ld_sched && add_offset != 0)
+ return false;
+
@@ -541,12 +629,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
+static bool
+compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order,
+ int *unsorted_regs)
- {
-- int unsorted_regs[4];
-- HOST_WIDE_INT unsorted_offsets[4];
-- int order[4];
-- int base_reg = -1;
- int i;
++{
++ int i;
+ for (i = 1; i < nops; i++)
+ {
+ int j;
@@ -596,161 +680,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
+ rtx base_reg_rtx = NULL;
+ int base_reg = -1;
+ int i, ldm_case;
-
- if (low_irq_latency)
- return 0;
-
-- /* Can only handle 2, 3, or 4 insns at present,
-- though could be easily extended if required. */
-- gcc_assert (nops >= 2 && nops <= 4);
-+ /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
-+ easily extended if required. */
-+ gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
-
-- memset (order, 0, 4 * sizeof (int));
-+ memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
-
- /* Loop over the operands and check that the memory references are
- suitable (i.e. immediate offsets from the same base register). At
-@@ -9735,32 +9842,30 @@ load_multiple_sequence (rtx *operands, i
- if (i == 0)
- {
- base_reg = REGNO (reg);
-- unsorted_regs[0] = (GET_CODE (operands[i]) == REG
-- ? REGNO (operands[i])
-- : REGNO (SUBREG_REG (operands[i])));
-- order[0] = 0;
-- }
-- else
-- {
-- if (base_reg != (int) REGNO (reg))
-- /* Not addressed from the same base register. */
-+ base_reg_rtx = reg;
-+ if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
- return 0;
--
-- unsorted_regs[i] = (GET_CODE (operands[i]) == REG
-- ? REGNO (operands[i])
-- : REGNO (SUBREG_REG (operands[i])));
-- if (unsorted_regs[i] < unsorted_regs[order[0]])
-- order[0] = i;
- }
-+ else if (base_reg != (int) REGNO (reg))
-+ /* Not addressed from the same base register. */
-+ return 0;
+
-+ unsorted_regs[i] = (GET_CODE (operands[i]) == REG
-+ ? REGNO (operands[i])
-+ : REGNO (SUBREG_REG (operands[i])));
-
- /* If it isn't an integer register, or if it overwrites the
- base register but isn't the last insn in the list, then
- we can't do this. */
-- if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
-+ if (unsorted_regs[i] < 0
-+ || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
-+ || unsorted_regs[i] > 14
- || (i != nops - 1 && unsorted_regs[i] == base_reg))
- return 0;
-
- unsorted_offsets[i] = INTVAL (offset);
-+ if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
-+ order[0] = i;
- }
- else
- /* Not a suitable memory address. */
-@@ -9769,167 +9874,90 @@ load_multiple_sequence (rtx *operands, i
-
- /* All the useful information has now been extracted from the
- operands into unsorted_regs and unsorted_offsets; additionally,
-- order[0] has been set to the lowest numbered register in the
-- list. Sort the registers into order, and check that the memory
-- offsets are ascending and adjacent. */
--
-- for (i = 1; i < nops; i++)
-- {
-- int j;
--
-- order[i] = order[i - 1];
-- for (j = 0; j < nops; j++)
-- if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
-- && (order[i] == order[i - 1]
-- || unsorted_regs[j] < unsorted_regs[order[i]]))
-- order[i] = j;
--
-- /* Have we found a suitable register? if not, one must be used more
-- than once. */
-- if (order[i] == order[i - 1])
-- return 0;
-+ order[0] has been set to the lowest offset in the list. Sort
-+ the offsets into order, verifying that they are adjacent, and
-+ check that the register numbers are ascending. */
-+ if (!compute_offset_order (nops, unsorted_offsets, order,
-+ check_regs ? unsorted_regs : NULL))
-+ return 0;
-
-- /* Is the memory address adjacent and ascending? */
-- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
-- return 0;
-- }
-+ if (saved_order)
-+ memcpy (saved_order, order, sizeof order);
-
- if (base)
- {
- *base = base_reg;
-
- for (i = 0; i < nops; i++)
-- regs[i] = unsorted_regs[order[i]];
-+ regs[i] = unsorted_regs[check_regs ? order[i] : i];
-
- *load_offset = unsorted_offsets[order[0]];
- }
-
-- if (unsorted_offsets[order[0]] == 0)
-- return 1; /* ldmia */
--
-- if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
-- return 2; /* ldmib */
--
-- if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
-- return 3; /* ldmda */
--
-- if (unsorted_offsets[order[nops - 1]] == -4)
-- return 4; /* ldmdb */
--
-- /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
-- if the offset isn't small enough. The reason 2 ldrs are faster
-- is because these ARMs are able to do more than one cache access
-- in a single cycle. The ARM9 and StrongARM have Harvard caches,
-- whilst the ARM8 has a double bandwidth cache. This means that
-- these cores can do both an instruction fetch and a data fetch in
-- a single cycle, so the trick of calculating the address into a
-- scratch register (one of the result regs) and then doing a load
-- multiple actually becomes slower (and no smaller in code size).
-- That is the transformation
--
-- ldr rd1, [rbase + offset]
-- ldr rd2, [rbase + offset + 4]
--
-- to
--
-- add rd1, rbase, offset
-- ldmia rd1, {rd1, rd2}
--
-- produces worse code -- '3 cycles + any stalls on rd2' instead of
-- '2 cycles + any stalls on rd2'. On ARMs with only one cache
-- access per cycle, the first sequence could never complete in less
-- than 6 cycles, whereas the ldm sequence would only take 5 and
-- would make better use of sequential accesses if not hitting the
-- cache.
--
-- We cheat here and test 'arm_ld_sched' which we currently know to
-- only be true for the ARM8, ARM9 and StrongARM. If this ever
-- changes, then the test below needs to be reworked. */
-- if (nops == 2 && arm_ld_sched)
-+ if (TARGET_THUMB1
-+ && !peep2_reg_dead_p (nops, base_reg_rtx))
++ if (low_irq_latency)
return 0;
- /* Can't do it without setting up the offset, only do this if it takes
@@ -769,7 +700,18 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
- int i;
-
- switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
-- {
++ /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
++ easily extended if required. */
++ gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
++
++ memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
++
++ /* Loop over the operands and check that the memory references are
++ suitable (i.e. immediate offsets from the same base register). At
++ the same time, extract the target register, and the memory
++ offsets. */
++ for (i = 0; i < nops; i++)
+ {
- case 1:
- strcpy (buf, "ldm%(ia%)\t");
- break;
@@ -791,7 +733,62 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
- sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
- reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
- (long) offset);
-- else
++ rtx reg;
++ rtx offset;
++
++ /* Convert a subreg of a mem into the mem itself. */
++ if (GET_CODE (operands[nops + i]) == SUBREG)
++ operands[nops + i] = alter_subreg (operands + (nops + i));
++
++ gcc_assert (GET_CODE (operands[nops + i]) == MEM);
++
++ /* Don't reorder volatile memory references; it doesn't seem worth
++ looking for the case where the order is ok anyway. */
++ if (MEM_VOLATILE_P (operands[nops + i]))
++ return 0;
++
++ offset = const0_rtx;
++
++ if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
++ || (GET_CODE (reg) == SUBREG
++ && GET_CODE (reg = SUBREG_REG (reg)) == REG))
++ || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
++ && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
++ == REG)
++ || (GET_CODE (reg) == SUBREG
++ && GET_CODE (reg = SUBREG_REG (reg)) == REG))
++ && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
++ == CONST_INT)))
++ {
++ if (i == 0)
++ {
++ base_reg = REGNO (reg);
++ base_reg_rtx = reg;
++ if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
++ return 0;
++ }
++ else if (base_reg != (int) REGNO (reg))
++ /* Not addressed from the same base register. */
++ return 0;
++
++ unsorted_regs[i] = (GET_CODE (operands[i]) == REG
++ ? REGNO (operands[i])
++ : REGNO (SUBREG_REG (operands[i])));
++
++ /* If it isn't an integer register, or if it overwrites the
++ base register but isn't the last insn in the list, then
++ we can't do this. */
++ if (unsorted_regs[i] < 0
++ || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
++ || unsorted_regs[i] > 14
++ || (i != nops - 1 && unsorted_regs[i] == base_reg))
++ return 0;
++
++ unsorted_offsets[i] = INTVAL (offset);
++ if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
++ order[0] = i;
++ }
+ else
- sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
- reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
- (long) -offset);
@@ -810,6 +807,41 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
- for (i = 1; i < nops; i++)
- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
- reg_names[regs[i]]);
+-
+- strcat (buf, "}\t%@ phole ldm");
+-
+- output_asm_insn (buf, operands);
+- return "";
++ /* Not a suitable memory address. */
++ return 0;
++ }
++
++ /* All the useful information has now been extracted from the
++ operands into unsorted_regs and unsorted_offsets; additionally,
++ order[0] has been set to the lowest offset in the list. Sort
++ the offsets into order, verifying that they are adjacent, and
++ check that the register numbers are ascending. */
++ if (!compute_offset_order (nops, unsorted_offsets, order,
++ check_regs ? unsorted_regs : NULL))
++ return 0;
++
++ if (saved_order)
++ memcpy (saved_order, order, sizeof order);
++
++ if (base)
++ {
++ *base = base_reg;
++
++ for (i = 0; i < nops; i++)
++ regs[i] = unsorted_regs[check_regs ? order[i] : i];
++
++ *load_offset = unsorted_offsets[order[0]];
++ }
++
++ if (TARGET_THUMB1
++ && !peep2_reg_dead_p (nops, base_reg_rtx))
++ return 0;
++
+ if (unsorted_offsets[order[0]] == 0)
+ ldm_case = 1; /* ldmia */
+ else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
@@ -823,25 +855,18 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
+ ldm_case = 5;
+ else
+ return 0;
-
-- strcat (buf, "}\t%@ phole ldm");
++
+ if (!multiple_operation_profitable_p (false, nops,
+ ldm_case == 5
+ ? unsorted_offsets[order[0]] : 0))
+ return 0;
-
-- output_asm_insn (buf, operands);
-- return "";
++
+ return ldm_case;
}
-int
-store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
- HOST_WIDE_INT * load_offset)
--{
-- int unsorted_regs[4];
-- HOST_WIDE_INT unsorted_offsets[4];
-- int order[4];
+/* Used to determine in a peephole whether a sequence of store instructions can
+ be changed into a store-multiple instruction.
+ NOPS is the number of separate store instructions we are examining.
@@ -863,7 +888,10 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
+store_multiple_sequence (rtx *operands, int nops, int nops_total,
+ int *regs, rtx *reg_rtxs, int *saved_order, int *base,
+ HOST_WIDE_INT *load_offset, bool check_regs)
-+{
+ {
+- int unsorted_regs[4];
+- HOST_WIDE_INT unsorted_offsets[4];
+- int order[4];
+ int unsorted_regs[MAX_LDM_STM_OPS];
+ rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS];
+ HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
@@ -888,7 +916,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* Loop over the operands and check that the memory references are
suitable (i.e. immediate offsets from the same base register). At
-@@ -9964,32 +9992,32 @@ store_multiple_sequence (rtx *operands,
+@@ -9964,32 +9992,32 @@
&& (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
== CONST_INT)))
{
@@ -937,7 +965,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
}
else
/* Not a suitable memory address. */
-@@ -9998,111 +10026,65 @@ store_multiple_sequence (rtx *operands,
+@@ -9998,111 +10026,65 @@
/* All the useful information has now been extracted from the
operands into unsorted_regs and unsorted_offsets; additionally,
@@ -960,17 +988,18 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
- than once. */
- if (order[i] == order[i - 1])
- return 0;
+-
+- /* Is the memory address adjacent and ascending? */
+- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
+- return 0;
+- }
+ order[0] has been set to the lowest offset in the list. Sort
+ the offsets into order, verifying that they are adjacent, and
+ check that the register numbers are ascending. */
+ if (!compute_offset_order (nops, unsorted_offsets, order,
+ check_regs ? unsorted_regs : NULL))
+ return 0;
-
-- /* Is the memory address adjacent and ascending? */
-- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
-- return 0;
-- }
++
+ if (saved_order)
+ memcpy (saved_order, order, sizeof order);
@@ -989,7 +1018,11 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
*load_offset = unsorted_offsets[order[0]];
}
-- if (unsorted_offsets[order[0]] == 0)
++ if (TARGET_THUMB1
++ && !peep2_reg_dead_p (nops_total, base_reg_rtx))
++ return 0;
++
+ if (unsorted_offsets[order[0]] == 0)
- return 1; /* stmia */
-
- if (unsorted_offsets[order[0]] == 4)
@@ -1037,14 +1070,15 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
-
- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
- reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
-+ if (TARGET_THUMB1
-+ && !peep2_reg_dead_p (nops_total, base_reg_rtx))
-+ return 0;
-
+-
- for (i = 1; i < nops; i++)
- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
- reg_names[regs[i]]);
-+ if (unsorted_offsets[order[0]] == 0)
+-
+- strcat (buf, "}\t%@ phole stm");
+-
+- output_asm_insn (buf, operands);
+- return "";
+ stm_case = 1; /* stmia */
+ else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
+ stm_case = 2; /* stmib */
@@ -1054,13 +1088,10 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
+ stm_case = 4; /* stmdb */
+ else
+ return 0;
-
-- strcat (buf, "}\t%@ phole stm");
++
+ if (!multiple_operation_profitable_p (false, nops, 0))
+ return 0;
-
-- output_asm_insn (buf, operands);
-- return "";
++
+ return stm_case;
}
@@ -1087,7 +1118,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* XScale has load-store double instructions, but they have stricter
alignment requirements than load-store multiple, so we cannot
-@@ -10139,18 +10121,10 @@ arm_gen_load_multiple (int base_regno, i
+@@ -10139,18 +10121,10 @@
start_sequence ();
for (i = 0; i < count; i++)
@@ -1109,7 +1140,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
seq = get_insns ();
end_sequence ();
-@@ -10159,41 +10133,40 @@ arm_gen_load_multiple (int base_regno, i
+@@ -10159,41 +10133,40 @@
}
result = gen_rtx_PARALLEL (VOIDmode,
@@ -1161,8 +1192,9 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
rtx result;
- int sign = up ? 1 : -1;
- rtx mem, addr;
-
+-
- /* See arm_gen_load_multiple for discussion of
++
+ if (GET_CODE (basereg) == PLUS)
+ basereg = XEXP (basereg, 0);
+
@@ -1170,7 +1202,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
the pros/cons of ldm/stm usage for XScale. */
if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
{
-@@ -10202,18 +10175,10 @@ arm_gen_store_multiple (int base_regno,
+@@ -10202,18 +10175,10 @@
start_sequence ();
for (i = 0; i < count; i++)
@@ -1192,7 +1224,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
seq = get_insns ();
end_sequence ();
-@@ -10222,29 +10187,319 @@ arm_gen_store_multiple (int base_regno,
+@@ -10222,29 +10187,319 @@
}
result = gen_rtx_PARALLEL (VOIDmode,
@@ -1522,7 +1554,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
}
int
-@@ -10280,20 +10535,21 @@ arm_gen_movmemqi (rtx *operands)
+@@ -10280,20 +10535,21 @@
for (i = 0; in_words_to_go >= 2; i+=4)
{
if (in_words_to_go > 4)
@@ -1552,11 +1584,11 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
(last_bytes == 0
? FALSE : TRUE),
dstbase, &dstoffset));
-Index: gcc-4_5-branch/gcc/config/arm/arm.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.h
-+++ gcc-4_5-branch/gcc/config/arm/arm.h
-@@ -1143,6 +1143,9 @@ extern int arm_structure_size_boundary;
+
+=== modified file 'gcc/config/arm/arm.h'
+--- old/gcc/config/arm/arm.h 2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm.h 2011-01-05 18:20:37 +0000
+@@ -1143,6 +1143,9 @@
((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
|| (MODE) == CImode || (MODE) == XImode)
@@ -1566,7 +1598,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.h
/* The order in which register should be allocated. It is good to use ip
since no saving is required (though calls clobber it) and it never contains
function parameters. It is quite good to use lr since other calls may
-@@ -2823,4 +2826,8 @@ enum arm_builtins
+@@ -2823,4 +2826,8 @@
#define NEED_INDICATE_EXEC_STACK 0
#endif
@@ -1575,10 +1607,10 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.h
+#define MAX_LDM_STM_OPS 4
+
#endif /* ! GCC_ARM_H */
-Index: gcc-4_5-branch/gcc/config/arm/arm.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.md
-+++ gcc-4_5-branch/gcc/config/arm/arm.md
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md 2011-01-05 12:12:18 +0000
++++ new/gcc/config/arm/arm.md 2011-01-05 18:20:37 +0000
@@ -6282,7 +6282,7 @@
;; load- and store-multiple insns
@@ -1957,7 +1989,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
-@@ -11554,6 +11246,8 @@
+@@ -11559,6 +11251,8 @@
"
)
@@ -1966,10 +1998,10 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
;; Load the FPA co-processor patterns
(include "fpa.md")
;; Load the Maverick co-processor patterns
-Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
-===================================================================
---- /dev/null
-+++ gcc-4_5-branch/gcc/config/arm/ldmstm.md
+
+=== added file 'gcc/config/arm/ldmstm.md'
+--- old/gcc/config/arm/ldmstm.md 1970-01-01 00:00:00 +0000
++++ new/gcc/config/arm/ldmstm.md 2010-11-16 13:08:47 +0000
@@ -0,0 +1,1191 @@
+/* ARM ldm/stm instruction patterns. This file was automatically generated
+ using arm-ldmstm.ml. Please do not edit manually.
@@ -3162,10 +3194,10 @@ Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
+ FAIL;
+})
+
-Index: gcc-4_5-branch/gcc/config/arm/predicates.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/predicates.md
-+++ gcc-4_5-branch/gcc/config/arm/predicates.md
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md 2010-11-04 10:45:05 +0000
++++ new/gcc/config/arm/predicates.md 2010-11-16 12:32:34 +0000
@@ -211,6 +211,11 @@
(and (match_code "ior,xor,and")
(match_test "mode == GET_MODE (op)")))
@@ -3312,24 +3344,16 @@ Index: gcc-4_5-branch/gcc/config/arm/predicates.md
}
return true;
-Index: gcc-4_5-branch/gcc/config/i386/i386.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/i386/i386.md
-+++ gcc-4_5-branch/gcc/config/i386/i386.md
-@@ -4934,6 +4934,7 @@
- (set (match_operand:SSEMODEI24 2 "register_operand" "")
- (fix:SSEMODEI24 (match_dup 0)))]
- "TARGET_SHORTEN_X87_SSE
-+ && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
- && peep2_reg_dead_p (2, operands[0])"
- [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
- "")
-@@ -20036,15 +20037,14 @@
+
+=== modified file 'gcc/config/i386/i386.md'
+--- old/gcc/config/i386/i386.md 2011-01-05 12:12:18 +0000
++++ new/gcc/config/i386/i386.md 2011-01-05 18:20:37 +0000
+@@ -20023,15 +20023,14 @@
;; leal (%edx,%eax,4), %eax
(define_peephole2
- [(parallel [(set (match_operand 0 "register_operand" "")
-+ [(match_scratch:P 5 "r")
++ [(match_scratch:SI 5 "r")
+ (parallel [(set (match_operand 0 "register_operand" "")
(ashift (match_operand 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")))
@@ -3345,12 +3369,9 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
(clobber (reg:CC FLAGS_REG))])]
"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
/* Validate MODE for lea. */
-@@ -20053,31 +20053,27 @@
- || GET_MODE (operands[0]) == HImode))
+@@ -20041,30 +20040,21 @@
|| GET_MODE (operands[0]) == SImode
|| (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
-+ && (rtx_equal_p (operands[0], operands[3])
-+ || peep2_reg_dead_p (2, operands[0]))
/* We reorder load and the shift. */
- && !rtx_equal_p (operands[1], operands[3])
- && !reg_overlap_mentioned_p (operands[0], operands[4])
@@ -3379,21 +3400,17 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
operands[1] = gen_rtx_PLUS (Pmode, base,
gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
-+ operands[5] = base;
if (mode != Pmode)
-- operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
-+ {
-+ operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
-+ operands[5] = gen_rtx_SUBREG (mode, operands[5], 0);
-+ }
+ operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
++ operands[5] = base;
operands[0] = dest;
})
-Index: gcc-4_5-branch/gcc/df-problems.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/df-problems.c
-+++ gcc-4_5-branch/gcc/df-problems.c
-@@ -3748,9 +3748,22 @@ df_simulate_find_defs (rtx insn, bitmap
+
+=== modified file 'gcc/df-problems.c'
+--- old/gcc/df-problems.c 2010-11-16 22:17:17 +0000
++++ new/gcc/df-problems.c 2010-12-02 13:42:47 +0000
+@@ -3748,9 +3748,22 @@
for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
{
df_ref def = *def_rec;
@@ -3419,7 +3436,7 @@ Index: gcc-4_5-branch/gcc/df-problems.c
bitmap_set_bit (defs, DF_REF_REGNO (def));
}
}
-@@ -3921,7 +3934,7 @@ df_simulate_initialize_forwards (basic_b
+@@ -3921,7 +3934,7 @@
{
df_ref def = *def_rec;
if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)
@@ -3428,7 +3445,7 @@ Index: gcc-4_5-branch/gcc/df-problems.c
}
}
-@@ -3942,7 +3955,7 @@ df_simulate_one_insn_forwards (basic_blo
+@@ -3942,7 +3955,7 @@
while here the scan is performed forwards! So, first assume that the
def is live, and if this is not true REG_UNUSED notes will rectify the
situation. */
@@ -3437,11 +3454,11 @@ Index: gcc-4_5-branch/gcc/df-problems.c
/* Clear all of the registers that go dead. */
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
-Index: gcc-4_5-branch/gcc/df.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/df.h
-+++ gcc-4_5-branch/gcc/df.h
-@@ -978,6 +978,7 @@ extern void df_note_add_problem (void);
+
+=== modified file 'gcc/df.h'
+--- old/gcc/df.h 2010-01-29 12:14:47 +0000
++++ new/gcc/df.h 2010-12-02 13:42:47 +0000
+@@ -978,6 +978,7 @@
extern void df_md_add_problem (void);
extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap);
extern void df_md_simulate_one_insn (basic_block, rtx, bitmap);
@@ -3449,11 +3466,11 @@ Index: gcc-4_5-branch/gcc/df.h
extern void df_simulate_find_defs (rtx, bitmap);
extern void df_simulate_defs (rtx, bitmap);
extern void df_simulate_uses (rtx, bitmap);
-Index: gcc-4_5-branch/gcc/fwprop.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/fwprop.c
-+++ gcc-4_5-branch/gcc/fwprop.c
-@@ -228,7 +228,10 @@ single_def_use_enter_block (struct dom_w
+
+=== modified file 'gcc/fwprop.c'
+--- old/gcc/fwprop.c 2010-04-02 18:54:46 +0000
++++ new/gcc/fwprop.c 2010-11-16 12:32:34 +0000
+@@ -228,7 +228,10 @@
process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP);
process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP);
@@ -3465,11 +3482,11 @@ Index: gcc-4_5-branch/gcc/fwprop.c
FOR_BB_INSNS (bb, insn)
if (INSN_P (insn))
-Index: gcc-4_5-branch/gcc/genoutput.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/genoutput.c
-+++ gcc-4_5-branch/gcc/genoutput.c
-@@ -266,6 +266,8 @@ output_operand_data (void)
+
+=== modified file 'gcc/genoutput.c'
+--- old/gcc/genoutput.c 2009-04-08 14:00:34 +0000
++++ new/gcc/genoutput.c 2010-11-16 12:32:34 +0000
+@@ -266,6 +266,8 @@
printf (" %d,\n", d->strict_low);
@@ -3478,11 +3495,11 @@ Index: gcc-4_5-branch/gcc/genoutput.c
printf (" %d\n", d->eliminable);
printf(" },\n");
-Index: gcc-4_5-branch/gcc/genrecog.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/genrecog.c
-+++ gcc-4_5-branch/gcc/genrecog.c
-@@ -1782,20 +1782,11 @@ change_state (const char *oldpos, const
+
+=== modified file 'gcc/genrecog.c'
+--- old/gcc/genrecog.c 2009-06-22 09:29:13 +0000
++++ new/gcc/genrecog.c 2010-11-16 12:32:34 +0000
+@@ -1782,20 +1782,11 @@
int odepth = strlen (oldpos);
int ndepth = strlen (newpos);
int depth;
@@ -3503,11 +3520,11 @@ Index: gcc-4_5-branch/gcc/genrecog.c
/* Go down to desired level. */
while (depth < ndepth)
{
-Index: gcc-4_5-branch/gcc/ifcvt.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/ifcvt.c
-+++ gcc-4_5-branch/gcc/ifcvt.c
-@@ -4011,6 +4011,7 @@ dead_or_predicable (basic_block test_bb,
+
+=== modified file 'gcc/ifcvt.c'
+--- old/gcc/ifcvt.c 2011-01-05 12:12:18 +0000
++++ new/gcc/ifcvt.c 2011-01-05 18:20:37 +0000
+@@ -4011,6 +4011,7 @@
basic_block new_dest = dest_edge->dest;
rtx head, end, jump, earliest = NULL_RTX, old_dest;
bitmap merge_set = NULL;
@@ -3515,7 +3532,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
/* Number of pending changes. */
int n_validated_changes = 0;
rtx new_dest_label;
-@@ -4169,6 +4170,7 @@ dead_or_predicable (basic_block test_bb,
+@@ -4169,6 +4170,7 @@
end of the block. */
merge_set = BITMAP_ALLOC (&reg_obstack);
@@ -3523,7 +3540,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
/* If we allocated new pseudos (e.g. in the conditional move
expander called from noce_emit_cmove), we must resize the
-@@ -4187,6 +4189,7 @@ dead_or_predicable (basic_block test_bb,
+@@ -4187,6 +4189,7 @@
df_ref def = *def_rec;
bitmap_set_bit (merge_set, DF_REF_REGNO (def));
}
@@ -3531,7 +3548,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
}
}
-@@ -4197,7 +4200,7 @@ dead_or_predicable (basic_block test_bb,
+@@ -4197,7 +4200,7 @@
unsigned i;
bitmap_iterator bi;
@@ -3540,7 +3557,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
{
if (i < FIRST_PSEUDO_REGISTER
&& ! fixed_regs[i]
-@@ -4233,7 +4236,7 @@ dead_or_predicable (basic_block test_bb,
+@@ -4233,7 +4236,7 @@
TEST_SET & DF_LIVE_IN (merge_bb)
are empty. */
@@ -3549,7 +3566,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
|| bitmap_intersect_p (merge_set, test_live)
|| bitmap_intersect_p (test_set, df_get_live_in (merge_bb)))
intersect = true;
-@@ -4320,6 +4323,7 @@ dead_or_predicable (basic_block test_bb,
+@@ -4320,6 +4323,7 @@
remove_reg_equal_equiv_notes_for_regno (i);
BITMAP_FREE (merge_set);
@@ -3557,7 +3574,7 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
}
reorder_insns (head, end, PREV_INSN (earliest));
-@@ -4340,7 +4344,10 @@ dead_or_predicable (basic_block test_bb,
+@@ -4340,7 +4344,10 @@
cancel_changes (0);
fail:
if (merge_set)
@@ -3569,11 +3586,11 @@ Index: gcc-4_5-branch/gcc/ifcvt.c
return FALSE;
}
-Index: gcc-4_5-branch/gcc/recog.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/recog.c
-+++ gcc-4_5-branch/gcc/recog.c
-@@ -2082,6 +2082,7 @@ extract_insn (rtx insn)
+
+=== modified file 'gcc/recog.c'
+--- old/gcc/recog.c 2010-08-05 15:28:47 +0000
++++ new/gcc/recog.c 2010-11-16 12:32:34 +0000
+@@ -2082,6 +2082,7 @@
recog_data.operand_loc,
recog_data.constraints,
recog_data.operand_mode, NULL);
@@ -3581,7 +3598,7 @@ Index: gcc-4_5-branch/gcc/recog.c
if (noperands > 0)
{
const char *p = recog_data.constraints[0];
-@@ -2111,6 +2112,7 @@ extract_insn (rtx insn)
+@@ -2111,6 +2112,7 @@
for (i = 0; i < noperands; i++)
{
recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
@@ -3589,7 +3606,7 @@ Index: gcc-4_5-branch/gcc/recog.c
recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
/* VOIDmode match_operands gets mode from their real operand. */
if (recog_data.operand_mode[i] == VOIDmode)
-@@ -2909,6 +2911,10 @@ struct peep2_insn_data
+@@ -2909,6 +2911,10 @@
static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
static int peep2_current;
@@ -3600,7 +3617,7 @@ Index: gcc-4_5-branch/gcc/recog.c
/* The number of instructions available to match a peep2. */
int peep2_current_count;
-@@ -2917,6 +2923,16 @@ int peep2_current_count;
+@@ -2917,6 +2923,16 @@
DF_LIVE_OUT for the block. */
#define PEEP2_EOB pc_rtx
@@ -3617,7 +3634,7 @@ Index: gcc-4_5-branch/gcc/recog.c
/* Return the Nth non-note insn after `current', or return NULL_RTX if it
does not exist. Used by the recognizer to find the next insn to match
in a multi-insn pattern. */
-@@ -2926,9 +2942,7 @@ peep2_next_insn (int n)
+@@ -2926,9 +2942,7 @@
{
gcc_assert (n <= peep2_current_count);
@@ -3628,7 +3645,7 @@ Index: gcc-4_5-branch/gcc/recog.c
return peep2_insn_data[n].insn;
}
-@@ -2941,9 +2955,7 @@ peep2_regno_dead_p (int ofs, int regno)
+@@ -2941,9 +2955,7 @@
{
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
@@ -3639,7 +3656,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
-@@ -2959,9 +2971,7 @@ peep2_reg_dead_p (int ofs, rtx reg)
+@@ -2959,9 +2971,7 @@
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
@@ -3650,7 +3667,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
-@@ -2996,12 +3006,8 @@ peep2_find_free_register (int from, int
+@@ -2996,12 +3006,8 @@
gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
@@ -3665,7 +3682,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
-@@ -3010,8 +3016,7 @@ peep2_find_free_register (int from, int
+@@ -3010,8 +3016,7 @@
{
HARD_REG_SET this_live;
@@ -3675,7 +3692,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
IOR_HARD_REG_SET (live, this_live);
-@@ -3104,19 +3109,234 @@ peep2_reinit_state (regset live)
+@@ -3104,19 +3109,234 @@
COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
}
@@ -3913,7 +3930,7 @@ Index: gcc-4_5-branch/gcc/recog.c
df_analyze ();
/* Initialize the regsets we're going to use. */
-@@ -3126,214 +3346,59 @@ peephole2_optimize (void)
+@@ -3126,214 +3346,59 @@
FOR_EACH_BB_REVERSE (bb)
{
@@ -3935,7 +3952,11 @@ Index: gcc-4_5-branch/gcc/recog.c
{
- prev = PREV_INSN (insn);
- if (NONDEBUG_INSN_P (insn))
-- {
++ rtx attempt, head;
++ int match_len;
++
++ if (!past_end && !NONDEBUG_INSN_P (insn))
+ {
- rtx attempt, before_try, x;
- int match_len;
- rtx note;
@@ -3972,9 +3993,7 @@ Index: gcc-4_5-branch/gcc/recog.c
- {
- int j;
- rtx old_insn, new_insn, note;
-+ rtx attempt, head;
-+ int match_len;
-
+-
- j = i + peep2_current;
- if (j >= MAX_INSNS_PER_PEEP2 + 1)
- j -= MAX_INSNS_PER_PEEP2 + 1;
@@ -4081,17 +4100,7 @@ Index: gcc-4_5-branch/gcc/recog.c
- possible. Zap dummy outgoing edges. */
- do_cleanup_cfg |= purge_dead_edges (bb);
- }
-+ if (!past_end && !NONDEBUG_INSN_P (insn))
-+ {
-+ next_insn:
-+ insn = NEXT_INSN (insn);
-+ if (insn == NEXT_INSN (BB_END (bb)))
-+ past_end = true;
-+ continue;
-+ }
-+ if (!past_end && peep2_fill_buffer (bb, insn, live))
-+ goto next_insn;
-
+-
- if (targetm.have_conditional_execution ())
- {
- for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
@@ -4127,15 +4136,10 @@ Index: gcc-4_5-branch/gcc/recog.c
- x = PREV_INSN (x);
- }
- while (x != prev);
-+ /* If we did not fill an empty buffer, it signals the end of the
-+ block. */
-+ if (peep2_current_count == 0)
-+ break;
-
+-
- peep2_current = i;
- }
-+ /* The buffer filled to the current maximum, so try to match. */
-
+-
- /* If we generated a jump instruction, it won't have
- JUMP_LABEL set. Recompute after we're done. */
- for (x = attempt; x != before_try; x = PREV_INSN (x))
@@ -4145,6 +4149,23 @@ Index: gcc-4_5-branch/gcc/recog.c
- break;
- }
- }
++ next_insn:
++ insn = NEXT_INSN (insn);
++ if (insn == NEXT_INSN (BB_END (bb)))
++ past_end = true;
++ continue;
+ }
++ if (!past_end && peep2_fill_buffer (bb, insn, live))
++ goto next_insn;
+
+- if (insn == BB_HEAD (bb))
++ /* If we did not fill an empty buffer, it signals the end of the
++ block. */
++ if (peep2_current_count == 0)
+ break;
++
++ /* The buffer filled to the current maximum, so try to match. */
++
+ pos = peep2_buf_position (peep2_current + peep2_current_count);
+ peep2_insn_data[pos].insn = PEEP2_EOB;
+ COPY_REG_SET (peep2_insn_data[pos].live_before, live);
@@ -4163,14 +4184,11 @@ Index: gcc-4_5-branch/gcc/recog.c
+ /* If no match, advance the buffer by one insn. */
+ peep2_current = peep2_buf_position (peep2_current + 1);
+ peep2_current_count--;
- }
--
-- if (insn == BB_HEAD (bb))
-- break;
++ }
}
}
-@@ -3341,7 +3406,7 @@ peephole2_optimize (void)
+@@ -3341,7 +3406,7 @@
for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
BITMAP_FREE (peep2_insn_data[i].live_before);
BITMAP_FREE (live);
@@ -4179,11 +4197,11 @@ Index: gcc-4_5-branch/gcc/recog.c
rebuild_jump_labels (get_insns ());
}
#endif /* HAVE_peephole2 */
-Index: gcc-4_5-branch/gcc/recog.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/recog.h
-+++ gcc-4_5-branch/gcc/recog.h
-@@ -194,6 +194,9 @@ struct recog_data
+
+=== modified file 'gcc/recog.h'
+--- old/gcc/recog.h 2009-10-26 21:55:59 +0000
++++ new/gcc/recog.h 2010-11-16 12:32:34 +0000
+@@ -194,6 +194,9 @@
/* Gives the constraint string for operand N. */
const char *constraints[MAX_RECOG_OPERANDS];
@@ -4193,7 +4211,7 @@ Index: gcc-4_5-branch/gcc/recog.h
/* Gives the mode of operand N. */
enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
-@@ -260,6 +263,8 @@ struct insn_operand_data
+@@ -260,6 +263,8 @@
const char strict_low;
@@ -4202,11 +4220,11 @@ Index: gcc-4_5-branch/gcc/recog.h
const char eliminable;
};
-Index: gcc-4_5-branch/gcc/reload.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/reload.c
-+++ gcc-4_5-branch/gcc/reload.c
-@@ -3631,7 +3631,7 @@ find_reloads (rtx insn, int replace, int
+
+=== modified file 'gcc/reload.c'
+--- old/gcc/reload.c 2009-12-21 16:32:44 +0000
++++ new/gcc/reload.c 2010-11-16 12:32:34 +0000
+@@ -3631,7 +3631,7 @@
|| modified[j] != RELOAD_WRITE)
&& j != i
/* Ignore things like match_operator operands. */
@@ -4215,3 +4233,4 @@ Index: gcc-4_5-branch/gcc/reload.c
/* Don't count an input operand that is constrained to match
the early clobber operand. */
&& ! (this_alternative_matches[j] == i
+
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch
deleted file mode 100644
index e8c8e63883..0000000000
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch
+++ /dev/null
@@ -1,157 +0,0 @@
- LP: #681138
- Backport from mainline:
-
- gcc/
- * config/arm/sync.md (sync_clobber, sync_t2_reqd): New code attribute.
- (arm_sync_old_<sync_optab>si, arm_sync_old_<sync_optab><mode>): Use
- the sync_clobber and sync_t2_reqd code attributes.
- * config/arm/arm.c (arm_output_sync_loop): Reverse the operation if
- the t2 argument is NULL.
-
-=== modified file 'gcc/config/arm/arm.c'
-Index: gcc-4_5-branch/gcc/config/arm/arm.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/arm.c
-+++ gcc-4_5-branch/gcc/config/arm/arm.c
-@@ -23098,10 +23098,46 @@ arm_output_sync_loop (emit_f emit,
- break;
- }
-
-- arm_output_strex (emit, mode, "", t2, t1, memory);
-- operands[0] = t2;
-- arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
-- arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX);
-+ if (t2)
-+ {
-+ arm_output_strex (emit, mode, "", t2, t1, memory);
-+ operands[0] = t2;
-+ arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
-+ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
-+ LOCAL_LABEL_PREFIX);
-+ }
-+ else
-+ {
-+ /* Use old_value for the return value because for some operations
-+ the old_value can easily be restored. This saves one register. */
-+ arm_output_strex (emit, mode, "", old_value, t1, memory);
-+ operands[0] = old_value;
-+ arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
-+ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
-+ LOCAL_LABEL_PREFIX);
-+
-+ switch (sync_op)
-+ {
-+ case SYNC_OP_ADD:
-+ arm_output_op3 (emit, "sub", old_value, t1, new_value);
-+ break;
-+
-+ case SYNC_OP_SUB:
-+ arm_output_op3 (emit, "add", old_value, t1, new_value);
-+ break;
-+
-+ case SYNC_OP_XOR:
-+ arm_output_op3 (emit, "eor", old_value, t1, new_value);
-+ break;
-+
-+ case SYNC_OP_NONE:
-+ arm_output_op2 (emit, "mov", old_value, required_value);
-+ break;
-+
-+ default:
-+ gcc_unreachable ();
-+ }
-+ }
-
- arm_process_output_memory_barrier (emit, NULL);
- arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
-Index: gcc-4_5-branch/gcc/config/arm/sync.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/sync.md
-+++ gcc-4_5-branch/gcc/config/arm/sync.md
-@@ -103,6 +103,18 @@
- (plus "add")
- (minus "sub")])
-
-+(define_code_attr sync_clobber [(ior "=&r")
-+ (and "=&r")
-+ (xor "X")
-+ (plus "X")
-+ (minus "X")])
-+
-+(define_code_attr sync_t2_reqd [(ior "4")
-+ (and "4")
-+ (xor "*")
-+ (plus "*")
-+ (minus "*")])
-+
- (define_expand "sync_<sync_optab>si"
- [(match_operand:SI 0 "memory_operand")
- (match_operand:SI 1 "s_register_operand")
-@@ -286,7 +298,6 @@
- VUNSPEC_SYNC_COMPARE_AND_SWAP))
- (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)]
- VUNSPEC_SYNC_COMPARE_AND_SWAP))
-- (clobber:SI (match_scratch:SI 4 "=&r"))
- (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
- VUNSPEC_SYNC_COMPARE_AND_SWAP))
- ]
-@@ -299,7 +310,6 @@
- (set_attr "sync_required_value" "2")
- (set_attr "sync_new_value" "3")
- (set_attr "sync_t1" "0")
-- (set_attr "sync_t2" "4")
- (set_attr "conds" "clob")
- (set_attr "predicable" "no")])
-
-@@ -313,7 +323,6 @@
- VUNSPEC_SYNC_COMPARE_AND_SWAP)))
- (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)]
- VUNSPEC_SYNC_COMPARE_AND_SWAP))
-- (clobber:SI (match_scratch:SI 4 "=&r"))
- (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
- VUNSPEC_SYNC_COMPARE_AND_SWAP))
- ]
-@@ -326,7 +335,6 @@
- (set_attr "sync_required_value" "2")
- (set_attr "sync_new_value" "3")
- (set_attr "sync_t1" "0")
-- (set_attr "sync_t2" "4")
- (set_attr "conds" "clob")
- (set_attr "predicable" "no")])
-
-@@ -487,7 +495,7 @@
- VUNSPEC_SYNC_OLD_OP))
- (clobber (reg:CC CC_REGNUM))
- (clobber (match_scratch:SI 3 "=&r"))
-- (clobber (match_scratch:SI 4 "=&r"))]
-+ (clobber (match_scratch:SI 4 "<sync_clobber>"))]
- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
- {
- return arm_output_sync_insn (insn, operands);
-@@ -496,7 +504,7 @@
- (set_attr "sync_memory" "1")
- (set_attr "sync_new_value" "2")
- (set_attr "sync_t1" "3")
-- (set_attr "sync_t2" "4")
-+ (set_attr "sync_t2" "<sync_t2_reqd>")
- (set_attr "sync_op" "<sync_optab>")
- (set_attr "conds" "clob")
- (set_attr "predicable" "no")])
-@@ -540,7 +548,7 @@
- VUNSPEC_SYNC_OLD_OP))
- (clobber (reg:CC CC_REGNUM))
- (clobber (match_scratch:SI 3 "=&r"))
-- (clobber (match_scratch:SI 4 "=&r"))]
-+ (clobber (match_scratch:SI 4 "<sync_clobber>"))]
- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
- {
- return arm_output_sync_insn (insn, operands);
-@@ -549,7 +557,7 @@
- (set_attr "sync_memory" "1")
- (set_attr "sync_new_value" "2")
- (set_attr "sync_t1" "3")
-- (set_attr "sync_t2" "4")
-+ (set_attr "sync_t2" "<sync_t2_reqd>")
- (set_attr "sync_op" "<sync_optab>")
- (set_attr "conds" "clob")
- (set_attr "predicable" "no")])
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch
deleted file mode 100644
index 32c2999a7c..0000000000
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-2011-01-18 Ulrich Weigand <uweigand@de.ibm.com>
-
- LP: #685352
- Backport from mainline:
-
- 2011-01-18 Jakub Jelinek <jakub@redhat.com>
-
- gcc/
- PR rtl-optimization/47299
- * expr.c (expand_expr_real_2) <case WIDEN_MULT_EXPR>: Don't use
- subtarget. Use normal multiplication if both operands are
- constants.
- * expmed.c (expand_widening_mult): Don't try to optimize constant
- multiplication if op0 has VOIDmode. Convert op1 constant to mode
- before using it.
-
- gcc/testsuite/
- PR rtl-optimization/47299
- * gcc.c-torture/execute/pr47299.c: New test.
-
-=== modified file 'gcc/expmed.c'
-Index: gcc-4_5-branch/gcc/expmed.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/expmed.c
-+++ gcc-4_5-branch/gcc/expmed.c
-@@ -3355,12 +3355,17 @@ expand_widening_mult (enum machine_mode
- int unsignedp, optab this_optab)
- {
- bool speed = optimize_insn_for_speed_p ();
-+ rtx cop1;
-
- if (CONST_INT_P (op1)
-- && (INTVAL (op1) >= 0
-+ && GET_MODE (op0) != VOIDmode
-+ && (cop1 = convert_modes (mode, GET_MODE (op0), op1,
-+ this_optab == umul_widen_optab))
-+ && CONST_INT_P (cop1)
-+ && (INTVAL (cop1) >= 0
- || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT))
- {
-- HOST_WIDE_INT coeff = INTVAL (op1);
-+ HOST_WIDE_INT coeff = INTVAL (cop1);
- int max_cost;
- enum mult_variant variant;
- struct algorithm algorithm;
-Index: gcc-4_5-branch/gcc/expr.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/expr.c
-+++ gcc-4_5-branch/gcc/expr.c
-@@ -7624,10 +7624,10 @@ expand_expr_real_2 (sepops ops, rtx targ
- if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
- {
- if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
-- expand_operands (treeop0, treeop1, subtarget, &op0, &op1,
-+ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
- EXPAND_NORMAL);
- else
-- expand_operands (treeop0, treeop1, subtarget, &op1, &op0,
-+ expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
- EXPAND_NORMAL);
- goto binop3;
- }
-@@ -7645,7 +7645,8 @@ expand_expr_real_2 (sepops ops, rtx targ
- optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
- this_optab = zextend_p ? umul_widen_optab : smul_widen_optab;
-
-- if (mode == GET_MODE_2XWIDER_MODE (innermode))
-+ if (mode == GET_MODE_2XWIDER_MODE (innermode)
-+ && TREE_CODE (treeop0) != INTEGER_CST)
- {
- if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
- {
-Index: gcc-4_5-branch/gcc/testsuite/gcc.c-torture/execute/pr47299.c
-===================================================================
---- /dev/null
-+++ gcc-4_5-branch/gcc/testsuite/gcc.c-torture/execute/pr47299.c
-@@ -0,0 +1,17 @@
-+/* PR rtl-optimization/47299 */
-+
-+extern void abort (void);
-+
-+__attribute__ ((noinline, noclone)) unsigned short
-+foo (unsigned char x)
-+{
-+ return x * 255;
-+}
-+
-+int
-+main ()
-+{
-+ if (foo (0x40) != 0x3fc0)
-+ abort ();
-+ return 0;
-+}
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch
deleted file mode 100644
index 580d4f4724..0000000000
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-2011-01-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-
- Backport from FSF mainline
-
- 2011-01-18 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-
- * config/arm/cortex-a9.md (cortex-a9-neon.md): Actually
- include.
- (cortex_a9_dp): Handle neon types correctly.
-
-=== modified file 'gcc/config/arm/cortex-a9.md'
-Index: gcc-4_5-branch/gcc/config/arm/cortex-a9.md
-===================================================================
---- gcc-4_5-branch.orig/gcc/config/arm/cortex-a9.md
-+++ gcc-4_5-branch/gcc/config/arm/cortex-a9.md
-@@ -79,10 +79,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cort
- ;; which can go down E2 without any problem.
- (define_insn_reservation "cortex_a9_dp" 2
- (and (eq_attr "tune" "cortexa9")
-- (ior (eq_attr "type" "alu")
-- (ior (and (eq_attr "type" "alu_shift_reg, alu_shift")
-- (eq_attr "insn" "mov"))
-- (eq_attr "neon_type" "none"))))
-+ (ior (and (eq_attr "type" "alu")
-+ (eq_attr "neon_type" "none"))
-+ (and (and (eq_attr "type" "alu_shift_reg, alu_shift")
-+ (eq_attr "insn" "mov"))
-+ (eq_attr "neon_type" "none"))))
- "cortex_a9_p0_default|cortex_a9_p1_default")
-
- ;; An instruction using the shifter will go down E1.
-@@ -263,3 +264,6 @@ cortex_a9_store3_4, cortex_a9_store1_2,
- (and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fdivd"))
- "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
-+
-+;; Include Neon pipeline description
-+(include "cortex-a9-neon.md")
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch
deleted file mode 100644
index cf22aaf16f..0000000000
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch
+++ /dev/null
@@ -1,811 +0,0 @@
-2010-12-13 Tom de Vries <tom@codesourcery.com>
-
- gcc/
- * tree-if-switch-conversion.c: New pass.
- * tree-pass.h (pass_if_to_switch): Declare.
- * common.opt (ftree-if-to-switch-conversion): New switch.
- * opts.c (decode_options): Set flag_tree_if_to_switch_conversion at -O2
- and higher.
- * passes.c (init_optimization_passes): Use new pass.
- * params.def (PARAM_IF_TO_SWITCH_THRESHOLD): New param.
- * doc/invoke.texi (-ftree-if-to-switch-conversion)
- (if-to-switch-threshold): New item.
- * doc/invoke.texi (Optimization Options, option -O2): Add
- -ftree-if-to-switch-conversion.
- * Makefile.in (OBJS-common): Add tree-if-switch-conversion.o.
- * Makefile.in (tree-if-switch-conversion.o): New rule.
-
-=== modified file 'gcc/Makefile.in'
-Index: gcc-4_5-branch/gcc/Makefile.in
-===================================================================
---- gcc-4_5-branch.orig/gcc/Makefile.in
-+++ gcc-4_5-branch/gcc/Makefile.in
-@@ -1354,6 +1354,7 @@ OBJS-common = \
- tree-profile.o \
- tree-scalar-evolution.o \
- tree-sra.o \
-+ tree-if-switch-conversion.o \
- tree-switch-conversion.o \
- tree-ssa-address.o \
- tree-ssa-alias.o \
-@@ -3013,6 +3014,11 @@ tree-sra.o : tree-sra.c $(CONFIG_H) $(SY
- $(TM_H) $(TREE_H) $(GIMPLE_H) $(CGRAPH_H) $(TREE_FLOW_H) $(IPA_PROP_H) \
- $(DIAGNOSTIC_H) statistics.h $(TREE_DUMP_H) $(TIMEVAR_H) $(PARAMS_H) \
- $(TARGET_H) $(FLAGS_H) $(EXPR_H) $(TREE_INLINE_H)
-+tree-if-switch-conversion.o : tree-if-switch-conversion.c $(CONFIG_H) \
-+ $(SYSTEM_H) $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) \
-+ $(TREE_INLINE_H) $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) \
-+ $(GIMPLE_H) $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) output.h \
-+ $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H)
- tree-switch-conversion.o : tree-switch-conversion.c $(CONFIG_H) $(SYSTEM_H) \
- $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) $(TREE_INLINE_H) \
- $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) $(GIMPLE_H) \
-Index: gcc-4_5-branch/gcc/common.opt
-===================================================================
---- gcc-4_5-branch.orig/gcc/common.opt
-+++ gcc-4_5-branch/gcc/common.opt
-@@ -1285,6 +1285,10 @@ ftree-switch-conversion
- Common Report Var(flag_tree_switch_conversion) Optimization
- Perform conversions of switch initializations.
-
-+ftree-if-to-switch-conversion
-+Common Report Var(flag_tree_if_to_switch_conversion) Optimization
-+Perform conversions of chains of ifs into switches.
-+
- ftree-dce
- Common Report Var(flag_tree_dce) Optimization
- Enable SSA dead code elimination optimization on trees
-Index: gcc-4_5-branch/gcc/doc/invoke.texi
-===================================================================
---- gcc-4_5-branch.orig/gcc/doc/invoke.texi
-+++ gcc-4_5-branch/gcc/doc/invoke.texi
-@@ -382,7 +382,8 @@ Objective-C and Objective-C++ Dialects}.
- -fstrict-aliasing -fstrict-overflow -fthread-jumps -ftracer @gol
- -ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol
- -ftree-copyrename -ftree-dce @gol
---ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre -ftree-loop-im @gol
-+-ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre @gol
-+-ftree-if-to-switch-conversion -ftree-loop-im @gol
- -ftree-phiprop -ftree-loop-distribution @gol
- -ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol
- -ftree-parallelize-loops=@var{n} -ftree-pre -ftree-pta -ftree-reassoc @gol
-@@ -5798,6 +5799,7 @@ also turns on the following optimization
- -fsched-interblock -fsched-spec @gol
- -fschedule-insns -fschedule-insns2 @gol
- -fstrict-aliasing -fstrict-overflow @gol
-+-ftree-if-to-switch-conversion @gol
- -ftree-switch-conversion @gol
- -ftree-pre @gol
- -ftree-vrp}
-@@ -6634,6 +6636,10 @@ Perform conversion of simple initializat
- initializations from a scalar array. This flag is enabled by default
- at @option{-O2} and higher.
-
-+@item -ftree-if-to-switch-conversion
-+Perform conversion of chains of ifs into switches. This flag is enabled by
-+default at @option{-O2} and higher.
-+
- @item -ftree-dce
- @opindex ftree-dce
- Perform dead code elimination (DCE) on trees. This flag is enabled by
-@@ -8577,6 +8583,12 @@ loop in the loop nest by a given number
- length can be changed using the @option{loop-block-tile-size}
- parameter. The default value is 51 iterations.
-
-+@item if-to-switch-threshold
-+If-chain to switch conversion, enabled by
-+@option{-ftree-if-to-switch-conversion} convert chains of ifs of sufficient
-+length into switches. The parameter @option{if-to-switch-threshold} can be
-+used to set the minimal required length. The default value is 3.
-+
- @end table
- @end table
-
-Index: gcc-4_5-branch/gcc/opts.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/opts.c
-+++ gcc-4_5-branch/gcc/opts.c
-@@ -905,6 +905,7 @@ decode_options (unsigned int argc, const
- flag_tree_builtin_call_dce = opt2;
- flag_tree_pre = opt2;
- flag_tree_switch_conversion = opt2;
-+ flag_tree_if_to_switch_conversion = opt2;
- flag_ipa_cp = opt2;
- flag_ipa_sra = opt2;
- flag_ee = opt2;
-Index: gcc-4_5-branch/gcc/params.def
-===================================================================
---- gcc-4_5-branch.orig/gcc/params.def
-+++ gcc-4_5-branch/gcc/params.def
-@@ -826,6 +826,11 @@ DEFPARAM (PARAM_IPA_SRA_PTR_GROWTH_FACTO
- "a pointer to an aggregate with",
- 2, 0, 0)
-
-+DEFPARAM (PARAM_IF_TO_SWITCH_THRESHOLD,
-+ "if-to-switch-threshold",
-+ "Threshold for converting an if-chain into a switch",
-+ 3, 0, 0)
-+
- /*
- Local variables:
- mode:c
-Index: gcc-4_5-branch/gcc/passes.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/passes.c
-+++ gcc-4_5-branch/gcc/passes.c
-@@ -788,6 +788,7 @@ init_optimization_passes (void)
- NEXT_PASS (pass_cd_dce);
- NEXT_PASS (pass_early_ipa_sra);
- NEXT_PASS (pass_tail_recursion);
-+ NEXT_PASS (pass_if_to_switch);
- NEXT_PASS (pass_convert_switch);
- NEXT_PASS (pass_cleanup_eh);
- NEXT_PASS (pass_profile);
-@@ -844,6 +845,7 @@ init_optimization_passes (void)
- NEXT_PASS (pass_phiprop);
- NEXT_PASS (pass_fre);
- NEXT_PASS (pass_copy_prop);
-+ NEXT_PASS (pass_if_to_switch);
- NEXT_PASS (pass_merge_phi);
- NEXT_PASS (pass_vrp);
- NEXT_PASS (pass_dce);
-Index: gcc-4_5-branch/gcc/tree-if-switch-conversion.c
-===================================================================
---- /dev/null
-+++ gcc-4_5-branch/gcc/tree-if-switch-conversion.c
-@@ -0,0 +1,643 @@
-+/* Convert a chain of ifs into a switch.
-+ Copyright (C) 2010 Free Software Foundation, Inc.
-+ Contributed by Tom de Vries <tom@codesourcery.com>
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify it
-+under the terms of the GNU General Public License as published by the
-+Free Software Foundation; either version 3, or (at your option) any
-+later version.
-+
-+GCC is distributed in the hope that it will be useful, but WITHOUT
-+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3. If not, write to the Free
-+Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
-+02110-1301, USA. */
-+
-+
-+/* The following pass converts a chain of ifs into a switch.
-+
-+ The if-chain has the following properties:
-+ - all bbs end in a GIMPLE_COND.
-+ - all but the first bb are empty, apart from the GIMPLE_COND.
-+ - the GIMPLE_CONDs compare the same variable against integer constants.
-+ - the true gotos all target the same bb.
-+ - the false gotos target the next in the if-chain.
-+
-+ F.i., consider the following if-chain:
-+ ...
-+ <bb 4>:
-+ ...
-+ if (D.1993_3 == 32)
-+ goto <bb 3>;
-+ else
-+ goto <bb 5>;
-+
-+ <bb 5>:
-+ if (D.1993_3 == 13)
-+ goto <bb 3>;
-+ else
-+ goto <bb 6>;
-+
-+ <bb 6>:
-+ if (D.1993_3 == 10)
-+ goto <bb 3>;
-+ else
-+ goto <bb 7>;
-+
-+ <bb 7>:
-+ if (D.1993_3 == 9)
-+ goto <bb 3>;
-+ else
-+ goto <bb 8>;
-+ ...
-+
-+ The pass will report this if-chain like this:
-+ ...
-+ var: D.1993_3
-+ first: <bb 4>
-+ true: <bb 3>
-+ last: <bb 7>
-+ constants: 9 10 13 32
-+ ...
-+
-+ and then convert the if-chain into a switch:
-+ ...
-+ <bb 4>:
-+ ...
-+ switch (D.1993_3) <default: <L8>,
-+ case 9: <L7>,
-+ case 10: <L7>,
-+ case 13: <L7>,
-+ case 32: <L7>>
-+ ...
-+
-+ The conversion does not happen if the chain is too short. The threshold is
-+ determined by the parameter PARAM_IF_TO_SWITCH_THRESHOLD.
-+
-+ The pass will try to construct a chain for each bb, unless the bb it is
-+ already contained in a chain. This ensures that all chains will be found,
-+ and that no chain will be constructed twice. The pass constructs and
-+ converts the chains one-by-one, rather than first calculating all the chains
-+ and then doing the conversions.
-+
-+ The pass could detect range-checks in analyze_bb as well, and handle them.
-+ Simple ones, like 'c <= 5', and more complex ones, like
-+ '(unsigned char) c + 247 <= 1', which is generated by the C front-end from
-+ code like '(c == 9 || c == 10)' or '(9 <= c && c <= 10)'. */
-+
-+#include "config.h"
-+#include "system.h"
-+#include "coretypes.h"
-+#include "tm.h"
-+
-+#include "params.h"
-+#include "flags.h"
-+#include "tree.h"
-+#include "basic-block.h"
-+#include "tree-flow.h"
-+#include "tree-flow-inline.h"
-+#include "tree-ssa-operands.h"
-+#include "diagnostic.h"
-+#include "tree-pass.h"
-+#include "tree-dump.h"
-+#include "timevar.h"
-+
-+/* Information we've collected about a single bb. */
-+
-+struct ifsc_info
-+{
-+ /* The variable of the bb's ending GIMPLE_COND, NULL_TREE if not present. */
-+ tree var;
-+ /* The cond_code of the bb's ending GIMPLE_COND. */
-+ enum tree_code cond_code;
-+ /* The constant of the bb's ending GIMPLE_COND. */
-+ tree constant;
-+ /* Successor edge of the bb if its GIMPLE_COND is true. */
-+ edge true_edge;
-+ /* Successor edge of the bb if its GIMPLE_COND is false. */
-+ edge false_edge;
-+ /* Set if the bb has valid ifsc_info. */
-+ bool valid;
-+ /* Set if the bb is part of a chain. */
-+ bool chained;
-+};
-+
-+/* Macros to access the fields of struct ifsc_info. */
-+
-+#define BB_IFSC_VAR(bb) (((struct ifsc_info *)bb->aux)->var)
-+#define BB_IFSC_COND_CODE(bb) (((struct ifsc_info *)bb->aux)->cond_code)
-+#define BB_IFSC_CONSTANT(bb) (((struct ifsc_info *)bb->aux)->constant)
-+#define BB_IFSC_TRUE_EDGE(bb) (((struct ifsc_info *)bb->aux)->true_edge)
-+#define BB_IFSC_FALSE_EDGE(bb) (((struct ifsc_info *)bb->aux)->false_edge)
-+#define BB_IFSC_VALID(bb) (((struct ifsc_info *)bb->aux)->valid)
-+#define BB_IFSC_CHAINED(bb) (((struct ifsc_info *)bb->aux)->chained)
-+
-+/* Data-type describing an if-chain. */
-+
-+struct if_chain
-+{
-+ /* First bb in the chain. */
-+ basic_block first;
-+ /* Last bb in the chain. */
-+ basic_block last;
-+ /* Variable that GIMPLE_CONDs of all bbs in chain compare against. */
-+ tree var;
-+ /* bb that all GIMPLE_CONDs jump to if comparison succeeds. */
-+ basic_block true_dest;
-+ /* Constants that GIMPLE_CONDs of all bbs in chain compare var against. */
-+ VEC (tree, heap) *constants;
-+ /* Same as previous, but sorted and with duplicates removed. */
-+ VEC (tree, heap) *unique_constants;
-+};
-+
-+/* Utility macro. */
-+
-+#define SWAP(T, X, Y) do { T tmp = (X); (X) = (Y); (Y) = tmp; } while (0)
-+
-+/* Helper function for sort_constants. */
-+
-+static int
-+compare_constants (const void *p1, const void *p2)
-+{
-+ const_tree const c1 = *(const_tree const*)p1;
-+ const_tree const c2 = *(const_tree const*)p2;
-+
-+ return tree_int_cst_compare (c1, c2);
-+}
-+
-+/* Sort constants in constants and copy to unique_constants, while skipping
-+ duplicates. */
-+
-+static void
-+sort_constants (VEC (tree,heap) *constants, VEC (tree,heap) **unique_constants)
-+{
-+ size_t len = VEC_length (tree, constants);
-+ unsigned int ix;
-+ tree prev = NULL_TREE, constant;
-+
-+ /* Sort constants. */
-+ qsort (VEC_address (tree, constants), len, sizeof (tree),
-+ compare_constants);
-+
-+ /* Copy to unique_constants, while skipping duplicates. */
-+ for (ix = 0; VEC_iterate (tree, constants, ix, constant); ix++)
-+ {
-+ if (prev != NULL_TREE && tree_int_cst_compare (prev, constant) == 0)
-+ continue;
-+ prev = constant;
-+
-+ VEC_safe_push (tree, heap, *unique_constants, constant);
-+ }
-+}
-+
-+/* Get true_edge and false_edge of a bb ending in a conditional jump. */
-+
-+static void
-+get_edges (basic_block bb, edge *true_edge, edge *false_edge)
-+{
-+ edge e0, e1;
-+ int e0_true;
-+ int n = EDGE_COUNT (bb->succs);
-+ gcc_assert (n == 2);
-+
-+ e0 = EDGE_SUCC (bb, 0);
-+ e1 = EDGE_SUCC (bb, 1);
-+
-+ e0_true = e0->flags & EDGE_TRUE_VALUE;
-+
-+ *true_edge = e0_true ? e0 : e1;
-+ *false_edge = e0_true ? e1 : e0;
-+
-+ gcc_assert ((*true_edge)->flags & EDGE_TRUE_VALUE);
-+ gcc_assert ((*false_edge)->flags & EDGE_FALSE_VALUE);
-+
-+ gcc_assert (((*true_edge)->flags & EDGE_FALLTHRU) == 0);
-+ gcc_assert (((*false_edge)->flags & EDGE_FALLTHRU) == 0);
-+}
-+
-+/* Analyze bb and store results in ifsc_info struct. */
-+
-+static void
-+analyze_bb (basic_block bb)
-+{
-+ gimple stmt = last_stmt (bb);
-+ tree lhs, rhs, var, constant;
-+ edge true_edge, false_edge;
-+ enum tree_code cond_code;
-+
-+ /* Don't redo analysis. */
-+ if (BB_IFSC_VALID (bb))
-+ return;
-+ BB_IFSC_VALID (bb) = true;
-+
-+
-+ /* bb needs to end in GIMPLE_COND. */
-+ if (!stmt || gimple_code (stmt) != GIMPLE_COND)
-+ return;
-+
-+ /* bb needs to end in EQ_EXPR or NE_EXPR. */
-+ cond_code = gimple_cond_code (stmt);
-+ if (cond_code != EQ_EXPR && cond_code != NE_EXPR)
-+ return;
-+
-+ lhs = gimple_cond_lhs (stmt);
-+ rhs = gimple_cond_rhs (stmt);
-+
-+ /* GIMPLE_COND needs to compare variable to constant. */
-+ if ((TREE_CONSTANT (lhs) == 0)
-+ == (TREE_CONSTANT (rhs) == 0))
-+ return;
-+
-+ var = TREE_CONSTANT (lhs) ? rhs : lhs;
-+ constant = TREE_CONSTANT (lhs)? lhs : rhs;
-+
-+ /* Switches cannot handle non-integral types. */
-+ if (!INTEGRAL_TYPE_P(TREE_TYPE (var)))
-+ return;
-+
-+ get_edges (bb, &true_edge, &false_edge);
-+
-+ if (cond_code == NE_EXPR)
-+ SWAP (edge, true_edge, false_edge);
-+
-+ /* TODO: loosen this constraint. In principle it's ok if true_edge->dest has
-+ phis, as long as for each phi all the edges coming from the chain have the
-+ same value. */
-+ if (!gimple_seq_empty_p (phi_nodes (true_edge->dest)))
-+ return;
-+
-+ /* Store analysis in ifsc_info struct. */
-+ BB_IFSC_VAR (bb) = var;
-+ BB_IFSC_COND_CODE (bb) = cond_code;
-+ BB_IFSC_CONSTANT (bb) = constant;
-+ BB_IFSC_TRUE_EDGE (bb) = true_edge;
-+ BB_IFSC_FALSE_EDGE (bb) = false_edge;
-+}
-+
-+/* Grow if-chain forward. */
-+
-+static void
-+grow_if_chain_forward (struct if_chain *chain)
-+{
-+ basic_block next_bb;
-+
-+ while (1)
-+ {
-+ next_bb = BB_IFSC_FALSE_EDGE (chain->last)->dest;
-+
-+ /* next_bb is already part of another chain. */
-+ if (BB_IFSC_CHAINED (next_bb))
-+ break;
-+
-+ /* next_bb needs to be dominated by the last bb. */
-+ if (!single_pred_p (next_bb))
-+ break;
-+
-+ analyze_bb (next_bb);
-+
-+ /* Does next_bb fit in chain? */
-+ if (BB_IFSC_VAR (next_bb) != chain->var
-+ || BB_IFSC_TRUE_EDGE (next_bb)->dest != chain->true_dest)
-+ break;
-+
-+ /* We can only add empty bbs at the end of the chain. */
-+ if (first_stmt (next_bb) != last_stmt (next_bb))
-+ break;
-+
-+ /* Add next_bb at end of chain. */
-+ VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (next_bb));
-+ BB_IFSC_CHAINED (next_bb) = true;
-+ chain->last = next_bb;
-+ }
-+}
-+
-+/* Grow if-chain backward. */
-+
-+static void
-+grow_if_chain_backward (struct if_chain *chain)
-+{
-+ basic_block prev_bb;
-+
-+ while (1)
-+ {
-+ /* First bb is not empty, cannot grow backwards. */
-+ if (first_stmt (chain->first) != last_stmt (chain->first))
-+ break;
-+
-+ /* First bb has no single predecessor, cannot grow backwards. */
-+ if (!single_pred_p (chain->first))
-+ break;
-+
-+ prev_bb = single_pred (chain->first);
-+
-+ /* prev_bb is already part of another chain. */
-+ if (BB_IFSC_CHAINED (prev_bb))
-+ break;
-+
-+ analyze_bb (prev_bb);
-+
-+ /* Does prev_bb fit in chain? */
-+ if (BB_IFSC_VAR (prev_bb) != chain->var
-+ || BB_IFSC_TRUE_EDGE (prev_bb)->dest != chain->true_dest)
-+ break;
-+
-+ /* Add prev_bb at beginning of chain. */
-+ VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (prev_bb));
-+ BB_IFSC_CHAINED (prev_bb) = true;
-+ chain->first = prev_bb;
-+ }
-+}
-+
-+/* Grow if-chain containing bb. */
-+
-+static void
-+grow_if_chain (basic_block bb, struct if_chain *chain)
-+{
-+ /* Initialize chain to empty. */
-+ VEC_truncate (tree, chain->constants, 0);
-+ VEC_truncate (tree, chain->unique_constants, 0);
-+
-+ /* bb is already part of another chain. */
-+ if (BB_IFSC_CHAINED (bb))
-+ return;
-+
-+ analyze_bb (bb);
-+
-+ /* bb is not fit to be part of a chain. */
-+ if (BB_IFSC_VAR (bb) == NULL_TREE)
-+ return;
-+
-+ /* Set bb as initial part of the chain. */
-+ VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (bb));
-+ chain->first = chain->last = bb;
-+ chain->var = BB_IFSC_VAR (bb);
-+ chain->true_dest = BB_IFSC_TRUE_EDGE (bb)->dest;
-+
-+ /* bb is part of a chain now. */
-+ BB_IFSC_CHAINED (bb) = true;
-+
-+ /* Grow chain to its maximum size. */
-+ grow_if_chain_forward (chain);
-+ grow_if_chain_backward (chain);
-+
-+ /* Sort constants and skip duplicates. */
-+ sort_constants (chain->constants, &chain->unique_constants);
-+}
-+
-+static void
-+dump_tree_vector (VEC (tree, heap) *vec)
-+{
-+ unsigned int ix;
-+ tree constant;
-+
-+ for (ix = 0; VEC_iterate (tree, vec, ix, constant); ix++)
-+ {
-+ if (ix != 0)
-+ fprintf (dump_file, " ");
-+ print_generic_expr (dump_file, constant, 0);
-+ }
-+ fprintf (dump_file, "\n");
-+}
-+
-+/* Dump if-chain to dump_file. */
-+
-+static void
-+dump_if_chain (struct if_chain *chain)
-+{
-+ if (!dump_file)
-+ return;
-+
-+ fprintf (dump_file, "var: ");
-+ print_generic_expr (dump_file, chain->var, 0);
-+ fprintf (dump_file, "\n");
-+ fprintf (dump_file, "first: <bb %d>\n", chain->first->index);
-+ fprintf (dump_file, "true: <bb %d>\n", chain->true_dest->index);
-+ fprintf (dump_file, "last: <bb %d>\n",chain->last->index);
-+
-+ fprintf (dump_file, "constants: ");
-+ dump_tree_vector (chain->constants);
-+
-+ if (VEC_length (tree, chain->unique_constants)
-+ != VEC_length (tree, chain->constants))
-+ {
-+ fprintf (dump_file, "unique_constants: ");
-+ dump_tree_vector (chain->unique_constants);
-+ }
-+}
-+
-+/* Remove redundant bbs and edges. */
-+
-+static void
-+remove_redundant_bbs_and_edges (struct if_chain *chain, int *false_prob)
-+{
-+ basic_block bb, next;
-+ edge true_edge, false_edge;
-+
-+ for (bb = chain->first;; bb = next)
-+ {
-+ true_edge = BB_IFSC_TRUE_EDGE (bb);
-+ false_edge = BB_IFSC_FALSE_EDGE (bb);
-+
-+ /* Determine next, before we delete false_edge. */
-+ next = false_edge->dest;
-+
-+ /* Accumulate probability. */
-+ *false_prob = (*false_prob * false_edge->probability) / REG_BR_PROB_BASE;
-+
-+ /* Don't remove the new true_edge. */
-+ if (bb != chain->first)
-+ remove_edge (true_edge);
-+
-+ /* Don't remove the new false_edge. */
-+ if (bb != chain->last)
-+ remove_edge (false_edge);
-+
-+ /* Don't remove the first bb. */
-+ if (bb != chain->first)
-+ delete_basic_block (bb);
-+
-+ /* Stop after last. */
-+ if (bb == chain->last)
-+ break;
-+ }
-+}
-+
-+/* Update control flow graph. */
-+
-+static void
-+update_cfg (struct if_chain *chain)
-+{
-+ edge true_edge, false_edge;
-+ int false_prob;
-+ int flags_mask = ~(EDGE_FALLTHRU|EDGE_TRUE_VALUE|EDGE_FALSE_VALUE);
-+
-+ /* We keep these 2 edges, and remove the rest. We need this specific
-+ false_edge, because a phi in chain->last->dest might reference (the index
-+ of) this edge. For true_edge, we could pick any of them. */
-+ true_edge = BB_IFSC_TRUE_EDGE (chain->first);
-+ false_edge = BB_IFSC_FALSE_EDGE (chain->last);
-+
-+ /* Update true edge. */
-+ true_edge->flags &= flags_mask;
-+
-+ /* Update false edge. */
-+ redirect_edge_pred (false_edge, chain->first);
-+ false_edge->flags &= flags_mask;
-+
-+ false_prob = REG_BR_PROB_BASE;
-+ remove_redundant_bbs_and_edges (chain, &false_prob);
-+
-+ /* Repair probabilities. */
-+ true_edge->probability = REG_BR_PROB_BASE - false_prob;
-+ false_edge->probability = false_prob;
-+
-+ /* Force recalculation of dominance info. */
-+ free_dominance_info (CDI_DOMINATORS);
-+ free_dominance_info (CDI_POST_DOMINATORS);
-+}
-+
-+/* Create switch statement. Borrows from gimplify_switch_expr. */
-+
-+static void
-+convert_if_chain_to_switch (struct if_chain *chain)
-+{
-+ tree label_decl_true, label_decl_false;
-+ gimple label_true, label_false, gimple_switch;
-+ gimple_stmt_iterator gsi;
-+ tree default_case, other_case, constant;
-+ unsigned int ix;
-+ VEC (tree, heap) *labels;
-+
-+ labels = VEC_alloc (tree, heap, 8);
-+
-+ /* Create and insert true jump label. */
-+ label_decl_true = create_artificial_label (UNKNOWN_LOCATION);
-+ label_true = gimple_build_label (label_decl_true);
-+ gsi = gsi_start_bb (chain->true_dest);
-+ gsi_insert_before (&gsi, label_true, GSI_SAME_STMT);
-+
-+ /* Create and insert false jump label. */
-+ label_decl_false = create_artificial_label (UNKNOWN_LOCATION);
-+ label_false = gimple_build_label (label_decl_false);
-+ gsi = gsi_start_bb (BB_IFSC_FALSE_EDGE (chain->last)->dest);
-+ gsi_insert_before (&gsi, label_false, GSI_SAME_STMT);
-+
-+ /* Create default case label. */
-+ default_case = build3 (CASE_LABEL_EXPR, void_type_node,
-+ NULL_TREE, NULL_TREE,
-+ label_decl_false);
-+
-+ /* Create case labels. */
-+ for (ix = 0; VEC_iterate (tree, chain->unique_constants, ix, constant); ix++)
-+ {
-+ /* TODO: use ranges, as in gimplify_switch_expr. */
-+ other_case = build3 (CASE_LABEL_EXPR, void_type_node,
-+ constant, NULL_TREE,
-+ label_decl_true);
-+ VEC_safe_push (tree, heap, labels, other_case);
-+ }
-+
-+ /* Create and insert switch. */
-+ gimple_switch = gimple_build_switch_vec (chain->var, default_case, labels);
-+ gsi = gsi_for_stmt (last_stmt (chain->first));
-+ gsi_insert_before (&gsi, gimple_switch, GSI_SAME_STMT);
-+
-+ /* Remove now obsolete if. */
-+ gsi_remove (&gsi, true);
-+
-+ VEC_free (tree, heap, labels);
-+}
-+
-+/* Allocation and initialization. */
-+
-+static void
-+init_pass (struct if_chain *chain)
-+{
-+ alloc_aux_for_blocks (sizeof (struct ifsc_info));
-+
-+ chain->constants = VEC_alloc (tree, heap, 8);
-+ chain->unique_constants = VEC_alloc (tree, heap, 8);
-+}
-+
-+/* Deallocation. */
-+
-+static void
-+finish_pass (struct if_chain *chain)
-+{
-+ free_aux_for_blocks ();
-+
-+ VEC_free (tree, heap, chain->constants);
-+ VEC_free (tree, heap, chain->unique_constants);
-+}
-+
-+/* Find if-chains and convert them to switches. */
-+
-+static unsigned int
-+do_if_to_switch (void)
-+{
-+ basic_block bb;
-+ struct if_chain chain;
-+ unsigned int convert_threshold = PARAM_VALUE (PARAM_IF_TO_SWITCH_THRESHOLD);
-+
-+ init_pass (&chain);
-+
-+ for (bb = cfun->cfg->x_entry_block_ptr->next_bb;
-+ bb != cfun->cfg->x_exit_block_ptr;)
-+ {
-+ grow_if_chain (bb, &chain);
-+
-+ do
-+ bb = bb->next_bb;
-+ while (BB_IFSC_CHAINED (bb));
-+
-+ /* Determine if the chain is long enough. */
-+ if (VEC_length (tree, chain.unique_constants) < convert_threshold)
-+ continue;
-+
-+ dump_if_chain (&chain);
-+
-+ convert_if_chain_to_switch (&chain);
-+
-+ update_cfg (&chain);
-+ }
-+
-+ finish_pass (&chain);
-+
-+ return 0;
-+}
-+
-+/* The pass gate. */
-+
-+static bool
-+if_to_switch_gate (void)
-+{
-+ return flag_tree_if_to_switch_conversion;
-+}
-+
-+/* The pass definition. */
-+
-+struct gimple_opt_pass pass_if_to_switch =
-+{
-+ {
-+ GIMPLE_PASS,
-+ "iftoswitch", /* name */
-+ if_to_switch_gate, /* gate */
-+ do_if_to_switch, /* execute */
-+ NULL, /* sub */
-+ NULL, /* next */
-+ 0, /* static_pass_number */
-+ TV_TREE_SWITCH_CONVERSION, /* tv_id */
-+ PROP_cfg | PROP_ssa, /* properties_required */
-+ 0, /* properties_provided */
-+ 0, /* properties_destroyed */
-+ 0, /* todo_flags_start */
-+ TODO_update_ssa | TODO_dump_func
-+ | TODO_ggc_collect | TODO_verify_ssa /* todo_flags_finish */
-+ }
-+};
-Index: gcc-4_5-branch/gcc/tree-pass.h
-===================================================================
---- gcc-4_5-branch.orig/gcc/tree-pass.h
-+++ gcc-4_5-branch/gcc/tree-pass.h
-@@ -560,6 +560,7 @@ extern struct gimple_opt_pass pass_inlin
- extern struct gimple_opt_pass pass_all_early_optimizations;
- extern struct gimple_opt_pass pass_update_address_taken;
- extern struct gimple_opt_pass pass_convert_switch;
-+extern struct gimple_opt_pass pass_if_to_switch;
-
- /* The root of the compilation pass tree, once constructed. */
- extern struct opt_pass *all_passes, *all_small_ipa_passes, *all_lowering_passes,
diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch
deleted file mode 100644
index 3ac7f7f6fd..0000000000
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch
+++ /dev/null
@@ -1,409 +0,0 @@
-2010-02-04 Tom de Vries <tom@codesourcery.com>
-
- gcc/
- stmt.c (set_jump_prob): Fix assert condition.
-
-2010-01-27 Tom de Vries <tom@codesourcery.com>
-
- gcc/
- stmt.c (rtx_seq_cost): Use insn_rtx_cost instead of rtx_cost.
-
-2010-01-26 Tom de Vries <tom@codesourcery.com>
-
- gcc/
- * stmt.c (struct case_bit_test): Add rev_hi and rev_lo field.
- * stmt.c (emit_case_bit_test_jump): New function.
- * stmt.c (rtx_seq_cost): New function.
- * stmt.c (choose_case_bit_test_expand_method): New function.
- * stmt.c (set_bit): New function.
- * stmt.c (emit_case_bit_test): Adjust comment.
- * stmt.c (emit_case_bit_test): Set and update rev_hi and rev_lo fields.
- * stmt.c (emit_case_bit_test): Use set_bit.
- * stmt.c (emit_case_bit_test): Use choose_case_bit_test_expand_method.
- * stmt.c (emit_case_bit_test): Use emit_case_bit_test_jump.
- * testsuite/gcc.dg/switch-bittest.c: New test.
-
-2010-01-25 Tom de Vries <tom@codesourcery.com>
-
- gcc/
- * stmt.c (emit_case_bit_tests): Change prototype.
- * stmt.c (struct case_bit_test): Add prob field.
- * stmt.c (get_label_prob): New function.
- * stmt.c (set_jump_prob): New function.
- * stmt.c (emit_case_bit_tests): Use get_label_prob.
- * stmt.c (emit_case_bit_tests): Set prob field.
- * stmt.c (emit_case_bit_tests): Use set_jump_prob.
- * stmt.c (expand_case): Add new args to emit_case_bit_tests invocation.
- * testsuite/gcc.dg/switch-prob.c: Add test.
-
-=== modified file 'gcc/stmt.c'
-Index: gcc-4_5-branch/gcc/stmt.c
-===================================================================
---- gcc-4_5-branch.orig/gcc/stmt.c
-+++ gcc-4_5-branch/gcc/stmt.c
-@@ -117,7 +117,8 @@ static void expand_value_return (rtx);
- static int estimate_case_costs (case_node_ptr);
- static bool lshift_cheap_p (void);
- static int case_bit_test_cmp (const void *, const void *);
--static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, rtx);
-+static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, tree,
-+ rtx, basic_block);
- static void balance_case_nodes (case_node_ptr *, case_node_ptr);
- static int node_has_low_bound (case_node_ptr, tree);
- static int node_has_high_bound (case_node_ptr, tree);
-@@ -2107,8 +2108,11 @@ struct case_bit_test
- {
- HOST_WIDE_INT hi;
- HOST_WIDE_INT lo;
-+ HOST_WIDE_INT rev_hi;
-+ HOST_WIDE_INT rev_lo;
- rtx label;
- int bits;
-+ int prob;
- };
-
- /* Determine whether "1 << x" is relatively cheap in word_mode. */
-@@ -2148,10 +2152,193 @@ case_bit_test_cmp (const void *p1, const
- return CODE_LABEL_NUMBER (d2->label) - CODE_LABEL_NUMBER (d1->label);
- }
-
-+/* Emit a bit test and a conditional jump. */
-+
-+static void
-+emit_case_bit_test_jump (unsigned int count, rtx index, rtx label,
-+ unsigned int method, HOST_WIDE_INT hi,
-+ HOST_WIDE_INT lo, HOST_WIDE_INT rev_hi,
-+ HOST_WIDE_INT rev_lo)
-+{
-+ rtx expr;
-+
-+ if (method == 1)
-+ {
-+ /* (1 << index). */
-+ if (count == 0)
-+ index = expand_binop (word_mode, ashl_optab, const1_rtx,
-+ index, NULL_RTX, 1, OPTAB_WIDEN);
-+ /* CST. */
-+ expr = immed_double_const (lo, hi, word_mode);
-+ /* ((1 << index) & CST). */
-+ expr = expand_binop (word_mode, and_optab, index, expr,
-+ NULL_RTX, 1, OPTAB_WIDEN);
-+ /* if (((1 << index) & CST)). */
-+ emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX,
-+ word_mode, 1, label);
-+ }
-+ else if (method == 2)
-+ {
-+ /* (bit_reverse (CST)) */
-+ expr = immed_double_const (rev_lo, rev_hi, word_mode);
-+ /* ((bit_reverse (CST)) << index) */
-+ expr = expand_binop (word_mode, ashl_optab, expr,
-+ index, NULL_RTX, 1, OPTAB_WIDEN);
-+ /* if (((bit_reverse (CST)) << index) < 0). */
-+ emit_cmp_and_jump_insns (expr, const0_rtx, LT, NULL_RTX,
-+ word_mode, 0, label);
-+ }
-+ else
-+ gcc_unreachable ();
-+}
-+
-+/* Return the cost of rtx sequence SEQ. The sequence is supposed to contain one
-+ jump, which has no effect in the cost. */
-+
-+static unsigned int
-+rtx_seq_cost (rtx seq)
-+{
-+ rtx one;
-+ unsigned int nr_branches = 0;
-+ unsigned int sum = 0, cost;
-+
-+ for (one = seq; one != NULL_RTX; one = NEXT_INSN (one))
-+ if (JUMP_P (one))
-+ nr_branches++;
-+ else
-+ {
-+ cost = insn_rtx_cost (PATTERN (one), optimize_insn_for_speed_p ());
-+ if (dump_file)
-+ {
-+ print_rtl_single (dump_file, one);
-+ fprintf (dump_file, "cost: %u\n", cost);
-+ }
-+ sum += cost;
-+ }
-+
-+ gcc_assert (nr_branches == 1);
-+
-+ if (dump_file)
-+ fprintf (dump_file, "total cost: %u\n", sum);
-+ return sum;
-+}
-+
-+/* Generate the rtx sequences for 2 bit test expansion methods, measure the cost
-+ and choose the cheapest. */
-+
-+static unsigned int
-+choose_case_bit_test_expand_method (rtx label)
-+{
-+ rtx seq, index;
-+ unsigned int cost[2];
-+ static bool method_known = false;
-+ static unsigned int method;
-+
-+ /* If already known, return the method. */
-+ if (method_known)
-+ return method;
-+
-+ index = gen_rtx_REG (word_mode, 10000);
-+
-+ for (method = 1; method <= 2; ++method)
-+ {
-+ start_sequence ();
-+ emit_case_bit_test_jump (0, index, label, method, 0, 0x0f0f0f0f, 0,
-+ 0x0f0f0f0f);
-+ seq = get_insns ();
-+ end_sequence ();
-+ cost[method - 1] = rtx_seq_cost (seq);
-+ }
-+
-+ /* Determine method based on heuristic. */
-+ method = ((cost[1] < cost[0]) ? 1 : 0) + 1;
-+
-+ /* Save and return method. */
-+ method_known = true;
-+ return method;
-+}
-+
-+/* Get the edge probability of the edge from SRC to LABEL_DECL. */
-+
-+static int
-+get_label_prob (basic_block src, tree label_decl)
-+{
-+ basic_block dest;
-+ int prob = 0, nr_prob = 0;
-+ unsigned int i;
-+ edge e;
-+
-+ if (label_decl == NULL_TREE)
-+ return 0;
-+
-+ dest = VEC_index (basic_block, label_to_block_map,
-+ LABEL_DECL_UID (label_decl));
-+
-+ for (i = 0; i < EDGE_COUNT (src->succs); ++i)
-+ {
-+ e = EDGE_SUCC (src, i);
-+
-+ if (e->dest != dest)
-+ continue;
-+
-+ prob += e->probability;
-+ nr_prob++;
-+ }
-+
-+ gcc_assert (nr_prob == 1);
-+
-+ return prob;
-+}
-+
-+/* Add probability note with scaled PROB to JUMP and update INV_SCALE. This
-+ function is intended to be used with a series of conditional jumps to L[i]
-+ where the probabilities p[i] to get to L[i] are known, and the jump
-+ probabilities j[i] need to be computed.
-+
-+ The algorithm to calculate the probabilities is
-+
-+ scale = REG_BR_PROB_BASE;
-+ for (i = 0; i < n; ++i)
-+ {
-+ j[i] = p[i] * scale / REG_BR_PROB_BASE;
-+ f[i] = REG_BR_PROB_BASE - j[i];
-+ scale = scale / (f[i] / REG_BR_PROB_BASE);
-+ }
-+
-+ The implementation uses inv_scale (REG_BR_PROB_BASE / scale) instead of
-+ scale, because scale tends to grow bigger than REG_BR_PROB_BASE. */
-+
-+static void
-+set_jump_prob (rtx jump, int prob, int *inv_scale)
-+{
-+ /* j[i] = p[i] * scale / REG_BR_PROB_BASE. */
-+ int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale;
-+ /* f[i] = REG_BR_PROB_BASE - j[i]. */
-+ int fallthrough_prob = REG_BR_PROB_BASE - jump_prob;
-+
-+ gcc_assert (jump_prob <= REG_BR_PROB_BASE);
-+ add_reg_note (jump, REG_BR_PROB, GEN_INT (jump_prob));
-+
-+ /* scale = scale / (f[i] / REG_BR_PROB_BASE). */
-+ *inv_scale = *inv_scale * fallthrough_prob / REG_BR_PROB_BASE;
-+}
-+
-+/* Set bit in hwi hi/lo pair. */
-+
-+static void
-+set_bit (HOST_WIDE_INT *hi, HOST_WIDE_INT *lo, unsigned int j)
-+{
-+ if (j >= HOST_BITS_PER_WIDE_INT)
-+ *hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT);
-+ else
-+ *lo |= (HOST_WIDE_INT) 1 << j;
-+}
-+
- /* Expand a switch statement by a short sequence of bit-wise
- comparisons. "switch(x)" is effectively converted into
-- "if ((1 << (x-MINVAL)) & CST)" where CST and MINVAL are
-- integer constants.
-+ "if ((1 << (x-MINVAL)) & CST)" or
-+ "if (((bit_reverse (CST)) << (x-MINVAL)) < 0)", where CST
-+ and MINVAL are integer constants.
-
- INDEX_EXPR is the value being switched on, which is of
- type INDEX_TYPE. MINVAL is the lowest case value of in
-@@ -2165,14 +2352,17 @@ case_bit_test_cmp (const void *p1, const
-
- static void
- emit_case_bit_tests (tree index_type, tree index_expr, tree minval,
-- tree range, case_node_ptr nodes, rtx default_label)
-+ tree range, case_node_ptr nodes, tree default_label_decl,
-+ rtx default_label, basic_block bb)
- {
- struct case_bit_test test[MAX_CASE_BIT_TESTS];
- enum machine_mode mode;
- rtx expr, index, label;
- unsigned int i,j,lo,hi;
- struct case_node *n;
-- unsigned int count;
-+ unsigned int count, method;
-+ int inv_scale = REG_BR_PROB_BASE;
-+ int default_prob = get_label_prob (bb, default_label_decl);
-
- count = 0;
- for (n = nodes; n; n = n->right)
-@@ -2187,8 +2377,11 @@ emit_case_bit_tests (tree index_type, tr
- gcc_assert (count < MAX_CASE_BIT_TESTS);
- test[i].hi = 0;
- test[i].lo = 0;
-+ test[i].rev_hi = 0;
-+ test[i].rev_lo = 0;
- test[i].label = label;
- test[i].bits = 1;
-+ test[i].prob = get_label_prob (bb, n->code_label);
- count++;
- }
- else
-@@ -2199,10 +2392,11 @@ emit_case_bit_tests (tree index_type, tr
- hi = tree_low_cst (fold_build2 (MINUS_EXPR, index_type,
- n->high, minval), 1);
- for (j = lo; j <= hi; j++)
-- if (j >= HOST_BITS_PER_WIDE_INT)
-- test[i].hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT);
-- else
-- test[i].lo |= (HOST_WIDE_INT) 1 << j;
-+ {
-+ set_bit (&test[i].hi, &test[i].lo, j);
-+ set_bit (&test[i].rev_hi, &test[i].rev_lo,
-+ GET_MODE_BITSIZE (word_mode) - j - 1);
-+ }
- }
-
- qsort (test, count, sizeof(*test), case_bit_test_cmp);
-@@ -2216,20 +2410,20 @@ emit_case_bit_tests (tree index_type, tr
- mode = TYPE_MODE (index_type);
- expr = expand_normal (range);
- if (default_label)
-- emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1,
-- default_label);
-+ {
-+ emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1,
-+ default_label);
-+ set_jump_prob (get_last_insn (), default_prob / 2, &inv_scale);
-+ }
-
- index = convert_to_mode (word_mode, index, 0);
-- index = expand_binop (word_mode, ashl_optab, const1_rtx,
-- index, NULL_RTX, 1, OPTAB_WIDEN);
-
-+ method = choose_case_bit_test_expand_method (test[0].label);
- for (i = 0; i < count; i++)
- {
-- expr = immed_double_const (test[i].lo, test[i].hi, word_mode);
-- expr = expand_binop (word_mode, and_optab, index, expr,
-- NULL_RTX, 1, OPTAB_WIDEN);
-- emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX,
-- word_mode, 1, test[i].label);
-+ emit_case_bit_test_jump (i, index, test[i].label, method, test[i].hi,
-+ test[i].lo, test[i].rev_hi, test[i].rev_lo);
-+ set_jump_prob (get_last_insn (), test[i].prob, &inv_scale);
- }
-
- if (default_label)
-@@ -2400,7 +2594,8 @@ expand_case (gimple stmt)
- range = maxval;
- }
- emit_case_bit_tests (index_type, index_expr, minval, range,
-- case_list, default_label);
-+ case_list, default_label_decl, default_label,
-+ gimple_bb (stmt));
- }
-
- /* If range of values is much bigger than number of values,
-Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-bittest.c
-===================================================================
---- /dev/null
-+++ gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-bittest.c
-@@ -0,0 +1,25 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fdump-rtl-expand" } */
-+
-+const char *
-+f (const char *p)
-+{
-+ while (1)
-+ {
-+ switch (*p)
-+ {
-+ case 9:
-+ case 10:
-+ case 13:
-+ case 32:
-+ break;
-+ default:
-+ return p;
-+ }
-+ }
-+}
-+
-+/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */
-+/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */
-+/* { dg-final { scan-rtl-dump-times "lt " 1 "expand" { target mips*-*-* } } } */
-+/* { dg-final { cleanup-rtl-dump "expand" } } */
-Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-prob.c
-===================================================================
---- /dev/null
-+++ gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-prob.c
-@@ -0,0 +1,25 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fdump-rtl-expand" } */
-+
-+const char *
-+f (const char *p)
-+{
-+ while (1)
-+ {
-+ switch (*p)
-+ {
-+ case 9:
-+ case 10:
-+ case 13:
-+ case 32:
-+ break;
-+ default:
-+ return p;
-+ }
-+ }
-+}
-+
-+/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */
-+/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */
-+/* { dg-final { scan-rtl-dump-times "heuristics" 0 "expand" { target mips*-*-* } } } */
-+/* { dg-final { cleanup-rtl-dump "expand" } } */
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-24 02:24:06 +0000